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f8d25d74 SR |
1 | /* |
2 | * Copyright (C) Marvell International Ltd. and its affiliates | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0 | |
5 | */ | |
6 | ||
7 | #ifndef __AXP_TRAINING_STATIC_H | |
8 | #define __AXP_TRAINING_STATIC_H | |
9 | ||
10 | /* | |
11 | * STATIC_TRAINING - Set only if static parameters for training are set and | |
12 | * required | |
13 | */ | |
14 | ||
15 | MV_DRAM_TRAINING_INIT ddr3_db_rev2_667[MV_MAX_DDR3_STATIC_SIZE] = { | |
16 | /* Read Leveling */ | |
17 | /*PUP RdSampleDly (+CL) Phase RL ADLL value */ | |
18 | /*0 */ | |
19 | {0x000016A0, 0xC002011A}, | |
20 | /*1 */ | |
21 | {0x000016A0, 0xC0420100}, | |
22 | /*2 */ | |
23 | {0x000016A0, 0xC082020A}, | |
24 | /*3 */ | |
25 | {0x000016A0, 0xC0C20017}, | |
26 | /*4 */ | |
27 | {0x000016A0, 0xC1020113}, | |
28 | /*5 */ | |
29 | {0x000016A0, 0xC1420107}, | |
30 | /*6 */ | |
31 | {0x000016A0, 0xC182011F}, | |
32 | /*7 */ | |
33 | {0x000016A0, 0xC1C2001C}, | |
34 | /*8 */ | |
35 | {0x000016A0, 0xC202010D}, | |
36 | ||
37 | /* Write Leveling */ | |
38 | /*0 */ | |
39 | {0x000016A0, 0xC0004A06}, | |
40 | /*1 */ | |
41 | {0x000016A0, 0xC040690D}, | |
42 | /*2 */ | |
43 | {0x000016A0, 0xC0806A0D}, | |
44 | /*3 */ | |
45 | {0x000016A0, 0xC0C0A01B}, | |
46 | /*4 */ | |
47 | {0x000016A0, 0xC1003A01}, | |
48 | /*5 */ | |
49 | {0x000016A0, 0xC1408113}, | |
50 | /*6 */ | |
51 | {0x000016A0, 0xC1805609}, | |
52 | /*7 */ | |
53 | {0x000016A0, 0xC1C04504}, | |
54 | /*8 */ | |
55 | {0x000016A0, 0xC2009518}, | |
56 | ||
57 | /*center DQS on read cycle */ | |
58 | {0x000016A0, 0xC803000F}, | |
59 | ||
60 | {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ | |
61 | {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ | |
62 | ||
63 | /*init DRAM */ | |
64 | {0x00001480, 0x00000001}, | |
65 | {0x0, 0x0} | |
66 | }; | |
67 | ||
68 | MV_DRAM_TRAINING_INIT ddr3_db_rev2_800[MV_MAX_DDR3_STATIC_SIZE] = { | |
69 | /* Read Leveling */ | |
70 | /*PUP RdSampleDly (+CL) Phase RL ADLL value */ | |
71 | /*0 */ | |
72 | {0x000016A0, 0xC0020301}, | |
73 | /*1 */ | |
74 | {0x000016A0, 0xC0420202}, | |
75 | /*2 */ | |
76 | {0x000016A0, 0xC0820314}, | |
77 | /*3 */ | |
78 | {0x000016A0, 0xC0C20117}, | |
79 | /*4 */ | |
80 | {0x000016A0, 0xC1020219}, | |
81 | /*5 */ | |
82 | {0x000016A0, 0xC142020B}, | |
83 | /*6 */ | |
84 | {0x000016A0, 0xC182030A}, | |
85 | /*7 */ | |
86 | {0x000016A0, 0xC1C2011D}, | |
87 | /*8 */ | |
88 | {0x000016A0, 0xC2020212}, | |
89 | ||
90 | /* Write Leveling */ | |
91 | /*0 */ | |
92 | {0x000016A0, 0xC0007A12}, | |
93 | /*1 */ | |
94 | {0x000016A0, 0xC0408D16}, | |
95 | /*2 */ | |
96 | {0x000016A0, 0xC0809E1B}, | |
97 | /*3 */ | |
98 | {0x000016A0, 0xC0C0AC1F}, | |
99 | /*4 */ | |
100 | {0x000016A0, 0xC1005E0A}, | |
101 | /*5 */ | |
102 | {0x000016A0, 0xC140A91D}, | |
103 | /*6 */ | |
104 | {0x000016A0, 0xC1808E17}, | |
105 | /*7 */ | |
106 | {0x000016A0, 0xC1C05509}, | |
107 | /*8 */ | |
108 | {0x000016A0, 0xC2003A01}, | |
109 | ||
110 | /* PBS Leveling */ | |
111 | /*0 */ | |
112 | {0x000016A0, 0xC0007A12}, | |
113 | /*1 */ | |
114 | {0x000016A0, 0xC0408D16}, | |
115 | /*2 */ | |
116 | {0x000016A0, 0xC0809E1B}, | |
117 | /*3 */ | |
118 | {0x000016A0, 0xC0C0AC1F}, | |
119 | /*4 */ | |
120 | {0x000016A0, 0xC1005E0A}, | |
121 | /*5 */ | |
122 | {0x000016A0, 0xC140A91D}, | |
123 | /*6 */ | |
124 | {0x000016A0, 0xC1808E17}, | |
125 | /*7 */ | |
126 | {0x000016A0, 0xC1C05509}, | |
127 | /*8 */ | |
128 | {0x000016A0, 0xC2003A01}, | |
129 | ||
130 | /*center DQS on read cycle */ | |
131 | {0x000016A0, 0xC803000B}, | |
132 | ||
133 | {0x00001538, 0x0000000D}, /*Read Data Sample Delays Register */ | |
134 | {0x0000153C, 0x00000011}, /*Read Data Ready Delay Register */ | |
135 | ||
136 | /*init DRAM */ | |
137 | {0x00001480, 0x00000001}, | |
138 | {0x0, 0x0} | |
139 | }; | |
140 | ||
141 | MV_DRAM_TRAINING_INIT ddr3_db_400[MV_MAX_DDR3_STATIC_SIZE] = { | |
142 | /* Read Leveling */ | |
143 | /*PUP RdSampleDly (+CL) Phase RL ADLL value */ | |
144 | /*0 2 4 15 */ | |
145 | {0x000016A0, 0xC002010C}, | |
146 | /*1 2 4 2 */ | |
147 | {0x000016A0, 0xC042001C}, | |
148 | /*2 2 4 27 */ | |
149 | {0x000016A0, 0xC0820115}, | |
150 | /*3 2 4 0 */ | |
151 | {0x000016A0, 0xC0C20019}, | |
152 | /*4 2 4 13 */ | |
153 | {0x000016A0, 0xC1020108}, | |
154 | /*5 2 4 5 */ | |
155 | {0x000016A0, 0xC1420100}, | |
156 | /*6 2 4 19 */ | |
157 | {0x000016A0, 0xC1820111}, | |
158 | /*7 2 4 0 */ | |
159 | {0x000016A0, 0xC1C2001B}, | |
160 | /*8 2 4 10 */ | |
161 | /*{0x000016A0, 0xC2020117}, */ | |
162 | {0x000016A0, 0xC202010C}, | |
163 | ||
164 | /* Write Leveling */ | |
165 | /*0 */ | |
166 | {0x000016A0, 0xC0005508}, | |
167 | /*1 */ | |
168 | {0x000016A0, 0xC0409819}, | |
169 | /*2 */ | |
170 | {0x000016A0, 0xC080650C}, | |
171 | /*3 */ | |
172 | {0x000016A0, 0xC0C0700F}, | |
173 | /*4 */ | |
174 | {0x000016A0, 0xC1004103}, | |
175 | /*5 */ | |
176 | {0x000016A0, 0xC140A81D}, | |
177 | /*6 */ | |
178 | {0x000016A0, 0xC180650C}, | |
179 | /*7 */ | |
180 | {0x000016A0, 0xC1C08013}, | |
181 | /*8 */ | |
182 | {0x000016A0, 0xC2005508}, | |
183 | ||
184 | /*center DQS on read cycle */ | |
185 | {0x000016A0, 0xC803000F}, | |
186 | ||
187 | {0x00001538, 0x00000008}, /*Read Data Sample Delays Register */ | |
188 | {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */ | |
189 | ||
190 | /*init DRAM */ | |
191 | {0x00001480, 0x00000001}, | |
192 | {0x0, 0x0} | |
193 | }; | |
194 | ||
195 | MV_DRAM_TRAINING_INIT ddr3_db_533[MV_MAX_DDR3_STATIC_SIZE] = { | |
196 | /* Read Leveling */ | |
197 | /*PUP RdSampleDly (+CL) Phase RL ADLL value */ | |
198 | /*0 2 4 15 */ | |
199 | {0x000016A0, 0xC002040C}, | |
200 | /*1 2 4 2 */ | |
201 | {0x000016A0, 0xC0420117}, | |
202 | /*2 2 4 27 */ | |
203 | {0x000016A0, 0xC082041B}, | |
204 | /*3 2 4 0 */ | |
205 | {0x000016A0, 0xC0C20117}, | |
206 | /*4 2 4 13 */ | |
207 | {0x000016A0, 0xC102040A}, | |
208 | /*5 2 4 5 */ | |
209 | {0x000016A0, 0xC1420117}, | |
210 | /*6 2 4 19 */ | |
211 | {0x000016A0, 0xC1820419}, | |
212 | /*7 2 4 0 */ | |
213 | {0x000016A0, 0xC1C20117}, | |
214 | /*8 2 4 10 */ | |
215 | {0x000016A0, 0xC2020117}, | |
216 | ||
217 | /* Write Leveling */ | |
218 | /*0 */ | |
219 | {0x000016A0, 0xC0008113}, | |
220 | /*1 */ | |
221 | {0x000016A0, 0xC0404504}, | |
222 | /*2 */ | |
223 | {0x000016A0, 0xC0808514}, | |
224 | /*3 */ | |
225 | {0x000016A0, 0xC0C09418}, | |
226 | /*4 */ | |
227 | {0x000016A0, 0xC1006D0E}, | |
228 | /*5 */ | |
229 | {0x000016A0, 0xC1405508}, | |
230 | /*6 */ | |
231 | {0x000016A0, 0xC1807D12}, | |
232 | /*7 */ | |
233 | {0x000016A0, 0xC1C0b01F}, | |
234 | /*8 */ | |
235 | {0x000016A0, 0xC2005D0A}, | |
236 | ||
237 | /*center DQS on read cycle */ | |
238 | {0x000016A0, 0xC803000F}, | |
239 | ||
240 | {0x00001538, 0x00000008}, /*Read Data Sample Delays Register */ | |
241 | {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */ | |
242 | ||
243 | /*init DRAM */ | |
244 | {0x00001480, 0x00000001}, | |
245 | {0x0, 0x0} | |
246 | }; | |
247 | ||
248 | MV_DRAM_TRAINING_INIT ddr3_db_600[MV_MAX_DDR3_STATIC_SIZE] = { | |
249 | /* Read Leveling */ | |
250 | /*PUP RdSampleDly (+CL) Phase RL ADLL value */ | |
251 | /*0 2 3 1 */ | |
252 | {0x000016A0, 0xC0020104}, | |
253 | /*1 2 2 6 */ | |
254 | {0x000016A0, 0xC0420010}, | |
255 | /*2 2 3 16 */ | |
256 | {0x000016A0, 0xC0820112}, | |
257 | /*3 2 1 26 */ | |
258 | {0x000016A0, 0xC0C20009}, | |
259 | /*4 2 2 29 */ | |
260 | {0x000016A0, 0xC102001F}, | |
261 | /*5 2 2 13 */ | |
262 | {0x000016A0, 0xC1420014}, | |
263 | /*6 2 3 6 */ | |
264 | {0x000016A0, 0xC1820109}, | |
265 | /*7 2 1 31 */ | |
266 | {0x000016A0, 0xC1C2000C}, | |
267 | /*8 2 2 22 */ | |
268 | {0x000016A0, 0xC2020112}, | |
269 | ||
270 | /* Write Leveling */ | |
271 | /*0 */ | |
272 | {0x000016A0, 0xC0009919}, | |
273 | /*1 */ | |
274 | {0x000016A0, 0xC0405508}, | |
275 | /*2 */ | |
276 | {0x000016A0, 0xC0809919}, | |
277 | /*3 */ | |
278 | {0x000016A0, 0xC0C09C1A}, | |
279 | /*4 */ | |
280 | {0x000016A0, 0xC1008113}, | |
281 | /*5 */ | |
282 | {0x000016A0, 0xC140650C}, | |
283 | /*6 */ | |
284 | {0x000016A0, 0xC1809518}, | |
285 | /*7 */ | |
286 | {0x000016A0, 0xC1C04103}, | |
287 | /*8 */ | |
288 | {0x000016A0, 0xC2006D0E}, | |
289 | ||
290 | /*center DQS on read cycle */ | |
291 | {0x000016A0, 0xC803000F}, | |
292 | ||
293 | {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ | |
294 | {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ | |
295 | /*init DRAM */ | |
296 | {0x00001480, 0x00000001}, | |
297 | {0x0, 0x0} | |
298 | }; | |
299 | ||
300 | MV_DRAM_TRAINING_INIT ddr3_db_667[MV_MAX_DDR3_STATIC_SIZE] = { | |
301 | ||
302 | /* Read Leveling */ | |
303 | /*PUP RdSampleDly (+CL) Phase RL ADLL value */ | |
304 | /*0 2 3 1 */ | |
305 | {0x000016A0, 0xC0020103}, | |
306 | /*1 2 2 6 */ | |
307 | {0x000016A0, 0xC0420012}, | |
308 | /*2 2 3 16 */ | |
309 | {0x000016A0, 0xC0820113}, | |
310 | /*3 2 1 26 */ | |
311 | {0x000016A0, 0xC0C20012}, | |
312 | /*4 2 2 29 */ | |
313 | {0x000016A0, 0xC1020100}, | |
314 | /*5 2 2 13 */ | |
315 | {0x000016A0, 0xC1420016}, | |
316 | /*6 2 3 6 */ | |
317 | {0x000016A0, 0xC1820109}, | |
318 | /*7 2 1 31 */ | |
319 | {0x000016A0, 0xC1C20010}, | |
320 | /*8 2 2 22 */ | |
321 | {0x000016A0, 0xC2020112}, | |
322 | ||
323 | /* Write Leveling */ | |
324 | /*0 */ | |
325 | {0x000016A0, 0xC000b11F}, | |
326 | /*1 */ | |
327 | {0x000016A0, 0xC040690D}, | |
328 | /*2 */ | |
329 | {0x000016A0, 0xC0803600}, | |
330 | /*3 */ | |
331 | {0x000016A0, 0xC0C0a81D}, | |
332 | /*4 */ | |
333 | {0x000016A0, 0xC1009919}, | |
334 | /*5 */ | |
335 | {0x000016A0, 0xC1407911}, | |
336 | /*6 */ | |
337 | {0x000016A0, 0xC180ad1e}, | |
338 | /*7 */ | |
339 | {0x000016A0, 0xC1C04d06}, | |
340 | /*8 */ | |
341 | {0x000016A0, 0xC2008514}, | |
342 | ||
343 | /*center DQS on read cycle */ | |
344 | {0x000016A0, 0xC803000F}, | |
345 | ||
346 | {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ | |
347 | {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ | |
348 | ||
349 | /*init DRAM */ | |
350 | {0x00001480, 0x00000001}, | |
351 | {0x0, 0x0} | |
352 | }; | |
353 | ||
354 | MV_DRAM_TRAINING_INIT ddr3_db_800[MV_MAX_DDR3_STATIC_SIZE] = { | |
355 | ||
356 | /* Read Leveling */ | |
357 | /*PUP RdSampleDly (+CL) Phase RL ADLL value */ | |
358 | /*0 2 3 1 */ | |
359 | {0x000016A0, 0xC0020213}, | |
360 | /*1 2 2 6 */ | |
361 | {0x000016A0, 0xC0420108}, | |
362 | /*2 2 3 16 */ | |
363 | {0x000016A0, 0xC0820210}, | |
364 | /*3 2 1 26 */ | |
365 | {0x000016A0, 0xC0C20108}, | |
366 | /*4 2 2 29 */ | |
367 | {0x000016A0, 0xC102011A}, | |
368 | /*5 2 2 13 */ | |
369 | {0x000016A0, 0xC1420300}, | |
370 | /*6 2 3 6 */ | |
371 | {0x000016A0, 0xC1820204}, | |
372 | /*7 2 1 31 */ | |
373 | {0x000016A0, 0xC1C20106}, | |
374 | /*8 2 2 22 */ | |
375 | {0x000016A0, 0xC2020112}, | |
376 | ||
377 | /* Write Leveling */ | |
378 | /*0 */ | |
379 | {0x000016A0, 0xC000620B}, | |
380 | /*1 */ | |
381 | {0x000016A0, 0xC0408D16}, | |
382 | /*2 */ | |
383 | {0x000016A0, 0xC0806A0D}, | |
384 | /*3 */ | |
385 | {0x000016A0, 0xC0C03D02}, | |
386 | /*4 */ | |
387 | {0x000016A0, 0xC1004a05}, | |
388 | /*5 */ | |
389 | {0x000016A0, 0xC140A11B}, | |
390 | /*6 */ | |
391 | {0x000016A0, 0xC1805E0A}, | |
392 | /*7 */ | |
393 | {0x000016A0, 0xC1C06D0E}, | |
394 | /*8 */ | |
395 | {0x000016A0, 0xC200AD1E}, | |
396 | ||
397 | /*center DQS on read cycle */ | |
398 | {0x000016A0, 0xC803000F}, | |
399 | ||
400 | {0x00001538, 0x0000000C}, /*Read Data Sample Delays Register */ | |
401 | {0x0000153C, 0x0000000E}, /*Read Data Ready Delay Register */ | |
402 | ||
403 | /*init DRAM */ | |
404 | {0x00001480, 0x00000001}, | |
405 | {0x0, 0x0} | |
406 | }; | |
407 | ||
408 | MV_DRAM_TRAINING_INIT ddr3_rd_667_0[MV_MAX_DDR3_STATIC_SIZE] = { | |
409 | /* Read Leveling */ | |
410 | /*PUP RdSampleDly (+CL) Phase RL ADLL value */ | |
411 | /*0 */ | |
412 | {0x000016A0, 0xC002010E}, | |
413 | /*1 */ | |
414 | {0x000016A0, 0xC042001E}, | |
415 | /*2 */ | |
416 | {0x000016A0, 0xC0820118}, | |
417 | /*3 */ | |
418 | {0x000016A0, 0xC0C2001E}, | |
419 | /*4 */ | |
420 | {0x000016A0, 0xC102010C}, | |
421 | /*5 */ | |
422 | {0x000016A0, 0xC1420102}, | |
423 | /*6 */ | |
424 | {0x000016A0, 0xC1820111}, | |
425 | /*7 */ | |
426 | {0x000016A0, 0xC1C2001C}, | |
427 | /*8 */ | |
428 | {0x000016A0, 0xC2020109}, | |
429 | ||
430 | /* Write Leveling */ | |
431 | /*0 */ | |
432 | {0x000016A0, 0xC0003600}, | |
433 | /*1 */ | |
434 | {0x000016A0, 0xC040690D}, | |
435 | /*2 */ | |
436 | {0x000016A0, 0xC0805207}, | |
437 | /*3 */ | |
438 | {0x000016A0, 0xC0C0A81D}, | |
439 | /*4 */ | |
440 | {0x000016A0, 0xC1009919}, | |
441 | /*5 */ | |
442 | {0x000016A0, 0xC1407911}, | |
443 | /*6 */ | |
444 | {0x000016A0, 0xC1803E02}, | |
445 | /*7 */ | |
446 | {0x000016A0, 0xC1C05107}, | |
447 | /*8 */ | |
448 | {0x000016A0, 0xC2008113}, | |
449 | ||
450 | /*center DQS on read cycle */ | |
451 | {0x000016A0, 0xC803000F}, | |
452 | ||
453 | {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ | |
454 | {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ | |
455 | ||
456 | /*init DRAM */ | |
457 | {0x00001480, 0x00000001}, | |
458 | {0x0, 0x0} | |
459 | }; | |
460 | ||
461 | MV_DRAM_TRAINING_INIT ddr3_rd_667_1[MV_MAX_DDR3_STATIC_SIZE] = { | |
462 | /* Read Leveling */ | |
463 | /*PUP RdSampleDly (+CL) Phase RL ADLL value */ | |
464 | /*0 */ | |
465 | {0x000016A0, 0xC0020106}, | |
466 | /*1 */ | |
467 | {0x000016A0, 0xC0420016}, | |
468 | /*2 */ | |
469 | {0x000016A0, 0xC0820117}, | |
470 | /*3 */ | |
471 | {0x000016A0, 0xC0C2000F}, | |
472 | /*4 */ | |
473 | {0x000016A0, 0xC1020105}, | |
474 | /*5 */ | |
475 | {0x000016A0, 0xC142001B}, | |
476 | /*6 */ | |
477 | {0x000016A0, 0xC182010C}, | |
478 | /*7 */ | |
479 | {0x000016A0, 0xC1C20011}, | |
480 | /*8 */ | |
481 | {0x000016A0, 0xC2020101}, | |
482 | ||
483 | /* Write Leveling */ | |
484 | /*0 */ | |
485 | {0x000016A0, 0xC0003600}, | |
486 | /*1 */ | |
487 | {0x000016A0, 0xC0406D0E}, | |
488 | /*2 */ | |
489 | {0x000016A0, 0xC0803600}, | |
490 | /*3 */ | |
491 | {0x000016A0, 0xC0C04504}, | |
492 | /*4 */ | |
493 | {0x000016A0, 0xC1009919}, | |
494 | /*5 */ | |
495 | {0x000016A0, 0xC1407911}, | |
496 | /*6 */ | |
497 | {0x000016A0, 0xC1803600}, | |
498 | /*7 */ | |
499 | {0x000016A0, 0xC1C0610B}, | |
500 | /*8 */ | |
501 | {0x000016A0, 0xC2008113}, | |
502 | ||
503 | /*center DQS on read cycle */ | |
504 | {0x000016A0, 0xC803000F}, | |
505 | ||
506 | {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ | |
507 | {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ | |
508 | ||
509 | /*init DRAM */ | |
510 | {0x00001480, 0x00000001}, | |
511 | {0x0, 0x0} | |
512 | }; | |
513 | ||
514 | MV_DRAM_TRAINING_INIT ddr3_rd_667_2[MV_MAX_DDR3_STATIC_SIZE] = { | |
515 | /* Read Leveling */ | |
516 | /*PUP RdSampleDly (+CL) Phase RL ADLL value */ | |
517 | /*0 */ | |
518 | {0x000016A0, 0xC002010C}, | |
519 | /*1 */ | |
520 | {0x000016A0, 0xC042001B}, | |
521 | /*2 */ | |
522 | {0x000016A0, 0xC082011D}, | |
523 | /*3 */ | |
524 | {0x000016A0, 0xC0C20015}, | |
525 | /*4 */ | |
526 | {0x000016A0, 0xC102010B}, | |
527 | /*5 */ | |
528 | {0x000016A0, 0xC1420101}, | |
529 | /*6 */ | |
530 | {0x000016A0, 0xC1820113}, | |
531 | /*7 */ | |
532 | {0x000016A0, 0xC1C20017}, | |
533 | /*8 */ | |
534 | {0x000016A0, 0xC2020107}, | |
535 | ||
536 | /* Write Leveling */ | |
537 | /*0 */ | |
538 | {0x000016A0, 0xC0003600}, | |
539 | /*1 */ | |
540 | {0x000016A0, 0xC0406D0E}, | |
541 | /*2 */ | |
542 | {0x000016A0, 0xC0803600}, | |
543 | /*3 */ | |
544 | {0x000016A0, 0xC0C04504}, | |
545 | /*4 */ | |
546 | {0x000016A0, 0xC1009919}, | |
547 | /*5 */ | |
548 | {0x000016A0, 0xC1407911}, | |
549 | /*6 */ | |
550 | {0x000016A0, 0xC180B11F}, | |
551 | /*7 */ | |
552 | {0x000016A0, 0xC1C0610B}, | |
553 | /*8 */ | |
554 | {0x000016A0, 0xC2008113}, | |
555 | ||
556 | /*center DQS on read cycle */ | |
557 | {0x000016A0, 0xC803000F}, | |
558 | ||
559 | {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ | |
560 | {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ | |
561 | ||
562 | /*init DRAM */ | |
563 | {0x00001480, 0x00000001}, | |
564 | {0x0, 0x0} | |
565 | }; | |
566 | ||
567 | MV_DRAM_TRAINING_INIT ddr3_db_667_M[MV_MAX_DDR3_STATIC_SIZE] = { | |
568 | /* Read Leveling */ | |
569 | /*PUP RdSampleDly (+CL) Phase RL ADLL value */ | |
570 | /* CS 0 */ | |
571 | /*0 2 3 1 */ | |
572 | {0x000016A0, 0xC0020103}, | |
573 | /*1 2 2 6 */ | |
574 | {0x000016A0, 0xC0420012}, | |
575 | /*2 2 3 16 */ | |
576 | {0x000016A0, 0xC0820113}, | |
577 | /*3 2 1 26 */ | |
578 | {0x000016A0, 0xC0C20012}, | |
579 | /*4 2 2 29 */ | |
580 | {0x000016A0, 0xC1020100}, | |
581 | /*5 2 2 13 */ | |
582 | {0x000016A0, 0xC1420016}, | |
583 | /*6 2 3 6 */ | |
584 | {0x000016A0, 0xC1820109}, | |
585 | /*7 2 1 31 */ | |
586 | {0x000016A0, 0xC1C20010}, | |
587 | /*8 2 2 22 */ | |
588 | {0x000016A0, 0xC2020112}, | |
589 | ||
590 | /* Write Leveling */ | |
591 | /*0 */ | |
592 | {0x000016A0, 0xC000b11F}, | |
593 | /*1 */ | |
594 | {0x000016A0, 0xC040690D}, | |
595 | /*2 */ | |
596 | {0x000016A0, 0xC0803600}, | |
597 | /*3 */ | |
598 | {0x000016A0, 0xC0C0a81D}, | |
599 | /*4 */ | |
600 | {0x000016A0, 0xC1009919}, | |
601 | /*5 */ | |
602 | {0x000016A0, 0xC1407911}, | |
603 | /*6 */ | |
604 | {0x000016A0, 0xC180ad1e}, | |
605 | /*7 */ | |
606 | {0x000016A0, 0xC1C04d06}, | |
607 | /*8 */ | |
608 | {0x000016A0, 0xC2008514}, | |
609 | ||
610 | /*center DQS on read cycle */ | |
611 | {0x000016A0, 0xC803000F}, | |
612 | ||
613 | /* CS 1 */ | |
614 | ||
615 | {0x000016A0, 0xC0060103}, | |
616 | /*1 2 2 6 */ | |
617 | {0x000016A0, 0xC0460012}, | |
618 | /*2 2 3 16 */ | |
619 | {0x000016A0, 0xC0860113}, | |
620 | /*3 2 1 26 */ | |
621 | {0x000016A0, 0xC0C60012}, | |
622 | /*4 2 2 29 */ | |
623 | {0x000016A0, 0xC1060100}, | |
624 | /*5 2 2 13 */ | |
625 | {0x000016A0, 0xC1460016}, | |
626 | /*6 2 3 6 */ | |
627 | {0x000016A0, 0xC1860109}, | |
628 | /*7 2 1 31 */ | |
629 | {0x000016A0, 0xC1C60010}, | |
630 | /*8 2 2 22 */ | |
631 | {0x000016A0, 0xC2060112}, | |
632 | ||
633 | /* Write Leveling */ | |
634 | /*0 */ | |
635 | {0x000016A0, 0xC004b11F}, | |
636 | /*1 */ | |
637 | {0x000016A0, 0xC044690D}, | |
638 | /*2 */ | |
639 | {0x000016A0, 0xC0843600}, | |
640 | /*3 */ | |
641 | {0x000016A0, 0xC0C4a81D}, | |
642 | /*4 */ | |
643 | {0x000016A0, 0xC1049919}, | |
644 | /*5 */ | |
645 | {0x000016A0, 0xC1447911}, | |
646 | /*6 */ | |
647 | {0x000016A0, 0xC184ad1e}, | |
648 | /*7 */ | |
649 | {0x000016A0, 0xC1C44d06}, | |
650 | /*8 */ | |
651 | {0x000016A0, 0xC2048514}, | |
652 | ||
653 | /*center DQS on read cycle */ | |
654 | {0x000016A0, 0xC807000F}, | |
655 | ||
656 | /* Both CS */ | |
657 | ||
658 | {0x00001538, 0x00000B0B}, /*Read Data Sample Delays Register */ | |
659 | {0x0000153C, 0x00000F0F}, /*Read Data Ready Delay Register */ | |
660 | ||
661 | /*init DRAM */ | |
662 | {0x00001480, 0x00000001}, | |
663 | {0x0, 0x0} | |
664 | }; | |
665 | ||
666 | MV_DRAM_TRAINING_INIT ddr3_rd_667_3[MV_MAX_DDR3_STATIC_SIZE] = { | |
667 | /* Read Leveling */ | |
668 | /*PUP RdSampleDly (+CL) Phase RL ADLL value */ | |
669 | /*0 */ | |
670 | {0x000016A0, 0xC0020118}, | |
671 | /*1 */ | |
672 | {0x000016A0, 0xC0420108}, | |
673 | /*2 */ | |
674 | {0x000016A0, 0xC0820202}, | |
675 | /*3 */ | |
676 | {0x000016A0, 0xC0C20108}, | |
677 | /*4 */ | |
678 | {0x000016A0, 0xC1020117}, | |
679 | /*5 */ | |
680 | {0x000016A0, 0xC142010C}, | |
681 | /*6 */ | |
682 | {0x000016A0, 0xC182011B}, | |
683 | /*7 */ | |
684 | {0x000016A0, 0xC1C20107}, | |
685 | /*8 */ | |
686 | {0x000016A0, 0xC2020113}, | |
687 | ||
688 | /* Write Leveling */ | |
689 | /*0 */ | |
690 | {0x000016A0, 0xC0003600}, | |
691 | /*1 */ | |
692 | {0x000016A0, 0xC0406D0E}, | |
693 | /*2 */ | |
694 | {0x000016A0, 0xC0805207}, | |
695 | /*3 */ | |
696 | {0x000016A0, 0xC0C0A81D}, | |
697 | /*4 */ | |
698 | {0x000016A0, 0xC1009919}, | |
699 | /*5 */ | |
700 | {0x000016A0, 0xC1407911}, | |
701 | /*6 */ | |
702 | {0x000016A0, 0xC1803E02}, | |
703 | /*7 */ | |
704 | {0x000016A0, 0xC1C04D06}, | |
705 | /*8 */ | |
706 | {0x000016A0, 0xC2008113}, | |
707 | ||
708 | /*center DQS on read cycle */ | |
709 | {0x000016A0, 0xC803000F}, | |
710 | ||
711 | {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */ | |
712 | {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */ | |
713 | ||
714 | /*init DRAM */ | |
715 | {0x00001480, 0x00000001}, | |
716 | {0x0, 0x0} | |
717 | }; | |
718 | ||
719 | MV_DRAM_TRAINING_INIT ddr3_pcac_600[MV_MAX_DDR3_STATIC_SIZE] = { | |
720 | /* Read Leveling */ | |
721 | /*PUP RdSampleDly (+CL) Phase RL ADLL value */ | |
722 | /*0 */ | |
723 | {0x000016A0, 0xC0020404}, | |
724 | /* 1 2 2 6 */ | |
725 | {0x000016A0, 0xC042031E}, | |
726 | /* 2 2 3 16 */ | |
727 | {0x000016A0, 0xC0820411}, | |
728 | /* 3 2 1 26 */ | |
729 | {0x000016A0, 0xC0C20400}, | |
730 | /* 4 2 2 29 */ | |
731 | {0x000016A0, 0xC1020404}, | |
732 | /* 5 2 2 13 */ | |
733 | {0x000016A0, 0xC142031D}, | |
734 | /* 6 2 3 6 */ | |
735 | {0x000016A0, 0xC182040C}, | |
736 | /* 7 2 1 31 */ | |
737 | {0x000016A0, 0xC1C2031B}, | |
738 | /* 8 2 2 22 */ | |
739 | {0x000016A0, 0xC2020112}, | |
740 | ||
741 | /* Write Leveling */ | |
742 | /* 0 */ | |
743 | {0x000016A0, 0xC0004905}, | |
744 | /* 1 */ | |
745 | {0x000016A0, 0xC040A81D}, | |
746 | /* 2 */ | |
747 | {0x000016A0, 0xC0804504}, | |
748 | /* 3 */ | |
749 | {0x000016A0, 0xC0C08013}, | |
750 | /* 4 */ | |
751 | {0x000016A0, 0xC1004504}, | |
752 | /* 5 */ | |
753 | {0x000016A0, 0xC140A81D}, | |
754 | /* 6 */ | |
755 | {0x000016A0, 0xC1805909}, | |
756 | /* 7 */ | |
757 | {0x000016A0, 0xC1C09418}, | |
758 | /* 8 */ | |
759 | {0x000016A0, 0xC2006D0E}, | |
760 | ||
761 | /*center DQS on read cycle */ | |
762 | {0x000016A0, 0xC803000F}, | |
763 | {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */ | |
764 | {0x0000153C, 0x0000000D}, /*Read Data Ready Delay Register */ | |
765 | /* init DRAM */ | |
766 | {0x00001480, 0x00000001}, | |
767 | {0x0, 0x0} | |
768 | }; | |
769 | ||
770 | #endif /* __AXP_TRAINING_STATIC_H */ |