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f8d25d74 SR |
1 | /* |
2 | * Copyright (C) Marvell International Ltd. and its affiliates | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0 | |
5 | */ | |
6 | ||
7 | #ifndef __AXP_MC_STATIC_H | |
8 | #define __AXP_MC_STATIC_H | |
9 | ||
10 | MV_DRAM_MC_INIT ddr3_A0_db_667[MV_MAX_DDR3_STATIC_SIZE] = { | |
11 | #ifdef MV_DDR_32BIT | |
12 | {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */ | |
13 | #else /*MV_DDR_64BIT */ | |
14 | {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ | |
15 | #endif | |
16 | {0x00001404, 0x3630b800}, /*Dunit Control Low Register */ | |
17 | {0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */ | |
18 | /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */ | |
19 | {0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */ | |
20 | ||
21 | #ifdef DB_78X60_PCAC | |
22 | {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */ | |
23 | #else | |
24 | {0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */ | |
25 | #endif | |
26 | ||
27 | {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */ | |
28 | {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */ | |
29 | {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */ | |
30 | {0x00001424, 0x0000D3FF}, /*Dunit Control High Register */ | |
31 | {0x00001428, 0x000F8830}, /*Dunit Control High Register */ | |
32 | {0x0000142C, 0x214C2F38}, /*Dunit Control High Register */ | |
33 | {0x0000147C, 0x0000c671}, | |
34 | ||
35 | {0x000014a0, 0x000002A9}, | |
36 | {0x000014a8, 0x00000101}, /*2:1 */ | |
37 | {0x00020220, 0x00000007}, | |
38 | ||
39 | {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */ | |
40 | {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */ | |
41 | {0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */ | |
42 | ||
43 | {0x000014C0, 0x192434e9}, /* DRAM address and Control Driving Strenght */ | |
44 | {0x000014C4, 0x092434e9}, /* DRAM Data and DQS Driving Strenght */ | |
45 | ||
46 | {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */ | |
47 | {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */ | |
48 | ||
49 | {0x0001504, 0x7FFFFFF1}, /* CS0 Size */ | |
50 | {0x000150C, 0x00000000}, /* CS1 Size */ | |
51 | {0x0001514, 0x00000000}, /* CS2 Size */ | |
52 | {0x000151C, 0x00000000}, /* CS3 Size */ | |
53 | ||
54 | /* {0x00001524, 0x0000C800}, */ | |
55 | {0x00001538, 0x0000000b}, /*Read Data Sample Delays Register */ | |
56 | {0x0000153C, 0x0000000d}, /*Read Data Ready Delay Register */ | |
57 | ||
58 | {0x000015D0, 0x00000640}, /*MR0 */ | |
59 | {0x000015D4, 0x00000046}, /*MR1 */ | |
60 | {0x000015D8, 0x00000010}, /*MR2 */ | |
61 | {0x000015DC, 0x00000000}, /*MR3 */ | |
62 | ||
63 | {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */ | |
64 | {0x000015EC, 0xd800aa25}, /*DDR PHY */ | |
65 | {0x0, 0x0} | |
66 | }; | |
67 | ||
68 | MV_DRAM_MC_INIT ddr3_A0_AMC_667[MV_MAX_DDR3_STATIC_SIZE] = { | |
69 | #ifdef MV_DDR_32BIT | |
70 | {0x00001400, 0x7301c924}, /*DDR SDRAM Configuration Register */ | |
71 | #else /*MV_DDR_64BIT */ | |
72 | {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ | |
73 | #endif | |
74 | {0x00001404, 0x3630b800}, /*Dunit Control Low Register */ | |
75 | {0x00001408, 0x43149775}, /*DDR SDRAM Timing (Low) Register */ | |
76 | /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */ | |
77 | {0x0000140C, 0x38d83fe0}, /*DDR SDRAM Timing (High) Register */ | |
78 | ||
79 | #ifdef DB_78X60_PCAC | |
80 | {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */ | |
81 | #else | |
82 | {0x00001410, 0x040F000C}, /*DDR SDRAM Open Pages Control Register */ | |
83 | #endif | |
84 | ||
85 | {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */ | |
86 | {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */ | |
87 | {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */ | |
88 | {0x00001424, 0x0000D3FF}, /*Dunit Control High Register */ | |
89 | {0x00001428, 0x000F8830}, /*Dunit Control High Register */ | |
90 | {0x0000142C, 0x214C2F38}, /*Dunit Control High Register */ | |
91 | {0x0000147C, 0x0000c671}, | |
92 | ||
93 | {0x000014a0, 0x000002A9}, | |
94 | {0x000014a8, 0x00000101}, /*2:1 */ | |
95 | {0x00020220, 0x00000007}, | |
96 | ||
97 | {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */ | |
98 | {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */ | |
99 | {0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */ | |
100 | ||
101 | {0x000014C0, 0x192434e9}, /* DRAM address and Control Driving Strenght */ | |
102 | {0x000014C4, 0x092434e9}, /* DRAM Data and DQS Driving Strenght */ | |
103 | ||
104 | {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */ | |
105 | {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */ | |
106 | ||
107 | {0x0001504, 0x3FFFFFF1}, /* CS0 Size */ | |
108 | {0x000150C, 0x00000000}, /* CS1 Size */ | |
109 | {0x0001514, 0x00000000}, /* CS2 Size */ | |
110 | {0x000151C, 0x00000000}, /* CS3 Size */ | |
111 | ||
112 | /* {0x00001524, 0x0000C800}, */ | |
113 | {0x00001538, 0x0000000b}, /*Read Data Sample Delays Register */ | |
114 | {0x0000153C, 0x0000000d}, /*Read Data Ready Delay Register */ | |
115 | ||
116 | {0x000015D0, 0x00000640}, /*MR0 */ | |
117 | {0x000015D4, 0x00000046}, /*MR1 */ | |
118 | {0x000015D8, 0x00000010}, /*MR2 */ | |
119 | {0x000015DC, 0x00000000}, /*MR3 */ | |
120 | ||
121 | {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */ | |
122 | {0x000015EC, 0xd800aa25}, /*DDR PHY */ | |
123 | {0x0, 0x0} | |
124 | }; | |
125 | ||
126 | MV_DRAM_MC_INIT ddr3_A0_db_400[MV_MAX_DDR3_STATIC_SIZE] = { | |
127 | #ifdef MV_DDR_32BIT | |
128 | {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */ | |
129 | #else /* MV_DDR_64BIT */ | |
130 | {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */ | |
131 | #endif | |
132 | {0x00001404, 0x3630B840}, /*Dunit Control Low Register */ | |
133 | {0x00001408, 0x33137663}, /*DDR SDRAM Timing (Low) Register */ | |
134 | {0x0000140C, 0x38000C55}, /*DDR SDRAM Timing (High) Register */ | |
135 | {0x00001410, 0x040F0000}, /*DDR SDRAM Address Control Register */ | |
136 | {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */ | |
137 | {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */ | |
138 | {0x0000141C, 0x00000672}, /*DDR SDRAM Mode Register */ | |
139 | {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */ | |
140 | {0x00001424, 0x0100D3FF}, /*Dunit Control High Register */ | |
141 | {0x00001428, 0x000D6720}, /*Dunit Control High Register */ | |
142 | {0x0000142C, 0x014C2F38}, /*Dunit Control High Register */ | |
143 | {0x0000147C, 0x00006571}, | |
144 | ||
145 | {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */ | |
146 | {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */ | |
147 | {0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */ | |
148 | ||
149 | {0x000014a0, 0x000002A9}, | |
150 | {0x000014a8, 0x00000101}, /*2:1 */ | |
151 | {0x00020220, 0x00000007}, | |
152 | ||
153 | {0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */ | |
154 | {0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */ | |
155 | ||
156 | {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */ | |
157 | {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */ | |
158 | ||
159 | {0x0001504, 0x7FFFFFF1}, /* CS0 Size */ | |
160 | {0x000150C, 0x00000000}, /* CS1 Size */ | |
161 | {0x0001514, 0x00000000}, /* CS2 Size */ | |
162 | {0x000151C, 0x00000000}, /* CS3 Size */ | |
163 | ||
164 | {0x00001538, 0x00000008}, /*Read Data Sample Delays Register */ | |
165 | {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */ | |
166 | ||
167 | {0x000015D0, 0x00000630}, /*MR0 */ | |
168 | {0x000015D4, 0x00000046}, /*MR1 */ | |
169 | {0x000015D8, 0x00000008}, /*MR2 */ | |
170 | {0x000015DC, 0x00000000}, /*MR3 */ | |
171 | ||
172 | {0x000015E4, 0x00203c18}, /*ZQDS Configuration Register */ | |
173 | /* {0x000015EC, 0xDE000025}, *//*DDR PHY */ | |
174 | {0x000015EC, 0xF800AA25}, /*DDR PHY */ | |
175 | {0x0, 0x0} | |
176 | }; | |
177 | ||
178 | MV_DRAM_MC_INIT ddr3_Z1_db_600[MV_MAX_DDR3_STATIC_SIZE] = { | |
179 | #ifdef MV_DDR_32BIT | |
180 | {0x00001400, 0x73014A28}, /*DDR SDRAM Configuration Register */ | |
181 | #else /*MV_DDR_64BIT */ | |
182 | {0x00001400, 0x7301CA28}, /*DDR SDRAM Configuration Register */ | |
183 | #endif | |
184 | {0x00001404, 0x3630B040}, /*Dunit Control Low Register */ | |
185 | {0x00001408, 0x44149887}, /*DDR SDRAM Timing (Low) Register */ | |
186 | /* {0x0000140C, 0x38000C6A}, *//*DDR SDRAM Timing (High) Register */ | |
187 | {0x0000140C, 0x38D83FE0}, /*DDR SDRAM Timing (High) Register */ | |
188 | ||
189 | #ifdef DB_78X60_PCAC | |
190 | {0x00001410, 0x040F0001}, /*DDR SDRAM Address Control Register */ | |
191 | #else | |
192 | {0x00001410, 0x040F0000}, /*DDR SDRAM Open Pages Control Register */ | |
193 | #endif | |
194 | ||
195 | {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */ | |
196 | {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */ | |
197 | {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */ | |
198 | {0x00001424, 0x0100D1FF}, /*Dunit Control High Register */ | |
199 | {0x00001428, 0x000F8830}, /*Dunit Control High Register */ | |
200 | {0x0000142C, 0x214C2F38}, /*Dunit Control High Register */ | |
201 | {0x0000147C, 0x0000c671}, | |
202 | ||
203 | {0x000014a8, 0x00000101}, /*2:1 */ | |
204 | {0x00020220, 0x00000007}, | |
205 | ||
206 | {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */ | |
207 | {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */ | |
208 | {0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */ | |
209 | ||
210 | {0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */ | |
211 | {0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */ | |
212 | ||
213 | {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */ | |
214 | {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */ | |
215 | ||
216 | {0x0001504, 0x7FFFFFF1}, /* CS0 Size */ | |
217 | {0x000150C, 0x00000000}, /* CS1 Size */ | |
218 | {0x0001514, 0x00000000}, /* CS2 Size */ | |
219 | {0x000151C, 0x00000000}, /* CS3 Size */ | |
220 | ||
221 | /* {0x00001524, 0x0000C800}, */ | |
222 | {0x00001538, 0x0000000b}, /*Read Data Sample Delays Register */ | |
223 | {0x0000153C, 0x0000000d}, /*Read Data Ready Delay Register */ | |
224 | ||
225 | {0x000015D0, 0x00000650}, /*MR0 */ | |
226 | {0x000015D4, 0x00000046}, /*MR1 */ | |
227 | {0x000015D8, 0x00000010}, /*MR2 */ | |
228 | {0x000015DC, 0x00000000}, /*MR3 */ | |
229 | ||
230 | {0x000015E4, 0x00203c18}, /*ZQC Configuration Register */ | |
231 | {0x000015EC, 0xDE000025}, /*DDR PHY */ | |
232 | {0x0, 0x0} | |
233 | }; | |
234 | ||
235 | MV_DRAM_MC_INIT ddr3_Z1_db_300[MV_MAX_DDR3_STATIC_SIZE] = { | |
236 | #ifdef MV_DDR_32BIT | |
237 | {0x00001400, 0x73004C30}, /*DDR SDRAM Configuration Register */ | |
238 | #else /*MV_DDR_64BIT */ | |
239 | {0x00001400, 0x7300CC30}, /*DDR SDRAM Configuration Register */ | |
240 | /*{0x00001400, 0x7304CC30}, *//*DDR SDRAM Configuration Register */ | |
241 | #endif | |
242 | {0x00001404, 0x3630B840}, /*Dunit Control Low Register */ | |
243 | {0x00001408, 0x33137663}, /*DDR SDRAM Timing (Low) Register */ | |
244 | {0x0000140C, 0x38000C55}, /*DDR SDRAM Timing (High) Register */ | |
245 | {0x00001410, 0x040F0000}, /*DDR SDRAM Address Control Register */ | |
246 | {0x00001414, 0x00000000}, /*DDR SDRAM Open Pages Control Register */ | |
247 | {0x00001418, 0x00000e00}, /*DDR SDRAM Operation Register */ | |
248 | {0x0000141C, 0x00000672}, /*DDR SDRAM Mode Register */ | |
249 | {0x00001420, 0x00000004}, /*DDR SDRAM Extended Mode Register */ | |
250 | {0x00001424, 0x0100F1FF}, /*Dunit Control High Register */ | |
251 | {0x00001428, 0x000D6720}, /*Dunit Control High Register */ | |
252 | {0x0000142C, 0x014C2F38}, /*Dunit Control High Register */ | |
253 | {0x0000147C, 0x00006571}, | |
254 | ||
255 | {0x00001494, 0x00010000}, /*DDR SDRAM ODT Control (Low) Register */ | |
256 | {0x00001498, 0x00000000}, /*DDR SDRAM ODT Control (High) Register */ | |
257 | {0x0000149C, 0x00000301}, /*DDR Dunit ODT Control Register */ | |
258 | ||
259 | {0x000014C0, 0x192424C8}, /* DRAM address and Control Driving Strenght */ | |
260 | {0x000014C4, 0xEFB24C8}, /* DRAM Data and DQS Driving Strenght */ | |
261 | ||
262 | {0x000200e8, 0x3FFF0E01}, /* DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the training sequence */ | |
263 | {0x00020184, 0x3FFFFFE0}, /* DO NOT Modify - Close fast path Window to - 2G */ | |
264 | ||
265 | {0x0001504, 0x7FFFFFF1}, /* CS0 Size */ | |
266 | {0x000150C, 0x00000000}, /* CS1 Size */ | |
267 | {0x0001514, 0x00000000}, /* CS2 Size */ | |
268 | {0x000151C, 0x00000000}, /* CS3 Size */ | |
269 | ||
270 | {0x00001538, 0x00000008}, /*Read Data Sample Delays Register */ | |
271 | {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */ | |
272 | ||
273 | {0x000015D0, 0x00000630}, /*MR0 */ | |
274 | {0x000015D4, 0x00000046}, /*MR1 */ | |
275 | {0x000015D8, 0x00000008}, /*MR2 */ | |
276 | {0x000015DC, 0x00000000}, /*MR3 */ | |
277 | ||
278 | {0x000015E4, 0x00203c18}, /*ZQDS Configuration Register */ | |
279 | {0x000015EC, 0xDE000025}, /*DDR PHY */ | |
280 | ||
281 | {0x0, 0x0} | |
282 | }; | |
283 | ||
284 | #endif /* __AXP_MC_STATIC_H */ |