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017f11f6 PT |
1 | /* |
2 | * Copyright 2004,2007,2008 Freescale Semiconductor, Inc. | |
3 | * (C) Copyright 2002, 2003 Motorola Inc. | |
4 | * Xianghua Xiao (X.Xiao@motorola.com) | |
5 | * | |
6 | * (C) Copyright 2000 | |
7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
8 | * | |
9 | * See file CREDITS for list of people who contributed to this | |
10 | * project. | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or | |
13 | * modify it under the terms of the GNU General Public License as | |
14 | * published by the Free Software Foundation; either version 2 of | |
15 | * the License, or (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | * MA 02111-1307 USA | |
26 | */ | |
27 | ||
28 | #include <config.h> | |
29 | #include <common.h> | |
a730393a | 30 | #include <asm/io.h> |
017f11f6 PT |
31 | #include <asm/fsl_dma.h> |
32 | ||
51402ac1 PT |
33 | /* Controller can only transfer 2^26 - 1 bytes at a time */ |
34 | #define FSL_DMA_MAX_SIZE (0x3ffffff) | |
35 | ||
017f11f6 | 36 | #if defined(CONFIG_MPC85xx) |
a730393a | 37 | ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); |
017f11f6 | 38 | #elif defined(CONFIG_MPC86xx) |
a730393a | 39 | ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR); |
017f11f6 PT |
40 | #else |
41 | #error "Freescale DMA engine not supported on your processor" | |
42 | #endif | |
43 | ||
44 | static void dma_sync(void) | |
45 | { | |
46 | #if defined(CONFIG_MPC85xx) | |
47 | asm("sync; isync; msync"); | |
48 | #elif defined(CONFIG_MPC86xx) | |
49 | asm("sync; isync"); | |
50 | #endif | |
51 | } | |
52 | ||
53 | static uint dma_check(void) { | |
54 | volatile fsl_dma_t *dma = &dma_base->dma[0]; | |
a730393a | 55 | uint status; |
017f11f6 PT |
56 | |
57 | /* While the channel is busy, spin */ | |
a730393a PT |
58 | do { |
59 | status = in_be32(&dma->sr); | |
60 | } while (status & FSL_DMA_SR_CB); | |
017f11f6 PT |
61 | |
62 | /* clear MR[CS] channel start bit */ | |
484919cf | 63 | out_be32(&dma->mr, in_be32(&dma->mr) & ~FSL_DMA_MR_CS); |
017f11f6 PT |
64 | dma_sync(); |
65 | ||
66 | if (status != 0) | |
67 | printf ("DMA Error: status = %x\n", status); | |
68 | ||
69 | return status; | |
70 | } | |
71 | ||
72 | void dma_init(void) { | |
73 | volatile fsl_dma_t *dma = &dma_base->dma[0]; | |
74 | ||
6af015b8 PT |
75 | out_be32(&dma->satr, FSL_DMA_SATR_SREAD_SNOOP); |
76 | out_be32(&dma->datr, FSL_DMA_DATR_DWRITE_SNOOP); | |
a730393a | 77 | out_be32(&dma->sr, 0xffffffff); /* clear any errors */ |
017f11f6 PT |
78 | dma_sync(); |
79 | } | |
80 | ||
7892f619 | 81 | int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) { |
017f11f6 | 82 | volatile fsl_dma_t *dma = &dma_base->dma[0]; |
51402ac1 | 83 | uint xfer_size; |
017f11f6 | 84 | |
51402ac1 PT |
85 | while (count) { |
86 | xfer_size = MIN(FSL_DMA_MAX_SIZE, count); | |
017f11f6 | 87 | |
51402ac1 PT |
88 | out_be32(&dma->dar, (uint) dest); |
89 | out_be32(&dma->sar, (uint) src); | |
90 | out_be32(&dma->bcr, xfer_size); | |
017f11f6 | 91 | |
51402ac1 PT |
92 | /* Disable bandwidth control, use direct transfer mode */ |
93 | out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT); | |
94 | dma_sync(); | |
95 | ||
96 | /* Start the transfer */ | |
97 | out_be32(&dma->mr, FSL_DMA_MR_BWC_DIS | | |
98 | FSL_DMA_MR_CTM_DIRECT | | |
99 | FSL_DMA_MR_CS); | |
100 | ||
101 | count -= xfer_size; | |
102 | src += xfer_size; | |
103 | dest += xfer_size; | |
104 | ||
105 | dma_sync(); | |
106 | ||
107 | if (dma_check()) | |
108 | return -1; | |
109 | } | |
017f11f6 | 110 | |
51402ac1 | 111 | return 0; |
017f11f6 | 112 | } |
0d595f76 PT |
113 | |
114 | #if (defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) | |
115 | void dma_meminit(uint val, uint size) | |
116 | { | |
117 | uint *p = 0; | |
118 | uint i = 0; | |
119 | ||
120 | for (*p = 0; p < (uint *)(8 * 1024); p++) { | |
121 | if (((uint)p & 0x1f) == 0) | |
122 | ppcDcbz((ulong)p); | |
123 | ||
124 | *p = (uint)CONFIG_MEM_INIT_VALUE; | |
125 | ||
126 | if (((uint)p & 0x1c) == 0x1c) | |
127 | ppcDcbf((ulong)p); | |
128 | } | |
129 | ||
130 | dmacpy(0x002000, 0, 0x002000); /* 8K */ | |
131 | dmacpy(0x004000, 0, 0x004000); /* 16K */ | |
132 | dmacpy(0x008000, 0, 0x008000); /* 32K */ | |
133 | dmacpy(0x010000, 0, 0x010000); /* 64K */ | |
134 | dmacpy(0x020000, 0, 0x020000); /* 128K */ | |
135 | dmacpy(0x040000, 0, 0x040000); /* 256K */ | |
136 | dmacpy(0x080000, 0, 0x080000); /* 512K */ | |
137 | dmacpy(0x100000, 0, 0x100000); /* 1M */ | |
138 | dmacpy(0x200000, 0, 0x200000); /* 2M */ | |
139 | dmacpy(0x400000, 0, 0x400000); /* 4M */ | |
140 | ||
141 | for (i = 1; i < size / 0x800000; i++) | |
142 | dmacpy((0x800000 * i), 0, 0x800000); | |
143 | } | |
144 | #endif |