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980db8ca SL |
1 | /* |
2 | * Copyright (C) 2008 by NXP Semiconductors | |
3 | * @Author: Kevin Wells | |
4 | * @Descr: LPC3250 DMA controller interface support functions | |
5 | * | |
6 | * Copyright (c) 2015 Tyco Fire Protection Products. | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
11 | #include <common.h> | |
12 | #include <errno.h> | |
13 | #include <asm/arch/dma.h> | |
14 | #include <asm/arch/cpu.h> | |
15 | #include <asm/arch/clk.h> | |
16 | #include <asm/arch/sys_proto.h> | |
17 | #include <asm/io.h> | |
18 | ||
19 | /* DMA controller channel register structure */ | |
20 | struct dmac_chan_reg { | |
21 | u32 src_addr; | |
22 | u32 dest_addr; | |
23 | u32 lli; | |
24 | u32 control; | |
25 | u32 config_ch; | |
26 | u32 reserved[3]; | |
27 | }; | |
28 | ||
29 | /* DMA controller register structures */ | |
30 | struct dma_reg { | |
31 | u32 int_stat; | |
32 | u32 int_tc_stat; | |
33 | u32 int_tc_clear; | |
34 | u32 int_err_stat; | |
35 | u32 int_err_clear; | |
36 | u32 raw_tc_stat; | |
37 | u32 raw_err_stat; | |
38 | u32 chan_enable; | |
39 | u32 sw_burst_req; | |
40 | u32 sw_single_req; | |
41 | u32 sw_last_burst_req; | |
42 | u32 sw_last_single_req; | |
43 | u32 config; | |
44 | u32 sync; | |
45 | u32 reserved[50]; | |
46 | struct dmac_chan_reg dma_chan[8]; | |
47 | }; | |
48 | ||
49 | #define DMA_NO_OF_CHANNELS 8 | |
50 | ||
51 | /* config register definitions */ | |
52 | #define DMAC_CTRL_ENABLE (1 << 0) /* For enabling the DMA controller */ | |
53 | ||
54 | static u32 alloc_ch; | |
55 | ||
56 | static struct dma_reg *dma = (struct dma_reg *)DMA_BASE; | |
57 | ||
58 | int lpc32xx_dma_get_channel(void) | |
59 | { | |
60 | int i; | |
61 | ||
62 | if (!alloc_ch) { /* First time caller */ | |
63 | /* | |
64 | * DMA clock are enable by "lpc32xx_dma_init()" and should | |
65 | * be call by board "board_early_init_f()" function. | |
66 | */ | |
67 | ||
68 | /* | |
69 | * Make sure DMA controller and all channels are disabled. | |
70 | * Controller is in little-endian mode. Disable sync signals. | |
71 | */ | |
72 | writel(0, &dma->config); | |
73 | writel(0, &dma->sync); | |
74 | ||
75 | /* Clear interrupt and error statuses */ | |
76 | writel(0xFF, &dma->int_tc_clear); | |
77 | writel(0xFF, &dma->raw_tc_stat); | |
78 | writel(0xFF, &dma->int_err_clear); | |
79 | writel(0xFF, &dma->raw_err_stat); | |
80 | ||
81 | /* Enable DMA controller */ | |
82 | writel(DMAC_CTRL_ENABLE, &dma->config); | |
83 | } | |
84 | ||
85 | i = ffz(alloc_ch); | |
86 | ||
87 | /* Check if all the available channels are busy */ | |
88 | if (unlikely(i == DMA_NO_OF_CHANNELS)) | |
89 | return -1; | |
90 | alloc_ch |= BIT_MASK(i); | |
91 | return i; | |
92 | } | |
93 | ||
94 | int lpc32xx_dma_start_xfer(unsigned int channel, | |
95 | const struct lpc32xx_dmac_ll *desc, u32 config) | |
96 | { | |
97 | if (unlikely(((BIT_MASK(channel) & alloc_ch) == 0) || | |
98 | (channel >= DMA_NO_OF_CHANNELS))) { | |
9b643e31 | 99 | pr_err("Request for xfer on unallocated channel %d", channel); |
980db8ca SL |
100 | return -1; |
101 | } | |
102 | writel(BIT_MASK(channel), &dma->int_tc_clear); | |
103 | writel(BIT_MASK(channel), &dma->int_err_clear); | |
104 | writel(desc->dma_src, &dma->dma_chan[channel].src_addr); | |
105 | writel(desc->dma_dest, &dma->dma_chan[channel].dest_addr); | |
106 | writel(desc->next_lli, &dma->dma_chan[channel].lli); | |
107 | writel(desc->next_ctrl, &dma->dma_chan[channel].control); | |
108 | writel(config, &dma->dma_chan[channel].config_ch); | |
109 | ||
110 | return 0; | |
111 | } | |
112 | ||
113 | int lpc32xx_dma_wait_status(unsigned int channel) | |
114 | { | |
115 | unsigned long start; | |
116 | u32 reg; | |
117 | ||
118 | /* Check if given channel is valid */ | |
119 | if (unlikely(channel >= DMA_NO_OF_CHANNELS)) { | |
9b643e31 | 120 | pr_err("Request for status on unallocated channel %d", channel); |
980db8ca SL |
121 | return -1; |
122 | } | |
123 | ||
124 | start = get_timer(0); | |
125 | while (1) { | |
126 | reg = readl(&dma->raw_tc_stat); | |
127 | reg |= readl(dma->raw_err_stat); | |
128 | if (reg & BIT_MASK(channel)) | |
129 | break; | |
130 | ||
131 | if (get_timer(start) > CONFIG_SYS_HZ) { | |
9b643e31 | 132 | pr_err("DMA status timeout channel %d\n", channel); |
980db8ca SL |
133 | return -ETIMEDOUT; |
134 | } | |
135 | udelay(1); | |
136 | } | |
137 | ||
138 | if (unlikely(readl(&dma->raw_err_stat) & BIT_MASK(channel))) { | |
139 | setbits_le32(&dma->int_err_clear, BIT_MASK(channel)); | |
140 | setbits_le32(&dma->raw_err_stat, BIT_MASK(channel)); | |
9b643e31 | 141 | pr_err("DMA error on channel %d\n", channel); |
980db8ca SL |
142 | return -1; |
143 | } | |
144 | setbits_le32(&dma->int_tc_clear, BIT_MASK(channel)); | |
145 | setbits_le32(&dma->raw_tc_stat, BIT_MASK(channel)); | |
146 | return 0; | |
147 | } |