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b7d861d9 BK |
1 | /* |
2 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
3 | * http://www.samsung.com | |
b3040e40 JB |
4 | * |
5 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | |
6 | * Jaswinder Singh <jassi.brar@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
b7d861d9 | 14 | #include <linux/kernel.h> |
b3040e40 JB |
15 | #include <linux/io.h> |
16 | #include <linux/init.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/module.h> | |
b7d861d9 BK |
19 | #include <linux/string.h> |
20 | #include <linux/delay.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/dma-mapping.h> | |
b3040e40 | 23 | #include <linux/dmaengine.h> |
b3040e40 | 24 | #include <linux/amba/bus.h> |
1b9bb715 | 25 | #include <linux/scatterlist.h> |
93ed5544 | 26 | #include <linux/of.h> |
a80258f9 | 27 | #include <linux/of_dma.h> |
bcc7fa95 | 28 | #include <linux/err.h> |
ae43b328 | 29 | #include <linux/pm_runtime.h> |
1d48745b | 30 | #include <linux/bug.h> |
b3040e40 | 31 | |
d2ebfb33 | 32 | #include "dmaengine.h" |
b7d861d9 BK |
33 | #define PL330_MAX_CHAN 8 |
34 | #define PL330_MAX_IRQS 32 | |
35 | #define PL330_MAX_PERI 32 | |
86a8ce7d | 36 | #define PL330_MAX_BURST 16 |
b7d861d9 | 37 | |
271e1b86 AK |
38 | #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0) |
39 | ||
f0564c7e LPC |
40 | enum pl330_cachectrl { |
41 | CCTRL0, /* Noncacheable and nonbufferable */ | |
42 | CCTRL1, /* Bufferable only */ | |
43 | CCTRL2, /* Cacheable, but do not allocate */ | |
44 | CCTRL3, /* Cacheable and bufferable, but do not allocate */ | |
45 | INVALID1, /* AWCACHE = 0x1000 */ | |
46 | INVALID2, | |
47 | CCTRL6, /* Cacheable write-through, allocate on writes only */ | |
48 | CCTRL7, /* Cacheable write-back, allocate on writes only */ | |
b7d861d9 BK |
49 | }; |
50 | ||
51 | enum pl330_byteswap { | |
52 | SWAP_NO, | |
53 | SWAP_2, | |
54 | SWAP_4, | |
55 | SWAP_8, | |
56 | SWAP_16, | |
57 | }; | |
58 | ||
b7d861d9 BK |
59 | /* Register and Bit field Definitions */ |
60 | #define DS 0x0 | |
61 | #define DS_ST_STOP 0x0 | |
62 | #define DS_ST_EXEC 0x1 | |
63 | #define DS_ST_CMISS 0x2 | |
64 | #define DS_ST_UPDTPC 0x3 | |
65 | #define DS_ST_WFE 0x4 | |
66 | #define DS_ST_ATBRR 0x5 | |
67 | #define DS_ST_QBUSY 0x6 | |
68 | #define DS_ST_WFP 0x7 | |
69 | #define DS_ST_KILL 0x8 | |
70 | #define DS_ST_CMPLT 0x9 | |
71 | #define DS_ST_FLTCMP 0xe | |
72 | #define DS_ST_FAULT 0xf | |
73 | ||
74 | #define DPC 0x4 | |
75 | #define INTEN 0x20 | |
76 | #define ES 0x24 | |
77 | #define INTSTATUS 0x28 | |
78 | #define INTCLR 0x2c | |
79 | #define FSM 0x30 | |
80 | #define FSC 0x34 | |
81 | #define FTM 0x38 | |
82 | ||
83 | #define _FTC 0x40 | |
84 | #define FTC(n) (_FTC + (n)*0x4) | |
85 | ||
86 | #define _CS 0x100 | |
87 | #define CS(n) (_CS + (n)*0x8) | |
88 | #define CS_CNS (1 << 21) | |
89 | ||
90 | #define _CPC 0x104 | |
91 | #define CPC(n) (_CPC + (n)*0x8) | |
92 | ||
93 | #define _SA 0x400 | |
94 | #define SA(n) (_SA + (n)*0x20) | |
95 | ||
96 | #define _DA 0x404 | |
97 | #define DA(n) (_DA + (n)*0x20) | |
98 | ||
99 | #define _CC 0x408 | |
100 | #define CC(n) (_CC + (n)*0x20) | |
101 | ||
102 | #define CC_SRCINC (1 << 0) | |
103 | #define CC_DSTINC (1 << 14) | |
104 | #define CC_SRCPRI (1 << 8) | |
105 | #define CC_DSTPRI (1 << 22) | |
106 | #define CC_SRCNS (1 << 9) | |
107 | #define CC_DSTNS (1 << 23) | |
108 | #define CC_SRCIA (1 << 10) | |
109 | #define CC_DSTIA (1 << 24) | |
110 | #define CC_SRCBRSTLEN_SHFT 4 | |
111 | #define CC_DSTBRSTLEN_SHFT 18 | |
112 | #define CC_SRCBRSTSIZE_SHFT 1 | |
113 | #define CC_DSTBRSTSIZE_SHFT 15 | |
114 | #define CC_SRCCCTRL_SHFT 11 | |
115 | #define CC_SRCCCTRL_MASK 0x7 | |
116 | #define CC_DSTCCTRL_SHFT 25 | |
117 | #define CC_DRCCCTRL_MASK 0x7 | |
118 | #define CC_SWAP_SHFT 28 | |
119 | ||
120 | #define _LC0 0x40c | |
121 | #define LC0(n) (_LC0 + (n)*0x20) | |
122 | ||
123 | #define _LC1 0x410 | |
124 | #define LC1(n) (_LC1 + (n)*0x20) | |
125 | ||
126 | #define DBGSTATUS 0xd00 | |
127 | #define DBG_BUSY (1 << 0) | |
128 | ||
129 | #define DBGCMD 0xd04 | |
130 | #define DBGINST0 0xd08 | |
131 | #define DBGINST1 0xd0c | |
132 | ||
133 | #define CR0 0xe00 | |
134 | #define CR1 0xe04 | |
135 | #define CR2 0xe08 | |
136 | #define CR3 0xe0c | |
137 | #define CR4 0xe10 | |
138 | #define CRD 0xe14 | |
139 | ||
140 | #define PERIPH_ID 0xfe0 | |
3ecf51a4 BK |
141 | #define PERIPH_REV_SHIFT 20 |
142 | #define PERIPH_REV_MASK 0xf | |
143 | #define PERIPH_REV_R0P0 0 | |
144 | #define PERIPH_REV_R1P0 1 | |
145 | #define PERIPH_REV_R1P1 2 | |
b7d861d9 BK |
146 | |
147 | #define CR0_PERIPH_REQ_SET (1 << 0) | |
148 | #define CR0_BOOT_EN_SET (1 << 1) | |
149 | #define CR0_BOOT_MAN_NS (1 << 2) | |
150 | #define CR0_NUM_CHANS_SHIFT 4 | |
151 | #define CR0_NUM_CHANS_MASK 0x7 | |
152 | #define CR0_NUM_PERIPH_SHIFT 12 | |
153 | #define CR0_NUM_PERIPH_MASK 0x1f | |
154 | #define CR0_NUM_EVENTS_SHIFT 17 | |
155 | #define CR0_NUM_EVENTS_MASK 0x1f | |
156 | ||
157 | #define CR1_ICACHE_LEN_SHIFT 0 | |
158 | #define CR1_ICACHE_LEN_MASK 0x7 | |
159 | #define CR1_NUM_ICACHELINES_SHIFT 4 | |
160 | #define CR1_NUM_ICACHELINES_MASK 0xf | |
161 | ||
162 | #define CRD_DATA_WIDTH_SHIFT 0 | |
163 | #define CRD_DATA_WIDTH_MASK 0x7 | |
164 | #define CRD_WR_CAP_SHIFT 4 | |
165 | #define CRD_WR_CAP_MASK 0x7 | |
166 | #define CRD_WR_Q_DEP_SHIFT 8 | |
167 | #define CRD_WR_Q_DEP_MASK 0xf | |
168 | #define CRD_RD_CAP_SHIFT 12 | |
169 | #define CRD_RD_CAP_MASK 0x7 | |
170 | #define CRD_RD_Q_DEP_SHIFT 16 | |
171 | #define CRD_RD_Q_DEP_MASK 0xf | |
172 | #define CRD_DATA_BUFF_SHIFT 20 | |
173 | #define CRD_DATA_BUFF_MASK 0x3ff | |
174 | ||
175 | #define PART 0x330 | |
176 | #define DESIGNER 0x41 | |
177 | #define REVISION 0x0 | |
178 | #define INTEG_CFG 0x0 | |
179 | #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) | |
180 | ||
b7d861d9 BK |
181 | #define PL330_STATE_STOPPED (1 << 0) |
182 | #define PL330_STATE_EXECUTING (1 << 1) | |
183 | #define PL330_STATE_WFE (1 << 2) | |
184 | #define PL330_STATE_FAULTING (1 << 3) | |
185 | #define PL330_STATE_COMPLETING (1 << 4) | |
186 | #define PL330_STATE_WFP (1 << 5) | |
187 | #define PL330_STATE_KILLING (1 << 6) | |
188 | #define PL330_STATE_FAULT_COMPLETING (1 << 7) | |
189 | #define PL330_STATE_CACHEMISS (1 << 8) | |
190 | #define PL330_STATE_UPDTPC (1 << 9) | |
191 | #define PL330_STATE_ATBARRIER (1 << 10) | |
192 | #define PL330_STATE_QUEUEBUSY (1 << 11) | |
193 | #define PL330_STATE_INVALID (1 << 15) | |
194 | ||
195 | #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ | |
196 | | PL330_STATE_WFE | PL330_STATE_FAULTING) | |
197 | ||
198 | #define CMD_DMAADDH 0x54 | |
199 | #define CMD_DMAEND 0x00 | |
200 | #define CMD_DMAFLUSHP 0x35 | |
201 | #define CMD_DMAGO 0xa0 | |
202 | #define CMD_DMALD 0x04 | |
203 | #define CMD_DMALDP 0x25 | |
204 | #define CMD_DMALP 0x20 | |
205 | #define CMD_DMALPEND 0x28 | |
206 | #define CMD_DMAKILL 0x01 | |
207 | #define CMD_DMAMOV 0xbc | |
208 | #define CMD_DMANOP 0x18 | |
209 | #define CMD_DMARMB 0x12 | |
210 | #define CMD_DMASEV 0x34 | |
211 | #define CMD_DMAST 0x08 | |
212 | #define CMD_DMASTP 0x29 | |
213 | #define CMD_DMASTZ 0x0c | |
214 | #define CMD_DMAWFE 0x36 | |
215 | #define CMD_DMAWFP 0x30 | |
216 | #define CMD_DMAWMB 0x13 | |
217 | ||
218 | #define SZ_DMAADDH 3 | |
219 | #define SZ_DMAEND 1 | |
220 | #define SZ_DMAFLUSHP 2 | |
221 | #define SZ_DMALD 1 | |
222 | #define SZ_DMALDP 2 | |
223 | #define SZ_DMALP 2 | |
224 | #define SZ_DMALPEND 2 | |
225 | #define SZ_DMAKILL 1 | |
226 | #define SZ_DMAMOV 6 | |
227 | #define SZ_DMANOP 1 | |
228 | #define SZ_DMARMB 1 | |
229 | #define SZ_DMASEV 2 | |
230 | #define SZ_DMAST 1 | |
231 | #define SZ_DMASTP 2 | |
232 | #define SZ_DMASTZ 1 | |
233 | #define SZ_DMAWFE 2 | |
234 | #define SZ_DMAWFP 2 | |
235 | #define SZ_DMAWMB 1 | |
236 | #define SZ_DMAGO 6 | |
237 | ||
238 | #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) | |
239 | #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) | |
240 | ||
241 | #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) | |
242 | #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) | |
243 | ||
244 | /* | |
245 | * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req | |
246 | * at 1byte/burst for P<->M and M<->M respectively. | |
247 | * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req | |
248 | * should be enough for P<->M and M<->M respectively. | |
249 | */ | |
250 | #define MCODE_BUFF_PER_REQ 256 | |
251 | ||
b7d861d9 BK |
252 | /* Use this _only_ to wait on transient states */ |
253 | #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); | |
254 | ||
255 | #ifdef PL330_DEBUG_MCGEN | |
256 | static unsigned cmd_line; | |
257 | #define PL330_DBGCMD_DUMP(off, x...) do { \ | |
258 | printk("%x:", cmd_line); \ | |
259 | printk(x); \ | |
260 | cmd_line += off; \ | |
261 | } while (0) | |
262 | #define PL330_DBGMC_START(addr) (cmd_line = addr) | |
263 | #else | |
264 | #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) | |
265 | #define PL330_DBGMC_START(addr) do {} while (0) | |
266 | #endif | |
267 | ||
268 | /* The number of default descriptors */ | |
d2ebfb33 | 269 | |
b3040e40 JB |
270 | #define NR_DEFAULT_DESC 16 |
271 | ||
ae43b328 KK |
272 | /* Delay for runtime PM autosuspend, ms */ |
273 | #define PL330_AUTOSUSPEND_DELAY 20 | |
274 | ||
b7d861d9 BK |
275 | /* Populated by the PL330 core driver for DMA API driver's info */ |
276 | struct pl330_config { | |
277 | u32 periph_id; | |
b7d861d9 BK |
278 | #define DMAC_MODE_NS (1 << 0) |
279 | unsigned int mode; | |
280 | unsigned int data_bus_width:10; /* In number of bits */ | |
1f0a5cbf | 281 | unsigned int data_buf_dep:11; |
b7d861d9 BK |
282 | unsigned int num_chan:4; |
283 | unsigned int num_peri:6; | |
284 | u32 peri_ns; | |
285 | unsigned int num_events:6; | |
286 | u32 irq_ns; | |
287 | }; | |
288 | ||
b7d861d9 BK |
289 | /** |
290 | * Request Configuration. | |
291 | * The PL330 core does not modify this and uses the last | |
292 | * working configuration if the request doesn't provide any. | |
293 | * | |
294 | * The Client may want to provide this info only for the | |
295 | * first request and a request with new settings. | |
296 | */ | |
297 | struct pl330_reqcfg { | |
298 | /* Address Incrementing */ | |
299 | unsigned dst_inc:1; | |
300 | unsigned src_inc:1; | |
301 | ||
302 | /* | |
303 | * For now, the SRC & DST protection levels | |
304 | * and burst size/length are assumed same. | |
305 | */ | |
306 | bool nonsecure; | |
307 | bool privileged; | |
308 | bool insnaccess; | |
309 | unsigned brst_len:5; | |
310 | unsigned brst_size:3; /* in power of 2 */ | |
311 | ||
f0564c7e LPC |
312 | enum pl330_cachectrl dcctl; |
313 | enum pl330_cachectrl scctl; | |
b7d861d9 | 314 | enum pl330_byteswap swap; |
3ecf51a4 | 315 | struct pl330_config *pcfg; |
b7d861d9 BK |
316 | }; |
317 | ||
318 | /* | |
319 | * One cycle of DMAC operation. | |
320 | * There may be more than one xfer in a request. | |
321 | */ | |
322 | struct pl330_xfer { | |
323 | u32 src_addr; | |
324 | u32 dst_addr; | |
325 | /* Size to xfer */ | |
326 | u32 bytes; | |
b7d861d9 BK |
327 | }; |
328 | ||
329 | /* The xfer callbacks are made with one of these arguments. */ | |
330 | enum pl330_op_err { | |
331 | /* The all xfers in the request were success. */ | |
332 | PL330_ERR_NONE, | |
333 | /* If req aborted due to global error. */ | |
334 | PL330_ERR_ABORT, | |
335 | /* If req failed due to problem with Channel. */ | |
336 | PL330_ERR_FAIL, | |
337 | }; | |
338 | ||
b7d861d9 BK |
339 | enum dmamov_dst { |
340 | SAR = 0, | |
341 | CCR, | |
342 | DAR, | |
343 | }; | |
344 | ||
345 | enum pl330_dst { | |
346 | SRC = 0, | |
347 | DST, | |
348 | }; | |
349 | ||
350 | enum pl330_cond { | |
351 | SINGLE, | |
352 | BURST, | |
353 | ALWAYS, | |
354 | }; | |
355 | ||
9dc5a315 LPC |
356 | struct dma_pl330_desc; |
357 | ||
b7d861d9 BK |
358 | struct _pl330_req { |
359 | u32 mc_bus; | |
360 | void *mc_cpu; | |
9dc5a315 | 361 | struct dma_pl330_desc *desc; |
b7d861d9 BK |
362 | }; |
363 | ||
364 | /* ToBeDone for tasklet */ | |
365 | struct _pl330_tbd { | |
366 | bool reset_dmac; | |
367 | bool reset_mngr; | |
368 | u8 reset_chan; | |
369 | }; | |
370 | ||
371 | /* A DMAC Thread */ | |
372 | struct pl330_thread { | |
373 | u8 id; | |
374 | int ev; | |
375 | /* If the channel is not yet acquired by any client */ | |
376 | bool free; | |
377 | /* Parent DMAC */ | |
378 | struct pl330_dmac *dmac; | |
379 | /* Only two at a time */ | |
380 | struct _pl330_req req[2]; | |
381 | /* Index of the last enqueued request */ | |
382 | unsigned lstenq; | |
383 | /* Index of the last submitted request or -1 if the DMA is stopped */ | |
384 | int req_running; | |
385 | }; | |
386 | ||
387 | enum pl330_dmac_state { | |
388 | UNINIT, | |
389 | INIT, | |
390 | DYING, | |
391 | }; | |
392 | ||
b3040e40 JB |
393 | enum desc_status { |
394 | /* In the DMAC pool */ | |
395 | FREE, | |
396 | /* | |
d73111c6 | 397 | * Allocated to some channel during prep_xxx |
b3040e40 JB |
398 | * Also may be sitting on the work_list. |
399 | */ | |
400 | PREP, | |
401 | /* | |
402 | * Sitting on the work_list and already submitted | |
403 | * to the PL330 core. Not more than two descriptors | |
404 | * of a channel can be BUSY at any time. | |
405 | */ | |
406 | BUSY, | |
407 | /* | |
408 | * Sitting on the channel work_list but xfer done | |
409 | * by PL330 core | |
410 | */ | |
411 | DONE, | |
412 | }; | |
413 | ||
414 | struct dma_pl330_chan { | |
415 | /* Schedule desc completion */ | |
416 | struct tasklet_struct task; | |
417 | ||
418 | /* DMA-Engine Channel */ | |
419 | struct dma_chan chan; | |
420 | ||
04abf5da LPC |
421 | /* List of submitted descriptors */ |
422 | struct list_head submitted_list; | |
423 | /* List of issued descriptors */ | |
b3040e40 | 424 | struct list_head work_list; |
39ff8613 LPC |
425 | /* List of completed descriptors */ |
426 | struct list_head completed_list; | |
b3040e40 JB |
427 | |
428 | /* Pointer to the DMAC that manages this channel, | |
429 | * NULL if the channel is available to be acquired. | |
430 | * As the parent, this DMAC also provides descriptors | |
431 | * to the channel. | |
432 | */ | |
f6f2421c | 433 | struct pl330_dmac *dmac; |
b3040e40 JB |
434 | |
435 | /* To protect channel manipulation */ | |
436 | spinlock_t lock; | |
437 | ||
65ad6060 LPC |
438 | /* |
439 | * Hardware channel thread of PL330 DMAC. NULL if the channel is | |
440 | * available. | |
b3040e40 | 441 | */ |
65ad6060 | 442 | struct pl330_thread *thread; |
1b9bb715 BK |
443 | |
444 | /* For D-to-M and M-to-D channels */ | |
445 | int burst_sz; /* the peripheral fifo width */ | |
1d0c1d60 | 446 | int burst_len; /* the number of burst */ |
4d6d74e2 RM |
447 | phys_addr_t fifo_addr; |
448 | /* DMA-mapped view of the FIFO; may differ if an IOMMU is present */ | |
449 | dma_addr_t fifo_dma; | |
450 | enum dma_data_direction dir; | |
445897cb | 451 | struct dma_slave_config slave_config; |
42bc9cf4 BK |
452 | |
453 | /* for cyclic capability */ | |
454 | bool cyclic; | |
5c9e6c2b MS |
455 | |
456 | /* for runtime pm tracking */ | |
457 | bool active; | |
b3040e40 JB |
458 | }; |
459 | ||
f6f2421c | 460 | struct pl330_dmac { |
b3040e40 JB |
461 | /* DMA-Engine Device */ |
462 | struct dma_device ddma; | |
463 | ||
b714b84e LPC |
464 | /* Holds info about sg limitations */ |
465 | struct device_dma_parameters dma_parms; | |
466 | ||
b3040e40 JB |
467 | /* Pool of descriptors available for the DMAC's channels */ |
468 | struct list_head desc_pool; | |
469 | /* To protect desc_pool manipulation */ | |
470 | spinlock_t pool_lock; | |
471 | ||
f6f2421c LPC |
472 | /* Size of MicroCode buffers for each channel. */ |
473 | unsigned mcbufsz; | |
474 | /* ioremap'ed address of PL330 registers. */ | |
475 | void __iomem *base; | |
476 | /* Populated by the PL330 core driver during pl330_add */ | |
477 | struct pl330_config pcfg; | |
478 | ||
479 | spinlock_t lock; | |
480 | /* Maximum possible events/irqs */ | |
481 | int events[32]; | |
482 | /* BUS address of MicroCode buffer */ | |
483 | dma_addr_t mcode_bus; | |
484 | /* CPU address of MicroCode buffer */ | |
485 | void *mcode_cpu; | |
486 | /* List of all Channel threads */ | |
487 | struct pl330_thread *channels; | |
488 | /* Pointer to the MANAGER thread */ | |
489 | struct pl330_thread *manager; | |
490 | /* To handle bad news in interrupt */ | |
491 | struct tasklet_struct tasks; | |
492 | struct _pl330_tbd dmac_tbd; | |
493 | /* State of DMAC operation */ | |
494 | enum pl330_dmac_state state; | |
495 | /* Holds list of reqs with due callbacks */ | |
496 | struct list_head req_done; | |
497 | ||
b3040e40 | 498 | /* Peripheral channels connected to this DMAC */ |
70cbb163 | 499 | unsigned int num_peripherals; |
4e0e6109 | 500 | struct dma_pl330_chan *peripherals; /* keep at end */ |
271e1b86 AK |
501 | int quirks; |
502 | }; | |
503 | ||
504 | static struct pl330_of_quirks { | |
505 | char *quirk; | |
506 | int id; | |
507 | } of_quirks[] = { | |
508 | { | |
509 | .quirk = "arm,pl330-broken-no-flushp", | |
510 | .id = PL330_QUIRK_BROKEN_NO_FLUSHP, | |
511 | } | |
b3040e40 JB |
512 | }; |
513 | ||
514 | struct dma_pl330_desc { | |
515 | /* To attach to a queue as child */ | |
516 | struct list_head node; | |
517 | ||
518 | /* Descriptor for the DMA Engine API */ | |
519 | struct dma_async_tx_descriptor txd; | |
520 | ||
521 | /* Xfer for PL330 core */ | |
522 | struct pl330_xfer px; | |
523 | ||
524 | struct pl330_reqcfg rqcfg; | |
b3040e40 JB |
525 | |
526 | enum desc_status status; | |
527 | ||
aee4d1fa RB |
528 | int bytes_requested; |
529 | bool last; | |
530 | ||
b3040e40 JB |
531 | /* The channel which currently holds this desc */ |
532 | struct dma_pl330_chan *pchan; | |
9dc5a315 LPC |
533 | |
534 | enum dma_transfer_direction rqtype; | |
535 | /* Index of peripheral for the xfer. */ | |
536 | unsigned peri:5; | |
537 | /* Hook to attach to DMAC's list of reqs with due callback */ | |
538 | struct list_head rqd; | |
539 | }; | |
540 | ||
541 | struct _xfer_spec { | |
542 | u32 ccr; | |
543 | struct dma_pl330_desc *desc; | |
b3040e40 JB |
544 | }; |
545 | ||
445897cb VK |
546 | static int pl330_config_write(struct dma_chan *chan, |
547 | struct dma_slave_config *slave_config, | |
548 | enum dma_transfer_direction direction); | |
549 | ||
b7d861d9 BK |
550 | static inline bool _queue_full(struct pl330_thread *thrd) |
551 | { | |
8ed30a14 | 552 | return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL; |
b7d861d9 BK |
553 | } |
554 | ||
555 | static inline bool is_manager(struct pl330_thread *thrd) | |
556 | { | |
fbbcd9be | 557 | return thrd->dmac->manager == thrd; |
b7d861d9 BK |
558 | } |
559 | ||
560 | /* If manager of the thread is in Non-Secure mode */ | |
561 | static inline bool _manager_ns(struct pl330_thread *thrd) | |
562 | { | |
f6f2421c | 563 | return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false; |
b7d861d9 BK |
564 | } |
565 | ||
3ecf51a4 BK |
566 | static inline u32 get_revision(u32 periph_id) |
567 | { | |
568 | return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; | |
569 | } | |
570 | ||
b7d861d9 BK |
571 | static inline u32 _emit_END(unsigned dry_run, u8 buf[]) |
572 | { | |
573 | if (dry_run) | |
574 | return SZ_DMAEND; | |
575 | ||
576 | buf[0] = CMD_DMAEND; | |
577 | ||
578 | PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); | |
579 | ||
580 | return SZ_DMAEND; | |
581 | } | |
582 | ||
583 | static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) | |
584 | { | |
585 | if (dry_run) | |
586 | return SZ_DMAFLUSHP; | |
587 | ||
588 | buf[0] = CMD_DMAFLUSHP; | |
589 | ||
590 | peri &= 0x1f; | |
591 | peri <<= 3; | |
592 | buf[1] = peri; | |
593 | ||
594 | PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); | |
595 | ||
596 | return SZ_DMAFLUSHP; | |
597 | } | |
598 | ||
599 | static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
600 | { | |
601 | if (dry_run) | |
602 | return SZ_DMALD; | |
603 | ||
604 | buf[0] = CMD_DMALD; | |
605 | ||
606 | if (cond == SINGLE) | |
607 | buf[0] |= (0 << 1) | (1 << 0); | |
608 | else if (cond == BURST) | |
609 | buf[0] |= (1 << 1) | (1 << 0); | |
610 | ||
611 | PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", | |
612 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
613 | ||
614 | return SZ_DMALD; | |
615 | } | |
616 | ||
617 | static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], | |
618 | enum pl330_cond cond, u8 peri) | |
619 | { | |
620 | if (dry_run) | |
621 | return SZ_DMALDP; | |
622 | ||
623 | buf[0] = CMD_DMALDP; | |
624 | ||
625 | if (cond == BURST) | |
626 | buf[0] |= (1 << 1); | |
627 | ||
628 | peri &= 0x1f; | |
629 | peri <<= 3; | |
630 | buf[1] = peri; | |
631 | ||
632 | PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", | |
633 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
634 | ||
635 | return SZ_DMALDP; | |
636 | } | |
637 | ||
638 | static inline u32 _emit_LP(unsigned dry_run, u8 buf[], | |
639 | unsigned loop, u8 cnt) | |
640 | { | |
641 | if (dry_run) | |
642 | return SZ_DMALP; | |
643 | ||
644 | buf[0] = CMD_DMALP; | |
645 | ||
646 | if (loop) | |
647 | buf[0] |= (1 << 1); | |
648 | ||
649 | cnt--; /* DMAC increments by 1 internally */ | |
650 | buf[1] = cnt; | |
651 | ||
652 | PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); | |
653 | ||
654 | return SZ_DMALP; | |
655 | } | |
656 | ||
657 | struct _arg_LPEND { | |
658 | enum pl330_cond cond; | |
659 | bool forever; | |
660 | unsigned loop; | |
661 | u8 bjump; | |
662 | }; | |
663 | ||
664 | static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], | |
665 | const struct _arg_LPEND *arg) | |
666 | { | |
667 | enum pl330_cond cond = arg->cond; | |
668 | bool forever = arg->forever; | |
669 | unsigned loop = arg->loop; | |
670 | u8 bjump = arg->bjump; | |
671 | ||
672 | if (dry_run) | |
673 | return SZ_DMALPEND; | |
674 | ||
675 | buf[0] = CMD_DMALPEND; | |
676 | ||
677 | if (loop) | |
678 | buf[0] |= (1 << 2); | |
679 | ||
680 | if (!forever) | |
681 | buf[0] |= (1 << 4); | |
682 | ||
683 | if (cond == SINGLE) | |
684 | buf[0] |= (0 << 1) | (1 << 0); | |
685 | else if (cond == BURST) | |
686 | buf[0] |= (1 << 1) | (1 << 0); | |
687 | ||
688 | buf[1] = bjump; | |
689 | ||
690 | PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", | |
691 | forever ? "FE" : "END", | |
692 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), | |
693 | loop ? '1' : '0', | |
694 | bjump); | |
695 | ||
696 | return SZ_DMALPEND; | |
697 | } | |
698 | ||
699 | static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) | |
700 | { | |
701 | if (dry_run) | |
702 | return SZ_DMAKILL; | |
703 | ||
704 | buf[0] = CMD_DMAKILL; | |
705 | ||
706 | return SZ_DMAKILL; | |
707 | } | |
708 | ||
709 | static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], | |
710 | enum dmamov_dst dst, u32 val) | |
711 | { | |
712 | if (dry_run) | |
713 | return SZ_DMAMOV; | |
714 | ||
715 | buf[0] = CMD_DMAMOV; | |
716 | buf[1] = dst; | |
d07c9e1e VM |
717 | buf[2] = val; |
718 | buf[3] = val >> 8; | |
719 | buf[4] = val >> 16; | |
720 | buf[5] = val >> 24; | |
b7d861d9 BK |
721 | |
722 | PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", | |
723 | dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); | |
724 | ||
725 | return SZ_DMAMOV; | |
726 | } | |
727 | ||
b7d861d9 BK |
728 | static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) |
729 | { | |
730 | if (dry_run) | |
731 | return SZ_DMARMB; | |
732 | ||
733 | buf[0] = CMD_DMARMB; | |
734 | ||
735 | PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); | |
736 | ||
737 | return SZ_DMARMB; | |
738 | } | |
739 | ||
740 | static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) | |
741 | { | |
742 | if (dry_run) | |
743 | return SZ_DMASEV; | |
744 | ||
745 | buf[0] = CMD_DMASEV; | |
746 | ||
747 | ev &= 0x1f; | |
748 | ev <<= 3; | |
749 | buf[1] = ev; | |
750 | ||
751 | PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); | |
752 | ||
753 | return SZ_DMASEV; | |
754 | } | |
755 | ||
756 | static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) | |
757 | { | |
758 | if (dry_run) | |
759 | return SZ_DMAST; | |
760 | ||
761 | buf[0] = CMD_DMAST; | |
762 | ||
763 | if (cond == SINGLE) | |
764 | buf[0] |= (0 << 1) | (1 << 0); | |
765 | else if (cond == BURST) | |
766 | buf[0] |= (1 << 1) | (1 << 0); | |
767 | ||
768 | PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", | |
769 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); | |
770 | ||
771 | return SZ_DMAST; | |
772 | } | |
773 | ||
774 | static inline u32 _emit_STP(unsigned dry_run, u8 buf[], | |
775 | enum pl330_cond cond, u8 peri) | |
776 | { | |
777 | if (dry_run) | |
778 | return SZ_DMASTP; | |
779 | ||
780 | buf[0] = CMD_DMASTP; | |
781 | ||
782 | if (cond == BURST) | |
783 | buf[0] |= (1 << 1); | |
784 | ||
785 | peri &= 0x1f; | |
786 | peri <<= 3; | |
787 | buf[1] = peri; | |
788 | ||
789 | PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", | |
790 | cond == SINGLE ? 'S' : 'B', peri >> 3); | |
791 | ||
792 | return SZ_DMASTP; | |
793 | } | |
794 | ||
b7d861d9 BK |
795 | static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], |
796 | enum pl330_cond cond, u8 peri) | |
797 | { | |
798 | if (dry_run) | |
799 | return SZ_DMAWFP; | |
800 | ||
801 | buf[0] = CMD_DMAWFP; | |
802 | ||
803 | if (cond == SINGLE) | |
804 | buf[0] |= (0 << 1) | (0 << 0); | |
805 | else if (cond == BURST) | |
806 | buf[0] |= (1 << 1) | (0 << 0); | |
807 | else | |
808 | buf[0] |= (0 << 1) | (1 << 0); | |
809 | ||
810 | peri &= 0x1f; | |
811 | peri <<= 3; | |
812 | buf[1] = peri; | |
813 | ||
814 | PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", | |
815 | cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); | |
816 | ||
817 | return SZ_DMAWFP; | |
818 | } | |
819 | ||
820 | static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) | |
821 | { | |
822 | if (dry_run) | |
823 | return SZ_DMAWMB; | |
824 | ||
825 | buf[0] = CMD_DMAWMB; | |
826 | ||
827 | PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); | |
828 | ||
829 | return SZ_DMAWMB; | |
830 | } | |
831 | ||
832 | struct _arg_GO { | |
833 | u8 chan; | |
834 | u32 addr; | |
835 | unsigned ns; | |
836 | }; | |
837 | ||
838 | static inline u32 _emit_GO(unsigned dry_run, u8 buf[], | |
839 | const struct _arg_GO *arg) | |
840 | { | |
841 | u8 chan = arg->chan; | |
842 | u32 addr = arg->addr; | |
843 | unsigned ns = arg->ns; | |
844 | ||
845 | if (dry_run) | |
846 | return SZ_DMAGO; | |
847 | ||
848 | buf[0] = CMD_DMAGO; | |
849 | buf[0] |= (ns << 1); | |
b7d861d9 | 850 | buf[1] = chan & 0x7; |
d07c9e1e VM |
851 | buf[2] = addr; |
852 | buf[3] = addr >> 8; | |
853 | buf[4] = addr >> 16; | |
854 | buf[5] = addr >> 24; | |
b7d861d9 BK |
855 | |
856 | return SZ_DMAGO; | |
857 | } | |
858 | ||
859 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
860 | ||
861 | /* Returns Time-Out */ | |
862 | static bool _until_dmac_idle(struct pl330_thread *thrd) | |
863 | { | |
f6f2421c | 864 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
865 | unsigned long loops = msecs_to_loops(5); |
866 | ||
867 | do { | |
868 | /* Until Manager is Idle */ | |
869 | if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) | |
870 | break; | |
871 | ||
872 | cpu_relax(); | |
873 | } while (--loops); | |
874 | ||
875 | if (!loops) | |
876 | return true; | |
877 | ||
878 | return false; | |
879 | } | |
880 | ||
881 | static inline void _execute_DBGINSN(struct pl330_thread *thrd, | |
882 | u8 insn[], bool as_manager) | |
883 | { | |
f6f2421c | 884 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
885 | u32 val; |
886 | ||
887 | val = (insn[0] << 16) | (insn[1] << 24); | |
888 | if (!as_manager) { | |
889 | val |= (1 << 0); | |
890 | val |= (thrd->id << 8); /* Channel Number */ | |
891 | } | |
892 | writel(val, regs + DBGINST0); | |
893 | ||
3a2307f7 | 894 | val = le32_to_cpu(*((__le32 *)&insn[2])); |
b7d861d9 BK |
895 | writel(val, regs + DBGINST1); |
896 | ||
897 | /* If timed out due to halted state-machine */ | |
898 | if (_until_dmac_idle(thrd)) { | |
f6f2421c | 899 | dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n"); |
b7d861d9 BK |
900 | return; |
901 | } | |
902 | ||
903 | /* Get going */ | |
904 | writel(0, regs + DBGCMD); | |
905 | } | |
906 | ||
b7d861d9 BK |
907 | static inline u32 _state(struct pl330_thread *thrd) |
908 | { | |
f6f2421c | 909 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
910 | u32 val; |
911 | ||
912 | if (is_manager(thrd)) | |
913 | val = readl(regs + DS) & 0xf; | |
914 | else | |
915 | val = readl(regs + CS(thrd->id)) & 0xf; | |
916 | ||
917 | switch (val) { | |
918 | case DS_ST_STOP: | |
919 | return PL330_STATE_STOPPED; | |
920 | case DS_ST_EXEC: | |
921 | return PL330_STATE_EXECUTING; | |
922 | case DS_ST_CMISS: | |
923 | return PL330_STATE_CACHEMISS; | |
924 | case DS_ST_UPDTPC: | |
925 | return PL330_STATE_UPDTPC; | |
926 | case DS_ST_WFE: | |
927 | return PL330_STATE_WFE; | |
928 | case DS_ST_FAULT: | |
929 | return PL330_STATE_FAULTING; | |
930 | case DS_ST_ATBRR: | |
931 | if (is_manager(thrd)) | |
932 | return PL330_STATE_INVALID; | |
933 | else | |
934 | return PL330_STATE_ATBARRIER; | |
935 | case DS_ST_QBUSY: | |
936 | if (is_manager(thrd)) | |
937 | return PL330_STATE_INVALID; | |
938 | else | |
939 | return PL330_STATE_QUEUEBUSY; | |
940 | case DS_ST_WFP: | |
941 | if (is_manager(thrd)) | |
942 | return PL330_STATE_INVALID; | |
943 | else | |
944 | return PL330_STATE_WFP; | |
945 | case DS_ST_KILL: | |
946 | if (is_manager(thrd)) | |
947 | return PL330_STATE_INVALID; | |
948 | else | |
949 | return PL330_STATE_KILLING; | |
950 | case DS_ST_CMPLT: | |
951 | if (is_manager(thrd)) | |
952 | return PL330_STATE_INVALID; | |
953 | else | |
954 | return PL330_STATE_COMPLETING; | |
955 | case DS_ST_FLTCMP: | |
956 | if (is_manager(thrd)) | |
957 | return PL330_STATE_INVALID; | |
958 | else | |
959 | return PL330_STATE_FAULT_COMPLETING; | |
960 | default: | |
961 | return PL330_STATE_INVALID; | |
962 | } | |
963 | } | |
964 | ||
965 | static void _stop(struct pl330_thread *thrd) | |
966 | { | |
f6f2421c | 967 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 BK |
968 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; |
969 | ||
970 | if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) | |
971 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
972 | ||
973 | /* Return if nothing needs to be done */ | |
974 | if (_state(thrd) == PL330_STATE_COMPLETING | |
975 | || _state(thrd) == PL330_STATE_KILLING | |
976 | || _state(thrd) == PL330_STATE_STOPPED) | |
977 | return; | |
978 | ||
979 | _emit_KILL(0, insn); | |
980 | ||
981 | /* Stop generating interrupts for SEV */ | |
982 | writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); | |
983 | ||
984 | _execute_DBGINSN(thrd, insn, is_manager(thrd)); | |
985 | } | |
986 | ||
987 | /* Start doing req 'idx' of thread 'thrd' */ | |
988 | static bool _trigger(struct pl330_thread *thrd) | |
989 | { | |
f6f2421c | 990 | void __iomem *regs = thrd->dmac->base; |
b7d861d9 | 991 | struct _pl330_req *req; |
9dc5a315 | 992 | struct dma_pl330_desc *desc; |
b7d861d9 BK |
993 | struct _arg_GO go; |
994 | unsigned ns; | |
995 | u8 insn[6] = {0, 0, 0, 0, 0, 0}; | |
996 | int idx; | |
997 | ||
998 | /* Return if already ACTIVE */ | |
999 | if (_state(thrd) != PL330_STATE_STOPPED) | |
1000 | return true; | |
1001 | ||
1002 | idx = 1 - thrd->lstenq; | |
8ed30a14 | 1003 | if (thrd->req[idx].desc != NULL) { |
b7d861d9 | 1004 | req = &thrd->req[idx]; |
8ed30a14 | 1005 | } else { |
b7d861d9 | 1006 | idx = thrd->lstenq; |
8ed30a14 | 1007 | if (thrd->req[idx].desc != NULL) |
b7d861d9 BK |
1008 | req = &thrd->req[idx]; |
1009 | else | |
1010 | req = NULL; | |
1011 | } | |
1012 | ||
1013 | /* Return if no request */ | |
8ed30a14 | 1014 | if (!req) |
b7d861d9 BK |
1015 | return true; |
1016 | ||
0091b9d6 AK |
1017 | /* Return if req is running */ |
1018 | if (idx == thrd->req_running) | |
1019 | return true; | |
1020 | ||
9dc5a315 | 1021 | desc = req->desc; |
b7d861d9 | 1022 | |
9dc5a315 | 1023 | ns = desc->rqcfg.nonsecure ? 1 : 0; |
b7d861d9 BK |
1024 | |
1025 | /* See 'Abort Sources' point-4 at Page 2-25 */ | |
1026 | if (_manager_ns(thrd) && !ns) | |
f6f2421c | 1027 | dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n", |
b7d861d9 BK |
1028 | __func__, __LINE__); |
1029 | ||
1030 | go.chan = thrd->id; | |
1031 | go.addr = req->mc_bus; | |
1032 | go.ns = ns; | |
1033 | _emit_GO(0, insn, &go); | |
1034 | ||
1035 | /* Set to generate interrupts for SEV */ | |
1036 | writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); | |
1037 | ||
1038 | /* Only manager can execute GO */ | |
1039 | _execute_DBGINSN(thrd, insn, true); | |
1040 | ||
1041 | thrd->req_running = idx; | |
1042 | ||
1043 | return true; | |
1044 | } | |
1045 | ||
1046 | static bool _start(struct pl330_thread *thrd) | |
1047 | { | |
1048 | switch (_state(thrd)) { | |
1049 | case PL330_STATE_FAULT_COMPLETING: | |
1050 | UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); | |
1051 | ||
1052 | if (_state(thrd) == PL330_STATE_KILLING) | |
1053 | UNTIL(thrd, PL330_STATE_STOPPED) | |
bbcb8755 | 1054 | /* fall through */ |
b7d861d9 BK |
1055 | |
1056 | case PL330_STATE_FAULTING: | |
1057 | _stop(thrd); | |
bbcb8755 | 1058 | /* fall through */ |
b7d861d9 BK |
1059 | |
1060 | case PL330_STATE_KILLING: | |
1061 | case PL330_STATE_COMPLETING: | |
1062 | UNTIL(thrd, PL330_STATE_STOPPED) | |
bbcb8755 | 1063 | /* fall through */ |
b7d861d9 BK |
1064 | |
1065 | case PL330_STATE_STOPPED: | |
1066 | return _trigger(thrd); | |
1067 | ||
1068 | case PL330_STATE_WFP: | |
1069 | case PL330_STATE_QUEUEBUSY: | |
1070 | case PL330_STATE_ATBARRIER: | |
1071 | case PL330_STATE_UPDTPC: | |
1072 | case PL330_STATE_CACHEMISS: | |
1073 | case PL330_STATE_EXECUTING: | |
1074 | return true; | |
1075 | ||
1076 | case PL330_STATE_WFE: /* For RESUME, nothing yet */ | |
1077 | default: | |
1078 | return false; | |
1079 | } | |
1080 | } | |
1081 | ||
1082 | static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], | |
1083 | const struct _xfer_spec *pxs, int cyc) | |
1084 | { | |
1085 | int off = 0; | |
9dc5a315 | 1086 | struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg; |
b7d861d9 | 1087 | |
3ecf51a4 BK |
1088 | /* check lock-up free version */ |
1089 | if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { | |
1090 | while (cyc--) { | |
1091 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1092 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1093 | } | |
1094 | } else { | |
1095 | while (cyc--) { | |
1096 | off += _emit_LD(dry_run, &buf[off], ALWAYS); | |
1097 | off += _emit_RMB(dry_run, &buf[off]); | |
1098 | off += _emit_ST(dry_run, &buf[off], ALWAYS); | |
1099 | off += _emit_WMB(dry_run, &buf[off]); | |
1100 | } | |
b7d861d9 BK |
1101 | } |
1102 | ||
1103 | return off; | |
1104 | } | |
1105 | ||
1d48745b FMH |
1106 | static u32 _emit_load(unsigned int dry_run, u8 buf[], |
1107 | enum pl330_cond cond, enum dma_transfer_direction direction, | |
1108 | u8 peri) | |
b7d861d9 BK |
1109 | { |
1110 | int off = 0; | |
848e9776 | 1111 | |
1d48745b FMH |
1112 | switch (direction) { |
1113 | case DMA_MEM_TO_MEM: | |
1114 | /* fall through */ | |
1115 | case DMA_MEM_TO_DEV: | |
1116 | off += _emit_LD(dry_run, &buf[off], cond); | |
1117 | break; | |
b7d861d9 | 1118 | |
1d48745b FMH |
1119 | case DMA_DEV_TO_MEM: |
1120 | if (cond == ALWAYS) { | |
1121 | off += _emit_LDP(dry_run, &buf[off], SINGLE, | |
1122 | peri); | |
1123 | off += _emit_LDP(dry_run, &buf[off], BURST, | |
1124 | peri); | |
1125 | } else { | |
1126 | off += _emit_LDP(dry_run, &buf[off], cond, | |
1127 | peri); | |
1128 | } | |
1129 | break; | |
271e1b86 | 1130 | |
1d48745b FMH |
1131 | default: |
1132 | /* this code should be unreachable */ | |
1133 | WARN_ON(1); | |
1134 | break; | |
b7d861d9 BK |
1135 | } |
1136 | ||
1137 | return off; | |
1138 | } | |
1139 | ||
1d48745b FMH |
1140 | static inline u32 _emit_store(unsigned int dry_run, u8 buf[], |
1141 | enum pl330_cond cond, enum dma_transfer_direction direction, | |
1142 | u8 peri) | |
1143 | { | |
1144 | int off = 0; | |
1145 | ||
1146 | switch (direction) { | |
1147 | case DMA_MEM_TO_MEM: | |
1148 | /* fall through */ | |
1149 | case DMA_DEV_TO_MEM: | |
1150 | off += _emit_ST(dry_run, &buf[off], cond); | |
1151 | break; | |
1152 | ||
1153 | case DMA_MEM_TO_DEV: | |
1154 | if (cond == ALWAYS) { | |
1155 | off += _emit_STP(dry_run, &buf[off], SINGLE, | |
1156 | peri); | |
1157 | off += _emit_STP(dry_run, &buf[off], BURST, | |
1158 | peri); | |
1159 | } else { | |
1160 | off += _emit_STP(dry_run, &buf[off], cond, | |
1161 | peri); | |
1162 | } | |
1163 | break; | |
1164 | ||
1165 | default: | |
1166 | /* this code should be unreachable */ | |
1167 | WARN_ON(1); | |
1168 | break; | |
1169 | } | |
1170 | ||
1171 | return off; | |
1172 | } | |
1173 | ||
1174 | static inline int _ldst_peripheral(struct pl330_dmac *pl330, | |
271e1b86 | 1175 | unsigned dry_run, u8 buf[], |
1d48745b FMH |
1176 | const struct _xfer_spec *pxs, int cyc, |
1177 | enum pl330_cond cond) | |
b7d861d9 BK |
1178 | { |
1179 | int off = 0; | |
848e9776 | 1180 | |
271e1b86 AK |
1181 | if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) |
1182 | cond = BURST; | |
b7d861d9 | 1183 | |
1d48745b FMH |
1184 | /* |
1185 | * do FLUSHP at beginning to clear any stale dma requests before the | |
1186 | * first WFP. | |
1187 | */ | |
1188 | if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)) | |
1189 | off += _emit_FLUSHP(dry_run, &buf[off], pxs->desc->peri); | |
b7d861d9 | 1190 | while (cyc--) { |
848e9776 | 1191 | off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri); |
1d48745b FMH |
1192 | off += _emit_load(dry_run, &buf[off], cond, pxs->desc->rqtype, |
1193 | pxs->desc->peri); | |
1194 | off += _emit_store(dry_run, &buf[off], cond, pxs->desc->rqtype, | |
1195 | pxs->desc->peri); | |
b7d861d9 BK |
1196 | } |
1197 | ||
1198 | return off; | |
1199 | } | |
1200 | ||
271e1b86 | 1201 | static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], |
b7d861d9 BK |
1202 | const struct _xfer_spec *pxs, int cyc) |
1203 | { | |
1204 | int off = 0; | |
1d48745b | 1205 | enum pl330_cond cond = BRST_LEN(pxs->ccr) > 1 ? BURST : SINGLE; |
b7d861d9 | 1206 | |
9dc5a315 | 1207 | switch (pxs->desc->rqtype) { |
585a9d0b | 1208 | case DMA_MEM_TO_DEV: |
1d48745b | 1209 | /* fall through */ |
585a9d0b | 1210 | case DMA_DEV_TO_MEM: |
1d48745b FMH |
1211 | off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, cyc, |
1212 | cond); | |
b7d861d9 | 1213 | break; |
1d48745b | 1214 | |
585a9d0b | 1215 | case DMA_MEM_TO_MEM: |
b7d861d9 BK |
1216 | off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); |
1217 | break; | |
1d48745b FMH |
1218 | |
1219 | default: | |
1220 | /* this code should be unreachable */ | |
1221 | WARN_ON(1); | |
1222 | break; | |
1223 | } | |
1224 | ||
1225 | return off; | |
1226 | } | |
1227 | ||
1228 | /* | |
1229 | * transfer dregs with single transfers to peripheral, or a reduced size burst | |
1230 | * for mem-to-mem. | |
1231 | */ | |
1232 | static int _dregs(struct pl330_dmac *pl330, unsigned int dry_run, u8 buf[], | |
1233 | const struct _xfer_spec *pxs, int transfer_length) | |
1234 | { | |
1235 | int off = 0; | |
1236 | int dregs_ccr; | |
1237 | ||
1238 | if (transfer_length == 0) | |
1239 | return off; | |
1240 | ||
1241 | switch (pxs->desc->rqtype) { | |
1242 | case DMA_MEM_TO_DEV: | |
1243 | /* fall through */ | |
1244 | case DMA_DEV_TO_MEM: | |
1245 | off += _ldst_peripheral(pl330, dry_run, &buf[off], pxs, | |
1246 | transfer_length, SINGLE); | |
1247 | break; | |
1248 | ||
1249 | case DMA_MEM_TO_MEM: | |
1250 | dregs_ccr = pxs->ccr; | |
1251 | dregs_ccr &= ~((0xf << CC_SRCBRSTLEN_SHFT) | | |
1252 | (0xf << CC_DSTBRSTLEN_SHFT)); | |
1253 | dregs_ccr |= (((transfer_length - 1) & 0xf) << | |
1254 | CC_SRCBRSTLEN_SHFT); | |
1255 | dregs_ccr |= (((transfer_length - 1) & 0xf) << | |
1256 | CC_DSTBRSTLEN_SHFT); | |
1257 | off += _emit_MOV(dry_run, &buf[off], CCR, dregs_ccr); | |
1258 | off += _ldst_memtomem(dry_run, &buf[off], pxs, 1); | |
1259 | break; | |
1260 | ||
b7d861d9 | 1261 | default: |
1d48745b FMH |
1262 | /* this code should be unreachable */ |
1263 | WARN_ON(1); | |
b7d861d9 BK |
1264 | break; |
1265 | } | |
1266 | ||
1267 | return off; | |
1268 | } | |
1269 | ||
1270 | /* Returns bytes consumed and updates bursts */ | |
271e1b86 | 1271 | static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], |
b7d861d9 BK |
1272 | unsigned long *bursts, const struct _xfer_spec *pxs) |
1273 | { | |
1274 | int cyc, cycmax, szlp, szlpend, szbrst, off; | |
1275 | unsigned lcnt0, lcnt1, ljmp0, ljmp1; | |
1276 | struct _arg_LPEND lpend; | |
1277 | ||
31495d60 | 1278 | if (*bursts == 1) |
848e9776 | 1279 | return _bursts(pl330, dry_run, buf, pxs, 1); |
31495d60 | 1280 | |
b7d861d9 BK |
1281 | /* Max iterations possible in DMALP is 256 */ |
1282 | if (*bursts >= 256*256) { | |
1283 | lcnt1 = 256; | |
1284 | lcnt0 = 256; | |
1285 | cyc = *bursts / lcnt1 / lcnt0; | |
1286 | } else if (*bursts > 256) { | |
1287 | lcnt1 = 256; | |
1288 | lcnt0 = *bursts / lcnt1; | |
1289 | cyc = 1; | |
1290 | } else { | |
1291 | lcnt1 = *bursts; | |
1292 | lcnt0 = 0; | |
1293 | cyc = 1; | |
1294 | } | |
1295 | ||
1296 | szlp = _emit_LP(1, buf, 0, 0); | |
271e1b86 | 1297 | szbrst = _bursts(pl330, 1, buf, pxs, 1); |
b7d861d9 BK |
1298 | |
1299 | lpend.cond = ALWAYS; | |
1300 | lpend.forever = false; | |
1301 | lpend.loop = 0; | |
1302 | lpend.bjump = 0; | |
1303 | szlpend = _emit_LPEND(1, buf, &lpend); | |
1304 | ||
1305 | if (lcnt0) { | |
1306 | szlp *= 2; | |
1307 | szlpend *= 2; | |
1308 | } | |
1309 | ||
1310 | /* | |
1311 | * Max bursts that we can unroll due to limit on the | |
1312 | * size of backward jump that can be encoded in DMALPEND | |
1313 | * which is 8-bits and hence 255 | |
1314 | */ | |
1315 | cycmax = (255 - (szlp + szlpend)) / szbrst; | |
1316 | ||
1317 | cyc = (cycmax < cyc) ? cycmax : cyc; | |
1318 | ||
1319 | off = 0; | |
1320 | ||
1321 | if (lcnt0) { | |
1322 | off += _emit_LP(dry_run, &buf[off], 0, lcnt0); | |
1323 | ljmp0 = off; | |
1324 | } | |
1325 | ||
1326 | off += _emit_LP(dry_run, &buf[off], 1, lcnt1); | |
1327 | ljmp1 = off; | |
1328 | ||
271e1b86 | 1329 | off += _bursts(pl330, dry_run, &buf[off], pxs, cyc); |
b7d861d9 BK |
1330 | |
1331 | lpend.cond = ALWAYS; | |
1332 | lpend.forever = false; | |
1333 | lpend.loop = 1; | |
1334 | lpend.bjump = off - ljmp1; | |
1335 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1336 | ||
1337 | if (lcnt0) { | |
1338 | lpend.cond = ALWAYS; | |
1339 | lpend.forever = false; | |
1340 | lpend.loop = 0; | |
1341 | lpend.bjump = off - ljmp0; | |
1342 | off += _emit_LPEND(dry_run, &buf[off], &lpend); | |
1343 | } | |
1344 | ||
1345 | *bursts = lcnt1 * cyc; | |
1346 | if (lcnt0) | |
1347 | *bursts *= lcnt0; | |
1348 | ||
1349 | return off; | |
1350 | } | |
1351 | ||
271e1b86 AK |
1352 | static inline int _setup_loops(struct pl330_dmac *pl330, |
1353 | unsigned dry_run, u8 buf[], | |
1354 | const struct _xfer_spec *pxs) | |
b7d861d9 | 1355 | { |
9dc5a315 | 1356 | struct pl330_xfer *x = &pxs->desc->px; |
b7d861d9 BK |
1357 | u32 ccr = pxs->ccr; |
1358 | unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); | |
1d48745b FMH |
1359 | int num_dregs = (x->bytes - BURST_TO_BYTE(bursts, ccr)) / |
1360 | BRST_SIZE(ccr); | |
b7d861d9 BK |
1361 | int off = 0; |
1362 | ||
1363 | while (bursts) { | |
1364 | c = bursts; | |
271e1b86 | 1365 | off += _loop(pl330, dry_run, &buf[off], &c, pxs); |
b7d861d9 BK |
1366 | bursts -= c; |
1367 | } | |
1d48745b | 1368 | off += _dregs(pl330, dry_run, &buf[off], pxs, num_dregs); |
b7d861d9 BK |
1369 | |
1370 | return off; | |
1371 | } | |
1372 | ||
271e1b86 AK |
1373 | static inline int _setup_xfer(struct pl330_dmac *pl330, |
1374 | unsigned dry_run, u8 buf[], | |
1375 | const struct _xfer_spec *pxs) | |
b7d861d9 | 1376 | { |
9dc5a315 | 1377 | struct pl330_xfer *x = &pxs->desc->px; |
b7d861d9 BK |
1378 | int off = 0; |
1379 | ||
1380 | /* DMAMOV SAR, x->src_addr */ | |
1381 | off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); | |
1382 | /* DMAMOV DAR, x->dst_addr */ | |
1383 | off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); | |
1384 | ||
1385 | /* Setup Loop(s) */ | |
271e1b86 | 1386 | off += _setup_loops(pl330, dry_run, &buf[off], pxs); |
b7d861d9 BK |
1387 | |
1388 | return off; | |
1389 | } | |
1390 | ||
1391 | /* | |
1392 | * A req is a sequence of one or more xfer units. | |
1393 | * Returns the number of bytes taken to setup the MC for the req. | |
1394 | */ | |
271e1b86 AK |
1395 | static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run, |
1396 | struct pl330_thread *thrd, unsigned index, | |
1397 | struct _xfer_spec *pxs) | |
b7d861d9 BK |
1398 | { |
1399 | struct _pl330_req *req = &thrd->req[index]; | |
b7d861d9 BK |
1400 | u8 *buf = req->mc_cpu; |
1401 | int off = 0; | |
1402 | ||
1403 | PL330_DBGMC_START(req->mc_bus); | |
1404 | ||
1405 | /* DMAMOV CCR, ccr */ | |
1406 | off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); | |
1407 | ||
271e1b86 | 1408 | off += _setup_xfer(pl330, dry_run, &buf[off], pxs); |
b7d861d9 BK |
1409 | |
1410 | /* DMASEV peripheral/event */ | |
1411 | off += _emit_SEV(dry_run, &buf[off], thrd->ev); | |
1412 | /* DMAEND */ | |
1413 | off += _emit_END(dry_run, &buf[off]); | |
1414 | ||
1415 | return off; | |
1416 | } | |
1417 | ||
1418 | static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) | |
1419 | { | |
1420 | u32 ccr = 0; | |
1421 | ||
1422 | if (rqc->src_inc) | |
1423 | ccr |= CC_SRCINC; | |
1424 | ||
1425 | if (rqc->dst_inc) | |
1426 | ccr |= CC_DSTINC; | |
1427 | ||
1428 | /* We set same protection levels for Src and DST for now */ | |
1429 | if (rqc->privileged) | |
1430 | ccr |= CC_SRCPRI | CC_DSTPRI; | |
1431 | if (rqc->nonsecure) | |
1432 | ccr |= CC_SRCNS | CC_DSTNS; | |
1433 | if (rqc->insnaccess) | |
1434 | ccr |= CC_SRCIA | CC_DSTIA; | |
1435 | ||
1436 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); | |
1437 | ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); | |
1438 | ||
1439 | ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); | |
1440 | ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); | |
1441 | ||
1442 | ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); | |
1443 | ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); | |
1444 | ||
1445 | ccr |= (rqc->swap << CC_SWAP_SHFT); | |
1446 | ||
1447 | return ccr; | |
1448 | } | |
1449 | ||
b7d861d9 BK |
1450 | /* |
1451 | * Submit a list of xfers after which the client wants notification. | |
1452 | * Client is not notified after each xfer unit, just once after all | |
1453 | * xfer units are done or some error occurs. | |
1454 | */ | |
9dc5a315 LPC |
1455 | static int pl330_submit_req(struct pl330_thread *thrd, |
1456 | struct dma_pl330_desc *desc) | |
b7d861d9 | 1457 | { |
f6f2421c | 1458 | struct pl330_dmac *pl330 = thrd->dmac; |
b7d861d9 BK |
1459 | struct _xfer_spec xs; |
1460 | unsigned long flags; | |
b7d861d9 BK |
1461 | unsigned idx; |
1462 | u32 ccr; | |
1463 | int ret = 0; | |
1464 | ||
1d48745b FMH |
1465 | switch (desc->rqtype) { |
1466 | case DMA_MEM_TO_DEV: | |
1467 | break; | |
1468 | ||
1469 | case DMA_DEV_TO_MEM: | |
1470 | break; | |
1471 | ||
1472 | case DMA_MEM_TO_MEM: | |
1473 | break; | |
1474 | ||
1475 | default: | |
1476 | return -ENOTSUPP; | |
1477 | } | |
1478 | ||
b7d861d9 BK |
1479 | if (pl330->state == DYING |
1480 | || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { | |
f6f2421c | 1481 | dev_info(thrd->dmac->ddma.dev, "%s:%d\n", |
b7d861d9 BK |
1482 | __func__, __LINE__); |
1483 | return -EAGAIN; | |
1484 | } | |
1485 | ||
1486 | /* If request for non-existing peripheral */ | |
9dc5a315 LPC |
1487 | if (desc->rqtype != DMA_MEM_TO_MEM && |
1488 | desc->peri >= pl330->pcfg.num_peri) { | |
f6f2421c | 1489 | dev_info(thrd->dmac->ddma.dev, |
b7d861d9 | 1490 | "%s:%d Invalid peripheral(%u)!\n", |
9dc5a315 | 1491 | __func__, __LINE__, desc->peri); |
b7d861d9 BK |
1492 | return -EINVAL; |
1493 | } | |
1494 | ||
1495 | spin_lock_irqsave(&pl330->lock, flags); | |
1496 | ||
1497 | if (_queue_full(thrd)) { | |
1498 | ret = -EAGAIN; | |
1499 | goto xfer_exit; | |
1500 | } | |
1501 | ||
9dc5a315 LPC |
1502 | /* Prefer Secure Channel */ |
1503 | if (!_manager_ns(thrd)) | |
1504 | desc->rqcfg.nonsecure = 0; | |
1505 | else | |
1506 | desc->rqcfg.nonsecure = 1; | |
b7d861d9 | 1507 | |
9dc5a315 | 1508 | ccr = _prepare_ccr(&desc->rqcfg); |
b7d861d9 | 1509 | |
8ed30a14 | 1510 | idx = thrd->req[0].desc == NULL ? 0 : 1; |
b7d861d9 BK |
1511 | |
1512 | xs.ccr = ccr; | |
9dc5a315 | 1513 | xs.desc = desc; |
b7d861d9 BK |
1514 | |
1515 | /* First dry run to check if req is acceptable */ | |
271e1b86 | 1516 | ret = _setup_req(pl330, 1, thrd, idx, &xs); |
b7d861d9 BK |
1517 | if (ret < 0) |
1518 | goto xfer_exit; | |
1519 | ||
f6f2421c | 1520 | if (ret > pl330->mcbufsz / 2) { |
e5489d5e MS |
1521 | dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n", |
1522 | __func__, __LINE__, ret, pl330->mcbufsz / 2); | |
b7d861d9 BK |
1523 | ret = -ENOMEM; |
1524 | goto xfer_exit; | |
1525 | } | |
1526 | ||
1527 | /* Hook the request */ | |
1528 | thrd->lstenq = idx; | |
9dc5a315 | 1529 | thrd->req[idx].desc = desc; |
271e1b86 | 1530 | _setup_req(pl330, 0, thrd, idx, &xs); |
b7d861d9 BK |
1531 | |
1532 | ret = 0; | |
1533 | ||
1534 | xfer_exit: | |
1535 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1536 | ||
1537 | return ret; | |
1538 | } | |
1539 | ||
9dc5a315 | 1540 | static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err) |
6079d38c | 1541 | { |
b1e51d77 | 1542 | struct dma_pl330_chan *pch; |
6079d38c LPC |
1543 | unsigned long flags; |
1544 | ||
b1e51d77 JMC |
1545 | if (!desc) |
1546 | return; | |
1547 | ||
1548 | pch = desc->pchan; | |
1549 | ||
6079d38c LPC |
1550 | /* If desc aborted */ |
1551 | if (!pch) | |
1552 | return; | |
1553 | ||
1554 | spin_lock_irqsave(&pch->lock, flags); | |
1555 | ||
1556 | desc->status = DONE; | |
1557 | ||
1558 | spin_unlock_irqrestore(&pch->lock, flags); | |
1559 | ||
1560 | tasklet_schedule(&pch->task); | |
1561 | } | |
1562 | ||
b7d861d9 BK |
1563 | static void pl330_dotask(unsigned long data) |
1564 | { | |
1565 | struct pl330_dmac *pl330 = (struct pl330_dmac *) data; | |
b7d861d9 BK |
1566 | unsigned long flags; |
1567 | int i; | |
1568 | ||
1569 | spin_lock_irqsave(&pl330->lock, flags); | |
1570 | ||
1571 | /* The DMAC itself gone nuts */ | |
1572 | if (pl330->dmac_tbd.reset_dmac) { | |
1573 | pl330->state = DYING; | |
1574 | /* Reset the manager too */ | |
1575 | pl330->dmac_tbd.reset_mngr = true; | |
1576 | /* Clear the reset flag */ | |
1577 | pl330->dmac_tbd.reset_dmac = false; | |
1578 | } | |
1579 | ||
1580 | if (pl330->dmac_tbd.reset_mngr) { | |
1581 | _stop(pl330->manager); | |
1582 | /* Reset all channels */ | |
f6f2421c | 1583 | pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1; |
b7d861d9 BK |
1584 | /* Clear the reset flag */ |
1585 | pl330->dmac_tbd.reset_mngr = false; | |
1586 | } | |
1587 | ||
f6f2421c | 1588 | for (i = 0; i < pl330->pcfg.num_chan; i++) { |
b7d861d9 BK |
1589 | |
1590 | if (pl330->dmac_tbd.reset_chan & (1 << i)) { | |
1591 | struct pl330_thread *thrd = &pl330->channels[i]; | |
f6f2421c | 1592 | void __iomem *regs = pl330->base; |
b7d861d9 BK |
1593 | enum pl330_op_err err; |
1594 | ||
1595 | _stop(thrd); | |
1596 | ||
1597 | if (readl(regs + FSC) & (1 << thrd->id)) | |
1598 | err = PL330_ERR_FAIL; | |
1599 | else | |
1600 | err = PL330_ERR_ABORT; | |
1601 | ||
1602 | spin_unlock_irqrestore(&pl330->lock, flags); | |
9dc5a315 LPC |
1603 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err); |
1604 | dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err); | |
b7d861d9 BK |
1605 | spin_lock_irqsave(&pl330->lock, flags); |
1606 | ||
9dc5a315 LPC |
1607 | thrd->req[0].desc = NULL; |
1608 | thrd->req[1].desc = NULL; | |
8ed30a14 | 1609 | thrd->req_running = -1; |
b7d861d9 BK |
1610 | |
1611 | /* Clear the reset flag */ | |
1612 | pl330->dmac_tbd.reset_chan &= ~(1 << i); | |
1613 | } | |
1614 | } | |
1615 | ||
1616 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1617 | ||
1618 | return; | |
1619 | } | |
1620 | ||
1621 | /* Returns 1 if state was updated, 0 otherwise */ | |
f6f2421c | 1622 | static int pl330_update(struct pl330_dmac *pl330) |
b7d861d9 | 1623 | { |
a3ca8312 | 1624 | struct dma_pl330_desc *descdone; |
b7d861d9 BK |
1625 | unsigned long flags; |
1626 | void __iomem *regs; | |
1627 | u32 val; | |
1628 | int id, ev, ret = 0; | |
1629 | ||
f6f2421c | 1630 | regs = pl330->base; |
b7d861d9 BK |
1631 | |
1632 | spin_lock_irqsave(&pl330->lock, flags); | |
1633 | ||
1634 | val = readl(regs + FSM) & 0x1; | |
1635 | if (val) | |
1636 | pl330->dmac_tbd.reset_mngr = true; | |
1637 | else | |
1638 | pl330->dmac_tbd.reset_mngr = false; | |
1639 | ||
f6f2421c | 1640 | val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1); |
b7d861d9 BK |
1641 | pl330->dmac_tbd.reset_chan |= val; |
1642 | if (val) { | |
1643 | int i = 0; | |
f6f2421c | 1644 | while (i < pl330->pcfg.num_chan) { |
b7d861d9 | 1645 | if (val & (1 << i)) { |
f6f2421c | 1646 | dev_info(pl330->ddma.dev, |
b7d861d9 BK |
1647 | "Reset Channel-%d\t CS-%x FTC-%x\n", |
1648 | i, readl(regs + CS(i)), | |
1649 | readl(regs + FTC(i))); | |
1650 | _stop(&pl330->channels[i]); | |
1651 | } | |
1652 | i++; | |
1653 | } | |
1654 | } | |
1655 | ||
1656 | /* Check which event happened i.e, thread notified */ | |
1657 | val = readl(regs + ES); | |
f6f2421c LPC |
1658 | if (pl330->pcfg.num_events < 32 |
1659 | && val & ~((1 << pl330->pcfg.num_events) - 1)) { | |
b7d861d9 | 1660 | pl330->dmac_tbd.reset_dmac = true; |
f6f2421c LPC |
1661 | dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__, |
1662 | __LINE__); | |
b7d861d9 BK |
1663 | ret = 1; |
1664 | goto updt_exit; | |
1665 | } | |
1666 | ||
f6f2421c | 1667 | for (ev = 0; ev < pl330->pcfg.num_events; ev++) { |
b7d861d9 BK |
1668 | if (val & (1 << ev)) { /* Event occurred */ |
1669 | struct pl330_thread *thrd; | |
1670 | u32 inten = readl(regs + INTEN); | |
1671 | int active; | |
1672 | ||
1673 | /* Clear the event */ | |
1674 | if (inten & (1 << ev)) | |
1675 | writel(1 << ev, regs + INTCLR); | |
1676 | ||
1677 | ret = 1; | |
1678 | ||
1679 | id = pl330->events[ev]; | |
1680 | ||
1681 | thrd = &pl330->channels[id]; | |
1682 | ||
1683 | active = thrd->req_running; | |
1684 | if (active == -1) /* Aborted */ | |
1685 | continue; | |
1686 | ||
fdec53d5 | 1687 | /* Detach the req */ |
9dc5a315 LPC |
1688 | descdone = thrd->req[active].desc; |
1689 | thrd->req[active].desc = NULL; | |
fdec53d5 | 1690 | |
0091b9d6 AK |
1691 | thrd->req_running = -1; |
1692 | ||
b7d861d9 BK |
1693 | /* Get going again ASAP */ |
1694 | _start(thrd); | |
1695 | ||
1696 | /* For now, just make a list of callbacks to be done */ | |
9dc5a315 | 1697 | list_add_tail(&descdone->rqd, &pl330->req_done); |
b7d861d9 BK |
1698 | } |
1699 | } | |
1700 | ||
1701 | /* Now that we are in no hurry, do the callbacks */ | |
a3ca8312 QH |
1702 | while (!list_empty(&pl330->req_done)) { |
1703 | descdone = list_first_entry(&pl330->req_done, | |
1704 | struct dma_pl330_desc, rqd); | |
9dc5a315 | 1705 | list_del(&descdone->rqd); |
b7d861d9 | 1706 | spin_unlock_irqrestore(&pl330->lock, flags); |
9dc5a315 | 1707 | dma_pl330_rqcb(descdone, PL330_ERR_NONE); |
b7d861d9 BK |
1708 | spin_lock_irqsave(&pl330->lock, flags); |
1709 | } | |
1710 | ||
1711 | updt_exit: | |
1712 | spin_unlock_irqrestore(&pl330->lock, flags); | |
1713 | ||
1714 | if (pl330->dmac_tbd.reset_dmac | |
1715 | || pl330->dmac_tbd.reset_mngr | |
1716 | || pl330->dmac_tbd.reset_chan) { | |
1717 | ret = 1; | |
1718 | tasklet_schedule(&pl330->tasks); | |
1719 | } | |
1720 | ||
1721 | return ret; | |
1722 | } | |
1723 | ||
b7d861d9 BK |
1724 | /* Reserve an event */ |
1725 | static inline int _alloc_event(struct pl330_thread *thrd) | |
1726 | { | |
1727 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1728 | int ev; |
1729 | ||
f6f2421c | 1730 | for (ev = 0; ev < pl330->pcfg.num_events; ev++) |
b7d861d9 BK |
1731 | if (pl330->events[ev] == -1) { |
1732 | pl330->events[ev] = thrd->id; | |
1733 | return ev; | |
1734 | } | |
1735 | ||
1736 | return -1; | |
1737 | } | |
1738 | ||
f6f2421c | 1739 | static bool _chan_ns(const struct pl330_dmac *pl330, int i) |
b7d861d9 | 1740 | { |
f6f2421c | 1741 | return pl330->pcfg.irq_ns & (1 << i); |
b7d861d9 BK |
1742 | } |
1743 | ||
1744 | /* Upon success, returns IdentityToken for the | |
1745 | * allocated channel, NULL otherwise. | |
1746 | */ | |
f6f2421c | 1747 | static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330) |
b7d861d9 BK |
1748 | { |
1749 | struct pl330_thread *thrd = NULL; | |
b7d861d9 BK |
1750 | int chans, i; |
1751 | ||
b7d861d9 BK |
1752 | if (pl330->state == DYING) |
1753 | return NULL; | |
1754 | ||
f6f2421c | 1755 | chans = pl330->pcfg.num_chan; |
b7d861d9 | 1756 | |
b7d861d9 BK |
1757 | for (i = 0; i < chans; i++) { |
1758 | thrd = &pl330->channels[i]; | |
1759 | if ((thrd->free) && (!_manager_ns(thrd) || | |
f6f2421c | 1760 | _chan_ns(pl330, i))) { |
b7d861d9 BK |
1761 | thrd->ev = _alloc_event(thrd); |
1762 | if (thrd->ev >= 0) { | |
1763 | thrd->free = false; | |
1764 | thrd->lstenq = 1; | |
9dc5a315 | 1765 | thrd->req[0].desc = NULL; |
9dc5a315 | 1766 | thrd->req[1].desc = NULL; |
8ed30a14 | 1767 | thrd->req_running = -1; |
b7d861d9 BK |
1768 | break; |
1769 | } | |
1770 | } | |
1771 | thrd = NULL; | |
1772 | } | |
1773 | ||
b7d861d9 BK |
1774 | return thrd; |
1775 | } | |
1776 | ||
1777 | /* Release an event */ | |
1778 | static inline void _free_event(struct pl330_thread *thrd, int ev) | |
1779 | { | |
1780 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1781 | |
1782 | /* If the event is valid and was held by the thread */ | |
f6f2421c | 1783 | if (ev >= 0 && ev < pl330->pcfg.num_events |
b7d861d9 BK |
1784 | && pl330->events[ev] == thrd->id) |
1785 | pl330->events[ev] = -1; | |
1786 | } | |
1787 | ||
65ad6060 | 1788 | static void pl330_release_channel(struct pl330_thread *thrd) |
b7d861d9 | 1789 | { |
b7d861d9 BK |
1790 | if (!thrd || thrd->free) |
1791 | return; | |
1792 | ||
1793 | _stop(thrd); | |
1794 | ||
9dc5a315 LPC |
1795 | dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT); |
1796 | dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT); | |
b7d861d9 | 1797 | |
b7d861d9 BK |
1798 | _free_event(thrd, thrd->ev); |
1799 | thrd->free = true; | |
b7d861d9 BK |
1800 | } |
1801 | ||
1802 | /* Initialize the structure for PL330 configuration, that can be used | |
1803 | * by the client driver the make best use of the DMAC | |
1804 | */ | |
f6f2421c | 1805 | static void read_dmac_config(struct pl330_dmac *pl330) |
b7d861d9 | 1806 | { |
f6f2421c | 1807 | void __iomem *regs = pl330->base; |
b7d861d9 BK |
1808 | u32 val; |
1809 | ||
1810 | val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; | |
1811 | val &= CRD_DATA_WIDTH_MASK; | |
f6f2421c | 1812 | pl330->pcfg.data_bus_width = 8 * (1 << val); |
b7d861d9 BK |
1813 | |
1814 | val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; | |
1815 | val &= CRD_DATA_BUFF_MASK; | |
f6f2421c | 1816 | pl330->pcfg.data_buf_dep = val + 1; |
b7d861d9 BK |
1817 | |
1818 | val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; | |
1819 | val &= CR0_NUM_CHANS_MASK; | |
1820 | val += 1; | |
f6f2421c | 1821 | pl330->pcfg.num_chan = val; |
b7d861d9 BK |
1822 | |
1823 | val = readl(regs + CR0); | |
1824 | if (val & CR0_PERIPH_REQ_SET) { | |
1825 | val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; | |
1826 | val += 1; | |
f6f2421c LPC |
1827 | pl330->pcfg.num_peri = val; |
1828 | pl330->pcfg.peri_ns = readl(regs + CR4); | |
b7d861d9 | 1829 | } else { |
f6f2421c | 1830 | pl330->pcfg.num_peri = 0; |
b7d861d9 BK |
1831 | } |
1832 | ||
1833 | val = readl(regs + CR0); | |
1834 | if (val & CR0_BOOT_MAN_NS) | |
f6f2421c | 1835 | pl330->pcfg.mode |= DMAC_MODE_NS; |
b7d861d9 | 1836 | else |
f6f2421c | 1837 | pl330->pcfg.mode &= ~DMAC_MODE_NS; |
b7d861d9 BK |
1838 | |
1839 | val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; | |
1840 | val &= CR0_NUM_EVENTS_MASK; | |
1841 | val += 1; | |
f6f2421c | 1842 | pl330->pcfg.num_events = val; |
b7d861d9 | 1843 | |
f6f2421c | 1844 | pl330->pcfg.irq_ns = readl(regs + CR3); |
b7d861d9 BK |
1845 | } |
1846 | ||
1847 | static inline void _reset_thread(struct pl330_thread *thrd) | |
1848 | { | |
1849 | struct pl330_dmac *pl330 = thrd->dmac; | |
b7d861d9 BK |
1850 | |
1851 | thrd->req[0].mc_cpu = pl330->mcode_cpu | |
f6f2421c | 1852 | + (thrd->id * pl330->mcbufsz); |
b7d861d9 | 1853 | thrd->req[0].mc_bus = pl330->mcode_bus |
f6f2421c | 1854 | + (thrd->id * pl330->mcbufsz); |
9dc5a315 | 1855 | thrd->req[0].desc = NULL; |
b7d861d9 BK |
1856 | |
1857 | thrd->req[1].mc_cpu = thrd->req[0].mc_cpu | |
f6f2421c | 1858 | + pl330->mcbufsz / 2; |
b7d861d9 | 1859 | thrd->req[1].mc_bus = thrd->req[0].mc_bus |
f6f2421c | 1860 | + pl330->mcbufsz / 2; |
9dc5a315 | 1861 | thrd->req[1].desc = NULL; |
8ed30a14 LPC |
1862 | |
1863 | thrd->req_running = -1; | |
b7d861d9 BK |
1864 | } |
1865 | ||
1866 | static int dmac_alloc_threads(struct pl330_dmac *pl330) | |
1867 | { | |
f6f2421c | 1868 | int chans = pl330->pcfg.num_chan; |
b7d861d9 BK |
1869 | struct pl330_thread *thrd; |
1870 | int i; | |
1871 | ||
1872 | /* Allocate 1 Manager and 'chans' Channel threads */ | |
6396bb22 | 1873 | pl330->channels = kcalloc(1 + chans, sizeof(*thrd), |
b7d861d9 BK |
1874 | GFP_KERNEL); |
1875 | if (!pl330->channels) | |
1876 | return -ENOMEM; | |
1877 | ||
1878 | /* Init Channel threads */ | |
1879 | for (i = 0; i < chans; i++) { | |
1880 | thrd = &pl330->channels[i]; | |
1881 | thrd->id = i; | |
1882 | thrd->dmac = pl330; | |
1883 | _reset_thread(thrd); | |
1884 | thrd->free = true; | |
1885 | } | |
1886 | ||
1887 | /* MANAGER is indexed at the end */ | |
1888 | thrd = &pl330->channels[chans]; | |
1889 | thrd->id = chans; | |
1890 | thrd->dmac = pl330; | |
1891 | thrd->free = false; | |
1892 | pl330->manager = thrd; | |
1893 | ||
1894 | return 0; | |
1895 | } | |
1896 | ||
1897 | static int dmac_alloc_resources(struct pl330_dmac *pl330) | |
1898 | { | |
f6f2421c | 1899 | int chans = pl330->pcfg.num_chan; |
b7d861d9 | 1900 | int ret; |
b3040e40 | 1901 | |
b3040e40 | 1902 | /* |
b7d861d9 BK |
1903 | * Alloc MicroCode buffer for 'chans' Channel threads. |
1904 | * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) | |
b3040e40 | 1905 | */ |
1b2354db | 1906 | pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev, |
f6f2421c | 1907 | chans * pl330->mcbufsz, |
1b2354db MH |
1908 | &pl330->mcode_bus, GFP_KERNEL, |
1909 | DMA_ATTR_PRIVILEGED); | |
b7d861d9 | 1910 | if (!pl330->mcode_cpu) { |
f6f2421c | 1911 | dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n", |
b7d861d9 BK |
1912 | __func__, __LINE__); |
1913 | return -ENOMEM; | |
1914 | } | |
1915 | ||
1916 | ret = dmac_alloc_threads(pl330); | |
1917 | if (ret) { | |
f6f2421c | 1918 | dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n", |
b7d861d9 | 1919 | __func__, __LINE__); |
f6f2421c LPC |
1920 | dma_free_coherent(pl330->ddma.dev, |
1921 | chans * pl330->mcbufsz, | |
b7d861d9 BK |
1922 | pl330->mcode_cpu, pl330->mcode_bus); |
1923 | return ret; | |
1924 | } | |
1925 | ||
1926 | return 0; | |
1927 | } | |
1928 | ||
f6f2421c | 1929 | static int pl330_add(struct pl330_dmac *pl330) |
b7d861d9 | 1930 | { |
b7d861d9 BK |
1931 | int i, ret; |
1932 | ||
b7d861d9 | 1933 | /* Check if we can handle this DMAC */ |
f6f2421c LPC |
1934 | if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { |
1935 | dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n", | |
1936 | pl330->pcfg.periph_id); | |
b7d861d9 BK |
1937 | return -EINVAL; |
1938 | } | |
b3040e40 | 1939 | |
b7d861d9 | 1940 | /* Read the configuration of the DMAC */ |
f6f2421c | 1941 | read_dmac_config(pl330); |
b3040e40 | 1942 | |
f6f2421c LPC |
1943 | if (pl330->pcfg.num_events == 0) { |
1944 | dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n", | |
b7d861d9 BK |
1945 | __func__, __LINE__); |
1946 | return -EINVAL; | |
1947 | } | |
b3040e40 | 1948 | |
b7d861d9 | 1949 | spin_lock_init(&pl330->lock); |
1b9bb715 | 1950 | |
b7d861d9 | 1951 | INIT_LIST_HEAD(&pl330->req_done); |
42bc9cf4 | 1952 | |
b7d861d9 | 1953 | /* Use default MC buffer size if not provided */ |
f6f2421c LPC |
1954 | if (!pl330->mcbufsz) |
1955 | pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2; | |
b3040e40 | 1956 | |
b7d861d9 | 1957 | /* Mark all events as free */ |
f6f2421c | 1958 | for (i = 0; i < pl330->pcfg.num_events; i++) |
b7d861d9 | 1959 | pl330->events[i] = -1; |
b3040e40 | 1960 | |
b7d861d9 BK |
1961 | /* Allocate resources needed by the DMAC */ |
1962 | ret = dmac_alloc_resources(pl330); | |
1963 | if (ret) { | |
f6f2421c | 1964 | dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n"); |
b7d861d9 BK |
1965 | return ret; |
1966 | } | |
b3040e40 | 1967 | |
b7d861d9 | 1968 | tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); |
b3040e40 | 1969 | |
b7d861d9 | 1970 | pl330->state = INIT; |
a2f5203f | 1971 | |
b7d861d9 BK |
1972 | return 0; |
1973 | } | |
b3040e40 | 1974 | |
b7d861d9 BK |
1975 | static int dmac_free_threads(struct pl330_dmac *pl330) |
1976 | { | |
b7d861d9 BK |
1977 | struct pl330_thread *thrd; |
1978 | int i; | |
b3040e40 | 1979 | |
b7d861d9 | 1980 | /* Release Channel threads */ |
f6f2421c | 1981 | for (i = 0; i < pl330->pcfg.num_chan; i++) { |
b7d861d9 | 1982 | thrd = &pl330->channels[i]; |
65ad6060 | 1983 | pl330_release_channel(thrd); |
b7d861d9 | 1984 | } |
b3040e40 | 1985 | |
b7d861d9 BK |
1986 | /* Free memory */ |
1987 | kfree(pl330->channels); | |
b3040e40 | 1988 | |
b7d861d9 BK |
1989 | return 0; |
1990 | } | |
b3040e40 | 1991 | |
f6f2421c | 1992 | static void pl330_del(struct pl330_dmac *pl330) |
b7d861d9 | 1993 | { |
b7d861d9 BK |
1994 | pl330->state = UNINIT; |
1995 | ||
1996 | tasklet_kill(&pl330->tasks); | |
1997 | ||
1998 | /* Free DMAC resources */ | |
f6f2421c | 1999 | dmac_free_threads(pl330); |
b7d861d9 | 2000 | |
f6f2421c LPC |
2001 | dma_free_coherent(pl330->ddma.dev, |
2002 | pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu, | |
2003 | pl330->mcode_bus); | |
b7d861d9 | 2004 | } |
b3040e40 | 2005 | |
3e2ec13a TA |
2006 | /* forward declaration */ |
2007 | static struct amba_driver pl330_driver; | |
2008 | ||
b3040e40 JB |
2009 | static inline struct dma_pl330_chan * |
2010 | to_pchan(struct dma_chan *ch) | |
2011 | { | |
2012 | if (!ch) | |
2013 | return NULL; | |
2014 | ||
2015 | return container_of(ch, struct dma_pl330_chan, chan); | |
2016 | } | |
2017 | ||
2018 | static inline struct dma_pl330_desc * | |
2019 | to_desc(struct dma_async_tx_descriptor *tx) | |
2020 | { | |
2021 | return container_of(tx, struct dma_pl330_desc, txd); | |
2022 | } | |
2023 | ||
b3040e40 JB |
2024 | static inline void fill_queue(struct dma_pl330_chan *pch) |
2025 | { | |
2026 | struct dma_pl330_desc *desc; | |
2027 | int ret; | |
2028 | ||
2029 | list_for_each_entry(desc, &pch->work_list, node) { | |
2030 | ||
2031 | /* If already submitted */ | |
2032 | if (desc->status == BUSY) | |
30fb980b | 2033 | continue; |
b3040e40 | 2034 | |
9dc5a315 | 2035 | ret = pl330_submit_req(pch->thread, desc); |
b3040e40 JB |
2036 | if (!ret) { |
2037 | desc->status = BUSY; | |
b3040e40 JB |
2038 | } else if (ret == -EAGAIN) { |
2039 | /* QFull or DMAC Dying */ | |
2040 | break; | |
2041 | } else { | |
2042 | /* Unacceptable request */ | |
2043 | desc->status = DONE; | |
f6f2421c | 2044 | dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", |
b3040e40 JB |
2045 | __func__, __LINE__, desc->txd.cookie); |
2046 | tasklet_schedule(&pch->task); | |
2047 | } | |
2048 | } | |
2049 | } | |
2050 | ||
2051 | static void pl330_tasklet(unsigned long data) | |
2052 | { | |
2053 | struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; | |
2054 | struct dma_pl330_desc *desc, *_dt; | |
2055 | unsigned long flags; | |
ae43b328 | 2056 | bool power_down = false; |
b3040e40 JB |
2057 | |
2058 | spin_lock_irqsave(&pch->lock, flags); | |
2059 | ||
2060 | /* Pick up ripe tomatoes */ | |
2061 | list_for_each_entry_safe(desc, _dt, &pch->work_list, node) | |
2062 | if (desc->status == DONE) { | |
30c1dc0f | 2063 | if (!pch->cyclic) |
eab21585 | 2064 | dma_cookie_complete(&desc->txd); |
39ff8613 | 2065 | list_move_tail(&desc->node, &pch->completed_list); |
b3040e40 JB |
2066 | } |
2067 | ||
2068 | /* Try to submit a req imm. next to the last completed cookie */ | |
2069 | fill_queue(pch); | |
2070 | ||
ae43b328 KK |
2071 | if (list_empty(&pch->work_list)) { |
2072 | spin_lock(&pch->thread->dmac->lock); | |
2073 | _stop(pch->thread); | |
2074 | spin_unlock(&pch->thread->dmac->lock); | |
2075 | power_down = true; | |
5c9e6c2b | 2076 | pch->active = false; |
ae43b328 KK |
2077 | } else { |
2078 | /* Make sure the PL330 Channel thread is active */ | |
2079 | spin_lock(&pch->thread->dmac->lock); | |
2080 | _start(pch->thread); | |
2081 | spin_unlock(&pch->thread->dmac->lock); | |
2082 | } | |
b3040e40 | 2083 | |
39ff8613 | 2084 | while (!list_empty(&pch->completed_list)) { |
f08462c6 | 2085 | struct dmaengine_desc_callback cb; |
b3040e40 | 2086 | |
39ff8613 LPC |
2087 | desc = list_first_entry(&pch->completed_list, |
2088 | struct dma_pl330_desc, node); | |
2089 | ||
f08462c6 | 2090 | dmaengine_desc_get_callback(&desc->txd, &cb); |
39ff8613 LPC |
2091 | |
2092 | if (pch->cyclic) { | |
2093 | desc->status = PREP; | |
2094 | list_move_tail(&desc->node, &pch->work_list); | |
ae43b328 | 2095 | if (power_down) { |
5c9e6c2b | 2096 | pch->active = true; |
ae43b328 KK |
2097 | spin_lock(&pch->thread->dmac->lock); |
2098 | _start(pch->thread); | |
2099 | spin_unlock(&pch->thread->dmac->lock); | |
2100 | power_down = false; | |
2101 | } | |
39ff8613 LPC |
2102 | } else { |
2103 | desc->status = FREE; | |
2104 | list_move_tail(&desc->node, &pch->dmac->desc_pool); | |
2105 | } | |
2106 | ||
d38a8c62 DW |
2107 | dma_descriptor_unmap(&desc->txd); |
2108 | ||
f08462c6 | 2109 | if (dmaengine_desc_callback_valid(&cb)) { |
39ff8613 | 2110 | spin_unlock_irqrestore(&pch->lock, flags); |
f08462c6 | 2111 | dmaengine_desc_callback_invoke(&cb, NULL); |
39ff8613 LPC |
2112 | spin_lock_irqsave(&pch->lock, flags); |
2113 | } | |
2114 | } | |
2115 | spin_unlock_irqrestore(&pch->lock, flags); | |
ae43b328 KK |
2116 | |
2117 | /* If work list empty, power down */ | |
2118 | if (power_down) { | |
2119 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); | |
2120 | pm_runtime_put_autosuspend(pch->dmac->ddma.dev); | |
2121 | } | |
b3040e40 JB |
2122 | } |
2123 | ||
a80258f9 PV |
2124 | static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, |
2125 | struct of_dma *ofdma) | |
2126 | { | |
2127 | int count = dma_spec->args_count; | |
f6f2421c | 2128 | struct pl330_dmac *pl330 = ofdma->of_dma_data; |
70cbb163 | 2129 | unsigned int chan_id; |
a80258f9 | 2130 | |
f6f2421c LPC |
2131 | if (!pl330) |
2132 | return NULL; | |
2133 | ||
a80258f9 PV |
2134 | if (count != 1) |
2135 | return NULL; | |
2136 | ||
70cbb163 | 2137 | chan_id = dma_spec->args[0]; |
f6f2421c | 2138 | if (chan_id >= pl330->num_peripherals) |
70cbb163 | 2139 | return NULL; |
a80258f9 | 2140 | |
f6f2421c | 2141 | return dma_get_slave_channel(&pl330->peripherals[chan_id].chan); |
a80258f9 PV |
2142 | } |
2143 | ||
b3040e40 JB |
2144 | static int pl330_alloc_chan_resources(struct dma_chan *chan) |
2145 | { | |
2146 | struct dma_pl330_chan *pch = to_pchan(chan); | |
f6f2421c | 2147 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2148 | unsigned long flags; |
2149 | ||
91539eb1 | 2150 | spin_lock_irqsave(&pl330->lock, flags); |
b3040e40 | 2151 | |
d3ee98cd | 2152 | dma_cookie_init(chan); |
42bc9cf4 | 2153 | pch->cyclic = false; |
b3040e40 | 2154 | |
f6f2421c | 2155 | pch->thread = pl330_request_channel(pl330); |
65ad6060 | 2156 | if (!pch->thread) { |
91539eb1 | 2157 | spin_unlock_irqrestore(&pl330->lock, flags); |
02747885 | 2158 | return -ENOMEM; |
b3040e40 JB |
2159 | } |
2160 | ||
2161 | tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); | |
2162 | ||
91539eb1 | 2163 | spin_unlock_irqrestore(&pl330->lock, flags); |
b3040e40 JB |
2164 | |
2165 | return 1; | |
2166 | } | |
2167 | ||
4d6d74e2 RM |
2168 | /* |
2169 | * We need the data direction between the DMAC (the dma-mapping "device") and | |
2170 | * the FIFO (the dmaengine "dev"), from the FIFO's point of view. Confusing! | |
2171 | */ | |
2172 | static enum dma_data_direction | |
2173 | pl330_dma_slave_map_dir(enum dma_transfer_direction dir) | |
2174 | { | |
2175 | switch (dir) { | |
2176 | case DMA_MEM_TO_DEV: | |
2177 | return DMA_FROM_DEVICE; | |
2178 | case DMA_DEV_TO_MEM: | |
2179 | return DMA_TO_DEVICE; | |
2180 | case DMA_DEV_TO_DEV: | |
2181 | return DMA_BIDIRECTIONAL; | |
2182 | default: | |
2183 | return DMA_NONE; | |
2184 | } | |
2185 | } | |
2186 | ||
2187 | static void pl330_unprep_slave_fifo(struct dma_pl330_chan *pch) | |
2188 | { | |
2189 | if (pch->dir != DMA_NONE) | |
2190 | dma_unmap_resource(pch->chan.device->dev, pch->fifo_dma, | |
2191 | 1 << pch->burst_sz, pch->dir, 0); | |
2192 | pch->dir = DMA_NONE; | |
2193 | } | |
2194 | ||
2195 | ||
2196 | static bool pl330_prep_slave_fifo(struct dma_pl330_chan *pch, | |
2197 | enum dma_transfer_direction dir) | |
2198 | { | |
2199 | struct device *dev = pch->chan.device->dev; | |
2200 | enum dma_data_direction dma_dir = pl330_dma_slave_map_dir(dir); | |
2201 | ||
2202 | /* Already mapped for this config? */ | |
2203 | if (pch->dir == dma_dir) | |
2204 | return true; | |
2205 | ||
2206 | pl330_unprep_slave_fifo(pch); | |
2207 | pch->fifo_dma = dma_map_resource(dev, pch->fifo_addr, | |
2208 | 1 << pch->burst_sz, dma_dir, 0); | |
2209 | if (dma_mapping_error(dev, pch->fifo_dma)) | |
2210 | return false; | |
2211 | ||
2212 | pch->dir = dma_dir; | |
2213 | return true; | |
2214 | } | |
2215 | ||
1d48745b FMH |
2216 | static int fixup_burst_len(int max_burst_len, int quirks) |
2217 | { | |
2218 | if (quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) | |
2219 | return 1; | |
2220 | else if (max_burst_len > PL330_MAX_BURST) | |
2221 | return PL330_MAX_BURST; | |
2222 | else if (max_burst_len < 1) | |
2223 | return 1; | |
2224 | else | |
2225 | return max_burst_len; | |
2226 | } | |
2227 | ||
445897cb VK |
2228 | static int pl330_config_write(struct dma_chan *chan, |
2229 | struct dma_slave_config *slave_config, | |
2230 | enum dma_transfer_direction direction) | |
740aa957 MR |
2231 | { |
2232 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2233 | ||
4d6d74e2 | 2234 | pl330_unprep_slave_fifo(pch); |
445897cb | 2235 | if (direction == DMA_MEM_TO_DEV) { |
740aa957 MR |
2236 | if (slave_config->dst_addr) |
2237 | pch->fifo_addr = slave_config->dst_addr; | |
2238 | if (slave_config->dst_addr_width) | |
2239 | pch->burst_sz = __ffs(slave_config->dst_addr_width); | |
1d48745b FMH |
2240 | pch->burst_len = fixup_burst_len(slave_config->dst_maxburst, |
2241 | pch->dmac->quirks); | |
445897cb | 2242 | } else if (direction == DMA_DEV_TO_MEM) { |
740aa957 MR |
2243 | if (slave_config->src_addr) |
2244 | pch->fifo_addr = slave_config->src_addr; | |
2245 | if (slave_config->src_addr_width) | |
2246 | pch->burst_sz = __ffs(slave_config->src_addr_width); | |
1d48745b FMH |
2247 | pch->burst_len = fixup_burst_len(slave_config->src_maxburst, |
2248 | pch->dmac->quirks); | |
740aa957 MR |
2249 | } |
2250 | ||
2251 | return 0; | |
2252 | } | |
2253 | ||
445897cb VK |
2254 | static int pl330_config(struct dma_chan *chan, |
2255 | struct dma_slave_config *slave_config) | |
2256 | { | |
2257 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2258 | ||
2259 | memcpy(&pch->slave_config, slave_config, sizeof(*slave_config)); | |
2260 | ||
2261 | return 0; | |
2262 | } | |
2263 | ||
740aa957 | 2264 | static int pl330_terminate_all(struct dma_chan *chan) |
b3040e40 JB |
2265 | { |
2266 | struct dma_pl330_chan *pch = to_pchan(chan); | |
39ff8613 | 2267 | struct dma_pl330_desc *desc; |
b3040e40 | 2268 | unsigned long flags; |
f6f2421c | 2269 | struct pl330_dmac *pl330 = pch->dmac; |
5c9e6c2b | 2270 | bool power_down = false; |
b3040e40 | 2271 | |
81cc6edc | 2272 | pm_runtime_get_sync(pl330->ddma.dev); |
740aa957 | 2273 | spin_lock_irqsave(&pch->lock, flags); |
e4975654 | 2274 | |
740aa957 MR |
2275 | spin_lock(&pl330->lock); |
2276 | _stop(pch->thread); | |
740aa957 MR |
2277 | pch->thread->req[0].desc = NULL; |
2278 | pch->thread->req[1].desc = NULL; | |
2279 | pch->thread->req_running = -1; | |
e4975654 JK |
2280 | spin_unlock(&pl330->lock); |
2281 | ||
5c9e6c2b MS |
2282 | power_down = pch->active; |
2283 | pch->active = false; | |
740aa957 MR |
2284 | |
2285 | /* Mark all desc done */ | |
2286 | list_for_each_entry(desc, &pch->submitted_list, node) { | |
2287 | desc->status = FREE; | |
2288 | dma_cookie_complete(&desc->txd); | |
2289 | } | |
ae43b328 | 2290 | |
740aa957 MR |
2291 | list_for_each_entry(desc, &pch->work_list , node) { |
2292 | desc->status = FREE; | |
2293 | dma_cookie_complete(&desc->txd); | |
1d0c1d60 | 2294 | } |
b3040e40 | 2295 | |
740aa957 MR |
2296 | list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool); |
2297 | list_splice_tail_init(&pch->work_list, &pl330->desc_pool); | |
2298 | list_splice_tail_init(&pch->completed_list, &pl330->desc_pool); | |
2299 | spin_unlock_irqrestore(&pch->lock, flags); | |
81cc6edc | 2300 | pm_runtime_mark_last_busy(pl330->ddma.dev); |
5c9e6c2b MS |
2301 | if (power_down) |
2302 | pm_runtime_put_autosuspend(pl330->ddma.dev); | |
81cc6edc | 2303 | pm_runtime_put_autosuspend(pl330->ddma.dev); |
740aa957 | 2304 | |
b3040e40 JB |
2305 | return 0; |
2306 | } | |
2307 | ||
88987d2c RB |
2308 | /* |
2309 | * We don't support DMA_RESUME command because of hardware | |
2310 | * limitations, so after pausing the channel we cannot restore | |
2311 | * it to active state. We have to terminate channel and setup | |
2312 | * DMA transfer again. This pause feature was implemented to | |
2313 | * allow safely read residue before channel termination. | |
2314 | */ | |
5503aed8 | 2315 | static int pl330_pause(struct dma_chan *chan) |
88987d2c RB |
2316 | { |
2317 | struct dma_pl330_chan *pch = to_pchan(chan); | |
2318 | struct pl330_dmac *pl330 = pch->dmac; | |
2319 | unsigned long flags; | |
2320 | ||
2321 | pm_runtime_get_sync(pl330->ddma.dev); | |
2322 | spin_lock_irqsave(&pch->lock, flags); | |
2323 | ||
2324 | spin_lock(&pl330->lock); | |
2325 | _stop(pch->thread); | |
2326 | spin_unlock(&pl330->lock); | |
2327 | ||
2328 | spin_unlock_irqrestore(&pch->lock, flags); | |
2329 | pm_runtime_mark_last_busy(pl330->ddma.dev); | |
2330 | pm_runtime_put_autosuspend(pl330->ddma.dev); | |
2331 | ||
2332 | return 0; | |
2333 | } | |
2334 | ||
b3040e40 JB |
2335 | static void pl330_free_chan_resources(struct dma_chan *chan) |
2336 | { | |
2337 | struct dma_pl330_chan *pch = to_pchan(chan); | |
91539eb1 | 2338 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2339 | unsigned long flags; |
2340 | ||
b3040e40 JB |
2341 | tasklet_kill(&pch->task); |
2342 | ||
ae43b328 | 2343 | pm_runtime_get_sync(pch->dmac->ddma.dev); |
91539eb1 | 2344 | spin_lock_irqsave(&pl330->lock, flags); |
da331ba8 | 2345 | |
65ad6060 LPC |
2346 | pl330_release_channel(pch->thread); |
2347 | pch->thread = NULL; | |
b3040e40 | 2348 | |
42bc9cf4 BK |
2349 | if (pch->cyclic) |
2350 | list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); | |
2351 | ||
91539eb1 | 2352 | spin_unlock_irqrestore(&pl330->lock, flags); |
ae43b328 KK |
2353 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); |
2354 | pm_runtime_put_autosuspend(pch->dmac->ddma.dev); | |
4d6d74e2 | 2355 | pl330_unprep_slave_fifo(pch); |
b3040e40 JB |
2356 | } |
2357 | ||
5503aed8 BD |
2358 | static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch, |
2359 | struct dma_pl330_desc *desc) | |
aee4d1fa RB |
2360 | { |
2361 | struct pl330_thread *thrd = pch->thread; | |
2362 | struct pl330_dmac *pl330 = pch->dmac; | |
2363 | void __iomem *regs = thrd->dmac->base; | |
2364 | u32 val, addr; | |
2365 | ||
2366 | pm_runtime_get_sync(pl330->ddma.dev); | |
2367 | val = addr = 0; | |
2368 | if (desc->rqcfg.src_inc) { | |
2369 | val = readl(regs + SA(thrd->id)); | |
2370 | addr = desc->px.src_addr; | |
2371 | } else { | |
2372 | val = readl(regs + DA(thrd->id)); | |
2373 | addr = desc->px.dst_addr; | |
2374 | } | |
2375 | pm_runtime_mark_last_busy(pch->dmac->ddma.dev); | |
2376 | pm_runtime_put_autosuspend(pl330->ddma.dev); | |
c44da03d SB |
2377 | |
2378 | /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */ | |
2379 | if (!val) | |
2380 | return 0; | |
2381 | ||
aee4d1fa RB |
2382 | return val - addr; |
2383 | } | |
2384 | ||
b3040e40 JB |
2385 | static enum dma_status |
2386 | pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, | |
2387 | struct dma_tx_state *txstate) | |
2388 | { | |
aee4d1fa RB |
2389 | enum dma_status ret; |
2390 | unsigned long flags; | |
d64e9a2c | 2391 | struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL; |
aee4d1fa RB |
2392 | struct dma_pl330_chan *pch = to_pchan(chan); |
2393 | unsigned int transferred, residual = 0; | |
2394 | ||
2395 | ret = dma_cookie_status(chan, cookie, txstate); | |
2396 | ||
2397 | if (!txstate) | |
2398 | return ret; | |
2399 | ||
2400 | if (ret == DMA_COMPLETE) | |
2401 | goto out; | |
2402 | ||
2403 | spin_lock_irqsave(&pch->lock, flags); | |
a40235a2 | 2404 | spin_lock(&pch->thread->dmac->lock); |
aee4d1fa RB |
2405 | |
2406 | if (pch->thread->req_running != -1) | |
2407 | running = pch->thread->req[pch->thread->req_running].desc; | |
2408 | ||
d64e9a2c SB |
2409 | last_enq = pch->thread->req[pch->thread->lstenq].desc; |
2410 | ||
aee4d1fa RB |
2411 | /* Check in pending list */ |
2412 | list_for_each_entry(desc, &pch->work_list, node) { | |
2413 | if (desc->status == DONE) | |
2414 | transferred = desc->bytes_requested; | |
2415 | else if (running && desc == running) | |
2416 | transferred = | |
2417 | pl330_get_current_xferred_count(pch, desc); | |
d64e9a2c SB |
2418 | else if (desc->status == BUSY) |
2419 | /* | |
2420 | * Busy but not running means either just enqueued, | |
2421 | * or finished and not yet marked done | |
2422 | */ | |
2423 | if (desc == last_enq) | |
2424 | transferred = 0; | |
2425 | else | |
2426 | transferred = desc->bytes_requested; | |
aee4d1fa RB |
2427 | else |
2428 | transferred = 0; | |
2429 | residual += desc->bytes_requested - transferred; | |
2430 | if (desc->txd.cookie == cookie) { | |
75967b78 BD |
2431 | switch (desc->status) { |
2432 | case DONE: | |
2433 | ret = DMA_COMPLETE; | |
2434 | break; | |
2435 | case PREP: | |
2436 | case BUSY: | |
2437 | ret = DMA_IN_PROGRESS; | |
2438 | break; | |
2439 | default: | |
2440 | WARN_ON(1); | |
2441 | } | |
aee4d1fa RB |
2442 | break; |
2443 | } | |
2444 | if (desc->last) | |
2445 | residual = 0; | |
2446 | } | |
a40235a2 | 2447 | spin_unlock(&pch->thread->dmac->lock); |
aee4d1fa RB |
2448 | spin_unlock_irqrestore(&pch->lock, flags); |
2449 | ||
2450 | out: | |
2451 | dma_set_residue(txstate, residual); | |
2452 | ||
2453 | return ret; | |
b3040e40 JB |
2454 | } |
2455 | ||
2456 | static void pl330_issue_pending(struct dma_chan *chan) | |
2457 | { | |
04abf5da LPC |
2458 | struct dma_pl330_chan *pch = to_pchan(chan); |
2459 | unsigned long flags; | |
2460 | ||
2461 | spin_lock_irqsave(&pch->lock, flags); | |
ae43b328 KK |
2462 | if (list_empty(&pch->work_list)) { |
2463 | /* | |
2464 | * Warn on nothing pending. Empty submitted_list may | |
2465 | * break our pm_runtime usage counter as it is | |
2466 | * updated on work_list emptiness status. | |
2467 | */ | |
2468 | WARN_ON(list_empty(&pch->submitted_list)); | |
5c9e6c2b | 2469 | pch->active = true; |
ae43b328 KK |
2470 | pm_runtime_get_sync(pch->dmac->ddma.dev); |
2471 | } | |
04abf5da LPC |
2472 | list_splice_tail_init(&pch->submitted_list, &pch->work_list); |
2473 | spin_unlock_irqrestore(&pch->lock, flags); | |
2474 | ||
2475 | pl330_tasklet((unsigned long)pch); | |
b3040e40 JB |
2476 | } |
2477 | ||
2478 | /* | |
2479 | * We returned the last one of the circular list of descriptor(s) | |
2480 | * from prep_xxx, so the argument to submit corresponds to the last | |
2481 | * descriptor of the list. | |
2482 | */ | |
2483 | static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) | |
2484 | { | |
2485 | struct dma_pl330_desc *desc, *last = to_desc(tx); | |
2486 | struct dma_pl330_chan *pch = to_pchan(tx->chan); | |
2487 | dma_cookie_t cookie; | |
2488 | unsigned long flags; | |
2489 | ||
2490 | spin_lock_irqsave(&pch->lock, flags); | |
2491 | ||
2492 | /* Assign cookies to all nodes */ | |
b3040e40 JB |
2493 | while (!list_empty(&last->node)) { |
2494 | desc = list_entry(last->node.next, struct dma_pl330_desc, node); | |
fc514460 LPC |
2495 | if (pch->cyclic) { |
2496 | desc->txd.callback = last->txd.callback; | |
2497 | desc->txd.callback_param = last->txd.callback_param; | |
2498 | } | |
5dd90e5b | 2499 | desc->last = false; |
b3040e40 | 2500 | |
884485e1 | 2501 | dma_cookie_assign(&desc->txd); |
b3040e40 | 2502 | |
04abf5da | 2503 | list_move_tail(&desc->node, &pch->submitted_list); |
b3040e40 JB |
2504 | } |
2505 | ||
aee4d1fa | 2506 | last->last = true; |
884485e1 | 2507 | cookie = dma_cookie_assign(&last->txd); |
04abf5da | 2508 | list_add_tail(&last->node, &pch->submitted_list); |
b3040e40 JB |
2509 | spin_unlock_irqrestore(&pch->lock, flags); |
2510 | ||
2511 | return cookie; | |
2512 | } | |
2513 | ||
2514 | static inline void _init_desc(struct dma_pl330_desc *desc) | |
2515 | { | |
b3040e40 | 2516 | desc->rqcfg.swap = SWAP_NO; |
f0564c7e LPC |
2517 | desc->rqcfg.scctl = CCTRL0; |
2518 | desc->rqcfg.dcctl = CCTRL0; | |
b3040e40 JB |
2519 | desc->txd.tx_submit = pl330_tx_submit; |
2520 | ||
2521 | INIT_LIST_HEAD(&desc->node); | |
2522 | } | |
2523 | ||
2524 | /* Returns the number of descriptors added to the DMAC pool */ | |
e5887103 AK |
2525 | static int add_desc(struct list_head *pool, spinlock_t *lock, |
2526 | gfp_t flg, int count) | |
b3040e40 JB |
2527 | { |
2528 | struct dma_pl330_desc *desc; | |
2529 | unsigned long flags; | |
2530 | int i; | |
2531 | ||
0baf8f6a | 2532 | desc = kcalloc(count, sizeof(*desc), flg); |
b3040e40 JB |
2533 | if (!desc) |
2534 | return 0; | |
2535 | ||
e5887103 | 2536 | spin_lock_irqsave(lock, flags); |
b3040e40 JB |
2537 | |
2538 | for (i = 0; i < count; i++) { | |
2539 | _init_desc(&desc[i]); | |
e5887103 | 2540 | list_add_tail(&desc[i].node, pool); |
b3040e40 JB |
2541 | } |
2542 | ||
e5887103 | 2543 | spin_unlock_irqrestore(lock, flags); |
b3040e40 JB |
2544 | |
2545 | return count; | |
2546 | } | |
2547 | ||
e5887103 AK |
2548 | static struct dma_pl330_desc *pluck_desc(struct list_head *pool, |
2549 | spinlock_t *lock) | |
b3040e40 JB |
2550 | { |
2551 | struct dma_pl330_desc *desc = NULL; | |
2552 | unsigned long flags; | |
2553 | ||
e5887103 | 2554 | spin_lock_irqsave(lock, flags); |
b3040e40 | 2555 | |
e5887103 AK |
2556 | if (!list_empty(pool)) { |
2557 | desc = list_entry(pool->next, | |
b3040e40 JB |
2558 | struct dma_pl330_desc, node); |
2559 | ||
2560 | list_del_init(&desc->node); | |
2561 | ||
2562 | desc->status = PREP; | |
2563 | desc->txd.callback = NULL; | |
2564 | } | |
2565 | ||
e5887103 | 2566 | spin_unlock_irqrestore(lock, flags); |
b3040e40 JB |
2567 | |
2568 | return desc; | |
2569 | } | |
2570 | ||
2571 | static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) | |
2572 | { | |
f6f2421c | 2573 | struct pl330_dmac *pl330 = pch->dmac; |
cd072515 | 2574 | u8 *peri_id = pch->chan.private; |
b3040e40 JB |
2575 | struct dma_pl330_desc *desc; |
2576 | ||
2577 | /* Pluck one desc from the pool of DMAC */ | |
e5887103 | 2578 | desc = pluck_desc(&pl330->desc_pool, &pl330->pool_lock); |
b3040e40 JB |
2579 | |
2580 | /* If the DMAC pool is empty, alloc new */ | |
2581 | if (!desc) { | |
e5887103 AK |
2582 | DEFINE_SPINLOCK(lock); |
2583 | LIST_HEAD(pool); | |
b3040e40 | 2584 | |
e5887103 | 2585 | if (!add_desc(&pool, &lock, GFP_ATOMIC, 1)) |
b3040e40 | 2586 | return NULL; |
e5887103 AK |
2587 | |
2588 | desc = pluck_desc(&pool, &lock); | |
2589 | WARN_ON(!desc || !list_empty(&pool)); | |
b3040e40 JB |
2590 | } |
2591 | ||
2592 | /* Initialize the descriptor */ | |
2593 | desc->pchan = pch; | |
2594 | desc->txd.cookie = 0; | |
2595 | async_tx_ack(&desc->txd); | |
2596 | ||
9dc5a315 | 2597 | desc->peri = peri_id ? pch->chan.chan_id : 0; |
f6f2421c | 2598 | desc->rqcfg.pcfg = &pch->dmac->pcfg; |
b3040e40 JB |
2599 | |
2600 | dma_async_tx_descriptor_init(&desc->txd, &pch->chan); | |
2601 | ||
2602 | return desc; | |
2603 | } | |
2604 | ||
2605 | static inline void fill_px(struct pl330_xfer *px, | |
2606 | dma_addr_t dst, dma_addr_t src, size_t len) | |
2607 | { | |
b3040e40 JB |
2608 | px->bytes = len; |
2609 | px->dst_addr = dst; | |
2610 | px->src_addr = src; | |
2611 | } | |
2612 | ||
2613 | static struct dma_pl330_desc * | |
2614 | __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, | |
2615 | dma_addr_t src, size_t len) | |
2616 | { | |
2617 | struct dma_pl330_desc *desc = pl330_get_desc(pch); | |
2618 | ||
2619 | if (!desc) { | |
f6f2421c | 2620 | dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", |
b3040e40 JB |
2621 | __func__, __LINE__); |
2622 | return NULL; | |
2623 | } | |
2624 | ||
2625 | /* | |
2626 | * Ideally we should lookout for reqs bigger than | |
2627 | * those that can be programmed with 256 bytes of | |
2628 | * MC buffer, but considering a req size is seldom | |
2629 | * going to be word-unaligned and more than 200MB, | |
2630 | * we take it easy. | |
2631 | * Also, should the limit is reached we'd rather | |
2632 | * have the platform increase MC buffer size than | |
2633 | * complicating this API driver. | |
2634 | */ | |
2635 | fill_px(&desc->px, dst, src, len); | |
2636 | ||
2637 | return desc; | |
2638 | } | |
2639 | ||
2640 | /* Call after fixing burst size */ | |
2641 | static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) | |
2642 | { | |
2643 | struct dma_pl330_chan *pch = desc->pchan; | |
f6f2421c | 2644 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 JB |
2645 | int burst_len; |
2646 | ||
f6f2421c | 2647 | burst_len = pl330->pcfg.data_bus_width / 8; |
c27f9556 | 2648 | burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan; |
b3040e40 JB |
2649 | burst_len >>= desc->rqcfg.brst_size; |
2650 | ||
2651 | /* src/dst_burst_len can't be more than 16 */ | |
1d48745b FMH |
2652 | if (burst_len > PL330_MAX_BURST) |
2653 | burst_len = PL330_MAX_BURST; | |
b3040e40 JB |
2654 | |
2655 | return burst_len; | |
2656 | } | |
2657 | ||
42bc9cf4 BK |
2658 | static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( |
2659 | struct dma_chan *chan, dma_addr_t dma_addr, size_t len, | |
185ecb5f | 2660 | size_t period_len, enum dma_transfer_direction direction, |
31c1e5a1 | 2661 | unsigned long flags) |
42bc9cf4 | 2662 | { |
fc514460 | 2663 | struct dma_pl330_desc *desc = NULL, *first = NULL; |
42bc9cf4 | 2664 | struct dma_pl330_chan *pch = to_pchan(chan); |
f6f2421c | 2665 | struct pl330_dmac *pl330 = pch->dmac; |
fc514460 | 2666 | unsigned int i; |
42bc9cf4 BK |
2667 | dma_addr_t dst; |
2668 | dma_addr_t src; | |
2669 | ||
fc514460 | 2670 | if (len % period_len != 0) |
42bc9cf4 | 2671 | return NULL; |
42bc9cf4 | 2672 | |
fc514460 | 2673 | if (!is_slave_direction(direction)) { |
f6f2421c | 2674 | dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n", |
42bc9cf4 BK |
2675 | __func__, __LINE__); |
2676 | return NULL; | |
2677 | } | |
2678 | ||
445897cb VK |
2679 | pl330_config_write(chan, &pch->slave_config, direction); |
2680 | ||
4d6d74e2 RM |
2681 | if (!pl330_prep_slave_fifo(pch, direction)) |
2682 | return NULL; | |
2683 | ||
fc514460 LPC |
2684 | for (i = 0; i < len / period_len; i++) { |
2685 | desc = pl330_get_desc(pch); | |
2686 | if (!desc) { | |
f6f2421c | 2687 | dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", |
fc514460 | 2688 | __func__, __LINE__); |
42bc9cf4 | 2689 | |
fc514460 LPC |
2690 | if (!first) |
2691 | return NULL; | |
2692 | ||
f6f2421c | 2693 | spin_lock_irqsave(&pl330->pool_lock, flags); |
fc514460 LPC |
2694 | |
2695 | while (!list_empty(&first->node)) { | |
2696 | desc = list_entry(first->node.next, | |
2697 | struct dma_pl330_desc, node); | |
f6f2421c | 2698 | list_move_tail(&desc->node, &pl330->desc_pool); |
fc514460 LPC |
2699 | } |
2700 | ||
f6f2421c | 2701 | list_move_tail(&first->node, &pl330->desc_pool); |
fc514460 | 2702 | |
f6f2421c | 2703 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
42bc9cf4 | 2704 | |
fc514460 LPC |
2705 | return NULL; |
2706 | } | |
2707 | ||
2708 | switch (direction) { | |
2709 | case DMA_MEM_TO_DEV: | |
2710 | desc->rqcfg.src_inc = 1; | |
2711 | desc->rqcfg.dst_inc = 0; | |
fc514460 | 2712 | src = dma_addr; |
4d6d74e2 | 2713 | dst = pch->fifo_dma; |
fc514460 LPC |
2714 | break; |
2715 | case DMA_DEV_TO_MEM: | |
2716 | desc->rqcfg.src_inc = 0; | |
2717 | desc->rqcfg.dst_inc = 1; | |
4d6d74e2 | 2718 | src = pch->fifo_dma; |
fc514460 LPC |
2719 | dst = dma_addr; |
2720 | break; | |
2721 | default: | |
2722 | break; | |
2723 | } | |
2724 | ||
9dc5a315 | 2725 | desc->rqtype = direction; |
fc514460 | 2726 | desc->rqcfg.brst_size = pch->burst_sz; |
1d48745b | 2727 | desc->rqcfg.brst_len = pch->burst_len; |
aee4d1fa | 2728 | desc->bytes_requested = period_len; |
fc514460 LPC |
2729 | fill_px(&desc->px, dst, src, period_len); |
2730 | ||
2731 | if (!first) | |
2732 | first = desc; | |
2733 | else | |
2734 | list_add_tail(&desc->node, &first->node); | |
2735 | ||
2736 | dma_addr += period_len; | |
2737 | } | |
2738 | ||
2739 | if (!desc) | |
2740 | return NULL; | |
2741 | ||
2742 | pch->cyclic = true; | |
2743 | desc->txd.flags = flags; | |
42bc9cf4 BK |
2744 | |
2745 | return &desc->txd; | |
2746 | } | |
2747 | ||
b3040e40 JB |
2748 | static struct dma_async_tx_descriptor * |
2749 | pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, | |
2750 | dma_addr_t src, size_t len, unsigned long flags) | |
2751 | { | |
2752 | struct dma_pl330_desc *desc; | |
2753 | struct dma_pl330_chan *pch = to_pchan(chan); | |
f5636854 | 2754 | struct pl330_dmac *pl330; |
b3040e40 JB |
2755 | int burst; |
2756 | ||
4e0e6109 | 2757 | if (unlikely(!pch || !len)) |
b3040e40 JB |
2758 | return NULL; |
2759 | ||
f5636854 MS |
2760 | pl330 = pch->dmac; |
2761 | ||
b3040e40 JB |
2762 | desc = __pl330_prep_dma_memcpy(pch, dst, src, len); |
2763 | if (!desc) | |
2764 | return NULL; | |
2765 | ||
2766 | desc->rqcfg.src_inc = 1; | |
2767 | desc->rqcfg.dst_inc = 1; | |
9dc5a315 | 2768 | desc->rqtype = DMA_MEM_TO_MEM; |
b3040e40 JB |
2769 | |
2770 | /* Select max possible burst size */ | |
f6f2421c | 2771 | burst = pl330->pcfg.data_bus_width / 8; |
b3040e40 | 2772 | |
137bd110 JM |
2773 | /* |
2774 | * Make sure we use a burst size that aligns with all the memcpy | |
2775 | * parameters because our DMA programming algorithm doesn't cope with | |
2776 | * transfers which straddle an entry in the DMA device's MFIFO. | |
2777 | */ | |
2778 | while ((src | dst | len) & (burst - 1)) | |
b3040e40 | 2779 | burst /= 2; |
b3040e40 JB |
2780 | |
2781 | desc->rqcfg.brst_size = 0; | |
2782 | while (burst != (1 << desc->rqcfg.brst_size)) | |
2783 | desc->rqcfg.brst_size++; | |
2784 | ||
137bd110 JM |
2785 | /* |
2786 | * If burst size is smaller than bus width then make sure we only | |
2787 | * transfer one at a time to avoid a burst stradling an MFIFO entry. | |
2788 | */ | |
2789 | if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width) | |
2790 | desc->rqcfg.brst_len = 1; | |
2791 | ||
b3040e40 | 2792 | desc->rqcfg.brst_len = get_burst_len(desc, len); |
ae128293 | 2793 | desc->bytes_requested = len; |
b3040e40 JB |
2794 | |
2795 | desc->txd.flags = flags; | |
2796 | ||
2797 | return &desc->txd; | |
2798 | } | |
2799 | ||
f6f2421c | 2800 | static void __pl330_giveback_desc(struct pl330_dmac *pl330, |
52a9d179 CP |
2801 | struct dma_pl330_desc *first) |
2802 | { | |
2803 | unsigned long flags; | |
2804 | struct dma_pl330_desc *desc; | |
2805 | ||
2806 | if (!first) | |
2807 | return; | |
2808 | ||
f6f2421c | 2809 | spin_lock_irqsave(&pl330->pool_lock, flags); |
52a9d179 CP |
2810 | |
2811 | while (!list_empty(&first->node)) { | |
2812 | desc = list_entry(first->node.next, | |
2813 | struct dma_pl330_desc, node); | |
f6f2421c | 2814 | list_move_tail(&desc->node, &pl330->desc_pool); |
52a9d179 CP |
2815 | } |
2816 | ||
f6f2421c | 2817 | list_move_tail(&first->node, &pl330->desc_pool); |
52a9d179 | 2818 | |
f6f2421c | 2819 | spin_unlock_irqrestore(&pl330->pool_lock, flags); |
52a9d179 CP |
2820 | } |
2821 | ||
b3040e40 JB |
2822 | static struct dma_async_tx_descriptor * |
2823 | pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, | |
db8196df | 2824 | unsigned int sg_len, enum dma_transfer_direction direction, |
185ecb5f | 2825 | unsigned long flg, void *context) |
b3040e40 JB |
2826 | { |
2827 | struct dma_pl330_desc *first, *desc = NULL; | |
2828 | struct dma_pl330_chan *pch = to_pchan(chan); | |
b3040e40 | 2829 | struct scatterlist *sg; |
1b9bb715 | 2830 | int i; |
b3040e40 | 2831 | |
cd072515 | 2832 | if (unlikely(!pch || !sgl || !sg_len)) |
b3040e40 JB |
2833 | return NULL; |
2834 | ||
445897cb VK |
2835 | pl330_config_write(chan, &pch->slave_config, direction); |
2836 | ||
4d6d74e2 RM |
2837 | if (!pl330_prep_slave_fifo(pch, direction)) |
2838 | return NULL; | |
b3040e40 JB |
2839 | |
2840 | first = NULL; | |
2841 | ||
2842 | for_each_sg(sgl, sg, sg_len, i) { | |
2843 | ||
2844 | desc = pl330_get_desc(pch); | |
2845 | if (!desc) { | |
f6f2421c | 2846 | struct pl330_dmac *pl330 = pch->dmac; |
b3040e40 | 2847 | |
f6f2421c | 2848 | dev_err(pch->dmac->ddma.dev, |
b3040e40 JB |
2849 | "%s:%d Unable to fetch desc\n", |
2850 | __func__, __LINE__); | |
f6f2421c | 2851 | __pl330_giveback_desc(pl330, first); |
b3040e40 JB |
2852 | |
2853 | return NULL; | |
2854 | } | |
2855 | ||
2856 | if (!first) | |
2857 | first = desc; | |
2858 | else | |
2859 | list_add_tail(&desc->node, &first->node); | |
2860 | ||
db8196df | 2861 | if (direction == DMA_MEM_TO_DEV) { |
b3040e40 JB |
2862 | desc->rqcfg.src_inc = 1; |
2863 | desc->rqcfg.dst_inc = 0; | |
4d6d74e2 RM |
2864 | fill_px(&desc->px, pch->fifo_dma, sg_dma_address(sg), |
2865 | sg_dma_len(sg)); | |
b3040e40 JB |
2866 | } else { |
2867 | desc->rqcfg.src_inc = 0; | |
2868 | desc->rqcfg.dst_inc = 1; | |
4d6d74e2 RM |
2869 | fill_px(&desc->px, sg_dma_address(sg), pch->fifo_dma, |
2870 | sg_dma_len(sg)); | |
b3040e40 JB |
2871 | } |
2872 | ||
1b9bb715 | 2873 | desc->rqcfg.brst_size = pch->burst_sz; |
1d48745b | 2874 | desc->rqcfg.brst_len = pch->burst_len; |
9dc5a315 | 2875 | desc->rqtype = direction; |
aee4d1fa | 2876 | desc->bytes_requested = sg_dma_len(sg); |
b3040e40 JB |
2877 | } |
2878 | ||
2879 | /* Return the last desc in the chain */ | |
2880 | desc->txd.flags = flg; | |
2881 | return &desc->txd; | |
2882 | } | |
2883 | ||
2884 | static irqreturn_t pl330_irq_handler(int irq, void *data) | |
2885 | { | |
2886 | if (pl330_update(data)) | |
2887 | return IRQ_HANDLED; | |
2888 | else | |
2889 | return IRQ_NONE; | |
2890 | } | |
2891 | ||
ca38ff13 LPC |
2892 | #define PL330_DMA_BUSWIDTHS \ |
2893 | BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ | |
2894 | BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ | |
2895 | BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ | |
2896 | BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ | |
2897 | BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) | |
2898 | ||
b816ccc5 KK |
2899 | /* |
2900 | * Runtime PM callbacks are provided by amba/bus.c driver. | |
2901 | * | |
2902 | * It is assumed here that IRQ safe runtime PM is chosen in probe and amba | |
2903 | * bus driver will only disable/enable the clock in runtime PM callbacks. | |
2904 | */ | |
2905 | static int __maybe_unused pl330_suspend(struct device *dev) | |
2906 | { | |
2907 | struct amba_device *pcdev = to_amba_device(dev); | |
2908 | ||
2909 | pm_runtime_disable(dev); | |
2910 | ||
2911 | if (!pm_runtime_status_suspended(dev)) { | |
2912 | /* amba did not disable the clock */ | |
2913 | amba_pclk_disable(pcdev); | |
2914 | } | |
2915 | amba_pclk_unprepare(pcdev); | |
2916 | ||
2917 | return 0; | |
2918 | } | |
2919 | ||
2920 | static int __maybe_unused pl330_resume(struct device *dev) | |
2921 | { | |
2922 | struct amba_device *pcdev = to_amba_device(dev); | |
2923 | int ret; | |
2924 | ||
2925 | ret = amba_pclk_prepare(pcdev); | |
2926 | if (ret) | |
2927 | return ret; | |
2928 | ||
2929 | if (!pm_runtime_status_suspended(dev)) | |
2930 | ret = amba_pclk_enable(pcdev); | |
2931 | ||
2932 | pm_runtime_enable(dev); | |
2933 | ||
2934 | return ret; | |
2935 | } | |
2936 | ||
2937 | static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume); | |
2938 | ||
463a1f8b | 2939 | static int |
aa25afad | 2940 | pl330_probe(struct amba_device *adev, const struct amba_id *id) |
b3040e40 | 2941 | { |
f6f2421c LPC |
2942 | struct pl330_config *pcfg; |
2943 | struct pl330_dmac *pl330; | |
0b94c577 | 2944 | struct dma_pl330_chan *pch, *_p; |
b3040e40 JB |
2945 | struct dma_device *pd; |
2946 | struct resource *res; | |
2947 | int i, ret, irq; | |
4e0e6109 | 2948 | int num_chan; |
271e1b86 | 2949 | struct device_node *np = adev->dev.of_node; |
b3040e40 | 2950 | |
64113016 RK |
2951 | ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); |
2952 | if (ret) | |
2953 | return ret; | |
2954 | ||
b3040e40 | 2955 | /* Allocate a new DMAC and its Channels */ |
f6f2421c | 2956 | pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL); |
aef94fea | 2957 | if (!pl330) |
b3040e40 | 2958 | return -ENOMEM; |
b3040e40 | 2959 | |
cee42392 AJ |
2960 | pd = &pl330->ddma; |
2961 | pd->dev = &adev->dev; | |
2962 | ||
e8bb4673 | 2963 | pl330->mcbufsz = 0; |
b3040e40 | 2964 | |
271e1b86 AK |
2965 | /* get quirk */ |
2966 | for (i = 0; i < ARRAY_SIZE(of_quirks); i++) | |
2967 | if (of_property_read_bool(np, of_quirks[i].quirk)) | |
2968 | pl330->quirks |= of_quirks[i].id; | |
2969 | ||
b3040e40 | 2970 | res = &adev->res; |
f6f2421c LPC |
2971 | pl330->base = devm_ioremap_resource(&adev->dev, res); |
2972 | if (IS_ERR(pl330->base)) | |
2973 | return PTR_ERR(pl330->base); | |
b3040e40 | 2974 | |
f6f2421c | 2975 | amba_set_drvdata(adev, pl330); |
a2f5203f | 2976 | |
02808b42 | 2977 | for (i = 0; i < AMBA_NR_IRQS; i++) { |
e98b3caf MS |
2978 | irq = adev->irq[i]; |
2979 | if (irq) { | |
2980 | ret = devm_request_irq(&adev->dev, irq, | |
2981 | pl330_irq_handler, 0, | |
f6f2421c | 2982 | dev_name(&adev->dev), pl330); |
e98b3caf MS |
2983 | if (ret) |
2984 | return ret; | |
2985 | } else { | |
2986 | break; | |
2987 | } | |
2988 | } | |
b3040e40 | 2989 | |
f6f2421c LPC |
2990 | pcfg = &pl330->pcfg; |
2991 | ||
2992 | pcfg->periph_id = adev->periphid; | |
2993 | ret = pl330_add(pl330); | |
b3040e40 | 2994 | if (ret) |
173e838c | 2995 | return ret; |
b3040e40 | 2996 | |
f6f2421c LPC |
2997 | INIT_LIST_HEAD(&pl330->desc_pool); |
2998 | spin_lock_init(&pl330->pool_lock); | |
b3040e40 JB |
2999 | |
3000 | /* Create a descriptor pool of default size */ | |
e5887103 AK |
3001 | if (!add_desc(&pl330->desc_pool, &pl330->pool_lock, |
3002 | GFP_KERNEL, NR_DEFAULT_DESC)) | |
b3040e40 JB |
3003 | dev_warn(&adev->dev, "unable to allocate desc\n"); |
3004 | ||
b3040e40 JB |
3005 | INIT_LIST_HEAD(&pd->channels); |
3006 | ||
3007 | /* Initialize channel parameters */ | |
e8bb4673 | 3008 | num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan); |
c8473828 | 3009 | |
f6f2421c | 3010 | pl330->num_peripherals = num_chan; |
70cbb163 | 3011 | |
6396bb22 | 3012 | pl330->peripherals = kcalloc(num_chan, sizeof(*pch), GFP_KERNEL); |
f6f2421c | 3013 | if (!pl330->peripherals) { |
61c6e753 | 3014 | ret = -ENOMEM; |
e4d43c17 | 3015 | goto probe_err2; |
61c6e753 | 3016 | } |
b3040e40 | 3017 | |
4e0e6109 | 3018 | for (i = 0; i < num_chan; i++) { |
f6f2421c | 3019 | pch = &pl330->peripherals[i]; |
b3040e40 | 3020 | |
e8bb4673 | 3021 | pch->chan.private = adev->dev.of_node; |
04abf5da | 3022 | INIT_LIST_HEAD(&pch->submitted_list); |
b3040e40 | 3023 | INIT_LIST_HEAD(&pch->work_list); |
39ff8613 | 3024 | INIT_LIST_HEAD(&pch->completed_list); |
b3040e40 | 3025 | spin_lock_init(&pch->lock); |
65ad6060 | 3026 | pch->thread = NULL; |
b3040e40 | 3027 | pch->chan.device = pd; |
f6f2421c | 3028 | pch->dmac = pl330; |
4d6d74e2 | 3029 | pch->dir = DMA_NONE; |
b3040e40 JB |
3030 | |
3031 | /* Add the channel to the DMAC list */ | |
b3040e40 JB |
3032 | list_add_tail(&pch->chan.device_node, &pd->channels); |
3033 | } | |
3034 | ||
e8bb4673 MS |
3035 | dma_cap_set(DMA_MEMCPY, pd->cap_mask); |
3036 | if (pcfg->num_peri) { | |
3037 | dma_cap_set(DMA_SLAVE, pd->cap_mask); | |
3038 | dma_cap_set(DMA_CYCLIC, pd->cap_mask); | |
3039 | dma_cap_set(DMA_PRIVATE, pd->cap_mask); | |
93ed5544 | 3040 | } |
b3040e40 JB |
3041 | |
3042 | pd->device_alloc_chan_resources = pl330_alloc_chan_resources; | |
3043 | pd->device_free_chan_resources = pl330_free_chan_resources; | |
3044 | pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; | |
42bc9cf4 | 3045 | pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; |
b3040e40 JB |
3046 | pd->device_tx_status = pl330_tx_status; |
3047 | pd->device_prep_slave_sg = pl330_prep_slave_sg; | |
740aa957 | 3048 | pd->device_config = pl330_config; |
88987d2c | 3049 | pd->device_pause = pl330_pause; |
740aa957 | 3050 | pd->device_terminate_all = pl330_terminate_all; |
b3040e40 | 3051 | pd->device_issue_pending = pl330_issue_pending; |
dcabe456 MR |
3052 | pd->src_addr_widths = PL330_DMA_BUSWIDTHS; |
3053 | pd->dst_addr_widths = PL330_DMA_BUSWIDTHS; | |
3054 | pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); | |
e3f329c6 | 3055 | pd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; |
86a8ce7d SL |
3056 | pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ? |
3057 | 1 : PL330_MAX_BURST); | |
b3040e40 JB |
3058 | |
3059 | ret = dma_async_device_register(pd); | |
3060 | if (ret) { | |
3061 | dev_err(&adev->dev, "unable to register DMAC\n"); | |
0b94c577 PV |
3062 | goto probe_err3; |
3063 | } | |
3064 | ||
3065 | if (adev->dev.of_node) { | |
3066 | ret = of_dma_controller_register(adev->dev.of_node, | |
f6f2421c | 3067 | of_dma_pl330_xlate, pl330); |
0b94c577 PV |
3068 | if (ret) { |
3069 | dev_err(&adev->dev, | |
3070 | "unable to register DMA to the generic DT DMA helpers\n"); | |
3071 | } | |
b3040e40 | 3072 | } |
b714b84e | 3073 | |
f6f2421c | 3074 | adev->dev.dma_parms = &pl330->dma_parms; |
b714b84e | 3075 | |
dbaf6d85 VK |
3076 | /* |
3077 | * This is the limit for transfers with a buswidth of 1, larger | |
3078 | * buswidths will have larger limits. | |
3079 | */ | |
3080 | ret = dma_set_max_seg_size(&adev->dev, 1900800); | |
3081 | if (ret) | |
3082 | dev_err(&adev->dev, "unable to set the seg size\n"); | |
3083 | ||
b3040e40 | 3084 | |
b3040e40 | 3085 | dev_info(&adev->dev, |
1f0a5cbf | 3086 | "Loaded driver for PL330 DMAC-%x\n", adev->periphid); |
b3040e40 JB |
3087 | dev_info(&adev->dev, |
3088 | "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", | |
f6f2421c LPC |
3089 | pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan, |
3090 | pcfg->num_peri, pcfg->num_events); | |
b3040e40 | 3091 | |
ae43b328 KK |
3092 | pm_runtime_irq_safe(&adev->dev); |
3093 | pm_runtime_use_autosuspend(&adev->dev); | |
3094 | pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY); | |
3095 | pm_runtime_mark_last_busy(&adev->dev); | |
3096 | pm_runtime_put_autosuspend(&adev->dev); | |
3097 | ||
b3040e40 | 3098 | return 0; |
0b94c577 | 3099 | probe_err3: |
0b94c577 | 3100 | /* Idle the DMAC */ |
f6f2421c | 3101 | list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, |
0b94c577 PV |
3102 | chan.device_node) { |
3103 | ||
3104 | /* Remove the channel */ | |
3105 | list_del(&pch->chan.device_node); | |
3106 | ||
3107 | /* Flush the channel */ | |
0f5ebabd | 3108 | if (pch->thread) { |
740aa957 | 3109 | pl330_terminate_all(&pch->chan); |
0f5ebabd KK |
3110 | pl330_free_chan_resources(&pch->chan); |
3111 | } | |
0b94c577 | 3112 | } |
b3040e40 | 3113 | probe_err2: |
f6f2421c | 3114 | pl330_del(pl330); |
b3040e40 JB |
3115 | |
3116 | return ret; | |
3117 | } | |
3118 | ||
4bf27b8b | 3119 | static int pl330_remove(struct amba_device *adev) |
b3040e40 | 3120 | { |
f6f2421c | 3121 | struct pl330_dmac *pl330 = amba_get_drvdata(adev); |
b3040e40 | 3122 | struct dma_pl330_chan *pch, *_p; |
46cf94d6 | 3123 | int i, irq; |
b3040e40 | 3124 | |
ae43b328 KK |
3125 | pm_runtime_get_noresume(pl330->ddma.dev); |
3126 | ||
0b94c577 PV |
3127 | if (adev->dev.of_node) |
3128 | of_dma_controller_free(adev->dev.of_node); | |
421da89a | 3129 | |
46cf94d6 VK |
3130 | for (i = 0; i < AMBA_NR_IRQS; i++) { |
3131 | irq = adev->irq[i]; | |
ebcdaee4 JPB |
3132 | if (irq) |
3133 | devm_free_irq(&adev->dev, irq, pl330); | |
46cf94d6 VK |
3134 | } |
3135 | ||
f6f2421c | 3136 | dma_async_device_unregister(&pl330->ddma); |
b3040e40 JB |
3137 | |
3138 | /* Idle the DMAC */ | |
f6f2421c | 3139 | list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, |
b3040e40 JB |
3140 | chan.device_node) { |
3141 | ||
3142 | /* Remove the channel */ | |
3143 | list_del(&pch->chan.device_node); | |
3144 | ||
3145 | /* Flush the channel */ | |
6e4a2a83 | 3146 | if (pch->thread) { |
740aa957 | 3147 | pl330_terminate_all(&pch->chan); |
6e4a2a83 KK |
3148 | pl330_free_chan_resources(&pch->chan); |
3149 | } | |
b3040e40 JB |
3150 | } |
3151 | ||
f6f2421c | 3152 | pl330_del(pl330); |
b3040e40 | 3153 | |
b3040e40 JB |
3154 | return 0; |
3155 | } | |
3156 | ||
b753351e | 3157 | static const struct amba_id pl330_ids[] = { |
b3040e40 JB |
3158 | { |
3159 | .id = 0x00041330, | |
3160 | .mask = 0x000fffff, | |
3161 | }, | |
3162 | { 0, 0 }, | |
3163 | }; | |
3164 | ||
e8fa516a DM |
3165 | MODULE_DEVICE_TABLE(amba, pl330_ids); |
3166 | ||
b3040e40 JB |
3167 | static struct amba_driver pl330_driver = { |
3168 | .drv = { | |
3169 | .owner = THIS_MODULE, | |
3170 | .name = "dma-pl330", | |
b816ccc5 | 3171 | .pm = &pl330_pm, |
b3040e40 JB |
3172 | }, |
3173 | .id_table = pl330_ids, | |
3174 | .probe = pl330_probe, | |
3175 | .remove = pl330_remove, | |
3176 | }; | |
3177 | ||
9e5ed094 | 3178 | module_amba_driver(pl330_driver); |
b3040e40 | 3179 | |
046209f6 | 3180 | MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>"); |
b3040e40 JB |
3181 | MODULE_DESCRIPTION("API Driver for PL330 DMAC"); |
3182 | MODULE_LICENSE("GPL"); |