[thirdparty/linux.git] / drivers / firmware / qcom_scm.h

/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.
 */
#ifndef __QCOM_SCM_INT_H
#define __QCOM_SCM_INT_H

enum qcom_scm_convention {
	SMC_CONVENTION_UNKNOWN,
	SMC_CONVENTION_LEGACY,
	SMC_CONVENTION_ARM_32,
	SMC_CONVENTION_ARM_64,
};

extern enum qcom_scm_convention qcom_scm_convention;

#define MAX_QCOM_SCM_ARGS 10
#define MAX_QCOM_SCM_RETS 3

enum qcom_scm_arg_types {
	QCOM_SCM_VAL,
	QCOM_SCM_RO,
	QCOM_SCM_RW,
	QCOM_SCM_BUFVAL,
};

#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
			   (((a) & 0x3) << 4) | \
			   (((b) & 0x3) << 6) | \
			   (((c) & 0x3) << 8) | \
			   (((d) & 0x3) << 10) | \
			   (((e) & 0x3) << 12) | \
			   (((f) & 0x3) << 14) | \
			   (((g) & 0x3) << 16) | \
			   (((h) & 0x3) << 18) | \
			   (((i) & 0x3) << 20) | \
			   (((j) & 0x3) << 22) | \
			   ((num) & 0xf))

#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)


/**
 * struct qcom_scm_desc
 * @arginfo:	Metadata describing the arguments in args[]
 * @args:	The array of arguments for the secure syscall
 */
struct qcom_scm_desc {
	u32 svc;
	u32 cmd;
	u32 arginfo;
	u64 args[MAX_QCOM_SCM_ARGS];
	u32 owner;
};

/**
 * struct qcom_scm_res
 * @result:	The values returned by the secure syscall
 */
struct qcom_scm_res {
	u64 result[MAX_QCOM_SCM_RETS];
};

#define SCM_SMC_FNID(s, c)	((((s) & 0xFF) << 8) | ((c) & 0xFF))
extern int scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
			struct qcom_scm_res *res, bool atomic);

#define SCM_LEGACY_FNID(s, c)	(((s) << 10) | ((c) & 0x3ff))
extern int scm_legacy_call_atomic(struct device *dev,
				  const struct qcom_scm_desc *desc,
				  struct qcom_scm_res *res);
extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
			   struct qcom_scm_res *res);

#define QCOM_SCM_SVC_BOOT		0x01
#define QCOM_SCM_BOOT_SET_ADDR		0x01
#define QCOM_SCM_BOOT_TERMINATE_PC	0x02
#define QCOM_SCM_BOOT_SET_DLOAD_MODE	0x10
#define QCOM_SCM_BOOT_SET_REMOTE_STATE	0x0a
#define QCOM_SCM_FLUSH_FLAG_MASK	0x3

#define QCOM_SCM_SVC_PIL		0x02
#define QCOM_SCM_PIL_PAS_INIT_IMAGE	0x01
#define QCOM_SCM_PIL_PAS_MEM_SETUP	0x02
#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET	0x05
#define QCOM_SCM_PIL_PAS_SHUTDOWN	0x06
#define QCOM_SCM_PIL_PAS_IS_SUPPORTED	0x07
#define QCOM_SCM_PIL_PAS_MSS_RESET	0x0a

#define QCOM_SCM_SVC_IO			0x05
#define QCOM_SCM_IO_READ		0x01
#define QCOM_SCM_IO_WRITE		0x02

#define QCOM_SCM_SVC_INFO		0x06
#define QCOM_SCM_INFO_IS_CALL_AVAIL	0x01

#define QCOM_SCM_SVC_MP				0x0c
#define QCOM_SCM_MP_RESTORE_SEC_CFG		0x02
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE	0x03
#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT	0x04
#define QCOM_SCM_MP_ASSIGN			0x16

#define QCOM_SCM_SVC_OCMEM		0x0f
#define QCOM_SCM_OCMEM_LOCK_CMD		0x01
#define QCOM_SCM_OCMEM_UNLOCK_CMD	0x02

#define QCOM_SCM_SVC_HDCP		0x11
#define QCOM_SCM_HDCP_INVOKE		0x01

#define QCOM_SCM_SVC_SMMU_PROGRAM		0x15
#define QCOM_SCM_SMMU_CONFIG_ERRATA1		0x03
#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL	0x02

extern void __qcom_scm_init(void);

/* common error codes */
#define QCOM_SCM_V2_EBUSY	-12
#define QCOM_SCM_ENOMEM		-5
#define QCOM_SCM_EOPNOTSUPP	-4
#define QCOM_SCM_EINVAL_ADDR	-3
#define QCOM_SCM_EINVAL_ARG	-2
#define QCOM_SCM_ERROR		-1
#define QCOM_SCM_INTERRUPTED	1

static inline int qcom_scm_remap_error(int err)
{
	switch (err) {
	case QCOM_SCM_ERROR:
		return -EIO;
	case QCOM_SCM_EINVAL_ADDR:
	case QCOM_SCM_EINVAL_ARG:
		return -EINVAL;
	case QCOM_SCM_EOPNOTSUPP:
		return -EOPNOTSUPP;
	case QCOM_SCM_ENOMEM:
		return -ENOMEM;
	case QCOM_SCM_V2_EBUSY:
		return -EBUSY;
	}
	return -EINVAL;
}

#endif
Commit	Line	Data
97fb5e8d	1	/* SPDX-License-Identifier: GPL-2.0-only */
5443cc5f	2	/* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.
b6a1dfbc KG	3	*/
	4	#ifndef __QCOM_SCM_INT_H
	5	#define __QCOM_SCM_INT_H
9a434cee EB	6
	7	enum qcom_scm_convention {
	8	SMC_CONVENTION_UNKNOWN,
	9	SMC_CONVENTION_LEGACY,
	10	SMC_CONVENTION_ARM_32,
	11	SMC_CONVENTION_ARM_64,
	12	};
	13
	14	extern enum qcom_scm_convention qcom_scm_convention;
	15
57d3b816 EB	16	#define MAX_QCOM_SCM_ARGS 10
	17	#define MAX_QCOM_SCM_RETS 3
	18
	19	enum qcom_scm_arg_types {
	20	QCOM_SCM_VAL,
	21	QCOM_SCM_RO,
	22	QCOM_SCM_RW,
	23	QCOM_SCM_BUFVAL,
	24	};
	25
	26	#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
	27	(((a) & 0x3) << 4) \| \
	28	(((b) & 0x3) << 6) \| \
	29	(((c) & 0x3) << 8) \| \
	30	(((d) & 0x3) << 10) \| \
	31	(((e) & 0x3) << 12) \| \
	32	(((f) & 0x3) << 14) \| \
	33	(((g) & 0x3) << 16) \| \
	34	(((h) & 0x3) << 18) \| \
	35	(((i) & 0x3) << 20) \| \
	36	(((j) & 0x3) << 22) \| \
	37	((num) & 0xf))
	38
	39	#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
	40
	41
	42	/**
	43	* struct qcom_scm_desc
	44	* @arginfo: Metadata describing the arguments in args[]
	45	* @args: The array of arguments for the secure syscall
	46	*/
	47	struct qcom_scm_desc {
	48	u32 svc;
	49	u32 cmd;
	50	u32 arginfo;
	51	u64 args[MAX_QCOM_SCM_ARGS];
	52	u32 owner;
	53	};
	54
	55	/**
	56	* struct qcom_scm_res
	57	* @result: The values returned by the secure syscall
	58	*/
	59	struct qcom_scm_res {
	60	u64 result[MAX_QCOM_SCM_RETS];
	61	};
	62
9a434cee EB	63	#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) \| ((c) & 0xFF))
	64	extern int scm_smc_call(struct device dev, const struct qcom_scm_desc desc,
	65	struct qcom_scm_res *res, bool atomic);
	66
	67	#define SCM_LEGACY_FNID(s, c) (((s) << 10) \| ((c) & 0x3ff))
	68	extern int scm_legacy_call_atomic(struct device *dev,
	69	const struct qcom_scm_desc *desc,
	70	struct qcom_scm_res *res);
	71	extern int scm_legacy_call(struct device dev, const struct qcom_scm_desc desc,
	72	struct qcom_scm_res *res);
b6a1dfbc	73
65f0c90b EB	74	#define QCOM_SCM_SVC_BOOT 0x01
	75	#define QCOM_SCM_BOOT_SET_ADDR 0x01
	76	#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
	77	#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
	78	#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
65f0c90b EB	79	#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
	80
	81	#define QCOM_SCM_SVC_PIL 0x02
	82	#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
	83	#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
	84	#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
	85	#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
	86	#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
	87	#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
b6a1dfbc	88
65f0c90b EB	89	#define QCOM_SCM_SVC_IO 0x05
	90	#define QCOM_SCM_IO_READ 0x01
	91	#define QCOM_SCM_IO_WRITE 0x02
4e659dbe	92
65f0c90b EB	93	#define QCOM_SCM_SVC_INFO 0x06
65f0c90b EB	94	#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
9626b699	95
65f0c90b EB	96	#define QCOM_SCM_SVC_MP 0x0c
	97	#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
	98	#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
	99	#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
	100	#define QCOM_SCM_MP_ASSIGN 0x16
b0a1614f	101
65f0c90b EB	102	#define QCOM_SCM_SVC_OCMEM 0x0f
	103	#define QCOM_SCM_OCMEM_LOCK_CMD 0x01
	104	#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02
b0a1614f	105
65f0c90b EB	106	#define QCOM_SCM_SVC_HDCP 0x11
65f0c90b EB	107	#define QCOM_SCM_HDCP_INVOKE 0x01
65f0c90b EB	108
	109	#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
	110	#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
	111	#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
65f0c90b EB	112
65f0c90b EB	113	extern void __qcom_scm_init(void);
f01e90fe	114
b6a1dfbc	115	/* common error codes */
6b1751a8	116	#define QCOM_SCM_V2_EBUSY -12
b6a1dfbc KG	117	#define QCOM_SCM_ENOMEM -5
	118	#define QCOM_SCM_EOPNOTSUPP -4
	119	#define QCOM_SCM_EINVAL_ADDR -3
	120	#define QCOM_SCM_EINVAL_ARG -2
	121	#define QCOM_SCM_ERROR -1
	122	#define QCOM_SCM_INTERRUPTED 1
	123
11bdcee4 AG	124	static inline int qcom_scm_remap_error(int err)
	125	{
	126	switch (err) {
	127	case QCOM_SCM_ERROR:
	128	return -EIO;
	129	case QCOM_SCM_EINVAL_ADDR:
	130	case QCOM_SCM_EINVAL_ARG:
	131	return -EINVAL;
	132	case QCOM_SCM_EOPNOTSUPP:
	133	return -EOPNOTSUPP;
	134	case QCOM_SCM_ENOMEM:
	135	return -ENOMEM;
6b1751a8 KG	136	case QCOM_SCM_V2_EBUSY:
6b1751a8 KG	137	return -EBUSY;
11bdcee4 AG	138	}
	139	return -EINVAL;
	140	}
	141
b6a1dfbc	142	#endif