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Commit | Line | Data |
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6ded73aa MS |
1 | menu "FPGA support" |
2 | ||
6b245014 SDPP |
3 | config FPGA |
4 | bool | |
5 | ||
98d62e61 PB |
6 | config FPGA_ALTERA |
7 | bool "Enable Altera FPGA drivers" | |
8 | select FPGA | |
9 | help | |
10 | Say Y here to enable the Altera FPGA driver | |
11 | ||
12 | This provides basic infrastructure to support Altera FPGA devices. | |
13 | Enable Altera FPGA specific functions which includes bitstream | |
14 | (in BIT format), fpga and device validation. | |
15 | ||
fa23ba1a TFC |
16 | config FPGA_SOCFPGA |
17 | bool "Enable Gen5 and Arria10 common FPGA drivers" | |
18 | select FPGA_ALTERA | |
19 | help | |
20 | Say Y here to enable the Gen5 and Arria10 common FPGA driver | |
21 | ||
22 | This provides common functionality for Gen5 and Arria10 devices. | |
23 | ||
98d62e61 PB |
24 | config FPGA_CYCLON2 |
25 | bool "Enable Altera FPGA driver for Cyclone II" | |
26 | depends on FPGA_ALTERA | |
27 | help | |
28 | Say Y here to enable the Altera Cyclone II FPGA specific driver | |
29 | ||
30 | This provides common functionality for Altera Cyclone II devices. | |
31 | Enable FPGA driver for loading bitstream in BIT and BIN format | |
32 | on Altera Cyclone II device. | |
33 | ||
c41e660b ACH |
34 | config FPGA_STRATIX10 |
35 | bool "Enable Altera FPGA driver for Stratix 10" | |
36 | depends on TARGET_SOCFPGA_STRATIX10 | |
37 | select FPGA_ALTERA | |
38 | help | |
39 | Say Y here to enable the Altera Stratix 10 FPGA specific driver | |
40 | ||
41 | This provides common functionality for Altera Stratix 10 devices. | |
42 | Enable FPGA driver for writing bitstream into Altera Stratix10 | |
43 | device. | |
44 | ||
6b245014 SDPP |
45 | config FPGA_XILINX |
46 | bool "Enable Xilinx FPGA drivers" | |
47 | select FPGA | |
48 | help | |
49 | Enable Xilinx FPGA specific functions which includes bitstream | |
50 | (in BIT format), fpga and device validation. | |
51 | ||
52 | config FPGA_ZYNQMPPL | |
53 | bool "Enable Xilinx FPGA driver for ZynqMP" | |
54 | depends on FPGA_XILINX | |
55 | help | |
56 | Enable FPGA driver for loading bitstream in BIT and BIN format | |
57 | on Xilinx Zynq UltraScale+ (ZynqMP) device. | |
58 | ||
f4158346 | 59 | config FPGA_SPARTAN3 |
a225f810 | 60 | bool "Enable Spartan3 FPGA driver" |
25d63a36 | 61 | depends on FPGA_XILINX |
a225f810 MS |
62 | help |
63 | Enable Spartan3 FPGA driver for loading in BIT format. | |
f4158346 | 64 | |
25d63a36 RH |
65 | config FPGA_VIRTEX2 |
66 | bool "Enable Xilinx Virtex-II and later FPGA driver" | |
67 | depends on FPGA_XILINX | |
68 | help | |
69 | Enable Virtex-II FPGA driver for loading in BIT format. This driver | |
70 | also supports many newer Xilinx FPGA families. | |
71 | ||
3990c9d6 | 72 | config FPGA_ZYNQPL |
a225f810 MS |
73 | bool "Enable Xilinx FPGA for Zynq" |
74 | depends on ARCH_ZYNQ | |
75 | help | |
76 | Enable FPGA driver for loading bitstream in BIT and BIN format | |
77 | on Xilinx Zynq devices. | |
3990c9d6 | 78 | |
6ded73aa | 79 | endmenu |