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Commit | Line | Data |
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e2211743 WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
e2211743 WD |
6 | */ |
7 | ||
f6555d90 | 8 | /* Generic FPGA support */ |
e2211743 WD |
9 | #include <common.h> /* core U-Boot definitions */ |
10 | #include <xilinx.h> /* xilinx specific definitions */ | |
11 | #include <altera.h> /* altera specific definitions */ | |
3b8ac464 | 12 | #include <lattice.h> |
e2211743 | 13 | |
e2211743 WD |
14 | /* Local definitions */ |
15 | #ifndef CONFIG_MAX_FPGA_DEVICES | |
16 | #define CONFIG_MAX_FPGA_DEVICES 5 | |
17 | #endif | |
18 | ||
e2211743 | 19 | /* Local static data */ |
e2211743 WD |
20 | static int next_desc = FPGA_INVALID_DEVICE; |
21 | static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES]; | |
22 | ||
f6555d90 MS |
23 | /* |
24 | * fpga_no_sup | |
e2211743 WD |
25 | * 'no support' message function |
26 | */ | |
f6555d90 | 27 | static void fpga_no_sup(char *fn, char *msg) |
e2211743 | 28 | { |
f6555d90 MS |
29 | if (fn && msg) |
30 | printf("%s: No support for %s.\n", fn, msg); | |
31 | else if (msg) | |
32 | printf("No support for %s.\n", msg); | |
33 | else | |
62a3b7dd | 34 | printf("No FPGA support!\n"); |
e2211743 WD |
35 | } |
36 | ||
37 | ||
38 | /* fpga_get_desc | |
39 | * map a device number to a descriptor | |
40 | */ | |
ebd322de | 41 | const fpga_desc *const fpga_get_desc(int devnum) |
e2211743 | 42 | { |
f6555d90 | 43 | fpga_desc *desc = (fpga_desc *)NULL; |
e2211743 | 44 | |
f6555d90 | 45 | if ((devnum >= 0) && (devnum < next_desc)) { |
e2211743 | 46 | desc = &desc_table[devnum]; |
f6555d90 MS |
47 | debug("%s: found fpga descriptor #%d @ 0x%p\n", |
48 | __func__, devnum, desc); | |
e2211743 WD |
49 | } |
50 | ||
51 | return desc; | |
52 | } | |
53 | ||
f6555d90 MS |
54 | /* |
55 | * fpga_validate | |
e2211743 WD |
56 | * generic parameter checking code |
57 | */ | |
6631db47 MS |
58 | const fpga_desc *const fpga_validate(int devnum, const void *buf, |
59 | size_t bsize, char *fn) | |
e2211743 | 60 | { |
f6555d90 | 61 | const fpga_desc *desc = fpga_get_desc(devnum); |
e2211743 | 62 | |
f6555d90 MS |
63 | if (!desc) |
64 | printf("%s: Invalid device number %d\n", fn, devnum); | |
e2211743 | 65 | |
f6555d90 MS |
66 | if (!buf) { |
67 | printf("%s: Null buffer.\n", fn); | |
e2211743 WD |
68 | return (fpga_desc * const)NULL; |
69 | } | |
e2211743 WD |
70 | return desc; |
71 | } | |
72 | ||
f6555d90 MS |
73 | /* |
74 | * fpga_dev_info | |
e2211743 WD |
75 | * generic multiplexing code |
76 | */ | |
f6555d90 | 77 | static int fpga_dev_info(int devnum) |
e2211743 | 78 | { |
f6555d90 MS |
79 | int ret_val = FPGA_FAIL; /* assume failure */ |
80 | const fpga_desc * const desc = fpga_get_desc(devnum); | |
e2211743 | 81 | |
f6555d90 MS |
82 | if (desc) { |
83 | debug("%s: Device Descriptor @ 0x%p\n", | |
84 | __func__, desc->devdesc); | |
e2211743 | 85 | |
f6555d90 | 86 | switch (desc->devtype) { |
e2211743 | 87 | case fpga_xilinx: |
0133502e | 88 | #if defined(CONFIG_FPGA_XILINX) |
f6555d90 MS |
89 | printf("Xilinx Device\nDescriptor @ 0x%p\n", desc); |
90 | ret_val = xilinx_info(desc->devdesc); | |
e2211743 | 91 | #else |
f6555d90 | 92 | fpga_no_sup((char *)__func__, "Xilinx devices"); |
e2211743 WD |
93 | #endif |
94 | break; | |
95 | case fpga_altera: | |
0133502e | 96 | #if defined(CONFIG_FPGA_ALTERA) |
f6555d90 MS |
97 | printf("Altera Device\nDescriptor @ 0x%p\n", desc); |
98 | ret_val = altera_info(desc->devdesc); | |
e2211743 | 99 | #else |
f6555d90 | 100 | fpga_no_sup((char *)__func__, "Altera devices"); |
e2211743 WD |
101 | #endif |
102 | break; | |
3b8ac464 | 103 | case fpga_lattice: |
439f6f7e | 104 | #if defined(CONFIG_FPGA_LATTICE) |
3b8ac464 SB |
105 | printf("Lattice Device\nDescriptor @ 0x%p\n", desc); |
106 | ret_val = lattice_info(desc->devdesc); | |
439f6f7e | 107 | #else |
f6555d90 | 108 | fpga_no_sup((char *)__func__, "Lattice devices"); |
439f6f7e | 109 | #endif |
3b8ac464 | 110 | break; |
e2211743 | 111 | default: |
f6555d90 MS |
112 | printf("%s: Invalid or unsupported device type %d\n", |
113 | __func__, desc->devtype); | |
e2211743 WD |
114 | } |
115 | } else { | |
f6555d90 | 116 | printf("%s: Invalid device number %d\n", __func__, devnum); |
e2211743 WD |
117 | } |
118 | ||
119 | return ret_val; | |
120 | } | |
121 | ||
f6555d90 | 122 | /* |
905bca6c | 123 | * fpga_init is usually called from misc_init_r() and MUST be called |
e2211743 WD |
124 | * before any of the other fpga functions are used. |
125 | */ | |
6385b281 | 126 | void fpga_init(void) |
e2211743 | 127 | { |
e2211743 | 128 | next_desc = 0; |
f6555d90 | 129 | memset(desc_table, 0, sizeof(desc_table)); |
e2211743 | 130 | |
ee976c1b | 131 | debug("%s\n", __func__); |
e2211743 WD |
132 | } |
133 | ||
f6555d90 MS |
134 | /* |
135 | * fpga_count | |
e2211743 WD |
136 | * Basic interface function to get the current number of devices available. |
137 | */ | |
f6555d90 | 138 | int fpga_count(void) |
e2211743 WD |
139 | { |
140 | return next_desc; | |
141 | } | |
142 | ||
f6555d90 MS |
143 | /* |
144 | * fpga_add | |
6385b281 | 145 | * Add the device descriptor to the device table. |
e2211743 | 146 | */ |
f6555d90 | 147 | int fpga_add(fpga_type devtype, void *desc) |
e2211743 WD |
148 | { |
149 | int devnum = FPGA_INVALID_DEVICE; | |
150 | ||
f6555d90 MS |
151 | if (next_desc < 0) { |
152 | printf("%s: FPGA support not initialized!\n", __func__); | |
153 | } else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) { | |
154 | if (desc) { | |
155 | if (next_desc < CONFIG_MAX_FPGA_DEVICES) { | |
6385b281 PT |
156 | devnum = next_desc; |
157 | desc_table[next_desc].devtype = devtype; | |
158 | desc_table[next_desc++].devdesc = desc; | |
e2211743 | 159 | } else { |
f6555d90 MS |
160 | printf("%s: Exceeded Max FPGA device count\n", |
161 | __func__); | |
e2211743 WD |
162 | } |
163 | } else { | |
f6555d90 | 164 | printf("%s: NULL device descriptor\n", __func__); |
e2211743 WD |
165 | } |
166 | } else { | |
f6555d90 | 167 | printf("%s: Unsupported FPGA type %d\n", __func__, devtype); |
e2211743 WD |
168 | } |
169 | ||
170 | return devnum; | |
171 | } | |
172 | ||
52c20644 MS |
173 | /* |
174 | * Convert bitstream data and load into the fpga | |
175 | */ | |
7a78bd26 MS |
176 | int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size, |
177 | bitstream_type bstype) | |
52c20644 MS |
178 | { |
179 | printf("Bitstream support not implemented for this FPGA device\n"); | |
180 | return FPGA_FAIL; | |
181 | } | |
182 | ||
1a897668 SDPP |
183 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
184 | int fpga_fsload(int devnum, const void *buf, size_t size, | |
185 | fpga_fs_info *fpga_fsinfo) | |
186 | { | |
187 | int ret_val = FPGA_FAIL; /* assume failure */ | |
188 | const fpga_desc *desc = fpga_validate(devnum, buf, size, | |
189 | (char *)__func__); | |
190 | ||
191 | if (desc) { | |
192 | switch (desc->devtype) { | |
193 | case fpga_xilinx: | |
194 | #if defined(CONFIG_FPGA_XILINX) | |
195 | ret_val = xilinx_loadfs(desc->devdesc, buf, size, | |
196 | fpga_fsinfo); | |
197 | #else | |
198 | fpga_no_sup((char *)__func__, "Xilinx devices"); | |
199 | #endif | |
200 | break; | |
201 | default: | |
202 | printf("%s: Invalid or unsupported device type %d\n", | |
203 | __func__, desc->devtype); | |
204 | } | |
205 | } | |
206 | ||
207 | return ret_val; | |
208 | } | |
209 | #endif | |
210 | ||
e2211743 | 211 | /* |
f6555d90 | 212 | * Generic multiplexing code |
e2211743 | 213 | */ |
7a78bd26 | 214 | int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype) |
e2211743 WD |
215 | { |
216 | int ret_val = FPGA_FAIL; /* assume failure */ | |
f6555d90 MS |
217 | const fpga_desc *desc = fpga_validate(devnum, buf, bsize, |
218 | (char *)__func__); | |
e2211743 | 219 | |
f6555d90 MS |
220 | if (desc) { |
221 | switch (desc->devtype) { | |
e2211743 | 222 | case fpga_xilinx: |
0133502e | 223 | #if defined(CONFIG_FPGA_XILINX) |
7a78bd26 MS |
224 | ret_val = xilinx_load(desc->devdesc, buf, bsize, |
225 | bstype); | |
e2211743 | 226 | #else |
f6555d90 | 227 | fpga_no_sup((char *)__func__, "Xilinx devices"); |
e2211743 WD |
228 | #endif |
229 | break; | |
230 | case fpga_altera: | |
0133502e | 231 | #if defined(CONFIG_FPGA_ALTERA) |
f6555d90 | 232 | ret_val = altera_load(desc->devdesc, buf, bsize); |
e2211743 | 233 | #else |
f6555d90 | 234 | fpga_no_sup((char *)__func__, "Altera devices"); |
e2211743 WD |
235 | #endif |
236 | break; | |
3b8ac464 | 237 | case fpga_lattice: |
439f6f7e | 238 | #if defined(CONFIG_FPGA_LATTICE) |
3b8ac464 | 239 | ret_val = lattice_load(desc->devdesc, buf, bsize); |
439f6f7e | 240 | #else |
f6555d90 | 241 | fpga_no_sup((char *)__func__, "Lattice devices"); |
439f6f7e | 242 | #endif |
3b8ac464 | 243 | break; |
e2211743 | 244 | default: |
f6555d90 MS |
245 | printf("%s: Invalid or unsupported device type %d\n", |
246 | __func__, desc->devtype); | |
e2211743 WD |
247 | } |
248 | } | |
249 | ||
250 | return ret_val; | |
251 | } | |
252 | ||
f6555d90 MS |
253 | /* |
254 | * fpga_dump | |
e2211743 WD |
255 | * generic multiplexing code |
256 | */ | |
e6a857da | 257 | int fpga_dump(int devnum, const void *buf, size_t bsize) |
e2211743 WD |
258 | { |
259 | int ret_val = FPGA_FAIL; /* assume failure */ | |
f6555d90 MS |
260 | const fpga_desc *desc = fpga_validate(devnum, buf, bsize, |
261 | (char *)__func__); | |
e2211743 | 262 | |
f6555d90 MS |
263 | if (desc) { |
264 | switch (desc->devtype) { | |
e2211743 | 265 | case fpga_xilinx: |
0133502e | 266 | #if defined(CONFIG_FPGA_XILINX) |
f6555d90 | 267 | ret_val = xilinx_dump(desc->devdesc, buf, bsize); |
e2211743 | 268 | #else |
f6555d90 | 269 | fpga_no_sup((char *)__func__, "Xilinx devices"); |
e2211743 WD |
270 | #endif |
271 | break; | |
272 | case fpga_altera: | |
0133502e | 273 | #if defined(CONFIG_FPGA_ALTERA) |
f6555d90 | 274 | ret_val = altera_dump(desc->devdesc, buf, bsize); |
e2211743 | 275 | #else |
f6555d90 | 276 | fpga_no_sup((char *)__func__, "Altera devices"); |
e2211743 WD |
277 | #endif |
278 | break; | |
3b8ac464 | 279 | case fpga_lattice: |
439f6f7e | 280 | #if defined(CONFIG_FPGA_LATTICE) |
3b8ac464 | 281 | ret_val = lattice_dump(desc->devdesc, buf, bsize); |
439f6f7e | 282 | #else |
f6555d90 | 283 | fpga_no_sup((char *)__func__, "Lattice devices"); |
439f6f7e | 284 | #endif |
3b8ac464 | 285 | break; |
e2211743 | 286 | default: |
f6555d90 MS |
287 | printf("%s: Invalid or unsupported device type %d\n", |
288 | __func__, desc->devtype); | |
e2211743 WD |
289 | } |
290 | } | |
291 | ||
292 | return ret_val; | |
293 | } | |
294 | ||
f6555d90 MS |
295 | /* |
296 | * fpga_info | |
e2211743 WD |
297 | * front end to fpga_dev_info. If devnum is invalid, report on all |
298 | * available devices. | |
299 | */ | |
f6555d90 | 300 | int fpga_info(int devnum) |
e2211743 | 301 | { |
f6555d90 MS |
302 | if (devnum == FPGA_INVALID_DEVICE) { |
303 | if (next_desc > 0) { | |
e2211743 WD |
304 | int dev; |
305 | ||
f6555d90 MS |
306 | for (dev = 0; dev < next_desc; dev++) |
307 | fpga_dev_info(dev); | |
308 | ||
e2211743 WD |
309 | return FPGA_SUCCESS; |
310 | } else { | |
f6555d90 | 311 | printf("%s: No FPGA devices available.\n", __func__); |
e2211743 WD |
312 | return FPGA_FAIL; |
313 | } | |
314 | } | |
e2211743 | 315 | |
f6555d90 MS |
316 | return fpga_dev_info(devnum); |
317 | } |