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5d3207da | 1 | /* |
d5dae85f MS |
2 | * (C) Copyright 2012-2013, Xilinx, Michal Simek |
3 | * | |
5d3207da WD |
4 | * (C) Copyright 2002 |
5 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. | |
6 | * Keith Outwater, keith_outwater@mvis.com | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
5d3207da WD |
9 | */ |
10 | ||
11 | /* | |
12 | * Xilinx FPGA support | |
13 | */ | |
14 | ||
15 | #include <common.h> | |
6631db47 | 16 | #include <fpga.h> |
5d3207da WD |
17 | #include <virtex2.h> |
18 | #include <spartan2.h> | |
875c7893 | 19 | #include <spartan3.h> |
d5dae85f | 20 | #include <zynqpl.h> |
5d3207da | 21 | |
5d3207da | 22 | /* Local Static Functions */ |
f8c1be98 | 23 | static int xilinx_validate(xilinx_desc *desc, char *fn); |
5d3207da WD |
24 | |
25 | /* ------------------------------------------------------------------------- */ | |
26 | ||
7a78bd26 MS |
27 | int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, |
28 | bitstream_type bstype) | |
52c20644 MS |
29 | { |
30 | unsigned int length; | |
31 | unsigned int swapsize; | |
32 | char buffer[80]; | |
33 | unsigned char *dataptr; | |
34 | unsigned int i; | |
6631db47 | 35 | const fpga_desc *desc; |
f8c1be98 | 36 | xilinx_desc *xdesc; |
52c20644 MS |
37 | |
38 | dataptr = (unsigned char *)fpgadata; | |
6631db47 MS |
39 | /* Find out fpga_description */ |
40 | desc = fpga_validate(devnum, dataptr, 0, (char *)__func__); | |
41 | /* Assign xilinx device description */ | |
42 | xdesc = desc->devdesc; | |
52c20644 MS |
43 | |
44 | /* skip the first bytes of the bitsteam, their meaning is unknown */ | |
45 | length = (*dataptr << 8) + *(dataptr + 1); | |
46 | dataptr += 2; | |
47 | dataptr += length; | |
48 | ||
49 | /* get design name (identifier, length, string) */ | |
50 | length = (*dataptr << 8) + *(dataptr + 1); | |
51 | dataptr += 2; | |
52 | if (*dataptr++ != 0x61) { | |
53 | debug("%s: Design name id not recognized in bitstream\n", | |
54 | __func__); | |
55 | return FPGA_FAIL; | |
56 | } | |
57 | ||
58 | length = (*dataptr << 8) + *(dataptr + 1); | |
59 | dataptr += 2; | |
60 | for (i = 0; i < length; i++) | |
61 | buffer[i] = *dataptr++; | |
62 | ||
63 | printf(" design filename = \"%s\"\n", buffer); | |
64 | ||
65 | /* get part number (identifier, length, string) */ | |
66 | if (*dataptr++ != 0x62) { | |
67 | printf("%s: Part number id not recognized in bitstream\n", | |
68 | __func__); | |
69 | return FPGA_FAIL; | |
70 | } | |
71 | ||
72 | length = (*dataptr << 8) + *(dataptr + 1); | |
73 | dataptr += 2; | |
74 | for (i = 0; i < length; i++) | |
75 | buffer[i] = *dataptr++; | |
6631db47 MS |
76 | |
77 | if (xdesc->name) { | |
f7213267 SDPP |
78 | i = (ulong)strstr(buffer, xdesc->name); |
79 | if (!i) { | |
6631db47 MS |
80 | printf("%s: Wrong bitstream ID for this device\n", |
81 | __func__); | |
82 | printf("%s: Bitstream ID %s, current device ID %d/%s\n", | |
83 | __func__, buffer, devnum, xdesc->name); | |
84 | return FPGA_FAIL; | |
85 | } | |
86 | } else { | |
f8c1be98 | 87 | printf("%s: Please fill correct device ID to xilinx_desc\n", |
6631db47 MS |
88 | __func__); |
89 | } | |
52c20644 MS |
90 | printf(" part number = \"%s\"\n", buffer); |
91 | ||
92 | /* get date (identifier, length, string) */ | |
93 | if (*dataptr++ != 0x63) { | |
94 | printf("%s: Date identifier not recognized in bitstream\n", | |
95 | __func__); | |
96 | return FPGA_FAIL; | |
97 | } | |
98 | ||
99 | length = (*dataptr << 8) + *(dataptr+1); | |
100 | dataptr += 2; | |
101 | for (i = 0; i < length; i++) | |
102 | buffer[i] = *dataptr++; | |
103 | printf(" date = \"%s\"\n", buffer); | |
104 | ||
105 | /* get time (identifier, length, string) */ | |
106 | if (*dataptr++ != 0x64) { | |
107 | printf("%s: Time identifier not recognized in bitstream\n", | |
108 | __func__); | |
109 | return FPGA_FAIL; | |
110 | } | |
111 | ||
112 | length = (*dataptr << 8) + *(dataptr+1); | |
113 | dataptr += 2; | |
114 | for (i = 0; i < length; i++) | |
115 | buffer[i] = *dataptr++; | |
116 | printf(" time = \"%s\"\n", buffer); | |
117 | ||
118 | /* get fpga data length (identifier, length) */ | |
119 | if (*dataptr++ != 0x65) { | |
120 | printf("%s: Data length id not recognized in bitstream\n", | |
121 | __func__); | |
122 | return FPGA_FAIL; | |
123 | } | |
124 | swapsize = ((unsigned int) *dataptr << 24) + | |
125 | ((unsigned int) *(dataptr + 1) << 16) + | |
126 | ((unsigned int) *(dataptr + 2) << 8) + | |
127 | ((unsigned int) *(dataptr + 3)); | |
128 | dataptr += 4; | |
129 | printf(" bytes in bitstream = %d\n", swapsize); | |
130 | ||
7a78bd26 | 131 | return fpga_load(devnum, dataptr, swapsize, bstype); |
52c20644 MS |
132 | } |
133 | ||
7a78bd26 MS |
134 | int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize, |
135 | bitstream_type bstype) | |
5d3207da | 136 | { |
77ddac94 | 137 | if (!xilinx_validate (desc, (char *)__FUNCTION__)) { |
5d3207da | 138 | printf ("%s: Invalid device descriptor\n", __FUNCTION__); |
14cfc4f3 MS |
139 | return FPGA_FAIL; |
140 | } | |
5d3207da | 141 | |
6cd68c81 MS |
142 | if (!desc->operations || !desc->operations->load) { |
143 | printf("%s: Missing load operation\n", __func__); | |
144 | return FPGA_FAIL; | |
145 | } | |
146 | ||
7a78bd26 | 147 | return desc->operations->load(desc, buf, bsize, bstype); |
5d3207da WD |
148 | } |
149 | ||
1a897668 SDPP |
150 | #if defined(CONFIG_CMD_FPGA_LOADFS) |
151 | int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize, | |
152 | fpga_fs_info *fpga_fsinfo) | |
153 | { | |
154 | if (!xilinx_validate(desc, (char *)__func__)) { | |
155 | printf("%s: Invalid device descriptor\n", __func__); | |
156 | return FPGA_FAIL; | |
157 | } | |
158 | ||
6cd68c81 MS |
159 | if (!desc->operations || !desc->operations->loadfs) { |
160 | printf("%s: Missing loadfs operation\n", __func__); | |
1a897668 | 161 | return FPGA_FAIL; |
6cd68c81 | 162 | } |
1a897668 SDPP |
163 | |
164 | return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo); | |
165 | } | |
166 | #endif | |
167 | ||
f8c1be98 | 168 | int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) |
5d3207da | 169 | { |
77ddac94 | 170 | if (!xilinx_validate (desc, (char *)__FUNCTION__)) { |
5d3207da | 171 | printf ("%s: Invalid device descriptor\n", __FUNCTION__); |
14cfc4f3 MS |
172 | return FPGA_FAIL; |
173 | } | |
5d3207da | 174 | |
6cd68c81 MS |
175 | if (!desc->operations || !desc->operations->dump) { |
176 | printf("%s: Missing dump operation\n", __func__); | |
177 | return FPGA_FAIL; | |
178 | } | |
179 | ||
14cfc4f3 | 180 | return desc->operations->dump(desc, buf, bsize); |
5d3207da WD |
181 | } |
182 | ||
f8c1be98 | 183 | int xilinx_info(xilinx_desc *desc) |
5d3207da WD |
184 | { |
185 | int ret_val = FPGA_FAIL; | |
186 | ||
77ddac94 | 187 | if (xilinx_validate (desc, (char *)__FUNCTION__)) { |
5d3207da WD |
188 | printf ("Family: \t"); |
189 | switch (desc->family) { | |
b625b9ae | 190 | case xilinx_spartan2: |
5d3207da WD |
191 | printf ("Spartan-II\n"); |
192 | break; | |
2a6e3869 | 193 | case xilinx_spartan3: |
875c7893 WD |
194 | printf ("Spartan-III\n"); |
195 | break; | |
d9071ce0 | 196 | case xilinx_virtex2: |
5d3207da WD |
197 | printf ("Virtex-II\n"); |
198 | break; | |
d5dae85f MS |
199 | case xilinx_zynq: |
200 | printf("Zynq PL\n"); | |
201 | break; | |
5d3207da WD |
202 | /* Add new family types here */ |
203 | default: | |
204 | printf ("Unknown family type, %d\n", desc->family); | |
205 | } | |
206 | ||
207 | printf ("Interface type:\t"); | |
208 | switch (desc->iface) { | |
209 | case slave_serial: | |
210 | printf ("Slave Serial\n"); | |
211 | break; | |
212 | case master_serial: /* Not used */ | |
213 | printf ("Master Serial\n"); | |
214 | break; | |
215 | case slave_parallel: | |
216 | printf ("Slave Parallel\n"); | |
217 | break; | |
218 | case jtag_mode: /* Not used */ | |
219 | printf ("JTAG Mode\n"); | |
220 | break; | |
221 | case slave_selectmap: | |
222 | printf ("Slave SelectMap Mode\n"); | |
223 | break; | |
224 | case master_selectmap: | |
225 | printf ("Master SelectMap Mode\n"); | |
226 | break; | |
d5dae85f MS |
227 | case devcfg: |
228 | printf("Device configuration interface (Zynq)\n"); | |
229 | break; | |
5d3207da WD |
230 | /* Add new interface types here */ |
231 | default: | |
232 | printf ("Unsupported interface type, %d\n", desc->iface); | |
233 | } | |
234 | ||
ddc94378 SG |
235 | printf("Device Size: \t%zd bytes\n" |
236 | "Cookie: \t0x%x (%d)\n", | |
237 | desc->size, desc->cookie, desc->cookie); | |
6631db47 MS |
238 | if (desc->name) |
239 | printf("Device name: \t%s\n", desc->name); | |
5d3207da | 240 | |
e136eaeb | 241 | if (desc->iface_fns) |
5d3207da | 242 | printf ("Device Function Table @ 0x%p\n", desc->iface_fns); |
e136eaeb | 243 | else |
5d3207da WD |
244 | printf ("No Device Function Table.\n"); |
245 | ||
e136eaeb MS |
246 | if (desc->operations && desc->operations->info) |
247 | desc->operations->info(desc); | |
248 | ||
5d3207da WD |
249 | ret_val = FPGA_SUCCESS; |
250 | } else { | |
251 | printf ("%s: Invalid device descriptor\n", __FUNCTION__); | |
252 | } | |
253 | ||
254 | return ret_val; | |
255 | } | |
256 | ||
5d3207da WD |
257 | /* ------------------------------------------------------------------------- */ |
258 | ||
f8c1be98 | 259 | static int xilinx_validate(xilinx_desc *desc, char *fn) |
5d3207da | 260 | { |
472d5460 | 261 | int ret_val = false; |
5d3207da WD |
262 | |
263 | if (desc) { | |
264 | if ((desc->family > min_xilinx_type) && | |
265 | (desc->family < max_xilinx_type)) { | |
266 | if ((desc->iface > min_xilinx_iface_type) && | |
267 | (desc->iface < max_xilinx_iface_type)) { | |
268 | if (desc->size) { | |
472d5460 | 269 | ret_val = true; |
5d3207da WD |
270 | } else |
271 | printf ("%s: NULL part size\n", fn); | |
272 | } else | |
273 | printf ("%s: Invalid Interface type, %d\n", | |
274 | fn, desc->iface); | |
275 | } else | |
276 | printf ("%s: Invalid family type, %d\n", fn, desc->family); | |
277 | } else | |
278 | printf ("%s: NULL descriptor!\n", fn); | |
279 | ||
280 | return ret_val; | |
281 | } |