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gpio/omap: remove useless gpio_valid() & check_gpio() checks
[people/ms/linux.git] / drivers / gpio / gpio-omap.c
CommitLineData
5e1c5ff4 1/*
5e1c5ff4
TL		 2 * Support functions for OMAP GPIO
3 *
92105bb7 4 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 6 *
44169075
SS		 7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
5e1c5ff4
TL		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
5e1c5ff4
TL		 15#include <linux/init.h>
16#include <linux/module.h>
5e1c5ff4 17#include <linux/interrupt.h>
3c437ffd 18#include <linux/syscore_ops.h>
92105bb7 19#include <linux/err.h>
f8ce2547 20#include <linux/clk.h>
fced80c7 21#include <linux/io.h>
77640aab
VC		 22#include <linux/slab.h>
23#include <linux/pm_runtime.h>
5e1c5ff4 24
a09e64fb 25#include <mach/hardware.h>
5e1c5ff4 26#include <asm/irq.h>
a09e64fb
RK		 27#include <mach/irqs.h>
28#include <mach/gpio.h>
5e1c5ff4
TL		 29#include <asm/mach/irq.h>
30
5e1c5ff4 31struct gpio_bank {
9f7065da 32 unsigned long pbase;
92105bb7 33 void __iomem *base;
5e1c5ff4
TL		 34 u16 irq;
35 u16 virtual_irq_start;
92105bb7 36 int method;
140455fa 37#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 38 u32 suspend_wakeup;
39 u32 saved_wakeup;
3ac4fa99 40#endif
3ac4fa99
JY		 41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
b144ff6f 47 u32 level_mask;
4318f36b 48 u32 toggle_mask;
5e1c5ff4 49 spinlock_t lock;
52e31344 50 struct gpio_chip chip;
89db9482 51 struct clk *dbck;
058af1ea 52 u32 mod_usage;
8865b9b6 53 u32 dbck_enable_mask;
77640aab
VC		 54 struct device *dev;
55 bool dbck_flag;
5de62b86 56 int stride;
d5f46247 57 u32 width;
fa87931a
KH		 58
59 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
60
61 struct omap_gpio_reg_offs *regs;
5e1c5ff4
TL		 62};
63
a8eb7ca0 64#ifdef CONFIG_ARCH_OMAP3
40c670f0 65struct omap3_gpio_regs {
40c670f0
RN		 66 u32 irqenable1;
67 u32 irqenable2;
68 u32 wake_en;
69 u32 ctrl;
70 u32 oe;
71 u32 leveldetect0;
72 u32 leveldetect1;
73 u32 risingdetect;
74 u32 fallingdetect;
75 u32 dataout;
5492fb1a
SMK		 76};
77
40c670f0 78static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
5492fb1a
SMK		 79#endif
80
77640aab
VC		 81/*
82 * TODO: Cleanup gpio_bank usage as it is having information
83 * related to all instances of the device
84 */
85static struct gpio_bank *gpio_bank;
44169075 86
c95d10bc
VC		 87/* TODO: Analyze removing gpio_bank_count usage from driver code */
88int gpio_bank_count;
5e1c5ff4 89
129fd223
KH		 90#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
91#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
92
5e1c5ff4
TL		 93static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
94{
92105bb7 95 void __iomem *reg = bank->base;
5e1c5ff4
TL		 96 u32 l;
97
fa87931a 98 reg += bank->regs->direction;
5e1c5ff4
TL		 99 l = __raw_readl(reg);
100 if (is_input)
101 l |= 1 << gpio;
102 else
103 l &= ~(1 << gpio);
104 __raw_writel(l, reg);
105}
106
fa87931a
KH		 107
108/* set data out value using dedicate set/clear register */
109static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
5e1c5ff4 110{
92105bb7 111 void __iomem *reg = bank->base;
fa87931a 112 u32 l = GPIO_BIT(bank, gpio);
5e1c5ff4 113
fa87931a
KH		 114 if (enable)
115 reg += bank->regs->set_dataout;
116 else
117 reg += bank->regs->clr_dataout;
118
119 __raw_writel(l, reg);
120}
121
122/* set data out value using mask register */
123static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
124{
125 void __iomem *reg = bank->base + bank->regs->dataout;
126 u32 gpio_bit = GPIO_BIT(bank, gpio);
127 u32 l;
128
129 l = __raw_readl(reg);
130 if (enable)
131 l |= gpio_bit;
132 else
133 l &= ~gpio_bit;
5e1c5ff4
TL		 134 __raw_writel(l, reg);
135}
136
b37c45b8 137static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
5e1c5ff4 138{
fa87931a 139 void __iomem *reg = bank->base + bank->regs->datain;
5e1c5ff4 140
fa87931a 141 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
5e1c5ff4
TL		 142}
143
b37c45b8
RQ		 144static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
145{
fa87931a 146 void __iomem *reg = bank->base + bank->regs->dataout;
b37c45b8 147
129fd223 148 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
b37c45b8
RQ		 149}
150
92105bb7
TL		 151#define MOD_REG_BIT(reg, bit_mask, set) \
152do { \
153 int l = __raw_readl(base + reg); \
154 if (set) l |= bit_mask; \
155 else l &= ~bit_mask; \
156 __raw_writel(l, base + reg); \
157} while(0)
158
168ef3d9
FB		 159/**
160 * _set_gpio_debounce - low level gpio debounce time
161 * @bank: the gpio bank we're acting upon
162 * @gpio: the gpio number on this @gpio
163 * @debounce: debounce time to use
164 *
165 * OMAP's debounce time is in 31us steps so we need
166 * to convert and round up to the closest unit.
167 */
168static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
169 unsigned debounce)
170{
171 void __iomem *reg = bank->base;
172 u32 val;
173 u32 l;
174
77640aab
VC		 175 if (!bank->dbck_flag)
176 return;
177
168ef3d9
FB		 178 if (debounce < 32)
179 debounce = 0x01;
180 else if (debounce > 7936)
181 debounce = 0xff;
182 else
183 debounce = (debounce / 0x1f) - 1;
184
129fd223 185 l = GPIO_BIT(bank, gpio);
168ef3d9 186
77640aab 187 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 188 reg += OMAP4_GPIO_DEBOUNCINGTIME;
189 else
190 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
191
192 __raw_writel(debounce, reg);
193
194 reg = bank->base;
77640aab 195 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 196 reg += OMAP4_GPIO_DEBOUNCENABLE;
197 else
198 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
199
200 val = __raw_readl(reg);
201
202 if (debounce) {
203 val |= l;
77640aab 204 clk_enable(bank->dbck);
168ef3d9
FB		 205 } else {
206 val &= ~l;
77640aab 207 clk_disable(bank->dbck);
168ef3d9 208 }
f7ec0b0b 209 bank->dbck_enable_mask = val;
168ef3d9
FB		 210
211 __raw_writel(val, reg);
212}
213
140455fa 214#ifdef CONFIG_ARCH_OMAP2PLUS
5eb3bb9c
KH		 215static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
216 int trigger)
5e1c5ff4 217{
3ac4fa99 218 void __iomem *base = bank->base;
92105bb7
TL		 219 u32 gpio_bit = 1 << gpio;
220
78a1a6d3
SR		 221 if (cpu_is_omap44xx()) {
222 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
223 trigger & IRQ_TYPE_LEVEL_LOW);
224 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
225 trigger & IRQ_TYPE_LEVEL_HIGH);
226 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
227 trigger & IRQ_TYPE_EDGE_RISING);
228 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
229 trigger & IRQ_TYPE_EDGE_FALLING);
230 } else {
231 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
232 trigger & IRQ_TYPE_LEVEL_LOW);
233 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
234 trigger & IRQ_TYPE_LEVEL_HIGH);
235 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
236 trigger & IRQ_TYPE_EDGE_RISING);
237 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
238 trigger & IRQ_TYPE_EDGE_FALLING);
239 }
3ac4fa99 240 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3 241 if (cpu_is_omap44xx()) {
0622b25b
CC		 242 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
243 trigger != 0);
78a1a6d3 244 } else {
699117a6
CW		 245 /*
246 * GPIO wakeup request can only be generated on edge
247 * transitions
248 */
249 if (trigger & IRQ_TYPE_EDGE_BOTH)
78a1a6d3 250 __raw_writel(1 << gpio, bank->base
5eb3bb9c 251 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 252 else
253 __raw_writel(1 << gpio, bank->base
5eb3bb9c 254 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 255 }
a118b5f3
TK		 256 }
257 /* This part needs to be executed always for OMAP34xx */
258 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
699117a6
CW		 259 /*
260 * Log the edge gpio and manually trigger the IRQ
261 * after resume if the input level changes
262 * to avoid irq lost during PER RET/OFF mode
263 * Applies for omap2 non-wakeup gpio and all omap3 gpios
264 */
265 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 266 bank->enabled_non_wakeup_gpios |= gpio_bit;
267 else
268 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
269 }
5eb3bb9c 270
78a1a6d3
SR		 271 if (cpu_is_omap44xx()) {
272 bank->level_mask =
273 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
274 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
275 } else {
276 bank->level_mask =
277 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
278 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
279 }
92105bb7 280}
3ac4fa99 281#endif
92105bb7 282
9198bcd3 283#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 284/*
285 * This only applies to chips that can't do both rising and falling edge
286 * detection at once. For all other chips, this function is a noop.
287 */
288static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
289{
290 void __iomem *reg = bank->base;
291 u32 l = 0;
292
293 switch (bank->method) {
4318f36b 294 case METHOD_MPUIO:
5de62b86 295 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
4318f36b 296 break;
4318f36b
CM		 297#ifdef CONFIG_ARCH_OMAP15XX
298 case METHOD_GPIO_1510:
299 reg += OMAP1510_GPIO_INT_CONTROL;
300 break;
301#endif
302#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
303 case METHOD_GPIO_7XX:
304 reg += OMAP7XX_GPIO_INT_CONTROL;
305 break;
306#endif
307 default:
308 return;
309 }
310
311 l = __raw_readl(reg);
312 if ((l >> gpio) & 1)
313 l &= ~(1 << gpio);
314 else
315 l |= 1 << gpio;
316
317 __raw_writel(l, reg);
318}
9198bcd3 319#endif
4318f36b 320
92105bb7
TL		 321static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
322{
323 void __iomem *reg = bank->base;
324 u32 l = 0;
5e1c5ff4
TL		 325
326 switch (bank->method) {
e5c56ed3 327#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 328 case METHOD_MPUIO:
5de62b86 329 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
5e1c5ff4 330 l = __raw_readl(reg);
29501577 331 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 332 bank->toggle_mask |= 1 << gpio;
6cab4860 333 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 334 l |= 1 << gpio;
6cab4860 335 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 336 l &= ~(1 << gpio);
92105bb7
TL		 337 else
338 goto bad;
5e1c5ff4 339 break;
e5c56ed3
DB		 340#endif
341#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 342 case METHOD_GPIO_1510:
343 reg += OMAP1510_GPIO_INT_CONTROL;
344 l = __raw_readl(reg);
29501577 345 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 346 bank->toggle_mask |= 1 << gpio;
6cab4860 347 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 348 l |= 1 << gpio;
6cab4860 349 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 350 l &= ~(1 << gpio);
92105bb7
TL		 351 else
352 goto bad;
5e1c5ff4 353 break;
e5c56ed3 354#endif
3ac4fa99 355#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 356 case METHOD_GPIO_1610:
5e1c5ff4
TL		 357 if (gpio & 0x08)
358 reg += OMAP1610_GPIO_EDGE_CTRL2;
359 else
360 reg += OMAP1610_GPIO_EDGE_CTRL1;
361 gpio &= 0x07;
362 l = __raw_readl(reg);
363 l &= ~(3 << (gpio << 1));
6cab4860 364 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 365 l |= 2 << (gpio << 1);
6cab4860 366 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 367 l |= 1 << (gpio << 1);
3ac4fa99
JY		 368 if (trigger)
369 /* Enable wake-up during idle for dynamic tick */
370 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
371 else
372 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 373 break;
3ac4fa99 374#endif
b718aa81 375#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 376 case METHOD_GPIO_7XX:
377 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69 378 l = __raw_readl(reg);
29501577 379 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 380 bank->toggle_mask |= 1 << gpio;
56739a69
ZM		 381 if (trigger & IRQ_TYPE_EDGE_RISING)
382 l |= 1 << gpio;
383 else if (trigger & IRQ_TYPE_EDGE_FALLING)
384 l &= ~(1 << gpio);
385 else
386 goto bad;
387 break;
388#endif
140455fa 389#ifdef CONFIG_ARCH_OMAP2PLUS
92105bb7 390 case METHOD_GPIO_24XX:
3f1686a9 391 case METHOD_GPIO_44XX:
3ac4fa99 392 set_24xx_gpio_triggering(bank, gpio, trigger);
f7c5cc45 393 return 0;
3ac4fa99 394#endif
5e1c5ff4 395 default:
92105bb7 396 goto bad;
5e1c5ff4 397 }
92105bb7
TL		 398 __raw_writel(l, reg);
399 return 0;
400bad:
401 return -EINVAL;
5e1c5ff4
TL		 402}
403
e9191028 404static int gpio_irq_type(struct irq_data *d, unsigned type)
5e1c5ff4
TL		 405{
406 struct gpio_bank *bank;
92105bb7
TL		 407 unsigned gpio;
408 int retval;
a6472533 409 unsigned long flags;
92105bb7 410
e9191028
LB		 411 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
412 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
92105bb7 413 else
e9191028 414 gpio = d->irq - IH_GPIO_BASE;
5e1c5ff4 415
e5c56ed3 416 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 417 return -EINVAL;
e5c56ed3
DB		 418
419 /* OMAP1 allows only only edge triggering */
5492fb1a 420 if (!cpu_class_is_omap2()
e5c56ed3 421 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 422 return -EINVAL;
423
e9191028 424 bank = irq_data_get_irq_chip_data(d);
a6472533 425 spin_lock_irqsave(&bank->lock, flags);
129fd223 426 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
a6472533 427 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 428
429 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
6845664a 430 __irq_set_handler_locked(d->irq, handle_level_irq);
672e302e 431 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
6845664a 432 __irq_set_handler_locked(d->irq, handle_edge_irq);
672e302e 433
92105bb7 434 return retval;
5e1c5ff4
TL		 435}
436
437static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
438{
92105bb7 439 void __iomem *reg = bank->base;
5e1c5ff4 440
eef4bec7 441 reg += bank->regs->irqstatus;
5e1c5ff4 442 __raw_writel(gpio_mask, reg);
bee7930f
HD		 443
444 /* Workaround for clearing DSP GPIO interrupts to allow retention */
eef4bec7
KH		 445 if (bank->regs->irqstatus2) {
446 reg = bank->base + bank->regs->irqstatus2;
bedfd154 447 __raw_writel(gpio_mask, reg);
eef4bec7 448 }
bedfd154
RQ		 449
450 /* Flush posted write for the irq status to avoid spurious interrupts */
451 __raw_readl(reg);
5e1c5ff4
TL		 452}
453
454static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
455{
129fd223 456 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
5e1c5ff4
TL		 457}
458
ea6dedd7
ID		 459static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
460{
461 void __iomem *reg = bank->base;
99c47707 462 u32 l;
c390aad0 463 u32 mask = (1 << bank->width) - 1;
ea6dedd7 464
28f3b5a0 465 reg += bank->regs->irqenable;
99c47707 466 l = __raw_readl(reg);
28f3b5a0 467 if (bank->regs->irqenable_inv)
99c47707
ID		 468 l = ~l;
469 l &= mask;
470 return l;
ea6dedd7
ID		 471}
472
28f3b5a0 473static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
5e1c5ff4 474{
92105bb7 475 void __iomem *reg = bank->base;
5e1c5ff4
TL		 476 u32 l;
477
28f3b5a0
KH		 478 if (bank->regs->set_irqenable) {
479 reg += bank->regs->set_irqenable;
480 l = gpio_mask;
481 } else {
482 reg += bank->regs->irqenable;
5e1c5ff4 483 l = __raw_readl(reg);
28f3b5a0
KH		 484 if (bank->regs->irqenable_inv)
485 l &= ~gpio_mask;
5e1c5ff4
TL		 486 else
487 l |= gpio_mask;
28f3b5a0
KH		 488 }
489
490 __raw_writel(l, reg);
491}
492
493static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
494{
495 void __iomem *reg = bank->base;
496 u32 l;
497
498 if (bank->regs->clr_irqenable) {
499 reg += bank->regs->clr_irqenable;
5e1c5ff4 500 l = gpio_mask;
28f3b5a0
KH		 501 } else {
502 reg += bank->regs->irqenable;
56739a69 503 l = __raw_readl(reg);
28f3b5a0 504 if (bank->regs->irqenable_inv)
56739a69 505 l |= gpio_mask;
78a1a6d3 506 else
28f3b5a0 507 l &= ~gpio_mask;
5e1c5ff4 508 }
28f3b5a0 509
5e1c5ff4
TL		 510 __raw_writel(l, reg);
511}
512
513static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
514{
28f3b5a0 515 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
5e1c5ff4
TL		 516}
517
92105bb7
TL		 518/*
519 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
520 * 1510 does not seem to have a wake-up register. If JTAG is connected
521 * to the target, system will wake up always on GPIO events. While
522 * system is running all registered GPIO interrupts need to have wake-up
523 * enabled. When system is suspended, only selected GPIO interrupts need
524 * to have wake-up enabled.
525 */
526static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
527{
4cc6420c 528 unsigned long uninitialized_var(flags);
a6472533 529
92105bb7 530 switch (bank->method) {
3ac4fa99 531#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 532 case METHOD_MPUIO:
92105bb7 533 case METHOD_GPIO_1610:
a6472533 534 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 535 if (enable)
92105bb7 536 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 537 else
92105bb7 538 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 539 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 540 return 0;
3ac4fa99 541#endif
140455fa 542#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99 543 case METHOD_GPIO_24XX:
3f1686a9 544 case METHOD_GPIO_44XX:
11a78b79
DB		 545 if (bank->non_wakeup_gpios & (1 << gpio)) {
546 printk(KERN_ERR "Unable to modify wakeup on "
547 "non-wakeup GPIO%d\n",
d5f46247 548 (bank - gpio_bank) * bank->width + gpio);
11a78b79
DB		 549 return -EINVAL;
550 }
a6472533 551 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 552 if (enable)
3ac4fa99 553 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 554 else
3ac4fa99 555 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 556 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 557 return 0;
558#endif
92105bb7
TL		 559 default:
560 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
561 bank->method);
562 return -EINVAL;
563 }
564}
565
4196dd6b
TL		 566static void _reset_gpio(struct gpio_bank *bank, int gpio)
567{
129fd223 568 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
4196dd6b
TL		 569 _set_gpio_irqenable(bank, gpio, 0);
570 _clear_gpio_irqstatus(bank, gpio);
129fd223 571 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 572}
573
92105bb7 574/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
e9191028 575static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
92105bb7 576{
e9191028 577 unsigned int gpio = d->irq - IH_GPIO_BASE;
92105bb7
TL		 578 struct gpio_bank *bank;
579 int retval;
580
e9191028 581 bank = irq_data_get_irq_chip_data(d);
129fd223 582 retval = _set_gpio_wakeup(bank, GPIO_INDEX(bank, gpio), enable);
92105bb7
TL		 583
584 return retval;
585}
586
3ff164e1 587static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 588{
3ff164e1 589 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 590 unsigned long flags;
52e31344 591
a6472533 592 spin_lock_irqsave(&bank->lock, flags);
92105bb7 593
4196dd6b
TL		 594 /* Set trigger to none. You need to enable the desired trigger with
595 * request_irq() or set_irq_type().
596 */
3ff164e1 597 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 598
1a8bfa1e 599#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 600 if (bank->method == METHOD_GPIO_1510) {
92105bb7 601 void __iomem *reg;
5e1c5ff4 602
92105bb7 603 /* Claim the pin for MPU */
5e1c5ff4 604 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 605 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 606 }
607#endif
058af1ea
C		 608 if (!cpu_class_is_omap1()) {
609 if (!bank->mod_usage) {
9f096868 610 void __iomem *reg = bank->base;
058af1ea 611 u32 ctrl;
9f096868
C		 612
613 if (cpu_is_omap24xx() || cpu_is_omap34xx())
614 reg += OMAP24XX_GPIO_CTRL;
615 else if (cpu_is_omap44xx())
616 reg += OMAP4_GPIO_CTRL;
617 ctrl = __raw_readl(reg);
058af1ea 618 /* Module is enabled, clocks are not gated */
9f096868
C		 619 ctrl &= 0xFFFFFFFE;
620 __raw_writel(ctrl, reg);
058af1ea
C		 621 }
622 bank->mod_usage |= 1 << offset;
623 }
a6472533 624 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 625
626 return 0;
627}
628
3ff164e1 629static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 630{
3ff164e1 631 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 632 unsigned long flags;
5e1c5ff4 633
a6472533 634 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 635#ifdef CONFIG_ARCH_OMAP16XX
636 if (bank->method == METHOD_GPIO_1610) {
637 /* Disable wake-up during idle for dynamic tick */
638 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 639 __raw_writel(1 << offset, reg);
92105bb7
TL		 640 }
641#endif
9f096868
C		 642#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
643 if (bank->method == METHOD_GPIO_24XX) {
92105bb7
TL		 644 /* Disable wake-up during idle for dynamic tick */
645 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 646 __raw_writel(1 << offset, reg);
92105bb7 647 }
9f096868
C		 648#endif
649#ifdef CONFIG_ARCH_OMAP4
650 if (bank->method == METHOD_GPIO_44XX) {
651 /* Disable wake-up during idle for dynamic tick */
652 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
653 __raw_writel(1 << offset, reg);
654 }
92105bb7 655#endif
058af1ea
C		 656 if (!cpu_class_is_omap1()) {
657 bank->mod_usage &= ~(1 << offset);
658 if (!bank->mod_usage) {
9f096868 659 void __iomem *reg = bank->base;
058af1ea 660 u32 ctrl;
9f096868
C		 661
662 if (cpu_is_omap24xx() || cpu_is_omap34xx())
663 reg += OMAP24XX_GPIO_CTRL;
664 else if (cpu_is_omap44xx())
665 reg += OMAP4_GPIO_CTRL;
666 ctrl = __raw_readl(reg);
058af1ea
C		 667 /* Module is disabled, clocks are gated */
668 ctrl |= 1;
9f096868 669 __raw_writel(ctrl, reg);
058af1ea
C		 670 }
671 }
3ff164e1 672 _reset_gpio(bank, bank->chip.base + offset);
a6472533 673 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 674}
675
676/*
677 * We need to unmask the GPIO bank interrupt as soon as possible to
678 * avoid missing GPIO interrupts for other lines in the bank.
679 * Then we need to mask-read-clear-unmask the triggered GPIO lines
680 * in the bank to avoid missing nested interrupts for a GPIO line.
681 * If we wait to unmask individual GPIO lines in the bank after the
682 * line's interrupt handler has been run, we may miss some nested
683 * interrupts.
684 */
10dd5ce2 685static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 686{
92105bb7 687 void __iomem *isr_reg = NULL;
5e1c5ff4 688 u32 isr;
4318f36b 689 unsigned int gpio_irq, gpio_index;
5e1c5ff4 690 struct gpio_bank *bank;
ea6dedd7
ID		 691 u32 retrigger = 0;
692 int unmasked = 0;
ee144182 693 struct irq_chip *chip = irq_desc_get_chip(desc);
5e1c5ff4 694
ee144182 695 chained_irq_enter(chip, desc);
5e1c5ff4 696
6845664a 697 bank = irq_get_handler_data(irq);
eef4bec7 698 isr_reg = bank->base + bank->regs->irqstatus;
b1cc4c55
EK		 699
700 if (WARN_ON(!isr_reg))
701 goto exit;
702
92105bb7 703 while(1) {
6e60e79a 704 u32 isr_saved, level_mask = 0;
ea6dedd7 705 u32 enabled;
6e60e79a 706
ea6dedd7
ID		 707 enabled = _get_gpio_irqbank_mask(bank);
708 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 709
710 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
711 isr &= 0x0000ffff;
712
5492fb1a 713 if (cpu_class_is_omap2()) {
b144ff6f 714 level_mask = bank->level_mask & enabled;
ea6dedd7 715 }
6e60e79a
TL		 716
717 /* clear edge sensitive interrupts before handler(s) are
718 called so that we don't miss any interrupt occurred while
719 executing them */
28f3b5a0 720 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
6e60e79a 721 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
28f3b5a0 722 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
6e60e79a
TL		 723
724 /* if there is only edge sensitive GPIO pin interrupts
725 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 726 if (!level_mask && !unmasked) {
727 unmasked = 1;
ee144182 728 chained_irq_exit(chip, desc);
ea6dedd7 729 }
92105bb7 730
ea6dedd7
ID		 731 isr |= retrigger;
732 retrigger = 0;
92105bb7
TL		 733 if (!isr)
734 break;
735
736 gpio_irq = bank->virtual_irq_start;
737 for (; isr != 0; isr >>= 1, gpio_irq++) {
129fd223 738 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
4318f36b 739
92105bb7
TL		 740 if (!(isr & 1))
741 continue;
29454dde 742
4318f36b
CM		 743#ifdef CONFIG_ARCH_OMAP1
744 /*
745 * Some chips can't respond to both rising and falling
746 * at the same time. If this irq was requested with
747 * both flags, we need to flip the ICR data for the IRQ
748 * to respond to the IRQ for the opposite direction.
749 * This will be indicated in the bank toggle_mask.
750 */
751 if (bank->toggle_mask & (1 << gpio_index))
752 _toggle_gpio_edge_triggering(bank, gpio_index);
753#endif
754
d8aa0251 755 generic_handle_irq(gpio_irq);
92105bb7 756 }
1a8bfa1e 757 }
ea6dedd7
ID		 758 /* if bank has any level sensitive GPIO pin interrupt
759 configured, we must unmask the bank interrupt only after
760 handler(s) are executed in order to avoid spurious bank
761 interrupt */
b1cc4c55 762exit:
ea6dedd7 763 if (!unmasked)
ee144182 764 chained_irq_exit(chip, desc);
5e1c5ff4
TL		 765}
766
e9191028 767static void gpio_irq_shutdown(struct irq_data *d)
4196dd6b 768{
e9191028
LB		 769 unsigned int gpio = d->irq - IH_GPIO_BASE;
770 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 771 unsigned long flags;
4196dd6b 772
85ec7b97 773 spin_lock_irqsave(&bank->lock, flags);
4196dd6b 774 _reset_gpio(bank, gpio);
85ec7b97 775 spin_unlock_irqrestore(&bank->lock, flags);
4196dd6b
TL		 776}
777
e9191028 778static void gpio_ack_irq(struct irq_data *d)
5e1c5ff4 779{
e9191028
LB		 780 unsigned int gpio = d->irq - IH_GPIO_BASE;
781 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 782
783 _clear_gpio_irqstatus(bank, gpio);
784}
785
e9191028 786static void gpio_mask_irq(struct irq_data *d)
5e1c5ff4 787{
e9191028
LB		 788 unsigned int gpio = d->irq - IH_GPIO_BASE;
789 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
85ec7b97 790 unsigned long flags;
5e1c5ff4 791
85ec7b97 792 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 793 _set_gpio_irqenable(bank, gpio, 0);
129fd223 794 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
85ec7b97 795 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 796}
797
e9191028 798static void gpio_unmask_irq(struct irq_data *d)
5e1c5ff4 799{
e9191028
LB		 800 unsigned int gpio = d->irq - IH_GPIO_BASE;
801 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
129fd223 802 unsigned int irq_mask = GPIO_BIT(bank, gpio);
8c04a176 803 u32 trigger = irqd_get_trigger_type(d);
85ec7b97 804 unsigned long flags;
55b6019a 805
85ec7b97 806 spin_lock_irqsave(&bank->lock, flags);
55b6019a 807 if (trigger)
129fd223 808 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
b144ff6f
KH		 809
810 /* For level-triggered GPIOs, the clearing must be done after
811 * the HW source is cleared, thus after the handler has run */
812 if (bank->level_mask & irq_mask) {
813 _set_gpio_irqenable(bank, gpio, 0);
814 _clear_gpio_irqstatus(bank, gpio);
815 }
5e1c5ff4 816
4de8c75b 817 _set_gpio_irqenable(bank, gpio, 1);
85ec7b97 818 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 819}
820
e5c56ed3
DB		 821static struct irq_chip gpio_irq_chip = {
822 .name = "GPIO",
e9191028
LB		 823 .irq_shutdown = gpio_irq_shutdown,
824 .irq_ack = gpio_ack_irq,
825 .irq_mask = gpio_mask_irq,
826 .irq_unmask = gpio_unmask_irq,
827 .irq_set_type = gpio_irq_type,
828 .irq_set_wake = gpio_wake_enable,
e5c56ed3
DB		 829};
830
831/*---------------------------------------------------------------------*/
832
833#ifdef CONFIG_ARCH_OMAP1
834
e5c56ed3
DB		 835#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
836
11a78b79
DB		 837#ifdef CONFIG_ARCH_OMAP16XX
838
839#include <linux/platform_device.h>
840
79ee031f 841static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 842{
79ee031f 843 struct platform_device *pdev = to_platform_device(dev);
11a78b79 844 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 845 void __iomem *mask_reg = bank->base +
846 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 847 unsigned long flags;
11a78b79 848
a6472533 849 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 850 bank->saved_wakeup = __raw_readl(mask_reg);
851 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 852 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 853
854 return 0;
855}
856
79ee031f 857static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 858{
79ee031f 859 struct platform_device *pdev = to_platform_device(dev);
11a78b79 860 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 861 void __iomem *mask_reg = bank->base +
862 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 863 unsigned long flags;
11a78b79 864
a6472533 865 spin_lock_irqsave(&bank->lock, flags);
11a78b79 866 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 867 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 868
869 return 0;
870}
871
47145210 872static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 873 .suspend_noirq = omap_mpuio_suspend_noirq,
874 .resume_noirq = omap_mpuio_resume_noirq,
875};
876
3c437ffd 877/* use platform_driver for this. */
11a78b79 878static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 879 .driver = {
880 .name = "mpuio",
79ee031f 881 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 882 },
883};
884
885static struct platform_device omap_mpuio_device = {
886 .name = "mpuio",
887 .id = -1,
888 .dev = {
889 .driver = &omap_mpuio_driver.driver,
890 }
891 /* could list the /proc/iomem resources */
892};
893
894static inline void mpuio_init(void)
895{
a8be8daf 896 struct gpio_bank *bank = &gpio_bank[0];
77640aab 897 platform_set_drvdata(&omap_mpuio_device, bank);
fcf126d8 898
11a78b79
DB		 899 if (platform_driver_register(&omap_mpuio_driver) == 0)
900 (void) platform_device_register(&omap_mpuio_device);
901}
902
903#else
904static inline void mpuio_init(void) {}
905#endif /* 16xx */
906
e5c56ed3
DB		 907#else
908
e5c56ed3 909#define bank_is_mpuio(bank) 0
11a78b79 910static inline void mpuio_init(void) {}
e5c56ed3
DB		 911
912#endif
913
914/*---------------------------------------------------------------------*/
5e1c5ff4 915
52e31344
DB		 916/* REVISIT these are stupid implementations! replace by ones that
917 * don't switch on METHOD_* and which mostly avoid spinlocks
918 */
919
920static int gpio_input(struct gpio_chip *chip, unsigned offset)
921{
922 struct gpio_bank *bank;
923 unsigned long flags;
924
925 bank = container_of(chip, struct gpio_bank, chip);
926 spin_lock_irqsave(&bank->lock, flags);
927 _set_gpio_direction(bank, offset, 1);
928 spin_unlock_irqrestore(&bank->lock, flags);
929 return 0;
930}
931
b37c45b8
RQ		 932static int gpio_is_input(struct gpio_bank *bank, int mask)
933{
fa87931a 934 void __iomem *reg = bank->base + bank->regs->direction;
b37c45b8 935
b37c45b8
RQ		 936 return __raw_readl(reg) & mask;
937}
938
52e31344
DB		 939static int gpio_get(struct gpio_chip *chip, unsigned offset)
940{
b37c45b8
RQ		 941 struct gpio_bank *bank;
942 void __iomem *reg;
943 int gpio;
944 u32 mask;
945
946 gpio = chip->base + offset;
a8be8daf 947 bank = container_of(chip, struct gpio_bank, chip);
b37c45b8 948 reg = bank->base;
129fd223 949 mask = GPIO_BIT(bank, gpio);
b37c45b8
RQ		 950
951 if (gpio_is_input(bank, mask))
952 return _get_gpio_datain(bank, gpio);
953 else
954 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 955}
956
957static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
958{
959 struct gpio_bank *bank;
960 unsigned long flags;
961
962 bank = container_of(chip, struct gpio_bank, chip);
963 spin_lock_irqsave(&bank->lock, flags);
fa87931a 964 bank->set_dataout(bank, offset, value);
52e31344
DB		 965 _set_gpio_direction(bank, offset, 0);
966 spin_unlock_irqrestore(&bank->lock, flags);
967 return 0;
968}
969
168ef3d9
FB		 970static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
971 unsigned debounce)
972{
973 struct gpio_bank *bank;
974 unsigned long flags;
975
976 bank = container_of(chip, struct gpio_bank, chip);
77640aab
VC		 977
978 if (!bank->dbck) {
979 bank->dbck = clk_get(bank->dev, "dbclk");
980 if (IS_ERR(bank->dbck))
981 dev_err(bank->dev, "Could not get gpio dbck\n");
982 }
983
168ef3d9
FB		 984 spin_lock_irqsave(&bank->lock, flags);
985 _set_gpio_debounce(bank, offset, debounce);
986 spin_unlock_irqrestore(&bank->lock, flags);
987
988 return 0;
989}
990
52e31344
DB		 991static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
992{
993 struct gpio_bank *bank;
994 unsigned long flags;
995
996 bank = container_of(chip, struct gpio_bank, chip);
997 spin_lock_irqsave(&bank->lock, flags);
fa87931a 998 bank->set_dataout(bank, offset, value);
52e31344
DB		 999 spin_unlock_irqrestore(&bank->lock, flags);
1000}
1001
a007b709
DB		 1002static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1003{
1004 struct gpio_bank *bank;
1005
1006 bank = container_of(chip, struct gpio_bank, chip);
1007 return bank->virtual_irq_start + offset;
1008}
1009
52e31344
DB		 1010/*---------------------------------------------------------------------*/
1011
9a748053 1012static void __init omap_gpio_show_rev(struct gpio_bank *bank)
9f7065da
TL		 1013{
1014 u32 rev;
1015
9a748053
TL		 1016 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1017 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
9f7065da 1018 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
9a748053 1019 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
9f7065da 1020 else if (cpu_is_omap44xx())
9a748053 1021 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
9f7065da
TL		 1022 else
1023 return;
1024
1025 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1026 (rev >> 4) & 0x0f, rev & 0x0f);
1027}
1028
8ba55c5c
DB		 1029/* This lock class tells lockdep that GPIO irqs are in a different
1030 * category than their parents, so it won't report false recursion.
1031 */
1032static struct lock_class_key gpio_lock_class;
1033
77640aab
VC		 1034static inline int init_gpio_info(struct platform_device *pdev)
1035{
1036 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1037 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1038 GFP_KERNEL);
1039 if (!gpio_bank) {
1040 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1041 return -ENOMEM;
1042 }
1043 return 0;
1044}
1045
1046/* TODO: Cleanup cpu_is_* checks */
2fae7fbe
VC		 1047static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1048{
1049 if (cpu_class_is_omap2()) {
1050 if (cpu_is_omap44xx()) {
1051 __raw_writel(0xffffffff, bank->base +
1052 OMAP4_GPIO_IRQSTATUSCLR0);
1053 __raw_writel(0x00000000, bank->base +
1054 OMAP4_GPIO_DEBOUNCENABLE);
1055 /* Initialize interface clk ungated, module enabled */
1056 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1057 } else if (cpu_is_omap34xx()) {
1058 __raw_writel(0x00000000, bank->base +
1059 OMAP24XX_GPIO_IRQENABLE1);
1060 __raw_writel(0xffffffff, bank->base +
1061 OMAP24XX_GPIO_IRQSTATUS1);
1062 __raw_writel(0x00000000, bank->base +
1063 OMAP24XX_GPIO_DEBOUNCE_EN);
1064
1065 /* Initialize interface clk ungated, module enabled */
1066 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1067 } else if (cpu_is_omap24xx()) {
1068 static const u32 non_wakeup_gpios[] = {
1069 0xe203ffc0, 0x08700040
1070 };
1071 if (id < ARRAY_SIZE(non_wakeup_gpios))
1072 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1073 }
1074 } else if (cpu_class_is_omap1()) {
1075 if (bank_is_mpuio(bank))
5de62b86
TL		 1076 __raw_writew(0xffff, bank->base +
1077 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
2fae7fbe
VC		 1078 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1079 __raw_writew(0xffff, bank->base
1080 + OMAP1510_GPIO_INT_MASK);
1081 __raw_writew(0x0000, bank->base
1082 + OMAP1510_GPIO_INT_STATUS);
1083 }
1084 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1085 __raw_writew(0x0000, bank->base
1086 + OMAP1610_GPIO_IRQENABLE1);
1087 __raw_writew(0xffff, bank->base
1088 + OMAP1610_GPIO_IRQSTATUS1);
1089 __raw_writew(0x0014, bank->base
1090 + OMAP1610_GPIO_SYSCONFIG);
1091
1092 /*
1093 * Enable system clock for GPIO module.
1094 * The CAM_CLK_CTRL *is* really the right place.
1095 */
1096 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1097 ULPD_CAM_CLK_CTRL);
1098 }
1099 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1100 __raw_writel(0xffffffff, bank->base
1101 + OMAP7XX_GPIO_INT_MASK);
1102 __raw_writel(0x00000000, bank->base
1103 + OMAP7XX_GPIO_INT_STATUS);
1104 }
1105 }
1106}
1107
f8b46b58
KH		 1108static __init void
1109omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1110 unsigned int num)
1111{
1112 struct irq_chip_generic *gc;
1113 struct irq_chip_type *ct;
1114
1115 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1116 handle_simple_irq);
1117 ct = gc->chip_types;
1118
1119 /* NOTE: No ack required, reading IRQ status clears it. */
1120 ct->chip.irq_mask = irq_gc_mask_set_bit;
1121 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1122 ct->chip.irq_set_type = gpio_irq_type;
1123 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1124 if (cpu_is_omap16xx())
1125 ct->chip.irq_set_wake = gpio_wake_enable,
1126
1127 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1128 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1129 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1130}
1131
d52b31de 1132static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
2fae7fbe 1133{
77640aab 1134 int j;
2fae7fbe
VC		 1135 static int gpio;
1136
2fae7fbe
VC		 1137 bank->mod_usage = 0;
1138 /*
1139 * REVISIT eventually switch from OMAP-specific gpio structs
1140 * over to the generic ones
1141 */
1142 bank->chip.request = omap_gpio_request;
1143 bank->chip.free = omap_gpio_free;
1144 bank->chip.direction_input = gpio_input;
1145 bank->chip.get = gpio_get;
1146 bank->chip.direction_output = gpio_output;
1147 bank->chip.set_debounce = gpio_debounce;
1148 bank->chip.set = gpio_set;
1149 bank->chip.to_irq = gpio_2irq;
1150 if (bank_is_mpuio(bank)) {
1151 bank->chip.label = "mpuio";
1152#ifdef CONFIG_ARCH_OMAP16XX
1153 bank->chip.dev = &omap_mpuio_device.dev;
1154#endif
1155 bank->chip.base = OMAP_MPUIO(0);
1156 } else {
1157 bank->chip.label = "gpio";
1158 bank->chip.base = gpio;
d5f46247 1159 gpio += bank->width;
2fae7fbe 1160 }
d5f46247 1161 bank->chip.ngpio = bank->width;
2fae7fbe
VC		 1162
1163 gpiochip_add(&bank->chip);
1164
1165 for (j = bank->virtual_irq_start;
d5f46247 1166 j < bank->virtual_irq_start + bank->width; j++) {
1475b85d 1167 irq_set_lockdep_class(j, &gpio_lock_class);
6845664a 1168 irq_set_chip_data(j, bank);
f8b46b58
KH		 1169 if (bank_is_mpuio(bank)) {
1170 omap_mpuio_alloc_gc(bank, j, bank->width);
1171 } else {
6845664a 1172 irq_set_chip(j, &gpio_irq_chip);
f8b46b58
KH		 1173 irq_set_handler(j, handle_simple_irq);
1174 set_irq_flags(j, IRQF_VALID);
1175 }
2fae7fbe 1176 }
6845664a
TG		 1177 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1178 irq_set_handler_data(bank->irq, bank);
2fae7fbe
VC		 1179}
1180
77640aab 1181static int __devinit omap_gpio_probe(struct platform_device *pdev)
5e1c5ff4 1182{
77640aab
VC		 1183 static int gpio_init_done;
1184 struct omap_gpio_platform_data *pdata;
1185 struct resource *res;
1186 int id;
5e1c5ff4
TL		 1187 struct gpio_bank *bank;
1188
77640aab
VC		 1189 if (!pdev->dev.platform_data)
1190 return -EINVAL;
5e1c5ff4 1191
77640aab 1192 pdata = pdev->dev.platform_data;
56a25641 1193
77640aab
VC		 1194 if (!gpio_init_done) {
1195 int ret;
5492fb1a 1196
77640aab
VC		 1197 ret = init_gpio_info(pdev);
1198 if (ret)
1199 return ret;
5492fb1a 1200 }
5492fb1a 1201
77640aab
VC		 1202 id = pdev->id;
1203 bank = &gpio_bank[id];
92105bb7 1204
77640aab
VC		 1205 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1206 if (unlikely(!res)) {
1207 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1208 return -ENODEV;
44169075 1209 }
5e1c5ff4 1210
77640aab
VC		 1211 bank->irq = res->start;
1212 bank->virtual_irq_start = pdata->virtual_irq_start;
1213 bank->method = pdata->bank_type;
1214 bank->dev = &pdev->dev;
1215 bank->dbck_flag = pdata->dbck_flag;
5de62b86 1216 bank->stride = pdata->bank_stride;
d5f46247 1217 bank->width = pdata->bank_width;
9f7065da 1218
fa87931a
KH		 1219 bank->regs = pdata->regs;
1220
1221 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1222 bank->set_dataout = _set_gpio_dataout_reg;
1223 else
1224 bank->set_dataout = _set_gpio_dataout_mask;
1225
77640aab 1226 spin_lock_init(&bank->lock);
9f7065da 1227
77640aab
VC		 1228 /* Static mapping, never released */
1229 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1230 if (unlikely(!res)) {
1231 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1232 return -ENODEV;
1233 }
89db9482 1234
77640aab
VC		 1235 bank->base = ioremap(res->start, resource_size(res));
1236 if (!bank->base) {
1237 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1238 return -ENOMEM;
5e1c5ff4
TL		 1239 }
1240
77640aab
VC		 1241 pm_runtime_enable(bank->dev);
1242 pm_runtime_get_sync(bank->dev);
1243
1244 omap_gpio_mod_init(bank, id);
1245 omap_gpio_chip_init(bank);
9a748053 1246 omap_gpio_show_rev(bank);
9f7065da 1247
77640aab
VC		 1248 if (!gpio_init_done)
1249 gpio_init_done = 1;
1250
5e1c5ff4
TL		 1251 return 0;
1252}
1253
140455fa 1254#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd 1255static int omap_gpio_suspend(void)
92105bb7
TL		 1256{
1257 int i;
1258
5492fb1a 1259 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1260 return 0;
1261
1262 for (i = 0; i < gpio_bank_count; i++) {
1263 struct gpio_bank *bank = &gpio_bank[i];
1264 void __iomem *wake_status;
1265 void __iomem *wake_clear;
1266 void __iomem *wake_set;
a6472533 1267 unsigned long flags;
92105bb7
TL		 1268
1269 switch (bank->method) {
e5c56ed3 1270#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1271 case METHOD_GPIO_1610:
1272 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1273 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1274 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1275 break;
e5c56ed3 1276#endif
a8eb7ca0 1277#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1278 case METHOD_GPIO_24XX:
723fdb78 1279 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1280 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1281 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1282 break;
78a1a6d3
SR		 1283#endif
1284#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1285 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1286 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1287 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1288 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1289 break;
e5c56ed3 1290#endif
92105bb7
TL		 1291 default:
1292 continue;
1293 }
1294
a6472533 1295 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1296 bank->saved_wakeup = __raw_readl(wake_status);
1297 __raw_writel(0xffffffff, wake_clear);
1298 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1299 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1300 }
1301
1302 return 0;
1303}
1304
3c437ffd 1305static void omap_gpio_resume(void)
92105bb7
TL		 1306{
1307 int i;
1308
723fdb78 1309 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
3c437ffd 1310 return;
92105bb7
TL		 1311
1312 for (i = 0; i < gpio_bank_count; i++) {
1313 struct gpio_bank *bank = &gpio_bank[i];
1314 void __iomem *wake_clear;
1315 void __iomem *wake_set;
a6472533 1316 unsigned long flags;
92105bb7
TL		 1317
1318 switch (bank->method) {
e5c56ed3 1319#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1320 case METHOD_GPIO_1610:
1321 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1322 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1323 break;
e5c56ed3 1324#endif
a8eb7ca0 1325#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1326 case METHOD_GPIO_24XX:
0d9356cb
TL		 1327 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1328 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1329 break;
78a1a6d3
SR		 1330#endif
1331#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1332 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1333 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1334 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1335 break;
e5c56ed3 1336#endif
92105bb7
TL		 1337 default:
1338 continue;
1339 }
1340
a6472533 1341 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1342 __raw_writel(0xffffffff, wake_clear);
1343 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1344 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1345 }
92105bb7
TL		 1346}
1347
3c437ffd 1348static struct syscore_ops omap_gpio_syscore_ops = {
92105bb7
TL		 1349 .suspend = omap_gpio_suspend,
1350 .resume = omap_gpio_resume,
1351};
1352
3ac4fa99
JY		 1353#endif
1354
140455fa 1355#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99
JY		 1356
1357static int workaround_enabled;
1358
72e06d08 1359void omap2_gpio_prepare_for_idle(int off_mode)
3ac4fa99
JY		 1360{
1361 int i, c = 0;
a118b5f3 1362 int min = 0;
3ac4fa99 1363
a118b5f3
TK		 1364 if (cpu_is_omap34xx())
1365 min = 1;
43ffcd9a 1366
a118b5f3 1367 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1368 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1369 u32 l1 = 0, l2 = 0;
0aed0435 1370 int j;
3ac4fa99 1371
0aed0435 1372 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1373 clk_disable(bank->dbck);
1374
72e06d08 1375 if (!off_mode)
43ffcd9a
KH		 1376 continue;
1377
1378 /* If going to OFF, remove triggering for all
1379 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1380 * generated. See OMAP2420 Errata item 1.101. */
3ac4fa99
JY		 1381 if (!(bank->enabled_non_wakeup_gpios))
1382 continue;
3f1686a9
TL		 1383
1384 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1385 bank->saved_datain = __raw_readl(bank->base +
1386 OMAP24XX_GPIO_DATAIN);
1387 l1 = __raw_readl(bank->base +
1388 OMAP24XX_GPIO_FALLINGDETECT);
1389 l2 = __raw_readl(bank->base +
1390 OMAP24XX_GPIO_RISINGDETECT);
1391 }
1392
1393 if (cpu_is_omap44xx()) {
1394 bank->saved_datain = __raw_readl(bank->base +
1395 OMAP4_GPIO_DATAIN);
1396 l1 = __raw_readl(bank->base +
1397 OMAP4_GPIO_FALLINGDETECT);
1398 l2 = __raw_readl(bank->base +
1399 OMAP4_GPIO_RISINGDETECT);
1400 }
1401
3ac4fa99
JY		 1402 bank->saved_fallingdetect = l1;
1403 bank->saved_risingdetect = l2;
1404 l1 &= ~bank->enabled_non_wakeup_gpios;
1405 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9
TL		 1406
1407 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1408 __raw_writel(l1, bank->base +
1409 OMAP24XX_GPIO_FALLINGDETECT);
1410 __raw_writel(l2, bank->base +
1411 OMAP24XX_GPIO_RISINGDETECT);
1412 }
1413
1414 if (cpu_is_omap44xx()) {
1415 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1416 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1417 }
1418
3ac4fa99
JY		 1419 c++;
1420 }
1421 if (!c) {
1422 workaround_enabled = 0;
1423 return;
1424 }
1425 workaround_enabled = 1;
1426}
1427
43ffcd9a 1428void omap2_gpio_resume_after_idle(void)
3ac4fa99
JY		 1429{
1430 int i;
a118b5f3 1431 int min = 0;
3ac4fa99 1432
a118b5f3
TK		 1433 if (cpu_is_omap34xx())
1434 min = 1;
1435 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1436 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1437 u32 l = 0, gen, gen0, gen1;
0aed0435 1438 int j;
3ac4fa99 1439
0aed0435 1440 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1441 clk_enable(bank->dbck);
1442
43ffcd9a
KH		 1443 if (!workaround_enabled)
1444 continue;
1445
3ac4fa99
JY		 1446 if (!(bank->enabled_non_wakeup_gpios))
1447 continue;
3f1686a9
TL		 1448
1449 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1450 __raw_writel(bank->saved_fallingdetect,
3ac4fa99 1451 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
3f1686a9 1452 __raw_writel(bank->saved_risingdetect,
3ac4fa99 1453 bank->base + OMAP24XX_GPIO_RISINGDETECT);
3f1686a9
TL		 1454 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1455 }
1456
1457 if (cpu_is_omap44xx()) {
1458 __raw_writel(bank->saved_fallingdetect,
78a1a6d3 1459 bank->base + OMAP4_GPIO_FALLINGDETECT);
3f1686a9 1460 __raw_writel(bank->saved_risingdetect,
78a1a6d3 1461 bank->base + OMAP4_GPIO_RISINGDETECT);
3f1686a9
TL		 1462 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1463 }
1464
3ac4fa99
JY		 1465 /* Check if any of the non-wakeup interrupt GPIOs have changed
1466 * state. If so, generate an IRQ by software. This is
1467 * horribly racy, but it's the best we can do to work around
1468 * this silicon bug. */
3ac4fa99 1469 l ^= bank->saved_datain;
a118b5f3 1470 l &= bank->enabled_non_wakeup_gpios;
82dbb9d3
EN		 1471
1472 /*
1473 * No need to generate IRQs for the rising edge for gpio IRQs
1474 * configured with falling edge only; and vice versa.
1475 */
1476 gen0 = l & bank->saved_fallingdetect;
1477 gen0 &= bank->saved_datain;
1478
1479 gen1 = l & bank->saved_risingdetect;
1480 gen1 &= ~(bank->saved_datain);
1481
1482 /* FIXME: Consider GPIO IRQs with level detections properly! */
1483 gen = l & (~(bank->saved_fallingdetect) &
1484 ~(bank->saved_risingdetect));
1485 /* Consider all GPIO IRQs needed to be updated */
1486 gen |= gen0 | gen1;
1487
1488 if (gen) {
3ac4fa99 1489 u32 old0, old1;
3f1686a9 1490
f00d6497 1491 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3f1686a9
TL		 1492 old0 = __raw_readl(bank->base +
1493 OMAP24XX_GPIO_LEVELDETECT0);
1494 old1 = __raw_readl(bank->base +
1495 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1496 __raw_writel(old0 | gen, bank->base +
82dbb9d3 1497 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1498 __raw_writel(old1 | gen, bank->base +
82dbb9d3 1499 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1500 __raw_writel(old0, bank->base +
3f1686a9 1501 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1502 __raw_writel(old1, bank->base +
3f1686a9
TL		 1503 OMAP24XX_GPIO_LEVELDETECT1);
1504 }
1505
1506 if (cpu_is_omap44xx()) {
1507 old0 = __raw_readl(bank->base +
78a1a6d3 1508 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1509 old1 = __raw_readl(bank->base +
78a1a6d3 1510 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1511 __raw_writel(old0 | l, bank->base +
78a1a6d3 1512 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1513 __raw_writel(old1 | l, bank->base +
78a1a6d3 1514 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1515 __raw_writel(old0, bank->base +
78a1a6d3 1516 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 1517 __raw_writel(old1, bank->base +
78a1a6d3 1518 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 1519 }
3ac4fa99
JY		 1520 }
1521 }
1522
1523}
1524
92105bb7
TL		 1525#endif
1526
a8eb7ca0 1527#ifdef CONFIG_ARCH_OMAP3
40c670f0
RN		 1528/* save the registers of bank 2-6 */
1529void omap_gpio_save_context(void)
1530{
1531 int i;
1532
1533 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1534 for (i = 1; i < gpio_bank_count; i++) {
1535 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 1536 gpio_context[i].irqenable1 =
1537 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1538 gpio_context[i].irqenable2 =
1539 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1540 gpio_context[i].wake_en =
1541 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1542 gpio_context[i].ctrl =
1543 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1544 gpio_context[i].oe =
1545 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1546 gpio_context[i].leveldetect0 =
1547 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1548 gpio_context[i].leveldetect1 =
1549 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1550 gpio_context[i].risingdetect =
1551 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1552 gpio_context[i].fallingdetect =
1553 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1554 gpio_context[i].dataout =
1555 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1556 }
1557}
1558
1559/* restore the required registers of bank 2-6 */
1560void omap_gpio_restore_context(void)
1561{
1562 int i;
1563
1564 for (i = 1; i < gpio_bank_count; i++) {
1565 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 1566 __raw_writel(gpio_context[i].irqenable1,
1567 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1568 __raw_writel(gpio_context[i].irqenable2,
1569 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1570 __raw_writel(gpio_context[i].wake_en,
1571 bank->base + OMAP24XX_GPIO_WAKE_EN);
1572 __raw_writel(gpio_context[i].ctrl,
1573 bank->base + OMAP24XX_GPIO_CTRL);
1574 __raw_writel(gpio_context[i].oe,
1575 bank->base + OMAP24XX_GPIO_OE);
1576 __raw_writel(gpio_context[i].leveldetect0,
1577 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1578 __raw_writel(gpio_context[i].leveldetect1,
1579 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1580 __raw_writel(gpio_context[i].risingdetect,
1581 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1582 __raw_writel(gpio_context[i].fallingdetect,
1583 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1584 __raw_writel(gpio_context[i].dataout,
1585 bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 1586 }
1587}
1588#endif
1589
77640aab
VC		 1590static struct platform_driver omap_gpio_driver = {
1591 .probe = omap_gpio_probe,
1592 .driver = {
1593 .name = "omap_gpio",
1594 },
1595};
1596
5e1c5ff4 1597/*
77640aab
VC		 1598 * gpio driver register needs to be done before
1599 * machine_init functions access gpio APIs.
1600 * Hence omap_gpio_drv_reg() is a postcore_initcall.
5e1c5ff4 1601 */
77640aab 1602static int __init omap_gpio_drv_reg(void)
5e1c5ff4 1603{
77640aab 1604 return platform_driver_register(&omap_gpio_driver);
5e1c5ff4 1605}
77640aab 1606postcore_initcall(omap_gpio_drv_reg);
5e1c5ff4 1607
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TL		 1608static int __init omap_gpio_sysinit(void)
1609{
11a78b79
DB		 1610 mpuio_init();
1611
140455fa 1612#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd
RW		 1613 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1614 register_syscore_ops(&omap_gpio_syscore_ops);
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TL		 1615#endif
1616
3c437ffd 1617 return 0;
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TL		 1618}
1619
92105bb7 1620arch_initcall(omap_gpio_sysinit);
Michael's Linux tree.