[thirdparty/u-boot.git] / drivers / gpio / gpio-uniphier.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016-2017 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 */

#include <common.h>
#include <dm.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <linux/errno.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>

#define UNIPHIER_GPIO_PORT_DATA		0x0	/* data */
#define UNIPHIER_GPIO_PORT_DIR		0x4	/* direction (1:in, 0:out) */
#define UNIPHIER_GPIO_IRQ_EN		0x90	/* irq enable */

struct uniphier_gpio_priv {
	void __iomem *regs;
};

static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
{
	unsigned int reg;

	reg = (bank + 1) * 8;

	/*
	 * Unfortunately, the GPIO port registers are not contiguous because
	 * offset 0x90-0x9f is used for IRQ.  Add 0x10 when crossing the region.
	 */
	if (reg >= UNIPHIER_GPIO_IRQ_EN)
		reg += 0x10;

	return reg;
}

static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
					    unsigned int *bank, u32 *mask)
{
	*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
	*mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
}

static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
				     unsigned int reg, u32 mask, u32 val)
{
	u32 tmp;

	tmp = readl(priv->regs + reg);
	tmp &= ~mask;
	tmp |= mask & val;
	writel(tmp, priv->regs + reg);
}

static void uniphier_gpio_bank_write(struct udevice *dev, unsigned int bank,
				     unsigned int reg, u32 mask, u32 val)
{
	struct uniphier_gpio_priv *priv = dev_get_priv(dev);

	if (!mask)
		return;

	uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
				 mask, val);
}

static void uniphier_gpio_offset_write(struct udevice *dev, unsigned int offset,
				       unsigned int reg, int val)
{
	unsigned int bank;
	u32 mask;

	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);

	uniphier_gpio_bank_write(dev, bank, reg, mask, val ? mask : 0);
}

static int uniphier_gpio_offset_read(struct udevice *dev,
				     unsigned int offset, unsigned int reg)
{
	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
	unsigned int bank, reg_offset;
	u32 mask;

	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
	reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;

	return !!(readl(priv->regs + reg_offset) & mask);
}

static int uniphier_gpio_get_function(struct udevice *dev, unsigned int offset)
{
	return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DIR) ?
						GPIOF_INPUT : GPIOF_OUTPUT;
}

static int uniphier_gpio_direction_input(struct udevice *dev,
					 unsigned int offset)
{
	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 1);

	return 0;
}

static int uniphier_gpio_direction_output(struct udevice *dev,
					  unsigned int offset, int value)
{
	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 0);

	return 0;
}

static int uniphier_gpio_get_value(struct udevice *dev, unsigned int offset)
{
	return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DATA);
}

static int uniphier_gpio_set_value(struct udevice *dev,
				   unsigned int offset, int value)
{
	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);

	return 0;
}

static const struct dm_gpio_ops uniphier_gpio_ops = {
	.direction_input	= uniphier_gpio_direction_input,
	.direction_output	= uniphier_gpio_direction_output,
	.get_value		= uniphier_gpio_get_value,
	.set_value		= uniphier_gpio_set_value,
	.get_function		= uniphier_gpio_get_function,
};

static int uniphier_gpio_probe(struct udevice *dev)
{
	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	fdt_addr_t addr;

	addr = devfdt_get_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->regs = devm_ioremap(dev, addr, SZ_512);
	if (!priv->regs)
		return -ENOMEM;

	uc_priv->gpio_count = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
					      "ngpios", 0);

	return 0;
}

static const struct udevice_id uniphier_gpio_match[] = {
	{ .compatible = "socionext,uniphier-gpio" },
	{ /* sentinel */ }
};

U_BOOT_DRIVER(uniphier_gpio) = {
	.name	= "uniphier-gpio",
	.id	= UCLASS_GPIO,
	.of_match = uniphier_gpio_match,
	.probe	= uniphier_gpio_probe,
	.priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
	.ops	= &uniphier_gpio_ops,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
b9a66b63	2	/*
c5fb1c25	3	* Copyright (C) 2016-2017 Socionext Inc.
4e3d8406	4	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
b9a66b63 MY	5	*/
	6
	7	#include <common.h>
9d922450	8	#include <dm.h>
b9a66b63 MY	9	#include <linux/bitops.h>
b9a66b63 MY	10	#include <linux/io.h>
bc82a131	11	#include <linux/sizes.h>
1221ce45	12	#include <linux/errno.h>
c5fb1c25	13	#include <asm/global_data.h>
b9a66b63	14	#include <asm/gpio.h>
e9986a4f	15	#include <dt-bindings/gpio/uniphier-gpio.h>
b9a66b63	16
c5fb1c25 MY	17	#define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
	18	#define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
	19	#define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */
b9a66b63 MY	20
b9a66b63 MY	21	struct uniphier_gpio_priv {
c5fb1c25	22	void __iomem *regs;
b9a66b63 MY	23	};
b9a66b63 MY	24
c5fb1c25 MY	25	static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
	26	{
	27	unsigned int reg;
	28
	29	reg = (bank + 1) * 8;
	30
	31	/*
	32	* Unfortunately, the GPIO port registers are not contiguous because
	33	* offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region.
	34	*/
	35	if (reg >= UNIPHIER_GPIO_IRQ_EN)
	36	reg += 0x10;
	37
	38	return reg;
	39	}
	40
	41	static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
	42	unsigned int bank, u32 mask)
	43	{
	44	*bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
	45	*mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
	46	}
	47
	48	static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
	49	unsigned int reg, u32 mask, u32 val)
b9a66b63	50	{
b9a66b63 MY	51	u32 tmp;
b9a66b63 MY	52
c5fb1c25 MY	53	tmp = readl(priv->regs + reg);
	54	tmp &= ~mask;
	55	tmp \|= mask & val;
	56	writel(tmp, priv->regs + reg);
b9a66b63 MY	57	}
b9a66b63 MY	58
c5fb1c25 MY	59	static void uniphier_gpio_bank_write(struct udevice *dev, unsigned int bank,
c5fb1c25 MY	60	unsigned int reg, u32 mask, u32 val)
b9a66b63 MY	61	{
	62	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
	63
c5fb1c25 MY	64	if (!mask)
	65	return;
	66
	67	uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
	68	mask, val);
b9a66b63 MY	69	}
b9a66b63 MY	70
c5fb1c25 MY	71	static void uniphier_gpio_offset_write(struct udevice *dev, unsigned int offset,
c5fb1c25 MY	72	unsigned int reg, int val)
b9a66b63	73	{
c5fb1c25 MY	74	unsigned int bank;
c5fb1c25 MY	75	u32 mask;
b9a66b63	76
c5fb1c25 MY	77	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
	78
	79	uniphier_gpio_bank_write(dev, bank, reg, mask, val ? mask : 0);
b9a66b63 MY	80	}
b9a66b63 MY	81
c5fb1c25 MY	82	static int uniphier_gpio_offset_read(struct udevice *dev,
c5fb1c25 MY	83	unsigned int offset, unsigned int reg)
b9a66b63	84	{
c5fb1c25 MY	85	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
	86	unsigned int bank, reg_offset;
	87	u32 mask;
b9a66b63	88
c5fb1c25 MY	89	uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
	90	reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
	91
	92	return !!(readl(priv->regs + reg_offset) & mask);
b9a66b63 MY	93	}
b9a66b63 MY	94
c5fb1c25	95	static int uniphier_gpio_get_function(struct udevice *dev, unsigned int offset)
b9a66b63	96	{
c5fb1c25 MY	97	return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DIR) ?
c5fb1c25 MY	98	GPIOF_INPUT : GPIOF_OUTPUT;
b9a66b63 MY	99	}
b9a66b63 MY	100
c5fb1c25 MY	101	static int uniphier_gpio_direction_input(struct udevice *dev,
c5fb1c25 MY	102	unsigned int offset)
b9a66b63	103	{
c5fb1c25	104	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 1);
b9a66b63 MY	105
	106	return 0;
	107	}
	108
c5fb1c25 MY	109	static int uniphier_gpio_direction_output(struct udevice *dev,
c5fb1c25 MY	110	unsigned int offset, int value)
b9a66b63	111	{
c5fb1c25 MY	112	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
	113	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 0);
	114
	115	return 0;
	116	}
	117
	118	static int uniphier_gpio_get_value(struct udevice *dev, unsigned int offset)
	119	{
	120	return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DATA);
	121	}
	122
	123	static int uniphier_gpio_set_value(struct udevice *dev,
	124	unsigned int offset, int value)
	125	{
	126	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
	127
	128	return 0;
b9a66b63 MY	129	}
	130
	131	static const struct dm_gpio_ops uniphier_gpio_ops = {
	132	.direction_input = uniphier_gpio_direction_input,
	133	.direction_output = uniphier_gpio_direction_output,
	134	.get_value = uniphier_gpio_get_value,
	135	.set_value = uniphier_gpio_set_value,
	136	.get_function = uniphier_gpio_get_function,
	137	};
	138
	139	static int uniphier_gpio_probe(struct udevice *dev)
	140	{
	141	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
	142	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
b9a66b63	143	fdt_addr_t addr;
b9a66b63	144
a821c4af	145	addr = devfdt_get_addr(dev);
b9a66b63 MY	146	if (addr == FDT_ADDR_T_NONE)
	147	return -EINVAL;
	148
c5fb1c25 MY	149	priv->regs = devm_ioremap(dev, addr, SZ_512);
c5fb1c25 MY	150	if (!priv->regs)
b9a66b63 MY	151	return -ENOMEM;
b9a66b63 MY	152
c5fb1c25 MY	153	uc_priv->gpio_count = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
c5fb1c25 MY	154	"ngpios", 0);
b9a66b63 MY	155
	156	return 0;
	157	}
	158
b9a66b63 MY	159	static const struct udevice_id uniphier_gpio_match[] = {
	160	{ .compatible = "socionext,uniphier-gpio" },
	161	{ /* sentinel */ }
	162	};
	163
	164	U_BOOT_DRIVER(uniphier_gpio) = {
c5fb1c25	165	.name = "uniphier-gpio",
b9a66b63 MY	166	.id = UCLASS_GPIO,
	167	.of_match = uniphier_gpio_match,
	168	.probe = uniphier_gpio_probe,
b9a66b63 MY	169	.priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
	170	.ops = &uniphier_gpio_ops,
	171	};