[people/ms/u-boot.git] / drivers / gpio / gpio-uniphier.c

/*
 * Copyright (C) 2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/sizes.h>
#include <linux/errno.h>
#include <asm/gpio.h>

#define UNIPHIER_GPIO_PORTS_PER_BANK	8

#define UNIPHIER_GPIO_REG_DATA		0	/* data */
#define UNIPHIER_GPIO_REG_DIR		4	/* direction (1:in, 0:out) */

struct uniphier_gpio_priv {
	void __iomem *base;
	char bank_name[16];
};

static void uniphier_gpio_offset_write(struct udevice *dev, unsigned offset,
				       unsigned reg, int value)
{
	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
	u32 tmp;

	tmp = readl(priv->base + reg);
	if (value)
		tmp |= BIT(offset);
	else
		tmp &= ~BIT(offset);
	writel(tmp, priv->base + reg);
}

static int uniphier_gpio_offset_read(struct udevice *dev, unsigned offset,
				     unsigned reg)
{
	struct uniphier_gpio_priv *priv = dev_get_priv(dev);

	return !!(readl(priv->base + reg) & BIT(offset));
}

static int uniphier_gpio_direction_input(struct udevice *dev, unsigned offset)
{
	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DIR, 1);

	return 0;
}

static int uniphier_gpio_direction_output(struct udevice *dev, unsigned offset,
					  int value)
{
	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DATA, value);
	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DIR, 0);

	return 0;
}

static int uniphier_gpio_get_value(struct udevice *dev, unsigned offset)
{
	return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_REG_DATA);
}

static int uniphier_gpio_set_value(struct udevice *dev, unsigned offset,
				   int value)
{
	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DATA, value);

	return 0;
}

static int uniphier_gpio_get_function(struct udevice *dev, unsigned offset)
{
	return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_REG_DIR) ?
						GPIOF_INPUT : GPIOF_OUTPUT;
}

static const struct dm_gpio_ops uniphier_gpio_ops = {
	.direction_input	= uniphier_gpio_direction_input,
	.direction_output	= uniphier_gpio_direction_output,
	.get_value		= uniphier_gpio_get_value,
	.set_value		= uniphier_gpio_set_value,
	.get_function		= uniphier_gpio_get_function,
};

static int uniphier_gpio_probe(struct udevice *dev)
{
	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	fdt_addr_t addr;
	unsigned int tmp;

	addr = dev_get_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->base = devm_ioremap(dev, addr, SZ_8);
	if (!priv->base)
		return -ENOMEM;

	uc_priv->gpio_count = UNIPHIER_GPIO_PORTS_PER_BANK;

	tmp = (addr & 0xfff);

	/* Unfortunately, there is a register hole at offset 0x90-0x9f. */
	if (tmp > 0x90)
		tmp -= 0x10;

	snprintf(priv->bank_name, sizeof(priv->bank_name) - 1,
		 "port%d-", (tmp - 8) / 8);

	uc_priv->bank_name = priv->bank_name;

	return 0;
}

/* .data = the number of GPIO banks */
static const struct udevice_id uniphier_gpio_match[] = {
	{ .compatible = "socionext,uniphier-gpio" },
	{ /* sentinel */ }
};

U_BOOT_DRIVER(uniphier_gpio) = {
	.name	= "uniphier_gpio",
	.id	= UCLASS_GPIO,
	.of_match = uniphier_gpio_match,
	.probe	= uniphier_gpio_probe,
	.priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
	.ops	= &uniphier_gpio_ops,
};
Commit	Line	Data
b9a66b63	1	/*
4e3d8406 MY	2	* Copyright (C) 2016 Socionext Inc.
4e3d8406 MY	3	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
b9a66b63 MY	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
9d922450	9	#include <dm.h>
b9a66b63 MY	10	#include <linux/bitops.h>
b9a66b63 MY	11	#include <linux/io.h>
bc82a131	12	#include <linux/sizes.h>
1221ce45	13	#include <linux/errno.h>
b9a66b63 MY	14	#include <asm/gpio.h>
	15
	16	#define UNIPHIER_GPIO_PORTS_PER_BANK 8
	17
	18	#define UNIPHIER_GPIO_REG_DATA 0 /* data */
	19	#define UNIPHIER_GPIO_REG_DIR 4 /* direction (1:in, 0:out) */
	20
	21	struct uniphier_gpio_priv {
	22	void __iomem *base;
	23	char bank_name[16];
	24	};
	25
	26	static void uniphier_gpio_offset_write(struct udevice *dev, unsigned offset,
	27	unsigned reg, int value)
	28	{
	29	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
	30	u32 tmp;
	31
	32	tmp = readl(priv->base + reg);
	33	if (value)
	34	tmp \|= BIT(offset);
	35	else
	36	tmp &= ~BIT(offset);
	37	writel(tmp, priv->base + reg);
	38	}
	39
	40	static int uniphier_gpio_offset_read(struct udevice *dev, unsigned offset,
	41	unsigned reg)
	42	{
	43	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
	44
	45	return !!(readl(priv->base + reg) & BIT(offset));
	46	}
	47
	48	static int uniphier_gpio_direction_input(struct udevice *dev, unsigned offset)
	49	{
	50	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DIR, 1);
	51
	52	return 0;
	53	}
	54
	55	static int uniphier_gpio_direction_output(struct udevice *dev, unsigned offset,
	56	int value)
	57	{
	58	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DATA, value);
	59	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DIR, 0);
	60
	61	return 0;
	62	}
	63
	64	static int uniphier_gpio_get_value(struct udevice *dev, unsigned offset)
	65	{
	66	return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_REG_DATA);
	67	}
	68
	69	static int uniphier_gpio_set_value(struct udevice *dev, unsigned offset,
	70	int value)
	71	{
	72	uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DATA, value);
	73
	74	return 0;
	75	}
	76
	77	static int uniphier_gpio_get_function(struct udevice *dev, unsigned offset)
78	{
79	return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_REG_DIR) ?
80	GPIOF_INPUT : GPIOF_OUTPUT;
81	}
82
83	static const struct dm_gpio_ops uniphier_gpio_ops = {
84	.direction_input = uniphier_gpio_direction_input,
85	.direction_output = uniphier_gpio_direction_output,
86	.get_value = uniphier_gpio_get_value,
87	.set_value = uniphier_gpio_set_value,
88	.get_function = uniphier_gpio_get_function,
89	};
90
91	static int uniphier_gpio_probe(struct udevice *dev)
92	{
93	struct uniphier_gpio_priv *priv = dev_get_priv(dev);
94	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
b9a66b63	95	fdt_addr_t addr;
b9a66b63 MY	96	unsigned int tmp;
b9a66b63 MY	97
bc82a131	98	addr = dev_get_addr(dev);
b9a66b63 MY	99	if (addr == FDT_ADDR_T_NONE)
	100	return -EINVAL;
	101
4e3d8406	102	priv->base = devm_ioremap(dev, addr, SZ_8);
b9a66b63 MY	103	if (!priv->base)
	104	return -ENOMEM;
	105
	106	uc_priv->gpio_count = UNIPHIER_GPIO_PORTS_PER_BANK;
	107
	108	tmp = (addr & 0xfff);
	109
	110	/* Unfortunately, there is a register hole at offset 0x90-0x9f. */
	111	if (tmp > 0x90)
	112	tmp -= 0x10;
	113
	114	snprintf(priv->bank_name, sizeof(priv->bank_name) - 1,
	115	"port%d-", (tmp - 8) / 8);
	116
	117	uc_priv->bank_name = priv->bank_name;
	118
	119	return 0;
	120	}
	121
b9a66b63 MY	122	/* .data = the number of GPIO banks */
	123	static const struct udevice_id uniphier_gpio_match[] = {
	124	{ .compatible = "socionext,uniphier-gpio" },
	125	{ /* sentinel */ }
	126	};
	127
	128	U_BOOT_DRIVER(uniphier_gpio) = {
	129	.name = "uniphier_gpio",
	130	.id = UCLASS_GPIO,
	131	.of_match = uniphier_gpio_match,
	132	.probe = uniphier_gpio_probe,
b9a66b63 MY	133	.priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
	134	.ops = &uniphier_gpio_ops,
	135	};