[thirdparty/kernel/stable.git] / drivers / gpio / gpio-vf610.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Freescale vf610 GPIO support through PORT and GPIO
 *
 * Copyright (c) 2014 Toradex AG.
 *
 * Author: Stefan Agner <stefan@agner.ch>.
 */
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/consumer.h>

#define VF610_GPIO_PER_PORT		32

struct fsl_gpio_soc_data {
	/* SoCs has a Port Data Direction Register (PDDR) */
	bool have_paddr;
};

struct vf610_gpio_port {
	struct gpio_chip gc;
	void __iomem *base;
	void __iomem *gpio_base;
	const struct fsl_gpio_soc_data *sdata;
	u8 irqc[VF610_GPIO_PER_PORT];
	struct clk *clk_port;
	struct clk *clk_gpio;
	int irq;
};

#define GPIO_PDOR		0x00
#define GPIO_PSOR		0x04
#define GPIO_PCOR		0x08
#define GPIO_PTOR		0x0c
#define GPIO_PDIR		0x10
#define GPIO_PDDR		0x14

#define PORT_PCR(n)		((n) * 0x4)
#define PORT_PCR_IRQC_OFFSET	16

#define PORT_ISFR		0xa0
#define PORT_DFER		0xc0
#define PORT_DFCR		0xc4
#define PORT_DFWR		0xc8

#define PORT_INT_OFF		0x0
#define PORT_INT_LOGIC_ZERO	0x8
#define PORT_INT_RISING_EDGE	0x9
#define PORT_INT_FALLING_EDGE	0xa
#define PORT_INT_EITHER_EDGE	0xb
#define PORT_INT_LOGIC_ONE	0xc

static const struct fsl_gpio_soc_data imx_data = {
	.have_paddr = true,
};

static const struct of_device_id vf610_gpio_dt_ids[] = {
	{ .compatible = "fsl,vf610-gpio",	.data = NULL, },
	{ .compatible = "fsl,imx7ulp-gpio",	.data = &imx_data, },
	{ /* sentinel */ }
};

static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
{
	writel_relaxed(val, reg);
}

static inline u32 vf610_gpio_readl(void __iomem *reg)
{
	return readl_relaxed(reg);
}

static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	unsigned long mask = BIT(gpio);
	unsigned long offset = GPIO_PDIR;

	if (port->sdata && port->sdata->have_paddr) {
		mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
		if (mask)
			offset = GPIO_PDOR;
	}

	return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio));
}

static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	unsigned long mask = BIT(gpio);
	unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR;

	vf610_gpio_writel(mask, port->gpio_base + offset);
}

static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
	struct vf610_gpio_port *port = gpiochip_get_data(chip);
	unsigned long mask = BIT(gpio);
	u32 val;

	if (port->sdata && port->sdata->have_paddr) {
		val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
		val &= ~mask;
		vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
	}

	return pinctrl_gpio_direction_input(chip->base + gpio);
}

static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
				       int value)
{
	struct vf610_gpio_port *port = gpiochip_get_data(chip);
	unsigned long mask = BIT(gpio);
	u32 val;

	vf610_gpio_set(chip, gpio, value);

	if (port->sdata && port->sdata->have_paddr) {
		val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
		val |= mask;
		vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
	}

	return pinctrl_gpio_direction_output(chip->base + gpio);
}

static void vf610_gpio_irq_handler(struct irq_desc *desc)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_desc_get_handler_data(desc));
	struct irq_chip *chip = irq_desc_get_chip(desc);
	int pin;
	unsigned long irq_isfr;

	chained_irq_enter(chip, desc);

	irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);

	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
		vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);

		generic_handle_domain_irq(port->gc.irq.domain, pin);
	}

	chained_irq_exit(chip, desc);
}

static void vf610_gpio_irq_ack(struct irq_data *d)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	int gpio = d->hwirq;

	vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
}

static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));
	u8 irqc;

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		irqc = PORT_INT_RISING_EDGE;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		irqc = PORT_INT_FALLING_EDGE;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		irqc = PORT_INT_EITHER_EDGE;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		irqc = PORT_INT_LOGIC_ZERO;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		irqc = PORT_INT_LOGIC_ONE;
		break;
	default:
		return -EINVAL;
	}

	port->irqc[d->hwirq] = irqc;

	if (type & IRQ_TYPE_LEVEL_MASK)
		irq_set_handler_locked(d, handle_level_irq);
	else
		irq_set_handler_locked(d, handle_edge_irq);

	return 0;
}

static void vf610_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);

	vf610_gpio_writel(0, pcr_base);
	gpiochip_disable_irq(gc, gpio_num);
}

static void vf610_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);

	gpiochip_enable_irq(gc, gpio_num);
	vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET,
			  pcr_base);
}

static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
{
	struct vf610_gpio_port *port =
		gpiochip_get_data(irq_data_get_irq_chip_data(d));

	if (enable)
		enable_irq_wake(port->irq);
	else
		disable_irq_wake(port->irq);

	return 0;
}

static const struct irq_chip vf610_irqchip = {
	.name = "gpio-vf610",
	.irq_ack = vf610_gpio_irq_ack,
	.irq_mask = vf610_gpio_irq_mask,
	.irq_unmask = vf610_gpio_irq_unmask,
	.irq_set_type = vf610_gpio_irq_set_type,
	.irq_set_wake = vf610_gpio_irq_set_wake,
	.flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND
			| IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

static void vf610_gpio_disable_clk(void *data)
{
	clk_disable_unprepare(data);
}

static int vf610_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct vf610_gpio_port *port;
	struct gpio_chip *gc;
	struct gpio_irq_chip *girq;
	int i;
	int ret;

	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
	if (!port)
		return -ENOMEM;

	port->sdata = of_device_get_match_data(dev);
	port->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(port->base))
		return PTR_ERR(port->base);

	port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
	if (IS_ERR(port->gpio_base))
		return PTR_ERR(port->gpio_base);

	port->irq = platform_get_irq(pdev, 0);
	if (port->irq < 0)
		return port->irq;

	port->clk_port = devm_clk_get(dev, "port");
	ret = PTR_ERR_OR_ZERO(port->clk_port);
	if (!ret) {
		ret = clk_prepare_enable(port->clk_port);
		if (ret)
			return ret;
		ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
					       port->clk_port);
		if (ret)
			return ret;
	} else if (ret == -EPROBE_DEFER) {
		/*
		 * Percolate deferrals, for anything else,
		 * just live without the clocking.
		 */
		return ret;
	}

	port->clk_gpio = devm_clk_get(dev, "gpio");
	ret = PTR_ERR_OR_ZERO(port->clk_gpio);
	if (!ret) {
		ret = clk_prepare_enable(port->clk_gpio);
		if (ret)
			return ret;
		ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
					       port->clk_gpio);
		if (ret)
			return ret;
	} else if (ret == -EPROBE_DEFER) {
		return ret;
	}

	gc = &port->gc;
	gc->parent = dev;
	gc->label = dev_name(dev);
	gc->ngpio = VF610_GPIO_PER_PORT;
	gc->base = -1;

	gc->request = gpiochip_generic_request;
	gc->free = gpiochip_generic_free;
	gc->direction_input = vf610_gpio_direction_input;
	gc->get = vf610_gpio_get;
	gc->direction_output = vf610_gpio_direction_output;
	gc->set = vf610_gpio_set;

	/* Mask all GPIO interrupts */
	for (i = 0; i < gc->ngpio; i++)
		vf610_gpio_writel(0, port->base + PORT_PCR(i));

	/* Clear the interrupt status register for all GPIO's */
	vf610_gpio_writel(~0, port->base + PORT_ISFR);

	girq = &gc->irq;
	gpio_irq_chip_set_chip(girq, &vf610_irqchip);
	girq->parent_handler = vf610_gpio_irq_handler;
	girq->num_parents = 1;
	girq->parents = devm_kcalloc(&pdev->dev, 1,
				     sizeof(*girq->parents),
				     GFP_KERNEL);
	if (!girq->parents)
		return -ENOMEM;
	girq->parents[0] = port->irq;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_edge_irq;

	return devm_gpiochip_add_data(dev, gc, port);
}

static struct platform_driver vf610_gpio_driver = {
	.driver		= {
		.name	= "gpio-vf610",
		.of_match_table = vf610_gpio_dt_ids,
	},
	.probe		= vf610_gpio_probe,
};

builtin_platform_driver(vf610_gpio_driver);
Commit	Line	Data
36e2add1	1	// SPDX-License-Identifier: GPL-2.0+
7f2691a1	2	/*
adaaf63e	3	* Freescale vf610 GPIO support through PORT and GPIO
7f2691a1 SA	4	*
	5	* Copyright (c) 2014 Toradex AG.
	6	*
	7	* Author: Stefan Agner <stefan@agner.ch>.
7f2691a1	8	*/
7f2691a1	9	#include <linux/bitops.h>
91393622	10	#include <linux/clk.h>
7f2691a1	11	#include <linux/err.h>
45e8296c	12	#include <linux/gpio/driver.h>
7f2691a1 SA	13	#include <linux/init.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/io.h>
	16	#include <linux/ioport.h>
	17	#include <linux/irq.h>
7f2691a1 SA	18	#include <linux/platform_device.h>
7f2691a1 SA	19	#include <linux/of.h>
7f2691a1	20	#include <linux/of_irq.h>
8af3a0b2	21	#include <linux/pinctrl/consumer.h>
7f2691a1 SA	22
	23	#define VF610_GPIO_PER_PORT 32
	24
659d8a62 DA	25	struct fsl_gpio_soc_data {
	26	/* SoCs has a Port Data Direction Register (PDDR) */
	27	bool have_paddr;
	28	};
	29
7f2691a1 SA	30	struct vf610_gpio_port {
	31	struct gpio_chip gc;
	32	void __iomem *base;
	33	void __iomem *gpio_base;
659d8a62	34	const struct fsl_gpio_soc_data *sdata;
7f2691a1	35	u8 irqc[VF610_GPIO_PER_PORT];
91393622 D	36	struct clk *clk_port;
91393622 D	37	struct clk *clk_gpio;
7f2691a1 SA	38	int irq;
	39	};
	40
	41	#define GPIO_PDOR 0x00
	42	#define GPIO_PSOR 0x04
	43	#define GPIO_PCOR 0x08
	44	#define GPIO_PTOR 0x0c
	45	#define GPIO_PDIR 0x10
659d8a62	46	#define GPIO_PDDR 0x14
7f2691a1 SA	47
	48	#define PORT_PCR(n) ((n) * 0x4)
	49	#define PORT_PCR_IRQC_OFFSET 16
	50
	51	#define PORT_ISFR 0xa0
	52	#define PORT_DFER 0xc0
	53	#define PORT_DFCR 0xc4
	54	#define PORT_DFWR 0xc8
	55
	56	#define PORT_INT_OFF 0x0
	57	#define PORT_INT_LOGIC_ZERO 0x8
	58	#define PORT_INT_RISING_EDGE 0x9
	59	#define PORT_INT_FALLING_EDGE 0xa
	60	#define PORT_INT_EITHER_EDGE 0xb
	61	#define PORT_INT_LOGIC_ONE 0xc
	62
659d8a62 DA	63	static const struct fsl_gpio_soc_data imx_data = {
	64	.have_paddr = true,
	65	};
	66
7f2691a1	67	static const struct of_device_id vf610_gpio_dt_ids[] = {
659d8a62 DA	68	{ .compatible = "fsl,vf610-gpio", .data = NULL, },
659d8a62 DA	69	{ .compatible = "fsl,imx7ulp-gpio", .data = &imx_data, },
7f2691a1 SA	70	{ /* sentinel */ }
	71	};
	72
	73	static inline void vf610_gpio_writel(u32 val, void __iomem *reg)
	74	{
	75	writel_relaxed(val, reg);
	76	}
	77
	78	static inline u32 vf610_gpio_readl(void __iomem *reg)
	79	{
	80	return readl_relaxed(reg);
	81	}
	82
7f2691a1 SA	83	static int vf610_gpio_get(struct gpio_chip *gc, unsigned int gpio)
7f2691a1 SA	84	{
65389b49	85	struct vf610_gpio_port *port = gpiochip_get_data(gc);
659d8a62	86	unsigned long mask = BIT(gpio);
4a8909d0	87	unsigned long offset = GPIO_PDIR;
659d8a62 DA	88
	89	if (port->sdata && port->sdata->have_paddr) {
	90	mask &= vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
4a8909d0 AS	91	if (mask)
4a8909d0 AS	92	offset = GPIO_PDOR;
659d8a62	93	}
4a8909d0 AS	94
4a8909d0 AS	95	return !!(vf610_gpio_readl(port->gpio_base + offset) & BIT(gpio));
7f2691a1 SA	96	}
	97
	98	static void vf610_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
	99	{
65389b49	100	struct vf610_gpio_port *port = gpiochip_get_data(gc);
7f2691a1	101	unsigned long mask = BIT(gpio);
a262555b	102	unsigned long offset = val ? GPIO_PSOR : GPIO_PCOR;
7f2691a1	103
a262555b	104	vf610_gpio_writel(mask, port->gpio_base + offset);
7f2691a1 SA	105	}
	106
	107	static int vf610_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
	108	{
659d8a62 DA	109	struct vf610_gpio_port *port = gpiochip_get_data(chip);
	110	unsigned long mask = BIT(gpio);
	111	u32 val;
	112
	113	if (port->sdata && port->sdata->have_paddr) {
	114	val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
	115	val &= ~mask;
	116	vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
	117	}
	118
7f2691a1 SA	119	return pinctrl_gpio_direction_input(chip->base + gpio);
	120	}
	121
	122	static int vf610_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
	123	int value)
	124	{
659d8a62 DA	125	struct vf610_gpio_port *port = gpiochip_get_data(chip);
659d8a62 DA	126	unsigned long mask = BIT(gpio);
9bf3ac46	127	u32 val;
659d8a62	128
fc363413 HC	129	vf610_gpio_set(chip, gpio, value);
fc363413 HC	130
9bf3ac46 HC	131	if (port->sdata && port->sdata->have_paddr) {
	132	val = vf610_gpio_readl(port->gpio_base + GPIO_PDDR);
	133	val \|= mask;
	134	vf610_gpio_writel(val, port->gpio_base + GPIO_PDDR);
	135	}
659d8a62	136
7f2691a1 SA	137	return pinctrl_gpio_direction_output(chip->base + gpio);
	138	}
	139
bd0b9ac4	140	static void vf610_gpio_irq_handler(struct irq_desc *desc)
7f2691a1	141	{
2f930643	142	struct vf610_gpio_port *port =
65389b49	143	gpiochip_get_data(irq_desc_get_handler_data(desc));
7f2691a1 SA	144	struct irq_chip *chip = irq_desc_get_chip(desc);
	145	int pin;
	146	unsigned long irq_isfr;
	147
	148	chained_irq_enter(chip, desc);
	149
	150	irq_isfr = vf610_gpio_readl(port->base + PORT_ISFR);
	151
	152	for_each_set_bit(pin, &irq_isfr, VF610_GPIO_PER_PORT) {
	153	vf610_gpio_writel(BIT(pin), port->base + PORT_ISFR);
	154
dbd1c54f	155	generic_handle_domain_irq(port->gc.irq.domain, pin);
7f2691a1 SA	156	}
	157
	158	chained_irq_exit(chip, desc);
	159	}
	160
	161	static void vf610_gpio_irq_ack(struct irq_data *d)
	162	{
2f930643	163	struct vf610_gpio_port *port =
65389b49	164	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	165	int gpio = d->hwirq;
	166
	167	vf610_gpio_writel(BIT(gpio), port->base + PORT_ISFR);
	168	}
	169
	170	static int vf610_gpio_irq_set_type(struct irq_data *d, u32 type)
	171	{
2f930643	172	struct vf610_gpio_port *port =
65389b49	173	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	174	u8 irqc;
	175
	176	switch (type) {
	177	case IRQ_TYPE_EDGE_RISING:
	178	irqc = PORT_INT_RISING_EDGE;
	179	break;
	180	case IRQ_TYPE_EDGE_FALLING:
	181	irqc = PORT_INT_FALLING_EDGE;
	182	break;
	183	case IRQ_TYPE_EDGE_BOTH:
	184	irqc = PORT_INT_EITHER_EDGE;
	185	break;
	186	case IRQ_TYPE_LEVEL_LOW:
	187	irqc = PORT_INT_LOGIC_ZERO;
	188	break;
	189	case IRQ_TYPE_LEVEL_HIGH:
	190	irqc = PORT_INT_LOGIC_ONE;
	191	break;
	192	default:
	193	return -EINVAL;
	194	}
	195
	196	port->irqc[d->hwirq] = irqc;
	197
fd968115	198	if (type & IRQ_TYPE_LEVEL_MASK)
a7147db0	199	irq_set_handler_locked(d, handle_level_irq);
fd968115	200	else
a7147db0	201	irq_set_handler_locked(d, handle_edge_irq);
fd968115	202
7f2691a1 SA	203	return 0;
	204	}
	205
	206	static void vf610_gpio_irq_mask(struct irq_data *d)
	207	{
e6ef4f8e AS	208	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	209	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	210	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	211	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
7f2691a1 SA	212
7f2691a1 SA	213	vf610_gpio_writel(0, pcr_base);
e6ef4f8e	214	gpiochip_disable_irq(gc, gpio_num);
7f2691a1 SA	215	}
	216
	217	static void vf610_gpio_irq_unmask(struct irq_data *d)
	218	{
e6ef4f8e AS	219	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	220	struct vf610_gpio_port *port = gpiochip_get_data(gc);
	221	irq_hw_number_t gpio_num = irqd_to_hwirq(d);
	222	void __iomem *pcr_base = port->base + PORT_PCR(gpio_num);
7f2691a1	223
e6ef4f8e AS	224	gpiochip_enable_irq(gc, gpio_num);
e6ef4f8e AS	225	vf610_gpio_writel(port->irqc[gpio_num] << PORT_PCR_IRQC_OFFSET,
7f2691a1 SA	226	pcr_base);
	227	}
	228
	229	static int vf610_gpio_irq_set_wake(struct irq_data *d, u32 enable)
	230	{
2f930643	231	struct vf610_gpio_port *port =
65389b49	232	gpiochip_get_data(irq_data_get_irq_chip_data(d));
7f2691a1 SA	233
	234	if (enable)
	235	enable_irq_wake(port->irq);
	236	else
	237	disable_irq_wake(port->irq);
	238
	239	return 0;
	240	}
	241
e6ef4f8e AS	242	static const struct irq_chip vf610_irqchip = {
	243	.name = "gpio-vf610",
	244	.irq_ack = vf610_gpio_irq_ack,
	245	.irq_mask = vf610_gpio_irq_mask,
	246	.irq_unmask = vf610_gpio_irq_unmask,
	247	.irq_set_type = vf610_gpio_irq_set_type,
	248	.irq_set_wake = vf610_gpio_irq_set_wake,
43023261 HC	249	.flags = IRQCHIP_IMMUTABLE \| IRQCHIP_MASK_ON_SUSPEND
43023261 HC	250	\| IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
e6ef4f8e AS	251	GPIOCHIP_IRQ_RESOURCE_HELPERS,
	252	};
	253
db9ed63c AS	254	static void vf610_gpio_disable_clk(void *data)
	255	{
	256	clk_disable_unprepare(data);
	257	}
7f2691a1 SA	258
	259	static int vf610_gpio_probe(struct platform_device *pdev)
	260	{
	261	struct device *dev = &pdev->dev;
7f2691a1	262	struct vf610_gpio_port *port;
7f2691a1	263	struct gpio_chip *gc;
e599256a	264	struct gpio_irq_chip *girq;
7ae710f9	265	int i;
7f2691a1 SA	266	int ret;
7f2691a1 SA	267
2e35bb6c	268	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
7f2691a1 SA	269	if (!port)
	270	return -ENOMEM;
	271
23e577eb	272	port->sdata = of_device_get_match_data(dev);
df53665b	273	port->base = devm_platform_ioremap_resource(pdev, 0);
7f2691a1 SA	274	if (IS_ERR(port->base))
	275	return PTR_ERR(port->base);
	276
df53665b	277	port->gpio_base = devm_platform_ioremap_resource(pdev, 1);
7f2691a1 SA	278	if (IS_ERR(port->gpio_base))
	279	return PTR_ERR(port->gpio_base);
	280
	281	port->irq = platform_get_irq(pdev, 0);
	282	if (port->irq < 0)
	283	return port->irq;
	284
2e35bb6c	285	port->clk_port = devm_clk_get(dev, "port");
663ba742 AS	286	ret = PTR_ERR_OR_ZERO(port->clk_port);
663ba742 AS	287	if (!ret) {
91393622 D	288	ret = clk_prepare_enable(port->clk_port);
	289	if (ret)
	290	return ret;
db9ed63c AS	291	ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
	292	port->clk_port);
	293	if (ret)
	294	return ret;
663ba742	295	} else if (ret == -EPROBE_DEFER) {
91393622 D	296	/*
	297	* Percolate deferrals, for anything else,
	298	* just live without the clocking.
	299	*/
663ba742	300	return ret;
91393622 D	301	}
91393622 D	302
2e35bb6c	303	port->clk_gpio = devm_clk_get(dev, "gpio");
663ba742 AS	304	ret = PTR_ERR_OR_ZERO(port->clk_gpio);
663ba742 AS	305	if (!ret) {
91393622	306	ret = clk_prepare_enable(port->clk_gpio);
db9ed63c	307	if (ret)
91393622	308	return ret;
fc57949c AS	309	ret = devm_add_action_or_reset(dev, vf610_gpio_disable_clk,
	310	port->clk_gpio);
	311	if (ret)
91393622	312	return ret;
663ba742 AS	313	} else if (ret == -EPROBE_DEFER) {
663ba742 AS	314	return ret;
91393622 D	315	}
91393622 D	316
7f2691a1	317	gc = &port->gc;
58383c78	318	gc->parent = dev;
6f8ecb7f	319	gc->label = dev_name(dev);
d32efe37	320	gc->ngpio = VF610_GPIO_PER_PORT;
bb5ad5ef	321	gc->base = -1;
7f2691a1	322
203f0daa JG	323	gc->request = gpiochip_generic_request;
203f0daa JG	324	gc->free = gpiochip_generic_free;
d32efe37 AL	325	gc->direction_input = vf610_gpio_direction_input;
	326	gc->get = vf610_gpio_get;
	327	gc->direction_output = vf610_gpio_direction_output;
	328	gc->set = vf610_gpio_set;
7f2691a1	329
7ae710f9 AL	330	/* Mask all GPIO interrupts */
	331	for (i = 0; i < gc->ngpio; i++)
	332	vf610_gpio_writel(0, port->base + PORT_PCR(i));
	333
7f2691a1 SA	334	/* Clear the interrupt status register for all GPIO's */
	335	vf610_gpio_writel(~0, port->base + PORT_ISFR);
	336
e599256a	337	girq = &gc->irq;
e6ef4f8e	338	gpio_irq_chip_set_chip(girq, &vf610_irqchip);
e599256a LW	339	girq->parent_handler = vf610_gpio_irq_handler;
	340	girq->num_parents = 1;
	341	girq->parents = devm_kcalloc(&pdev->dev, 1,
	342	sizeof(*girq->parents),
	343	GFP_KERNEL);
	344	if (!girq->parents)
	345	return -ENOMEM;
	346	girq->parents[0] = port->irq;
	347	girq->default_type = IRQ_TYPE_NONE;
	348	girq->handler = handle_edge_irq;
7f2691a1	349
e599256a	350	return devm_gpiochip_add_data(dev, gc, port);
7f2691a1 SA	351	}
	352
	353	static struct platform_driver vf610_gpio_driver = {
	354	.driver = {
	355	.name = "gpio-vf610",
7f2691a1 SA	356	.of_match_table = vf610_gpio_dt_ids,
	357	},
	358	.probe = vf610_gpio_probe,
	359	};
	360
df950da1	361	builtin_platform_driver(vf610_gpio_driver);