[thirdparty/u-boot.git] / drivers / gpio / intel_ich6_gpio.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2012 The Chromium OS Authors.
 */

/*
 * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
 * through the PCI bus. Each PCI device has 256 bytes of configuration space,
 * consisting of a standard header and a device-specific set of registers. PCI
 * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
 * other things). Within the PCI configuration space, the GPIOBASE register
 * tells us where in the device's I/O region we can find more registers to
 * actually access the GPIOs.
 *
 * PCI bus/device/function 0:1f:0  => PCI config registers
 *   PCI config register "GPIOBASE"
 *     PCI I/O space + [GPIOBASE]  => start of GPIO registers
 *       GPIO registers => gpio pin function, direction, value
 *
 *
 * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
 * ICH versions have more, but the decoding the matrix that describes them is
 * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
 * but they will ONLY work for certain unspecified chipsets because the offset
 * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
 * reserved or subject to arcane restrictions.
 */

#include <common.h>
#include <dm.h>
#include <errno.h>
#include <fdtdec.h>
#include <pch.h>
#include <pci.h>
#include <asm/cpu.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/pci.h>

DECLARE_GLOBAL_DATA_PTR;

#define GPIO_PER_BANK	32

struct ich6_bank_priv {
	/* These are I/O addresses */
	uint16_t use_sel;
	uint16_t io_sel;
	uint16_t lvl;
	u32 lvl_write_cache;
	bool use_lvl_write_cache;
};

#define GPIO_USESEL_OFFSET(x)	(x)
#define GPIO_IOSEL_OFFSET(x)	(x + 4)
#define GPIO_LVL_OFFSET(x)	(x + 8)

static int _ich6_gpio_set_value(struct ich6_bank_priv *bank, unsigned offset,
				int value)
{
	u32 val;

	if (bank->use_lvl_write_cache)
		val = bank->lvl_write_cache;
	else
		val = inl(bank->lvl);

	if (value)
		val |= (1UL << offset);
	else
		val &= ~(1UL << offset);
	outl(val, bank->lvl);
	if (bank->use_lvl_write_cache)
		bank->lvl_write_cache = val;

	return 0;
}

static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
{
	u32 val;

	if (!dir) {
		val = inl(base);
		val |= (1UL << offset);
		outl(val, base);
	} else {
		val = inl(base);
		val &= ~(1UL << offset);
		outl(val, base);
	}

	return 0;
}

static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
{
	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
	u32 gpiobase;
	int offset;
	int ret;

	ret = pch_get_gpio_base(dev->parent, &gpiobase);
	if (ret)
		return ret;

	offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
	if (offset == -1) {
		debug("%s: Invalid register offset %d\n", __func__, offset);
		return -EINVAL;
	}
	plat->offset = offset;
	plat->base_addr = gpiobase + offset;
	plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
				      "bank-name", NULL);

	return 0;
}

static int ich6_gpio_probe(struct udevice *dev)
{
	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	struct ich6_bank_priv *bank = dev_get_priv(dev);
	const void *prop;

	uc_priv->gpio_count = GPIO_PER_BANK;
	uc_priv->bank_name = plat->bank_name;
	bank->use_sel = plat->base_addr;
	bank->io_sel = plat->base_addr + 4;
	bank->lvl = plat->base_addr + 8;

	prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
			   "use-lvl-write-cache", NULL);
	if (prop)
		bank->use_lvl_write_cache = true;
	else
		bank->use_lvl_write_cache = false;
	bank->lvl_write_cache = 0;

	return 0;
}

static int ich6_gpio_request(struct udevice *dev, unsigned offset,
			     const char *label)
{
	struct ich6_bank_priv *bank = dev_get_priv(dev);
	u32 tmplong;

	/*
	 * Make sure that the GPIO pin we want isn't already in use for some
	 * built-in hardware function. We have to check this for every
	 * requested pin.
	 */
	tmplong = inl(bank->use_sel);
	if (!(tmplong & (1UL << offset))) {
		debug("%s: gpio %d is reserved for internal use\n", __func__,
		      offset);
		return -EPERM;
	}

	return 0;
}

static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
{
	struct ich6_bank_priv *bank = dev_get_priv(dev);

	return _ich6_gpio_set_direction(bank->io_sel, offset, 0);
}

static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
				       int value)
{
	int ret;
	struct ich6_bank_priv *bank = dev_get_priv(dev);

	ret = _ich6_gpio_set_direction(bank->io_sel, offset, 1);
	if (ret)
		return ret;

	return _ich6_gpio_set_value(bank, offset, value);
}

static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
{
	struct ich6_bank_priv *bank = dev_get_priv(dev);
	u32 tmplong;
	int r;

	tmplong = inl(bank->lvl);
	if (bank->use_lvl_write_cache)
		tmplong |= bank->lvl_write_cache;
	r = (tmplong & (1UL << offset)) ? 1 : 0;
	return r;
}

static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
			       int value)
{
	struct ich6_bank_priv *bank = dev_get_priv(dev);
	return _ich6_gpio_set_value(bank, offset, value);
}

static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
{
	struct ich6_bank_priv *bank = dev_get_priv(dev);
	u32 mask = 1UL << offset;

	if (!(inl(bank->use_sel) & mask))
		return GPIOF_FUNC;
	if (inl(bank->io_sel) & mask)
		return GPIOF_INPUT;
	else
		return GPIOF_OUTPUT;
}

static const struct dm_gpio_ops gpio_ich6_ops = {
	.request		= ich6_gpio_request,
	.direction_input	= ich6_gpio_direction_input,
	.direction_output	= ich6_gpio_direction_output,
	.get_value		= ich6_gpio_get_value,
	.set_value		= ich6_gpio_set_value,
	.get_function		= ich6_gpio_get_function,
};

static const struct udevice_id intel_ich6_gpio_ids[] = {
	{ .compatible = "intel,ich6-gpio" },
	{ }
};

U_BOOT_DRIVER(gpio_ich6) = {
	.name	= "gpio_ich6",
	.id	= UCLASS_GPIO,
	.of_match = intel_ich6_gpio_ids,
	.ops	= &gpio_ich6_ops,
	.ofdata_to_platdata	= gpio_ich6_ofdata_to_platdata,
	.probe	= ich6_gpio_probe,
	.priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
	.platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
55ae10f8 BR	2	/*
55ae10f8 BR	3	* Copyright (c) 2012 The Chromium OS Authors.
55ae10f8 BR	4	*/
	5
	6	/*
	7	* This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed
	8	* through the PCI bus. Each PCI device has 256 bytes of configuration space,
	9	* consisting of a standard header and a device-specific set of registers. PCI
	10	* bus 0, device 31, function 0 gives us access to the chipset GPIOs (among
	11	* other things). Within the PCI configuration space, the GPIOBASE register
	12	* tells us where in the device's I/O region we can find more registers to
	13	* actually access the GPIOs.
	14	*
	15	* PCI bus/device/function 0:1f:0 => PCI config registers
	16	* PCI config register "GPIOBASE"
	17	* PCI I/O space + [GPIOBASE] => start of GPIO registers
	18	* GPIO registers => gpio pin function, direction, value
57be9172 BR	19	*
	20	*
	21	* Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most
	22	* ICH versions have more, but the decoding the matrix that describes them is
	23	* absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2,
	24	* but they will ONLY work for certain unspecified chipsets because the offset
	25	* from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or
	26	* reserved or subject to arcane restrictions.
55ae10f8 BR	27	*/
	28
	29	#include <common.h>
7414112d SG	30	#include <dm.h>
	31	#include <errno.h>
	32	#include <fdtdec.h>
3ddc1c7b	33	#include <pch.h>
55ae10f8	34	#include <pci.h>
15cf75ec	35	#include <asm/cpu.h>
55ae10f8 BR	36	#include <asm/gpio.h>
55ae10f8 BR	37	#include <asm/io.h>
1b4f25ff	38	#include <asm/pci.h>
55ae10f8	39
8b097916 SG	40	DECLARE_GLOBAL_DATA_PTR;
8b097916 SG	41
7414112d SG	42	#define GPIO_PER_BANK 32
7414112d SG	43
7414112d SG	44	struct ich6_bank_priv {
7414112d SG	45	/* These are I/O addresses */
b71eec31 BM	46	uint16_t use_sel;
	47	uint16_t io_sel;
	48	uint16_t lvl;
770ee017 BM	49	u32 lvl_write_cache;
770ee017 BM	50	bool use_lvl_write_cache;
57be9172 BR	51	};
57be9172 BR	52
5318f18d GH	53	#define GPIO_USESEL_OFFSET(x) (x)
	54	#define GPIO_IOSEL_OFFSET(x) (x + 4)
	55	#define GPIO_LVL_OFFSET(x) (x + 8)
	56
770ee017 BM	57	static int _ich6_gpio_set_value(struct ich6_bank_priv *bank, unsigned offset,
770ee017 BM	58	int value)
5318f18d GH	59	{
	60	u32 val;
	61
770ee017 BM	62	if (bank->use_lvl_write_cache)
	63	val = bank->lvl_write_cache;
	64	else
	65	val = inl(bank->lvl);
	66
5318f18d GH	67	if (value)
	68	val \|= (1UL << offset);
	69	else
	70	val &= ~(1UL << offset);
770ee017 BM	71	outl(val, bank->lvl);
	72	if (bank->use_lvl_write_cache)
	73	bank->lvl_write_cache = val;
5318f18d GH	74
	75	return 0;
	76	}
	77
5318f18d GH	78	static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
	79	{
	80	u32 val;
	81
	82	if (!dir) {
	83	val = inl(base);
	84	val \|= (1UL << offset);
	85	outl(val, base);
	86	} else {
	87	val = inl(base);
	88	val &= ~(1UL << offset);
	89	outl(val, base);
	90	}
	91
	92	return 0;
	93	}
	94
5318f18d GH	95	static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
	96	{
	97	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
3ddc1c7b	98	u32 gpiobase;
5318f18d	99	int offset;
3ddc1c7b BM	100	int ret;
	101
	102	ret = pch_get_gpio_base(dev->parent, &gpiobase);
	103	if (ret)
	104	return ret;
5318f18d	105
e160f7d4	106	offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", -1);
7414112d SG	107	if (offset == -1) {
	108	debug("%s: Invalid register offset %d\n", __func__, offset);
	109	return -EINVAL;
	110	}
d6d50db8	111	plat->offset = offset;
7414112d	112	plat->base_addr = gpiobase + offset;
e160f7d4	113	plat->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
7414112d	114	"bank-name", NULL);
55ae10f8	115
55ae10f8 BR	116	return 0;
	117	}
	118
1b4f25ff	119	static int ich6_gpio_probe(struct udevice *dev)
55ae10f8	120	{
7414112d	121	struct ich6_bank_platdata *plat = dev_get_platdata(dev);
e564f054	122	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
7414112d	123	struct ich6_bank_priv *bank = dev_get_priv(dev);
770ee017	124	const void *prop;
2795573a	125
7414112d SG	126	uc_priv->gpio_count = GPIO_PER_BANK;
	127	uc_priv->bank_name = plat->bank_name;
	128	bank->use_sel = plat->base_addr;
	129	bank->io_sel = plat->base_addr + 4;
	130	bank->lvl = plat->base_addr + 8;
55ae10f8	131
da409ccc	132	prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
770ee017 BM	133	"use-lvl-write-cache", NULL);
	134	if (prop)
	135	bank->use_lvl_write_cache = true;
	136	else
	137	bank->use_lvl_write_cache = false;
	138	bank->lvl_write_cache = 0;
	139
7414112d SG	140	return 0;
7414112d SG	141	}
55ae10f8	142
1b4f25ff SG	143	static int ich6_gpio_request(struct udevice *dev, unsigned offset,
1b4f25ff SG	144	const char *label)
7414112d SG	145	{
	146	struct ich6_bank_priv *bank = dev_get_priv(dev);
	147	u32 tmplong;
55ae10f8 BR	148
	149	/*
	150	* Make sure that the GPIO pin we want isn't already in use for some
	151	* built-in hardware function. We have to check this for every
	152	* requested pin.
	153	*/
7414112d SG	154	tmplong = inl(bank->use_sel);
7414112d SG	155	if (!(tmplong & (1UL << offset))) {
57be9172	156	debug("%s: gpio %d is reserved for internal use\n", __func__,
7414112d SG	157	offset);
7414112d SG	158	return -EPERM;
55ae10f8 BR	159	}
55ae10f8 BR	160
55ae10f8 BR	161	return 0;
	162	}
	163
7414112d	164	static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset)
55ae10f8	165	{
7414112d	166	struct ich6_bank_priv *bank = dev_get_priv(dev);
57be9172	167
e7cc0b6f	168	return _ich6_gpio_set_direction(bank->io_sel, offset, 0);
55ae10f8 BR	169	}
55ae10f8 BR	170
7414112d SG	171	static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset,
7414112d SG	172	int value)
55ae10f8	173	{
5318f18d	174	int ret;
7414112d	175	struct ich6_bank_priv *bank = dev_get_priv(dev);
55ae10f8	176
e7cc0b6f	177	ret = _ich6_gpio_set_direction(bank->io_sel, offset, 1);
5318f18d GH	178	if (ret)
5318f18d GH	179	return ret;
0a54745f	180
770ee017	181	return _ich6_gpio_set_value(bank, offset, value);
55ae10f8 BR	182	}
55ae10f8 BR	183
7414112d	184	static int ich6_gpio_get_value(struct udevice *dev, unsigned offset)
55ae10f8	185	{
7414112d	186	struct ich6_bank_priv *bank = dev_get_priv(dev);
55ae10f8	187	u32 tmplong;
57be9172	188	int r;
55ae10f8	189
7414112d	190	tmplong = inl(bank->lvl);
770ee017 BM	191	if (bank->use_lvl_write_cache)
770ee017 BM	192	tmplong \|= bank->lvl_write_cache;
7414112d	193	r = (tmplong & (1UL << offset)) ? 1 : 0;
57be9172	194	return r;
55ae10f8 BR	195	}
55ae10f8 BR	196
7414112d SG	197	static int ich6_gpio_set_value(struct udevice *dev, unsigned offset,
7414112d SG	198	int value)
55ae10f8	199	{
7414112d	200	struct ich6_bank_priv *bank = dev_get_priv(dev);
770ee017	201	return _ich6_gpio_set_value(bank, offset, value);
55ae10f8	202	}
7414112d SG	203
	204	static int ich6_gpio_get_function(struct udevice *dev, unsigned offset)
	205	{
	206	struct ich6_bank_priv *bank = dev_get_priv(dev);
	207	u32 mask = 1UL << offset;
	208
	209	if (!(inl(bank->use_sel) & mask))
	210	return GPIOF_FUNC;
	211	if (inl(bank->io_sel) & mask)
	212	return GPIOF_INPUT;
	213	else
	214	return GPIOF_OUTPUT;
	215	}
	216
	217	static const struct dm_gpio_ops gpio_ich6_ops = {
	218	.request = ich6_gpio_request,
	219	.direction_input = ich6_gpio_direction_input,
	220	.direction_output = ich6_gpio_direction_output,
	221	.get_value = ich6_gpio_get_value,
	222	.set_value = ich6_gpio_set_value,
	223	.get_function = ich6_gpio_get_function,
	224	};
	225
	226	static const struct udevice_id intel_ich6_gpio_ids[] = {
	227	{ .compatible = "intel,ich6-gpio" },
	228	{ }
	229	};
	230
	231	U_BOOT_DRIVER(gpio_ich6) = {
	232	.name = "gpio_ich6",
	233	.id = UCLASS_GPIO,
	234	.of_match = intel_ich6_gpio_ids,
	235	.ops = &gpio_ich6_ops,
	236	.ofdata_to_platdata = gpio_ich6_ofdata_to_platdata,
	237	.probe = ich6_gpio_probe,
	238	.priv_auto_alloc_size = sizeof(struct ich6_bank_priv),
	239	.platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata),
	240	};