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55ae10f8 BR |
1 | /* |
2 | * Copyright (c) 2012 The Chromium OS Authors. | |
1a459660 | 3 | * SPDX-License-Identifier: GPL-2.0+ |
55ae10f8 BR |
4 | */ |
5 | ||
6 | /* | |
7 | * This is a GPIO driver for Intel ICH6 and later. The x86 GPIOs are accessed | |
8 | * through the PCI bus. Each PCI device has 256 bytes of configuration space, | |
9 | * consisting of a standard header and a device-specific set of registers. PCI | |
10 | * bus 0, device 31, function 0 gives us access to the chipset GPIOs (among | |
11 | * other things). Within the PCI configuration space, the GPIOBASE register | |
12 | * tells us where in the device's I/O region we can find more registers to | |
13 | * actually access the GPIOs. | |
14 | * | |
15 | * PCI bus/device/function 0:1f:0 => PCI config registers | |
16 | * PCI config register "GPIOBASE" | |
17 | * PCI I/O space + [GPIOBASE] => start of GPIO registers | |
18 | * GPIO registers => gpio pin function, direction, value | |
57be9172 BR |
19 | * |
20 | * | |
21 | * Danger Will Robinson! Bank 0 (GPIOs 0-31) seems to be fairly stable. Most | |
22 | * ICH versions have more, but the decoding the matrix that describes them is | |
23 | * absurdly complex and constantly changing. We'll provide Bank 1 and Bank 2, | |
24 | * but they will ONLY work for certain unspecified chipsets because the offset | |
25 | * from GPIOBASE changes randomly. Even then, many GPIOs are unimplemented or | |
26 | * reserved or subject to arcane restrictions. | |
55ae10f8 BR |
27 | */ |
28 | ||
29 | #include <common.h> | |
7414112d SG |
30 | #include <dm.h> |
31 | #include <errno.h> | |
32 | #include <fdtdec.h> | |
55ae10f8 BR |
33 | #include <pci.h> |
34 | #include <asm/gpio.h> | |
35 | #include <asm/io.h> | |
1b4f25ff | 36 | #include <asm/pci.h> |
55ae10f8 | 37 | |
7414112d SG |
38 | #define GPIO_PER_BANK 32 |
39 | ||
7414112d SG |
40 | struct ich6_bank_priv { |
41 | /* These are I/O addresses */ | |
b71eec31 BM |
42 | uint16_t use_sel; |
43 | uint16_t io_sel; | |
44 | uint16_t lvl; | |
57be9172 BR |
45 | }; |
46 | ||
1b4f25ff SG |
47 | /* TODO: Move this to device tree, or platform data */ |
48 | void ich_gpio_set_gpio_map(const struct pch_gpio_map *map) | |
49 | { | |
50 | gd->arch.gpio_map = map; | |
51 | } | |
1b4f25ff | 52 | |
7414112d | 53 | static int gpio_ich6_ofdata_to_platdata(struct udevice *dev) |
55ae10f8 | 54 | { |
7414112d SG |
55 | struct ich6_bank_platdata *plat = dev_get_platdata(dev); |
56 | pci_dev_t pci_dev; /* handle for 0:1f:0 */ | |
55ae10f8 BR |
57 | u8 tmpbyte; |
58 | u16 tmpword; | |
59 | u32 tmplong; | |
b71eec31 | 60 | u16 gpiobase; |
7414112d | 61 | int offset; |
55ae10f8 BR |
62 | |
63 | /* Where should it be? */ | |
7414112d | 64 | pci_dev = PCI_BDF(0, 0x1f, 0); |
55ae10f8 BR |
65 | |
66 | /* Is the device present? */ | |
1b4f25ff | 67 | tmpword = pci_read_config16(pci_dev, PCI_VENDOR_ID); |
55ae10f8 BR |
68 | if (tmpword != PCI_VENDOR_ID_INTEL) { |
69 | debug("%s: wrong VendorID\n", __func__); | |
7414112d | 70 | return -ENODEV; |
55ae10f8 | 71 | } |
57be9172 | 72 | |
1b4f25ff | 73 | tmpword = pci_read_config16(pci_dev, PCI_DEVICE_ID); |
57be9172 | 74 | debug("Found %04x:%04x\n", PCI_VENDOR_ID_INTEL, tmpword); |
55ae10f8 | 75 | /* |
57be9172 | 76 | * We'd like to validate the Device ID too, but pretty much any |
55ae10f8 | 77 | * value is either a) correct with slight differences, or b) |
57be9172 BR |
78 | * correct but undocumented. We'll have to check a bunch of other |
79 | * things instead... | |
55ae10f8 BR |
80 | */ |
81 | ||
82 | /* I/O should already be enabled (it's a RO bit). */ | |
1b4f25ff | 83 | tmpword = pci_read_config16(pci_dev, PCI_COMMAND); |
55ae10f8 BR |
84 | if (!(tmpword & PCI_COMMAND_IO)) { |
85 | debug("%s: device IO not enabled\n", __func__); | |
7414112d | 86 | return -ENODEV; |
55ae10f8 BR |
87 | } |
88 | ||
89 | /* Header Type must be normal (bits 6-0 only; see spec.) */ | |
1b4f25ff | 90 | tmpbyte = pci_read_config8(pci_dev, PCI_HEADER_TYPE); |
55ae10f8 BR |
91 | if ((tmpbyte & 0x7f) != PCI_HEADER_TYPE_NORMAL) { |
92 | debug("%s: invalid Header type\n", __func__); | |
7414112d | 93 | return -ENODEV; |
55ae10f8 BR |
94 | } |
95 | ||
96 | /* Base Class must be a bridge device */ | |
1b4f25ff | 97 | tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_CODE); |
55ae10f8 BR |
98 | if (tmpbyte != PCI_CLASS_CODE_BRIDGE) { |
99 | debug("%s: invalid class\n", __func__); | |
7414112d | 100 | return -ENODEV; |
55ae10f8 BR |
101 | } |
102 | /* Sub Class must be ISA */ | |
1b4f25ff | 103 | tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_SUB_CODE); |
55ae10f8 BR |
104 | if (tmpbyte != PCI_CLASS_SUB_CODE_BRIDGE_ISA) { |
105 | debug("%s: invalid subclass\n", __func__); | |
7414112d | 106 | return -ENODEV; |
55ae10f8 BR |
107 | } |
108 | ||
109 | /* Programming Interface must be 0x00 (no others exist) */ | |
1b4f25ff | 110 | tmpbyte = pci_read_config8(pci_dev, PCI_CLASS_PROG); |
55ae10f8 BR |
111 | if (tmpbyte != 0x00) { |
112 | debug("%s: invalid interface type\n", __func__); | |
7414112d | 113 | return -ENODEV; |
55ae10f8 BR |
114 | } |
115 | ||
116 | /* | |
117 | * GPIOBASE moved to its current offset with ICH6, but prior to | |
118 | * that it was unused (or undocumented). Check that it looks | |
b71eec31 BM |
119 | * okay: not all ones or zeros. |
120 | * | |
121 | * Note we don't need check bit0 here, because the Tunnel Creek | |
122 | * GPIO base address register bit0 is reserved (read returns 0), | |
123 | * while on the Ivybridge the bit0 is used to indicate it is an | |
124 | * I/O space. | |
55ae10f8 | 125 | */ |
1b4f25ff | 126 | tmplong = pci_read_config32(pci_dev, PCI_CFG_GPIOBASE); |
b71eec31 | 127 | if (tmplong == 0x00000000 || tmplong == 0xffffffff) { |
55ae10f8 | 128 | debug("%s: unexpected GPIOBASE value\n", __func__); |
7414112d | 129 | return -ENODEV; |
55ae10f8 BR |
130 | } |
131 | ||
132 | /* | |
133 | * Okay, I guess we're looking at the right device. The actual | |
134 | * GPIO registers are in the PCI device's I/O space, starting | |
135 | * at the offset that we just read. Bit 0 indicates that it's | |
136 | * an I/O address, not a memory address, so mask that off. | |
137 | */ | |
b71eec31 | 138 | gpiobase = tmplong & 0xfffe; |
7414112d SG |
139 | offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "reg", -1); |
140 | if (offset == -1) { | |
141 | debug("%s: Invalid register offset %d\n", __func__, offset); | |
142 | return -EINVAL; | |
143 | } | |
144 | plat->base_addr = gpiobase + offset; | |
145 | plat->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, | |
146 | "bank-name", NULL); | |
55ae10f8 | 147 | |
55ae10f8 BR |
148 | return 0; |
149 | } | |
150 | ||
1b4f25ff | 151 | static int ich6_gpio_probe(struct udevice *dev) |
55ae10f8 | 152 | { |
7414112d SG |
153 | struct ich6_bank_platdata *plat = dev_get_platdata(dev); |
154 | struct gpio_dev_priv *uc_priv = dev->uclass_priv; | |
155 | struct ich6_bank_priv *bank = dev_get_priv(dev); | |
156 | ||
1b4f25ff | 157 | if (gd->arch.gpio_map) { |
2795573a | 158 | setup_pch_gpios(plat->base_addr, gd->arch.gpio_map); |
1b4f25ff SG |
159 | gd->arch.gpio_map = NULL; |
160 | } | |
2795573a | 161 | |
7414112d SG |
162 | uc_priv->gpio_count = GPIO_PER_BANK; |
163 | uc_priv->bank_name = plat->bank_name; | |
164 | bank->use_sel = plat->base_addr; | |
165 | bank->io_sel = plat->base_addr + 4; | |
166 | bank->lvl = plat->base_addr + 8; | |
55ae10f8 | 167 | |
7414112d SG |
168 | return 0; |
169 | } | |
55ae10f8 | 170 | |
1b4f25ff SG |
171 | static int ich6_gpio_request(struct udevice *dev, unsigned offset, |
172 | const char *label) | |
7414112d SG |
173 | { |
174 | struct ich6_bank_priv *bank = dev_get_priv(dev); | |
175 | u32 tmplong; | |
55ae10f8 BR |
176 | |
177 | /* | |
178 | * Make sure that the GPIO pin we want isn't already in use for some | |
179 | * built-in hardware function. We have to check this for every | |
180 | * requested pin. | |
181 | */ | |
7414112d SG |
182 | tmplong = inl(bank->use_sel); |
183 | if (!(tmplong & (1UL << offset))) { | |
57be9172 | 184 | debug("%s: gpio %d is reserved for internal use\n", __func__, |
7414112d SG |
185 | offset); |
186 | return -EPERM; | |
55ae10f8 BR |
187 | } |
188 | ||
55ae10f8 BR |
189 | return 0; |
190 | } | |
191 | ||
7414112d | 192 | static int ich6_gpio_direction_input(struct udevice *dev, unsigned offset) |
55ae10f8 | 193 | { |
7414112d | 194 | struct ich6_bank_priv *bank = dev_get_priv(dev); |
55ae10f8 | 195 | u32 tmplong; |
57be9172 | 196 | |
7414112d SG |
197 | tmplong = inl(bank->io_sel); |
198 | tmplong |= (1UL << offset); | |
199 | outl(bank->io_sel, tmplong); | |
55ae10f8 BR |
200 | return 0; |
201 | } | |
202 | ||
7414112d SG |
203 | static int ich6_gpio_direction_output(struct udevice *dev, unsigned offset, |
204 | int value) | |
55ae10f8 | 205 | { |
7414112d | 206 | struct ich6_bank_priv *bank = dev_get_priv(dev); |
55ae10f8 BR |
207 | u32 tmplong; |
208 | ||
0a54745f AL |
209 | gpio_set_value(offset, value); |
210 | ||
7414112d SG |
211 | tmplong = inl(bank->io_sel); |
212 | tmplong &= ~(1UL << offset); | |
213 | outl(bank->io_sel, tmplong); | |
55ae10f8 BR |
214 | return 0; |
215 | } | |
216 | ||
7414112d SG |
217 | static int ich6_gpio_get_value(struct udevice *dev, unsigned offset) |
218 | ||
55ae10f8 | 219 | { |
7414112d | 220 | struct ich6_bank_priv *bank = dev_get_priv(dev); |
55ae10f8 | 221 | u32 tmplong; |
57be9172 | 222 | int r; |
55ae10f8 | 223 | |
7414112d SG |
224 | tmplong = inl(bank->lvl); |
225 | r = (tmplong & (1UL << offset)) ? 1 : 0; | |
57be9172 | 226 | return r; |
55ae10f8 BR |
227 | } |
228 | ||
7414112d SG |
229 | static int ich6_gpio_set_value(struct udevice *dev, unsigned offset, |
230 | int value) | |
55ae10f8 | 231 | { |
7414112d | 232 | struct ich6_bank_priv *bank = dev_get_priv(dev); |
55ae10f8 BR |
233 | u32 tmplong; |
234 | ||
7414112d | 235 | tmplong = inl(bank->lvl); |
55ae10f8 | 236 | if (value) |
7414112d | 237 | tmplong |= (1UL << offset); |
55ae10f8 | 238 | else |
7414112d SG |
239 | tmplong &= ~(1UL << offset); |
240 | outl(bank->lvl, tmplong); | |
55ae10f8 BR |
241 | return 0; |
242 | } | |
7414112d SG |
243 | |
244 | static int ich6_gpio_get_function(struct udevice *dev, unsigned offset) | |
245 | { | |
246 | struct ich6_bank_priv *bank = dev_get_priv(dev); | |
247 | u32 mask = 1UL << offset; | |
248 | ||
249 | if (!(inl(bank->use_sel) & mask)) | |
250 | return GPIOF_FUNC; | |
251 | if (inl(bank->io_sel) & mask) | |
252 | return GPIOF_INPUT; | |
253 | else | |
254 | return GPIOF_OUTPUT; | |
255 | } | |
256 | ||
257 | static const struct dm_gpio_ops gpio_ich6_ops = { | |
258 | .request = ich6_gpio_request, | |
259 | .direction_input = ich6_gpio_direction_input, | |
260 | .direction_output = ich6_gpio_direction_output, | |
261 | .get_value = ich6_gpio_get_value, | |
262 | .set_value = ich6_gpio_set_value, | |
263 | .get_function = ich6_gpio_get_function, | |
264 | }; | |
265 | ||
266 | static const struct udevice_id intel_ich6_gpio_ids[] = { | |
267 | { .compatible = "intel,ich6-gpio" }, | |
268 | { } | |
269 | }; | |
270 | ||
271 | U_BOOT_DRIVER(gpio_ich6) = { | |
272 | .name = "gpio_ich6", | |
273 | .id = UCLASS_GPIO, | |
274 | .of_match = intel_ich6_gpio_ids, | |
275 | .ops = &gpio_ich6_ops, | |
276 | .ofdata_to_platdata = gpio_ich6_ofdata_to_platdata, | |
277 | .probe = ich6_gpio_probe, | |
278 | .priv_auto_alloc_size = sizeof(struct ich6_bank_priv), | |
279 | .platdata_auto_alloc_size = sizeof(struct ich6_bank_platdata), | |
280 | }; |