[people/ms/u-boot.git] / drivers / gpio / mxs_gpio.c

/*
 * Freescale i.MX28 GPIO control code
 *
 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
 * on behalf of DENX Software Engineering GmbH
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <netdev.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>

#if	defined(CONFIG_MX23)
#define	PINCTRL_BANKS		3
#define	PINCTRL_DOUT(n)		(0x0500 + ((n) * 0x10))
#define	PINCTRL_DIN(n)		(0x0600 + ((n) * 0x10))
#define	PINCTRL_DOE(n)		(0x0700 + ((n) * 0x10))
#define	PINCTRL_PIN2IRQ(n)	(0x0800 + ((n) * 0x10))
#define	PINCTRL_IRQEN(n)	(0x0900 + ((n) * 0x10))
#define	PINCTRL_IRQSTAT(n)	(0x0c00 + ((n) * 0x10))
#elif	defined(CONFIG_MX28)
#define	PINCTRL_BANKS		5
#define	PINCTRL_DOUT(n)		(0x0700 + ((n) * 0x10))
#define	PINCTRL_DIN(n)		(0x0900 + ((n) * 0x10))
#define	PINCTRL_DOE(n)		(0x0b00 + ((n) * 0x10))
#define	PINCTRL_PIN2IRQ(n)	(0x1000 + ((n) * 0x10))
#define	PINCTRL_IRQEN(n)	(0x1100 + ((n) * 0x10))
#define	PINCTRL_IRQSTAT(n)	(0x1400 + ((n) * 0x10))
#else
#error "Please select CONFIG_MX23 or CONFIG_MX28"
#endif

#define GPIO_INT_FALL_EDGE	0x0
#define GPIO_INT_LOW_LEV	0x1
#define GPIO_INT_RISE_EDGE	0x2
#define GPIO_INT_HIGH_LEV	0x3
#define GPIO_INT_LEV_MASK	(1 << 0)
#define GPIO_INT_POL_MASK	(1 << 1)

void mxs_gpio_init(void)
{
	int i;

	for (i = 0; i < PINCTRL_BANKS; i++) {
		writel(0, MXS_PINCTRL_BASE + PINCTRL_PIN2IRQ(i));
		writel(0, MXS_PINCTRL_BASE + PINCTRL_IRQEN(i));
		/* Use SCT address here to clear the IRQSTAT bits */
		writel(0xffffffff, MXS_PINCTRL_BASE + PINCTRL_IRQSTAT(i) + 8);
	}
}

int gpio_get_value(unsigned gpio)
{
	uint32_t bank = PAD_BANK(gpio);
	uint32_t offset = PINCTRL_DIN(bank);
	struct mxs_register_32 *reg =
		(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);

	return (readl(&reg->reg) >> PAD_PIN(gpio)) & 1;
}

void gpio_set_value(unsigned gpio, int value)
{
	uint32_t bank = PAD_BANK(gpio);
	uint32_t offset = PINCTRL_DOUT(bank);
	struct mxs_register_32 *reg =
		(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);

	if (value)
		writel(1 << PAD_PIN(gpio), &reg->reg_set);
	else
		writel(1 << PAD_PIN(gpio), &reg->reg_clr);
}

int gpio_direction_input(unsigned gpio)
{
	uint32_t bank = PAD_BANK(gpio);
	uint32_t offset = PINCTRL_DOE(bank);
	struct mxs_register_32 *reg =
		(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);

	writel(1 << PAD_PIN(gpio), &reg->reg_clr);

	return 0;
}

int gpio_direction_output(unsigned gpio, int value)
{
	uint32_t bank = PAD_BANK(gpio);
	uint32_t offset = PINCTRL_DOE(bank);
	struct mxs_register_32 *reg =
		(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);

	gpio_set_value(gpio, value);

	writel(1 << PAD_PIN(gpio), &reg->reg_set);

	return 0;
}

int gpio_request(unsigned gpio, const char *label)
{
	if (PAD_BANK(gpio) >= PINCTRL_BANKS)
		return -1;

	return 0;
}

int gpio_free(unsigned gpio)
{
	return 0;
}
Commit	Line	Data
6b6440de MV	1	/*
	2	* Freescale i.MX28 GPIO control code
	3	*
	4	* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
	5	* on behalf of DENX Software Engineering GmbH
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
6b6440de MV	8	*/
	9
	10	#include <common.h>
	11	#include <netdev.h>
	12	#include <asm/errno.h>
	13	#include <asm/io.h>
	14	#include <asm/arch/iomux.h>
	15	#include <asm/arch/imx-regs.h>
	16
	17	#if defined(CONFIG_MX23)
	18	#define PINCTRL_BANKS 3
	19	#define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10))
	20	#define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10))
	21	#define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10))
	22	#define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10))
	23	#define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10))
	24	#define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10))
	25	#elif defined(CONFIG_MX28)
	26	#define PINCTRL_BANKS 5
	27	#define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10))
	28	#define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10))
	29	#define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10))
	30	#define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10))
	31	#define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10))
	32	#define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10))
	33	#else
	34	#error "Please select CONFIG_MX23 or CONFIG_MX28"
	35	#endif
	36
	37	#define GPIO_INT_FALL_EDGE 0x0
	38	#define GPIO_INT_LOW_LEV 0x1
	39	#define GPIO_INT_RISE_EDGE 0x2
	40	#define GPIO_INT_HIGH_LEV 0x3
	41	#define GPIO_INT_LEV_MASK (1 << 0)
	42	#define GPIO_INT_POL_MASK (1 << 1)
	43
	44	void mxs_gpio_init(void)
	45	{
	46	int i;
	47
	48	for (i = 0; i < PINCTRL_BANKS; i++) {
	49	writel(0, MXS_PINCTRL_BASE + PINCTRL_PIN2IRQ(i));
	50	writel(0, MXS_PINCTRL_BASE + PINCTRL_IRQEN(i));
	51	/* Use SCT address here to clear the IRQSTAT bits */
	52	writel(0xffffffff, MXS_PINCTRL_BASE + PINCTRL_IRQSTAT(i) + 8);
	53	}
	54	}
	55
365d6070	56	int gpio_get_value(unsigned gpio)
6b6440de	57	{
365d6070	58	uint32_t bank = PAD_BANK(gpio);
6b6440de	59	uint32_t offset = PINCTRL_DIN(bank);
ddcf13b1 OS	60	struct mxs_register_32 *reg =
ddcf13b1 OS	61	(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
6b6440de	62
365d6070	63	return (readl(&reg->reg) >> PAD_PIN(gpio)) & 1;
6b6440de MV	64	}
6b6440de MV	65
365d6070	66	void gpio_set_value(unsigned gpio, int value)
6b6440de	67	{
365d6070	68	uint32_t bank = PAD_BANK(gpio);
6b6440de	69	uint32_t offset = PINCTRL_DOUT(bank);
ddcf13b1 OS	70	struct mxs_register_32 *reg =
ddcf13b1 OS	71	(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
6b6440de MV	72
6b6440de MV	73	if (value)
365d6070	74	writel(1 << PAD_PIN(gpio), &reg->reg_set);
6b6440de	75	else
365d6070	76	writel(1 << PAD_PIN(gpio), &reg->reg_clr);
6b6440de MV	77	}
6b6440de MV	78
365d6070	79	int gpio_direction_input(unsigned gpio)
6b6440de	80	{
365d6070	81	uint32_t bank = PAD_BANK(gpio);
6b6440de	82	uint32_t offset = PINCTRL_DOE(bank);
ddcf13b1 OS	83	struct mxs_register_32 *reg =
ddcf13b1 OS	84	(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
6b6440de	85
365d6070	86	writel(1 << PAD_PIN(gpio), &reg->reg_clr);
6b6440de MV	87
	88	return 0;
	89	}
	90
365d6070	91	int gpio_direction_output(unsigned gpio, int value)
6b6440de	92	{
365d6070	93	uint32_t bank = PAD_BANK(gpio);
6b6440de	94	uint32_t offset = PINCTRL_DOE(bank);
ddcf13b1 OS	95	struct mxs_register_32 *reg =
ddcf13b1 OS	96	(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
6b6440de	97
365d6070	98	gpio_set_value(gpio, value);
6b6440de	99
ac135f66 MH	100	writel(1 << PAD_PIN(gpio), &reg->reg_set);
ac135f66 MH	101
6b6440de MV	102	return 0;
	103	}
	104
365d6070	105	int gpio_request(unsigned gpio, const char *label)
6b6440de	106	{
365d6070 JH	107	if (PAD_BANK(gpio) >= PINCTRL_BANKS)
365d6070 JH	108	return -1;
6b6440de MV	109
	110	return 0;
	111	}
	112
365d6070	113	int gpio_free(unsigned gpio)
6b6440de	114	{
365d6070	115	return 0;
6b6440de	116	}