[people/ms/u-boot.git] / drivers / gpio / tegra_gpio.c

/*
 * NVIDIA Tegra20 GPIO handling.
 *  (C) Copyright 2010-2012
 *  NVIDIA Corporation <www.nvidia.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
 * Tom Warren (twarren@nvidia.com)
 */

#include <common.h>
#include <dm.h>
#include <malloc.h>
#include <errno.h>
#include <fdtdec.h>
#include <asm/io.h>
#include <asm/bitops.h>
#include <asm/arch/tegra.h>
#include <asm/gpio.h>
#include <dm/device-internal.h>
#include <dt-bindings/gpio/gpio.h>

DECLARE_GLOBAL_DATA_PTR;

enum {
	TEGRA_CMD_INFO,
	TEGRA_CMD_PORT,
	TEGRA_CMD_OUTPUT,
	TEGRA_CMD_INPUT,
};

struct tegra_gpio_platdata {
	struct gpio_ctlr_bank *bank;
	const char *port_name;	/* Name of port, e.g. "B" */
	int base_gpio;		/* Port number for this port (0, 1,.., n-1) */
};

/* Information about each port at run-time */
struct tegra_port_info {
	struct gpio_ctlr_bank *bank;
	int base_gpio;		/* Port number for this port (0, 1,.., n-1) */
};

/* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */
static int get_config(unsigned gpio)
{
	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
	u32 u;
	int type;

	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
	type =  (u >> GPIO_BIT(gpio)) & 1;

	debug("get_config: port = %d, bit = %d is %s\n",
		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");

	return type;
}

/* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */
static void set_config(unsigned gpio, int type)
{
	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
	u32 u;

	debug("set_config: port = %d, bit = %d, %s\n",
		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");

	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
	if (type)				/* GPIO */
		u |= 1 << GPIO_BIT(gpio);
	else
		u &= ~(1 << GPIO_BIT(gpio));
	writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
}

/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
static int get_direction(unsigned gpio)
{
	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
	u32 u;
	int dir;

	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
	dir =  (u >> GPIO_BIT(gpio)) & 1;

	debug("get_direction: port = %d, bit = %d, %s\n",
		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");

	return dir;
}

/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
static void set_direction(unsigned gpio, int output)
{
	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
	u32 u;

	debug("set_direction: port = %d, bit = %d, %s\n",
		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");

	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
	if (output)
		u |= 1 << GPIO_BIT(gpio);
	else
		u &= ~(1 << GPIO_BIT(gpio));
	writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
}

/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
static void set_level(unsigned gpio, int high)
{
	struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
	u32 u;

	debug("set_level: port = %d, bit %d == %d\n",
		GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);

	u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
	if (high)
		u |= 1 << GPIO_BIT(gpio);
	else
		u &= ~(1 << GPIO_BIT(gpio));
	writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
}

/*
 * Generic_GPIO primitives.
 */

static int tegra_gpio_request(struct udevice *dev, unsigned offset,
			      const char *label)
{
	struct tegra_port_info *state = dev_get_priv(dev);

	/* Configure as a GPIO */
	set_config(state->base_gpio + offset, 1);

	return 0;
}

/* set GPIO pin 'gpio' as an input */
static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
{
	struct tegra_port_info *state = dev_get_priv(dev);

	/* Configure GPIO direction as input. */
	set_direction(state->base_gpio + offset, 0);

	return 0;
}

/* set GPIO pin 'gpio' as an output, with polarity 'value' */
static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
				       int value)
{
	struct tegra_port_info *state = dev_get_priv(dev);
	int gpio = state->base_gpio + offset;

	/* Configure GPIO output value. */
	set_level(gpio, value);

	/* Configure GPIO direction as output. */
	set_direction(gpio, 1);

	return 0;
}

/* read GPIO IN value of pin 'gpio' */
static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
{
	struct tegra_port_info *state = dev_get_priv(dev);
	int gpio = state->base_gpio + offset;
	int val;

	debug("%s: pin = %d (port %d:bit %d)\n", __func__,
	      gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));

	val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);

	return (val >> GPIO_BIT(gpio)) & 1;
}

/* write GPIO OUT value to pin 'gpio' */
static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
{
	struct tegra_port_info *state = dev_get_priv(dev);
	int gpio = state->base_gpio + offset;

	debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
	      gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);

	/* Configure GPIO output value. */
	set_level(gpio, value);

	return 0;
}

void gpio_config_table(const struct tegra_gpio_config *config, int len)
{
	int i;

	for (i = 0; i < len; i++) {
		switch (config[i].init) {
		case TEGRA_GPIO_INIT_IN:
			gpio_direction_input(config[i].gpio);
			break;
		case TEGRA_GPIO_INIT_OUT0:
			gpio_direction_output(config[i].gpio, 0);
			break;
		case TEGRA_GPIO_INIT_OUT1:
			gpio_direction_output(config[i].gpio, 1);
			break;
		}
		set_config(config[i].gpio, 1);
	}
}

static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
{
	struct tegra_port_info *state = dev_get_priv(dev);
	int gpio = state->base_gpio + offset;

	if (!get_config(gpio))
		return GPIOF_FUNC;
	else if (get_direction(gpio))
		return GPIOF_OUTPUT;
	else
		return GPIOF_INPUT;
}

static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
			    struct fdtdec_phandle_args *args)
{
	int gpio, port, ret;

	gpio = args->args[0];
	port = gpio / TEGRA_GPIOS_PER_PORT;
	ret = device_get_child(dev, port, &desc->dev);
	if (ret)
		return ret;
	desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;

	return 0;
}

static const struct dm_gpio_ops gpio_tegra_ops = {
	.request		= tegra_gpio_request,
	.direction_input	= tegra_gpio_direction_input,
	.direction_output	= tegra_gpio_direction_output,
	.get_value		= tegra_gpio_get_value,
	.set_value		= tegra_gpio_set_value,
	.get_function		= tegra_gpio_get_function,
	.xlate			= tegra_gpio_xlate,
};

/**
 * Returns the name of a GPIO port
 *
 * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
 *
 * @base_port: Base port number (0, 1..n-1)
 * @return allocated string containing the name
 */
static char *gpio_port_name(int base_port)
{
	char *name, *s;

	name = malloc(3);
	if (name) {
		s = name;
		*s++ = 'A' + (base_port % 26);
		if (base_port >= 26)
			*s++ = *name;
		*s = '\0';
	}

	return name;
}

static const struct udevice_id tegra_gpio_ids[] = {
	{ .compatible = "nvidia,tegra30-gpio" },
	{ .compatible = "nvidia,tegra20-gpio" },
	{ }
};

static int gpio_tegra_probe(struct udevice *dev)
{
	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
	struct tegra_port_info *priv = dev->priv;
	struct tegra_gpio_platdata *plat = dev->platdata;

	/* Only child devices have ports */
	if (!plat)
		return 0;

	priv->bank = plat->bank;
	priv->base_gpio = plat->base_gpio;

	uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
	uc_priv->bank_name = plat->port_name;

	return 0;
}

/**
 * We have a top-level GPIO device with no actual GPIOs. It has a child
 * device for each Tegra port.
 */
static int gpio_tegra_bind(struct udevice *parent)
{
	struct tegra_gpio_platdata *plat = parent->platdata;
	struct gpio_ctlr *ctlr;
	int bank_count;
	int bank;
	int ret;

	/* If this is a child device, there is nothing to do here */
	if (plat)
		return 0;

	/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
#ifdef CONFIG_SPL_BUILD
	ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
	bank_count = TEGRA_GPIO_BANKS;
#else
	{
	int len;

	/*
	 * This driver does not make use of interrupts, other than to figure
	 * out the number of GPIO banks
	 */
	if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len))
		return -EINVAL;
	bank_count = len / 3 / sizeof(u32);
	ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob,
						   parent->of_offset, "reg");
	}
#endif
	for (bank = 0; bank < bank_count; bank++) {
		int port;

		for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
			struct tegra_gpio_platdata *plat;
			struct udevice *dev;
			int base_port;

			plat = calloc(1, sizeof(*plat));
			if (!plat)
				return -ENOMEM;
			plat->bank = &ctlr->gpio_bank[bank];
			base_port = bank * TEGRA_PORTS_PER_BANK + port;
			plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
			plat->port_name = gpio_port_name(base_port);

			ret = device_bind(parent, parent->driver,
					  plat->port_name, plat, -1, &dev);
			if (ret)
				return ret;
			dev->of_offset = parent->of_offset;
		}
	}

	return 0;
}

U_BOOT_DRIVER(gpio_tegra) = {
	.name	= "gpio_tegra",
	.id	= UCLASS_GPIO,
	.of_match = tegra_gpio_ids,
	.bind	= gpio_tegra_bind,
	.probe = gpio_tegra_probe,
	.priv_auto_alloc_size = sizeof(struct tegra_port_info),
	.ops	= &gpio_tegra_ops,
	.flags	= DM_FLAG_PRE_RELOC,
};
Commit	Line	Data
4e5ae09e	1	/*
00a2749d	2	* NVIDIA Tegra20 GPIO handling.
52a8b820	3	* (C) Copyright 2010-2012
4e5ae09e TW	4	* NVIDIA Corporation <www.nvidia.com>
4e5ae09e TW	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
4e5ae09e TW	7	*/
	8
	9	/*
	10	* Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
	11	* Tom Warren (twarren@nvidia.com)
	12	*/
	13
	14	#include <common.h>
2fccd2d9 SG	15	#include <dm.h>
	16	#include <malloc.h>
	17	#include <errno.h>
	18	#include <fdtdec.h>
4e5ae09e TW	19	#include <asm/io.h>
4e5ae09e TW	20	#include <asm/bitops.h>
150c2493	21	#include <asm/arch/tegra.h>
4e5ae09e	22	#include <asm/gpio.h>
2fccd2d9	23	#include <dm/device-internal.h>
838aa5c9	24	#include <dt-bindings/gpio/gpio.h>
2fccd2d9 SG	25
2fccd2d9 SG	26	DECLARE_GLOBAL_DATA_PTR;
4e5ae09e TW	27
4e5ae09e TW	28	enum {
29f3e3f2 TW	29	TEGRA_CMD_INFO,
	30	TEGRA_CMD_PORT,
	31	TEGRA_CMD_OUTPUT,
	32	TEGRA_CMD_INPUT,
4e5ae09e TW	33	};
4e5ae09e TW	34
2fccd2d9 SG	35	struct tegra_gpio_platdata {
	36	struct gpio_ctlr_bank *bank;
	37	const char port_name; / Name of port, e.g. "B" */
	38	int base_gpio; /* Port number for this port (0, 1,.., n-1) */
	39	};
4e5ae09e	40
2fccd2d9 SG	41	/* Information about each port at run-time */
2fccd2d9 SG	42	struct tegra_port_info {
2fccd2d9 SG	43	struct gpio_ctlr_bank *bank;
	44	int base_gpio; /* Port number for this port (0, 1,.., n-1) */
	45	};
4e5ae09e	46
365d6070 JH	47	/* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */
365d6070 JH	48	static int get_config(unsigned gpio)
4e5ae09e	49	{
365d6070 JH	50	struct gpio_ctlr ctlr = (struct gpio_ctlr )NV_PA_GPIO_BASE;
365d6070 JH	51	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
4e5ae09e TW	52	u32 u;
	53	int type;
	54
365d6070 JH	55	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
365d6070 JH	56	type = (u >> GPIO_BIT(gpio)) & 1;
4e5ae09e TW	57
4e5ae09e TW	58	debug("get_config: port = %d, bit = %d is %s\n",
365d6070	59	GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
4e5ae09e TW	60
	61	return type;
	62	}
	63
365d6070 JH	64	/* Config pin 'gpio' as GPIO or SFPIO, based on 'type' */
365d6070 JH	65	static void set_config(unsigned gpio, int type)
4e5ae09e	66	{
365d6070 JH	67	struct gpio_ctlr ctlr = (struct gpio_ctlr )NV_PA_GPIO_BASE;
365d6070 JH	68	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
4e5ae09e TW	69	u32 u;
	70
	71	debug("set_config: port = %d, bit = %d, %s\n",
365d6070	72	GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
4e5ae09e	73
365d6070	74	u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
4e5ae09e	75	if (type) /* GPIO */
365d6070	76	u \|= 1 << GPIO_BIT(gpio);
4e5ae09e	77	else
365d6070 JH	78	u &= ~(1 << GPIO_BIT(gpio));
365d6070 JH	79	writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
4e5ae09e TW	80	}
4e5ae09e TW	81
365d6070 JH	82	/* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
365d6070 JH	83	static int get_direction(unsigned gpio)
4e5ae09e	84	{
365d6070 JH	85	struct gpio_ctlr ctlr = (struct gpio_ctlr )NV_PA_GPIO_BASE;
365d6070 JH	86	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
4e5ae09e TW	87	u32 u;
	88	int dir;
	89
365d6070 JH	90	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
365d6070 JH	91	dir = (u >> GPIO_BIT(gpio)) & 1;
4e5ae09e TW	92
4e5ae09e TW	93	debug("get_direction: port = %d, bit = %d, %s\n",
365d6070	94	GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
4e5ae09e TW	95
	96	return dir;
	97	}
	98
365d6070 JH	99	/* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
365d6070 JH	100	static void set_direction(unsigned gpio, int output)
4e5ae09e	101	{
365d6070 JH	102	struct gpio_ctlr ctlr = (struct gpio_ctlr )NV_PA_GPIO_BASE;
365d6070 JH	103	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
4e5ae09e TW	104	u32 u;
	105
	106	debug("set_direction: port = %d, bit = %d, %s\n",
365d6070	107	GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
4e5ae09e	108
365d6070	109	u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
4e5ae09e	110	if (output)
365d6070	111	u \|= 1 << GPIO_BIT(gpio);
4e5ae09e	112	else
365d6070 JH	113	u &= ~(1 << GPIO_BIT(gpio));
365d6070 JH	114	writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
4e5ae09e TW	115	}
4e5ae09e TW	116
365d6070 JH	117	/* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
365d6070 JH	118	static void set_level(unsigned gpio, int high)
4e5ae09e	119	{
365d6070 JH	120	struct gpio_ctlr ctlr = (struct gpio_ctlr )NV_PA_GPIO_BASE;
365d6070 JH	121	struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
4e5ae09e TW	122	u32 u;
	123
	124	debug("set_level: port = %d, bit %d == %d\n",
365d6070	125	GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
4e5ae09e	126
365d6070	127	u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
4e5ae09e	128	if (high)
365d6070	129	u \|= 1 << GPIO_BIT(gpio);
4e5ae09e	130	else
365d6070 JH	131	u &= ~(1 << GPIO_BIT(gpio));
365d6070 JH	132	writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
4e5ae09e TW	133	}
	134
	135	/*
	136	* Generic_GPIO primitives.
	137	*/
	138
2fccd2d9 SG	139	static int tegra_gpio_request(struct udevice *dev, unsigned offset,
2fccd2d9 SG	140	const char *label)
4e5ae09e	141	{
2fccd2d9	142	struct tegra_port_info *state = dev_get_priv(dev);
4e5ae09e	143
4e5ae09e	144	/* Configure as a GPIO */
2fccd2d9	145	set_config(state->base_gpio + offset, 1);
4e5ae09e TW	146
	147	return 0;
	148	}
	149
365d6070	150	/* set GPIO pin 'gpio' as an input */
2fccd2d9	151	static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
4e5ae09e	152	{
2fccd2d9	153	struct tegra_port_info *state = dev_get_priv(dev);
4e5ae09e TW	154
4e5ae09e TW	155	/* Configure GPIO direction as input. */
2fccd2d9	156	set_direction(state->base_gpio + offset, 0);
4e5ae09e TW	157
	158	return 0;
	159	}
	160
365d6070	161	/* set GPIO pin 'gpio' as an output, with polarity 'value' */
2fccd2d9 SG	162	static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
2fccd2d9 SG	163	int value)
4e5ae09e	164	{
2fccd2d9 SG	165	struct tegra_port_info *state = dev_get_priv(dev);
2fccd2d9 SG	166	int gpio = state->base_gpio + offset;
4e5ae09e TW	167
4e5ae09e TW	168	/* Configure GPIO output value. */
365d6070	169	set_level(gpio, value);
4e5ae09e TW	170
4e5ae09e TW	171	/* Configure GPIO direction as output. */
365d6070	172	set_direction(gpio, 1);
4e5ae09e TW	173
	174	return 0;
	175	}
	176
365d6070	177	/* read GPIO IN value of pin 'gpio' */
2fccd2d9	178	static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
4e5ae09e	179	{
2fccd2d9 SG	180	struct tegra_port_info *state = dev_get_priv(dev);
2fccd2d9 SG	181	int gpio = state->base_gpio + offset;
4e5ae09e TW	182	int val;
4e5ae09e TW	183
2fccd2d9 SG	184	debug("%s: pin = %d (port %d:bit %d)\n", __func__,
2fccd2d9 SG	185	gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
4e5ae09e	186
2fccd2d9	187	val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
4e5ae09e	188
365d6070	189	return (val >> GPIO_BIT(gpio)) & 1;
4e5ae09e TW	190	}
4e5ae09e TW	191
365d6070	192	/* write GPIO OUT value to pin 'gpio' */
2fccd2d9	193	static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
4e5ae09e	194	{
2fccd2d9 SG	195	struct tegra_port_info *state = dev_get_priv(dev);
2fccd2d9 SG	196	int gpio = state->base_gpio + offset;
2fccd2d9	197
4e5ae09e	198	debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
2fccd2d9	199	gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
4e5ae09e TW	200
4e5ae09e TW	201	/* Configure GPIO output value. */
365d6070 JH	202	set_level(gpio, value);
	203
	204	return 0;
4e5ae09e TW	205	}
4e5ae09e TW	206
eceb3f26 SW	207	void gpio_config_table(const struct tegra_gpio_config *config, int len)
	208	{
	209	int i;
	210
	211	for (i = 0; i < len; i++) {
	212	switch (config[i].init) {
	213	case TEGRA_GPIO_INIT_IN:
	214	gpio_direction_input(config[i].gpio);
	215	break;
	216	case TEGRA_GPIO_INIT_OUT0:
	217	gpio_direction_output(config[i].gpio, 0);
	218	break;
	219	case TEGRA_GPIO_INIT_OUT1:
	220	gpio_direction_output(config[i].gpio, 1);
	221	break;
	222	}
	223	set_config(config[i].gpio, 1);
	224	}
	225	}
	226
2fccd2d9 SG	227	static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
	228	{
	229	struct tegra_port_info *state = dev_get_priv(dev);
	230	int gpio = state->base_gpio + offset;
	231
2fccd2d9 SG	232	if (!get_config(gpio))
	233	return GPIOF_FUNC;
	234	else if (get_direction(gpio))
	235	return GPIOF_OUTPUT;
	236	else
	237	return GPIOF_INPUT;
	238	}
	239
838aa5c9 SG	240	static int tegra_gpio_xlate(struct udevice dev, struct gpio_desc desc,
	241	struct fdtdec_phandle_args *args)
	242	{
	243	int gpio, port, ret;
	244
	245	gpio = args->args[0];
	246	port = gpio / TEGRA_GPIOS_PER_PORT;
	247	ret = device_get_child(dev, port, &desc->dev);
	248	if (ret)
	249	return ret;
	250	desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
	251	desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
	252
	253	return 0;
	254	}
	255
2fccd2d9 SG	256	static const struct dm_gpio_ops gpio_tegra_ops = {
2fccd2d9 SG	257	.request = tegra_gpio_request,
2fccd2d9 SG	258	.direction_input = tegra_gpio_direction_input,
	259	.direction_output = tegra_gpio_direction_output,
	260	.get_value = tegra_gpio_get_value,
	261	.set_value = tegra_gpio_set_value,
	262	.get_function = tegra_gpio_get_function,
838aa5c9	263	.xlate = tegra_gpio_xlate,
2fccd2d9 SG	264	};
	265
	266	/**
	267	* Returns the name of a GPIO port
	268	*
	269	* GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
	270	*
	271	* @base_port: Base port number (0, 1..n-1)
	272	* @return allocated string containing the name
4e5ae09e	273	*/
2fccd2d9	274	static char *gpio_port_name(int base_port)
4e5ae09e	275	{
2fccd2d9 SG	276	char name, s;
	277
	278	name = malloc(3);
	279	if (name) {
	280	s = name;
	281	*s++ = 'A' + (base_port % 26);
	282	if (base_port >= 26)
	283	s++ = name;
	284	*s = '\0';
	285	}
4e5ae09e	286
2fccd2d9 SG	287	return name;
	288	}
	289
	290	static const struct udevice_id tegra_gpio_ids[] = {
	291	{ .compatible = "nvidia,tegra30-gpio" },
	292	{ .compatible = "nvidia,tegra20-gpio" },
	293	{ }
	294	};
	295
	296	static int gpio_tegra_probe(struct udevice *dev)
	297	{
	298	struct gpio_dev_priv *uc_priv = dev->uclass_priv;
	299	struct tegra_port_info *priv = dev->priv;
	300	struct tegra_gpio_platdata *plat = dev->platdata;
	301
	302	/* Only child devices have ports */
	303	if (!plat)
	304	return 0;
	305
	306	priv->bank = plat->bank;
	307	priv->base_gpio = plat->base_gpio;
	308
	309	uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
	310	uc_priv->bank_name = plat->port_name;
	311
	312	return 0;
	313	}
	314
	315	/**
	316	* We have a top-level GPIO device with no actual GPIOs. It has a child
	317	* device for each Tegra port.
	318	*/
	319	static int gpio_tegra_bind(struct udevice *parent)
	320	{
	321	struct tegra_gpio_platdata *plat = parent->platdata;
	322	struct gpio_ctlr *ctlr;
	323	int bank_count;
	324	int bank;
	325	int ret;
2fccd2d9 SG	326
	327	/* If this is a child device, there is nothing to do here */
	328	if (plat)
	329	return 0;
	330
bdfb3416 SG	331	/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
	332	#ifdef CONFIG_SPL_BUILD
	333	ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
	334	bank_count = TEGRA_GPIO_BANKS;
	335	#else
	336	{
	337	int len;
	338
2fccd2d9 SG	339	/*
	340	* This driver does not make use of interrupts, other than to figure
	341	* out the number of GPIO banks
	342	*/
	343	if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len))
	344	return -EINVAL;
	345	bank_count = len / 3 / sizeof(u32);
	346	ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob,
	347	parent->of_offset, "reg");
bdfb3416 SG	348	}
bdfb3416 SG	349	#endif
2fccd2d9 SG	350	for (bank = 0; bank < bank_count; bank++) {
	351	int port;
	352
	353	for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
	354	struct tegra_gpio_platdata *plat;
	355	struct udevice *dev;
	356	int base_port;
	357
	358	plat = calloc(1, sizeof(*plat));
	359	if (!plat)
	360	return -ENOMEM;
	361	plat->bank = &ctlr->gpio_bank[bank];
	362	base_port = bank * TEGRA_PORTS_PER_BANK + port;
	363	plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
	364	plat->port_name = gpio_port_name(base_port);
	365
	366	ret = device_bind(parent, parent->driver,
	367	plat->port_name, plat, -1, &dev);
	368	if (ret)
	369	return ret;
	370	dev->of_offset = parent->of_offset;
	371	}
4e5ae09e	372	}
2fccd2d9 SG	373
2fccd2d9 SG	374	return 0;
4e5ae09e	375	}
2fccd2d9 SG	376
	377	U_BOOT_DRIVER(gpio_tegra) = {
	378	.name = "gpio_tegra",
	379	.id = UCLASS_GPIO,
	380	.of_match = tegra_gpio_ids,
	381	.bind = gpio_tegra_bind,
	382	.probe = gpio_tegra_probe,
	383	.priv_auto_alloc_size = sizeof(struct tegra_port_info),
	384	.ops = &gpio_tegra_ops,
bdfb3416	385	.flags = DM_FLAG_PRE_RELOC,
2fccd2d9	386	};