[thirdparty/u-boot.git] / drivers / gpio / xilinx_gpio.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2013 - 2018 Xilinx, Michal Simek
 */

#include <common.h>
#include <errno.h>
#include <malloc.h>
#include <linux/list.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <dm.h>
#include <dt-bindings/gpio/gpio.h>

#define XILINX_GPIO_MAX_BANK	2

/* Gpio simple map */
struct gpio_regs {
	u32 gpiodata;
	u32 gpiodir;
};

struct xilinx_gpio_platdata {
	struct gpio_regs *regs;
	int bank_max[XILINX_GPIO_MAX_BANK];
	int bank_input[XILINX_GPIO_MAX_BANK];
	int bank_output[XILINX_GPIO_MAX_BANK];
	u32 dout_default[XILINX_GPIO_MAX_BANK];
};

struct xilinx_gpio_privdata {
	u32 output_val[XILINX_GPIO_MAX_BANK];
};

static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
				    u32 *bank_pin_num, struct udevice *dev)
{
	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
	u32 bank, max_pins;
	/* the first gpio is 0 not 1 */
	u32 pin_num = offset;

	for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) {
		max_pins = platdata->bank_max[bank];
		if (pin_num < max_pins) {
			debug("%s: found at bank 0x%x pin 0x%x\n", __func__,
			      bank, pin_num);
			*bank_num = bank;
			*bank_pin_num = pin_num;
			return 0;
		}
		pin_num -= max_pins;
	}

	return -EINVAL;
}

static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
				 int value)
{
	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
	int val, ret;
	u32 bank, pin;

	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	if (ret)
		return ret;

	val = priv->output_val[bank];

	debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
	      __func__, (ulong)platdata->regs, value, offset, bank, pin, val);

	if (value)
		val = val | (1 << pin);
	else
		val = val & ~(1 << pin);

	writel(val, &platdata->regs->gpiodata + bank * 2);

	priv->output_val[bank] = val;

	return 0;
};

static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
{
	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
	int val, ret;
	u32 bank, pin;

	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	if (ret)
		return ret;

	debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
	      (ulong)platdata->regs, offset, bank, pin);

	if (platdata->bank_output[bank]) {
		debug("%s: Read saved output value\n", __func__);
		val = priv->output_val[bank];
	} else {
		debug("%s: Read input value from reg\n", __func__);
		val = readl(&platdata->regs->gpiodata + bank * 2);
	}

	val = !!(val & (1 << pin));

	return val;
};

static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
{
	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
	int val, ret;
	u32 bank, pin;

	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	if (ret)
		return ret;

	/* Check if all pins are inputs */
	if (platdata->bank_input[bank])
		return GPIOF_INPUT;

	/* Check if all pins are outputs */
	if (platdata->bank_output[bank])
		return GPIOF_OUTPUT;

	/* FIXME test on dual */
	val = readl(&platdata->regs->gpiodir + bank * 2);
	val = !(val & (1 << pin));

	/* input is 1 in reg but GPIOF_INPUT is 0 */
	/* output is 0 in reg but GPIOF_OUTPUT is 1 */

	return val;
}

static int xilinx_gpio_direction_output(struct udevice *dev, unsigned offset,
					int value)
{
	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
	int val, ret;
	u32 bank, pin;

	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	if (ret)
		return ret;

	/* can't change it if all is input by default */
	if (platdata->bank_input[bank])
		return -EINVAL;

	xilinx_gpio_set_value(dev, offset, value);

	if (!platdata->bank_output[bank]) {
		val = readl(&platdata->regs->gpiodir + bank * 2);
		val = val & ~(1 << pin);
		writel(val, &platdata->regs->gpiodir + bank * 2);
	}

	return 0;
}

static int xilinx_gpio_direction_input(struct udevice *dev, unsigned offset)
{
	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
	int val, ret;
	u32 bank, pin;

	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	if (ret)
		return ret;

	/* Already input */
	if (platdata->bank_input[bank])
		return 0;

	/* can't change it if all is output by default */
	if (platdata->bank_output[bank])
		return -EINVAL;

	val = readl(&platdata->regs->gpiodir + bank * 2);
	val = val | (1 << pin);
	writel(val, &platdata->regs->gpiodir + bank * 2);

	return 0;
}

static int xilinx_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
			     struct ofnode_phandle_args *args)
{
	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);

	desc->offset = args->args[0];

	debug("%s: argc: %x, [0]: %x, [1]: %x, [2]: %x\n", __func__,
	      args->args_count, args->args[0], args->args[1], args->args[2]);

	/*
	 * The second cell is channel offset:
	 *  0 is first channel, 8 is second channel
	 *
	 * U-Boot driver just combine channels together that's why simply
	 * add amount of pins in second channel if present.
	 */
	if (args->args[1]) {
		if (!platdata->bank_max[1]) {
			printf("%s: %s has no second channel\n",
			       __func__, dev->name);
			return -EINVAL;
		}

		desc->offset += platdata->bank_max[0];
	}

	/* The third cell is optional */
	if (args->args_count > 2)
		desc->flags = (args->args[2] &
			       GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);

	debug("%s: offset %x, flags %lx\n",
	      __func__, desc->offset, desc->flags);
	return 0;
}

static const struct dm_gpio_ops xilinx_gpio_ops = {
	.direction_input = xilinx_gpio_direction_input,
	.direction_output = xilinx_gpio_direction_output,
	.get_value = xilinx_gpio_get_value,
	.set_value = xilinx_gpio_set_value,
	.get_function = xilinx_gpio_get_function,
	.xlate = xilinx_gpio_xlate,
};

static int xilinx_gpio_probe(struct udevice *dev)
{
	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	const void *label_ptr;

	label_ptr = dev_read_prop(dev, "label", NULL);
	if (label_ptr) {
		uc_priv->bank_name = strdup(label_ptr);
		if (!uc_priv->bank_name)
			return -ENOMEM;
	} else {
		uc_priv->bank_name = dev->name;
	}

	uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1];

	priv->output_val[0] = platdata->dout_default[0];

	if (platdata->bank_max[1])
		priv->output_val[1] = platdata->dout_default[1];

	return 0;
}

static int xilinx_gpio_ofdata_to_platdata(struct udevice *dev)
{
	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
	int is_dual;

	platdata->regs = (struct gpio_regs *)dev_read_addr(dev);

	platdata->bank_max[0] = dev_read_u32_default(dev,
						     "xlnx,gpio-width", 0);
	platdata->bank_input[0] = dev_read_u32_default(dev,
						       "xlnx,all-inputs", 0);
	platdata->bank_output[0] = dev_read_u32_default(dev,
							"xlnx,all-outputs", 0);
	platdata->dout_default[0] = dev_read_u32_default(dev,
							 "xlnx,dout-default",
							 0);

	is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
	if (is_dual) {
		platdata->bank_max[1] = dev_read_u32_default(dev,
						"xlnx,gpio2-width", 0);
		platdata->bank_input[1] = dev_read_u32_default(dev,
						"xlnx,all-inputs-2", 0);
		platdata->bank_output[1] = dev_read_u32_default(dev,
						"xlnx,all-outputs-2", 0);
		platdata->dout_default[1] = dev_read_u32_default(dev,
						"xlnx,dout-default-2", 0);
	}

	return 0;
}

static const struct udevice_id xilinx_gpio_ids[] = {
	{ .compatible = "xlnx,xps-gpio-1.00.a",},
	{ }
};

U_BOOT_DRIVER(xilinx_gpio) = {
	.name = "xlnx_gpio",
	.id = UCLASS_GPIO,
	.ops = &xilinx_gpio_ops,
	.of_match = xilinx_gpio_ids,
	.ofdata_to_platdata = xilinx_gpio_ofdata_to_platdata,
	.probe = xilinx_gpio_probe,
	.platdata_auto_alloc_size = sizeof(struct xilinx_gpio_platdata),
	.priv_auto_alloc_size = sizeof(struct xilinx_gpio_privdata),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
4e779ad2	2	/*
10441ec9	3	* Copyright (c) 2013 - 2018 Xilinx, Michal Simek
4e779ad2 MS	4	*/
	5
	6	#include <common.h>
	7	#include <errno.h>
	8	#include <malloc.h>
	9	#include <linux/list.h>
	10	#include <asm/io.h>
	11	#include <asm/gpio.h>
10441ec9	12	#include <dm.h>
6f81ff04	13	#include <dt-bindings/gpio/gpio.h>
4e779ad2	14
6f81ff04	15	#define XILINX_GPIO_MAX_BANK 2
4e779ad2 MS	16
	17	/* Gpio simple map */
	18	struct gpio_regs {
	19	u32 gpiodata;
	20	u32 gpiodir;
	21	};
	22
10441ec9 MS	23	struct xilinx_gpio_platdata {
	24	struct gpio_regs *regs;
	25	int bank_max[XILINX_GPIO_MAX_BANK];
	26	int bank_input[XILINX_GPIO_MAX_BANK];
	27	int bank_output[XILINX_GPIO_MAX_BANK];
c714aeae MS	28	u32 dout_default[XILINX_GPIO_MAX_BANK];
	29	};
	30
	31	struct xilinx_gpio_privdata {
	32	u32 output_val[XILINX_GPIO_MAX_BANK];
10441ec9 MS	33	};
	34
	35	static int xilinx_gpio_get_bank_pin(unsigned offset, u32 *bank_num,
	36	u32 bank_pin_num, struct udevice dev)
	37	{
	38	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
	39	u32 bank, max_pins;
	40	/* the first gpio is 0 not 1 */
	41	u32 pin_num = offset;
	42
	43	for (bank = 0; bank < XILINX_GPIO_MAX_BANK; bank++) {
	44	max_pins = platdata->bank_max[bank];
	45	if (pin_num < max_pins) {
	46	debug("%s: found at bank 0x%x pin 0x%x\n", __func__,
	47	bank, pin_num);
	48	*bank_num = bank;
	49	*bank_pin_num = pin_num;
	50	return 0;
	51	}
	52	pin_num -= max_pins;
	53	}
	54
	55	return -EINVAL;
	56	}
	57
	58	static int xilinx_gpio_set_value(struct udevice *dev, unsigned offset,
	59	int value)
	60	{
	61	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
c714aeae	62	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
10441ec9 MS	63	int val, ret;
	64	u32 bank, pin;
	65
	66	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	67	if (ret)
	68	return ret;
	69
c714aeae	70	val = priv->output_val[bank];
642a8604	71
c714aeae MS	72	debug("%s: regs: %lx, value: %x, gpio: %x, bank %x, pin %x, out %x\n",
c714aeae MS	73	__func__, (ulong)platdata->regs, value, offset, bank, pin, val);
10441ec9	74
642a8604	75	if (value)
10441ec9	76	val = val \| (1 << pin);
642a8604	77	else
10441ec9	78	val = val & ~(1 << pin);
642a8604 MS	79
642a8604 MS	80	writel(val, &platdata->regs->gpiodata + bank * 2);
10441ec9	81
c714aeae MS	82	priv->output_val[bank] = val;
c714aeae MS	83
ac7f0613	84	return 0;
10441ec9 MS	85	};
	86
	87	static int xilinx_gpio_get_value(struct udevice *dev, unsigned offset)
	88	{
	89	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
c714aeae	90	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
10441ec9 MS	91	int val, ret;
	92	u32 bank, pin;
	93
	94	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	95	if (ret)
	96	return ret;
	97
	98	debug("%s: regs: %lx, gpio: %x, bank %x, pin %x\n", __func__,
	99	(ulong)platdata->regs, offset, bank, pin);
	100
c714aeae MS	101	if (platdata->bank_output[bank]) {
	102	debug("%s: Read saved output value\n", __func__);
	103	val = priv->output_val[bank];
	104	} else {
	105	debug("%s: Read input value from reg\n", __func__);
	106	val = readl(&platdata->regs->gpiodata + bank * 2);
	107	}
	108
10441ec9 MS	109	val = !!(val & (1 << pin));
	110
	111	return val;
	112	};
	113
	114	static int xilinx_gpio_get_function(struct udevice *dev, unsigned offset)
	115	{
	116	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
	117	int val, ret;
	118	u32 bank, pin;
	119
ddd7b3fa MS	120	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	121	if (ret)
	122	return ret;
	123
10441ec9 MS	124	/* Check if all pins are inputs */
	125	if (platdata->bank_input[bank])
	126	return GPIOF_INPUT;
	127
	128	/* Check if all pins are outputs */
	129	if (platdata->bank_output[bank])
	130	return GPIOF_OUTPUT;
	131
10441ec9 MS	132	/* FIXME test on dual */
	133	val = readl(&platdata->regs->gpiodir + bank * 2);
	134	val = !(val & (1 << pin));
	135
	136	/* input is 1 in reg but GPIOF_INPUT is 0 */
	137	/* output is 0 in reg but GPIOF_OUTPUT is 1 */
	138
	139	return val;
	140	}
	141
	142	static int xilinx_gpio_direction_output(struct udevice *dev, unsigned offset,
	143	int value)
	144	{
	145	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
	146	int val, ret;
	147	u32 bank, pin;
	148
	149	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	150	if (ret)
	151	return ret;
	152
	153	/* can't change it if all is input by default */
	154	if (platdata->bank_input[bank])
	155	return -EINVAL;
	156
bf2a69de MS	157	xilinx_gpio_set_value(dev, offset, value);
bf2a69de MS	158
10441ec9 MS	159	if (!platdata->bank_output[bank]) {
	160	val = readl(&platdata->regs->gpiodir + bank * 2);
	161	val = val & ~(1 << pin);
	162	writel(val, &platdata->regs->gpiodir + bank * 2);
	163	}
	164
10441ec9 MS	165	return 0;
	166	}
	167
	168	static int xilinx_gpio_direction_input(struct udevice *dev, unsigned offset)
	169	{
	170	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
	171	int val, ret;
	172	u32 bank, pin;
	173
	174	ret = xilinx_gpio_get_bank_pin(offset, &bank, &pin, dev);
	175	if (ret)
	176	return ret;
	177
	178	/* Already input */
	179	if (platdata->bank_input[bank])
	180	return 0;
	181
	182	/* can't change it if all is output by default */
	183	if (platdata->bank_output[bank])
	184	return -EINVAL;
	185
	186	val = readl(&platdata->regs->gpiodir + bank * 2);
	187	val = val \| (1 << pin);
	188	writel(val, &platdata->regs->gpiodir + bank * 2);
	189
	190	return 0;
	191	}
	192
	193	static int xilinx_gpio_xlate(struct udevice dev, struct gpio_desc desc,
	194	struct ofnode_phandle_args *args)
	195	{
	196	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
	197
	198	desc->offset = args->args[0];
	199
	200	debug("%s: argc: %x, [0]: %x, [1]: %x, [2]: %x\n", __func__,
	201	args->args_count, args->args[0], args->args[1], args->args[2]);
	202
	203	/*
	204	* The second cell is channel offset:
	205	* 0 is first channel, 8 is second channel
	206	*
	207	* U-Boot driver just combine channels together that's why simply
	208	* add amount of pins in second channel if present.
	209	*/
	210	if (args->args[1]) {
	211	if (!platdata->bank_max[1]) {
	212	printf("%s: %s has no second channel\n",
	213	__func__, dev->name);
	214	return -EINVAL;
	215	}
	216
	217	desc->offset += platdata->bank_max[0];
	218	}
	219
	220	/* The third cell is optional */
	221	if (args->args_count > 2)
	222	desc->flags = (args->args[2] &
	223	GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0);
	224
	225	debug("%s: offset %x, flags %lx\n",
	226	__func__, desc->offset, desc->flags);
	227	return 0;
	228	}
229
230	static const struct dm_gpio_ops xilinx_gpio_ops = {
231	.direction_input = xilinx_gpio_direction_input,
232	.direction_output = xilinx_gpio_direction_output,
233	.get_value = xilinx_gpio_get_value,
234	.set_value = xilinx_gpio_set_value,
235	.get_function = xilinx_gpio_get_function,
236	.xlate = xilinx_gpio_xlate,
237	};
238
239	static int xilinx_gpio_probe(struct udevice *dev)
240	{
241	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
c714aeae	242	struct xilinx_gpio_privdata *priv = dev_get_priv(dev);
10441ec9	243	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
312dd1c5	244	const void *label_ptr;
10441ec9	245
312dd1c5 MS	246	label_ptr = dev_read_prop(dev, "label", NULL);
	247	if (label_ptr) {
	248	uc_priv->bank_name = strdup(label_ptr);
	249	if (!uc_priv->bank_name)
	250	return -ENOMEM;
	251	} else {
	252	uc_priv->bank_name = dev->name;
	253	}
10441ec9 MS	254
	255	uc_priv->gpio_count = platdata->bank_max[0] + platdata->bank_max[1];
	256
c714aeae MS	257	priv->output_val[0] = platdata->dout_default[0];
	258
	259	if (platdata->bank_max[1])
	260	priv->output_val[1] = platdata->dout_default[1];
	261
10441ec9 MS	262	return 0;
	263	}
	264
	265	static int xilinx_gpio_ofdata_to_platdata(struct udevice *dev)
	266	{
	267	struct xilinx_gpio_platdata *platdata = dev_get_platdata(dev);
	268	int is_dual;
	269
	270	platdata->regs = (struct gpio_regs *)dev_read_addr(dev);
	271
	272	platdata->bank_max[0] = dev_read_u32_default(dev,
	273	"xlnx,gpio-width", 0);
	274	platdata->bank_input[0] = dev_read_u32_default(dev,
	275	"xlnx,all-inputs", 0);
	276	platdata->bank_output[0] = dev_read_u32_default(dev,
	277	"xlnx,all-outputs", 0);
c714aeae MS	278	platdata->dout_default[0] = dev_read_u32_default(dev,
	279	"xlnx,dout-default",
	280	0);
10441ec9 MS	281
	282	is_dual = dev_read_u32_default(dev, "xlnx,is-dual", 0);
	283	if (is_dual) {
	284	platdata->bank_max[1] = dev_read_u32_default(dev,
	285	"xlnx,gpio2-width", 0);
	286	platdata->bank_input[1] = dev_read_u32_default(dev,
	287	"xlnx,all-inputs-2", 0);
	288	platdata->bank_output[1] = dev_read_u32_default(dev,
	289	"xlnx,all-outputs-2", 0);
c714aeae MS	290	platdata->dout_default[1] = dev_read_u32_default(dev,
c714aeae MS	291	"xlnx,dout-default-2", 0);
10441ec9 MS	292	}
	293
	294	return 0;
	295	}
	296
	297	static const struct udevice_id xilinx_gpio_ids[] = {
	298	{ .compatible = "xlnx,xps-gpio-1.00.a",},
	299	{ }
	300	};
	301
	302	U_BOOT_DRIVER(xilinx_gpio) = {
	303	.name = "xlnx_gpio",
	304	.id = UCLASS_GPIO,
	305	.ops = &xilinx_gpio_ops,
	306	.of_match = xilinx_gpio_ids,
	307	.ofdata_to_platdata = xilinx_gpio_ofdata_to_platdata,
	308	.probe = xilinx_gpio_probe,
	309	.platdata_auto_alloc_size = sizeof(struct xilinx_gpio_platdata),
c714aeae	310	.priv_auto_alloc_size = sizeof(struct xilinx_gpio_privdata),
10441ec9	311	};