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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
d38ceaf9 | 25 | #include <drm/amdgpu_drm.h> |
fdf2f6c5 | 26 | #include <drm/drm_drv.h> |
d38ceaf9 | 27 | #include <drm/drm_gem.h> |
fdf2f6c5 | 28 | #include <drm/drm_vblank.h> |
d38ceaf9 AD |
29 | #include "amdgpu_drv.h" |
30 | ||
31 | #include <drm/drm_pciids.h> | |
32 | #include <linux/console.h> | |
33 | #include <linux/module.h> | |
fdf2f6c5 | 34 | #include <linux/pci.h> |
d38ceaf9 AD |
35 | #include <linux/pm_runtime.h> |
36 | #include <linux/vga_switcheroo.h> | |
fcd70cd3 | 37 | #include <drm/drm_probe_helper.h> |
c7d8b782 | 38 | #include <linux/mmu_notifier.h> |
d38ceaf9 AD |
39 | |
40 | #include "amdgpu.h" | |
41 | #include "amdgpu_irq.h" | |
2fbd6f94 | 42 | #include "amdgpu_dma_buf.h" |
d38ceaf9 | 43 | |
130e0371 OG |
44 | #include "amdgpu_amdkfd.h" |
45 | ||
7c6e68c7 AG |
46 | #include "amdgpu_ras.h" |
47 | ||
d38ceaf9 AD |
48 | /* |
49 | * KMS wrapper. | |
50 | * - 3.0.0 - initial driver | |
6055f37a | 51 | * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) |
f84e63f2 MO |
52 | * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same |
53 | * at the end of IBs. | |
d347ce66 | 54 | * - 3.3.0 - Add VM support for UVD on supported hardware. |
83a59b63 | 55 | * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. |
8dd31d74 | 56 | * - 3.5.0 - Add support for new UVD_NO_OP register. |
753ad49c | 57 | * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. |
9cee3c1f | 58 | * - 3.7.0 - Add support for VCE clock list packet |
b62b5931 | 59 | * - 3.8.0 - Add support raster config init in the kernel |
ef704318 | 60 | * - 3.9.0 - Add support for memory query info about VRAM and GTT. |
a5b11dac | 61 | * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags |
5ebbac4b | 62 | * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). |
dfe38bd8 | 63 | * - 3.12.0 - Add query for double offchip LDS buffers |
8eafd505 | 64 | * - 3.13.0 - Add PRT support |
203eb0cb | 65 | * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality |
44eb8c1b | 66 | * - 3.15.0 - Export more gpu info for gfx9 |
b98b8dbc | 67 | * - 3.16.0 - Add reserved vmid support |
68e2c5ff | 68 | * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. |
dbfe85ea | 69 | * - 3.18.0 - Export gpu always on cu bitmap |
33476319 | 70 | * - 3.19.0 - Add support for UVD MJPEG decode |
fd8bf087 | 71 | * - 3.20.0 - Add support for local BOs |
7ca24cf2 | 72 | * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl |
b285f1db | 73 | * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl |
c057c114 | 74 | * - 3.23.0 - Add query for VRAM lost counter |
f8e3e0ee | 75 | * - 3.24.0 - Add high priority compute support for gfx9 |
7b158d16 | 76 | * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). |
d240cd9e | 77 | * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. |
964d0fbf | 78 | * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. |
67dd1a36 | 79 | * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES |
41cca166 | 80 | * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID |
767e06a9 | 81 | * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. |
df8368be | 82 | * - 3.31.0 - Add support for per-flip tiling attribute changes with DC |
1afeb314 | 83 | * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. |
635e2c5f | 84 | * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. |
965ebe3d | 85 | * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches |
815fb4c9 | 86 | * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask |
664fe85a | 87 | * - 3.36.0 - Allow reading more status registers on si/cik |
9017a489 | 88 | * - 3.37.0 - L2 is invalidated before SDMA IBs, needed for correctness |
d38ceaf9 AD |
89 | */ |
90 | #define KMS_DRIVER_MAJOR 3 | |
9017a489 | 91 | #define KMS_DRIVER_MINOR 37 |
d38ceaf9 AD |
92 | #define KMS_DRIVER_PATCHLEVEL 0 |
93 | ||
94 | int amdgpu_vram_limit = 0; | |
218b5dcd | 95 | int amdgpu_vis_vram_limit = 0; |
83e74db6 | 96 | int amdgpu_gart_size = -1; /* auto */ |
36d38372 | 97 | int amdgpu_gtt_size = -1; /* auto */ |
95844d20 | 98 | int amdgpu_moverate = -1; /* auto */ |
d38ceaf9 AD |
99 | int amdgpu_benchmarking = 0; |
100 | int amdgpu_testing = 0; | |
101 | int amdgpu_audio = -1; | |
102 | int amdgpu_disp_priority = 0; | |
103 | int amdgpu_hw_i2c = 0; | |
104 | int amdgpu_pcie_gen2 = -1; | |
105 | int amdgpu_msi = -1; | |
f440ff44 | 106 | char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; |
d38ceaf9 | 107 | int amdgpu_dpm = -1; |
e635ee07 | 108 | int amdgpu_fw_load_type = -1; |
d38ceaf9 AD |
109 | int amdgpu_aspm = -1; |
110 | int amdgpu_runtime_pm = -1; | |
0b693f0b | 111 | uint amdgpu_ip_block_mask = 0xffffffff; |
d38ceaf9 AD |
112 | int amdgpu_bapm = -1; |
113 | int amdgpu_deep_color = 0; | |
bab4fee7 | 114 | int amdgpu_vm_size = -1; |
d07f14be | 115 | int amdgpu_vm_fragment_size = -1; |
d38ceaf9 | 116 | int amdgpu_vm_block_size = -1; |
d9c13156 | 117 | int amdgpu_vm_fault_stop = 0; |
b495bd3a | 118 | int amdgpu_vm_debug = 0; |
9a4b7d4c | 119 | int amdgpu_vm_update_mode = -1; |
d38ceaf9 | 120 | int amdgpu_exp_hw_support = 0; |
4562236b | 121 | int amdgpu_dc = -1; |
b70f014d | 122 | int amdgpu_sched_jobs = 32; |
4afcb303 | 123 | int amdgpu_sched_hw_submission = 2; |
0b693f0b RZ |
124 | uint amdgpu_pcie_gen_cap = 0; |
125 | uint amdgpu_pcie_lane_cap = 0; | |
126 | uint amdgpu_cg_mask = 0xffffffff; | |
127 | uint amdgpu_pg_mask = 0xffffffff; | |
128 | uint amdgpu_sdma_phase_quantum = 32; | |
6f8941a2 | 129 | char *amdgpu_disable_cu = NULL; |
9accf2fd | 130 | char *amdgpu_virtual_display = NULL; |
00544006 HR |
131 | /* OverDrive(bit 14) disabled by default*/ |
132 | uint amdgpu_pp_feature_mask = 0xffffbfff; | |
367039bf | 133 | uint amdgpu_force_long_training = 0; |
65781c78 | 134 | int amdgpu_job_hang_limit = 0; |
e8835e0e | 135 | int amdgpu_lbpw = -1; |
4a75aefe | 136 | int amdgpu_compute_multipipe = -1; |
dcebf026 | 137 | int amdgpu_gpu_recovery = -1; /* auto */ |
bfca0289 | 138 | int amdgpu_emu_mode = 0; |
7951e376 | 139 | uint amdgpu_smu_memory_pool_size = 0; |
7875a226 AD |
140 | /* FBC (bit 0) disabled by default*/ |
141 | uint amdgpu_dc_feature_mask = 0; | |
5bfca069 | 142 | int amdgpu_async_gfx_ring = 1; |
b239c017 | 143 | int amdgpu_mcbp = 0; |
63e2fef6 | 144 | int amdgpu_discovery = -1; |
38487284 | 145 | int amdgpu_mes = 0; |
7aec9ec1 | 146 | int amdgpu_noretry; |
4e66d7d2 | 147 | int amdgpu_force_asic_type = -1; |
7875a226 | 148 | |
62d73fbc EQ |
149 | struct amdgpu_mgpu_info mgpu_info = { |
150 | .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), | |
151 | }; | |
1218252f | 152 | int amdgpu_ras_enable = -1; |
e53aec7e | 153 | uint amdgpu_ras_mask = 0xffffffff; |
d38ceaf9 | 154 | |
8405cf39 SJ |
155 | /** |
156 | * DOC: vramlimit (int) | |
157 | * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). | |
158 | */ | |
d38ceaf9 AD |
159 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); |
160 | module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); | |
161 | ||
8405cf39 SJ |
162 | /** |
163 | * DOC: vis_vramlimit (int) | |
164 | * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). | |
165 | */ | |
218b5dcd JB |
166 | MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); |
167 | module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); | |
168 | ||
8405cf39 SJ |
169 | /** |
170 | * DOC: gartsize (uint) | |
171 | * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). | |
172 | */ | |
a4da14cc | 173 | MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); |
f9321cc4 | 174 | module_param_named(gartsize, amdgpu_gart_size, uint, 0600); |
d38ceaf9 | 175 | |
8405cf39 SJ |
176 | /** |
177 | * DOC: gttsize (int) | |
178 | * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, | |
179 | * otherwise 3/4 RAM size). | |
180 | */ | |
36d38372 CK |
181 | MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); |
182 | module_param_named(gttsize, amdgpu_gtt_size, int, 0600); | |
d38ceaf9 | 183 | |
8405cf39 SJ |
184 | /** |
185 | * DOC: moverate (int) | |
186 | * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). | |
187 | */ | |
95844d20 MO |
188 | MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); |
189 | module_param_named(moverate, amdgpu_moverate, int, 0600); | |
190 | ||
8405cf39 SJ |
191 | /** |
192 | * DOC: benchmark (int) | |
193 | * Run benchmarks. The default is 0 (Skip benchmarks). | |
194 | */ | |
d38ceaf9 AD |
195 | MODULE_PARM_DESC(benchmark, "Run benchmark"); |
196 | module_param_named(benchmark, amdgpu_benchmarking, int, 0444); | |
197 | ||
8405cf39 SJ |
198 | /** |
199 | * DOC: test (int) | |
200 | * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). | |
201 | */ | |
d38ceaf9 AD |
202 | MODULE_PARM_DESC(test, "Run tests"); |
203 | module_param_named(test, amdgpu_testing, int, 0444); | |
204 | ||
8405cf39 SJ |
205 | /** |
206 | * DOC: audio (int) | |
207 | * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. | |
208 | */ | |
d38ceaf9 AD |
209 | MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); |
210 | module_param_named(audio, amdgpu_audio, int, 0444); | |
211 | ||
8405cf39 SJ |
212 | /** |
213 | * DOC: disp_priority (int) | |
214 | * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). | |
215 | */ | |
d38ceaf9 AD |
216 | MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); |
217 | module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); | |
218 | ||
8405cf39 SJ |
219 | /** |
220 | * DOC: hw_i2c (int) | |
221 | * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). | |
222 | */ | |
d38ceaf9 AD |
223 | MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); |
224 | module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); | |
225 | ||
8405cf39 SJ |
226 | /** |
227 | * DOC: pcie_gen2 (int) | |
228 | * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). | |
229 | */ | |
d38ceaf9 AD |
230 | MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); |
231 | module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); | |
232 | ||
8405cf39 SJ |
233 | /** |
234 | * DOC: msi (int) | |
235 | * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). | |
236 | */ | |
d38ceaf9 AD |
237 | MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); |
238 | module_param_named(msi, amdgpu_msi, int, 0444); | |
239 | ||
8405cf39 | 240 | /** |
912dfc84 EQ |
241 | * DOC: lockup_timeout (string) |
242 | * Set GPU scheduler timeout value in ms. | |
243 | * | |
244 | * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or | |
245 | * multiple values specified. 0 and negative values are invalidated. They will be adjusted | |
879e723d AZ |
246 | * to the default timeout. |
247 | * | |
248 | * - With one value specified, the setting will apply to all non-compute jobs. | |
249 | * - With multiple values specified, the first one will be for GFX. | |
250 | * The second one is for Compute. The third and fourth ones are | |
251 | * for SDMA and Video. | |
252 | * | |
912dfc84 EQ |
253 | * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) |
254 | * jobs is 10000. And there is no timeout enforced on compute jobs. | |
255 | */ | |
bcccee89 ED |
256 | MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " |
257 | "for passthrough or sriov, 10000 for all jobs." | |
71cc9ef3 | 258 | " 0: keep default value. negative: infinity timeout), " |
bcccee89 ED |
259 | "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " |
260 | "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); | |
912dfc84 | 261 | module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); |
d38ceaf9 | 262 | |
8405cf39 SJ |
263 | /** |
264 | * DOC: dpm (int) | |
54b998ca HZ |
265 | * Override for dynamic power management setting |
266 | * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20) | |
267 | * The default is -1 (auto). | |
8405cf39 | 268 | */ |
d38ceaf9 AD |
269 | MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); |
270 | module_param_named(dpm, amdgpu_dpm, int, 0444); | |
271 | ||
8405cf39 SJ |
272 | /** |
273 | * DOC: fw_load_type (int) | |
274 | * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). | |
275 | */ | |
e635ee07 HR |
276 | MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); |
277 | module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); | |
d38ceaf9 | 278 | |
8405cf39 SJ |
279 | /** |
280 | * DOC: aspm (int) | |
281 | * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). | |
282 | */ | |
d38ceaf9 AD |
283 | MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); |
284 | module_param_named(aspm, amdgpu_aspm, int, 0444); | |
285 | ||
8405cf39 SJ |
286 | /** |
287 | * DOC: runpm (int) | |
288 | * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down | |
289 | * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. | |
290 | */ | |
d38ceaf9 AD |
291 | MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); |
292 | module_param_named(runpm, amdgpu_runtime_pm, int, 0444); | |
293 | ||
8405cf39 SJ |
294 | /** |
295 | * DOC: ip_block_mask (uint) | |
296 | * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). | |
297 | * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have | |
298 | * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in | |
299 | * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). | |
300 | */ | |
d38ceaf9 AD |
301 | MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); |
302 | module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); | |
303 | ||
8405cf39 SJ |
304 | /** |
305 | * DOC: bapm (int) | |
306 | * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. | |
307 | * The default -1 (auto, enabled) | |
308 | */ | |
d38ceaf9 AD |
309 | MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); |
310 | module_param_named(bapm, amdgpu_bapm, int, 0444); | |
311 | ||
8405cf39 SJ |
312 | /** |
313 | * DOC: deep_color (int) | |
314 | * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). | |
315 | */ | |
d38ceaf9 AD |
316 | MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); |
317 | module_param_named(deep_color, amdgpu_deep_color, int, 0444); | |
318 | ||
8405cf39 SJ |
319 | /** |
320 | * DOC: vm_size (int) | |
321 | * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). | |
322 | */ | |
ed885b21 | 323 | MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); |
d38ceaf9 | 324 | module_param_named(vm_size, amdgpu_vm_size, int, 0444); |
d07f14be | 325 | |
8405cf39 SJ |
326 | /** |
327 | * DOC: vm_fragment_size (int) | |
328 | * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). | |
329 | */ | |
d07f14be RH |
330 | MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); |
331 | module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); | |
d38ceaf9 | 332 | |
8405cf39 SJ |
333 | /** |
334 | * DOC: vm_block_size (int) | |
335 | * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). | |
336 | */ | |
d38ceaf9 AD |
337 | MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); |
338 | module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); | |
339 | ||
8405cf39 SJ |
340 | /** |
341 | * DOC: vm_fault_stop (int) | |
342 | * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). | |
343 | */ | |
d9c13156 CK |
344 | MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); |
345 | module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); | |
346 | ||
8405cf39 SJ |
347 | /** |
348 | * DOC: vm_debug (int) | |
349 | * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). | |
350 | */ | |
b495bd3a CK |
351 | MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); |
352 | module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); | |
353 | ||
8405cf39 SJ |
354 | /** |
355 | * DOC: vm_update_mode (int) | |
356 | * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default | |
357 | * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). | |
358 | */ | |
9a4b7d4c HK |
359 | MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); |
360 | module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); | |
361 | ||
8405cf39 SJ |
362 | /** |
363 | * DOC: exp_hw_support (int) | |
364 | * Enable experimental hw support (1 = enable). The default is 0 (disabled). | |
365 | */ | |
d38ceaf9 AD |
366 | MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); |
367 | module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); | |
368 | ||
8405cf39 SJ |
369 | /** |
370 | * DOC: dc (int) | |
371 | * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). | |
372 | */ | |
4562236b HW |
373 | MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); |
374 | module_param_named(dc, amdgpu_dc, int, 0444); | |
375 | ||
8405cf39 SJ |
376 | /** |
377 | * DOC: sched_jobs (int) | |
378 | * Override the max number of jobs supported in the sw queue. The default is 32. | |
379 | */ | |
b70f014d | 380 | MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); |
1333f723 JZ |
381 | module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); |
382 | ||
8405cf39 SJ |
383 | /** |
384 | * DOC: sched_hw_submission (int) | |
385 | * Override the max number of HW submissions. The default is 2. | |
386 | */ | |
4afcb303 JZ |
387 | MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); |
388 | module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); | |
389 | ||
8405cf39 SJ |
390 | /** |
391 | * DOC: ppfeaturemask (uint) | |
392 | * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. | |
393 | * The default is the current set of stable power features. | |
394 | */ | |
5141e9d2 | 395 | MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); |
88826351 | 396 | module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); |
3a74f6f2 | 397 | |
367039bf TY |
398 | /** |
399 | * DOC: forcelongtraining (uint) | |
400 | * Force long memory training in resume. | |
401 | * The default is zero, indicates short training in resume. | |
402 | */ | |
403 | MODULE_PARM_DESC(forcelongtraining, "force memory long training"); | |
404 | module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); | |
405 | ||
8405cf39 SJ |
406 | /** |
407 | * DOC: pcie_gen_cap (uint) | |
408 | * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. | |
409 | * The default is 0 (automatic for each asic). | |
410 | */ | |
cd474ba0 AD |
411 | MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); |
412 | module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); | |
413 | ||
8405cf39 SJ |
414 | /** |
415 | * DOC: pcie_lane_cap (uint) | |
416 | * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. | |
417 | * The default is 0 (automatic for each asic). | |
418 | */ | |
cd474ba0 AD |
419 | MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); |
420 | module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); | |
421 | ||
8405cf39 SJ |
422 | /** |
423 | * DOC: cg_mask (uint) | |
424 | * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in | |
425 | * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). | |
426 | */ | |
395d1fb9 NH |
427 | MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); |
428 | module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); | |
429 | ||
8405cf39 SJ |
430 | /** |
431 | * DOC: pg_mask (uint) | |
432 | * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in | |
433 | * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). | |
434 | */ | |
395d1fb9 NH |
435 | MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); |
436 | module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); | |
437 | ||
8405cf39 SJ |
438 | /** |
439 | * DOC: sdma_phase_quantum (uint) | |
440 | * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. | |
441 | */ | |
a667386c FK |
442 | MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); |
443 | module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); | |
444 | ||
8405cf39 SJ |
445 | /** |
446 | * DOC: disable_cu (charp) | |
447 | * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. | |
448 | */ | |
6f8941a2 NH |
449 | MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); |
450 | module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); | |
451 | ||
8405cf39 SJ |
452 | /** |
453 | * DOC: virtual_display (charp) | |
454 | * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards | |
455 | * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of | |
456 | * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci | |
457 | * device at 26:00.0. The default is NULL. | |
458 | */ | |
0f66356d ED |
459 | MODULE_PARM_DESC(virtual_display, |
460 | "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); | |
9accf2fd | 461 | module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); |
e443059d | 462 | |
8405cf39 SJ |
463 | /** |
464 | * DOC: job_hang_limit (int) | |
465 | * Set how much time allow a job hang and not drop it. The default is 0. | |
466 | */ | |
65781c78 ML |
467 | MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); |
468 | module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); | |
469 | ||
8405cf39 SJ |
470 | /** |
471 | * DOC: lbpw (int) | |
472 | * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). | |
473 | */ | |
e8835e0e HZ |
474 | MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); |
475 | module_param_named(lbpw, amdgpu_lbpw, int, 0444); | |
bce23e00 | 476 | |
4a75aefe AR |
477 | MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); |
478 | module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); | |
479 | ||
8405cf39 SJ |
480 | /** |
481 | * DOC: gpu_recovery (int) | |
482 | * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). | |
483 | */ | |
d869ae09 | 484 | MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); |
dcebf026 AG |
485 | module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); |
486 | ||
8405cf39 SJ |
487 | /** |
488 | * DOC: emu_mode (int) | |
489 | * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). | |
490 | */ | |
d869ae09 | 491 | MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); |
bfca0289 SL |
492 | module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); |
493 | ||
1218252f | 494 | /** |
2f3940e9 | 495 | * DOC: ras_enable (int) |
1218252f | 496 | * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) |
497 | */ | |
2f3940e9 | 498 | MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); |
1218252f | 499 | module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); |
500 | ||
501 | /** | |
2f3940e9 | 502 | * DOC: ras_mask (uint) |
1218252f | 503 | * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 |
504 | * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | |
505 | */ | |
2f3940e9 | 506 | MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); |
1218252f | 507 | module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); |
508 | ||
8405cf39 SJ |
509 | /** |
510 | * DOC: si_support (int) | |
511 | * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, | |
512 | * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, | |
513 | * otherwise using amdgpu driver. | |
514 | */ | |
6dd13096 | 515 | #ifdef CONFIG_DRM_AMDGPU_SI |
53efaf56 MD |
516 | |
517 | #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) | |
6dd13096 FK |
518 | int amdgpu_si_support = 0; |
519 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); | |
53efaf56 MD |
520 | #else |
521 | int amdgpu_si_support = 1; | |
522 | MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); | |
523 | #endif | |
524 | ||
6dd13096 FK |
525 | module_param_named(si_support, amdgpu_si_support, int, 0444); |
526 | #endif | |
527 | ||
8405cf39 SJ |
528 | /** |
529 | * DOC: cik_support (int) | |
530 | * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, | |
531 | * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, | |
532 | * otherwise using amdgpu driver. | |
533 | */ | |
7df28986 | 534 | #ifdef CONFIG_DRM_AMDGPU_CIK |
53efaf56 MD |
535 | |
536 | #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) | |
2b059658 MD |
537 | int amdgpu_cik_support = 0; |
538 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); | |
53efaf56 MD |
539 | #else |
540 | int amdgpu_cik_support = 1; | |
541 | MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); | |
542 | #endif | |
543 | ||
7df28986 FK |
544 | module_param_named(cik_support, amdgpu_cik_support, int, 0444); |
545 | #endif | |
546 | ||
8405cf39 SJ |
547 | /** |
548 | * DOC: smu_memory_pool_size (uint) | |
549 | * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. | |
550 | * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). | |
551 | */ | |
7951e376 RZ |
552 | MODULE_PARM_DESC(smu_memory_pool_size, |
553 | "reserve gtt for smu debug usage, 0 = disable," | |
554 | "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); | |
555 | module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); | |
556 | ||
51bcce46 HZ |
557 | /** |
558 | * DOC: async_gfx_ring (int) | |
559 | * It is used to enable gfx rings that could be configured with different prioritites or equal priorities | |
560 | */ | |
561 | MODULE_PARM_DESC(async_gfx_ring, | |
5bfca069 | 562 | "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); |
51bcce46 HZ |
563 | module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); |
564 | ||
40562787 AD |
565 | /** |
566 | * DOC: mcbp (int) | |
567 | * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) | |
568 | */ | |
b239c017 JX |
569 | MODULE_PARM_DESC(mcbp, |
570 | "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); | |
571 | module_param_named(mcbp, amdgpu_mcbp, int, 0444); | |
572 | ||
40562787 AD |
573 | /** |
574 | * DOC: discovery (int) | |
575 | * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. | |
63e2fef6 | 576 | * (-1 = auto (default), 0 = disabled, 1 = enabled) |
40562787 | 577 | */ |
a190d1c7 XY |
578 | MODULE_PARM_DESC(discovery, |
579 | "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); | |
580 | module_param_named(discovery, amdgpu_discovery, int, 0444); | |
581 | ||
40562787 AD |
582 | /** |
583 | * DOC: mes (int) | |
584 | * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. | |
585 | * (0 = disabled (default), 1 = enabled) | |
586 | */ | |
38487284 JX |
587 | MODULE_PARM_DESC(mes, |
588 | "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); | |
589 | module_param_named(mes, amdgpu_mes, int, 0444); | |
590 | ||
75ee6487 | 591 | MODULE_PARM_DESC(noretry, |
7aec9ec1 | 592 | "Disable retry faults (0 = retry enabled (default), 1 = retry disabled)"); |
75ee6487 FK |
593 | module_param_named(noretry, amdgpu_noretry, int, 0644); |
594 | ||
4e66d7d2 YZ |
595 | /** |
596 | * DOC: force_asic_type (int) | |
597 | * A non negative value used to specify the asic type for all supported GPUs. | |
598 | */ | |
599 | MODULE_PARM_DESC(force_asic_type, | |
600 | "A non negative value used to specify the asic type for all supported GPUs"); | |
601 | module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); | |
602 | ||
603 | ||
604 | ||
2690262e | 605 | #ifdef CONFIG_HSA_AMD |
521fb7d0 AL |
606 | /** |
607 | * DOC: sched_policy (int) | |
608 | * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. | |
609 | * Setting 1 disables over-subscription. Setting 2 disables HWS and statically | |
610 | * assigns queues to HQDs. | |
611 | */ | |
2690262e | 612 | int sched_policy = KFD_SCHED_POLICY_HWS; |
521fb7d0 AL |
613 | module_param(sched_policy, int, 0444); |
614 | MODULE_PARM_DESC(sched_policy, | |
615 | "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); | |
616 | ||
617 | /** | |
618 | * DOC: hws_max_conc_proc (int) | |
619 | * Maximum number of processes that HWS can schedule concurrently. The maximum is the | |
620 | * number of VMIDs assigned to the HWS, which is also the default. | |
621 | */ | |
2690262e | 622 | int hws_max_conc_proc = 8; |
521fb7d0 AL |
623 | module_param(hws_max_conc_proc, int, 0444); |
624 | MODULE_PARM_DESC(hws_max_conc_proc, | |
625 | "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); | |
626 | ||
627 | /** | |
628 | * DOC: cwsr_enable (int) | |
629 | * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in | |
630 | * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 | |
631 | * disables it. | |
632 | */ | |
2690262e | 633 | int cwsr_enable = 1; |
521fb7d0 AL |
634 | module_param(cwsr_enable, int, 0444); |
635 | MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); | |
636 | ||
637 | /** | |
638 | * DOC: max_num_of_queues_per_device (int) | |
639 | * Maximum number of queues per device. Valid setting is between 1 and 4096. Default | |
640 | * is 4096. | |
641 | */ | |
2690262e | 642 | int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; |
521fb7d0 AL |
643 | module_param(max_num_of_queues_per_device, int, 0444); |
644 | MODULE_PARM_DESC(max_num_of_queues_per_device, | |
645 | "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); | |
646 | ||
647 | /** | |
648 | * DOC: send_sigterm (int) | |
649 | * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm | |
650 | * but just print errors on dmesg. Setting 1 enables sending sigterm. | |
651 | */ | |
2690262e | 652 | int send_sigterm; |
521fb7d0 AL |
653 | module_param(send_sigterm, int, 0444); |
654 | MODULE_PARM_DESC(send_sigterm, | |
655 | "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); | |
656 | ||
657 | /** | |
658 | * DOC: debug_largebar (int) | |
659 | * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar | |
660 | * system. This limits the VRAM size reported to ROCm applications to the visible | |
661 | * size, usually 256MB. | |
662 | * Default value is 0, diabled. | |
663 | */ | |
2690262e | 664 | int debug_largebar; |
521fb7d0 AL |
665 | module_param(debug_largebar, int, 0444); |
666 | MODULE_PARM_DESC(debug_largebar, | |
667 | "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); | |
668 | ||
669 | /** | |
670 | * DOC: ignore_crat (int) | |
671 | * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT | |
672 | * table to get information about AMD APUs. This option can serve as a workaround on | |
673 | * systems with a broken CRAT table. | |
674 | */ | |
2690262e | 675 | int ignore_crat; |
521fb7d0 AL |
676 | module_param(ignore_crat, int, 0444); |
677 | MODULE_PARM_DESC(ignore_crat, | |
678 | "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); | |
679 | ||
521fb7d0 AL |
680 | /** |
681 | * DOC: halt_if_hws_hang (int) | |
682 | * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. | |
683 | * Setting 1 enables halt on hang. | |
684 | */ | |
2690262e | 685 | int halt_if_hws_hang; |
521fb7d0 AL |
686 | module_param(halt_if_hws_hang, int, 0644); |
687 | MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); | |
29e76462 OZ |
688 | |
689 | /** | |
690 | * DOC: hws_gws_support(bool) | |
691 | * Whether HWS support gws barriers. Default value: false (not supported) | |
692 | * This will be replaced with a MEC firmware version check once firmware | |
693 | * is ready | |
694 | */ | |
695 | bool hws_gws_support; | |
696 | module_param(hws_gws_support, bool, 0444); | |
697 | MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)"); | |
14328aa5 PC |
698 | |
699 | /** | |
700 | * DOC: queue_preemption_timeout_ms (int) | |
701 | * queue preemption timeout in ms (1 = Minimum, 9000 = default) | |
702 | */ | |
f51af435 | 703 | int queue_preemption_timeout_ms = 9000; |
14328aa5 PC |
704 | module_param(queue_preemption_timeout_ms, int, 0644); |
705 | MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); | |
2690262e | 706 | #endif |
521fb7d0 | 707 | |
7875a226 AD |
708 | /** |
709 | * DOC: dcfeaturemask (uint) | |
710 | * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. | |
711 | * The default is the current set of stable display features. | |
712 | */ | |
713 | MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); | |
714 | module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); | |
715 | ||
ad4de27f NK |
716 | /** |
717 | * DOC: abmlevel (uint) | |
718 | * Override the default ABM (Adaptive Backlight Management) level used for DC | |
719 | * enabled hardware. Requires DMCU to be supported and loaded. | |
720 | * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by | |
721 | * default. Values 1-4 control the maximum allowable brightness reduction via | |
722 | * the ABM algorithm, with 1 being the least reduction and 4 being the most | |
723 | * reduction. | |
724 | * | |
725 | * Defaults to 0, or disabled. Userspace can still override this level later | |
726 | * after boot. | |
727 | */ | |
728 | uint amdgpu_dm_abm_level = 0; | |
729 | MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); | |
730 | module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); | |
731 | ||
f498d9ed | 732 | static const struct pci_device_id pciidlist[] = { |
78fbb685 KW |
733 | #ifdef CONFIG_DRM_AMDGPU_SI |
734 | {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
735 | {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
736 | {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
737 | {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
738 | {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
739 | {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
740 | {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
741 | {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
742 | {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
743 | {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
744 | {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
745 | {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
746 | {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, | |
747 | {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
748 | {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
749 | {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, | |
750 | {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
751 | {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
752 | {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
753 | {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
754 | {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
755 | {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
756 | {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
757 | {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
758 | {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, | |
759 | {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
760 | {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
761 | {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
762 | {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
763 | {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
764 | {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
765 | {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
766 | {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
767 | {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
768 | {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
769 | {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
770 | {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
771 | {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
772 | {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
773 | {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
774 | {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, | |
775 | {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, | |
776 | {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
777 | {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
778 | {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
779 | {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
780 | {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
781 | {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
782 | {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
783 | {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
784 | {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
785 | {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
786 | {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
787 | {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
788 | {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
789 | {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
790 | {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
791 | {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
792 | {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, | |
793 | {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
794 | {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
795 | {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
796 | {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
797 | {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
798 | {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
799 | {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, | |
800 | {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
801 | {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
802 | {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
803 | {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
804 | {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
805 | {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, | |
806 | #endif | |
89330c39 AD |
807 | #ifdef CONFIG_DRM_AMDGPU_CIK |
808 | /* Kaveri */ | |
2f7d10b3 JZ |
809 | {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, |
810 | {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
811 | {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
812 | {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
813 | {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
814 | {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
815 | {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
816 | {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
817 | {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
818 | {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
819 | {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
820 | {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
821 | {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
822 | {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
823 | {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
824 | {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
825 | {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
826 | {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
827 | {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
828 | {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
829 | {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
830 | {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, | |
89330c39 | 831 | /* Bonaire */ |
2f7d10b3 JZ |
832 | {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, |
833 | {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
834 | {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
835 | {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, | |
89330c39 AD |
836 | {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
837 | {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
838 | {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
839 | {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
840 | {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
841 | {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, | |
fb4f1737 | 842 | {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, |
89330c39 AD |
843 | /* Hawaii */ |
844 | {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
845 | {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
846 | {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
847 | {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
848 | {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
849 | {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
850 | {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
851 | {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
852 | {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
853 | {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
854 | {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
855 | {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, | |
856 | /* Kabini */ | |
2f7d10b3 JZ |
857 | {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, |
858 | {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
859 | {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
860 | {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
861 | {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
862 | {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
863 | {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
864 | {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
865 | {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
866 | {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
867 | {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
868 | {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, | |
869 | {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
870 | {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
871 | {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
872 | {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, | |
89330c39 | 873 | /* mullins */ |
2f7d10b3 JZ |
874 | {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, |
875 | {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
876 | {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
877 | {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
878 | {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
879 | {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
880 | {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
881 | {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
882 | {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
883 | {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
884 | {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
885 | {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
886 | {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
887 | {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
888 | {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
889 | {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, | |
89330c39 | 890 | #endif |
1256a8b8 | 891 | /* topaz */ |
dba280b2 AD |
892 | {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, |
893 | {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
894 | {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
895 | {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
896 | {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, | |
1256a8b8 AD |
897 | /* tonga */ |
898 | {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
899 | {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
900 | {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
1f8d9625 | 901 | {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
1256a8b8 AD |
902 | {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
903 | {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
1f8d9625 | 904 | {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
1256a8b8 AD |
905 | {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, |
906 | {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, | |
2da78e21 DZ |
907 | /* fiji */ |
908 | {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, | |
e1d99217 | 909 | {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, |
1256a8b8 | 910 | /* carrizo */ |
2f7d10b3 JZ |
911 | {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, |
912 | {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
913 | {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
914 | {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
915 | {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, | |
81b1509a SL |
916 | /* stoney */ |
917 | {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, | |
2cc0c0b5 FC |
918 | /* Polaris11 */ |
919 | {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
35621b80 | 920 | {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 921 | {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 922 | {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
35621b80 | 923 | {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
2cc0c0b5 | 924 | {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
35621b80 FC |
925 | {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, |
926 | {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
927 | {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, | |
2cc0c0b5 FC |
928 | /* Polaris10 */ |
929 | {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
1dcf4801 FC |
930 | {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
931 | {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
932 | {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
933 | {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
7dae6181 | 934 | {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
2cc0c0b5 | 935 | {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
1dcf4801 FC |
936 | {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
937 | {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
938 | {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
939 | {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
940 | {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, | |
30f3984e | 941 | {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, |
fc8e9c54 JZ |
942 | /* Polaris12 */ |
943 | {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
944 | {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
945 | {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
946 | {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
947 | {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, | |
cf8c73af | 948 | {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
6e88491c | 949 | {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
fc8e9c54 | 950 | {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, |
e9307932 LL |
951 | /* VEGAM */ |
952 | {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, | |
953 | {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, | |
f6653a0e | 954 | {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, |
ca2f1cca | 955 | /* Vega 10 */ |
dfbf0c14 AD |
956 | {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
957 | {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
958 | {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
959 | {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
960 | {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
961 | {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
962 | {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
2244b588 AD |
963 | {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
964 | {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
965 | {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
dfbf0c14 | 966 | {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
2244b588 AD |
967 | {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
968 | {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
969 | {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, | |
dfbf0c14 | 970 | {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, |
dc53d543 AD |
971 | /* Vega 12 */ |
972 | {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
973 | {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
974 | {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
975 | {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
976 | {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, | |
1204a26e | 977 | /* Vega 20 */ |
6dddaeef AD |
978 | {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, |
979 | {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, | |
980 | {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, | |
981 | {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, | |
ec5b2020 | 982 | {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, |
6dddaeef AD |
983 | {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, |
984 | {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, | |
df515052 | 985 | /* Raven */ |
acc34503 | 986 | {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, |
741deade | 987 | {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, |
48c69cda | 988 | /* Arcturus */ |
a08a4dae AD |
989 | {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, |
990 | {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, | |
991 | {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, | |
ea207b29 | 992 | {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, |
bd1c0fdf AD |
993 | /* Navi10 */ |
994 | {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, | |
995 | {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, | |
996 | {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, | |
4f56d9d4 | 997 | {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
bd1c0fdf | 998 | {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
4f56d9d4 | 999 | {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
bd1c0fdf | 1000 | {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, |
26051720 | 1001 | /* Navi14 */ |
b62d9554 AD |
1002 | {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, |
1003 | {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, | |
1004 | {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, | |
1005 | {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, | |
df515052 | 1006 | |
61bdb39c | 1007 | /* Renoir */ |
23fe1390 | 1008 | {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, |
61bdb39c | 1009 | |
10e85054 | 1010 | /* Navi12 */ |
e16a7cbc | 1011 | {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT}, |
57d4f3b7 | 1012 | {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT}, |
10e85054 | 1013 | |
d38ceaf9 AD |
1014 | {0, 0, 0} |
1015 | }; | |
1016 | ||
1017 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
1018 | ||
1019 | static struct drm_driver kms_driver; | |
1020 | ||
d38ceaf9 AD |
1021 | static int amdgpu_pci_probe(struct pci_dev *pdev, |
1022 | const struct pci_device_id *ent) | |
1023 | { | |
b58c1131 | 1024 | struct drm_device *dev; |
c6385e50 | 1025 | struct amdgpu_device *adev; |
d38ceaf9 | 1026 | unsigned long flags = ent->driver_data; |
1daee8b4 | 1027 | int ret, retry = 0; |
3fa203af AD |
1028 | bool supports_atomic = false; |
1029 | ||
1030 | if (!amdgpu_virtual_display && | |
1031 | amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) | |
1032 | supports_atomic = true; | |
d38ceaf9 | 1033 | |
2f7d10b3 | 1034 | if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { |
d38ceaf9 AD |
1035 | DRM_INFO("This hardware requires experimental hardware support.\n" |
1036 | "See modparam exp_hw_support\n"); | |
1037 | return -ENODEV; | |
1038 | } | |
1039 | ||
984d7a92 HG |
1040 | #ifdef CONFIG_DRM_AMDGPU_SI |
1041 | if (!amdgpu_si_support) { | |
1042 | switch (flags & AMD_ASIC_MASK) { | |
1043 | case CHIP_TAHITI: | |
1044 | case CHIP_PITCAIRN: | |
1045 | case CHIP_VERDE: | |
1046 | case CHIP_OLAND: | |
1047 | case CHIP_HAINAN: | |
1048 | dev_info(&pdev->dev, | |
1049 | "SI support provided by radeon.\n"); | |
1050 | dev_info(&pdev->dev, | |
1051 | "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" | |
1052 | ); | |
1053 | return -ENODEV; | |
1054 | } | |
1055 | } | |
1056 | #endif | |
1057 | #ifdef CONFIG_DRM_AMDGPU_CIK | |
1058 | if (!amdgpu_cik_support) { | |
1059 | switch (flags & AMD_ASIC_MASK) { | |
1060 | case CHIP_KAVERI: | |
1061 | case CHIP_BONAIRE: | |
1062 | case CHIP_HAWAII: | |
1063 | case CHIP_KABINI: | |
1064 | case CHIP_MULLINS: | |
1065 | dev_info(&pdev->dev, | |
1066 | "CIK support provided by radeon.\n"); | |
1067 | dev_info(&pdev->dev, | |
1068 | "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" | |
1069 | ); | |
1070 | return -ENODEV; | |
1071 | } | |
1072 | } | |
1073 | #endif | |
1074 | ||
d38ceaf9 | 1075 | /* Get rid of things like offb */ |
35616a4a | 1076 | ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); |
d38ceaf9 AD |
1077 | if (ret) |
1078 | return ret; | |
1079 | ||
b58c1131 AD |
1080 | dev = drm_dev_alloc(&kms_driver, &pdev->dev); |
1081 | if (IS_ERR(dev)) | |
1082 | return PTR_ERR(dev); | |
1083 | ||
351c4dbe VS |
1084 | if (!supports_atomic) |
1085 | dev->driver_features &= ~DRIVER_ATOMIC; | |
1086 | ||
b58c1131 AD |
1087 | ret = pci_enable_device(pdev); |
1088 | if (ret) | |
1089 | goto err_free; | |
1090 | ||
1091 | dev->pdev = pdev; | |
1092 | ||
1093 | pci_set_drvdata(pdev, dev); | |
1094 | ||
c6385e50 AD |
1095 | amdgpu_driver_load_kms(dev, ent->driver_data); |
1096 | ||
1daee8b4 | 1097 | retry_init: |
b58c1131 | 1098 | ret = drm_dev_register(dev, ent->driver_data); |
1daee8b4 PD |
1099 | if (ret == -EAGAIN && ++retry <= 3) { |
1100 | DRM_INFO("retry init %d\n", retry); | |
1101 | /* Don't request EX mode too frequently which is attacking */ | |
1102 | msleep(5000); | |
1103 | goto retry_init; | |
1104 | } else if (ret) | |
b58c1131 AD |
1105 | goto err_pci; |
1106 | ||
c6385e50 AD |
1107 | adev = dev->dev_private; |
1108 | ret = amdgpu_debugfs_init(adev); | |
1109 | if (ret) | |
1110 | DRM_ERROR("Creating debugfs files failed (%d).\n", ret); | |
1111 | ||
b58c1131 AD |
1112 | return 0; |
1113 | ||
1114 | err_pci: | |
1115 | pci_disable_device(pdev); | |
1116 | err_free: | |
c3c18309 | 1117 | drm_dev_put(dev); |
b58c1131 | 1118 | return ret; |
d38ceaf9 AD |
1119 | } |
1120 | ||
1121 | static void | |
1122 | amdgpu_pci_remove(struct pci_dev *pdev) | |
1123 | { | |
1124 | struct drm_device *dev = pci_get_drvdata(pdev); | |
1125 | ||
56f074d8 CK |
1126 | #ifdef MODULE |
1127 | if (THIS_MODULE->state != MODULE_STATE_GOING) | |
1128 | #endif | |
1129 | DRM_ERROR("Hotplug removal is not supported\n"); | |
88b35d83 | 1130 | drm_dev_unplug(dev); |
c6385e50 | 1131 | amdgpu_driver_unload_kms(dev); |
fd4495e5 XY |
1132 | pci_disable_device(pdev); |
1133 | pci_set_drvdata(pdev, NULL); | |
6c26d558 | 1134 | drm_dev_put(dev); |
d38ceaf9 AD |
1135 | } |
1136 | ||
61e11306 AD |
1137 | static void |
1138 | amdgpu_pci_shutdown(struct pci_dev *pdev) | |
1139 | { | |
faefba95 AD |
1140 | struct drm_device *dev = pci_get_drvdata(pdev); |
1141 | struct amdgpu_device *adev = dev->dev_private; | |
1142 | ||
7c6e68c7 AG |
1143 | if (amdgpu_ras_intr_triggered()) |
1144 | return; | |
1145 | ||
61e11306 | 1146 | /* if we are running in a VM, make sure the device |
00ea8cba AD |
1147 | * torn down properly on reboot/shutdown. |
1148 | * unfortunately we can't detect certain | |
1149 | * hypervisors so just do this all the time. | |
61e11306 | 1150 | */ |
a3a09142 | 1151 | adev->mp1_state = PP_MP1_STATE_UNLOAD; |
cdd61df6 | 1152 | amdgpu_device_ip_suspend(adev); |
a3a09142 | 1153 | adev->mp1_state = PP_MP1_STATE_NONE; |
61e11306 AD |
1154 | } |
1155 | ||
d38ceaf9 AD |
1156 | static int amdgpu_pmops_suspend(struct device *dev) |
1157 | { | |
911d8b30 | 1158 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
74b0b157 | 1159 | |
de185019 | 1160 | return amdgpu_device_suspend(drm_dev, true); |
d38ceaf9 AD |
1161 | } |
1162 | ||
1163 | static int amdgpu_pmops_resume(struct device *dev) | |
1164 | { | |
911d8b30 | 1165 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
85e154c2 AD |
1166 | |
1167 | /* GPU comes up enabled by the bios on resume */ | |
19134317 AD |
1168 | if (amdgpu_device_supports_boco(drm_dev) || |
1169 | amdgpu_device_supports_baco(drm_dev)) { | |
85e154c2 AD |
1170 | pm_runtime_disable(dev); |
1171 | pm_runtime_set_active(dev); | |
1172 | pm_runtime_enable(dev); | |
1173 | } | |
1174 | ||
de185019 | 1175 | return amdgpu_device_resume(drm_dev, true); |
d38ceaf9 AD |
1176 | } |
1177 | ||
1178 | static int amdgpu_pmops_freeze(struct device *dev) | |
1179 | { | |
911d8b30 | 1180 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
897483d8 AD |
1181 | struct amdgpu_device *adev = drm_dev->dev_private; |
1182 | int r; | |
74b0b157 | 1183 | |
b2b6290a | 1184 | adev->in_hibernate = true; |
de185019 | 1185 | r = amdgpu_device_suspend(drm_dev, true); |
b2b6290a | 1186 | adev->in_hibernate = false; |
897483d8 AD |
1187 | if (r) |
1188 | return r; | |
1189 | return amdgpu_asic_reset(adev); | |
d38ceaf9 AD |
1190 | } |
1191 | ||
1192 | static int amdgpu_pmops_thaw(struct device *dev) | |
1193 | { | |
911d8b30 | 1194 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
74b0b157 | 1195 | |
de185019 | 1196 | return amdgpu_device_resume(drm_dev, true); |
74b0b157 | 1197 | } |
1198 | ||
1199 | static int amdgpu_pmops_poweroff(struct device *dev) | |
1200 | { | |
911d8b30 | 1201 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
74b0b157 | 1202 | |
de185019 | 1203 | return amdgpu_device_suspend(drm_dev, true); |
74b0b157 | 1204 | } |
1205 | ||
1206 | static int amdgpu_pmops_restore(struct device *dev) | |
1207 | { | |
911d8b30 | 1208 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
74b0b157 | 1209 | |
de185019 | 1210 | return amdgpu_device_resume(drm_dev, true); |
d38ceaf9 AD |
1211 | } |
1212 | ||
1213 | static int amdgpu_pmops_runtime_suspend(struct device *dev) | |
1214 | { | |
1215 | struct pci_dev *pdev = to_pci_dev(dev); | |
1216 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
6ae6c7d4 | 1217 | struct amdgpu_device *adev = drm_dev->dev_private; |
719423f6 | 1218 | int ret, i; |
d38ceaf9 | 1219 | |
6ae6c7d4 | 1220 | if (!adev->runpm) { |
d38ceaf9 AD |
1221 | pm_runtime_forbid(dev); |
1222 | return -EBUSY; | |
1223 | } | |
1224 | ||
719423f6 AD |
1225 | /* wait for all rings to drain before suspending */ |
1226 | for (i = 0; i < AMDGPU_MAX_RINGS; i++) { | |
1227 | struct amdgpu_ring *ring = adev->rings[i]; | |
1228 | if (ring && ring->sched.ready) { | |
1229 | ret = amdgpu_fence_wait_empty(ring); | |
1230 | if (ret) | |
1231 | return -EBUSY; | |
1232 | } | |
1233 | } | |
1234 | ||
f0f7ddfc | 1235 | adev->in_runpm = true; |
b97e9d47 AD |
1236 | if (amdgpu_device_supports_boco(drm_dev)) |
1237 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
d38ceaf9 | 1238 | drm_kms_helper_poll_disable(drm_dev); |
d38ceaf9 | 1239 | |
de185019 | 1240 | ret = amdgpu_device_suspend(drm_dev, false); |
70bedd68 RB |
1241 | if (ret) |
1242 | return ret; | |
1243 | ||
b97e9d47 | 1244 | if (amdgpu_device_supports_boco(drm_dev)) { |
562b49fc AD |
1245 | /* Only need to handle PCI state in the driver for ATPX |
1246 | * PCI core handles it for _PR3. | |
1247 | */ | |
1248 | if (amdgpu_is_atpx_hybrid()) { | |
1249 | pci_ignore_hotplug(pdev); | |
1250 | } else { | |
1251 | pci_save_state(pdev); | |
1252 | pci_disable_device(pdev); | |
1253 | pci_ignore_hotplug(pdev); | |
b97e9d47 | 1254 | pci_set_power_state(pdev, PCI_D3cold); |
562b49fc | 1255 | } |
b97e9d47 | 1256 | drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; |
19134317 AD |
1257 | } else if (amdgpu_device_supports_baco(drm_dev)) { |
1258 | amdgpu_device_baco_enter(drm_dev); | |
b97e9d47 | 1259 | } |
d38ceaf9 AD |
1260 | |
1261 | return 0; | |
1262 | } | |
1263 | ||
1264 | static int amdgpu_pmops_runtime_resume(struct device *dev) | |
1265 | { | |
1266 | struct pci_dev *pdev = to_pci_dev(dev); | |
1267 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
6ae6c7d4 | 1268 | struct amdgpu_device *adev = drm_dev->dev_private; |
d38ceaf9 AD |
1269 | int ret; |
1270 | ||
6ae6c7d4 | 1271 | if (!adev->runpm) |
d38ceaf9 AD |
1272 | return -EINVAL; |
1273 | ||
b97e9d47 AD |
1274 | if (amdgpu_device_supports_boco(drm_dev)) { |
1275 | drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; | |
1276 | ||
562b49fc AD |
1277 | /* Only need to handle PCI state in the driver for ATPX |
1278 | * PCI core handles it for _PR3. | |
1279 | */ | |
1280 | if (amdgpu_is_atpx_hybrid()) { | |
1281 | pci_set_master(pdev); | |
1282 | } else { | |
b97e9d47 | 1283 | pci_set_power_state(pdev, PCI_D0); |
562b49fc AD |
1284 | pci_restore_state(pdev); |
1285 | ret = pci_enable_device(pdev); | |
1286 | if (ret) | |
1287 | return ret; | |
1288 | pci_set_master(pdev); | |
1289 | } | |
19134317 AD |
1290 | } else if (amdgpu_device_supports_baco(drm_dev)) { |
1291 | amdgpu_device_baco_exit(drm_dev); | |
b97e9d47 | 1292 | } |
de185019 | 1293 | ret = amdgpu_device_resume(drm_dev, false); |
d38ceaf9 | 1294 | drm_kms_helper_poll_enable(drm_dev); |
b97e9d47 AD |
1295 | if (amdgpu_device_supports_boco(drm_dev)) |
1296 | drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; | |
f0f7ddfc | 1297 | adev->in_runpm = false; |
d38ceaf9 AD |
1298 | return 0; |
1299 | } | |
1300 | ||
1301 | static int amdgpu_pmops_runtime_idle(struct device *dev) | |
1302 | { | |
911d8b30 | 1303 | struct drm_device *drm_dev = dev_get_drvdata(dev); |
6ae6c7d4 | 1304 | struct amdgpu_device *adev = drm_dev->dev_private; |
97f6a21b AG |
1305 | /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ |
1306 | int ret = 1; | |
d38ceaf9 | 1307 | |
6ae6c7d4 | 1308 | if (!adev->runpm) { |
d38ceaf9 AD |
1309 | pm_runtime_forbid(dev); |
1310 | return -EBUSY; | |
1311 | } | |
1312 | ||
97f6a21b AG |
1313 | if (amdgpu_device_has_dc_support(adev)) { |
1314 | struct drm_crtc *crtc; | |
1315 | ||
1316 | drm_modeset_lock_all(drm_dev); | |
1317 | ||
1318 | drm_for_each_crtc(crtc, drm_dev) { | |
1319 | if (crtc->state->active) { | |
1320 | ret = -EBUSY; | |
1321 | break; | |
1322 | } | |
d38ceaf9 | 1323 | } |
97f6a21b AG |
1324 | |
1325 | drm_modeset_unlock_all(drm_dev); | |
1326 | ||
1327 | } else { | |
1328 | struct drm_connector *list_connector; | |
1329 | struct drm_connector_list_iter iter; | |
1330 | ||
1331 | mutex_lock(&drm_dev->mode_config.mutex); | |
1332 | drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); | |
1333 | ||
1334 | drm_connector_list_iter_begin(drm_dev, &iter); | |
1335 | drm_for_each_connector_iter(list_connector, &iter) { | |
1336 | if (list_connector->dpms == DRM_MODE_DPMS_ON) { | |
1337 | ret = -EBUSY; | |
1338 | break; | |
1339 | } | |
1340 | } | |
1341 | ||
1342 | drm_connector_list_iter_end(&iter); | |
1343 | ||
1344 | drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); | |
1345 | mutex_unlock(&drm_dev->mode_config.mutex); | |
d38ceaf9 AD |
1346 | } |
1347 | ||
97f6a21b AG |
1348 | if (ret == -EBUSY) |
1349 | DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); | |
1350 | ||
d38ceaf9 AD |
1351 | pm_runtime_mark_last_busy(dev); |
1352 | pm_runtime_autosuspend(dev); | |
97f6a21b | 1353 | return ret; |
d38ceaf9 AD |
1354 | } |
1355 | ||
1356 | long amdgpu_drm_ioctl(struct file *filp, | |
1357 | unsigned int cmd, unsigned long arg) | |
1358 | { | |
1359 | struct drm_file *file_priv = filp->private_data; | |
1360 | struct drm_device *dev; | |
1361 | long ret; | |
1362 | dev = file_priv->minor->dev; | |
1363 | ret = pm_runtime_get_sync(dev->dev); | |
1364 | if (ret < 0) | |
1365 | return ret; | |
1366 | ||
1367 | ret = drm_ioctl(filp, cmd, arg); | |
1368 | ||
1369 | pm_runtime_mark_last_busy(dev->dev); | |
1370 | pm_runtime_put_autosuspend(dev->dev); | |
1371 | return ret; | |
1372 | } | |
1373 | ||
1374 | static const struct dev_pm_ops amdgpu_pm_ops = { | |
1375 | .suspend = amdgpu_pmops_suspend, | |
1376 | .resume = amdgpu_pmops_resume, | |
1377 | .freeze = amdgpu_pmops_freeze, | |
1378 | .thaw = amdgpu_pmops_thaw, | |
74b0b157 | 1379 | .poweroff = amdgpu_pmops_poweroff, |
1380 | .restore = amdgpu_pmops_restore, | |
d38ceaf9 AD |
1381 | .runtime_suspend = amdgpu_pmops_runtime_suspend, |
1382 | .runtime_resume = amdgpu_pmops_runtime_resume, | |
1383 | .runtime_idle = amdgpu_pmops_runtime_idle, | |
1384 | }; | |
1385 | ||
48ad368a AG |
1386 | static int amdgpu_flush(struct file *f, fl_owner_t id) |
1387 | { | |
1388 | struct drm_file *file_priv = f->private_data; | |
1389 | struct amdgpu_fpriv *fpriv = file_priv->driver_priv; | |
56753e73 | 1390 | long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; |
48ad368a | 1391 | |
56753e73 CK |
1392 | timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); |
1393 | timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); | |
48ad368a | 1394 | |
56753e73 | 1395 | return timeout >= 0 ? 0 : timeout; |
48ad368a AG |
1396 | } |
1397 | ||
d38ceaf9 AD |
1398 | static const struct file_operations amdgpu_driver_kms_fops = { |
1399 | .owner = THIS_MODULE, | |
1400 | .open = drm_open, | |
48ad368a | 1401 | .flush = amdgpu_flush, |
d38ceaf9 AD |
1402 | .release = drm_release, |
1403 | .unlocked_ioctl = amdgpu_drm_ioctl, | |
1404 | .mmap = amdgpu_mmap, | |
1405 | .poll = drm_poll, | |
1406 | .read = drm_read, | |
1407 | #ifdef CONFIG_COMPAT | |
1408 | .compat_ioctl = amdgpu_kms_compat_ioctl, | |
1409 | #endif | |
1410 | }; | |
1411 | ||
021830d2 BN |
1412 | int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) |
1413 | { | |
1414 | struct drm_file *file; | |
1415 | ||
1416 | if (!filp) | |
1417 | return -EINVAL; | |
1418 | ||
1419 | if (filp->f_op != &amdgpu_driver_kms_fops) { | |
1420 | return -EINVAL; | |
1421 | } | |
1422 | ||
1423 | file = filp->private_data; | |
1424 | *fpriv = file->driver_priv; | |
1425 | return 0; | |
1426 | } | |
1427 | ||
d38ceaf9 AD |
1428 | static struct drm_driver kms_driver = { |
1429 | .driver_features = | |
f3ed6739 | 1430 | DRIVER_ATOMIC | |
1ff49481 | 1431 | DRIVER_GEM | |
db4ff423 CZ |
1432 | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | |
1433 | DRIVER_SYNCOBJ_TIMELINE, | |
d38ceaf9 | 1434 | .open = amdgpu_driver_open_kms, |
d38ceaf9 AD |
1435 | .postclose = amdgpu_driver_postclose_kms, |
1436 | .lastclose = amdgpu_driver_lastclose_kms, | |
d38ceaf9 AD |
1437 | .irq_handler = amdgpu_irq_handler, |
1438 | .ioctls = amdgpu_ioctls_kms, | |
e7294dee | 1439 | .gem_free_object_unlocked = amdgpu_gem_object_free, |
d38ceaf9 AD |
1440 | .gem_open_object = amdgpu_gem_object_open, |
1441 | .gem_close_object = amdgpu_gem_object_close, | |
1442 | .dumb_create = amdgpu_mode_dumb_create, | |
1443 | .dumb_map_offset = amdgpu_mode_dumb_mmap, | |
d38ceaf9 AD |
1444 | .fops = &amdgpu_driver_kms_fops, |
1445 | ||
1446 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, | |
1447 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, | |
1448 | .gem_prime_export = amdgpu_gem_prime_export, | |
09052fc3 | 1449 | .gem_prime_import = amdgpu_gem_prime_import, |
d38ceaf9 AD |
1450 | .gem_prime_vmap = amdgpu_gem_prime_vmap, |
1451 | .gem_prime_vunmap = amdgpu_gem_prime_vunmap, | |
dfced2e4 | 1452 | .gem_prime_mmap = amdgpu_gem_prime_mmap, |
d38ceaf9 AD |
1453 | |
1454 | .name = DRIVER_NAME, | |
1455 | .desc = DRIVER_DESC, | |
1456 | .date = DRIVER_DATE, | |
1457 | .major = KMS_DRIVER_MAJOR, | |
1458 | .minor = KMS_DRIVER_MINOR, | |
1459 | .patchlevel = KMS_DRIVER_PATCHLEVEL, | |
1460 | }; | |
1461 | ||
d38ceaf9 AD |
1462 | static struct pci_driver amdgpu_kms_pci_driver = { |
1463 | .name = DRIVER_NAME, | |
1464 | .id_table = pciidlist, | |
1465 | .probe = amdgpu_pci_probe, | |
1466 | .remove = amdgpu_pci_remove, | |
61e11306 | 1467 | .shutdown = amdgpu_pci_shutdown, |
d38ceaf9 AD |
1468 | .driver.pm = &amdgpu_pm_ops, |
1469 | }; | |
1470 | ||
d573de2d RZ |
1471 | |
1472 | ||
d38ceaf9 AD |
1473 | static int __init amdgpu_init(void) |
1474 | { | |
245ae5e9 CK |
1475 | int r; |
1476 | ||
c60e22f7 TI |
1477 | if (vgacon_text_force()) { |
1478 | DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); | |
1479 | return -EINVAL; | |
1480 | } | |
1481 | ||
245ae5e9 CK |
1482 | r = amdgpu_sync_init(); |
1483 | if (r) | |
1484 | goto error_sync; | |
1485 | ||
1486 | r = amdgpu_fence_slab_init(); | |
1487 | if (r) | |
1488 | goto error_fence; | |
1489 | ||
d38ceaf9 | 1490 | DRM_INFO("amdgpu kernel modesetting enabled.\n"); |
448d1051 | 1491 | kms_driver.num_ioctls = amdgpu_max_kms_ioctl; |
d38ceaf9 | 1492 | amdgpu_register_atpx_handler(); |
03a1c08d FK |
1493 | |
1494 | /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ | |
1495 | amdgpu_amdkfd_init(); | |
1496 | ||
d38ceaf9 | 1497 | /* let modprobe override vga console setting */ |
448d1051 | 1498 | return pci_register_driver(&amdgpu_kms_pci_driver); |
245ae5e9 | 1499 | |
245ae5e9 CK |
1500 | error_fence: |
1501 | amdgpu_sync_fini(); | |
1502 | ||
1503 | error_sync: | |
1504 | return r; | |
d38ceaf9 AD |
1505 | } |
1506 | ||
1507 | static void __exit amdgpu_exit(void) | |
1508 | { | |
130e0371 | 1509 | amdgpu_amdkfd_fini(); |
448d1051 | 1510 | pci_unregister_driver(&amdgpu_kms_pci_driver); |
d38ceaf9 | 1511 | amdgpu_unregister_atpx_handler(); |
257bf15a | 1512 | amdgpu_sync_fini(); |
d573de2d | 1513 | amdgpu_fence_slab_fini(); |
c7d8b782 | 1514 | mmu_notifier_synchronize(); |
d38ceaf9 AD |
1515 | } |
1516 | ||
1517 | module_init(amdgpu_init); | |
1518 | module_exit(amdgpu_exit); | |
1519 | ||
1520 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
1521 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1522 | MODULE_LICENSE("GPL and additional rights"); |