[thirdparty/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_fb.c

/*
 * Copyright © 2007 David Airlie
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *     David Airlie
 */

#include <linux/module.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/vga_switcheroo.h>

#include <drm/amdgpu_drm.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/drm_fourcc.h>

#include "amdgpu.h"
#include "cikd.h"
#include "amdgpu_gem.h"

#include "amdgpu_display.h"

/* object hierarchy -
   this contains a helper + a amdgpu fb
   the helper contains a pointer to amdgpu framebuffer baseclass.
*/

static int
amdgpufb_open(struct fb_info *info, int user)
{
	struct drm_fb_helper *fb_helper = info->par;
	int ret = pm_runtime_get_sync(fb_helper->dev->dev);
	if (ret < 0 && ret != -EACCES) {
		pm_runtime_mark_last_busy(fb_helper->dev->dev);
		pm_runtime_put_autosuspend(fb_helper->dev->dev);
		return ret;
	}
	return 0;
}

static int
amdgpufb_release(struct fb_info *info, int user)
{
	struct drm_fb_helper *fb_helper = info->par;

	pm_runtime_mark_last_busy(fb_helper->dev->dev);
	pm_runtime_put_autosuspend(fb_helper->dev->dev);
	return 0;
}

static const struct fb_ops amdgpufb_ops = {
	.owner = THIS_MODULE,
	DRM_FB_HELPER_DEFAULT_OPS,
	.fb_open = amdgpufb_open,
	.fb_release = amdgpufb_release,
	.fb_fillrect = drm_fb_helper_cfb_fillrect,
	.fb_copyarea = drm_fb_helper_cfb_copyarea,
	.fb_imageblit = drm_fb_helper_cfb_imageblit,
};


int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
{
	int aligned = width;
	int pitch_mask = 0;

	switch (cpp) {
	case 1:
		pitch_mask = 255;
		break;
	case 2:
		pitch_mask = 127;
		break;
	case 3:
	case 4:
		pitch_mask = 63;
		break;
	}

	aligned += pitch_mask;
	aligned &= ~pitch_mask;
	return aligned * cpp;
}

static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
{
	struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
	int ret;

	ret = amdgpu_bo_reserve(abo, true);
	if (likely(ret == 0)) {
		amdgpu_bo_kunmap(abo);
		amdgpu_bo_unpin(abo);
		amdgpu_bo_unreserve(abo);
	}
	drm_gem_object_put_unlocked(gobj);
}

static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
					 struct drm_mode_fb_cmd2 *mode_cmd,
					 struct drm_gem_object **gobj_p)
{
	const struct drm_format_info *info;
	struct amdgpu_device *adev = rfbdev->adev;
	struct drm_gem_object *gobj = NULL;
	struct amdgpu_bo *abo = NULL;
	bool fb_tiled = false; /* useful for testing */
	u32 tiling_flags = 0, domain;
	int ret;
	int aligned_size, size;
	int height = mode_cmd->height;
	u32 cpp;
	u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
			       AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS     |
			       AMDGPU_GEM_CREATE_VRAM_CLEARED;

	info = drm_get_format_info(adev->ddev, mode_cmd);
	cpp = info->cpp[0];

	/* need to align pitch with crtc limits */
	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
						  fb_tiled);
	domain = amdgpu_display_supported_domains(adev, flags);
	height = ALIGN(mode_cmd->height, 8);
	size = mode_cmd->pitches[0] * height;
	aligned_size = ALIGN(size, PAGE_SIZE);
	ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags,
				       ttm_bo_type_kernel, NULL, &gobj);
	if (ret) {
		pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
		return -ENOMEM;
	}
	abo = gem_to_amdgpu_bo(gobj);

	if (fb_tiled)
		tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);

	ret = amdgpu_bo_reserve(abo, false);
	if (unlikely(ret != 0))
		goto out_unref;

	if (tiling_flags) {
		ret = amdgpu_bo_set_tiling_flags(abo,
						 tiling_flags);
		if (ret)
			dev_err(adev->dev, "FB failed to set tiling flags\n");
	}

	ret = amdgpu_bo_pin(abo, domain);
	if (ret) {
		amdgpu_bo_unreserve(abo);
		goto out_unref;
	}

	ret = amdgpu_ttm_alloc_gart(&abo->tbo);
	if (ret) {
		amdgpu_bo_unreserve(abo);
		dev_err(adev->dev, "%p bind failed\n", abo);
		goto out_unref;
	}

	ret = amdgpu_bo_kmap(abo, NULL);
	amdgpu_bo_unreserve(abo);
	if (ret) {
		goto out_unref;
	}

	*gobj_p = gobj;
	return 0;
out_unref:
	amdgpufb_destroy_pinned_object(gobj);
	*gobj_p = NULL;
	return ret;
}

static int amdgpufb_create(struct drm_fb_helper *helper,
			   struct drm_fb_helper_surface_size *sizes)
{
	struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper;
	struct amdgpu_device *adev = rfbdev->adev;
	struct fb_info *info;
	struct drm_framebuffer *fb = NULL;
	struct drm_mode_fb_cmd2 mode_cmd;
	struct drm_gem_object *gobj = NULL;
	struct amdgpu_bo *abo = NULL;
	int ret;
	unsigned long tmp;

	mode_cmd.width = sizes->surface_width;
	mode_cmd.height = sizes->surface_height;

	if (sizes->surface_bpp == 24)
		sizes->surface_bpp = 32;

	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
							  sizes->surface_depth);

	ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	if (ret) {
		DRM_ERROR("failed to create fbcon object %d\n", ret);
		return ret;
	}

	abo = gem_to_amdgpu_bo(gobj);

	/* okay we have an object now allocate the framebuffer */
	info = drm_fb_helper_alloc_fbi(helper);
	if (IS_ERR(info)) {
		ret = PTR_ERR(info);
		goto out;
	}

	ret = amdgpu_display_framebuffer_init(adev->ddev, &rfbdev->rfb,
					      &mode_cmd, gobj);
	if (ret) {
		DRM_ERROR("failed to initialize framebuffer %d\n", ret);
		goto out;
	}

	fb = &rfbdev->rfb.base;

	/* setup helper */
	rfbdev->helper.fb = fb;

	info->fbops = &amdgpufb_ops;

	tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
	info->fix.smem_start = adev->gmc.aper_base + tmp;
	info->fix.smem_len = amdgpu_bo_size(abo);
	info->screen_base = amdgpu_bo_kptr(abo);
	info->screen_size = amdgpu_bo_size(abo);

	drm_fb_helper_fill_info(info, &rfbdev->helper, sizes);

	/* setup aperture base/size for vesafb takeover */
	info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
	info->apertures->ranges[0].size = adev->gmc.aper_size;

	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */

	if (info->screen_base == NULL) {
		ret = -ENOSPC;
		goto out;
	}

	DRM_INFO("fb mappable at 0x%lX\n",  info->fix.smem_start);
	DRM_INFO("vram apper at 0x%lX\n",  (unsigned long)adev->gmc.aper_base);
	DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
	DRM_INFO("fb depth is %d\n", fb->format->depth);
	DRM_INFO("   pitch is %d\n", fb->pitches[0]);

	vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
	return 0;

out:
	if (abo) {

	}
	if (fb && ret) {
		drm_gem_object_put_unlocked(gobj);
		drm_framebuffer_unregister_private(fb);
		drm_framebuffer_cleanup(fb);
		kfree(fb);
	}
	return ret;
}

static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev)
{
	struct amdgpu_framebuffer *rfb = &rfbdev->rfb;

	drm_fb_helper_unregister_fbi(&rfbdev->helper);

	if (rfb->base.obj[0]) {
		amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
		rfb->base.obj[0] = NULL;
		drm_framebuffer_unregister_private(&rfb->base);
		drm_framebuffer_cleanup(&rfb->base);
	}
	drm_fb_helper_fini(&rfbdev->helper);

	return 0;
}

static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
	.fb_probe = amdgpufb_create,
};

int amdgpu_fbdev_init(struct amdgpu_device *adev)
{
	struct amdgpu_fbdev *rfbdev;
	int bpp_sel = 32;
	int ret;

	/* don't init fbdev on hw without DCE */
	if (!adev->mode_info.mode_config_initialized)
		return 0;

	/* don't init fbdev if there are no connectors */
	if (list_empty(&adev->ddev->mode_config.connector_list))
		return 0;

	/* select 8 bpp console on low vram cards */
	if (adev->gmc.real_vram_size <= (32*1024*1024))
		bpp_sel = 8;

	rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
	if (!rfbdev)
		return -ENOMEM;

	rfbdev->adev = adev;
	adev->mode_info.rfbdev = rfbdev;

	drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
			&amdgpu_fb_helper_funcs);

	ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper);
	if (ret) {
		kfree(rfbdev);
		return ret;
	}

	/* disable all the possible outputs/crtcs before entering KMS mode */
	if (!amdgpu_device_has_dc_support(adev))
		drm_helper_disable_unused_functions(adev->ddev);

	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	return 0;
}

void amdgpu_fbdev_fini(struct amdgpu_device *adev)
{
	if (!adev->mode_info.rfbdev)
		return;

	amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
	kfree(adev->mode_info.rfbdev);
	adev->mode_info.rfbdev = NULL;
}

void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
{
	if (adev->mode_info.rfbdev)
		drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper,
						   state);
}

int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
{
	struct amdgpu_bo *robj;
	int size = 0;

	if (!adev->mode_info.rfbdev)
		return 0;

	robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]);
	size += amdgpu_bo_size(robj);
	return size;
}

bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj)
{
	if (!adev->mode_info.rfbdev)
		return false;
	if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]))
		return true;
	return false;
}
Commit	Line	Data
d38ceaf9 AD	1	/*
	2	* Copyright © 2007 David Airlie
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	21	* DEALINGS IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* David Airlie
	25	*/
fdf2f6c5	26
d38ceaf9	27	#include <linux/module.h>
7c1fa1db	28	#include <linux/pm_runtime.h>
fdf2f6c5 SR	29	#include <linux/slab.h>
fdf2f6c5 SR	30	#include <linux/vga_switcheroo.h>
d38ceaf9	31
fdf2f6c5	32	#include <drm/amdgpu_drm.h>
d38ceaf9 AD	33	#include <drm/drm_crtc.h>
d38ceaf9 AD	34	#include <drm/drm_crtc_helper.h>
fdf2f6c5 SR	35	#include <drm/drm_fb_helper.h>
	36	#include <drm/drm_fourcc.h>
	37
d38ceaf9	38	#include "amdgpu.h"
fbd76d59	39	#include "cikd.h"
2cddc50e	40	#include "amdgpu_gem.h"
d38ceaf9	41
5d43be0c CK	42	#include "amdgpu_display.h"
5d43be0c CK	43
d38ceaf9 AD	44	/* object hierarchy -
	45	this contains a helper + a amdgpu fb
	46	the helper contains a pointer to amdgpu framebuffer baseclass.
	47	*/
d38ceaf9	48
7c1fa1db AD	49	static int
	50	amdgpufb_open(struct fb_info *info, int user)
	51	{
bb1c08f9 DV	52	struct drm_fb_helper *fb_helper = info->par;
bb1c08f9 DV	53	int ret = pm_runtime_get_sync(fb_helper->dev->dev);
7c1fa1db	54	if (ret < 0 && ret != -EACCES) {
bb1c08f9 DV	55	pm_runtime_mark_last_busy(fb_helper->dev->dev);
bb1c08f9 DV	56	pm_runtime_put_autosuspend(fb_helper->dev->dev);
7c1fa1db AD	57	return ret;
	58	}
	59	return 0;
	60	}
	61
	62	static int
	63	amdgpufb_release(struct fb_info *info, int user)
	64	{
bb1c08f9	65	struct drm_fb_helper *fb_helper = info->par;
7c1fa1db	66
bb1c08f9 DV	67	pm_runtime_mark_last_busy(fb_helper->dev->dev);
bb1c08f9 DV	68	pm_runtime_put_autosuspend(fb_helper->dev->dev);
7c1fa1db AD	69	return 0;
	70	}
	71
b6ff753a	72	static const struct fb_ops amdgpufb_ops = {
d38ceaf9	73	.owner = THIS_MODULE,
ea4ffffe	74	DRM_FB_HELPER_DEFAULT_OPS,
7c1fa1db AD	75	.fb_open = amdgpufb_open,
7c1fa1db AD	76	.fb_release = amdgpufb_release,
2dbaf392 AT	77	.fb_fillrect = drm_fb_helper_cfb_fillrect,
	78	.fb_copyarea = drm_fb_helper_cfb_copyarea,
	79	.fb_imageblit = drm_fb_helper_cfb_imageblit,
d38ceaf9 AD	80	};
	81
	82
8e911ab7	83	int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled)
d38ceaf9 AD	84	{
	85	int aligned = width;
	86	int pitch_mask = 0;
	87
8e911ab7	88	switch (cpp) {
d38ceaf9 AD	89	case 1:
	90	pitch_mask = 255;
	91	break;
	92	case 2:
	93	pitch_mask = 127;
	94	break;
	95	case 3:
	96	case 4:
	97	pitch_mask = 63;
	98	break;
	99	}
	100
	101	aligned += pitch_mask;
	102	aligned &= ~pitch_mask;
8e911ab7	103	return aligned * cpp;
d38ceaf9 AD	104	}
	105
	106	static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj)
	107	{
765e7fbf	108	struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
d38ceaf9 AD	109	int ret;
d38ceaf9 AD	110
c81a1a74	111	ret = amdgpu_bo_reserve(abo, true);
d38ceaf9	112	if (likely(ret == 0)) {
765e7fbf CK	113	amdgpu_bo_kunmap(abo);
	114	amdgpu_bo_unpin(abo);
	115	amdgpu_bo_unreserve(abo);
d38ceaf9	116	}
f62facc2	117	drm_gem_object_put_unlocked(gobj);
d38ceaf9 AD	118	}
	119
	120	static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
	121	struct drm_mode_fb_cmd2 *mode_cmd,
	122	struct drm_gem_object **gobj_p)
	123	{
92f08076	124	const struct drm_format_info *info;
d38ceaf9 AD	125	struct amdgpu_device *adev = rfbdev->adev;
d38ceaf9 AD	126	struct drm_gem_object *gobj = NULL;
765e7fbf	127	struct amdgpu_bo *abo = NULL;
d38ceaf9	128	bool fb_tiled = false; /* useful for testing */
5d43be0c	129	u32 tiling_flags = 0, domain;
d38ceaf9 AD	130	int ret;
	131	int aligned_size, size;
	132	int height = mode_cmd->height;
8e911ab7	133	u32 cpp;
f2bd8a0e AG	134	u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED \|
f2bd8a0e AG	135	AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS \|
a6aacb2b	136	AMDGPU_GEM_CREATE_VRAM_CLEARED;
d38ceaf9	137
92f08076	138	info = drm_get_format_info(adev->ddev, mode_cmd);
b0f986b4	139	cpp = info->cpp[0];
d38ceaf9 AD	140
d38ceaf9 AD	141	/* need to align pitch with crtc limits */
8e911ab7 LP	142	mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
8e911ab7 LP	143	fb_tiled);
f2bd8a0e	144	domain = amdgpu_display_supported_domains(adev, flags);
d38ceaf9 AD	145	height = ALIGN(mode_cmd->height, 8);
	146	size = mode_cmd->pitches[0] * height;
	147	aligned_size = ALIGN(size, PAGE_SIZE);
f2bd8a0e	148	ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags,
f8ddb39a	149	ttm_bo_type_kernel, NULL, &gobj);
d38ceaf9	150	if (ret) {
7ca85295	151	pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
d38ceaf9 AD	152	return -ENOMEM;
d38ceaf9 AD	153	}
765e7fbf	154	abo = gem_to_amdgpu_bo(gobj);
d38ceaf9 AD	155
d38ceaf9 AD	156	if (fb_tiled)
fbd76d59	157	tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
d38ceaf9	158
765e7fbf	159	ret = amdgpu_bo_reserve(abo, false);
d38ceaf9 AD	160	if (unlikely(ret != 0))
	161	goto out_unref;
	162
	163	if (tiling_flags) {
765e7fbf	164	ret = amdgpu_bo_set_tiling_flags(abo,
63ab1c2b	165	tiling_flags);
d38ceaf9 AD	166	if (ret)
	167	dev_err(adev->dev, "FB failed to set tiling flags\n");
	168	}
	169
7b7c6c81	170	ret = amdgpu_bo_pin(abo, domain);
d38ceaf9	171	if (ret) {
765e7fbf	172	amdgpu_bo_unreserve(abo);
d38ceaf9 AD	173	goto out_unref;
d38ceaf9 AD	174	}
bb812f1e JZ	175
	176	ret = amdgpu_ttm_alloc_gart(&abo->tbo);
	177	if (ret) {
	178	amdgpu_bo_unreserve(abo);
	179	dev_err(adev->dev, "%p bind failed\n", abo);
	180	goto out_unref;
	181	}
	182
765e7fbf CK	183	ret = amdgpu_bo_kmap(abo, NULL);
765e7fbf CK	184	amdgpu_bo_unreserve(abo);
d38ceaf9 AD	185	if (ret) {
	186	goto out_unref;
	187	}
	188
	189	*gobj_p = gobj;
	190	return 0;
	191	out_unref:
	192	amdgpufb_destroy_pinned_object(gobj);
	193	*gobj_p = NULL;
	194	return ret;
	195	}
	196
	197	static int amdgpufb_create(struct drm_fb_helper *helper,
	198	struct drm_fb_helper_surface_size *sizes)
	199	{
	200	struct amdgpu_fbdev rfbdev = (struct amdgpu_fbdev )helper;
	201	struct amdgpu_device *adev = rfbdev->adev;
	202	struct fb_info *info;
	203	struct drm_framebuffer *fb = NULL;
	204	struct drm_mode_fb_cmd2 mode_cmd;
	205	struct drm_gem_object *gobj = NULL;
765e7fbf	206	struct amdgpu_bo *abo = NULL;
d38ceaf9 AD	207	int ret;
	208	unsigned long tmp;
	209
	210	mode_cmd.width = sizes->surface_width;
	211	mode_cmd.height = sizes->surface_height;
	212
	213	if (sizes->surface_bpp == 24)
	214	sizes->surface_bpp = 32;
	215
	216	mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
	217	sizes->surface_depth);
	218
	219	ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
	220	if (ret) {
	221	DRM_ERROR("failed to create fbcon object %d\n", ret);
	222	return ret;
	223	}
	224
765e7fbf	225	abo = gem_to_amdgpu_bo(gobj);
d38ceaf9 AD	226
d38ceaf9 AD	227	/* okay we have an object now allocate the framebuffer */
2dbaf392 AT	228	info = drm_fb_helper_alloc_fbi(helper);
	229	if (IS_ERR(info)) {
	230	ret = PTR_ERR(info);
da7bdda2	231	goto out;
d38ceaf9 AD	232	}
d38ceaf9 AD	233
9da3f2d9 SL	234	ret = amdgpu_display_framebuffer_init(adev->ddev, &rfbdev->rfb,
9da3f2d9 SL	235	&mode_cmd, gobj);
d38ceaf9 AD	236	if (ret) {
d38ceaf9 AD	237	DRM_ERROR("failed to initialize framebuffer %d\n", ret);
da7bdda2	238	goto out;
d38ceaf9 AD	239	}
	240
	241	fb = &rfbdev->rfb.base;
	242
	243	/* setup helper */
	244	rfbdev->helper.fb = fb;
d38ceaf9	245
d38ceaf9 AD	246	info->fbops = &amdgpufb_ops;
d38ceaf9 AD	247
770d13b1 CK	248	tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
770d13b1 CK	249	info->fix.smem_start = adev->gmc.aper_base + tmp;
765e7fbf	250	info->fix.smem_len = amdgpu_bo_size(abo);
f5e1c740	251	info->screen_base = amdgpu_bo_kptr(abo);
765e7fbf	252	info->screen_size = amdgpu_bo_size(abo);
d38ceaf9	253
bb1c08f9	254	drm_fb_helper_fill_info(info, &rfbdev->helper, sizes);
d38ceaf9 AD	255
d38ceaf9 AD	256	/* setup aperture base/size for vesafb takeover */
d38ceaf9	257	info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
770d13b1	258	info->apertures->ranges[0].size = adev->gmc.aper_size;
d38ceaf9 AD	259
	260	/* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
	261
	262	if (info->screen_base == NULL) {
	263	ret = -ENOSPC;
da7bdda2	264	goto out;
d38ceaf9 AD	265	}
	266
	267	DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
770d13b1	268	DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base);
765e7fbf	269	DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
b00c600e	270	DRM_INFO("fb depth is %d\n", fb->format->depth);
d38ceaf9 AD	271	DRM_INFO(" pitch is %d\n", fb->pitches[0]);
	272
	273	vga_switcheroo_client_fb_set(adev->ddev->pdev, info);
	274	return 0;
	275
da7bdda2	276	out:
765e7fbf	277	if (abo) {
d38ceaf9 AD	278
	279	}
	280	if (fb && ret) {
f62facc2	281	drm_gem_object_put_unlocked(gobj);
d38ceaf9 AD	282	drm_framebuffer_unregister_private(fb);
	283	drm_framebuffer_cleanup(fb);
	284	kfree(fb);
	285	}
	286	return ret;
	287	}
	288
d38ceaf9 AD	289	static int amdgpu_fbdev_destroy(struct drm_device dev, struct amdgpu_fbdev rfbdev)
d38ceaf9 AD	290	{
d38ceaf9 AD	291	struct amdgpu_framebuffer *rfb = &rfbdev->rfb;
d38ceaf9 AD	292
2dbaf392	293	drm_fb_helper_unregister_fbi(&rfbdev->helper);
d38ceaf9	294
e68d14dd DS	295	if (rfb->base.obj[0]) {
	296	amdgpufb_destroy_pinned_object(rfb->base.obj[0]);
	297	rfb->base.obj[0] = NULL;
a072c5f8 MD	298	drm_framebuffer_unregister_private(&rfb->base);
a072c5f8 MD	299	drm_framebuffer_cleanup(&rfb->base);
d38ceaf9 AD	300	}
d38ceaf9 AD	301	drm_fb_helper_fini(&rfbdev->helper);
d38ceaf9 AD	302
	303	return 0;
	304	}
	305
d38ceaf9	306	static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
d38ceaf9 AD	307	.fb_probe = amdgpufb_create,
	308	};
	309
	310	int amdgpu_fbdev_init(struct amdgpu_device *adev)
	311	{
	312	struct amdgpu_fbdev *rfbdev;
	313	int bpp_sel = 32;
	314	int ret;
	315
	316	/* don't init fbdev on hw without DCE */
	317	if (!adev->mode_info.mode_config_initialized)
	318	return 0;
	319
f49d45c9 AD	320	/* don't init fbdev if there are no connectors */
	321	if (list_empty(&adev->ddev->mode_config.connector_list))
	322	return 0;
	323
d38ceaf9	324	/* select 8 bpp console on low vram cards */
770d13b1	325	if (adev->gmc.real_vram_size <= (3210241024))
d38ceaf9 AD	326	bpp_sel = 8;
	327
	328	rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);
	329	if (!rfbdev)
	330	return -ENOMEM;
	331
	332	rfbdev->adev = adev;
	333	adev->mode_info.rfbdev = rfbdev;
	334
	335	drm_fb_helper_prepare(adev->ddev, &rfbdev->helper,
	336	&amdgpu_fb_helper_funcs);
	337
2dea2d11	338	ret = drm_fb_helper_init(adev->ddev, &rfbdev->helper);
d38ceaf9 AD	339	if (ret) {
	340	kfree(rfbdev);
	341	return ret;
	342	}
	343
d38ceaf9	344	/* disable all the possible outputs/crtcs before entering KMS mode */
93b8ca9b AG	345	if (!amdgpu_device_has_dc_support(adev))
93b8ca9b AG	346	drm_helper_disable_unused_functions(adev->ddev);
d38ceaf9 AD	347
	348	drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel);
	349	return 0;
	350	}
	351
	352	void amdgpu_fbdev_fini(struct amdgpu_device *adev)
	353	{
	354	if (!adev->mode_info.rfbdev)
	355	return;
	356
	357	amdgpu_fbdev_destroy(adev->ddev, adev->mode_info.rfbdev);
	358	kfree(adev->mode_info.rfbdev);
	359	adev->mode_info.rfbdev = NULL;
	360	}
	361
	362	void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state)
	363	{
	364	if (adev->mode_info.rfbdev)
ecb8c503 S	365	drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper,
ecb8c503 S	366	state);
d38ceaf9 AD	367	}
	368
	369	int amdgpu_fbdev_total_size(struct amdgpu_device *adev)
	370	{
	371	struct amdgpu_bo *robj;
	372	int size = 0;
	373
	374	if (!adev->mode_info.rfbdev)
	375	return 0;
	376
e68d14dd	377	robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]);
d38ceaf9 AD	378	size += amdgpu_bo_size(robj);
	379	return size;
	380	}
	381
	382	bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device adev, struct amdgpu_bo robj)
	383	{
	384	if (!adev->mode_info.rfbdev)
	385	return false;
e68d14dd	386	if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]))
d38ceaf9 AD	387	return true;
	388	return false;
	389	}