[thirdparty/linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_mca.c

/*
 * Copyright 2021 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#include "amdgpu_ras.h"
#include "amdgpu.h"
#include "amdgpu_mca.h"

#include "umc/umc_6_7_0_offset.h"
#include "umc/umc_6_7_0_sh_mask.h"

void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,
					      uint64_t mc_status_addr,
					      unsigned long *error_count)
{
	uint64_t mc_status = RREG64_PCIE(mc_status_addr);

	if (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
	    REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
		*error_count += 1;
}

void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,
						uint64_t mc_status_addr,
						unsigned long *error_count)
{
	uint64_t mc_status = RREG64_PCIE(mc_status_addr);

	if ((REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
	    (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 ||
	    REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 ||
	    REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 ||
	    REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 ||
	    REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
		*error_count += 1;
}

void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,
				  uint64_t mc_status_addr)
{
	WREG64_PCIE(mc_status_addr, 0x0ULL);
}

void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,
				      uint64_t mc_status_addr,
				      void *ras_error_status)
{
	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;

	amdgpu_mca_query_correctable_error_count(adev, mc_status_addr, &(err_data->ce_count));
	amdgpu_mca_query_uncorrectable_error_count(adev, mc_status_addr, &(err_data->ue_count));

	amdgpu_mca_reset_error_count(adev, mc_status_addr);
}

int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev)
{
	int err;
	struct amdgpu_mca_ras_block *ras;

	if (!adev->mca.mp0.ras)
		return 0;

	ras = adev->mca.mp0.ras;

	err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
	if (err) {
		dev_err(adev->dev, "Failed to register mca.mp0 ras block!\n");
		return err;
	}

	strcpy(ras->ras_block.ras_comm.name, "mca.mp0");
	ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA;
	ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
	adev->mca.mp0.ras_if = &ras->ras_block.ras_comm;

	return 0;
}

int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev)
{
	int err;
	struct amdgpu_mca_ras_block *ras;

	if (!adev->mca.mp1.ras)
		return 0;

	ras = adev->mca.mp1.ras;

	err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
	if (err) {
		dev_err(adev->dev, "Failed to register mca.mp1 ras block!\n");
		return err;
	}

	strcpy(ras->ras_block.ras_comm.name, "mca.mp1");
	ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA;
	ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
	adev->mca.mp1.ras_if = &ras->ras_block.ras_comm;

	return 0;
}

int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev)
{
	int err;
	struct amdgpu_mca_ras_block *ras;

	if (!adev->mca.mpio.ras)
		return 0;

	ras = adev->mca.mpio.ras;

	err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
	if (err) {
		dev_err(adev->dev, "Failed to register mca.mpio ras block!\n");
		return err;
	}

	strcpy(ras->ras_block.ras_comm.name, "mca.mpio");
	ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA;
	ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
	adev->mca.mpio.ras_if = &ras->ras_block.ras_comm;

	return 0;
}

void amdgpu_mca_bank_set_init(struct mca_bank_set *mca_set)
{
	if (!mca_set)
		return;

	memset(mca_set, 0, sizeof(*mca_set));
	INIT_LIST_HEAD(&mca_set->list);
}

int amdgpu_mca_bank_set_add_entry(struct mca_bank_set *mca_set, struct mca_bank_entry *entry)
{
	struct mca_bank_node *node;

	if (!entry)
		return -EINVAL;

	node = kvzalloc(sizeof(*node), GFP_KERNEL);
	if (!node)
		return -ENOMEM;

	memcpy(&node->entry, entry, sizeof(*entry));

	INIT_LIST_HEAD(&node->node);
	list_add_tail(&node->node, &mca_set->list);

	mca_set->nr_entries++;

	return 0;
}

void amdgpu_mca_bank_set_release(struct mca_bank_set *mca_set)
{
	struct mca_bank_node *node, *tmp;

	list_for_each_entry_safe(node, tmp, &mca_set->list, node) {
		list_del(&node->node);
		kvfree(node);
	}
}

void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs)
{
	struct amdgpu_mca *mca = &adev->mca;

	mca->mca_funcs = mca_funcs;
}

int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
{
	const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;

	if (mca_funcs && mca_funcs->mca_set_debug_mode)
		return mca_funcs->mca_set_debug_mode(adev, enable);

	return -EOPNOTSUPP;
}

static void amdgpu_mca_smu_mca_bank_dump(struct amdgpu_device *adev, int idx, struct mca_bank_entry *entry)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(entry->regs); i++)
		dev_dbg(adev->dev, "mca entry[%02d].regs[%02d]=0x%016llx\n", idx, i, entry->regs[i]);
}

int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, struct ras_err_data *err_data)
{
	struct amdgpu_smuio_mcm_config_info mcm_info;
	struct mca_bank_set mca_set;
	struct mca_bank_node *node;
	struct mca_bank_entry *entry;
	uint32_t count;
	int ret, i = 0;

	amdgpu_mca_bank_set_init(&mca_set);

	ret = amdgpu_mca_smu_get_mca_set(adev, blk, type, &mca_set);
	if (ret)
		goto out_mca_release;

	list_for_each_entry(node, &mca_set.list, node) {
		entry = &node->entry;

		amdgpu_mca_smu_mca_bank_dump(adev, i++, entry);

		count = 0;
		ret = amdgpu_mca_smu_parse_mca_error_count(adev, blk, type, entry, &count);
		if (ret)
			goto out_mca_release;

		if (!count)
			continue;

		mcm_info.socket_id = entry->info.socket_id;
		mcm_info.die_id = entry->info.aid;

		if (type == AMDGPU_MCA_ERROR_TYPE_UE)
			amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, (uint64_t)count);
		else
			amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, (uint64_t)count);
	}

out_mca_release:
	amdgpu_mca_bank_set_release(&mca_set);

	return ret;
}


int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)
{
	const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;

	if (!count)
		return -EINVAL;

	if (mca_funcs && mca_funcs->mca_get_valid_mca_count)
		return mca_funcs->mca_get_valid_mca_count(adev, type, count);

	return -EOPNOTSUPP;
}

int amdgpu_mca_smu_get_mca_set_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
					    enum amdgpu_mca_error_type type, uint32_t *total)
{
	const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
	struct mca_bank_set mca_set;
	struct mca_bank_node *node;
	struct mca_bank_entry *entry;
	uint32_t count;
	int ret;

	if (!total)
		return -EINVAL;

	if (!mca_funcs)
		return -EOPNOTSUPP;

	if (!mca_funcs->mca_get_ras_mca_set || !mca_funcs->mca_get_valid_mca_count)
		return -EOPNOTSUPP;

	amdgpu_mca_bank_set_init(&mca_set);

	ret = mca_funcs->mca_get_ras_mca_set(adev, blk, type, &mca_set);
	if (ret)
		goto err_mca_set_release;

	*total = 0;
	list_for_each_entry(node, &mca_set.list, node) {
		entry = &node->entry;

		count = 0;
		ret = mca_funcs->mca_parse_mca_error_count(adev, blk, type, entry, &count);
		if (ret)
			goto err_mca_set_release;

		*total += count;
	}

err_mca_set_release:
	amdgpu_mca_bank_set_release(&mca_set);

	return ret;
}

int amdgpu_mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
					 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
{
	const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
	if (!count || !entry)
		return -EINVAL;

	if (!mca_funcs || !mca_funcs->mca_parse_mca_error_count)
		return -EOPNOTSUPP;


	return mca_funcs->mca_parse_mca_error_count(adev, blk, type, entry, count);
}

int amdgpu_mca_smu_get_mca_set(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
			       enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set)
{
	const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;

	if (!mca_set)
		return -EINVAL;

	if (!mca_funcs || !mca_funcs->mca_get_ras_mca_set)
		return -EOPNOTSUPP;

	WARN_ON(!list_empty(&mca_set->list));

	return mca_funcs->mca_get_ras_mca_set(adev, blk, type, mca_set);
}

int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
				 int idx, struct mca_bank_entry *entry)
{
	const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
	int count;

	switch (type) {
	case AMDGPU_MCA_ERROR_TYPE_UE:
		count = mca_funcs->max_ue_count;
		break;
	case AMDGPU_MCA_ERROR_TYPE_CE:
		count = mca_funcs->max_ce_count;
		break;
	default:
		return -EINVAL;
	}

	if (idx >= count)
		return -EINVAL;

	if (mca_funcs && mca_funcs->mca_get_mca_entry)
		return mca_funcs->mca_get_mca_entry(adev, type, idx, entry);

	return -EOPNOTSUPP;
}

#if defined(CONFIG_DEBUG_FS)
static int amdgpu_mca_smu_debug_mode_set(void *data, u64 val)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)data;
	int ret;

	ret = amdgpu_mca_smu_set_debug_mode(adev, val ? true : false);
	if (ret)
		return ret;

	dev_info(adev->dev, "amdgpu set smu mca debug mode %s success\n", val ? "on" : "off");

	return 0;
}

static void mca_dump_entry(struct seq_file *m, struct mca_bank_entry *entry)
{
	int i, idx = entry->idx;

	seq_printf(m, "mca entry[%d].type: %s\n", idx, entry->type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE");
	seq_printf(m, "mca entry[%d].ip: %d\n", idx, entry->ip);
	seq_printf(m, "mca entry[%d].info: socketid:%d aid:%d hwid:0x%03x mcatype:0x%04x\n",
		   idx, entry->info.socket_id, entry->info.aid, entry->info.hwid, entry->info.mcatype);

	for (i = 0; i < ARRAY_SIZE(entry->regs); i++)
		seq_printf(m, "mca entry[%d].regs[%d]: 0x%016llx\n", idx, i, entry->regs[i]);
}

static int mca_dump_show(struct seq_file *m, enum amdgpu_mca_error_type type)
{
	struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
	struct mca_bank_entry *entry;
	uint32_t count = 0;
	int i, ret;

	ret = amdgpu_mca_smu_get_valid_mca_count(adev, type, &count);
	if (ret)
		return ret;

	seq_printf(m, "amdgpu smu %s valid mca count: %d\n",
		   type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", count);

	if (!count)
		return 0;

	entry = kmalloc(sizeof(*entry), GFP_KERNEL);
	if (!entry)
		return -ENOMEM;

	for (i = 0; i < count; i++) {
		memset(entry, 0, sizeof(*entry));

		ret = amdgpu_mca_smu_get_mca_entry(adev, type, i, entry);
		if (ret)
			goto err_free_entry;

		mca_dump_entry(m, entry);
	}

err_free_entry:
	kfree(entry);

	return ret;
}

static int mca_dump_ce_show(struct seq_file *m, void *unused)
{
	return mca_dump_show(m, AMDGPU_MCA_ERROR_TYPE_CE);
}

static int mca_dump_ce_open(struct inode *inode, struct file *file)
{
	return single_open(file, mca_dump_ce_show, inode->i_private);
}

static const struct file_operations mca_ce_dump_debug_fops = {
	.owner = THIS_MODULE,
	.open = mca_dump_ce_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
};

static int mca_dump_ue_show(struct seq_file *m, void *unused)
{
	return mca_dump_show(m, AMDGPU_MCA_ERROR_TYPE_UE);
}

static int mca_dump_ue_open(struct inode *inode, struct file *file)
{
	return single_open(file, mca_dump_ue_show, inode->i_private);
}

static const struct file_operations mca_ue_dump_debug_fops = {
	.owner = THIS_MODULE,
	.open = mca_dump_ue_open,
	.read = seq_read,
	.llseek = seq_lseek,
	.release = single_release,
};

DEFINE_DEBUGFS_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n");
#endif

void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root)
{
#if defined(CONFIG_DEBUG_FS)
	if (!root || adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 6))
		return;

	debugfs_create_file("mca_debug_mode", 0200, root, adev, &mca_debug_mode_fops);
	debugfs_create_file("mca_ue_dump", 0400, root, adev, &mca_ue_dump_debug_fops);
	debugfs_create_file("mca_ce_dump", 0400, root, adev, &mca_ce_dump_debug_fops);
#endif
}
Commit	Line	Data
3907c492 JC	1	/*
	2	* Copyright 2021 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	*/
	23	#include "amdgpu_ras.h"
	24	#include "amdgpu.h"
	25	#include "amdgpu_mca.h"
	26
	27	#include "umc/umc_6_7_0_offset.h"
	28	#include "umc/umc_6_7_0_sh_mask.h"
	29
	30	void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,
	31	uint64_t mc_status_addr,
	32	unsigned long *error_count)
	33	{
640ae42e	34	uint64_t mc_status = RREG64_PCIE(mc_status_addr);
3907c492 JC	35
	36	if (REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1 &&
	37	REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, CECC) == 1)
	38	*error_count += 1;
	39	}
	40
	41	void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,
	42	uint64_t mc_status_addr,
	43	unsigned long *error_count)
	44	{
640ae42e	45	uint64_t mc_status = RREG64_PCIE(mc_status_addr);
3907c492 JC	46
	47	if ((REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&
	48	(REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Deferred) == 1 \|\|
	49	REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UECC) == 1 \|\|
	50	REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, PCC) == 1 \|\|
	51	REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, UC) == 1 \|\|
	52	REG_GET_FIELD(mc_status, MCA_UMC_UMC0_MCUMC_STATUST0, TCC) == 1))
	53	*error_count += 1;
	54	}
	55
	56	void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,
	57	uint64_t mc_status_addr)
	58	{
640ae42e	59	WREG64_PCIE(mc_status_addr, 0x0ULL);
3907c492 JC	60	}
	61
	62	void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,
	63	uint64_t mc_status_addr,
	64	void *ras_error_status)
	65	{
	66	struct ras_err_data err_data = (struct ras_err_data )ras_error_status;
	67
	68	amdgpu_mca_query_correctable_error_count(adev, mc_status_addr, &(err_data->ce_count));
	69	amdgpu_mca_query_uncorrectable_error_count(adev, mc_status_addr, &(err_data->ue_count));
	70
	71	amdgpu_mca_reset_error_count(adev, mc_status_addr);
	72	}
7f544c54 HZ	73
	74	int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev)
	75	{
	76	int err;
	77	struct amdgpu_mca_ras_block *ras;
	78
	79	if (!adev->mca.mp0.ras)
	80	return 0;
	81
	82	ras = adev->mca.mp0.ras;
	83
	84	err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
	85	if (err) {
	86	dev_err(adev->dev, "Failed to register mca.mp0 ras block!\n");
	87	return err;
	88	}
	89
	90	strcpy(ras->ras_block.ras_comm.name, "mca.mp0");
	91	ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA;
	92	ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
	93	adev->mca.mp0.ras_if = &ras->ras_block.ras_comm;
	94
	95	return 0;
	96	}
	97
	98	int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev)
	99	{
	100	int err;
	101	struct amdgpu_mca_ras_block *ras;
	102
	103	if (!adev->mca.mp1.ras)
	104	return 0;
	105
	106	ras = adev->mca.mp1.ras;
	107
	108	err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
	109	if (err) {
	110	dev_err(adev->dev, "Failed to register mca.mp1 ras block!\n");
	111	return err;
	112	}
	113
	114	strcpy(ras->ras_block.ras_comm.name, "mca.mp1");
	115	ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA;
	116	ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
	117	adev->mca.mp1.ras_if = &ras->ras_block.ras_comm;
	118
	119	return 0;
	120	}
	121
	122	int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev)
	123	{
	124	int err;
	125	struct amdgpu_mca_ras_block *ras;
	126
	127	if (!adev->mca.mpio.ras)
	128	return 0;
	129
	130	ras = adev->mca.mpio.ras;
	131
	132	err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
	133	if (err) {
	134	dev_err(adev->dev, "Failed to register mca.mpio ras block!\n");
	135	return err;
	136	}
137
138	strcpy(ras->ras_block.ras_comm.name, "mca.mpio");
139	ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA;
140	ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
141	adev->mca.mpio.ras_if = &ras->ras_block.ras_comm;
142
143	return 0;
144	}
7ff607e2	145
07c1db70 YW	146	void amdgpu_mca_bank_set_init(struct mca_bank_set *mca_set)
	147	{
	148	if (!mca_set)
	149	return;
	150
	151	memset(mca_set, 0, sizeof(*mca_set));
	152	INIT_LIST_HEAD(&mca_set->list);
	153	}
	154
	155	int amdgpu_mca_bank_set_add_entry(struct mca_bank_set mca_set, struct mca_bank_entry entry)
	156	{
	157	struct mca_bank_node *node;
	158
	159	if (!entry)
	160	return -EINVAL;
	161
	162	node = kvzalloc(sizeof(*node), GFP_KERNEL);
	163	if (!node)
	164	return -ENOMEM;
	165
	166	memcpy(&node->entry, entry, sizeof(*entry));
	167
	168	INIT_LIST_HEAD(&node->node);
	169	list_add_tail(&node->node, &mca_set->list);
	170
	171	mca_set->nr_entries++;
	172
	173	return 0;
	174	}
	175
	176	void amdgpu_mca_bank_set_release(struct mca_bank_set *mca_set)
	177	{
	178	struct mca_bank_node node, tmp;
	179
	180	list_for_each_entry_safe(node, tmp, &mca_set->list, node) {
	181	list_del(&node->node);
	182	kvfree(node);
	183	}
	184	}
	185
7ff607e2 YW	186	void amdgpu_mca_smu_init_funcs(struct amdgpu_device adev, const struct amdgpu_mca_smu_funcs mca_funcs)
	187	{
	188	struct amdgpu_mca *mca = &adev->mca;
	189
	190	mca->mca_funcs = mca_funcs;
	191	}
	192
	193	int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
	194	{
	195	const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
	196
	197	if (mca_funcs && mca_funcs->mca_set_debug_mode)
	198	return mca_funcs->mca_set_debug_mode(adev, enable);
	199
	200	return -EOPNOTSUPP;
	201	}
	202
07c1db70 YW	203	static void amdgpu_mca_smu_mca_bank_dump(struct amdgpu_device adev, int idx, struct mca_bank_entry entry)
	204	{
	205	int i;
	206
	207	for (i = 0; i < ARRAY_SIZE(entry->regs); i++)
	208	dev_dbg(adev->dev, "mca entry[%02d].regs[%02d]=0x%016llx\n", idx, i, entry->regs[i]);
	209	}
	210
	211	int amdgpu_mca_smu_log_ras_error(struct amdgpu_device adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type, struct ras_err_data err_data)
	212	{
	213	struct amdgpu_smuio_mcm_config_info mcm_info;
	214	struct mca_bank_set mca_set;
	215	struct mca_bank_node *node;
	216	struct mca_bank_entry *entry;
	217	uint32_t count;
	218	int ret, i = 0;
	219
	220	amdgpu_mca_bank_set_init(&mca_set);
	221
	222	ret = amdgpu_mca_smu_get_mca_set(adev, blk, type, &mca_set);
	223	if (ret)
	224	goto out_mca_release;
	225
	226	list_for_each_entry(node, &mca_set.list, node) {
	227	entry = &node->entry;
	228
	229	amdgpu_mca_smu_mca_bank_dump(adev, i++, entry);
	230
	231	count = 0;
	232	ret = amdgpu_mca_smu_parse_mca_error_count(adev, blk, type, entry, &count);
	233	if (ret)
	234	goto out_mca_release;
	235
	236	if (!count)
	237	continue;
	238
	239	mcm_info.socket_id = entry->info.socket_id;
	240	mcm_info.die_id = entry->info.aid;
	241
	242	if (type == AMDGPU_MCA_ERROR_TYPE_UE)
	243	amdgpu_ras_error_statistic_ue_count(err_data, &mcm_info, (uint64_t)count);
	244	else
	245	amdgpu_ras_error_statistic_ce_count(err_data, &mcm_info, (uint64_t)count);
	246	}
	247
	248	out_mca_release:
	249	amdgpu_mca_bank_set_release(&mca_set);
	250
	251	return ret;
	252	}
	253
	254
7ff607e2 YW	255	int amdgpu_mca_smu_get_valid_mca_count(struct amdgpu_device adev, enum amdgpu_mca_error_type type, uint32_t count)
	256	{
	257	const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
	258
	259	if (!count)
	260	return -EINVAL;
	261
	262	if (mca_funcs && mca_funcs->mca_get_valid_mca_count)
	263	return mca_funcs->mca_get_valid_mca_count(adev, type, count);
	264
	265	return -EOPNOTSUPP;
	266	}
	267
07c1db70 YW	268	int amdgpu_mca_smu_get_mca_set_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
07c1db70 YW	269	enum amdgpu_mca_error_type type, uint32_t *total)
7ff607e2 YW	270	{
7ff607e2 YW	271	const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
07c1db70 YW	272	struct mca_bank_set mca_set;
	273	struct mca_bank_node *node;
	274	struct mca_bank_entry *entry;
	275	uint32_t count;
	276	int ret;
	277
	278	if (!total)
7ff607e2 YW	279	return -EINVAL;
7ff607e2 YW	280
07c1db70 YW	281	if (!mca_funcs)
07c1db70 YW	282	return -EOPNOTSUPP;
7ff607e2	283
07c1db70 YW	284	if (!mca_funcs->mca_get_ras_mca_set \|\| !mca_funcs->mca_get_valid_mca_count)
	285	return -EOPNOTSUPP;
	286
	287	amdgpu_mca_bank_set_init(&mca_set);
	288
	289	ret = mca_funcs->mca_get_ras_mca_set(adev, blk, type, &mca_set);
	290	if (ret)
	291	goto err_mca_set_release;
	292
	293	*total = 0;
	294	list_for_each_entry(node, &mca_set.list, node) {
	295	entry = &node->entry;
	296
	297	count = 0;
	298	ret = mca_funcs->mca_parse_mca_error_count(adev, blk, type, entry, &count);
	299	if (ret)
	300	goto err_mca_set_release;
	301
	302	*total += count;
	303	}
	304
	305	err_mca_set_release:
	306	amdgpu_mca_bank_set_release(&mca_set);
	307
	308	return ret;
	309	}
	310
	311	int amdgpu_mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
	312	enum amdgpu_mca_error_type type, struct mca_bank_entry entry, uint32_t count)
	313	{
	314	const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
	315	if (!count \|\| !entry)
	316	return -EINVAL;
	317
	318	if (!mca_funcs \|\| !mca_funcs->mca_parse_mca_error_count)
	319	return -EOPNOTSUPP;
	320
	321
	322	return mca_funcs->mca_parse_mca_error_count(adev, blk, type, entry, count);
	323	}
	324
	325	int amdgpu_mca_smu_get_mca_set(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
	326	enum amdgpu_mca_error_type type, struct mca_bank_set *mca_set)
	327	{
	328	const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
	329
	330	if (!mca_set)
	331	return -EINVAL;
	332
	333	if (!mca_funcs \|\| !mca_funcs->mca_get_ras_mca_set)
	334	return -EOPNOTSUPP;
	335
	336	WARN_ON(!list_empty(&mca_set->list));
	337
	338	return mca_funcs->mca_get_ras_mca_set(adev, blk, type, mca_set);
7ff607e2 YW	339	}
	340
	341	int amdgpu_mca_smu_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
	342	int idx, struct mca_bank_entry *entry)
	343	{
	344	const struct amdgpu_mca_smu_funcs *mca_funcs = adev->mca.mca_funcs;
	345	int count;
	346
	347	switch (type) {
	348	case AMDGPU_MCA_ERROR_TYPE_UE:
	349	count = mca_funcs->max_ue_count;
	350	break;
	351	case AMDGPU_MCA_ERROR_TYPE_CE:
	352	count = mca_funcs->max_ce_count;
	353	break;
	354	default:
	355	return -EINVAL;
	356	}
	357
	358	if (idx >= count)
	359	return -EINVAL;
	360
	361	if (mca_funcs && mca_funcs->mca_get_mca_entry)
	362	return mca_funcs->mca_get_mca_entry(adev, type, idx, entry);
	363
	364	return -EOPNOTSUPP;
	365	}
	366
4051844c YW	367	#if defined(CONFIG_DEBUG_FS)
	368	static int amdgpu_mca_smu_debug_mode_set(void *data, u64 val)
	369	{
	370	struct amdgpu_device adev = (struct amdgpu_device )data;
	371	int ret;
	372
	373	ret = amdgpu_mca_smu_set_debug_mode(adev, val ? true : false);
	374	if (ret)
	375	return ret;
	376
	377	dev_info(adev->dev, "amdgpu set smu mca debug mode %s success\n", val ? "on" : "off");
	378
	379	return 0;
	380	}
	381
	382	static void mca_dump_entry(struct seq_file m, struct mca_bank_entry entry)
	383	{
	384	int i, idx = entry->idx;
	385
	386	seq_printf(m, "mca entry[%d].type: %s\n", idx, entry->type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE");
	387	seq_printf(m, "mca entry[%d].ip: %d\n", idx, entry->ip);
	388	seq_printf(m, "mca entry[%d].info: socketid:%d aid:%d hwid:0x%03x mcatype:0x%04x\n",
	389	idx, entry->info.socket_id, entry->info.aid, entry->info.hwid, entry->info.mcatype);
	390
	391	for (i = 0; i < ARRAY_SIZE(entry->regs); i++)
	392	seq_printf(m, "mca entry[%d].regs[%d]: 0x%016llx\n", idx, i, entry->regs[i]);
	393	}
	394
	395	static int mca_dump_show(struct seq_file *m, enum amdgpu_mca_error_type type)
	396	{
	397	struct amdgpu_device adev = (struct amdgpu_device )m->private;
	398	struct mca_bank_entry *entry;
	399	uint32_t count = 0;
	400	int i, ret;
	401
	402	ret = amdgpu_mca_smu_get_valid_mca_count(adev, type, &count);
	403	if (ret)
	404	return ret;
	405
	406	seq_printf(m, "amdgpu smu %s valid mca count: %d\n",
	407	type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", count);
	408
	409	if (!count)
	410	return 0;
	411
	412	entry = kmalloc(sizeof(*entry), GFP_KERNEL);
	413	if (!entry)
	414	return -ENOMEM;
	415
	416	for (i = 0; i < count; i++) {
	417	memset(entry, 0, sizeof(*entry));
	418
	419	ret = amdgpu_mca_smu_get_mca_entry(adev, type, i, entry);
	420	if (ret)
	421	goto err_free_entry;
	422
	423	mca_dump_entry(m, entry);
	424	}
	425
	426	err_free_entry:
	427	kfree(entry);
	428
	429	return ret;
	430	}
431
432	static int mca_dump_ce_show(struct seq_file m, void unused)
433	{
434	return mca_dump_show(m, AMDGPU_MCA_ERROR_TYPE_CE);
435	}
436
437	static int mca_dump_ce_open(struct inode inode, struct file file)
438	{
439	return single_open(file, mca_dump_ce_show, inode->i_private);
440	}
441
442	static const struct file_operations mca_ce_dump_debug_fops = {
443	.owner = THIS_MODULE,
444	.open = mca_dump_ce_open,
445	.read = seq_read,
446	.llseek = seq_lseek,
447	.release = single_release,
448	};
449
450	static int mca_dump_ue_show(struct seq_file m, void unused)
451	{
452	return mca_dump_show(m, AMDGPU_MCA_ERROR_TYPE_UE);
453	}
454
455	static int mca_dump_ue_open(struct inode inode, struct file file)
456	{
457	return single_open(file, mca_dump_ue_show, inode->i_private);
458	}
459
460	static const struct file_operations mca_ue_dump_debug_fops = {
461	.owner = THIS_MODULE,
462	.open = mca_dump_ue_open,
463	.read = seq_read,
464	.llseek = seq_lseek,
465	.release = single_release,
466	};
467
468	DEFINE_DEBUGFS_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n");
469	#endif
470
471	void amdgpu_mca_smu_debugfs_init(struct amdgpu_device adev, struct dentry root)
472	{
473	#if defined(CONFIG_DEBUG_FS)
474	if (!root \|\| adev->ip_versions[MP1_HWIP][0] != IP_VERSION(13, 0, 6))
475	return;
476
477	debugfs_create_file("mca_debug_mode", 0200, root, adev, &mca_debug_mode_fops);
478	debugfs_create_file("mca_ue_dump", 0400, root, adev, &mca_ue_dump_debug_fops);
479	debugfs_create_file("mca_ce_dump", 0400, root, adev, &mca_ce_dump_debug_fops);
480	#endif
481	}
482