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e60f8db5 AX |
1 | /* |
2 | * Copyright 2016 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #include "amdgpu.h" | |
24 | #include "mmhub_v1_0.h" | |
25 | ||
65417d9f FX |
26 | #include "mmhub/mmhub_1_0_offset.h" |
27 | #include "mmhub/mmhub_1_0_sh_mask.h" | |
28 | #include "mmhub/mmhub_1_0_default.h" | |
6ce68225 FX |
29 | #include "athub/athub_1_0_offset.h" |
30 | #include "athub/athub_1_0_sh_mask.h" | |
fb960bd2 | 31 | #include "vega10_enum.h" |
e60f8db5 AX |
32 | |
33 | #include "soc15_common.h" | |
34 | ||
2547a7aa HR |
35 | #define mmDAGB0_CNTL_MISC2_RV 0x008f |
36 | #define mmDAGB0_CNTL_MISC2_RV_BASE_IDX 0 | |
37 | ||
e60f8db5 AX |
38 | u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev) |
39 | { | |
2a419183 | 40 | u64 base = RREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE); |
e60f8db5 AX |
41 | |
42 | base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK; | |
43 | base <<= 24; | |
44 | ||
45 | return base; | |
46 | } | |
47 | ||
a51dca4f HR |
48 | static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev) |
49 | { | |
50 | uint64_t value; | |
51 | ||
52 | BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL)); | |
770d13b1 | 53 | value = adev->gart.table_addr - adev->gmc.vram_start + |
a51dca4f HR |
54 | adev->vm_manager.vram_base_offset; |
55 | value &= 0x0000FFFFFFFFF000ULL; | |
56 | value |= 0x1; /* valid bit */ | |
57 | ||
2a419183 HR |
58 | WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, |
59 | lower_32_bits(value)); | |
a51dca4f | 60 | |
2a419183 HR |
61 | WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, |
62 | upper_32_bits(value)); | |
a51dca4f HR |
63 | } |
64 | ||
9bbad6fd HR |
65 | static void mmhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev) |
66 | { | |
67 | mmhub_v1_0_init_gart_pt_regs(adev); | |
68 | ||
2a419183 | 69 | WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, |
770d13b1 | 70 | (u32)(adev->gmc.gart_start >> 12)); |
2a419183 | 71 | WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, |
770d13b1 | 72 | (u32)(adev->gmc.gart_start >> 44)); |
2a419183 HR |
73 | |
74 | WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, | |
770d13b1 | 75 | (u32)(adev->gmc.gart_end >> 12)); |
2a419183 | 76 | WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, |
770d13b1 | 77 | (u32)(adev->gmc.gart_end >> 44)); |
9bbad6fd HR |
78 | } |
79 | ||
fc4b884b | 80 | static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) |
e60f8db5 | 81 | { |
fc4b884b HR |
82 | uint64_t value; |
83 | uint32_t tmp; | |
e60f8db5 | 84 | |
fc4b884b | 85 | /* Disable AGP. */ |
2a419183 HR |
86 | WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0); |
87 | WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0); | |
88 | WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF); | |
a51dca4f | 89 | |
fc4b884b | 90 | /* Program the system aperture low logical page number. */ |
2a419183 | 91 | WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR, |
770d13b1 | 92 | adev->gmc.vram_start >> 18); |
2a419183 | 93 | WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
770d13b1 | 94 | adev->gmc.vram_end >> 18); |
fc4b884b HR |
95 | |
96 | /* Set default page address. */ | |
770d13b1 | 97 | value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start + |
e60f8db5 | 98 | adev->vm_manager.vram_base_offset; |
2a419183 HR |
99 | WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, |
100 | (u32)(value >> 12)); | |
101 | WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, | |
102 | (u32)(value >> 44)); | |
fc4b884b HR |
103 | |
104 | /* Program "protection fault". */ | |
2a419183 | 105 | WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32, |
92e71b06 | 106 | (u32)(adev->dummy_page_addr >> 12)); |
2a419183 | 107 | WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32, |
92e71b06 | 108 | (u32)((u64)adev->dummy_page_addr >> 44)); |
2a419183 HR |
109 | |
110 | tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2); | |
fc4b884b HR |
111 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2, |
112 | ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1); | |
2a419183 | 113 | WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL2, tmp); |
fc4b884b HR |
114 | } |
115 | ||
34269839 HR |
116 | static void mmhub_v1_0_init_tlb_regs(struct amdgpu_device *adev) |
117 | { | |
118 | uint32_t tmp; | |
119 | ||
120 | /* Setup TLB control */ | |
2a419183 | 121 | tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); |
34269839 HR |
122 | |
123 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1); | |
124 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3); | |
125 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, | |
126 | ENABLE_ADVANCED_DRIVER_MODEL, 1); | |
127 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, | |
128 | SYSTEM_APERTURE_UNMAPPED_ACCESS, 0); | |
129 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0); | |
130 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, | |
131 | MTYPE, MTYPE_UC);/* XXX for emulation. */ | |
132 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1); | |
133 | ||
2a419183 | 134 | WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); |
34269839 HR |
135 | } |
136 | ||
41f6f311 HR |
137 | static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev) |
138 | { | |
a3ce3645 | 139 | uint32_t tmp; |
41f6f311 HR |
140 | |
141 | /* Setup L2 cache */ | |
2a419183 | 142 | tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); |
41f6f311 | 143 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); |
6be7adb3 | 144 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1); |
41f6f311 HR |
145 | /* XXX for emulation, Refer to closed source code.*/ |
146 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE, | |
147 | 0); | |
148 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1); | |
149 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1); | |
150 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0); | |
2a419183 | 151 | WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); |
41f6f311 | 152 | |
2a419183 | 153 | tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); |
41f6f311 HR |
154 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1); |
155 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1); | |
2a419183 | 156 | WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); |
41f6f311 | 157 | |
770d13b1 | 158 | if (adev->gmc.translate_further) { |
6a42fd6f CK |
159 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12); |
160 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, | |
161 | L2_CACHE_BIGK_FRAGMENT_SIZE, 9); | |
162 | } else { | |
163 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9); | |
164 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, | |
165 | L2_CACHE_BIGK_FRAGMENT_SIZE, 6); | |
166 | } | |
41f6f311 HR |
167 | |
168 | tmp = mmVM_L2_CNTL4_DEFAULT; | |
169 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0); | |
170 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0); | |
2a419183 | 171 | WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL4, tmp); |
41f6f311 HR |
172 | } |
173 | ||
02c4704b HR |
174 | static void mmhub_v1_0_enable_system_domain(struct amdgpu_device *adev) |
175 | { | |
176 | uint32_t tmp; | |
177 | ||
2a419183 | 178 | tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); |
02c4704b HR |
179 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1); |
180 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0); | |
2a419183 | 181 | WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp); |
02c4704b HR |
182 | } |
183 | ||
d5c87390 HR |
184 | static void mmhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev) |
185 | { | |
2a419183 HR |
186 | WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, |
187 | 0XFFFFFFFF); | |
188 | WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, | |
189 | 0x0000000F); | |
190 | ||
191 | WREG32_SOC15(MMHUB, 0, | |
192 | mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0); | |
193 | WREG32_SOC15(MMHUB, 0, | |
194 | mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0); | |
195 | ||
196 | WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, | |
197 | 0); | |
198 | WREG32_SOC15(MMHUB, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, | |
199 | 0); | |
d5c87390 HR |
200 | } |
201 | ||
3dff4cc4 | 202 | static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev) |
fc4b884b | 203 | { |
6a42fd6f | 204 | unsigned num_level, block_size; |
3dff4cc4 | 205 | uint32_t tmp; |
6a42fd6f CK |
206 | int i; |
207 | ||
208 | num_level = adev->vm_manager.num_level; | |
209 | block_size = adev->vm_manager.block_size; | |
770d13b1 | 210 | if (adev->gmc.translate_further) |
6a42fd6f CK |
211 | num_level -= 1; |
212 | else | |
213 | block_size -= 9; | |
e60f8db5 AX |
214 | |
215 | for (i = 0; i <= 14; i++) { | |
deca8322 | 216 | tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i); |
6a42fd6f CK |
217 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); |
218 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, | |
219 | num_level); | |
e60f8db5 | 220 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
6a42fd6f | 221 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
e60f8db5 | 222 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
6a42fd6f CK |
223 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, |
224 | 1); | |
e60f8db5 | 225 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
6a42fd6f | 226 | PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
e60f8db5 | 227 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
6a42fd6f | 228 | VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
e60f8db5 | 229 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
6a42fd6f | 230 | READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
e60f8db5 | 231 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
6a42fd6f | 232 | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
e60f8db5 | 233 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
6a42fd6f | 234 | EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); |
e60f8db5 | 235 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, |
6a42fd6f CK |
236 | PAGE_TABLE_BLOCK_SIZE, |
237 | block_size); | |
9f57f7b4 JC |
238 | /* Send no-retry XNACK on fault to suppress VM fault storm. */ |
239 | tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, | |
240 | RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0); | |
deca8322 TSD |
241 | WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL, i, tmp); |
242 | WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0); | |
243 | WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0); | |
244 | WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32, i*2, | |
22770e5a | 245 | lower_32_bits(adev->vm_manager.max_pfn - 1)); |
deca8322 | 246 | WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2, |
22770e5a | 247 | upper_32_bits(adev->vm_manager.max_pfn - 1)); |
e60f8db5 | 248 | } |
3dff4cc4 HR |
249 | } |
250 | ||
1e4eccda HR |
251 | static void mmhub_v1_0_program_invalidation(struct amdgpu_device *adev) |
252 | { | |
253 | unsigned i; | |
254 | ||
255 | for (i = 0; i < 18; ++i) { | |
deca8322 TSD |
256 | WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32, |
257 | 2 * i, 0xffffffff); | |
258 | WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32, | |
259 | 2 * i, 0x1f); | |
1e4eccda HR |
260 | } |
261 | } | |
262 | ||
2fcd43ce | 263 | struct pctl_data { |
a69c7e01 HZ |
264 | uint32_t index; |
265 | uint32_t data; | |
2fcd43ce HZ |
266 | }; |
267 | ||
606ce3c0 | 268 | static const struct pctl_data pctl0_data[] = { |
a69c7e01 HZ |
269 | {0x0, 0x7a640}, |
270 | {0x9, 0x2a64a}, | |
271 | {0xd, 0x2a680}, | |
272 | {0x11, 0x6a684}, | |
273 | {0x19, 0xea68e}, | |
274 | {0x29, 0xa69e}, | |
c8553f4b YZ |
275 | {0x2b, 0x0010a6c0}, |
276 | {0x3d, 0x83a707}, | |
277 | {0xc2, 0x8a7a4}, | |
278 | {0xcc, 0x1a7b8}, | |
279 | {0xcf, 0xfa7cc}, | |
280 | {0xe0, 0x17a7dd}, | |
281 | {0xf9, 0xa7dc}, | |
282 | {0xfb, 0x12a7f5}, | |
283 | {0x10f, 0xa808}, | |
284 | {0x111, 0x12a810}, | |
285 | {0x125, 0x7a82c} | |
2fcd43ce | 286 | }; |
376b6a1f | 287 | #define PCTL0_DATA_LEN (ARRAY_SIZE(pctl0_data)) |
2fcd43ce | 288 | |
c8553f4b | 289 | #define PCTL0_RENG_EXEC_END_PTR 0x12d |
2fcd43ce HZ |
290 | #define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE 0xa640 |
291 | #define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833 | |
292 | ||
606ce3c0 | 293 | static const struct pctl_data pctl1_data[] = { |
a69c7e01 HZ |
294 | {0x0, 0x39a000}, |
295 | {0x3b, 0x44a040}, | |
296 | {0x81, 0x2a08d}, | |
297 | {0x85, 0x6ba094}, | |
298 | {0xf2, 0x18a100}, | |
299 | {0x10c, 0x4a132}, | |
300 | {0x112, 0xca141}, | |
301 | {0x120, 0x2fa158}, | |
302 | {0x151, 0x17a1d0}, | |
303 | {0x16a, 0x1a1e9}, | |
304 | {0x16d, 0x13a1ec}, | |
305 | {0x182, 0x7a201}, | |
306 | {0x18b, 0x3a20a}, | |
307 | {0x190, 0x7a580}, | |
308 | {0x199, 0xa590}, | |
309 | {0x19b, 0x4a594}, | |
310 | {0x1a1, 0x1a59c}, | |
311 | {0x1a4, 0x7a82c}, | |
312 | {0x1ad, 0xfa7cc}, | |
313 | {0x1be, 0x17a7dd}, | |
314 | {0x1d7, 0x12a810}, | |
315 | {0x1eb, 0x4000a7e1}, | |
316 | {0x1ec, 0x5000a7f5}, | |
317 | {0x1ed, 0x4000a7e2}, | |
318 | {0x1ee, 0x5000a7dc}, | |
319 | {0x1ef, 0x4000a7e3}, | |
320 | {0x1f0, 0x5000a7f6}, | |
321 | {0x1f1, 0x5000a7e4} | |
2fcd43ce | 322 | }; |
376b6a1f | 323 | #define PCTL1_DATA_LEN (ARRAY_SIZE(pctl1_data)) |
2fcd43ce | 324 | |
a69c7e01 | 325 | #define PCTL1_RENG_EXEC_END_PTR 0x1f1 |
2fcd43ce HZ |
326 | #define PCTL1_STCTRL_REG_SAVE_RANGE0_BASE 0xa000 |
327 | #define PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa20d | |
328 | #define PCTL1_STCTRL_REG_SAVE_RANGE1_BASE 0xa580 | |
329 | #define PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT 0xa59d | |
330 | #define PCTL1_STCTRL_REG_SAVE_RANGE2_BASE 0xa82c | |
331 | #define PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT 0xa833 | |
332 | ||
333 | static void mmhub_v1_0_power_gating_write_save_ranges(struct amdgpu_device *adev) | |
334 | { | |
335 | uint32_t tmp = 0; | |
336 | ||
337 | /* PCTL0_STCTRL_REGISTER_SAVE_RANGE0 */ | |
338 | tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0, | |
339 | STCTRL_REGISTER_SAVE_BASE, | |
340 | PCTL0_STCTRL_REG_SAVE_RANGE0_BASE); | |
341 | tmp = REG_SET_FIELD(tmp, PCTL0_STCTRL_REGISTER_SAVE_RANGE0, | |
342 | STCTRL_REGISTER_SAVE_LIMIT, | |
343 | PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT); | |
344 | WREG32_SOC15(MMHUB, 0, mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0, tmp); | |
345 | ||
346 | /* PCTL1_STCTRL_REGISTER_SAVE_RANGE0 */ | |
347 | tmp = 0; | |
348 | tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0, | |
349 | STCTRL_REGISTER_SAVE_BASE, | |
350 | PCTL1_STCTRL_REG_SAVE_RANGE0_BASE); | |
351 | tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE0, | |
352 | STCTRL_REGISTER_SAVE_LIMIT, | |
353 | PCTL1_STCTRL_REG_SAVE_RANGE0_LIMIT); | |
354 | WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0, tmp); | |
355 | ||
356 | /* PCTL1_STCTRL_REGISTER_SAVE_RANGE1 */ | |
357 | tmp = 0; | |
358 | tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1, | |
359 | STCTRL_REGISTER_SAVE_BASE, | |
360 | PCTL1_STCTRL_REG_SAVE_RANGE1_BASE); | |
361 | tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE1, | |
362 | STCTRL_REGISTER_SAVE_LIMIT, | |
363 | PCTL1_STCTRL_REG_SAVE_RANGE1_LIMIT); | |
364 | WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1, tmp); | |
365 | ||
366 | /* PCTL1_STCTRL_REGISTER_SAVE_RANGE2 */ | |
367 | tmp = 0; | |
368 | tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2, | |
369 | STCTRL_REGISTER_SAVE_BASE, | |
370 | PCTL1_STCTRL_REG_SAVE_RANGE2_BASE); | |
371 | tmp = REG_SET_FIELD(tmp, PCTL1_STCTRL_REGISTER_SAVE_RANGE2, | |
372 | STCTRL_REGISTER_SAVE_LIMIT, | |
373 | PCTL1_STCTRL_REG_SAVE_RANGE2_LIMIT); | |
374 | WREG32_SOC15(MMHUB, 0, mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2, tmp); | |
375 | } | |
376 | ||
377 | void mmhub_v1_0_initialize_power_gating(struct amdgpu_device *adev) | |
378 | { | |
379 | uint32_t pctl0_misc = 0; | |
380 | uint32_t pctl0_reng_execute = 0; | |
381 | uint32_t pctl1_misc = 0; | |
382 | uint32_t pctl1_reng_execute = 0; | |
383 | int i = 0; | |
384 | ||
385 | if (amdgpu_sriov_vf(adev)) | |
386 | return; | |
387 | ||
c8553f4b | 388 | /****************** pctl0 **********************/ |
2fcd43ce HZ |
389 | pctl0_misc = RREG32_SOC15(MMHUB, 0, mmPCTL0_MISC); |
390 | pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE); | |
2fcd43ce HZ |
391 | |
392 | /* Light sleep must be disabled before writing to pctl0 registers */ | |
393 | pctl0_misc &= ~PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK; | |
394 | WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc); | |
395 | ||
396 | /* Write data used to access ram of register engine */ | |
397 | for (i = 0; i < PCTL0_DATA_LEN; i++) { | |
398 | WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_INDEX, | |
399 | pctl0_data[i].index); | |
400 | WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_RAM_DATA, | |
401 | pctl0_data[i].data); | |
402 | } | |
403 | ||
c8553f4b YZ |
404 | /* Re-enable light sleep */ |
405 | pctl0_misc |= PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK; | |
406 | WREG32_SOC15(MMHUB, 0, mmPCTL0_MISC, pctl0_misc); | |
407 | ||
408 | /****************** pctl1 **********************/ | |
409 | pctl1_misc = RREG32_SOC15(MMHUB, 0, mmPCTL1_MISC); | |
410 | pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE); | |
2fcd43ce HZ |
411 | |
412 | /* Light sleep must be disabled before writing to pctl1 registers */ | |
413 | pctl1_misc &= ~PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK; | |
414 | WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc); | |
415 | ||
416 | /* Write data used to access ram of register engine */ | |
417 | for (i = 0; i < PCTL1_DATA_LEN; i++) { | |
418 | WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_INDEX, | |
419 | pctl1_data[i].index); | |
420 | WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_RAM_DATA, | |
421 | pctl1_data[i].data); | |
422 | } | |
423 | ||
c8553f4b YZ |
424 | /* Re-enable light sleep */ |
425 | pctl1_misc |= PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK; | |
426 | WREG32_SOC15(MMHUB, 0, mmPCTL1_MISC, pctl1_misc); | |
427 | ||
428 | mmhub_v1_0_power_gating_write_save_ranges(adev); | |
429 | ||
430 | /* Set the reng execute end ptr for pctl0 */ | |
431 | pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, | |
432 | PCTL0_RENG_EXECUTE, | |
433 | RENG_EXECUTE_END_PTR, | |
434 | PCTL0_RENG_EXEC_END_PTR); | |
435 | WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute); | |
436 | ||
2fcd43ce HZ |
437 | /* Set the reng execute end ptr for pctl1 */ |
438 | pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, | |
439 | PCTL1_RENG_EXECUTE, | |
440 | RENG_EXECUTE_END_PTR, | |
441 | PCTL1_RENG_EXEC_END_PTR); | |
442 | WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute); | |
2fcd43ce HZ |
443 | } |
444 | ||
a95890b4 HZ |
445 | void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev, |
446 | bool enable) | |
447 | { | |
448 | uint32_t pctl0_reng_execute = 0; | |
449 | uint32_t pctl1_reng_execute = 0; | |
450 | ||
451 | if (amdgpu_sriov_vf(adev)) | |
452 | return; | |
453 | ||
454 | pctl0_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE); | |
455 | pctl1_reng_execute = RREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE); | |
456 | ||
f8386b35 | 457 | if (enable && adev->pg_flags & AMD_PG_SUPPORT_MMHUB) { |
a95890b4 HZ |
458 | pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, |
459 | PCTL0_RENG_EXECUTE, | |
460 | RENG_EXECUTE_ON_PWR_UP, 1); | |
461 | pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, | |
462 | PCTL0_RENG_EXECUTE, | |
463 | RENG_EXECUTE_ON_REG_UPDATE, 1); | |
464 | WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute); | |
465 | ||
466 | pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, | |
467 | PCTL1_RENG_EXECUTE, | |
468 | RENG_EXECUTE_ON_PWR_UP, 1); | |
469 | pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, | |
470 | PCTL1_RENG_EXECUTE, | |
471 | RENG_EXECUTE_ON_REG_UPDATE, 1); | |
472 | WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute); | |
473 | ||
7e452ce9 EH |
474 | if (adev->powerplay.pp_funcs->set_mmhub_powergating_by_smu) |
475 | amdgpu_dpm_set_mmhub_powergating_by_smu(adev); | |
476 | ||
a95890b4 HZ |
477 | } else { |
478 | pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, | |
479 | PCTL0_RENG_EXECUTE, | |
480 | RENG_EXECUTE_ON_PWR_UP, 0); | |
481 | pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute, | |
482 | PCTL0_RENG_EXECUTE, | |
483 | RENG_EXECUTE_ON_REG_UPDATE, 0); | |
484 | WREG32_SOC15(MMHUB, 0, mmPCTL0_RENG_EXECUTE, pctl0_reng_execute); | |
485 | ||
486 | pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, | |
487 | PCTL1_RENG_EXECUTE, | |
488 | RENG_EXECUTE_ON_PWR_UP, 0); | |
489 | pctl1_reng_execute = REG_SET_FIELD(pctl1_reng_execute, | |
490 | PCTL1_RENG_EXECUTE, | |
491 | RENG_EXECUTE_ON_REG_UPDATE, 0); | |
492 | WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute); | |
493 | } | |
494 | } | |
495 | ||
3dff4cc4 HR |
496 | int mmhub_v1_0_gart_enable(struct amdgpu_device *adev) |
497 | { | |
498 | if (amdgpu_sriov_vf(adev)) { | |
499 | /* | |
500 | * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are | |
501 | * VF copy registers so vbios post doesn't program them, for | |
502 | * SRIOV driver need to program them | |
503 | */ | |
2a419183 | 504 | WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE, |
770d13b1 | 505 | adev->gmc.vram_start >> 24); |
2a419183 | 506 | WREG32_SOC15(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP, |
770d13b1 | 507 | adev->gmc.vram_end >> 24); |
3dff4cc4 HR |
508 | } |
509 | ||
510 | /* GART Enable. */ | |
511 | mmhub_v1_0_init_gart_aperture_regs(adev); | |
512 | mmhub_v1_0_init_system_aperture_regs(adev); | |
513 | mmhub_v1_0_init_tlb_regs(adev); | |
514 | mmhub_v1_0_init_cache_regs(adev); | |
515 | ||
516 | mmhub_v1_0_enable_system_domain(adev); | |
517 | mmhub_v1_0_disable_identity_aperture(adev); | |
518 | mmhub_v1_0_setup_vmid_config(adev); | |
1e4eccda | 519 | mmhub_v1_0_program_invalidation(adev); |
e60f8db5 AX |
520 | |
521 | return 0; | |
522 | } | |
523 | ||
524 | void mmhub_v1_0_gart_disable(struct amdgpu_device *adev) | |
525 | { | |
526 | u32 tmp; | |
527 | u32 i; | |
528 | ||
529 | /* Disable all tables */ | |
530 | for (i = 0; i < 16; i++) | |
deca8322 | 531 | WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, i, 0); |
e60f8db5 AX |
532 | |
533 | /* Setup TLB control */ | |
2a419183 | 534 | tmp = RREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL); |
e60f8db5 AX |
535 | tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0); |
536 | tmp = REG_SET_FIELD(tmp, | |
537 | MC_VM_MX_L1_TLB_CNTL, | |
538 | ENABLE_ADVANCED_DRIVER_MODEL, | |
539 | 0); | |
2a419183 | 540 | WREG32_SOC15(MMHUB, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp); |
e60f8db5 AX |
541 | |
542 | /* Setup L2 cache */ | |
2a419183 | 543 | tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL); |
e60f8db5 | 544 | tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); |
2a419183 HR |
545 | WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL, tmp); |
546 | WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL3, 0); | |
e60f8db5 AX |
547 | } |
548 | ||
549 | /** | |
550 | * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling | |
551 | * | |
552 | * @adev: amdgpu_device pointer | |
553 | * @value: true redirects VM faults to the default page | |
554 | */ | |
555 | void mmhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev, bool value) | |
556 | { | |
557 | u32 tmp; | |
2a419183 | 558 | tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); |
e60f8db5 AX |
559 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, |
560 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
561 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, | |
562 | PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
563 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, | |
564 | PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
565 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, | |
566 | PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
567 | tmp = REG_SET_FIELD(tmp, | |
568 | VM_L2_PROTECTION_FAULT_CNTL, | |
569 | TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT, | |
570 | value); | |
571 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, | |
572 | NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
573 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, | |
574 | DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
575 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, | |
576 | VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
577 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, | |
578 | READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
579 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, | |
580 | WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
581 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, | |
582 | EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); | |
4bd9a67e ML |
583 | if (!value) { |
584 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, | |
585 | CRASH_ON_NO_RETRY_FAULT, 1); | |
586 | tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL, | |
587 | CRASH_ON_RETRY_FAULT, 1); | |
588 | } | |
589 | ||
2a419183 | 590 | WREG32_SOC15(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp); |
e60f8db5 AX |
591 | } |
592 | ||
77f6c763 | 593 | void mmhub_v1_0_init(struct amdgpu_device *adev) |
e60f8db5 | 594 | { |
e60f8db5 AX |
595 | struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB]; |
596 | ||
597 | hub->ctx0_ptb_addr_lo32 = | |
598 | SOC15_REG_OFFSET(MMHUB, 0, | |
599 | mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32); | |
600 | hub->ctx0_ptb_addr_hi32 = | |
601 | SOC15_REG_OFFSET(MMHUB, 0, | |
602 | mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32); | |
603 | hub->vm_inv_eng0_req = | |
604 | SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_REQ); | |
605 | hub->vm_inv_eng0_ack = | |
606 | SOC15_REG_OFFSET(MMHUB, 0, mmVM_INVALIDATE_ENG0_ACK); | |
607 | hub->vm_context0_cntl = | |
608 | SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL); | |
609 | hub->vm_l2_pro_fault_status = | |
610 | SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_STATUS); | |
611 | hub->vm_l2_pro_fault_cntl = | |
612 | SOC15_REG_OFFSET(MMHUB, 0, mmVM_L2_PROTECTION_FAULT_CNTL); | |
613 | ||
77f6c763 HR |
614 | } |
615 | ||
e60f8db5 AX |
616 | static void mmhub_v1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, |
617 | bool enable) | |
618 | { | |
2547a7aa | 619 | uint32_t def, data, def1, data1, def2 = 0, data2 = 0; |
e60f8db5 | 620 | |
2a419183 | 621 | def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); |
2547a7aa HR |
622 | |
623 | if (adev->asic_type != CHIP_RAVEN) { | |
2a419183 HR |
624 | def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2); |
625 | def2 = data2 = RREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2); | |
2547a7aa | 626 | } else |
2a419183 | 627 | def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV); |
e60f8db5 AX |
628 | |
629 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) { | |
630 | data |= ATC_L2_MISC_CG__ENABLE_MASK; | |
631 | ||
632 | data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | | |
633 | DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | | |
634 | DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | | |
635 | DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | | |
636 | DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | | |
637 | DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); | |
638 | ||
2547a7aa HR |
639 | if (adev->asic_type != CHIP_RAVEN) |
640 | data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | | |
641 | DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | | |
642 | DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | | |
643 | DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | | |
644 | DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | | |
645 | DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); | |
e60f8db5 AX |
646 | } else { |
647 | data &= ~ATC_L2_MISC_CG__ENABLE_MASK; | |
648 | ||
649 | data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | | |
650 | DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK | | |
651 | DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | | |
652 | DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK | | |
653 | DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | | |
654 | DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); | |
655 | ||
2547a7aa HR |
656 | if (adev->asic_type != CHIP_RAVEN) |
657 | data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK | | |
658 | DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK | | |
659 | DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK | | |
660 | DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK | | |
661 | DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK | | |
662 | DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK); | |
e60f8db5 AX |
663 | } |
664 | ||
665 | if (def != data) | |
2a419183 | 666 | WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); |
e60f8db5 | 667 | |
2547a7aa HR |
668 | if (def1 != data1) { |
669 | if (adev->asic_type != CHIP_RAVEN) | |
2a419183 | 670 | WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1); |
2547a7aa | 671 | else |
2a419183 | 672 | WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_RV, data1); |
2547a7aa | 673 | } |
e60f8db5 | 674 | |
2547a7aa | 675 | if (adev->asic_type != CHIP_RAVEN && def2 != data2) |
2a419183 | 676 | WREG32_SOC15(MMHUB, 0, mmDAGB1_CNTL_MISC2, data2); |
e60f8db5 AX |
677 | } |
678 | ||
679 | static void athub_update_medium_grain_clock_gating(struct amdgpu_device *adev, | |
680 | bool enable) | |
681 | { | |
682 | uint32_t def, data; | |
683 | ||
2a419183 | 684 | def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); |
e60f8db5 AX |
685 | |
686 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) | |
687 | data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK; | |
688 | else | |
689 | data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK; | |
690 | ||
691 | if (def != data) | |
2a419183 | 692 | WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); |
e60f8db5 AX |
693 | } |
694 | ||
695 | static void mmhub_v1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev, | |
696 | bool enable) | |
697 | { | |
698 | uint32_t def, data; | |
699 | ||
2a419183 | 700 | def = data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); |
e60f8db5 AX |
701 | |
702 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)) | |
703 | data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; | |
704 | else | |
705 | data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK; | |
706 | ||
707 | if (def != data) | |
2a419183 | 708 | WREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG, data); |
e60f8db5 AX |
709 | } |
710 | ||
711 | static void athub_update_medium_grain_light_sleep(struct amdgpu_device *adev, | |
712 | bool enable) | |
713 | { | |
714 | uint32_t def, data; | |
715 | ||
2a419183 | 716 | def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); |
e60f8db5 AX |
717 | |
718 | if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) && | |
719 | (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) | |
720 | data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; | |
721 | else | |
722 | data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK; | |
723 | ||
724 | if(def != data) | |
2a419183 | 725 | WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data); |
e60f8db5 AX |
726 | } |
727 | ||
d5583d4f HR |
728 | int mmhub_v1_0_set_clockgating(struct amdgpu_device *adev, |
729 | enum amd_clockgating_state state) | |
e60f8db5 | 730 | { |
98c24b24 XY |
731 | if (amdgpu_sriov_vf(adev)) |
732 | return 0; | |
733 | ||
e60f8db5 AX |
734 | switch (adev->asic_type) { |
735 | case CHIP_VEGA10: | |
2547a7aa | 736 | case CHIP_RAVEN: |
e60f8db5 AX |
737 | mmhub_v1_0_update_medium_grain_clock_gating(adev, |
738 | state == AMD_CG_STATE_GATE ? true : false); | |
739 | athub_update_medium_grain_clock_gating(adev, | |
740 | state == AMD_CG_STATE_GATE ? true : false); | |
741 | mmhub_v1_0_update_medium_grain_light_sleep(adev, | |
742 | state == AMD_CG_STATE_GATE ? true : false); | |
743 | athub_update_medium_grain_light_sleep(adev, | |
744 | state == AMD_CG_STATE_GATE ? true : false); | |
745 | break; | |
746 | default: | |
747 | break; | |
748 | } | |
749 | ||
750 | return 0; | |
751 | } | |
752 | ||
13052be5 | 753 | void mmhub_v1_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) |
e2a4cd69 | 754 | { |
e2a4cd69 HR |
755 | int data; |
756 | ||
757 | if (amdgpu_sriov_vf(adev)) | |
758 | *flags = 0; | |
759 | ||
760 | /* AMD_CG_SUPPORT_MC_MGCG */ | |
2a419183 | 761 | data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL); |
e2a4cd69 HR |
762 | if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK) |
763 | *flags |= AMD_CG_SUPPORT_MC_MGCG; | |
764 | ||
765 | /* AMD_CG_SUPPORT_MC_LS */ | |
2a419183 | 766 | data = RREG32_SOC15(MMHUB, 0, mmATC_L2_MISC_CG); |
e2a4cd69 HR |
767 | if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK) |
768 | *flags |= AMD_CG_SUPPORT_MC_LS; | |
769 | } |