[thirdparty/linux.git] / drivers / gpu / drm / amd / display / dc / dcn10 / dcn10_init.c

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "hw_sequencer_private.h"
#include "dce110/dce110_hw_sequencer.h"
#include "dcn10_hw_sequencer.h"

static const struct hw_sequencer_funcs dcn10_funcs = {
	.program_gamut_remap = dcn10_program_gamut_remap,
	.init_hw = dcn10_init_hw,
	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
	.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
	.post_unlock_program_front_end = dcn10_post_unlock_program_front_end,
	.update_plane_addr = dcn10_update_plane_addr,
	.update_dchub = dcn10_update_dchub,
	.update_pending_status = dcn10_update_pending_status,
	.program_output_csc = dcn10_program_output_csc,
	.enable_accelerated_mode = dce110_enable_accelerated_mode,
	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
	.update_info_frame = dce110_update_info_frame,
	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
	.enable_stream = dce110_enable_stream,
	.disable_stream = dce110_disable_stream,
	.unblank_stream = dcn10_unblank_stream,
	.blank_stream = dce110_blank_stream,
	.enable_audio_stream = dce110_enable_audio_stream,
	.disable_audio_stream = dce110_disable_audio_stream,
	.disable_plane = dcn10_disable_plane,
	.pipe_control_lock = dcn10_pipe_control_lock,
	.cursor_lock = dcn10_cursor_lock,
	.interdependent_update_lock = dcn10_lock_all_pipes,
	.prepare_bandwidth = dcn10_prepare_bandwidth,
	.optimize_bandwidth = dcn10_optimize_bandwidth,
	.set_drr = dcn10_set_drr,
	.get_position = dcn10_get_position,
	.set_static_screen_control = dcn10_set_static_screen_control,
	.setup_stereo = dcn10_setup_stereo,
	.set_avmute = dce110_set_avmute,
	.log_hw_state = dcn10_log_hw_state,
	.get_hw_state = dcn10_get_hw_state,
	.clear_status_bits = dcn10_clear_status_bits,
	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
	.edp_power_control = dce110_edp_power_control,
	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
	.set_cursor_position = dcn10_set_cursor_position,
	.set_cursor_attribute = dcn10_set_cursor_attribute,
	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
	.set_clock = dcn10_set_clock,
	.get_clock = dcn10_get_clock,
	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
};

static const struct hwseq_private_funcs dcn10_private_funcs = {
	.init_pipes = dcn10_init_pipes,
	.update_plane_addr = dcn10_update_plane_addr,
	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
	.program_pipe = dcn10_program_pipe,
	.update_mpcc = dcn10_update_mpcc,
	.set_input_transfer_func = dcn10_set_input_transfer_func,
	.set_output_transfer_func = dcn10_set_output_transfer_func,
	.power_down = dce110_power_down,
	.enable_display_power_gating = dcn10_dummy_display_power_gating,
	.blank_pixel_data = dcn10_blank_pixel_data,
	.reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
	.enable_stream_timing = dcn10_enable_stream_timing,
	.edp_backlight_control = dce110_edp_backlight_control,
	.is_panel_backlight_on = dce110_is_panel_backlight_on,
	.is_panel_powered_on = dce110_is_panel_powered_on,
	.disable_stream_gating = NULL,
	.enable_stream_gating = NULL,
	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
	.did_underflow_occur = dcn10_did_underflow_occur,
	.init_blank = NULL,
	.disable_vga = dcn10_disable_vga,
	.bios_golden_init = dcn10_bios_golden_init,
	.plane_atomic_disable = dcn10_plane_atomic_disable,
	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
	.enable_power_gating_plane = dcn10_enable_power_gating_plane,
	.dpp_pg_control = dcn10_dpp_pg_control,
	.hubp_pg_control = dcn10_hubp_pg_control,
	.dsc_pg_control = NULL,
	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
};

void dcn10_hw_sequencer_construct(struct dc *dc)
{
	dc->hwss = dcn10_funcs;
	dc->hwseq->funcs = dcn10_private_funcs;
}
Commit	Line	Data
78c77382 AK	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
f42ea55b	26	#include "hw_sequencer_private.h"
78c77382 AK	27	#include "dce110/dce110_hw_sequencer.h"
	28	#include "dcn10_hw_sequencer.h"
	29
	30	static const struct hw_sequencer_funcs dcn10_funcs = {
	31	.program_gamut_remap = dcn10_program_gamut_remap,
	32	.init_hw = dcn10_init_hw,
78c77382 AK	33	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
78c77382 AK	34	.apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
bbf5f6c3	35	.post_unlock_program_front_end = dcn10_post_unlock_program_front_end,
78c77382	36	.update_plane_addr = dcn10_update_plane_addr,
78c77382	37	.update_dchub = dcn10_update_dchub,
78c77382	38	.update_pending_status = dcn10_update_pending_status,
78c77382	39	.program_output_csc = dcn10_program_output_csc,
78c77382 AK	40	.enable_accelerated_mode = dce110_enable_accelerated_mode,
	41	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
	42	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
	43	.update_info_frame = dce110_update_info_frame,
	44	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
	45	.enable_stream = dce110_enable_stream,
	46	.disable_stream = dce110_disable_stream,
	47	.unblank_stream = dcn10_unblank_stream,
	48	.blank_stream = dce110_blank_stream,
	49	.enable_audio_stream = dce110_enable_audio_stream,
	50	.disable_audio_stream = dce110_disable_audio_stream,
78c77382	51	.disable_plane = dcn10_disable_plane,
78c77382	52	.pipe_control_lock = dcn10_pipe_control_lock,
b2a7b0ce	53	.cursor_lock = dcn10_cursor_lock,
009114f6	54	.interdependent_update_lock = dcn10_lock_all_pipes,
78c77382 AK	55	.prepare_bandwidth = dcn10_prepare_bandwidth,
78c77382 AK	56	.optimize_bandwidth = dcn10_optimize_bandwidth,
78c77382 AK	57	.set_drr = dcn10_set_drr,
	58	.get_position = dcn10_get_position,
	59	.set_static_screen_control = dcn10_set_static_screen_control,
	60	.setup_stereo = dcn10_setup_stereo,
	61	.set_avmute = dce110_set_avmute,
	62	.log_hw_state = dcn10_log_hw_state,
	63	.get_hw_state = dcn10_get_hw_state,
	64	.clear_status_bits = dcn10_clear_status_bits,
	65	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
78c77382 AK	66	.edp_power_control = dce110_edp_power_control,
	67	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
	68	.set_cursor_position = dcn10_set_cursor_position,
	69	.set_cursor_attribute = dcn10_set_cursor_attribute,
	70	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
78c77382	71	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
78c77382 AK	72	.set_clock = dcn10_set_clock,
78c77382 AK	73	.get_clock = dcn10_get_clock,
f42ea55b AK	74	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
	75	};
	76
	77	static const struct hwseq_private_funcs dcn10_private_funcs = {
	78	.init_pipes = dcn10_init_pipes,
	79	.update_plane_addr = dcn10_update_plane_addr,
	80	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
	81	.program_pipe = dcn10_program_pipe,
	82	.update_mpcc = dcn10_update_mpcc,
	83	.set_input_transfer_func = dcn10_set_input_transfer_func,
	84	.set_output_transfer_func = dcn10_set_output_transfer_func,
	85	.power_down = dce110_power_down,
	86	.enable_display_power_gating = dcn10_dummy_display_power_gating,
	87	.blank_pixel_data = dcn10_blank_pixel_data,
	88	.reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
	89	.enable_stream_timing = dcn10_enable_stream_timing,
	90	.edp_backlight_control = dce110_edp_backlight_control,
accde06f AK	91	.is_panel_backlight_on = dce110_is_panel_backlight_on,
accde06f AK	92	.is_panel_powered_on = dce110_is_panel_powered_on,
f42ea55b AK	93	.disable_stream_gating = NULL,
	94	.enable_stream_gating = NULL,
	95	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
78c77382 AK	96	.did_underflow_occur = dcn10_did_underflow_occur,
	97	.init_blank = NULL,
	98	.disable_vga = dcn10_disable_vga,
	99	.bios_golden_init = dcn10_bios_golden_init,
	100	.plane_atomic_disable = dcn10_plane_atomic_disable,
	101	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
	102	.enable_power_gating_plane = dcn10_enable_power_gating_plane,
	103	.dpp_pg_control = dcn10_dpp_pg_control,
	104	.hubp_pg_control = dcn10_hubp_pg_control,
	105	.dsc_pg_control = NULL,
	106	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
	107	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
	108	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
	109	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
78c77382 AK	110	};
	111
	112	void dcn10_hw_sequencer_construct(struct dc *dc)
	113	{
	114	dc->hwss = dcn10_funcs;
f42ea55b	115	dc->hwseq->funcs = dcn10_private_funcs;
78c77382	116	}