[thirdparty/linux.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_init.c

/*
 * Copyright 2016 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#include "dce110/dce110_hw_sequencer.h"
#include "dcn10/dcn10_hw_sequencer.h"
#include "dcn20_hwseq.h"

static const struct hw_sequencer_funcs dcn20_funcs = {
	.program_gamut_remap = dcn10_program_gamut_remap,
	.init_hw = dcn10_init_hw,
	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
	.apply_ctx_for_surface = NULL,
	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
	.update_plane_addr = dcn20_update_plane_addr,
	.update_dchub = dcn10_update_dchub,
	.update_pending_status = dcn10_update_pending_status,
	.program_output_csc = dcn20_program_output_csc,
	.enable_accelerated_mode = dce110_enable_accelerated_mode,
	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
	.update_info_frame = dce110_update_info_frame,
	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
	.enable_stream = dcn20_enable_stream,
	.disable_stream = dce110_disable_stream,
	.unblank_stream = dcn20_unblank_stream,
	.blank_stream = dce110_blank_stream,
	.enable_audio_stream = dce110_enable_audio_stream,
	.disable_audio_stream = dce110_disable_audio_stream,
	.disable_plane = dcn20_disable_plane,
	.pipe_control_lock = dcn20_pipe_control_lock,
	.interdependent_update_lock = dcn10_lock_all_pipes,
	.cursor_lock = dcn10_cursor_lock,
	.prepare_bandwidth = dcn20_prepare_bandwidth,
	.optimize_bandwidth = dcn20_optimize_bandwidth,
	.update_bandwidth = dcn20_update_bandwidth,
	.set_drr = dcn10_set_drr,
	.get_position = dcn10_get_position,
	.set_static_screen_control = dcn10_set_static_screen_control,
	.setup_stereo = dcn10_setup_stereo,
	.set_avmute = dce110_set_avmute,
	.log_hw_state = dcn10_log_hw_state,
	.get_hw_state = dcn10_get_hw_state,
	.clear_status_bits = dcn10_clear_status_bits,
	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
	.edp_power_control = dce110_edp_power_control,
	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
	.set_cursor_position = dcn10_set_cursor_position,
	.set_cursor_attribute = dcn10_set_cursor_attribute,
	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
	.set_clock = dcn10_set_clock,
	.get_clock = dcn10_get_clock,
	.program_triplebuffer = dcn20_program_triple_buffer,
	.enable_writeback = dcn20_enable_writeback,
	.disable_writeback = dcn20_disable_writeback,
	.dmdata_status_done = dcn20_dmdata_status_done,
	.program_dmdata_engine = dcn20_program_dmdata_engine,
	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
	.init_sys_ctx = dcn20_init_sys_ctx,
	.init_vm_ctx = dcn20_init_vm_ctx,
	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
};

static const struct hwseq_private_funcs dcn20_private_funcs = {
	.init_pipes = dcn10_init_pipes,
	.update_plane_addr = dcn20_update_plane_addr,
	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
	.update_mpcc = dcn20_update_mpcc,
	.set_input_transfer_func = dcn20_set_input_transfer_func,
	.set_output_transfer_func = dcn20_set_output_transfer_func,
	.power_down = dce110_power_down,
	.enable_display_power_gating = dcn10_dummy_display_power_gating,
	.blank_pixel_data = dcn20_blank_pixel_data,
	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
	.enable_stream_timing = dcn20_enable_stream_timing,
	.edp_backlight_control = dce110_edp_backlight_control,
	.is_panel_backlight_on = dce110_is_panel_backlight_on,
	.is_panel_powered_on = dce110_is_panel_powered_on,
	.disable_stream_gating = dcn20_disable_stream_gating,
	.enable_stream_gating = dcn20_enable_stream_gating,
	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
	.did_underflow_occur = dcn10_did_underflow_occur,
	.init_blank = dcn20_init_blank,
	.disable_vga = dcn20_disable_vga,
	.bios_golden_init = dcn10_bios_golden_init,
	.plane_atomic_disable = dcn20_plane_atomic_disable,
	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
	.enable_power_gating_plane = dcn20_enable_power_gating_plane,
	.dpp_pg_control = dcn20_dpp_pg_control,
	.hubp_pg_control = dcn20_hubp_pg_control,
	.update_odm = dcn20_update_odm,
	.dsc_pg_control = dcn20_dsc_pg_control,
	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
	.dccg_init = dcn20_dccg_init,
	.set_blend_lut = dcn20_set_blend_lut,
	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
};

void dcn20_hw_sequencer_construct(struct dc *dc)
{
	dc->hwss = dcn20_funcs;
	dc->hwseq->funcs = dcn20_private_funcs;

	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
		dc->hwss.init_hw = dcn20_fpga_init_hw;
		dc->hwseq->funcs.init_pipes = NULL;
	}
}
Commit	Line	Data
78c77382 AK	1	/*
	2	* Copyright 2016 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#include "dce110/dce110_hw_sequencer.h"
	27	#include "dcn10/dcn10_hw_sequencer.h"
	28	#include "dcn20_hwseq.h"
	29
	30	static const struct hw_sequencer_funcs dcn20_funcs = {
	31	.program_gamut_remap = dcn10_program_gamut_remap,
	32	.init_hw = dcn10_init_hw,
78c77382 AK	33	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
	34	.apply_ctx_for_surface = NULL,
	35	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
bbf5f6c3	36	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
78c77382	37	.update_plane_addr = dcn20_update_plane_addr,
78c77382	38	.update_dchub = dcn10_update_dchub,
78c77382	39	.update_pending_status = dcn10_update_pending_status,
78c77382	40	.program_output_csc = dcn20_program_output_csc,
78c77382 AK	41	.enable_accelerated_mode = dce110_enable_accelerated_mode,
	42	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
	43	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
	44	.update_info_frame = dce110_update_info_frame,
	45	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
	46	.enable_stream = dcn20_enable_stream,
	47	.disable_stream = dce110_disable_stream,
	48	.unblank_stream = dcn20_unblank_stream,
	49	.blank_stream = dce110_blank_stream,
	50	.enable_audio_stream = dce110_enable_audio_stream,
	51	.disable_audio_stream = dce110_disable_audio_stream,
78c77382	52	.disable_plane = dcn20_disable_plane,
78c77382	53	.pipe_control_lock = dcn20_pipe_control_lock,
009114f6	54	.interdependent_update_lock = dcn10_lock_all_pipes,
b2a7b0ce	55	.cursor_lock = dcn10_cursor_lock,
78c77382 AK	56	.prepare_bandwidth = dcn20_prepare_bandwidth,
	57	.optimize_bandwidth = dcn20_optimize_bandwidth,
	58	.update_bandwidth = dcn20_update_bandwidth,
78c77382 AK	59	.set_drr = dcn10_set_drr,
	60	.get_position = dcn10_get_position,
	61	.set_static_screen_control = dcn10_set_static_screen_control,
	62	.setup_stereo = dcn10_setup_stereo,
	63	.set_avmute = dce110_set_avmute,
	64	.log_hw_state = dcn10_log_hw_state,
	65	.get_hw_state = dcn10_get_hw_state,
	66	.clear_status_bits = dcn10_clear_status_bits,
	67	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
78c77382 AK	68	.edp_power_control = dce110_edp_power_control,
	69	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
	70	.set_cursor_position = dcn10_set_cursor_position,
	71	.set_cursor_attribute = dcn10_set_cursor_attribute,
	72	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
78c77382	73	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
78c77382 AK	74	.set_clock = dcn10_set_clock,
78c77382 AK	75	.get_clock = dcn10_get_clock,
f42ea55b AK	76	.program_triplebuffer = dcn20_program_triple_buffer,
	77	.enable_writeback = dcn20_enable_writeback,
	78	.disable_writeback = dcn20_disable_writeback,
	79	.dmdata_status_done = dcn20_dmdata_status_done,
	80	.program_dmdata_engine = dcn20_program_dmdata_engine,
	81	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
	82	.init_sys_ctx = dcn20_init_sys_ctx,
	83	.init_vm_ctx = dcn20_init_vm_ctx,
	84	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
	85	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
	86	};
	87
	88	static const struct hwseq_private_funcs dcn20_private_funcs = {
	89	.init_pipes = dcn10_init_pipes,
	90	.update_plane_addr = dcn20_update_plane_addr,
	91	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
	92	.update_mpcc = dcn20_update_mpcc,
	93	.set_input_transfer_func = dcn20_set_input_transfer_func,
	94	.set_output_transfer_func = dcn20_set_output_transfer_func,
	95	.power_down = dce110_power_down,
	96	.enable_display_power_gating = dcn10_dummy_display_power_gating,
	97	.blank_pixel_data = dcn20_blank_pixel_data,
	98	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
	99	.enable_stream_timing = dcn20_enable_stream_timing,
	100	.edp_backlight_control = dce110_edp_backlight_control,
accde06f AK	101	.is_panel_backlight_on = dce110_is_panel_backlight_on,
accde06f AK	102	.is_panel_powered_on = dce110_is_panel_powered_on,
f42ea55b AK	103	.disable_stream_gating = dcn20_disable_stream_gating,
	104	.enable_stream_gating = dcn20_enable_stream_gating,
	105	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
78c77382 AK	106	.did_underflow_occur = dcn10_did_underflow_occur,
	107	.init_blank = dcn20_init_blank,
	108	.disable_vga = dcn20_disable_vga,
	109	.bios_golden_init = dcn10_bios_golden_init,
	110	.plane_atomic_disable = dcn20_plane_atomic_disable,
	111	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
	112	.enable_power_gating_plane = dcn20_enable_power_gating_plane,
	113	.dpp_pg_control = dcn20_dpp_pg_control,
	114	.hubp_pg_control = dcn20_hubp_pg_control,
78c77382	115	.update_odm = dcn20_update_odm,
78c77382 AK	116	.dsc_pg_control = dcn20_dsc_pg_control,
	117	.get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color,
	118	.get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color,
	119	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
	120	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
	121	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
	122	.dccg_init = dcn20_dccg_init,
	123	.set_blend_lut = dcn20_set_blend_lut,
	124	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
78c77382 AK	125	};
	126
	127	void dcn20_hw_sequencer_construct(struct dc *dc)
	128	{
	129	dc->hwss = dcn20_funcs;
f42ea55b	130	dc->hwseq->funcs = dcn20_private_funcs;
78c77382 AK	131
	132	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
	133	dc->hwss.init_hw = dcn20_fpga_init_hw;
f42ea55b	134	dc->hwseq->funcs.init_pipes = NULL;
78c77382 AK	135	}
78c77382 AK	136	}