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Merge tag 'io_uring-5.7-2020-05-22' of git://git.kernel.dk/linux-block
[thirdparty/linux.git] / drivers / gpu / drm / amd / display / dc / dcn20 / dcn20_resource.c
CommitLineData
7ed4e635
HW		 1/*
2* Copyright 2016 Advanced Micro Devices, Inc.
6ca3928d 3 * Copyright 2019 Raptor Engineering, LLC
7ed4e635
HW		 4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
d7929c1e
AD		 27#include <linux/slab.h>
28
7ed4e635
HW		 29#include "dm_services.h"
30#include "dc.h"
31
78c77382
AK		 32#include "dcn20_init.h"
33
7ed4e635
HW		 34#include "resource.h"
35#include "include/irq_service_interface.h"
36#include "dcn20/dcn20_resource.h"
37
38#include "dcn10/dcn10_hubp.h"
39#include "dcn10/dcn10_ipp.h"
40#include "dcn20_hubbub.h"
41#include "dcn20_mpc.h"
42#include "dcn20_hubp.h"
43#include "irq/dcn20/irq_service_dcn20.h"
44#include "dcn20_dpp.h"
45#include "dcn20_optc.h"
46#include "dcn20_hwseq.h"
47#include "dce110/dce110_hw_sequencer.h"
278141f5 48#include "dcn10/dcn10_resource.h"
7ed4e635
HW		 49#include "dcn20_opp.h"
50
97bda032 51#include "dcn20_dsc.h"
97bda032 52
7ed4e635
HW		 53#include "dcn20_link_encoder.h"
54#include "dcn20_stream_encoder.h"
55#include "dce/dce_clock_source.h"
56#include "dce/dce_audio.h"
57#include "dce/dce_hwseq.h"
58#include "virtual/virtual_stream_encoder.h"
59#include "dce110/dce110_resource.h"
60#include "dml/display_mode_vba.h"
61#include "dcn20_dccg.h"
62#include "dcn20_vmid.h"
d9a07577 63#include "dc_link_ddc.h"
7ed4e635
HW		 64
65#include "navi10_ip_offset.h"
66
67#include "dcn/dcn_2_0_0_offset.h"
68#include "dcn/dcn_2_0_0_sh_mask.h"
a771ded8
RL		 69#include "dpcs/dpcs_2_0_0_offset.h"
70#include "dpcs/dpcs_2_0_0_sh_mask.h"
7ed4e635
HW		 71
72#include "nbio/nbio_2_3_offset.h"
73
bb21290f
CL		 74#include "dcn20/dcn20_dwb.h"
75#include "dcn20/dcn20_mmhubbub.h"
76
7ed4e635
HW		 77#include "mmhub/mmhub_2_0_0_offset.h"
78#include "mmhub/mmhub_2_0_0_sh_mask.h"
79
80#include "reg_helper.h"
81#include "dce/dce_abm.h"
82#include "dce/dce_dmcu.h"
83#include "dce/dce_aux.h"
84#include "dce/dce_i2c.h"
85#include "vm_helper.h"
86
87#include "amdgpu_socbb.h"
88
7ed4e635
HW		 89#define DC_LOGGER_INIT(logger)
90
91struct _vcs_dpi_ip_params_st dcn2_0_ip = {
92 .odm_capable = 1,
93 .gpuvm_enable = 0,
94 .hostvm_enable = 0,
95 .gpuvm_max_page_table_levels = 4,
96 .hostvm_max_page_table_levels = 4,
97 .hostvm_cached_page_table_levels = 0,
98 .pte_group_size_bytes = 2048,
97bda032 99 .num_dsc = 6,
7ed4e635
HW		 100 .rob_buffer_size_kbytes = 168,
101 .det_buffer_size_kbytes = 164,
102 .dpte_buffer_size_in_pte_reqs_luma = 84,
103 .pde_proc_buffer_size_64k_reqs = 48,
104 .dpp_output_buffer_pixels = 2560,
105 .opp_output_buffer_lines = 1,
106 .pixel_chunk_size_kbytes = 8,
107 .pte_chunk_size_kbytes = 2,
108 .meta_chunk_size_kbytes = 2,
109 .writeback_chunk_size_kbytes = 2,
110 .line_buffer_size_bits = 789504,
111 .is_line_buffer_bpp_fixed = 0,
112 .line_buffer_fixed_bpp = 0,
113 .dcc_supported = true,
114 .max_line_buffer_lines = 12,
115 .writeback_luma_buffer_size_kbytes = 12,
116 .writeback_chroma_buffer_size_kbytes = 8,
117 .writeback_chroma_line_buffer_width_pixels = 4,
118 .writeback_max_hscl_ratio = 1,
119 .writeback_max_vscl_ratio = 1,
120 .writeback_min_hscl_ratio = 1,
121 .writeback_min_vscl_ratio = 1,
122 .writeback_max_hscl_taps = 12,
123 .writeback_max_vscl_taps = 12,
124 .writeback_line_buffer_luma_buffer_size = 0,
125 .writeback_line_buffer_chroma_buffer_size = 14643,
126 .cursor_buffer_size = 8,
127 .cursor_chunk_size = 2,
128 .max_num_otg = 6,
129 .max_num_dpp = 6,
130 .max_num_wb = 1,
131 .max_dchub_pscl_bw_pix_per_clk = 4,
132 .max_pscl_lb_bw_pix_per_clk = 2,
133 .max_lb_vscl_bw_pix_per_clk = 4,
134 .max_vscl_hscl_bw_pix_per_clk = 4,
135 .max_hscl_ratio = 8,
136 .max_vscl_ratio = 8,
137 .hscl_mults = 4,
138 .vscl_mults = 4,
139 .max_hscl_taps = 8,
140 .max_vscl_taps = 8,
141 .dispclk_ramp_margin_percent = 1,
142 .underscan_factor = 1.10,
143 .min_vblank_lines = 32, //
144 .dppclk_delay_subtotal = 77, //
145 .dppclk_delay_scl_lb_only = 16,
146 .dppclk_delay_scl = 50,
147 .dppclk_delay_cnvc_formatter = 8,
148 .dppclk_delay_cnvc_cursor = 6,
149 .dispclk_delay_subtotal = 87, //
150 .dcfclk_cstate_latency = 10, // SRExitTime
151 .max_inter_dcn_tile_repeaters = 8,
152
153 .xfc_supported = true,
154 .xfc_fill_bw_overhead_percent = 10.0,
155 .xfc_fill_constant_bytes = 0,
8f174fdb 156 .number_of_cursors = 1,
7ed4e635
HW		 157};
158
a2c63407
Z		 159struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
160 .odm_capable = 1,
161 .gpuvm_enable = 0,
162 .hostvm_enable = 0,
163 .gpuvm_max_page_table_levels = 4,
164 .hostvm_max_page_table_levels = 4,
165 .hostvm_cached_page_table_levels = 0,
166 .num_dsc = 5,
167 .rob_buffer_size_kbytes = 168,
168 .det_buffer_size_kbytes = 164,
169 .dpte_buffer_size_in_pte_reqs_luma = 84,
170 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
171 .dpp_output_buffer_pixels = 2560,
172 .opp_output_buffer_lines = 1,
173 .pixel_chunk_size_kbytes = 8,
174 .pte_enable = 1,
175 .max_page_table_levels = 4,
176 .pte_chunk_size_kbytes = 2,
177 .meta_chunk_size_kbytes = 2,
178 .writeback_chunk_size_kbytes = 2,
179 .line_buffer_size_bits = 789504,
180 .is_line_buffer_bpp_fixed = 0,
181 .line_buffer_fixed_bpp = 0,
182 .dcc_supported = true,
183 .max_line_buffer_lines = 12,
184 .writeback_luma_buffer_size_kbytes = 12,
185 .writeback_chroma_buffer_size_kbytes = 8,
186 .writeback_chroma_line_buffer_width_pixels = 4,
187 .writeback_max_hscl_ratio = 1,
188 .writeback_max_vscl_ratio = 1,
189 .writeback_min_hscl_ratio = 1,
190 .writeback_min_vscl_ratio = 1,
191 .writeback_max_hscl_taps = 12,
192 .writeback_max_vscl_taps = 12,
193 .writeback_line_buffer_luma_buffer_size = 0,
194 .writeback_line_buffer_chroma_buffer_size = 14643,
195 .cursor_buffer_size = 8,
196 .cursor_chunk_size = 2,
197 .max_num_otg = 5,
198 .max_num_dpp = 5,
199 .max_num_wb = 1,
200 .max_dchub_pscl_bw_pix_per_clk = 4,
201 .max_pscl_lb_bw_pix_per_clk = 2,
202 .max_lb_vscl_bw_pix_per_clk = 4,
203 .max_vscl_hscl_bw_pix_per_clk = 4,
204 .max_hscl_ratio = 8,
205 .max_vscl_ratio = 8,
206 .hscl_mults = 4,
207 .vscl_mults = 4,
208 .max_hscl_taps = 8,
209 .max_vscl_taps = 8,
210 .dispclk_ramp_margin_percent = 1,
211 .underscan_factor = 1.10,
212 .min_vblank_lines = 32, //
213 .dppclk_delay_subtotal = 77, //
214 .dppclk_delay_scl_lb_only = 16,
215 .dppclk_delay_scl = 50,
216 .dppclk_delay_cnvc_formatter = 8,
217 .dppclk_delay_cnvc_cursor = 6,
218 .dispclk_delay_subtotal = 87, //
219 .dcfclk_cstate_latency = 10, // SRExitTime
220 .max_inter_dcn_tile_repeaters = 8,
221 .xfc_supported = true,
222 .xfc_fill_bw_overhead_percent = 10.0,
223 .xfc_fill_constant_bytes = 0,
8f174fdb
YS		 224 .ptoi_supported = 0,
225 .number_of_cursors = 1,
a2c63407
Z		 226};
227
fb6959ae
NK		 228struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
229 /* Defaults that get patched on driver load from firmware. */
230 .clock_limits = {
231 {
232 .state = 0,
233 .dcfclk_mhz = 560.0,
234 .fabricclk_mhz = 560.0,
235 .dispclk_mhz = 513.0,
236 .dppclk_mhz = 513.0,
237 .phyclk_mhz = 540.0,
238 .socclk_mhz = 560.0,
239 .dscclk_mhz = 171.0,
240 .dram_speed_mts = 8960.0,
241 },
242 {
243 .state = 1,
244 .dcfclk_mhz = 694.0,
245 .fabricclk_mhz = 694.0,
246 .dispclk_mhz = 642.0,
247 .dppclk_mhz = 642.0,
248 .phyclk_mhz = 600.0,
249 .socclk_mhz = 694.0,
250 .dscclk_mhz = 214.0,
251 .dram_speed_mts = 11104.0,
252 },
253 {
254 .state = 2,
255 .dcfclk_mhz = 875.0,
256 .fabricclk_mhz = 875.0,
257 .dispclk_mhz = 734.0,
258 .dppclk_mhz = 734.0,
259 .phyclk_mhz = 810.0,
260 .socclk_mhz = 875.0,
261 .dscclk_mhz = 245.0,
262 .dram_speed_mts = 14000.0,
263 },
264 {
265 .state = 3,
266 .dcfclk_mhz = 1000.0,
267 .fabricclk_mhz = 1000.0,
268 .dispclk_mhz = 1100.0,
269 .dppclk_mhz = 1100.0,
270 .phyclk_mhz = 810.0,
271 .socclk_mhz = 1000.0,
272 .dscclk_mhz = 367.0,
273 .dram_speed_mts = 16000.0,
274 },
275 {
276 .state = 4,
277 .dcfclk_mhz = 1200.0,
278 .fabricclk_mhz = 1200.0,
279 .dispclk_mhz = 1284.0,
280 .dppclk_mhz = 1284.0,
281 .phyclk_mhz = 810.0,
282 .socclk_mhz = 1200.0,
283 .dscclk_mhz = 428.0,
284 .dram_speed_mts = 16000.0,
285 },
286 /*Extra state, no dispclk ramping*/
287 {
288 .state = 5,
289 .dcfclk_mhz = 1200.0,
290 .fabricclk_mhz = 1200.0,
291 .dispclk_mhz = 1284.0,
292 .dppclk_mhz = 1284.0,
293 .phyclk_mhz = 810.0,
294 .socclk_mhz = 1200.0,
295 .dscclk_mhz = 428.0,
296 .dram_speed_mts = 16000.0,
297 },
298 },
299 .num_states = 5,
300 .sr_exit_time_us = 8.6,
301 .sr_enter_plus_exit_time_us = 10.9,
302 .urgent_latency_us = 4.0,
303 .urgent_latency_pixel_data_only_us = 4.0,
304 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
305 .urgent_latency_vm_data_only_us = 4.0,
306 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
307 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
308 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
309 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
310 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
311 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
312 .max_avg_sdp_bw_use_normal_percent = 40.0,
313 .max_avg_dram_bw_use_normal_percent = 40.0,
314 .writeback_latency_us = 12.0,
315 .ideal_dram_bw_after_urgent_percent = 40.0,
316 .max_request_size_bytes = 256,
317 .dram_channel_width_bytes = 2,
318 .fabric_datapath_to_dcn_data_return_bytes = 64,
319 .dcn_downspread_percent = 0.5,
320 .downspread_percent = 0.38,
321 .dram_page_open_time_ns = 50.0,
322 .dram_rw_turnaround_time_ns = 17.5,
323 .dram_return_buffer_per_channel_bytes = 8192,
324 .round_trip_ping_latency_dcfclk_cycles = 131,
325 .urgent_out_of_order_return_per_channel_bytes = 256,
326 .channel_interleave_bytes = 256,
327 .num_banks = 8,
328 .num_chans = 16,
329 .vmm_page_size_bytes = 4096,
330 .dram_clock_change_latency_us = 404.0,
331 .dummy_pstate_latency_us = 5.0,
332 .writeback_dram_clock_change_latency_us = 23.0,
333 .return_bus_width_bytes = 64,
334 .dispclk_dppclk_vco_speed_mhz = 3850,
335 .xfc_bus_transport_time_us = 20,
336 .xfc_xbuf_latency_tolerance_us = 4,
337 .use_urgent_burst_bw = 0
338};
7ed4e635 339
e1ab4a91
ML		 340struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
341 .clock_limits = {
342 {
343 .state = 0,
344 .dcfclk_mhz = 560.0,
345 .fabricclk_mhz = 560.0,
346 .dispclk_mhz = 513.0,
347 .dppclk_mhz = 513.0,
348 .phyclk_mhz = 540.0,
349 .socclk_mhz = 560.0,
350 .dscclk_mhz = 171.0,
351 .dram_speed_mts = 8960.0,
352 },
353 {
354 .state = 1,
355 .dcfclk_mhz = 694.0,
356 .fabricclk_mhz = 694.0,
357 .dispclk_mhz = 642.0,
358 .dppclk_mhz = 642.0,
359 .phyclk_mhz = 600.0,
360 .socclk_mhz = 694.0,
361 .dscclk_mhz = 214.0,
362 .dram_speed_mts = 11104.0,
363 },
364 {
365 .state = 2,
366 .dcfclk_mhz = 875.0,
367 .fabricclk_mhz = 875.0,
368 .dispclk_mhz = 734.0,
369 .dppclk_mhz = 734.0,
370 .phyclk_mhz = 810.0,
371 .socclk_mhz = 875.0,
372 .dscclk_mhz = 245.0,
373 .dram_speed_mts = 14000.0,
374 },
375 {
376 .state = 3,
377 .dcfclk_mhz = 1000.0,
378 .fabricclk_mhz = 1000.0,
379 .dispclk_mhz = 1100.0,
380 .dppclk_mhz = 1100.0,
381 .phyclk_mhz = 810.0,
382 .socclk_mhz = 1000.0,
383 .dscclk_mhz = 367.0,
384 .dram_speed_mts = 16000.0,
385 },
386 {
387 .state = 4,
388 .dcfclk_mhz = 1200.0,
389 .fabricclk_mhz = 1200.0,
390 .dispclk_mhz = 1284.0,
391 .dppclk_mhz = 1284.0,
392 .phyclk_mhz = 810.0,
393 .socclk_mhz = 1200.0,
394 .dscclk_mhz = 428.0,
395 .dram_speed_mts = 16000.0,
396 },
397 /*Extra state, no dispclk ramping*/
398 {
399 .state = 5,
400 .dcfclk_mhz = 1200.0,
401 .fabricclk_mhz = 1200.0,
402 .dispclk_mhz = 1284.0,
403 .dppclk_mhz = 1284.0,
404 .phyclk_mhz = 810.0,
405 .socclk_mhz = 1200.0,
406 .dscclk_mhz = 428.0,
407 .dram_speed_mts = 16000.0,
408 },
409 },
410 .num_states = 5,
411 .sr_exit_time_us = 8.6,
412 .sr_enter_plus_exit_time_us = 10.9,
413 .urgent_latency_us = 4.0,
414 .urgent_latency_pixel_data_only_us = 4.0,
415 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
416 .urgent_latency_vm_data_only_us = 4.0,
417 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
418 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
419 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
420 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
421 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
422 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
423 .max_avg_sdp_bw_use_normal_percent = 40.0,
424 .max_avg_dram_bw_use_normal_percent = 40.0,
425 .writeback_latency_us = 12.0,
426 .ideal_dram_bw_after_urgent_percent = 40.0,
427 .max_request_size_bytes = 256,
428 .dram_channel_width_bytes = 2,
429 .fabric_datapath_to_dcn_data_return_bytes = 64,
430 .dcn_downspread_percent = 0.5,
431 .downspread_percent = 0.38,
432 .dram_page_open_time_ns = 50.0,
433 .dram_rw_turnaround_time_ns = 17.5,
434 .dram_return_buffer_per_channel_bytes = 8192,
435 .round_trip_ping_latency_dcfclk_cycles = 131,
436 .urgent_out_of_order_return_per_channel_bytes = 256,
437 .channel_interleave_bytes = 256,
438 .num_banks = 8,
439 .num_chans = 8,
440 .vmm_page_size_bytes = 4096,
441 .dram_clock_change_latency_us = 404.0,
442 .dummy_pstate_latency_us = 5.0,
443 .writeback_dram_clock_change_latency_us = 23.0,
444 .return_bus_width_bytes = 64,
445 .dispclk_dppclk_vco_speed_mhz = 3850,
446 .xfc_bus_transport_time_us = 20,
447 .xfc_xbuf_latency_tolerance_us = 4,
448 .use_urgent_burst_bw = 0
449};
450
675a9e38 451struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
7ed4e635
HW		 452
453#ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
454 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x210f
455 #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
456 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x220f
457 #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
458 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x230f
459 #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
460 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x240f
461 #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
462 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x250f
463 #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
464 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x260f
465 #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
466 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x270f
467 #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX 2
468#endif
469
470
471enum dcn20_clk_src_array_id {
472 DCN20_CLK_SRC_PLL0,
473 DCN20_CLK_SRC_PLL1,
474 DCN20_CLK_SRC_PLL2,
475 DCN20_CLK_SRC_PLL3,
476 DCN20_CLK_SRC_PLL4,
477 DCN20_CLK_SRC_PLL5,
478 DCN20_CLK_SRC_TOTAL
479};
480
481/* begin *********************
482 * macros to expend register list macro defined in HW object header file */
483
484/* DCN */
485/* TODO awful hack. fixup dcn20_dwb.h */
486#undef BASE_INNER
487#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
488
489#define BASE(seg) BASE_INNER(seg)
490
491#define SR(reg_name)\
492 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
493 mm ## reg_name
494
495#define SRI(reg_name, block, id)\
496 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
497 mm ## block ## id ## _ ## reg_name
498
499#define SRIR(var_name, reg_name, block, id)\
500 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
501 mm ## block ## id ## _ ## reg_name
502
503#define SRII(reg_name, block, id)\
504 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
505 mm ## block ## id ## _ ## reg_name
506
507#define DCCG_SRII(reg_name, block, id)\
508 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
509 mm ## block ## id ## _ ## reg_name
510
b2a7b0ce
AC		 511#define VUPDATE_SRII(reg_name, block, id)\
512 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
513 mm ## reg_name ## _ ## block ## id
514
7ed4e635
HW		 515/* NBIO */
516#define NBIO_BASE_INNER(seg) \
517 NBIO_BASE__INST0_SEG ## seg
518
519#define NBIO_BASE(seg) \
520 NBIO_BASE_INNER(seg)
521
522#define NBIO_SR(reg_name)\
523 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
524 mm ## reg_name
525
526/* MMHUB */
527#define MMHUB_BASE_INNER(seg) \
528 MMHUB_BASE__INST0_SEG ## seg
529
530#define MMHUB_BASE(seg) \
531 MMHUB_BASE_INNER(seg)
532
533#define MMHUB_SR(reg_name)\
534 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
535 mmMM ## reg_name
536
537static const struct bios_registers bios_regs = {
538 NBIO_SR(BIOS_SCRATCH_3),
539 NBIO_SR(BIOS_SCRATCH_6)
540};
541
542#define clk_src_regs(index, pllid)\
543[index] = {\
544 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
545}
546
547static const struct dce110_clk_src_regs clk_src_regs[] = {
548 clk_src_regs(0, A),
549 clk_src_regs(1, B),
550 clk_src_regs(2, C),
551 clk_src_regs(3, D),
552 clk_src_regs(4, E),
553 clk_src_regs(5, F)
554};
555
556static const struct dce110_clk_src_shift cs_shift = {
557 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
558};
559
560static const struct dce110_clk_src_mask cs_mask = {
561 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
562};
563
564static const struct dce_dmcu_registers dmcu_regs = {
565 DMCU_DCN10_REG_LIST()
566};
567
568static const struct dce_dmcu_shift dmcu_shift = {
569 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
570};
571
572static const struct dce_dmcu_mask dmcu_mask = {
573 DMCU_MASK_SH_LIST_DCN10(_MASK)
574};
d7c29549 575
7ed4e635 576static const struct dce_abm_registers abm_regs = {
d7c29549 577 ABM_DCN20_REG_LIST()
7ed4e635
HW		 578};
579
580static const struct dce_abm_shift abm_shift = {
d7c29549 581 ABM_MASK_SH_LIST_DCN20(__SHIFT)
7ed4e635
HW		 582};
583
584static const struct dce_abm_mask abm_mask = {
d7c29549 585 ABM_MASK_SH_LIST_DCN20(_MASK)
7ed4e635 586};
d7c29549 587
7ed4e635
HW		 588#define audio_regs(id)\
589[id] = {\
590 AUD_COMMON_REG_LIST(id)\
591}
592
593static const struct dce_audio_registers audio_regs[] = {
594 audio_regs(0),
595 audio_regs(1),
596 audio_regs(2),
597 audio_regs(3),
598 audio_regs(4),
599 audio_regs(5),
600 audio_regs(6),
601};
602
603#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
604 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
605 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
606 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
607
608static const struct dce_audio_shift audio_shift = {
609 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
610};
611
54a9bcb0 612static const struct dce_audio_mask audio_mask = {
7ed4e635
HW		 613 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
614};
615
616#define stream_enc_regs(id)\
617[id] = {\
618 SE_DCN2_REG_LIST(id)\
619}
620
621static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
622 stream_enc_regs(0),
623 stream_enc_regs(1),
624 stream_enc_regs(2),
625 stream_enc_regs(3),
626 stream_enc_regs(4),
627 stream_enc_regs(5),
628};
629
630static const struct dcn10_stream_encoder_shift se_shift = {
631 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
632};
633
634static const struct dcn10_stream_encoder_mask se_mask = {
635 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
636};
637
638
639#define aux_regs(id)\
640[id] = {\
641 DCN2_AUX_REG_LIST(id)\
642}
643
644static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
645 aux_regs(0),
646 aux_regs(1),
647 aux_regs(2),
648 aux_regs(3),
649 aux_regs(4),
650 aux_regs(5)
651};
652
653#define hpd_regs(id)\
654[id] = {\
655 HPD_REG_LIST(id)\
656}
657
658static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
659 hpd_regs(0),
660 hpd_regs(1),
661 hpd_regs(2),
662 hpd_regs(3),
663 hpd_regs(4),
664 hpd_regs(5)
665};
666
667#define link_regs(id, phyid)\
668[id] = {\
669 LE_DCN10_REG_LIST(id), \
670 UNIPHY_DCN2_REG_LIST(phyid), \
a771ded8 671 DPCS_DCN2_REG_LIST(id), \
7ed4e635
HW		 672 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
673}
674
675static const struct dcn10_link_enc_registers link_enc_regs[] = {
676 link_regs(0, A),
677 link_regs(1, B),
678 link_regs(2, C),
679 link_regs(3, D),
680 link_regs(4, E),
681 link_regs(5, F)
682};
683
684static const struct dcn10_link_enc_shift le_shift = {
a771ded8
RL		 685 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
686 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
7ed4e635
HW		 687};
688
689static const struct dcn10_link_enc_mask le_mask = {
a771ded8
RL		 690 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
691 DPCS_DCN2_MASK_SH_LIST(_MASK)
7ed4e635
HW		 692};
693
694#define ipp_regs(id)\
695[id] = {\
696 IPP_REG_LIST_DCN20(id),\
697}
698
699static const struct dcn10_ipp_registers ipp_regs[] = {
700 ipp_regs(0),
701 ipp_regs(1),
702 ipp_regs(2),
703 ipp_regs(3),
704 ipp_regs(4),
705 ipp_regs(5),
706};
707
708static const struct dcn10_ipp_shift ipp_shift = {
709 IPP_MASK_SH_LIST_DCN20(__SHIFT)
710};
711
712static const struct dcn10_ipp_mask ipp_mask = {
713 IPP_MASK_SH_LIST_DCN20(_MASK),
714};
715
716#define opp_regs(id)\
717[id] = {\
718 OPP_REG_LIST_DCN20(id),\
719}
720
721static const struct dcn20_opp_registers opp_regs[] = {
722 opp_regs(0),
723 opp_regs(1),
724 opp_regs(2),
725 opp_regs(3),
726 opp_regs(4),
727 opp_regs(5),
728};
729
730static const struct dcn20_opp_shift opp_shift = {
731 OPP_MASK_SH_LIST_DCN20(__SHIFT)
732};
733
734static const struct dcn20_opp_mask opp_mask = {
735 OPP_MASK_SH_LIST_DCN20(_MASK)
736};
737
738#define aux_engine_regs(id)\
739[id] = {\
740 AUX_COMMON_REG_LIST0(id), \
741 .AUXN_IMPCAL = 0, \
742 .AUXP_IMPCAL = 0, \
743 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
744}
745
746static const struct dce110_aux_registers aux_engine_regs[] = {
747 aux_engine_regs(0),
748 aux_engine_regs(1),
749 aux_engine_regs(2),
750 aux_engine_regs(3),
751 aux_engine_regs(4),
752 aux_engine_regs(5)
753};
754
755#define tf_regs(id)\
756[id] = {\
757 TF_REG_LIST_DCN20(id),\
d9eb70ae 758 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
7ed4e635
HW		 759}
760
761static const struct dcn2_dpp_registers tf_regs[] = {
762 tf_regs(0),
763 tf_regs(1),
764 tf_regs(2),
765 tf_regs(3),
766 tf_regs(4),
767 tf_regs(5),
768};
769
770static const struct dcn2_dpp_shift tf_shift = {
d56eaa7c 771 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
c1e34175 772 TF_DEBUG_REG_LIST_SH_DCN20
7ed4e635
HW		 773};
774
775static const struct dcn2_dpp_mask tf_mask = {
d56eaa7c 776 TF_REG_LIST_SH_MASK_DCN20(_MASK),
c1e34175 777 TF_DEBUG_REG_LIST_MASK_DCN20
7ed4e635
HW		 778};
779
bb21290f
CL		 780#define dwbc_regs_dcn2(id)\
781[id] = {\
782 DWBC_COMMON_REG_LIST_DCN2_0(id),\
783 }
784
785static const struct dcn20_dwbc_registers dwbc20_regs[] = {
786 dwbc_regs_dcn2(0),
787};
788
789static const struct dcn20_dwbc_shift dwbc20_shift = {
790 DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
791};
792
793static const struct dcn20_dwbc_mask dwbc20_mask = {
794 DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
795};
796
797#define mcif_wb_regs_dcn2(id)\
798[id] = {\
799 MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
800 }
801
802static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
803 mcif_wb_regs_dcn2(0),
804};
805
806static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
807 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
808};
809
810static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
811 MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
812};
813
7ed4e635
HW		 814static const struct dcn20_mpc_registers mpc_regs = {
815 MPC_REG_LIST_DCN2_0(0),
816 MPC_REG_LIST_DCN2_0(1),
817 MPC_REG_LIST_DCN2_0(2),
818 MPC_REG_LIST_DCN2_0(3),
819 MPC_REG_LIST_DCN2_0(4),
820 MPC_REG_LIST_DCN2_0(5),
821 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
822 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
823 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
824 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
825 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
826 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
e8027e08 827 MPC_DBG_REG_LIST_DCN2_0()
7ed4e635
HW		 828};
829
830static const struct dcn20_mpc_shift mpc_shift = {
c1e34175
NA		 831 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
832 MPC_DEBUG_REG_LIST_SH_DCN20
7ed4e635
HW		 833};
834
835static const struct dcn20_mpc_mask mpc_mask = {
c1e34175
NA		 836 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
837 MPC_DEBUG_REG_LIST_MASK_DCN20
7ed4e635
HW		 838};
839
840#define tg_regs(id)\
841[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
842
843
844static const struct dcn_optc_registers tg_regs[] = {
845 tg_regs(0),
846 tg_regs(1),
847 tg_regs(2),
848 tg_regs(3),
849 tg_regs(4),
850 tg_regs(5)
851};
852
853static const struct dcn_optc_shift tg_shift = {
854 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
855};
856
857static const struct dcn_optc_mask tg_mask = {
858 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
859};
860
861#define hubp_regs(id)\
862[id] = {\
863 HUBP_REG_LIST_DCN20(id)\
864}
865
866static const struct dcn_hubp2_registers hubp_regs[] = {
867 hubp_regs(0),
868 hubp_regs(1),
869 hubp_regs(2),
870 hubp_regs(3),
871 hubp_regs(4),
872 hubp_regs(5)
873};
874
875static const struct dcn_hubp2_shift hubp_shift = {
876 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
877};
878
879static const struct dcn_hubp2_mask hubp_mask = {
880 HUBP_MASK_SH_LIST_DCN20(_MASK)
881};
882
883static const struct dcn_hubbub_registers hubbub_reg = {
884 HUBBUB_REG_LIST_DCN20(0)
885};
886
887static const struct dcn_hubbub_shift hubbub_shift = {
888 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
889};
890
891static const struct dcn_hubbub_mask hubbub_mask = {
892 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
893};
894
895#define vmid_regs(id)\
896[id] = {\
897 DCN20_VMID_REG_LIST(id)\
898}
899
900static const struct dcn_vmid_registers vmid_regs[] = {
901 vmid_regs(0),
902 vmid_regs(1),
903 vmid_regs(2),
904 vmid_regs(3),
905 vmid_regs(4),
906 vmid_regs(5),
907 vmid_regs(6),
908 vmid_regs(7),
909 vmid_regs(8),
910 vmid_regs(9),
911 vmid_regs(10),
912 vmid_regs(11),
913 vmid_regs(12),
914 vmid_regs(13),
915 vmid_regs(14),
916 vmid_regs(15)
917};
918
919static const struct dcn20_vmid_shift vmid_shifts = {
920 DCN20_VMID_MASK_SH_LIST(__SHIFT)
921};
922
923static const struct dcn20_vmid_mask vmid_masks = {
924 DCN20_VMID_MASK_SH_LIST(_MASK)
925};
926
8276dd87 927static const struct dce110_aux_registers_shift aux_shift = {
928 DCN_AUX_MASK_SH_LIST(__SHIFT)
929};
930
931static const struct dce110_aux_registers_mask aux_mask = {
932 DCN_AUX_MASK_SH_LIST(_MASK)
933};
934
bf7f5ac3
YMM		 935static int map_transmitter_id_to_phy_instance(
936 enum transmitter transmitter)
937{
938 switch (transmitter) {
939 case TRANSMITTER_UNIPHY_A:
940 return 0;
941 break;
942 case TRANSMITTER_UNIPHY_B:
943 return 1;
944 break;
945 case TRANSMITTER_UNIPHY_C:
946 return 2;
947 break;
948 case TRANSMITTER_UNIPHY_D:
949 return 3;
950 break;
951 case TRANSMITTER_UNIPHY_E:
952 return 4;
953 break;
954 case TRANSMITTER_UNIPHY_F:
955 return 5;
956 break;
957 default:
958 ASSERT(0);
959 return 0;
960 }
961}
8276dd87 962
97bda032
HW		 963#define dsc_regsDCN20(id)\
964[id] = {\
965 DSC_REG_LIST_DCN20(id)\
966}
967
968static const struct dcn20_dsc_registers dsc_regs[] = {
969 dsc_regsDCN20(0),
970 dsc_regsDCN20(1),
971 dsc_regsDCN20(2),
972 dsc_regsDCN20(3),
973 dsc_regsDCN20(4),
974 dsc_regsDCN20(5)
975};
976
977static const struct dcn20_dsc_shift dsc_shift = {
978 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
979};
980
981static const struct dcn20_dsc_mask dsc_mask = {
982 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
983};
7ed4e635
HW		 984
985static const struct dccg_registers dccg_regs = {
986 DCCG_REG_LIST_DCN2()
987};
988
989static const struct dccg_shift dccg_shift = {
990 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
991};
992
993static const struct dccg_mask dccg_mask = {
994 DCCG_MASK_SH_LIST_DCN2(_MASK)
995};
996
997static const struct resource_caps res_cap_nv10 = {
998 .num_timing_generator = 6,
999 .num_opp = 6,
1000 .num_video_plane = 6,
1001 .num_audio = 7,
1002 .num_stream_encoder = 6,
1003 .num_pll = 6,
9cbee6ef 1004 .num_dwb = 1,
7ed4e635
HW		 1005 .num_ddc = 6,
1006 .num_vmid = 16,
97bda032 1007 .num_dsc = 6,
7ed4e635
HW		 1008};
1009
1010static const struct dc_plane_cap plane_cap = {
1011 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
1012 .blends_with_above = true,
1013 .blends_with_below = true,
7ed4e635 1014 .per_pixel_alpha = true,
5b1b2f20
AD		 1015
1016 .pixel_format_support = {
1017 .argb8888 = true,
1018 .nv12 = true,
cbec6477
SW		 1019 .fp16 = true,
1020 .p010 = true
5b1b2f20
AD		 1021 },
1022
1023 .max_upscale_factor = {
1024 .argb8888 = 16000,
1025 .nv12 = 16000,
1026 .fp16 = 1
1027 },
1028
1029 .max_downscale_factor = {
1030 .argb8888 = 250,
1031 .nv12 = 250,
1032 .fp16 = 1
1033 }
7ed4e635 1034};
2ebe1773
BL		 1035static const struct resource_caps res_cap_nv14 = {
1036 .num_timing_generator = 5,
1037 .num_opp = 5,
1038 .num_video_plane = 5,
1039 .num_audio = 6,
1040 .num_stream_encoder = 5,
1041 .num_pll = 5,
80df905d 1042 .num_dwb = 1,
2ebe1773 1043 .num_ddc = 5,
6bb27085
ZL		 1044 .num_vmid = 16,
1045 .num_dsc = 5,
2ebe1773 1046};
7ed4e635
HW		 1047
1048static const struct dc_debug_options debug_defaults_drv = {
f0a574c9 1049 .disable_dmcu = false,
7ed4e635
HW		 1050 .force_abm_enable = false,
1051 .timing_trace = false,
1052 .clock_trace = true,
1053 .disable_pplib_clock_request = true,
1054 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
4d25a0d5 1055 .force_single_disp_pipe_split = false,
7ed4e635
HW		 1056 .disable_dcc = DCC_ENABLE,
1057 .vsr_support = true,
1058 .performance_trace = false,
1059 .max_downscale_src_width = 5120,/*upto 5K*/
1060 .disable_pplib_wm_range = false,
1061 .scl_reset_length10 = true,
9e14d4f1 1062 .sanity_checks = false,
7ed4e635 1063 .disable_tri_buf = true,
1a7d296d 1064 .underflow_assert_delay_us = 0xFFFFFFFF,
7ed4e635
HW		 1065};
1066
1067static const struct dc_debug_options debug_defaults_diags = {
f0a574c9 1068 .disable_dmcu = false,
7ed4e635
HW		 1069 .force_abm_enable = false,
1070 .timing_trace = true,
1071 .clock_trace = true,
1072 .disable_dpp_power_gate = true,
1073 .disable_hubp_power_gate = true,
1074 .disable_clock_gate = true,
1075 .disable_pplib_clock_request = true,
1076 .disable_pplib_wm_range = true,
1077 .disable_stutter = true,
1078 .scl_reset_length10 = true,
1a7d296d 1079 .underflow_assert_delay_us = 0xFFFFFFFF,
7ed4e635
HW		 1080};
1081
1082void dcn20_dpp_destroy(struct dpp **dpp)
1083{
1084 kfree(TO_DCN20_DPP(*dpp));
1085 *dpp = NULL;
1086}
1087
1088struct dpp *dcn20_dpp_create(
1089 struct dc_context *ctx,
1090 uint32_t inst)
1091{
1092 struct dcn20_dpp *dpp =
1093 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
1094
1095 if (!dpp)
1096 return NULL;
1097
1098 if (dpp2_construct(dpp, ctx, inst,
1099 &tf_regs[inst], &tf_shift, &tf_mask))
1100 return &dpp->base;
1101
1102 BREAK_TO_DEBUGGER();
1103 kfree(dpp);
1104 return NULL;
1105}
1106
1107struct input_pixel_processor *dcn20_ipp_create(
1108 struct dc_context *ctx, uint32_t inst)
1109{
1110 struct dcn10_ipp *ipp =
1111 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
1112
1113 if (!ipp) {
1114 BREAK_TO_DEBUGGER();
1115 return NULL;
1116 }
1117
1118 dcn20_ipp_construct(ipp, ctx, inst,
1119 &ipp_regs[inst], &ipp_shift, &ipp_mask);
1120 return &ipp->base;
1121}
1122
1123
1124struct output_pixel_processor *dcn20_opp_create(
1125 struct dc_context *ctx, uint32_t inst)
1126{
1127 struct dcn20_opp *opp =
1128 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1129
1130 if (!opp) {
1131 BREAK_TO_DEBUGGER();
1132 return NULL;
1133 }
1134
1135 dcn20_opp_construct(opp, ctx, inst,
1136 &opp_regs[inst], &opp_shift, &opp_mask);
1137 return &opp->base;
1138}
1139
1140struct dce_aux *dcn20_aux_engine_create(
1141 struct dc_context *ctx,
1142 uint32_t inst)
1143{
1144 struct aux_engine_dce110 *aux_engine =
1145 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1146
1147 if (!aux_engine)
1148 return NULL;
1149
1150 dce110_aux_engine_construct(aux_engine, ctx, inst,
1151 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
8276dd87 1152 &aux_engine_regs[inst],
1153 &aux_mask,
f6040a43 1154 &aux_shift,
1155 ctx->dc->caps.extended_aux_timeout_support);
7ed4e635
HW		 1156
1157 return &aux_engine->base;
1158}
1159#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
1160
1161static const struct dce_i2c_registers i2c_hw_regs[] = {
1162 i2c_inst_regs(1),
1163 i2c_inst_regs(2),
1164 i2c_inst_regs(3),
1165 i2c_inst_regs(4),
1166 i2c_inst_regs(5),
1167 i2c_inst_regs(6),
1168};
1169
1170static const struct dce_i2c_shift i2c_shifts = {
1171 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
1172};
1173
1174static const struct dce_i2c_mask i2c_masks = {
1175 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
1176};
1177
1178struct dce_i2c_hw *dcn20_i2c_hw_create(
1179 struct dc_context *ctx,
1180 uint32_t inst)
1181{
1182 struct dce_i2c_hw *dce_i2c_hw =
1183 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1184
1185 if (!dce_i2c_hw)
1186 return NULL;
1187
1188 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1189 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1190
1191 return dce_i2c_hw;
1192}
1193struct mpc *dcn20_mpc_create(struct dc_context *ctx)
1194{
1195 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1196 GFP_KERNEL);
1197
1198 if (!mpc20)
1199 return NULL;
1200
1201 dcn20_mpc_construct(mpc20, ctx,
1202 &mpc_regs,
1203 &mpc_shift,
1204 &mpc_mask,
1205 6);
1206
1207 return &mpc20->base;
1208}
1209
1210struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
1211{
1212 int i;
1213 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1214 GFP_KERNEL);
1215
1216 if (!hubbub)
1217 return NULL;
1218
1219 hubbub2_construct(hubbub, ctx,
1220 &hubbub_reg,
1221 &hubbub_shift,
1222 &hubbub_mask);
1223
1224 for (i = 0; i < res_cap_nv10.num_vmid; i++) {
1225 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1226
1227 vmid->ctx = ctx;
1228
1229 vmid->regs = &vmid_regs[i];
1230 vmid->shifts = &vmid_shifts;
1231 vmid->masks = &vmid_masks;
1232 }
1233
1234 return &hubbub->base;
1235}
1236
1237struct timing_generator *dcn20_timing_generator_create(
1238 struct dc_context *ctx,
1239 uint32_t instance)
1240{
1241 struct optc *tgn10 =
1242 kzalloc(sizeof(struct optc), GFP_KERNEL);
1243
1244 if (!tgn10)
1245 return NULL;
1246
1247 tgn10->base.inst = instance;
1248 tgn10->base.ctx = ctx;
1249
1250 tgn10->tg_regs = &tg_regs[instance];
1251 tgn10->tg_shift = &tg_shift;
1252 tgn10->tg_mask = &tg_mask;
1253
1254 dcn20_timing_generator_init(tgn10);
1255
1256 return &tgn10->base;
1257}
1258
1259static const struct encoder_feature_support link_enc_feature = {
1260 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1261 .max_hdmi_pixel_clock = 600000,
1262 .hdmi_ycbcr420_supported = true,
1263 .dp_ycbcr420_supported = true,
c14b726e 1264 .fec_supported = true,
7ed4e635
HW		 1265 .flags.bits.IS_HBR2_CAPABLE = true,
1266 .flags.bits.IS_HBR3_CAPABLE = true,
1267 .flags.bits.IS_TPS3_CAPABLE = true,
1268 .flags.bits.IS_TPS4_CAPABLE = true
1269};
1270
1271struct link_encoder *dcn20_link_encoder_create(
1272 const struct encoder_init_data *enc_init_data)
1273{
1274 struct dcn20_link_encoder *enc20 =
1275 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
bf7f5ac3 1276 int link_regs_id;
7ed4e635
HW		 1277
1278 if (!enc20)
1279 return NULL;
1280
bf7f5ac3
YMM		 1281 link_regs_id =
1282 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1283
7ed4e635
HW		 1284 dcn20_link_encoder_construct(enc20,
1285 enc_init_data,
1286 &link_enc_feature,
bf7f5ac3 1287 &link_enc_regs[link_regs_id],
7ed4e635
HW		 1288 &link_enc_aux_regs[enc_init_data->channel - 1],
1289 &link_enc_hpd_regs[enc_init_data->hpd_source],
1290 &le_shift,
1291 &le_mask);
1292
1293 return &enc20->enc10.base;
1294}
1295
1296struct clock_source *dcn20_clock_source_create(
1297 struct dc_context *ctx,
1298 struct dc_bios *bios,
1299 enum clock_source_id id,
1300 const struct dce110_clk_src_regs *regs,
1301 bool dp_clk_src)
1302{
1303 struct dce110_clk_src *clk_src =
1304 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1305
1306 if (!clk_src)
1307 return NULL;
1308
1309 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1310 regs, &cs_shift, &cs_mask)) {
1311 clk_src->base.dp_clk_src = dp_clk_src;
1312 return &clk_src->base;
1313 }
1314
cabe144b 1315 kfree(clk_src);
7ed4e635
HW		 1316 BREAK_TO_DEBUGGER();
1317 return NULL;
1318}
1319
1320static void read_dce_straps(
1321 struct dc_context *ctx,
1322 struct resource_straps *straps)
1323{
1324 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1325 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1326}
1327
1328static struct audio *dcn20_create_audio(
1329 struct dc_context *ctx, unsigned int inst)
1330{
1331 return dce_audio_create(ctx, inst,
1332 &audio_regs[inst], &audio_shift, &audio_mask);
1333}
1334
1335struct stream_encoder *dcn20_stream_encoder_create(
1336 enum engine_id eng_id,
1337 struct dc_context *ctx)
1338{
1339 struct dcn10_stream_encoder *enc1 =
1340 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1341
1342 if (!enc1)
1343 return NULL;
1344
9fd4c2d7
ZL		 1345 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1346 if (eng_id >= ENGINE_ID_DIGD)
1347 eng_id++;
1348 }
1349
7ed4e635
HW		 1350 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1351 &stream_enc_regs[eng_id],
1352 &se_shift, &se_mask);
1353
1354 return &enc1->base;
1355}
1356
1357static const struct dce_hwseq_registers hwseq_reg = {
1358 HWSEQ_DCN2_REG_LIST()
1359};
1360
1361static const struct dce_hwseq_shift hwseq_shift = {
1362 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1363};
1364
1365static const struct dce_hwseq_mask hwseq_mask = {
1366 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1367};
1368
1369struct dce_hwseq *dcn20_hwseq_create(
1370 struct dc_context *ctx)
1371{
1372 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1373
1374 if (hws) {
1375 hws->ctx = ctx;
1376 hws->regs = &hwseq_reg;
1377 hws->shifts = &hwseq_shift;
1378 hws->masks = &hwseq_mask;
1379 }
1380 return hws;
1381}
1382
1383static const struct resource_create_funcs res_create_funcs = {
1384 .read_dce_straps = read_dce_straps,
1385 .create_audio = dcn20_create_audio,
1386 .create_stream_encoder = dcn20_stream_encoder_create,
1387 .create_hwseq = dcn20_hwseq_create,
1388};
1389
1390static const struct resource_create_funcs res_create_maximus_funcs = {
1391 .read_dce_straps = NULL,
1392 .create_audio = NULL,
1393 .create_stream_encoder = NULL,
1394 .create_hwseq = dcn20_hwseq_create,
1395};
1396
44e149bb
AD		 1397static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1398
7ed4e635
HW		 1399void dcn20_clock_source_destroy(struct clock_source **clk_src)
1400{
1401 kfree(TO_DCE110_CLK_SRC(*clk_src));
1402 *clk_src = NULL;
1403}
1404
97bda032
HW		 1405
1406struct display_stream_compressor *dcn20_dsc_create(
1407 struct dc_context *ctx, uint32_t inst)
1408{
1409 struct dcn20_dsc *dsc =
1410 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1411
1412 if (!dsc) {
1413 BREAK_TO_DEBUGGER();
1414 return NULL;
1415 }
1416
1417 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1418 return &dsc->base;
1419}
1420
1421void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1422{
1423 kfree(container_of(*dsc, struct dcn20_dsc, base));
1424 *dsc = NULL;
1425}
1426
7ed4e635 1427
d9e32672 1428static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
7ed4e635
HW		 1429{
1430 unsigned int i;
1431
1432 for (i = 0; i < pool->base.stream_enc_count; i++) {
1433 if (pool->base.stream_enc[i] != NULL) {
1434 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1435 pool->base.stream_enc[i] = NULL;
1436 }
1437 }
1438
97bda032
HW		 1439 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1440 if (pool->base.dscs[i] != NULL)
1441 dcn20_dsc_destroy(&pool->base.dscs[i]);
1442 }
7ed4e635
HW		 1443
1444 if (pool->base.mpc != NULL) {
1445 kfree(TO_DCN20_MPC(pool->base.mpc));
1446 pool->base.mpc = NULL;
1447 }
1448 if (pool->base.hubbub != NULL) {
1449 kfree(pool->base.hubbub);
1450 pool->base.hubbub = NULL;
1451 }
1452 for (i = 0; i < pool->base.pipe_count; i++) {
1453 if (pool->base.dpps[i] != NULL)
1454 dcn20_dpp_destroy(&pool->base.dpps[i]);
1455
1456 if (pool->base.ipps[i] != NULL)
1457 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1458
1459 if (pool->base.hubps[i] != NULL) {
1460 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1461 pool->base.hubps[i] = NULL;
1462 }
1463
1464 if (pool->base.irqs != NULL) {
1465 dal_irq_service_destroy(&pool->base.irqs);
1466 }
1467 }
1468
1469 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1470 if (pool->base.engines[i] != NULL)
1471 dce110_engine_destroy(&pool->base.engines[i]);
1472 if (pool->base.hw_i2cs[i] != NULL) {
1473 kfree(pool->base.hw_i2cs[i]);
1474 pool->base.hw_i2cs[i] = NULL;
1475 }
1476 if (pool->base.sw_i2cs[i] != NULL) {
1477 kfree(pool->base.sw_i2cs[i]);
1478 pool->base.sw_i2cs[i] = NULL;
1479 }
1480 }
1481
1482 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1483 if (pool->base.opps[i] != NULL)
1484 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1485 }
1486
1487 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1488 if (pool->base.timing_generators[i] != NULL) {
1489 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1490 pool->base.timing_generators[i] = NULL;
1491 }
1492 }
1493
bb21290f
CL		 1494 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1495 if (pool->base.dwbc[i] != NULL) {
1496 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1497 pool->base.dwbc[i] = NULL;
1498 }
1499 if (pool->base.mcif_wb[i] != NULL) {
1500 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1501 pool->base.mcif_wb[i] = NULL;
1502 }
1503 }
1504
7ed4e635
HW		 1505 for (i = 0; i < pool->base.audio_count; i++) {
1506 if (pool->base.audios[i])
1507 dce_aud_destroy(&pool->base.audios[i]);
1508 }
1509
1510 for (i = 0; i < pool->base.clk_src_count; i++) {
1511 if (pool->base.clock_sources[i] != NULL) {
1512 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1513 pool->base.clock_sources[i] = NULL;
1514 }
1515 }
1516
1517 if (pool->base.dp_clock_source != NULL) {
1518 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1519 pool->base.dp_clock_source = NULL;
1520 }
1521
1522
1523 if (pool->base.abm != NULL)
1524 dce_abm_destroy(&pool->base.abm);
1525
1526 if (pool->base.dmcu != NULL)
1527 dce_dmcu_destroy(&pool->base.dmcu);
1528
1529 if (pool->base.dccg != NULL)
1530 dcn_dccg_destroy(&pool->base.dccg);
1531
1532 if (pool->base.pp_smu != NULL)
1533 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1534
d9a07577
JL		 1535 if (pool->base.oem_device != NULL)
1536 dal_ddc_service_destroy(&pool->base.oem_device);
7ed4e635
HW		 1537}
1538
1539struct hubp *dcn20_hubp_create(
1540 struct dc_context *ctx,
1541 uint32_t inst)
1542{
1543 struct dcn20_hubp *hubp2 =
1544 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1545
1546 if (!hubp2)
1547 return NULL;
1548
1549 if (hubp2_construct(hubp2, ctx, inst,
1550 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1551 return &hubp2->base;
1552
1553 BREAK_TO_DEBUGGER();
1554 kfree(hubp2);
1555 return NULL;
1556}
1557
1558static void get_pixel_clock_parameters(
1559 struct pipe_ctx *pipe_ctx,
1560 struct pixel_clk_params *pixel_clk_params)
1561{
1562 const struct dc_stream_state *stream = pipe_ctx->stream;
b1f6d01c
DL		 1563 struct pipe_ctx *odm_pipe;
1564 int opp_cnt = 1;
1565
1566 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1567 opp_cnt++;
7ed4e635
HW		 1568
1569 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1570 pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1571 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1572 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1573 /* TODO: un-hardcode*/
1574 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1575 LINK_RATE_REF_FREQ_IN_KHZ;
1576 pixel_clk_params->flags.ENABLE_SS = 0;
1577 pixel_clk_params->color_depth =
1578 stream->timing.display_color_depth;
1579 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1580 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1581
1582 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1583 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1584
b1f6d01c
DL		 1585 if (opp_cnt == 4)
1586 pixel_clk_params->requested_pix_clk_100hz /= 4;
78c77382 1587 else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
7ed4e635
HW		 1588 pixel_clk_params->requested_pix_clk_100hz /= 2;
1589
1590 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1591 pixel_clk_params->requested_pix_clk_100hz *= 2;
1592
1593}
1594
1595static void build_clamping_params(struct dc_stream_state *stream)
1596{
1597 stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1598 stream->clamping.c_depth = stream->timing.display_color_depth;
1599 stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1600}
1601
1602static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1603{
1604
1605 get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1606
1607 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1608 pipe_ctx->clock_source,
1609 &pipe_ctx->stream_res.pix_clk_params,
1610 &pipe_ctx->pll_settings);
1611
1612 pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1613
1614 resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1615 &pipe_ctx->stream->bit_depth_params);
1616 build_clamping_params(pipe_ctx->stream);
1617
1618 return DC_OK;
1619}
1620
1621enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1622{
1623 enum dc_status status = DC_OK;
1624 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1625
1626 /*TODO Seems unneeded anymore */
1627 /* if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1628 if (stream != NULL && old_context->streams[i] != NULL) {
1629 todo: shouldn't have to copy missing parameter here
1630 resource_build_bit_depth_reduction_params(stream,
1631 &stream->bit_depth_params);
1632 stream->clamping.pixel_encoding =
1633 stream->timing.pixel_encoding;
1634
1635 resource_build_bit_depth_reduction_params(stream,
1636 &stream->bit_depth_params);
1637 build_clamping_params(stream);
1638
1639 continue;
1640 }
1641 }
1642 */
1643
1644 if (!pipe_ctx)
1645 return DC_ERROR_UNEXPECTED;
1646
1647
1648 status = build_pipe_hw_param(pipe_ctx);
1649
1650 return status;
1651}
1652
97bda032 1653
c9ae6e16
NC		 1654static void acquire_dsc(struct resource_context *res_ctx,
1655 const struct resource_pool *pool,
eab4bb97
NC		 1656 struct display_stream_compressor **dsc,
1657 int pipe_idx)
97bda032
HW		 1658{
1659 int i;
c9ae6e16
NC		 1660
1661 ASSERT(*dsc == NULL);
1662 *dsc = NULL;
97bda032 1663
eab4bb97
NC		 1664 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1665 *dsc = pool->dscs[pipe_idx];
1666 res_ctx->is_dsc_acquired[pipe_idx] = true;
1667 return;
1668 }
1669
97bda032
HW		 1670 /* Find first free DSC */
1671 for (i = 0; i < pool->res_cap->num_dsc; i++)
1672 if (!res_ctx->is_dsc_acquired[i]) {
c9ae6e16 1673 *dsc = pool->dscs[i];
97bda032
HW		 1674 res_ctx->is_dsc_acquired[i] = true;
1675 break;
1676 }
97bda032
HW		 1677}
1678
7287a675 1679void dcn20_release_dsc(struct resource_context *res_ctx,
97bda032 1680 const struct resource_pool *pool,
c9ae6e16 1681 struct display_stream_compressor **dsc)
97bda032
HW		 1682{
1683 int i;
1684
1685 for (i = 0; i < pool->res_cap->num_dsc; i++)
c9ae6e16 1686 if (pool->dscs[i] == *dsc) {
97bda032 1687 res_ctx->is_dsc_acquired[i] = false;
c9ae6e16 1688 *dsc = NULL;
97bda032
HW		 1689 break;
1690 }
1691}
1692
7ed4e635 1693
7ed4e635 1694
8c20a1ed 1695enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
c9ae6e16
NC		 1696 struct dc_state *dc_ctx,
1697 struct dc_stream_state *dc_stream)
1698{
1699 enum dc_status result = DC_OK;
1700 int i;
1701 const struct resource_pool *pool = dc->res_pool;
97bda032 1702
c9ae6e16
NC		 1703 /* Get a DSC if required and available */
1704 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1705 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
97bda032 1706
c9ae6e16
NC		 1707 if (pipe_ctx->stream != dc_stream)
1708 continue;
97bda032 1709
8c20a1ed
DF		 1710 if (pipe_ctx->stream_res.dsc)
1711 continue;
1712
eab4bb97 1713 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i);
97bda032 1714
c9ae6e16
NC		 1715 /* The number of DSCs can be less than the number of pipes */
1716 if (!pipe_ctx->stream_res.dsc) {
c9ae6e16 1717 result = DC_NO_DSC_RESOURCE;
97bda032 1718 }
7ed4e635 1719
c9ae6e16
NC		 1720 break;
1721 }
7ed4e635
HW		 1722
1723 return result;
1724}
1725
1726
ba32c50f 1727static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
c9ae6e16
NC		 1728 struct dc_state *new_ctx,
1729 struct dc_stream_state *dc_stream)
7ed4e635
HW		 1730{
1731 struct pipe_ctx *pipe_ctx = NULL;
1732 int i;
1733
7ed4e635
HW		 1734 for (i = 0; i < MAX_PIPES; i++) {
1735 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1736 pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
b1f6d01c
DL		 1737
1738 if (pipe_ctx->stream_res.dsc)
7287a675 1739 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
7ed4e635
HW		 1740 }
1741 }
1742
1743 if (!pipe_ctx)
1744 return DC_ERROR_UNEXPECTED;
b1f6d01c
DL		 1745 else
1746 return DC_OK;
7ed4e635 1747}
c9ae6e16
NC		 1748
1749
1750enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1751{
1752 enum dc_status result = DC_ERROR_UNEXPECTED;
1753
1754 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1755
1756 if (result == DC_OK)
1757 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1758
c9ae6e16
NC		 1759 /* Get a DSC if required and available */
1760 if (result == DC_OK && dc_stream->timing.flags.DSC)
8c20a1ed 1761 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
c9ae6e16
NC		 1762
1763 if (result == DC_OK)
1764 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1765
1766 return result;
1767}
1768
1769
1770enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1771{
1772 enum dc_status result = DC_OK;
1773
ba32c50f 1774 result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
c9ae6e16
NC		 1775
1776 return result;
1777}
7ed4e635
HW		 1778
1779
1780static void swizzle_to_dml_params(
1781 enum swizzle_mode_values swizzle,
1782 unsigned int *sw_mode)
1783{
1784 switch (swizzle) {
1785 case DC_SW_LINEAR:
1786 *sw_mode = dm_sw_linear;
1787 break;
1788 case DC_SW_4KB_S:
1789 *sw_mode = dm_sw_4kb_s;
1790 break;
1791 case DC_SW_4KB_S_X:
1792 *sw_mode = dm_sw_4kb_s_x;
1793 break;
1794 case DC_SW_4KB_D:
1795 *sw_mode = dm_sw_4kb_d;
1796 break;
1797 case DC_SW_4KB_D_X:
1798 *sw_mode = dm_sw_4kb_d_x;
1799 break;
1800 case DC_SW_64KB_S:
1801 *sw_mode = dm_sw_64kb_s;
1802 break;
1803 case DC_SW_64KB_S_X:
1804 *sw_mode = dm_sw_64kb_s_x;
1805 break;
1806 case DC_SW_64KB_S_T:
1807 *sw_mode = dm_sw_64kb_s_t;
1808 break;
1809 case DC_SW_64KB_D:
1810 *sw_mode = dm_sw_64kb_d;
1811 break;
1812 case DC_SW_64KB_D_X:
1813 *sw_mode = dm_sw_64kb_d_x;
1814 break;
1815 case DC_SW_64KB_D_T:
1816 *sw_mode = dm_sw_64kb_d_t;
1817 break;
1818 case DC_SW_64KB_R_X:
1819 *sw_mode = dm_sw_64kb_r_x;
1820 break;
1821 case DC_SW_VAR_S:
1822 *sw_mode = dm_sw_var_s;
1823 break;
1824 case DC_SW_VAR_S_X:
1825 *sw_mode = dm_sw_var_s_x;
1826 break;
1827 case DC_SW_VAR_D:
1828 *sw_mode = dm_sw_var_d;
1829 break;
1830 case DC_SW_VAR_D_X:
1831 *sw_mode = dm_sw_var_d_x;
1832 break;
1833
1834 default:
1835 ASSERT(0); /* Not supported */
1836 break;
1837 }
1838}
1839
b6bfba6c 1840bool dcn20_split_stream_for_odm(
b1f6d01c
DL		 1841 struct resource_context *res_ctx,
1842 const struct resource_pool *pool,
1843 struct pipe_ctx *prev_odm_pipe,
1844 struct pipe_ctx *next_odm_pipe)
1845{
1846 int pipe_idx = next_odm_pipe->pipe_idx;
b1f6d01c
DL		 1847
1848 *next_odm_pipe = *prev_odm_pipe;
b1f6d01c
DL		 1849
1850 next_odm_pipe->pipe_idx = pipe_idx;
1851 next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1852 next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1853 next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1854 next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1855 next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1856 next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
b1f6d01c 1857 next_odm_pipe->stream_res.dsc = NULL;
b1f6d01c 1858 if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
b1f6d01c
DL		 1859 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1860 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1861 }
1862 prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1863 next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1864 ASSERT(next_odm_pipe->top_pipe == NULL);
1865
1866 if (prev_odm_pipe->plane_state) {
c0358809
DL		 1867 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1868 int new_width;
1869
b1f6d01c
DL		 1870 /* HACTIVE halved for odm combine */
1871 sd->h_active /= 2;
b1f6d01c
DL		 1872 /* Calculate new vp and recout for left pipe */
1873 /* Need at least 16 pixels width per side */
1874 if (sd->recout.x + 16 >= sd->h_active)
1875 return false;
1876 new_width = sd->h_active - sd->recout.x;
1877 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1878 sd->ratios.horz, sd->recout.width - new_width));
1879 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1880 sd->ratios.horz_c, sd->recout.width - new_width));
1881 sd->recout.width = new_width;
1882
1883 /* Calculate new vp and recout for right pipe */
1884 sd = &next_odm_pipe->plane_res.scl_data;
c0358809
DL		 1885 /* HACTIVE halved for odm combine */
1886 sd->h_active /= 2;
b1f6d01c
DL		 1887 /* Need at least 16 pixels width per side */
1888 if (new_width <= 16)
1889 return false;
c0358809 1890 new_width = sd->recout.width + sd->recout.x - sd->h_active;
b1f6d01c
DL		 1891 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1892 sd->ratios.horz, sd->recout.width - new_width));
1893 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1894 sd->ratios.horz_c, sd->recout.width - new_width));
1895 sd->recout.width = new_width;
1896 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1897 sd->ratios.horz, sd->h_active - sd->recout.x));
1898 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1899 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1900 sd->recout.x = 0;
1901 }
1902 next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
b1f6d01c 1903 if (next_odm_pipe->stream->timing.flags.DSC == 1) {
eab4bb97 1904 acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
b1f6d01c
DL		 1905 ASSERT(next_odm_pipe->stream_res.dsc);
1906 if (next_odm_pipe->stream_res.dsc == NULL)
1907 return false;
1908 }
b1f6d01c
DL		 1909
1910 return true;
1911}
1912
b6bfba6c 1913void dcn20_split_stream_for_mpc(
7ed4e635
HW		 1914 struct resource_context *res_ctx,
1915 const struct resource_pool *pool,
1916 struct pipe_ctx *primary_pipe,
b1f6d01c 1917 struct pipe_ctx *secondary_pipe)
7ed4e635
HW		 1918{
1919 int pipe_idx = secondary_pipe->pipe_idx;
7ed4e635 1920 struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
7ed4e635
HW		 1921
1922 *secondary_pipe = *primary_pipe;
1923 secondary_pipe->bottom_pipe = sec_bot_pipe;
1924
1925 secondary_pipe->pipe_idx = pipe_idx;
1926 secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1927 secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1928 secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1929 secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1930 secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1931 secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
c92b4c46 1932 secondary_pipe->stream_res.dsc = NULL;
7ed4e635
HW		 1933 if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1934 ASSERT(!secondary_pipe->bottom_pipe);
1935 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1936 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1937 }
1938 primary_pipe->bottom_pipe = secondary_pipe;
1939 secondary_pipe->top_pipe = primary_pipe;
1940
b1f6d01c
DL		 1941 ASSERT(primary_pipe->plane_state);
1942 resource_build_scaling_params(primary_pipe);
1943 resource_build_scaling_params(secondary_pipe);
7ed4e635
HW		 1944}
1945
1946void dcn20_populate_dml_writeback_from_context(
1947 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1948{
1949 int pipe_cnt, i;
1950
1951 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1952 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1953
1954 if (!res_ctx->pipe_ctx[i].stream)
1955 continue;
1956
1957 /* Set writeback information */
1958 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1959 pipes[pipe_cnt].dout.num_active_wb++;
1960 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1961 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1962 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1963 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1964 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1965 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1966 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1967 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1968 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1969 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1970 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1971 if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1972 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1973 else
1974 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
1975 } else
1976 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
1977
1978 pipe_cnt++;
1979 }
1980
1981}
1982
1983int dcn20_populate_dml_pipes_from_context(
2f488884 1984 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
7ed4e635
HW		 1985{
1986 int pipe_cnt, i;
1987 bool synchronized_vblank = true;
2f488884 1988 struct resource_context *res_ctx = &context->res_ctx;
7ed4e635
HW		 1989
1990 for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
1991 if (!res_ctx->pipe_ctx[i].stream)
1992 continue;
1993
1994 if (pipe_cnt < 0) {
1995 pipe_cnt = i;
1996 continue;
1997 }
785908cf 1998 if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable(
7ed4e635
HW		 1999 res_ctx->pipe_ctx[pipe_cnt].stream,
2000 res_ctx->pipe_ctx[i].stream)) {
2001 synchronized_vblank = false;
2002 break;
2003 }
2004 }
2005
2006 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2007 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
2f488884 2008 unsigned int v_total;
1075735e 2009 unsigned int front_porch;
03fd87db 2010 int output_bpc;
7ed4e635
HW		 2011
2012 if (!res_ctx->pipe_ctx[i].stream)
2013 continue;
2f488884
AL		 2014
2015 v_total = timing->v_total;
1075735e 2016 front_porch = timing->v_front_porch;
7ed4e635
HW		 2017 /* todo:
2018 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
2019 pipes[pipe_cnt].pipe.src.dcc = 0;
2020 pipes[pipe_cnt].pipe.src.vm = 0;*/
2021
5fc11598
DL		 2022 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2023
97bda032
HW		 2024 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
2025 /* todo: rotation?*/
2026 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
7ed4e635
HW		 2027 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
2028 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
2029 /* 1/2 vblank */
2030 pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
2f488884 2031 (v_total - timing->v_addressable
7ed4e635
HW		 2032 - timing->v_border_top - timing->v_border_bottom) / 2;
2033 /* 36 bytes dp, 32 hdmi */
2034 pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
2035 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
2036 }
2037 pipes[pipe_cnt].pipe.src.dcc = false;
2038 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
2039 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
2040 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
2041 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
2042 - timing->h_addressable
2043 - timing->h_border_left
2044 - timing->h_border_right;
1075735e 2045 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
7ed4e635
HW		 2046 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
2047 - timing->v_addressable
2048 - timing->v_border_top
2049 - timing->v_border_bottom;
2050 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
2f488884 2051 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
7ed4e635
HW		 2052 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
2053 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
2054 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
2055 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
2056 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2057 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
2058 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
1621f4c4 2059 pipes[pipe_cnt].dout.dp_lanes = 4;
8bb3d7e7
CL		 2060 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
2061 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
5bf24270
DL		 2062 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) {
2063 case 1:
5fc11598
DL		 2064 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
2065 break;
2066 default:
2067 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
2068 }
c0358809
DL		 2069 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2070 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
56260cbf
DL		 2071 == res_ctx->pipe_ctx[i].plane_state) {
2072 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
2073
2074 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
2075 == res_ctx->pipe_ctx[i].plane_state)
2076 first_pipe = first_pipe->top_pipe;
2077 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2078 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
c0358809
DL		 2079 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
2080
2081 while (first_pipe->prev_odm_pipe)
2082 first_pipe = first_pipe->prev_odm_pipe;
2083 pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2084 }
7ed4e635 2085
7ed4e635
HW		 2086 switch (res_ctx->pipe_ctx[i].stream->signal) {
2087 case SIGNAL_TYPE_DISPLAY_PORT_MST:
2088 case SIGNAL_TYPE_DISPLAY_PORT:
2089 pipes[pipe_cnt].dout.output_type = dm_dp;
2090 break;
2091 case SIGNAL_TYPE_EDP:
2092 pipes[pipe_cnt].dout.output_type = dm_edp;
2093 break;
2094 case SIGNAL_TYPE_HDMI_TYPE_A:
2095 case SIGNAL_TYPE_DVI_SINGLE_LINK:
2096 case SIGNAL_TYPE_DVI_DUAL_LINK:
2097 pipes[pipe_cnt].dout.output_type = dm_hdmi;
2098 break;
2099 default:
2100 /* In case there is no signal, set dp with 4 lanes to allow max config */
2101 pipes[pipe_cnt].dout.output_type = dm_dp;
2102 pipes[pipe_cnt].dout.dp_lanes = 4;
2103 }
03fd87db
IB		 2104
2105 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
2106 case COLOR_DEPTH_666:
2107 output_bpc = 6;
2108 break;
2109 case COLOR_DEPTH_888:
2110 output_bpc = 8;
2111 break;
2112 case COLOR_DEPTH_101010:
2113 output_bpc = 10;
2114 break;
2115 case COLOR_DEPTH_121212:
2116 output_bpc = 12;
2117 break;
2118 case COLOR_DEPTH_141414:
2119 output_bpc = 14;
2120 break;
2121 case COLOR_DEPTH_161616:
2122 output_bpc = 16;
2123 break;
03fd87db
IB		 2124 case COLOR_DEPTH_999:
2125 output_bpc = 9;
2126 break;
2127 case COLOR_DEPTH_111111:
2128 output_bpc = 11;
2129 break;
03fd87db
IB		 2130 default:
2131 output_bpc = 8;
2132 break;
2133 }
2134
7ed4e635
HW		 2135 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
2136 case PIXEL_ENCODING_RGB:
2137 case PIXEL_ENCODING_YCBCR444:
2138 pipes[pipe_cnt].dout.output_format = dm_444;
03fd87db 2139 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
7ed4e635
HW		 2140 break;
2141 case PIXEL_ENCODING_YCBCR420:
2142 pipes[pipe_cnt].dout.output_format = dm_420;
486cc0ee 2143 pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
7ed4e635
HW		 2144 break;
2145 case PIXEL_ENCODING_YCBCR422:
2146 if (true) /* todo */
2147 pipes[pipe_cnt].dout.output_format = dm_s422;
2148 else
2149 pipes[pipe_cnt].dout.output_format = dm_n422;
03fd87db 2150 pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
7ed4e635
HW		 2151 break;
2152 default:
2153 pipes[pipe_cnt].dout.output_format = dm_444;
03fd87db 2154 pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
7ed4e635 2155 }
7ed4e635 2156
486cc0ee
NC		 2157 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
2158 pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
2159
7ed4e635
HW		 2160 /* todo: default max for now, until there is logic reflecting this in dc*/
2161 pipes[pipe_cnt].dout.output_bpc = 12;
2162 /*
8f174fdb 2163 * For graphic plane, cursor number is 1, nv12 is 0
7ed4e635
HW		 2164 * bw calculations due to cursor on/off
2165 */
8f174fdb
YS		 2166 if (res_ctx->pipe_ctx[i].plane_state &&
2167 res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2168 pipes[pipe_cnt].pipe.src.num_cursors = 0;
2169 else
2170 pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
2171
ed07237c
IB		 2172 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
2173 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
7ed4e635
HW		 2174
2175 if (!res_ctx->pipe_ctx[i].plane_state) {
56260cbf 2176 pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
7ed4e635
HW		 2177 pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
2178 pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
2179 pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
2180 pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2181 if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2182 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2183 pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2184 if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
2185 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
71e6bd2a 2186 pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
5fc11598
DL		 2187 pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
2188 pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
2189 pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
7ed4e635
HW		 2190 pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
2191 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2192 pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
2193 pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
2194 pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width; /*when is_hsplit != 1*/
2195 pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
2196 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2197 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2198 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2199 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
2200 pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
2201 pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2f488884
AL		 2202 pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
2203 pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
56260cbf
DL		 2204
2205 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
2206 pipes[pipe_cnt].pipe.src.viewport_width /= 2;
2207 pipes[pipe_cnt].pipe.dest.recout_width /= 2;
2208 }
7ed4e635
HW		 2209 } else {
2210 struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
2211 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
2212
7ed4e635 2213 pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
56260cbf
DL		 2214 pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
2215 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
2216 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
7ed4e635
HW		 2217 pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
2218 || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
2219 pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport.y;
2220 pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c.y;
2221 pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport.width;
2222 pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c.width;
2223 pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport.height;
2224 pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c.height;
5fc11598 2225 pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
71e6bd2a 2226 pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
5fc11598
DL		 2227 pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
2228 pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
7ed4e635 2229 if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
12e2b2d4
DL		 2230 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2231 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
2232 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2233 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
7ed4e635 2234 } else {
12e2b2d4
DL		 2235 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2236 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
7ed4e635
HW		 2237 }
2238 pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
2239 pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2240 pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
7ed4e635 2241 pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
5bf24270
DL		 2242 pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
2243 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
2244 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
2245 else {
2246 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
2247
2248 while (split_pipe && split_pipe->plane_state == pln) {
2249 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2250 split_pipe = split_pipe->bottom_pipe;
2251 }
2252 split_pipe = res_ctx->pipe_ctx[i].top_pipe;
2253 while (split_pipe && split_pipe->plane_state == pln) {
2254 pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2255 split_pipe = split_pipe->top_pipe;
2256 }
7ed4e635
HW		 2257 }
2258
ed07237c 2259 pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
7ed4e635
HW		 2260 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2261 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2262 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2263 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2264 pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
2265 scl->ratios.vert.value != dc_fixpt_one.value
2266 || scl->ratios.horz.value != dc_fixpt_one.value
2267 || scl->ratios.vert_c.value != dc_fixpt_one.value
2268 || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
2269 || dc->debug.always_scale; /*support always scale*/
2270 pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2271 pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2272 pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2273 pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2274
b964e790
DL		 2275 pipes[pipe_cnt].pipe.src.macro_tile_size =
2276 swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
7ed4e635
HW		 2277 swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2278 &pipes[pipe_cnt].pipe.src.sw_mode);
2279
2280 switch (pln->format) {
2281 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2282 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2283 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2284 break;
2285 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2286 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2287 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2288 break;
2289 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2290 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2291 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2292 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2293 break;
2294 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2295 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2296 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2297 break;
2298 case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2299 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2300 break;
2301 default:
2302 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2303 break;
2304 }
2305 }
2306
2307 pipe_cnt++;
2308 }
2309
2310 /* populate writeback information */
2311 dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2312
2313 return pipe_cnt;
2314}
2315
2316unsigned int dcn20_calc_max_scaled_time(
2317 unsigned int time_per_pixel,
2318 enum mmhubbub_wbif_mode mode,
2319 unsigned int urgent_watermark)
2320{
2321 unsigned int time_per_byte = 0;
2322 unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
2323 unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
2324 unsigned int small_free_entry, max_free_entry;
2325 unsigned int buf_lh_capability;
2326 unsigned int max_scaled_time;
2327
2328 if (mode == PACKED_444) /* packed mode */
2329 time_per_byte = time_per_pixel/4;
2330 else if (mode == PLANAR_420_8BPC)
2331 time_per_byte = time_per_pixel;
2332 else if (mode == PLANAR_420_10BPC) /* p010 */
2333 time_per_byte = time_per_pixel * 819/1024;
2334
2335 if (time_per_byte == 0)
2336 time_per_byte = 1;
2337
2338 small_free_entry = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2339 max_free_entry = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2340 buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
2341 max_scaled_time = buf_lh_capability - urgent_watermark;
2342 return max_scaled_time;
2343}
2344
2345void dcn20_set_mcif_arb_params(
2346 struct dc *dc,
2347 struct dc_state *context,
2348 display_e2e_pipe_params_st *pipes,
2349 int pipe_cnt)
2350{
2351 enum mmhubbub_wbif_mode wbif_mode;
2352 struct mcif_arb_params *wb_arb_params;
2353 int i, j, k, dwb_pipe;
2354
2355 /* Writeback MCIF_WB arbitration parameters */
2356 dwb_pipe = 0;
2357 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2358
2359 if (!context->res_ctx.pipe_ctx[i].stream)
2360 continue;
2361
2362 for (j = 0; j < MAX_DWB_PIPES; j++) {
2363 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2364 continue;
2365
2366 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
2367 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2368
2369 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2370 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2371 wbif_mode = PLANAR_420_8BPC;
2372 else
2373 wbif_mode = PLANAR_420_10BPC;
2374 } else
2375 wbif_mode = PACKED_444;
2376
2377 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2378 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2379 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2380 }
2381 wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
2382 wb_arb_params->slice_lines = 32;
2383 wb_arb_params->arbitration_slice = 2;
2384 wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2385 wbif_mode,
2386 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
2387
2388 dwb_pipe++;
2389
2390 if (dwb_pipe >= MAX_DWB_PIPES)
2391 return;
2392 }
2393 if (dwb_pipe >= MAX_DWB_PIPES)
2394 return;
2395 }
2396}
2397
b6bfba6c 2398bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
0ba37b20
DL		 2399{
2400 int i;
2401
2402 /* Validate DSC config, dsc count validation is already done */
2403 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2404 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2405 struct dc_stream_state *stream = pipe_ctx->stream;
2406 struct dsc_config dsc_cfg;
b1f6d01c
DL		 2407 struct pipe_ctx *odm_pipe;
2408 int opp_cnt = 1;
2409
2410 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2411 opp_cnt++;
0ba37b20
DL		 2412
2413 /* Only need to validate top pipe */
b1f6d01c 2414 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
0ba37b20
DL		 2415 continue;
2416
b1f6d01c
DL		 2417 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2418 + stream->timing.h_border_right) / opp_cnt;
0ba37b20
DL		 2419 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2420 + stream->timing.v_border_bottom;
0ba37b20
DL		 2421 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2422 dsc_cfg.color_depth = stream->timing.display_color_depth;
df8e34ac 2423 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
0ba37b20 2424 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
b1f6d01c 2425 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
0ba37b20
DL		 2426
2427 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2428 return false;
2429 }
2430 return true;
2431}
0ba37b20 2432
b6bfba6c 2433struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
c681491a
JL		 2434 struct resource_context *res_ctx,
2435 const struct resource_pool *pool,
2436 const struct pipe_ctx *primary_pipe)
2437{
2438 struct pipe_ctx *secondary_pipe = NULL;
2439
2440 if (dc && primary_pipe) {
2441 int j;
2442 int preferred_pipe_idx = 0;
2443
2444 /* first check the prev dc state:
2445 * if this primary pipe has a bottom pipe in prev. state
2446 * and if the bottom pipe is still available (which it should be),
2447 * pick that pipe as secondary
b1f6d01c
DL		 2448 * Same logic applies for ODM pipes. Since mpo is not allowed with odm
2449 * check in else case.
c681491a
JL		 2450 */
2451 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2452 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
2453 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2454 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2455 secondary_pipe->pipe_idx = preferred_pipe_idx;
2456 }
b1f6d01c
DL		 2457 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2458 preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
2459 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2460 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2461 secondary_pipe->pipe_idx = preferred_pipe_idx;
2462 }
c681491a
JL		 2463 }
2464
2465 /*
2466 * if this primary pipe does not have a bottom pipe in prev. state
2467 * start backward and find a pipe that did not used to be a bottom pipe in
2468 * prev. dc state. This way we make sure we keep the same assignment as
2469 * last state and will not have to reprogram every pipe
2470 */
2471 if (secondary_pipe == NULL) {
2472 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
8b8eda01
DL		 2473 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
2474 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
c681491a
JL		 2475 preferred_pipe_idx = j;
2476
2477 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2478 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2479 secondary_pipe->pipe_idx = preferred_pipe_idx;
2480 break;
2481 }
2482 }
2483 }
2484 }
2485 /*
2486 * We should never hit this assert unless assignments are shuffled around
2487 * if this happens we will prob. hit a vsync tdr
2488 */
2489 ASSERT(secondary_pipe);
2490 /*
2491 * search backwards for the second pipe to keep pipe
2492 * assignment more consistent
2493 */
2494 if (secondary_pipe == NULL) {
2495 for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2496 preferred_pipe_idx = j;
2497
2498 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2499 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2500 secondary_pipe->pipe_idx = preferred_pipe_idx;
2501 break;
2502 }
2503 }
2504 }
2505 }
2506
2507 return secondary_pipe;
2508}
2509
7287a675 2510static void dcn20_merge_pipes_for_validate(
6de20237 2511 struct dc *dc,
b6bfba6c 2512 struct dc_state *context)
7ed4e635 2513{
b6bfba6c 2514 int i;
7ed4e635 2515
b1f6d01c
DL		 2516 /* merge previously split odm pipes since mode support needs to make the decision */
2517 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2518 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2519 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2520
2521 if (pipe->prev_odm_pipe)
2522 continue;
2523
2524 pipe->next_odm_pipe = NULL;
2525 while (odm_pipe) {
2526 struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2527
2528 odm_pipe->plane_state = NULL;
2529 odm_pipe->stream = NULL;
2530 odm_pipe->top_pipe = NULL;
2531 odm_pipe->bottom_pipe = NULL;
2532 odm_pipe->prev_odm_pipe = NULL;
2533 odm_pipe->next_odm_pipe = NULL;
b1f6d01c 2534 if (odm_pipe->stream_res.dsc)
7287a675 2535 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
b1f6d01c
DL		 2536 /* Clear plane_res and stream_res */
2537 memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2538 memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2539 odm_pipe = next_odm_pipe;
2540 }
2541 if (pipe->plane_state)
2542 resource_build_scaling_params(pipe);
2543 }
2544
2545 /* merge previously mpc split pipes since mode support needs to make the decision */
7ed4e635
HW		 2546 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2547 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2548 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2549
2550 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2551 continue;
2552
7ed4e635
HW		 2553 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2554 if (hsplit_pipe->bottom_pipe)
2555 hsplit_pipe->bottom_pipe->top_pipe = pipe;
2556 hsplit_pipe->plane_state = NULL;
2557 hsplit_pipe->stream = NULL;
2558 hsplit_pipe->top_pipe = NULL;
2559 hsplit_pipe->bottom_pipe = NULL;
b1f6d01c 2560
7ed4e635
HW		 2561 /* Clear plane_res and stream_res */
2562 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2563 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2564 if (pipe->plane_state)
2565 resource_build_scaling_params(pipe);
2566 }
b6bfba6c 2567}
7ed4e635 2568
b6bfba6c
DL		 2569int dcn20_validate_apply_pipe_split_flags(
2570 struct dc *dc,
2571 struct dc_state *context,
2572 int vlevel,
7287a675
DL		 2573 bool *split,
2574 bool *merge)
b6bfba6c 2575{
b745ecdb 2576 int i, pipe_idx, vlevel_split;
cd3e05a7 2577 int plane_count = 0;
b6bfba6c 2578 bool force_split = false;
cd3e05a7 2579 bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
7ed4e635 2580
cd3e05a7
DL		 2581 if (context->stream_count > 1) {
2582 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)
2583 avoid_split = true;
2584 } else if (dc->debug.force_single_disp_pipe_split)
2585 force_split = true;
2586
2587 /* TODO: fix dc bugs and remove this split threshold thing */
7ed4e635
HW		 2588 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2589 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
7ed4e635 2590
cd3e05a7
DL		 2591 if (pipe->stream && !pipe->prev_odm_pipe &&
2592 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
2593 ++plane_count;
7ed4e635 2594 }
cd3e05a7 2595 if (plane_count > dc->res_pool->pipe_count / 2)
7ed4e635
HW		 2596 avoid_split = true;
2597
b745ecdb 2598 /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
b6bfba6c
DL		 2599 if (avoid_split) {
2600 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2601 if (!context->res_ctx.pipe_ctx[i].stream)
2602 continue;
2603
b745ecdb 2604 for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
b6bfba6c
DL		 2605 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
2606 break;
2607 /* Impossible to not split this pipe */
b745ecdb
DL		 2608 if (vlevel > context->bw_ctx.dml.soc.num_states)
2609 vlevel = vlevel_split;
b6bfba6c
DL		 2610 pipe_idx++;
2611 }
2612 context->bw_ctx.dml.vba.maxMpcComb = 0;
2613 }
2614
b745ecdb 2615 /* Split loop sets which pipe should be split based on dml outputs and dc flags */
7ed4e635 2616 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
b6bfba6c 2617 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
7287a675 2618 int pipe_plane = context->bw_ctx.dml.vba.pipe_plane[pipe_idx];
b6bfba6c 2619
7ed4e635
HW		 2620 if (!context->res_ctx.pipe_ctx[i].stream)
2621 continue;
b6bfba6c 2622
7287a675 2623 if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_plane] > 1)
b6bfba6c
DL		 2624 split[i] = true;
2625 if ((pipe->stream->view_format ==
2626 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2627 pipe->stream->view_format ==
2628 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2629 (pipe->stream->timing.timing_3d_format ==
2630 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2631 pipe->stream->timing.timing_3d_format ==
2632 TIMING_3D_FORMAT_SIDE_BY_SIDE))
2633 split[i] = true;
2634 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2635 split[i] = true;
7287a675 2636 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
b6bfba6c 2637 }
7287a675
DL		 2638 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_plane] =
2639 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_plane];
2640
2641 if (pipe->prev_odm_pipe && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_plane] != dm_odm_combine_mode_disabled) {
2642 /*Already split odm pipe tree, don't try to split again*/
2643 split[i] = false;
2644 split[pipe->prev_odm_pipe->pipe_idx] = false;
2645 } else if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state
2646 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
2647 /*Already split mpc tree, don't try to split again, assumes only 2x mpc combine*/
2648 split[i] = false;
2649 split[pipe->top_pipe->pipe_idx] = false;
2650 } else if (pipe->prev_odm_pipe || (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)) {
2651 if (split[i] == false) {
2652 /*Exiting mpc/odm combine*/
2653 merge[i] = true;
2654 if (pipe->prev_odm_pipe) {
2655 ASSERT(0); /*should not actually happen yet*/
2656 merge[pipe->prev_odm_pipe->pipe_idx] = true;
2657 } else
2658 merge[pipe->top_pipe->pipe_idx] = true;
2659 } else {
2660 /*Transition from mpc combine to odm combine or vice versa*/
2661 ASSERT(0); /*should not actually happen yet*/
2662 split[i] = true;
2663 merge[i] = true;
2664 if (pipe->prev_odm_pipe) {
2665 split[pipe->prev_odm_pipe->pipe_idx] = true;
2666 merge[pipe->prev_odm_pipe->pipe_idx] = true;
2667 } else {
2668 split[pipe->top_pipe->pipe_idx] = true;
2669 merge[pipe->top_pipe->pipe_idx] = true;
2670 }
2671 }
2672 }
2673
b6bfba6c
DL		 2674 /* Adjust dppclk when split is forced, do not bother with dispclk */
2675 if (split[i] && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
2676 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
7ed4e635
HW		 2677 pipe_idx++;
2678 }
2679
b6bfba6c
DL		 2680 return vlevel;
2681}
2682
2683bool dcn20_fast_validate_bw(
2684 struct dc *dc,
2685 struct dc_state *context,
2686 display_e2e_pipe_params_st *pipes,
2687 int *pipe_cnt_out,
2688 int *pipe_split_from,
2689 int *vlevel_out)
2690{
2691 bool out = false;
2692 bool split[MAX_PIPES] = { false };
2693 int pipe_cnt, i, pipe_idx, vlevel;
2694
2695 ASSERT(pipes);
2696 if (!pipes)
2697 return false;
2698
2699 dcn20_merge_pipes_for_validate(dc, context);
2700
2f488884 2701 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
b6bfba6c
DL		 2702
2703 *pipe_cnt_out = pipe_cnt;
2704
2705 if (!pipe_cnt) {
2706 out = true;
2707 goto validate_out;
2708 }
2709
2710 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2711
2712 if (vlevel > context->bw_ctx.dml.soc.num_states)
2713 goto validate_fail;
2714
7287a675 2715 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
b6bfba6c
DL		 2716
2717 /*initialize pipe_just_split_from to invalid idx*/
2718 for (i = 0; i < MAX_PIPES; i++)
2719 pipe_split_from[i] = -1;
2720
7ed4e635
HW		 2721 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2722 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2723 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
7ed4e635
HW		 2724
2725 if (!pipe->stream || pipe_split_from[i] >= 0)
2726 continue;
2727
2728 pipe_idx++;
2729
7ed4e635 2730 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
c681491a 2731 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
7ed4e635 2732 ASSERT(hsplit_pipe);
b1f6d01c 2733 if (!dcn20_split_stream_for_odm(
7ed4e635 2734 &context->res_ctx, dc->res_pool,
b1f6d01c 2735 pipe, hsplit_pipe))
7ed4e635
HW		 2736 goto validate_fail;
2737 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2738 dcn20_build_mapped_resource(dc, context, pipe->stream);
2739 }
2740
2741 if (!pipe->plane_state)
2742 continue;
2743 /* Skip 2nd half of already split pipe */
2744 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2745 continue;
2746
02ce5a79
DL		 2747 /* We do not support mpo + odm at the moment */
2748 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2749 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2750 goto validate_fail;
2751
b6bfba6c 2752 if (split[i]) {
7ed4e635
HW		 2753 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2754 /* pipe not split previously needs split */
c681491a 2755 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
b6bfba6c 2756 ASSERT(hsplit_pipe);
ff86391e
MS		 2757 if (!hsplit_pipe) {
2758 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
7ed4e635 2759 continue;
ff86391e 2760 }
b1f6d01c
DL		 2761 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2762 if (!dcn20_split_stream_for_odm(
2763 &context->res_ctx, dc->res_pool,
2764 pipe, hsplit_pipe))
2765 goto validate_fail;
387596ef 2766 dcn20_build_mapped_resource(dc, context, pipe->stream);
b1f6d01c
DL		 2767 } else
2768 dcn20_split_stream_for_mpc(
7ed4e635 2769 &context->res_ctx, dc->res_pool,
b1f6d01c 2770 pipe, hsplit_pipe);
7ed4e635
HW		 2771 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2772 }
02ce5a79 2773 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
7ed4e635
HW		 2774 /* merge should already have been done */
2775 ASSERT(0);
2776 }
2777 }
0ba37b20 2778 /* Actual dsc count per stream dsc validation*/
c84ad0d6 2779 if (!dcn20_validate_dsc(dc, context)) {
0ba37b20
DL		 2780 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2781 DML_FAIL_DSC_VALIDATION_FAILURE;
2782 goto validate_fail;
2783 }
7ed4e635 2784
6de20237 2785 *vlevel_out = vlevel;
42351c66 2786
6de20237
EY		 2787 out = true;
2788 goto validate_out;
2789
2790validate_fail:
2791 out = false;
2792
2793validate_out:
2794 return out;
2795}
2796
e2e316d5 2797static void dcn20_calculate_wm(
6de20237
EY		 2798 struct dc *dc, struct dc_state *context,
2799 display_e2e_pipe_params_st *pipes,
2800 int *out_pipe_cnt,
2801 int *pipe_split_from,
2802 int vlevel)
2803{
2804 int pipe_cnt, i, pipe_idx;
254eb07c 2805
7ed4e635 2806 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
41f03a6d
DL		 2807 if (!context->res_ctx.pipe_ctx[i].stream)
2808 continue;
7ed4e635 2809
41f03a6d
DL		 2810 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2811 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
7ed4e635 2812
41f03a6d
DL		 2813 if (pipe_split_from[i] < 0) {
2814 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2815 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2816 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2817 pipes[pipe_cnt].pipe.dest.odm_combine =
b6bfba6c 2818 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
41f03a6d
DL		 2819 else
2820 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2821 pipe_idx++;
2822 } else {
2823 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2824 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2825 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2826 pipes[pipe_cnt].pipe.dest.odm_combine =
b6bfba6c 2827 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
41f03a6d
DL		 2828 else
2829 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
7ed4e635 2830 }
6de20237 2831
41f03a6d
DL		 2832 if (dc->config.forced_clocks) {
2833 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2834 pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
a6465d1f 2835 }
41f03a6d
DL		 2836 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2837 pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2838 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2839 pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2840
2841 pipe_cnt++;
2842 }
7ed4e635 2843
41f03a6d
DL		 2844 if (pipe_cnt != pipe_idx) {
2845 if (dc->res_pool->funcs->populate_dml_pipes)
2846 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2f488884 2847 context, pipes);
41f03a6d
DL		 2848 else
2849 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2f488884 2850 context, pipes);
41f03a6d 2851 }
7ed4e635 2852
41f03a6d 2853 *out_pipe_cnt = pipe_cnt;
6de20237 2854
41f03a6d
DL		 2855 pipes[0].clks_cfg.voltage = vlevel;
2856 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2857 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2858
2859 /* only pipe 0 is read for voltage and dcf/soc clocks */
2860 if (vlevel < 1) {
2861 pipes[0].clks_cfg.voltage = 1;
2862 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
2863 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
2864 }
2865 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2866 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2867 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2868 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2869 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 2870 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2871 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
b617b265 2872 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 2873
2874 if (vlevel < 2) {
2875 pipes[0].clks_cfg.voltage = 2;
2876 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2877 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2878 }
2879 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2880 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2881 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2882 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2883 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 2884 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2885 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 2886
2887 if (vlevel < 3) {
2888 pipes[0].clks_cfg.voltage = 3;
2889 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2890 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2891 }
2892 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2893 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2894 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2895 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2896 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 2897 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2898 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
41f03a6d
DL		 2899
2900 pipes[0].clks_cfg.voltage = vlevel;
2901 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2902 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2903 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2904 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2905 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2906 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2907 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
4de094ee
BL		 2908 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2909 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
6de20237
EY		 2910}
2911
2912void dcn20_calculate_dlg_params(
2913 struct dc *dc, struct dc_state *context,
2914 display_e2e_pipe_params_st *pipes,
2915 int pipe_cnt,
2916 int vlevel)
2917{
41f03a6d
DL		 2918 int i, j, pipe_idx, pipe_idx_unsplit;
2919 bool visited[MAX_PIPES] = { 0 };
8e27a2d4 2920
7ed4e635
HW		 2921 /* Writeback MCIF_WB arbitration parameters */
2922 dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
2923
2924 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
2925 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
2926 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
173932de 2927 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
7ed4e635 2928 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
799c5b9c 2929 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
7ed4e635
HW		 2930 context->bw_ctx.bw.dcn.clk.p_state_change_support =
2931 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
2932 != dm_dram_clock_change_unsupported;
2933 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
2934
cab5dec4
YS		 2935 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
2936 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
2937
41f03a6d
DL		 2938 /*
2939 * An artifact of dml pipe split/odm is that pipes get merged back together for
2940 * calculation. Therefore we need to only extract for first pipe in ascending index order
2941 * and copy into the other split half.
2942 */
2943 for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
2944 if (!context->res_ctx.pipe_ctx[i].stream)
2945 continue;
6de20237 2946
41f03a6d 2947 if (!visited[pipe_idx]) {
74df06dd
DL		 2948 display_pipe_source_params_st *src = &pipes[pipe_idx].pipe.src;
2949 display_pipe_dest_params_st *dst = &pipes[pipe_idx].pipe.dest;
41f03a6d
DL		 2950
2951 dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2952 dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2953 dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2954 dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2955 /*
2956 * j iterates inside pipes array, unlike i which iterates inside
2957 * pipe_ctx array
2958 */
2959 if (src->is_hsplit)
2960 for (j = pipe_idx + 1; j < pipe_cnt; j++) {
2961 display_pipe_source_params_st *src_j = &pipes[j].pipe.src;
2962 display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest;
2963
2964 if (src_j->is_hsplit && !visited[j]
2965 && src->hsplit_grp == src_j->hsplit_grp) {
2966 dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2967 dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2968 dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2969 dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2970 visited[j] = true;
2971 }
2972 }
2973 visited[pipe_idx] = true;
2974 pipe_idx_unsplit++;
2975 }
2976 pipe_idx++;
2977 }
42351c66 2978
7ed4e635
HW		 2979 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2980 if (!context->res_ctx.pipe_ctx[i].stream)
2981 continue;
7ed4e635
HW		 2982 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2983 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
2984 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
2985 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
41f03a6d 2986 ASSERT(visited[pipe_idx]);
7ed4e635
HW		 2987 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
2988 pipe_idx++;
2989 }
925f566c
CL		 2990 /*save a original dppclock copy*/
2991 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
2992 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
41f03a6d
DL		 2993 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
2994 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
7ed4e635
HW		 2995
2996 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2997 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
2998
2999 if (!context->res_ctx.pipe_ctx[i].stream)
3000 continue;
3001
3002 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
3003 &context->res_ctx.pipe_ctx[i].dlg_regs,
3004 &context->res_ctx.pipe_ctx[i].ttu_regs,
3005 pipes,
3006 pipe_cnt,
3007 pipe_idx,
3008 cstate_en,
f82c916c
CL		 3009 context->bw_ctx.bw.dcn.clk.p_state_change_support,
3010 false, false, false);
254eb07c 3011
7ed4e635
HW		 3012 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
3013 &context->res_ctx.pipe_ctx[i].rq_regs,
3014 pipes[pipe_idx].pipe);
3015 pipe_idx++;
3016 }
6de20237
EY		 3017}
3018
057fc695 3019static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
6de20237
EY		 3020 bool fast_validate)
3021{
3022 bool out = false;
3023
3024 BW_VAL_TRACE_SETUP();
3025
3026 int vlevel = 0;
3027 int pipe_split_from[MAX_PIPES];
3028 int pipe_cnt = 0;
3029 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
3030 DC_LOGGER_INIT(dc->ctx->logger);
3031
3032 BW_VAL_TRACE_COUNT();
3033
5e335add
EY		 3034 out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
3035
3036 if (pipe_cnt == 0)
3037 goto validate_out;
6de20237
EY		 3038
3039 if (!out)
3040 goto validate_fail;
3041
3042 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
3043
3044 if (fast_validate) {
3045 BW_VAL_TRACE_SKIP(fast);
3046 goto validate_out;
3047 }
3048
3049 dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
3050 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
3051
3052 BW_VAL_TRACE_END_WATERMARKS();
7ed4e635 3053
254eb07c 3054 goto validate_out;
7ed4e635
HW		 3055
3056validate_fail:
00999d99
DL		 3057 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
3058 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
254eb07c 3059
42351c66 3060 BW_VAL_TRACE_SKIP(fail);
254eb07c
JA		 3061 out = false;
3062
3063validate_out:
7ed4e635 3064 kfree(pipes);
254eb07c 3065
42351c66
JA		 3066 BW_VAL_TRACE_FINISH();
3067
254eb07c 3068 return out;
7ed4e635
HW		 3069}
3070
59dfb0c6
DK		 3071/*
3072 * This must be noinline to ensure anything that deals with FP registers
3073 * is contained within this call; previously our compiling with hard-float
3074 * would result in fp instructions being emitted outside of the boundaries
3075 * of the DC_FP_START/END macros, which makes sense as the compiler has no
3076 * idea about what is wrapped and what is not
3077 *
3078 * This is largely just a workaround to avoid breakage introduced with 5.6,
3079 * ideally all fp-using code should be moved into its own file, only that
3080 * should be compiled with hard-float, and all code exported from there
3081 * should be strictly wrapped with DC_FP_START/END
3082 */
3083static noinline bool dcn20_validate_bandwidth_fp(struct dc *dc,
3084 struct dc_state *context, bool fast_validate)
057fc695
JL		 3085{
3086 bool voltage_supported = false;
3087 bool full_pstate_supported = false;
3088 bool dummy_pstate_supported = false;
7a8a3430 3089 double p_state_latency_us;
057fc695 3090
7a8a3430
TP		 3091 p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
3092 context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
3093 dc->debug.disable_dram_clock_change_vactive_support;
057fc695 3094
7a8a3430 3095 if (fast_validate) {
59dfb0c6 3096 return dcn20_validate_bandwidth_internal(dc, context, true);
7a8a3430 3097 }
057fc695
JL		 3098
3099 // Best case, we support full UCLK switch latency
3100 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3101 full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3102
3103 if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
3104 (voltage_supported && full_pstate_supported)) {
30c9b7a1 3105 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;
057fc695
JL		 3106 goto restore_dml_state;
3107 }
3108
b9e8d95a 3109 // Fallback: Try to only support G6 temperature read latency
057fc695
JL		 3110 context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
3111
3112 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3113 dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3114
3115 if (voltage_supported && dummy_pstate_supported) {
3116 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
3117 goto restore_dml_state;
3118 }
3119
b9e8d95a 3120 // ERROR: fallback is supposed to always work.
057fc695
JL		 3121 ASSERT(false);
3122
3123restore_dml_state:
057fc695 3124 context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
59dfb0c6
DK		 3125 return voltage_supported;
3126}
057fc695 3127
59dfb0c6
DK		 3128bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
3129 bool fast_validate)
3130{
3131 bool voltage_supported = false;
3132 DC_FP_START();
3133 voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);
7a8a3430 3134 DC_FP_END();
057fc695
JL		 3135 return voltage_supported;
3136}
3137
7ed4e635
HW		 3138struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
3139 struct dc_state *state,
3140 const struct resource_pool *pool,
3141 struct dc_stream_state *stream)
3142{
3143 struct resource_context *res_ctx = &state->res_ctx;
3144 struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
3145 struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
3146
3147 if (!head_pipe)
3148 ASSERT(0);
3149
3150 if (!idle_pipe)
7a17c8ce 3151 return NULL;
7ed4e635
HW		 3152
3153 idle_pipe->stream = head_pipe->stream;
3154 idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
3155 idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
3156
3157 idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
3158 idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
3159 idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
3160 idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
3161
3162 return idle_pipe;
3163}
3164
3165bool dcn20_get_dcc_compression_cap(const struct dc *dc,
3166 const struct dc_dcc_surface_param *input,
3167 struct dc_surface_dcc_cap *output)
3168{
3169 return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
3170 dc->res_pool->hubbub,
3171 input,
3172 output);
3173}
3174
3175static void dcn20_destroy_resource_pool(struct resource_pool **pool)
3176{
3177 struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
3178
d9e32672 3179 dcn20_resource_destruct(dcn20_pool);
7ed4e635
HW		 3180 kfree(dcn20_pool);
3181 *pool = NULL;
3182}
3183
3184
3185static struct dc_cap_funcs cap_funcs = {
3186 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
3187};
3188
3189
8d8c82b6 3190enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)
7ed4e635
HW		 3191{
3192 enum dc_status result = DC_OK;
3193
3194 enum surface_pixel_format surf_pix_format = plane_state->format;
3195 unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
3196
3197 enum swizzle_mode_values swizzle = DC_SW_LINEAR;
3198
3199 if (bpp == 64)
3200 swizzle = DC_SW_64KB_D;
3201 else
3202 swizzle = DC_SW_64KB_S;
3203
3204 plane_state->tiling_info.gfx9.swizzle = swizzle;
3205 return result;
3206}
3207
3208static struct resource_funcs dcn20_res_pool_funcs = {
3209 .destroy = dcn20_destroy_resource_pool,
3210 .link_enc_create = dcn20_link_encoder_create,
3211 .validate_bandwidth = dcn20_validate_bandwidth,
7ed4e635
HW		 3212 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
3213 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
3214 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
3215 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
8d8c82b6 3216 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
c9ae6e16 3217 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
b6bfba6c 3218 .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
278141f5 3219 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
7ed4e635
HW		 3220};
3221
bb21290f
CL		 3222bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
3223{
3224 int i;
3225 uint32_t pipe_count = pool->res_cap->num_dwb;
3226
bb21290f
CL		 3227 for (i = 0; i < pipe_count; i++) {
3228 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
3229 GFP_KERNEL);
3230
3231 if (!dwbc20) {
3232 dm_error("DC: failed to create dwbc20!\n");
3233 return false;
3234 }
3235 dcn20_dwbc_construct(dwbc20, ctx,
3236 &dwbc20_regs[i],
3237 &dwbc20_shift,
3238 &dwbc20_mask,
3239 i);
3240 pool->dwbc[i] = &dwbc20->base;
3241 }
3242 return true;
3243}
3244
3245bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
3246{
3247 int i;
3248 uint32_t pipe_count = pool->res_cap->num_dwb;
3249
3250 ASSERT(pipe_count > 0);
3251
3252 for (i = 0; i < pipe_count; i++) {
3253 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
3254 GFP_KERNEL);
3255
3256 if (!mcif_wb20) {
3257 dm_error("DC: failed to create mcif_wb20!\n");
3258 return false;
3259 }
3260
3261 dcn20_mmhubbub_construct(mcif_wb20, ctx,
3262 &mcif_wb20_regs[i],
3263 &mcif_wb20_shift,
3264 &mcif_wb20_mask,
3265 i);
3266
3267 pool->mcif_wb[i] = &mcif_wb20->base;
3268 }
3269 return true;
3270}
3271
44e149bb 3272static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
7ed4e635
HW		 3273{
3274 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
3275
3276 if (!pp_smu)
3277 return pp_smu;
3278
3279 dm_pp_get_funcs(ctx, pp_smu);
3280
3281 if (pp_smu->ctx.ver != PP_SMU_VER_NV)
3282 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
3283
3284 return pp_smu;
3285}
3286
44e149bb 3287static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
7ed4e635
HW		 3288{
3289 if (pp_smu && *pp_smu) {
3290 kfree(*pp_smu);
3291 *pp_smu = NULL;
3292 }
3293}
3294
44ce0cd3 3295void dcn20_cap_soc_clocks(
7ed4e635
HW		 3296 struct _vcs_dpi_soc_bounding_box_st *bb,
3297 struct pp_smu_nv_clock_table max_clocks)
3298{
3299 int i;
3300
3301 // First pass - cap all clocks higher than the reported max
3302 for (i = 0; i < bb->num_states; i++) {
3303 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
3304 && max_clocks.dcfClockInKhz != 0)
3305 bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
3306
3307 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
3308 && max_clocks.uClockInKhz != 0)
3309 bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
3310
3311 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
3312 && max_clocks.fabricClockInKhz != 0)
3313 bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3314
3315 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3316 && max_clocks.displayClockInKhz != 0)
3317 bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3318
3319 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3320 && max_clocks.dppClockInKhz != 0)
3321 bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3322
3323 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3324 && max_clocks.phyClockInKhz != 0)
3325 bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3326
3327 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3328 && max_clocks.socClockInKhz != 0)
3329 bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3330
3331 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3332 && max_clocks.dscClockInKhz != 0)
3333 bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3334 }
3335
3336 // Second pass - remove all duplicate clock states
3337 for (i = bb->num_states - 1; i > 1; i--) {
3338 bool duplicate = true;
3339
3340 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
3341 duplicate = false;
3342 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
3343 duplicate = false;
3344 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
3345 duplicate = false;
3346 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
3347 duplicate = false;
3348 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
3349 duplicate = false;
3350 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
3351 duplicate = false;
3352 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
3353 duplicate = false;
3354 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
3355 duplicate = false;
3356
3357 if (duplicate)
3358 bb->num_states--;
3359 }
3360}
3361
44ce0cd3 3362void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
7ed4e635
HW		 3363 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3364{
c42656f8 3365 struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
f18bc4e5 3366 int i;
7ed4e635 3367 int num_calculated_states = 0;
f18bc4e5 3368 int min_dcfclk = 0;
7ed4e635
HW		 3369
3370 if (num_states == 0)
3371 return;
3372
960b6f4f
RR		 3373 memset(calculated_states, 0, sizeof(calculated_states));
3374
f18bc4e5
JL		 3375 if (dc->bb_overrides.min_dcfclk_mhz > 0)
3376 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
6ce2427d
AL		 3377 else {
3378 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3379 min_dcfclk = 310;
3380 else
3381 // Accounting for SOC/DCF relationship, we can go as high as
3382 // 506Mhz in Vmin.
3383 min_dcfclk = 506;
3384 }
f18bc4e5 3385
7ed4e635 3386 for (i = 0; i < num_states; i++) {
f18bc4e5
JL		 3387 int min_fclk_required_by_uclk;
3388 calculated_states[i].state = i;
3389 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
7ed4e635 3390
5d36f783 3391 // FCLK:UCLK ratio is 1.08
5f65ae34 3392 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
7ed4e635 3393
f18bc4e5
JL		 3394 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
3395 min_dcfclk : min_fclk_required_by_uclk;
7ed4e635 3396
f18bc4e5
JL		 3397 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
3398 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 3399
f18bc4e5
JL		 3400 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
3401 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
7ed4e635 3402
f18bc4e5
JL		 3403 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
3404 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
3405 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
7ed4e635 3406
f18bc4e5 3407 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
7ed4e635 3408
f18bc4e5 3409 num_calculated_states++;
7ed4e635
HW		 3410 }
3411
6da16270
JL		 3412 calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
3413 calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
3414 calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
3415
7ed4e635
HW		 3416 memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
3417 bb->num_states = num_calculated_states;
f18bc4e5
JL		 3418
3419 // Duplicate the last state, DML always an extra state identical to max state to work
3420 memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
3421 bb->clock_limits[num_calculated_states].state = bb->num_states;
7ed4e635
HW		 3422}
3423
44ce0cd3 3424void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
7ed4e635 3425{
7ed4e635
HW		 3426 if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3427 && dc->bb_overrides.sr_exit_time_ns) {
3428 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3429 }
3430
3431 if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
3432 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3433 && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3434 bb->sr_enter_plus_exit_time_us =
3435 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3436 }
3437
3438 if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3439 && dc->bb_overrides.urgent_latency_ns) {
3440 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3441 }
3442
3443 if ((int)(bb->dram_clock_change_latency_us * 1000)
3444 != dc->bb_overrides.dram_clock_change_latency_ns
3445 && dc->bb_overrides.dram_clock_change_latency_ns) {
3446 bb->dram_clock_change_latency_us =
3447 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3448 }
7ed4e635
HW		 3449}
3450
675a9e38
LL		 3451static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3452 uint32_t hw_internal_rev)
3453{
e1ab4a91
ML		 3454 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3455 return &dcn2_0_nv14_soc;
3456
675a9e38
LL		 3457 if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3458 return &dcn2_0_nv12_soc;
3459
3460 return &dcn2_0_soc;
3461}
3462
3463static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3464 uint32_t hw_internal_rev)
3465{
72b741af
Z		 3466 /* NV14 */
3467 if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3468 return &dcn2_0_nv14_ip;
3469
675a9e38
LL		 3470 /* NV12 and NV10 */
3471 return &dcn2_0_ip;
3472}
3473
3474static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3475{
3476 return DML_PROJECT_NAVI10v2;
3477}
3478
7ed4e635
HW		 3479#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
3480#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
3481
3482static bool init_soc_bounding_box(struct dc *dc,
3483 struct dcn20_resource_pool *pool)
3484{
3485 const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
675a9e38
LL		 3486 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3487 get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3488 struct _vcs_dpi_ip_params_st *loaded_ip =
3489 get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3490
7ed4e635
HW		 3491 DC_LOGGER_INIT(dc->ctx->logger);
3492
3e0c55f3
ZL		 3493 /* TODO: upstream NV12 bounding box when its launched */
3494 if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
7ed4e635
HW		 3495 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
3496 return false;
3497 }
3498
3e0c55f3 3499 if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
7ed4e635
HW		 3500 int i;
3501
675a9e38 3502 dcn2_0_nv12_soc.sr_exit_time_us =
7ed4e635 3503 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
675a9e38 3504 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
7ed4e635 3505 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
675a9e38 3506 dcn2_0_nv12_soc.urgent_latency_us =
7ed4e635 3507 fixed16_to_double_to_cpu(bb->urgent_latency_us);
675a9e38 3508 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us =
7ed4e635 3509 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
675a9e38 3510 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us =
7ed4e635 3511 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
675a9e38 3512 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us =
7ed4e635 3513 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
675a9e38 3514 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
7ed4e635 3515 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
675a9e38 3516 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
7ed4e635 3517 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
675a9e38 3518 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
7ed4e635 3519 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
675a9e38 3520 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
7ed4e635 3521 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
675a9e38 3522 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
7ed4e635 3523 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
675a9e38 3524 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
7ed4e635 3525 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
675a9e38 3526 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent =
7ed4e635 3527 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
675a9e38 3528 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent =
7ed4e635 3529 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
675a9e38 3530 dcn2_0_nv12_soc.writeback_latency_us =
7ed4e635 3531 fixed16_to_double_to_cpu(bb->writeback_latency_us);
675a9e38 3532 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent =
7ed4e635 3533 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
675a9e38 3534 dcn2_0_nv12_soc.max_request_size_bytes =
7ed4e635 3535 le32_to_cpu(bb->max_request_size_bytes);
675a9e38 3536 dcn2_0_nv12_soc.dram_channel_width_bytes =
7ed4e635 3537 le32_to_cpu(bb->dram_channel_width_bytes);
675a9e38 3538 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes =
7ed4e635 3539 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
675a9e38 3540 dcn2_0_nv12_soc.dcn_downspread_percent =
7ed4e635 3541 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
675a9e38 3542 dcn2_0_nv12_soc.downspread_percent =
7ed4e635 3543 fixed16_to_double_to_cpu(bb->downspread_percent);
675a9e38 3544 dcn2_0_nv12_soc.dram_page_open_time_ns =
7ed4e635 3545 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
675a9e38 3546 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns =
7ed4e635 3547 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
675a9e38 3548 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes =
7ed4e635 3549 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
675a9e38 3550 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles =
7ed4e635 3551 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
675a9e38 3552 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes =
7ed4e635 3553 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
675a9e38 3554 dcn2_0_nv12_soc.channel_interleave_bytes =
7ed4e635 3555 le32_to_cpu(bb->channel_interleave_bytes);
675a9e38 3556 dcn2_0_nv12_soc.num_banks =
7ed4e635 3557 le32_to_cpu(bb->num_banks);
675a9e38 3558 dcn2_0_nv12_soc.num_chans =
7ed4e635 3559 le32_to_cpu(bb->num_chans);
675a9e38 3560 dcn2_0_nv12_soc.vmm_page_size_bytes =
7ed4e635 3561 le32_to_cpu(bb->vmm_page_size_bytes);
675a9e38 3562 dcn2_0_nv12_soc.dram_clock_change_latency_us =
7ed4e635 3563 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
675a9e38
LL		 3564 // HACK!! Lower uclock latency switch time so we don't switch
3565 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
3566 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us =
7ed4e635 3567 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
675a9e38 3568 dcn2_0_nv12_soc.return_bus_width_bytes =
7ed4e635 3569 le32_to_cpu(bb->return_bus_width_bytes);
675a9e38 3570 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz =
7ed4e635 3571 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
675a9e38 3572 dcn2_0_nv12_soc.xfc_bus_transport_time_us =
7ed4e635 3573 le32_to_cpu(bb->xfc_bus_transport_time_us);
675a9e38 3574 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us =
7ed4e635 3575 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
675a9e38 3576 dcn2_0_nv12_soc.use_urgent_burst_bw =
7ed4e635 3577 le32_to_cpu(bb->use_urgent_burst_bw);
675a9e38 3578 dcn2_0_nv12_soc.num_states =
7ed4e635
HW		 3579 le32_to_cpu(bb->num_states);
3580
675a9e38
LL		 3581 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
3582 dcn2_0_nv12_soc.clock_limits[i].state =
7ed4e635 3583 le32_to_cpu(bb->clock_limits[i].state);
675a9e38 3584 dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz =
7ed4e635 3585 fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
675a9e38 3586 dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz =
7ed4e635 3587 fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
675a9e38 3588 dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz =
7ed4e635 3589 fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
675a9e38 3590 dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz =
7ed4e635 3591 fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
675a9e38 3592 dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz =
7ed4e635 3593 fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
675a9e38 3594 dcn2_0_nv12_soc.clock_limits[i].socclk_mhz =
7ed4e635 3595 fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
675a9e38 3596 dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz =
7ed4e635 3597 fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
675a9e38 3598 dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
7ed4e635
HW		 3599 fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
3600 }
3601 }
3602
3603 if (pool->base.pp_smu) {
3604 struct pp_smu_nv_clock_table max_clocks = {0};
3605 unsigned int uclk_states[8] = {0};
3606 unsigned int num_states = 0;
3607 enum pp_smu_status status;
3608 bool clock_limits_available = false;
3609 bool uclk_states_available = false;
3610
3611 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3612 status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3613 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3614
3615 uclk_states_available = (status == PP_SMU_RESULT_OK);
3616 }
3617
3618 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3619 status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3620 (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
c2ad17c3
AW		 3621 /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
3622 */
3623 if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3624 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
7ed4e635
HW		 3625 clock_limits_available = (status == PP_SMU_RESULT_OK);
3626 }
3627
c2ad17c3 3628 if (clock_limits_available && uclk_states_available && num_states)
44ce0cd3 3629 dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
7ed4e635 3630 else if (clock_limits_available)
44ce0cd3 3631 dcn20_cap_soc_clocks(loaded_bb, max_clocks);
7ed4e635
HW		 3632 }
3633
675a9e38
LL		 3634 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
3635 loaded_ip->max_num_dpp = pool->base.pipe_count;
44ce0cd3 3636 dcn20_patch_bounding_box(dc, loaded_bb);
7ed4e635
HW		 3637
3638 return true;
3639}
3640
d9e32672 3641static bool dcn20_resource_construct(
7ed4e635
HW		 3642 uint8_t num_virtual_links,
3643 struct dc *dc,
3644 struct dcn20_resource_pool *pool)
3645{
3646 int i;
3647 struct dc_context *ctx = dc->ctx;
3648 struct irq_service_init_data init_data;
d9a07577 3649 struct ddc_service_init_data ddc_init_data;
675a9e38
LL		 3650 struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3651 get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3652 struct _vcs_dpi_ip_params_st *loaded_ip =
3653 get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3654 enum dml_project dml_project_version =
3655 get_dml_project_version(ctx->asic_id.hw_internal_rev);
7ed4e635 3656
7a8a3430
TP		 3657 DC_FP_START();
3658
7ed4e635 3659 ctx->dc_bios->regs = &bios_regs;
7ed4e635
HW		 3660 pool->base.funcs = &dcn20_res_pool_funcs;
3661
2ebe1773
BL		 3662 if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3663 pool->base.res_cap = &res_cap_nv14;
3664 pool->base.pipe_count = 5;
3665 pool->base.mpcc_count = 5;
3666 } else {
3667 pool->base.res_cap = &res_cap_nv10;
3668 pool->base.pipe_count = 6;
3669 pool->base.mpcc_count = 6;
3670 }
7ed4e635
HW		 3671 /*************************************************
3672 * Resource + asic cap harcoding *
3673 *************************************************/
3674 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3675
7ed4e635
HW		 3676 dc->caps.max_downscale_ratio = 200;
3677 dc->caps.i2c_speed_in_khz = 100;
3678 dc->caps.max_cursor_size = 256;
3679 dc->caps.dmdata_alloc_size = 2048;
3680
3681 dc->caps.max_slave_planes = 1;
3682 dc->caps.post_blend_color_processing = true;
3683 dc->caps.force_dp_tps4_for_cp2520 = true;
3684 dc->caps.hw_3d_lut = true;
ca4f844e 3685 dc->caps.extended_aux_timeout_support = true;
7ed4e635 3686
803a1412 3687 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
7ed4e635 3688 dc->debug = debug_defaults_drv;
803a1412
ES		 3689 } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3690 pool->base.pipe_count = 4;
7ed4e635
HW		 3691 pool->base.mpcc_count = pool->base.pipe_count;
3692 dc->debug = debug_defaults_diags;
803a1412 3693 } else {
7ed4e635 3694 dc->debug = debug_defaults_diags;
803a1412 3695 }
7ed4e635
HW		 3696 //dcn2.0x
3697 dc->work_arounds.dedcn20_305_wa = true;
3698
3699 // Init the vm_helper
3700 if (dc->vm_helper)
bda9afda 3701 vm_helper_init(dc->vm_helper, 16);
7ed4e635
HW		 3702
3703 /*************************************************
3704 * Create resources *
3705 *************************************************/
3706
3707 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3708 dcn20_clock_source_create(ctx, ctx->dc_bios,
3709 CLOCK_SOURCE_COMBO_PHY_PLL0,
3710 &clk_src_regs[0], false);
3711 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3712 dcn20_clock_source_create(ctx, ctx->dc_bios,
3713 CLOCK_SOURCE_COMBO_PHY_PLL1,
3714 &clk_src_regs[1], false);
3715 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3716 dcn20_clock_source_create(ctx, ctx->dc_bios,
3717 CLOCK_SOURCE_COMBO_PHY_PLL2,
3718 &clk_src_regs[2], false);
3719 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3720 dcn20_clock_source_create(ctx, ctx->dc_bios,
3721 CLOCK_SOURCE_COMBO_PHY_PLL3,
3722 &clk_src_regs[3], false);
3723 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3724 dcn20_clock_source_create(ctx, ctx->dc_bios,
3725 CLOCK_SOURCE_COMBO_PHY_PLL4,
3726 &clk_src_regs[4], false);
3727 pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3728 dcn20_clock_source_create(ctx, ctx->dc_bios,
3729 CLOCK_SOURCE_COMBO_PHY_PLL5,
3730 &clk_src_regs[5], false);
3731 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3732 /* todo: not reuse phy_pll registers */
3733 pool->base.dp_clock_source =
3734 dcn20_clock_source_create(ctx, ctx->dc_bios,
3735 CLOCK_SOURCE_ID_DP_DTO,
3736 &clk_src_regs[0], true);
3737
3738 for (i = 0; i < pool->base.clk_src_count; i++) {
3739 if (pool->base.clock_sources[i] == NULL) {
3740 dm_error("DC: failed to create clock sources!\n");
3741 BREAK_TO_DEBUGGER();
3742 goto create_fail;
3743 }
3744 }
3745
3746 pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3747 if (pool->base.dccg == NULL) {
3748 dm_error("DC: failed to create dccg!\n");
3749 BREAK_TO_DEBUGGER();
3750 goto create_fail;
3751 }
3752
3753 pool->base.dmcu = dcn20_dmcu_create(ctx,
3754 &dmcu_regs,
3755 &dmcu_shift,
3756 &dmcu_mask);
3757 if (pool->base.dmcu == NULL) {
3758 dm_error("DC: failed to create dmcu!\n");
3759 BREAK_TO_DEBUGGER();
3760 goto create_fail;
3761 }
3762
d7c29549 3763 pool->base.abm = dce_abm_create(ctx,
7ed4e635
HW		 3764 &abm_regs,
3765 &abm_shift,
3766 &abm_mask);
3767 if (pool->base.abm == NULL) {
3768 dm_error("DC: failed to create abm!\n");
3769 BREAK_TO_DEBUGGER();
3770 goto create_fail;
d7c29549 3771 }
7ed4e635
HW		 3772
3773 pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3774
3775
3776 if (!init_soc_bounding_box(dc, pool)) {
3777 dm_error("DC: failed to initialize soc bounding box!\n");
3778 BREAK_TO_DEBUGGER();
3779 goto create_fail;
3780 }
3781
675a9e38 3782 dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
7ed4e635
HW		 3783
3784 if (!dc->debug.disable_pplib_wm_range) {
3785 struct pp_smu_wm_range_sets ranges = {0};
3786 int i = 0;
3787
3788 ranges.num_reader_wm_sets = 0;
3789
675a9e38 3790 if (loaded_bb->num_states == 1) {
7ed4e635
HW		 3791 ranges.reader_wm_sets[0].wm_inst = i;
3792 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3793 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3794 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3795 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3796
3797 ranges.num_reader_wm_sets = 1;
675a9e38
LL		 3798 } else if (loaded_bb->num_states > 1) {
3799 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
7ed4e635
HW		 3800 ranges.reader_wm_sets[i].wm_inst = i;
3801 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3802 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
675a9e38
LL		 3803 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3804 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
7ed4e635
HW		 3805
3806 ranges.num_reader_wm_sets = i + 1;
3807 }
7ed4e635 3808
5d36f783
JL		 3809 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3810 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3811 }
7ed4e635
HW		 3812
3813 ranges.num_writer_wm_sets = 1;
3814
3815 ranges.writer_wm_sets[0].wm_inst = 0;
3816 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3817 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3818 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3819 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3820
3821 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3822 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3823 pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3824 }
3825
3826 init_data.ctx = dc->ctx;
3827 pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3828 if (!pool->base.irqs)
3829 goto create_fail;
3830
3831 /* mem input -> ipp -> dpp -> opp -> TG */
3832 for (i = 0; i < pool->base.pipe_count; i++) {
3833 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3834 if (pool->base.hubps[i] == NULL) {
3835 BREAK_TO_DEBUGGER();
3836 dm_error(
3837 "DC: failed to create memory input!\n");
3838 goto create_fail;
3839 }
3840
3841 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3842 if (pool->base.ipps[i] == NULL) {
3843 BREAK_TO_DEBUGGER();
3844 dm_error(
3845 "DC: failed to create input pixel processor!\n");
3846 goto create_fail;
3847 }
3848
3849 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3850 if (pool->base.dpps[i] == NULL) {
3851 BREAK_TO_DEBUGGER();
3852 dm_error(
3853 "DC: failed to create dpps!\n");
3854 goto create_fail;
3855 }
3856 }
3857 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3858 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3859 if (pool->base.engines[i] == NULL) {
3860 BREAK_TO_DEBUGGER();
3861 dm_error(
3862 "DC:failed to create aux engine!!\n");
3863 goto create_fail;
3864 }
3865 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3866 if (pool->base.hw_i2cs[i] == NULL) {
3867 BREAK_TO_DEBUGGER();
3868 dm_error(
3869 "DC:failed to create hw i2c!!\n");
3870 goto create_fail;
3871 }
3872 pool->base.sw_i2cs[i] = NULL;
3873 }
3874
3875 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3876 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3877 if (pool->base.opps[i] == NULL) {
3878 BREAK_TO_DEBUGGER();
3879 dm_error(
3880 "DC: failed to create output pixel processor!\n");
3881 goto create_fail;
3882 }
3883 }
3884
3885 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3886 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3887 ctx, i);
3888 if (pool->base.timing_generators[i] == NULL) {
3889 BREAK_TO_DEBUGGER();
3890 dm_error("DC: failed to create tg!\n");
3891 goto create_fail;
3892 }
3893 }
3894
3895 pool->base.timing_generator_count = i;
3896
3897 pool->base.mpc = dcn20_mpc_create(ctx);
3898 if (pool->base.mpc == NULL) {
3899 BREAK_TO_DEBUGGER();
3900 dm_error("DC: failed to create mpc!\n");
3901 goto create_fail;
3902 }
3903
3904 pool->base.hubbub = dcn20_hubbub_create(ctx);
3905 if (pool->base.hubbub == NULL) {
3906 BREAK_TO_DEBUGGER();
3907 dm_error("DC: failed to create hubbub!\n");
3908 goto create_fail;
3909 }
3910
97bda032
HW		 3911 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3912 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3913 if (pool->base.dscs[i] == NULL) {
3914 BREAK_TO_DEBUGGER();
3915 dm_error("DC: failed to create display stream compressor %d!\n", i);
3916 goto create_fail;
3917 }
3918 }
7ed4e635 3919
bb21290f
CL		 3920 if (!dcn20_dwbc_create(ctx, &pool->base)) {
3921 BREAK_TO_DEBUGGER();
3922 dm_error("DC: failed to create dwbc!\n");
3923 goto create_fail;
3924 }
3925 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
3926 BREAK_TO_DEBUGGER();
3927 dm_error("DC: failed to create mcif_wb!\n");
3928 goto create_fail;
3929 }
3930
7ed4e635
HW		 3931 if (!resource_construct(num_virtual_links, dc, &pool->base,
3932 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3933 &res_create_funcs : &res_create_maximus_funcs)))
3934 goto create_fail;
3935
3936 dcn20_hw_sequencer_construct(dc);
3937
3c9de4da
AL		 3938 // IF NV12, set PG function pointer to NULL. It's not that
3939 // PG isn't supported for NV12, it's that we don't want to
3940 // program the registers because that will cause more power
3941 // to be consumed. We could have created dcn20_init_hw to get
3942 // the same effect by checking ASIC rev, but there was a
3943 // request at some point to not check ASIC rev on hw sequencer.
3944 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3945 dc->hwseq->funcs.enable_power_gating_plane = NULL;
3946
7ed4e635
HW		 3947 dc->caps.max_planes = pool->base.pipe_count;
3948
3949 for (i = 0; i < dc->caps.max_planes; ++i)
3950 dc->caps.planes[i] = plane_cap;
3951
3952 dc->cap_funcs = cap_funcs;
3953
d9a07577
JL		 3954 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
3955 ddc_init_data.ctx = dc->ctx;
3956 ddc_init_data.link = NULL;
3957 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
3958 ddc_init_data.id.enum_id = 0;
3959 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
3960 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
3961 } else {
3962 pool->base.oem_device = NULL;
3963 }
3964
7a8a3430 3965 DC_FP_END();
7ed4e635
HW		 3966 return true;
3967
3968create_fail:
3969
7a8a3430 3970 DC_FP_END();
d9e32672 3971 dcn20_resource_destruct(pool);
7ed4e635
HW		 3972
3973 return false;
3974}
3975
3976struct resource_pool *dcn20_create_resource_pool(
3977 const struct dc_init_data *init_data,
3978 struct dc *dc)
3979{
3980 struct dcn20_resource_pool *pool =
3981 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
3982
3983 if (!pool)
3984 return NULL;
3985
d9e32672 3986 if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
7ed4e635
HW		 3987 return &pool->base;
3988
3989 BREAK_TO_DEBUGGER();
3990 kfree(pool);
3991 return NULL;
3992}
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