[thirdparty/kernel/stable.git] / drivers / gpu / drm / amd / display / dc / inc / hw / timing_generator.h

/*
 * Copyright 2012-15 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: AMD
 *
 */

#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
#define __DAL_TIMING_GENERATOR_TYPES_H__

#include "hw_shared.h"

struct dc_bios;

/* Contains CRTC vertical/horizontal pixel counters */
struct crtc_position {
	int32_t vertical_count;
	int32_t horizontal_count;
	int32_t nominal_vcount;
};

struct dcp_gsl_params {
	int gsl_group;
	int gsl_master;
};

struct gsl_params {
	int gsl0_en;
	int gsl1_en;
	int gsl2_en;
	int gsl_master_en;
	int gsl_master_mode;
	int master_update_lock_gsl_en;
	int gsl_window_start_x;
	int gsl_window_end_x;
	int gsl_window_start_y;
	int gsl_window_end_y;
};

/* define the structure of Dynamic Refresh Mode */
struct drr_params {
	uint32_t vertical_total_min;
	uint32_t vertical_total_max;
	bool immediate_flip;
};

#define LEFT_EYE_3D_PRIMARY_SURFACE 1
#define RIGHT_EYE_3D_PRIMARY_SURFACE 0

enum crtc_state {
	CRTC_STATE_VBLANK = 0,
	CRTC_STATE_VACTIVE
};

struct _dlg_otg_param {
	int vstartup_start;
	int vupdate_offset;
	int vupdate_width;
	int vready_offset;
	enum signal_type signal;
};

struct vupdate_keepout_params {
	int start_offset;
	int end_offset;
	int enable;
};

struct crtc_stereo_flags {
	uint8_t PROGRAM_STEREO         : 1;
	uint8_t PROGRAM_POLARITY       : 1;
	uint8_t RIGHT_EYE_POLARITY     : 1;
	uint8_t FRAME_PACKED           : 1;
	uint8_t DISABLE_STEREO_DP_SYNC : 1;
};

enum crc_selection {
	/* Order must match values expected by hardware */
	UNION_WINDOW_A_B = 0,
	UNION_WINDOW_A_NOT_B,
	UNION_WINDOW_NOT_A_B,
	UNION_WINDOW_NOT_A_NOT_B,
	INTERSECT_WINDOW_A_B,
	INTERSECT_WINDOW_A_NOT_B,
	INTERSECT_WINDOW_NOT_A_B,
	INTERSECT_WINDOW_NOT_A_NOT_B,
};

struct crc_params {
	/* Regions used to calculate CRC*/
	uint16_t windowa_x_start;
	uint16_t windowa_x_end;
	uint16_t windowa_y_start;
	uint16_t windowa_y_end;

	uint16_t windowb_x_start;
	uint16_t windowb_x_end;
	uint16_t windowb_y_start;
	uint16_t windowb_y_end;

	enum crc_selection selection;

	bool continuous_mode;
	bool enable;
};

struct timing_generator {
	const struct timing_generator_funcs *funcs;
	struct dc_bios *bp;
	struct dc_context *ctx;
	struct _dlg_otg_param dlg_otg_param;
	int inst;
};

struct dc_crtc_timing;

struct drr_params;

union vline_config;


enum vline_select {
	VLINE0,
	VLINE1,
	VLINE2
};

struct timing_generator_funcs {
	bool (*validate_timing)(struct timing_generator *tg,
							const struct dc_crtc_timing *timing);
	void (*program_timing)(struct timing_generator *tg,
							const struct dc_crtc_timing *timing,
							bool use_vbios);
	void (*program_vline_interrupt)(
			struct timing_generator *optc,
			const struct dc_crtc_timing *dc_crtc_timing,
			enum vline_select vline,
			const union vline_config *vline_config);

	void (*program_vupdate_interrupt)(struct timing_generator *optc,
			const struct dc_crtc_timing *dc_crtc_timing);
	bool (*enable_crtc)(struct timing_generator *tg);
	bool (*disable_crtc)(struct timing_generator *tg);
	bool (*is_counter_moving)(struct timing_generator *tg);
	void (*get_position)(struct timing_generator *tg,
				struct crtc_position *position);

	uint32_t (*get_frame_count)(struct timing_generator *tg);
	void (*get_scanoutpos)(
		struct timing_generator *tg,
		uint32_t *v_blank_start,
		uint32_t *v_blank_end,
		uint32_t *h_position,
		uint32_t *v_position);
	bool (*get_otg_active_size)(struct timing_generator *optc,
			uint32_t *otg_active_width,
			uint32_t *otg_active_height);
	bool (*is_matching_timing)(struct timing_generator *tg,
			const struct dc_crtc_timing *otg_timing);
	void (*set_early_control)(struct timing_generator *tg,
							   uint32_t early_cntl);
	void (*wait_for_state)(struct timing_generator *tg,
							enum crtc_state state);
	void (*set_blank)(struct timing_generator *tg,
					bool enable_blanking);
	bool (*is_blanked)(struct timing_generator *tg);
	void (*set_overscan_blank_color) (struct timing_generator *tg, const struct tg_color *color);
	void (*set_blank_color)(struct timing_generator *tg, const struct tg_color *color);
	void (*set_colors)(struct timing_generator *tg,
						const struct tg_color *blank_color,
						const struct tg_color *overscan_color);

	void (*disable_vga)(struct timing_generator *tg);
	bool (*did_triggered_reset_occur)(struct timing_generator *tg);
	void (*setup_global_swap_lock)(struct timing_generator *tg,
							const struct dcp_gsl_params *gsl_params);
	void (*unlock)(struct timing_generator *tg);
	void (*lock)(struct timing_generator *tg);
	void (*enable_reset_trigger)(struct timing_generator *tg,
				     int source_tg_inst);
	void (*enable_crtc_reset)(struct timing_generator *tg,
				  int source_tg_inst,
				  struct crtc_trigger_info *crtc_tp);
	void (*disable_reset_trigger)(struct timing_generator *tg);
	void (*tear_down_global_swap_lock)(struct timing_generator *tg);
	void (*enable_advanced_request)(struct timing_generator *tg,
					bool enable, const struct dc_crtc_timing *timing);
	void (*set_drr)(struct timing_generator *tg, const struct drr_params *params);
	void (*set_static_screen_control)(struct timing_generator *tg,
							uint32_t value);
	void (*set_test_pattern)(
		struct timing_generator *tg,
		enum controller_dp_test_pattern test_pattern,
		enum dc_color_depth color_depth);

	bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width);

	void (*program_global_sync)(struct timing_generator *tg);
	void (*enable_optc_clock)(struct timing_generator *tg, bool enable);
	void (*program_stereo)(struct timing_generator *tg,
		const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags);
	bool (*is_stereo_left_eye)(struct timing_generator *tg);

	void (*set_blank_data_double_buffer)(struct timing_generator *tg, bool enable);

	void (*tg_init)(struct timing_generator *tg);
	bool (*is_tg_enabled)(struct timing_generator *tg);
	bool (*is_optc_underflow_occurred)(struct timing_generator *tg);
	void (*clear_optc_underflow)(struct timing_generator *tg);

	/**
	 * Configure CRCs for the given timing generator. Return false if TG is
	 * not on.
	 */
	bool (*configure_crc)(struct timing_generator *tg,
			       const struct crc_params *params);

	/**
	 * Get CRCs for the given timing generator. Return false if CRCs are
	 * not enabled (via configure_crc).
	 */
	bool (*get_crc)(struct timing_generator *tg,
			uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb);

};

#endif
Commit	Line	Data
4562236b HW	1	/*
	2	* Copyright 2012-15 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: AMD
	23	*
	24	*/
	25
	26	#ifndef __DAL_TIMING_GENERATOR_TYPES_H__
	27	#define __DAL_TIMING_GENERATOR_TYPES_H__
	28
f7f36c1f EB	29	#include "hw_shared.h"
f7f36c1f EB	30
4562236b HW	31	struct dc_bios;
4562236b HW	32
4562236b HW	33	/* Contains CRTC vertical/horizontal pixel counters */
4562236b HW	34	struct crtc_position {
72ada5f7 EC	35	int32_t vertical_count;
	36	int32_t horizontal_count;
	37	int32_t nominal_vcount;
4562236b HW	38	};
	39
	40	struct dcp_gsl_params {
	41	int gsl_group;
	42	int gsl_master;
	43	};
	44
4b4f8f74 YHL	45	struct gsl_params {
	46	int gsl0_en;
	47	int gsl1_en;
	48	int gsl2_en;
	49	int gsl_master_en;
	50	int gsl_master_mode;
	51	int master_update_lock_gsl_en;
	52	int gsl_window_start_x;
	53	int gsl_window_end_x;
	54	int gsl_window_start_y;
	55	int gsl_window_end_y;
	56	};
	57
9c3b2b50 TC	58	/* define the structure of Dynamic Refresh Mode */
	59	struct drr_params {
	60	uint32_t vertical_total_min;
	61	uint32_t vertical_total_max;
	62	bool immediate_flip;
	63	};
	64
4562236b HW	65	#define LEFT_EYE_3D_PRIMARY_SURFACE 1
	66	#define RIGHT_EYE_3D_PRIMARY_SURFACE 0
	67
4562236b HW	68	enum crtc_state {
	69	CRTC_STATE_VBLANK = 0,
	70	CRTC_STATE_VACTIVE
	71	};
43193c79	72
ff5ef992 AD	73	struct _dlg_otg_param {
	74	int vstartup_start;
	75	int vupdate_offset;
	76	int vupdate_width;
	77	int vready_offset;
	78	enum signal_type signal;
	79	};
9edba557	80
4b4f8f74 YHL	81	struct vupdate_keepout_params {
	82	int start_offset;
	83	int end_offset;
	84	int enable;
	85	};
	86
9edba557 VP	87	struct crtc_stereo_flags {
	88	uint8_t PROGRAM_STEREO : 1;
	89	uint8_t PROGRAM_POLARITY : 1;
	90	uint8_t RIGHT_EYE_POLARITY : 1;
	91	uint8_t FRAME_PACKED : 1;
	92	uint8_t DISABLE_STEREO_DP_SYNC : 1;
	93	};
	94
31aec354 LSL	95	enum crc_selection {
	96	/* Order must match values expected by hardware */
	97	UNION_WINDOW_A_B = 0,
	98	UNION_WINDOW_A_NOT_B,
	99	UNION_WINDOW_NOT_A_B,
	100	UNION_WINDOW_NOT_A_NOT_B,
	101	INTERSECT_WINDOW_A_B,
	102	INTERSECT_WINDOW_A_NOT_B,
	103	INTERSECT_WINDOW_NOT_A_B,
	104	INTERSECT_WINDOW_NOT_A_NOT_B,
	105	};
	106
	107	struct crc_params {
	108	/* Regions used to calculate CRC*/
	109	uint16_t windowa_x_start;
	110	uint16_t windowa_x_end;
	111	uint16_t windowa_y_start;
	112	uint16_t windowa_y_end;
	113
	114	uint16_t windowb_x_start;
	115	uint16_t windowb_x_end;
	116	uint16_t windowb_y_start;
	117	uint16_t windowb_y_end;
	118
	119	enum crc_selection selection;
	120
	121	bool continuous_mode;
	122	bool enable;
	123	};
	124
4562236b HW	125	struct timing_generator {
	126	const struct timing_generator_funcs *funcs;
	127	struct dc_bios *bp;
	128	struct dc_context *ctx;
ff5ef992	129	struct _dlg_otg_param dlg_otg_param;
4562236b HW	130	int inst;
	131	};
	132
	133	struct dc_crtc_timing;
	134
	135	struct drr_params;
	136
810ece19	137	union vline_config;
8fde60b7 FD	138
	139
	140	enum vline_select {
	141	VLINE0,
	142	VLINE1,
	143	VLINE2
	144	};
	145
4562236b HW	146	struct timing_generator_funcs {
	147	bool (validate_timing)(struct timing_generator tg,
	148	const struct dc_crtc_timing *timing);
	149	void (program_timing)(struct timing_generator tg,
	150	const struct dc_crtc_timing *timing,
	151	bool use_vbios);
810ece19 YS	152	void (*program_vline_interrupt)(
	153	struct timing_generator *optc,
	154	const struct dc_crtc_timing *dc_crtc_timing,
8fde60b7	155	enum vline_select vline,
810ece19	156	const union vline_config *vline_config);
a122b62d AK	157
	158	void (program_vupdate_interrupt)(struct timing_generator optc,
	159	const struct dc_crtc_timing *dc_crtc_timing);
4562236b HW	160	bool (enable_crtc)(struct timing_generator tg);
	161	bool (disable_crtc)(struct timing_generator tg);
	162	bool (is_counter_moving)(struct timing_generator tg);
	163	void (get_position)(struct timing_generator tg,
72ada5f7 EC	164	struct crtc_position *position);
72ada5f7 EC	165
4562236b	166	uint32_t (get_frame_count)(struct timing_generator tg);
81c50963	167	void (*get_scanoutpos)(
4562236b	168	struct timing_generator *tg,
81c50963 ST	169	uint32_t *v_blank_start,
	170	uint32_t *v_blank_end,
	171	uint32_t *h_position,
	172	uint32_t *v_position);
0f6ca3ba EB	173	bool (get_otg_active_size)(struct timing_generator optc,
	174	uint32_t *otg_active_width,
	175	uint32_t *otg_active_height);
68f1a00c AK	176	bool (is_matching_timing)(struct timing_generator tg,
68f1a00c AK	177	const struct dc_crtc_timing *otg_timing);
4562236b HW	178	void (set_early_control)(struct timing_generator tg,
	179	uint32_t early_cntl);
	180	void (wait_for_state)(struct timing_generator tg,
	181	enum crtc_state state);
4b5e7d62	182	void (set_blank)(struct timing_generator tg,
4562236b HW	183	bool enable_blanking);
	184	bool (is_blanked)(struct timing_generator tg);
	185	void (set_overscan_blank_color) (struct timing_generator tg, const struct tg_color *color);
	186	void (set_blank_color)(struct timing_generator tg, const struct tg_color *color);
	187	void (set_colors)(struct timing_generator tg,
	188	const struct tg_color *blank_color,
	189	const struct tg_color *overscan_color);
	190
	191	void (disable_vga)(struct timing_generator tg);
	192	bool (did_triggered_reset_occur)(struct timing_generator tg);
	193	void (setup_global_swap_lock)(struct timing_generator tg,
	194	const struct dcp_gsl_params *gsl_params);
	195	void (unlock)(struct timing_generator tg);
	196	void (lock)(struct timing_generator tg);
fa2123db ML	197	void (enable_reset_trigger)(struct timing_generator tg,
	198	int source_tg_inst);
	199	void (enable_crtc_reset)(struct timing_generator tg,
	200	int source_tg_inst,
	201	struct crtc_trigger_info *crtc_tp);
4562236b HW	202	void (disable_reset_trigger)(struct timing_generator tg);
	203	void (tear_down_global_swap_lock)(struct timing_generator tg);
	204	void (enable_advanced_request)(struct timing_generator tg,
	205	bool enable, const struct dc_crtc_timing *timing);
	206	void (set_drr)(struct timing_generator tg, const struct drr_params *params);
	207	void (set_static_screen_control)(struct timing_generator tg,
	208	uint32_t value);
	209	void (*set_test_pattern)(
	210	struct timing_generator *tg,
	211	enum controller_dp_test_pattern test_pattern,
	212	enum dc_color_depth color_depth);
	213
667e1498 AG	214	bool (arm_vert_intr)(struct timing_generator tg, uint8_t width);
667e1498 AG	215
ff5ef992 AD	216	void (program_global_sync)(struct timing_generator tg);
ff5ef992 AD	217	void (enable_optc_clock)(struct timing_generator tg, bool enable);
9edba557 VP	218	void (program_stereo)(struct timing_generator tg,
	219	const struct dc_crtc_timing timing, struct crtc_stereo_flags flags);
	220	bool (is_stereo_left_eye)(struct timing_generator tg);
38614212 YS	221
38614212 YS	222	void (set_blank_data_double_buffer)(struct timing_generator tg, bool enable);
073a45e8 YS	223
073a45e8 YS	224	void (tg_init)(struct timing_generator tg);
0af4096d	225	bool (is_tg_enabled)(struct timing_generator tg);
5cc2687c YS	226	bool (is_optc_underflow_occurred)(struct timing_generator tg);
5cc2687c YS	227	void (clear_optc_underflow)(struct timing_generator tg);
31aec354 LSL	228
	229	/**
	230	* Configure CRCs for the given timing generator. Return false if TG is
	231	* not on.
	232	*/
	233	bool (configure_crc)(struct timing_generator tg,
	234	const struct crc_params *params);
	235
	236	/**
	237	* Get CRCs for the given timing generator. Return false if CRCs are
	238	* not enabled (via configure_crc).
	239	*/
	240	bool (get_crc)(struct timing_generator tg,
	241	uint32_t r_cr, uint32_t g_y, uint32_t *b_cb);
5f353208	242
4562236b HW	243	};
	244
	245	#endif