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d38ceaf9 AD |
1 | /* |
2 | * Copyright 2014 Advanced Micro Devices, Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | */ | |
23 | #ifndef __AMDGPU_DPM_H__ | |
24 | #define __AMDGPU_DPM_H__ | |
25 | ||
bc143d8b EQ |
26 | /* Argument for PPSMC_MSG_GpuChangeState */ |
27 | enum gfx_change_state { | |
28 | sGpuChangeState_D0Entry = 1, | |
29 | sGpuChangeState_D3Entry, | |
30 | }; | |
31 | ||
cf097881 AD |
32 | enum amdgpu_int_thermal_type { |
33 | THERMAL_TYPE_NONE, | |
34 | THERMAL_TYPE_EXTERNAL, | |
35 | THERMAL_TYPE_EXTERNAL_GPIO, | |
36 | THERMAL_TYPE_RV6XX, | |
37 | THERMAL_TYPE_RV770, | |
38 | THERMAL_TYPE_ADT7473_WITH_INTERNAL, | |
39 | THERMAL_TYPE_EVERGREEN, | |
40 | THERMAL_TYPE_SUMO, | |
41 | THERMAL_TYPE_NI, | |
42 | THERMAL_TYPE_SI, | |
43 | THERMAL_TYPE_EMC2103_WITH_INTERNAL, | |
44 | THERMAL_TYPE_CI, | |
45 | THERMAL_TYPE_KV, | |
46 | }; | |
47 | ||
50fe04d4 GC |
48 | enum amdgpu_runpm_mode { |
49 | AMDGPU_RUNPM_NONE, | |
50 | AMDGPU_RUNPM_PX, | |
51 | AMDGPU_RUNPM_BOCO, | |
52 | AMDGPU_RUNPM_BACO, | |
53 | }; | |
54 | ||
cf097881 AD |
55 | struct amdgpu_ps { |
56 | u32 caps; /* vbios flags */ | |
57 | u32 class; /* vbios flags */ | |
58 | u32 class2; /* vbios flags */ | |
59 | /* UVD clocks */ | |
60 | u32 vclk; | |
61 | u32 dclk; | |
62 | /* VCE clocks */ | |
63 | u32 evclk; | |
64 | u32 ecclk; | |
65 | bool vce_active; | |
0d8de7ca | 66 | enum amd_vce_level vce_level; |
cf097881 AD |
67 | /* asic priv */ |
68 | void *ps_priv; | |
69 | }; | |
70 | ||
71 | struct amdgpu_dpm_thermal { | |
72 | /* thermal interrupt work */ | |
73 | struct work_struct work; | |
74 | /* low temperature threshold */ | |
75 | int min_temp; | |
76 | /* high temperature threshold */ | |
77 | int max_temp; | |
901cb599 EQ |
78 | /* edge max emergency(shutdown) temp */ |
79 | int max_edge_emergency_temp; | |
437ccd17 EQ |
80 | /* hotspot low temperature threshold */ |
81 | int min_hotspot_temp; | |
82 | /* hotspot high temperature critical threshold */ | |
83 | int max_hotspot_crit_temp; | |
901cb599 EQ |
84 | /* hotspot max emergency(shutdown) temp */ |
85 | int max_hotspot_emergency_temp; | |
437ccd17 EQ |
86 | /* memory low temperature threshold */ |
87 | int min_mem_temp; | |
88 | /* memory high temperature critical threshold */ | |
89 | int max_mem_crit_temp; | |
901cb599 EQ |
90 | /* memory max emergency(shutdown) temp */ |
91 | int max_mem_emergency_temp; | |
064329c5 EQ |
92 | /* SWCTF threshold */ |
93 | int sw_ctf_threshold; | |
cf097881 AD |
94 | /* was last interrupt low to high or high to low */ |
95 | bool high_to_low; | |
96 | /* interrupt source */ | |
97 | struct amdgpu_irq_src irq; | |
98 | }; | |
99 | ||
cf097881 AD |
100 | struct amdgpu_clock_and_voltage_limits { |
101 | u32 sclk; | |
102 | u32 mclk; | |
103 | u16 vddc; | |
104 | u16 vddci; | |
105 | }; | |
106 | ||
107 | struct amdgpu_clock_array { | |
108 | u32 count; | |
109 | u32 *values; | |
110 | }; | |
111 | ||
112 | struct amdgpu_clock_voltage_dependency_entry { | |
113 | u32 clk; | |
114 | u16 v; | |
115 | }; | |
116 | ||
117 | struct amdgpu_clock_voltage_dependency_table { | |
118 | u32 count; | |
119 | struct amdgpu_clock_voltage_dependency_entry *entries; | |
120 | }; | |
121 | ||
122 | union amdgpu_cac_leakage_entry { | |
123 | struct { | |
124 | u16 vddc; | |
125 | u32 leakage; | |
126 | }; | |
127 | struct { | |
128 | u16 vddc1; | |
129 | u16 vddc2; | |
130 | u16 vddc3; | |
131 | }; | |
132 | }; | |
133 | ||
134 | struct amdgpu_cac_leakage_table { | |
135 | u32 count; | |
136 | union amdgpu_cac_leakage_entry *entries; | |
137 | }; | |
138 | ||
139 | struct amdgpu_phase_shedding_limits_entry { | |
140 | u16 voltage; | |
141 | u32 sclk; | |
142 | u32 mclk; | |
143 | }; | |
144 | ||
145 | struct amdgpu_phase_shedding_limits_table { | |
146 | u32 count; | |
147 | struct amdgpu_phase_shedding_limits_entry *entries; | |
148 | }; | |
149 | ||
150 | struct amdgpu_uvd_clock_voltage_dependency_entry { | |
151 | u32 vclk; | |
152 | u32 dclk; | |
153 | u16 v; | |
154 | }; | |
155 | ||
156 | struct amdgpu_uvd_clock_voltage_dependency_table { | |
157 | u8 count; | |
158 | struct amdgpu_uvd_clock_voltage_dependency_entry *entries; | |
159 | }; | |
160 | ||
161 | struct amdgpu_vce_clock_voltage_dependency_entry { | |
162 | u32 ecclk; | |
163 | u32 evclk; | |
164 | u16 v; | |
165 | }; | |
166 | ||
167 | struct amdgpu_vce_clock_voltage_dependency_table { | |
168 | u8 count; | |
169 | struct amdgpu_vce_clock_voltage_dependency_entry *entries; | |
170 | }; | |
171 | ||
172 | struct amdgpu_ppm_table { | |
173 | u8 ppm_design; | |
174 | u16 cpu_core_number; | |
175 | u32 platform_tdp; | |
176 | u32 small_ac_platform_tdp; | |
177 | u32 platform_tdc; | |
178 | u32 small_ac_platform_tdc; | |
179 | u32 apu_tdp; | |
180 | u32 dgpu_tdp; | |
181 | u32 dgpu_ulv_power; | |
182 | u32 tj_max; | |
183 | }; | |
184 | ||
185 | struct amdgpu_cac_tdp_table { | |
186 | u16 tdp; | |
187 | u16 configurable_tdp; | |
188 | u16 tdc; | |
189 | u16 battery_power_limit; | |
190 | u16 small_power_limit; | |
191 | u16 low_cac_leakage; | |
192 | u16 high_cac_leakage; | |
193 | u16 maximum_power_delivery_limit; | |
194 | }; | |
195 | ||
196 | struct amdgpu_dpm_dynamic_state { | |
197 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; | |
198 | struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; | |
199 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; | |
200 | struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; | |
201 | struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; | |
202 | struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; | |
203 | struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; | |
204 | struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; | |
205 | struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; | |
206 | struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; | |
207 | struct amdgpu_clock_array valid_sclk_values; | |
208 | struct amdgpu_clock_array valid_mclk_values; | |
209 | struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; | |
210 | struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; | |
211 | u32 mclk_sclk_ratio; | |
212 | u32 sclk_mclk_delta; | |
213 | u16 vddc_vddci_delta; | |
214 | u16 min_vddc_for_pcie_gen2; | |
215 | struct amdgpu_cac_leakage_table cac_leakage_table; | |
216 | struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; | |
217 | struct amdgpu_ppm_table *ppm_table; | |
218 | struct amdgpu_cac_tdp_table *cac_tdp_table; | |
219 | }; | |
220 | ||
221 | struct amdgpu_dpm_fan { | |
222 | u16 t_min; | |
223 | u16 t_med; | |
224 | u16 t_high; | |
225 | u16 pwm_min; | |
226 | u16 pwm_med; | |
227 | u16 pwm_high; | |
228 | u8 t_hyst; | |
229 | u32 cycle_delay; | |
230 | u16 t_max; | |
231 | u8 control_mode; | |
232 | u16 default_max_fan_pwm; | |
233 | u16 default_fan_output_sensitivity; | |
234 | u16 fan_output_sensitivity; | |
235 | bool ucode_fan_control; | |
236 | }; | |
237 | ||
cf097881 AD |
238 | struct amdgpu_dpm { |
239 | struct amdgpu_ps *ps; | |
240 | /* number of valid power states */ | |
241 | int num_ps; | |
242 | /* current power state that is active */ | |
243 | struct amdgpu_ps *current_ps; | |
244 | /* requested power state */ | |
245 | struct amdgpu_ps *requested_ps; | |
246 | /* boot up power state */ | |
247 | struct amdgpu_ps *boot_ps; | |
248 | /* default uvd power state */ | |
249 | struct amdgpu_ps *uvd_ps; | |
250 | /* vce requirements */ | |
66ba1afd | 251 | u32 num_of_vce_states; |
0d8de7ca RZ |
252 | struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS]; |
253 | enum amd_vce_level vce_level; | |
cf097881 AD |
254 | enum amd_pm_state_type state; |
255 | enum amd_pm_state_type user_state; | |
86f8c599 RZ |
256 | enum amd_pm_state_type last_state; |
257 | enum amd_pm_state_type last_user_state; | |
cf097881 AD |
258 | u32 platform_caps; |
259 | u32 voltage_response_time; | |
260 | u32 backbias_response_time; | |
261 | void *priv; | |
262 | u32 new_active_crtcs; | |
263 | int new_active_crtc_count; | |
264 | u32 current_active_crtcs; | |
265 | int current_active_crtc_count; | |
266 | struct amdgpu_dpm_dynamic_state dyn_state; | |
267 | struct amdgpu_dpm_fan fan; | |
268 | u32 tdp_limit; | |
269 | u32 near_tdp_limit; | |
270 | u32 near_tdp_limit_adjusted; | |
271 | u32 sq_ramping_threshold; | |
272 | u32 cac_leakage; | |
273 | u16 tdp_od_limit; | |
274 | u32 tdp_adjustment; | |
275 | u16 load_line_slope; | |
276 | bool power_control; | |
cf097881 AD |
277 | /* special states active */ |
278 | bool thermal_active; | |
279 | bool uvd_active; | |
280 | bool vce_active; | |
281 | /* thermal handling */ | |
282 | struct amdgpu_dpm_thermal thermal; | |
283 | /* forced levels */ | |
e5d03ac2 | 284 | enum amd_dpm_forced_level forced_level; |
cf097881 AD |
285 | }; |
286 | ||
6c08e0ef EQ |
287 | enum ip_power_state { |
288 | POWER_STATE_UNKNOWN, | |
289 | POWER_STATE_ON, | |
290 | POWER_STATE_OFF, | |
291 | }; | |
292 | ||
7e31a858 EQ |
293 | /* Used to mask smu debug modes */ |
294 | #define SMU_DEBUG_HALT_ON_ERROR 0x1 | |
295 | ||
2f60dd50 LT |
296 | #define MAX_SMU_I2C_BUSES 2 |
297 | ||
298 | struct amdgpu_smu_i2c_bus { | |
299 | struct i2c_adapter adapter; | |
300 | struct amdgpu_device *adev; | |
301 | int port; | |
302 | struct mutex mutex; | |
303 | }; | |
304 | ||
b874c667 EQ |
305 | struct config_table_setting |
306 | { | |
307 | uint16_t gfxclk_average_tau; | |
308 | uint16_t socclk_average_tau; | |
309 | uint16_t uclk_average_tau; | |
310 | uint16_t gfx_activity_average_tau; | |
311 | uint16_t mem_activity_average_tau; | |
312 | uint16_t socket_power_average_tau; | |
313 | uint16_t apu_socket_power_average_tau; | |
314 | uint16_t fclk_average_tau; | |
315 | }; | |
316 | ||
d7bf1b55 EQ |
317 | #define OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE BIT(0) |
318 | #define OD_OPS_SUPPORT_FAN_CURVE_SET BIT(1) | |
548009ad EQ |
319 | #define OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE BIT(2) |
320 | #define OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET BIT(3) | |
47cf6fcb EQ |
321 | #define OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE BIT(4) |
322 | #define OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET BIT(5) | |
eedd5a34 EQ |
323 | #define OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE BIT(6) |
324 | #define OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET BIT(7) | |
9df5d008 EQ |
325 | #define OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE BIT(8) |
326 | #define OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET BIT(9) | |
d7bf1b55 | 327 | |
cf097881 AD |
328 | struct amdgpu_pm { |
329 | struct mutex mutex; | |
330 | u32 current_sclk; | |
331 | u32 current_mclk; | |
332 | u32 default_sclk; | |
333 | u32 default_mclk; | |
334 | struct amdgpu_i2c_chan *i2c_bus; | |
84dd1f69 | 335 | bool bus_locked; |
cf097881 AD |
336 | /* internal thermal controller on rv6xx+ */ |
337 | enum amdgpu_int_thermal_type int_thermal_type; | |
338 | struct device *int_hwmon_dev; | |
339 | /* fan control parameters */ | |
340 | bool no_fan; | |
341 | u8 fan_pulses_per_revolution; | |
342 | u8 fan_min_rpm; | |
343 | u8 fan_max_rpm; | |
344 | /* dpm */ | |
345 | bool dpm_enabled; | |
346 | bool sysfs_initialized; | |
347 | struct amdgpu_dpm dpm; | |
348 | const struct firmware *fw; /* SMC firmware */ | |
349 | uint32_t fw_version; | |
cf097881 AD |
350 | uint32_t pcie_gen_mask; |
351 | uint32_t pcie_mlw_mask; | |
4562236b | 352 | struct amd_pp_display_configuration pm_display_cfg;/* set by dc */ |
7951e376 RZ |
353 | uint32_t smu_prv_buffer_size; |
354 | struct amdgpu_bo *smu_prv_buffer; | |
600ae890 | 355 | bool ac_power; |
3b94fb10 LG |
356 | /* powerplay feature */ |
357 | uint32_t pp_feature; | |
358 | ||
9015d60c | 359 | /* Used for I2C access to various EEPROMs on relevant ASICs */ |
2f60dd50 LT |
360 | struct amdgpu_smu_i2c_bus smu_i2c[MAX_SMU_I2C_BUSES]; |
361 | struct i2c_adapter *ras_eeprom_i2c_bus; | |
362 | struct i2c_adapter *fru_eeprom_i2c_bus; | |
ba02fd6b | 363 | struct list_head pm_attr_list; |
6c08e0ef EQ |
364 | |
365 | atomic_t pwr_state[AMD_IP_BLOCK_TYPE_NUM]; | |
7e31a858 EQ |
366 | |
367 | /* | |
368 | * 0 = disabled (default), otherwise enable corresponding debug mode | |
369 | */ | |
370 | uint32_t smu_debug_mask; | |
d698a2c4 EQ |
371 | |
372 | bool pp_force_state_enabled; | |
8cda7a4f AD |
373 | |
374 | struct mutex stable_pstate_ctx_lock; | |
375 | struct amdgpu_ctx *stable_pstate_ctx; | |
b874c667 EQ |
376 | |
377 | struct config_table_setting config_table; | |
50fe04d4 GC |
378 | /* runtime mode */ |
379 | enum amdgpu_runpm_mode rpm_mode; | |
3e38b634 EQ |
380 | |
381 | struct list_head od_kobj_list; | |
d7bf1b55 | 382 | uint32_t od_feature_mask; |
cf097881 AD |
383 | }; |
384 | ||
4a5a2de6 KW |
385 | int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor, |
386 | void *data, uint32_t *size); | |
d38ceaf9 | 387 | |
c3ed0e72 KL |
388 | int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit); |
389 | int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit); | |
390 | ||
bca32528 KF |
391 | int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, |
392 | uint32_t block_type, bool gate); | |
393 | ||
c5bee44b LG |
394 | extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low); |
395 | ||
396 | extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low); | |
397 | ||
9530273e EQ |
398 | int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev, |
399 | uint32_t pstate); | |
400 | ||
401 | int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev, | |
402 | enum PP_SMC_POWER_PROFILE type, | |
403 | bool en); | |
404 | ||
405 | int amdgpu_dpm_baco_reset(struct amdgpu_device *adev); | |
406 | ||
407 | int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev); | |
230dd6bb | 408 | int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev); |
9530273e EQ |
409 | |
410 | bool amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev); | |
411 | ||
ea8139d8 WS |
412 | bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev); |
413 | int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev); | |
414 | ||
9530273e EQ |
415 | int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev, |
416 | enum pp_mp1_state mp1_state); | |
417 | ||
8c4e9105 PY |
418 | int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en); |
419 | ||
7101ab97 HR |
420 | int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev); |
421 | ||
9530273e EQ |
422 | int amdgpu_dpm_baco_exit(struct amdgpu_device *adev); |
423 | ||
424 | int amdgpu_dpm_baco_enter(struct amdgpu_device *adev); | |
425 | ||
53e0f1e6 HZ |
426 | int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev, |
427 | uint32_t cstate); | |
428 | ||
21e43386 LM |
429 | int amdgpu_dpm_get_xgmi_plpd_mode(struct amdgpu_device *adev, |
430 | char **mode); | |
431 | ||
432 | int amdgpu_dpm_set_xgmi_plpd_mode(struct amdgpu_device *adev, int mode); | |
433 | ||
f10bb940 EQ |
434 | int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev); |
435 | ||
b89e9eb6 EQ |
436 | int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev, |
437 | uint32_t msg_id); | |
438 | ||
20d3c28c EQ |
439 | int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev, |
440 | bool acquire); | |
441 | ||
e9372d23 EQ |
442 | void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev); |
443 | ||
84176663 | 444 | void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev); |
e9372d23 EQ |
445 | void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable); |
446 | void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable); | |
447 | void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable); | |
e9372d23 | 448 | int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version); |
bc143d8b EQ |
449 | int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable); |
450 | int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size); | |
d510eccf | 451 | int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size); |
bc143d8b EQ |
452 | int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev, |
453 | enum pp_clock_type type, | |
454 | uint32_t *min, | |
455 | uint32_t *max); | |
456 | int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev, | |
457 | enum pp_clock_type type, | |
458 | uint32_t min, | |
459 | uint32_t max); | |
13f5dbd6 | 460 | int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev); |
bc143d8b EQ |
461 | int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event, |
462 | uint64_t event_arg); | |
0ad7347a AA |
463 | int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value); |
464 | int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value); | |
465 | int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value); | |
bc143d8b EQ |
466 | int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value); |
467 | uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev); | |
468 | void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev, | |
469 | enum gfx_change_state state); | |
470 | int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev, | |
471 | void *umc_ecc); | |
79c65f3f EQ |
472 | struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev, |
473 | uint32_t idx); | |
474 | void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, enum amd_pm_state_type *state); | |
475 | void amdgpu_dpm_set_power_state(struct amdgpu_device *adev, | |
476 | enum amd_pm_state_type state); | |
477 | enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev); | |
478 | int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev, | |
479 | enum amd_dpm_forced_level level); | |
480 | int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev, | |
481 | struct pp_states_info *states); | |
482 | int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev, | |
483 | enum amd_pp_task task_id, | |
484 | enum amd_pm_state_type *user_state); | |
485 | int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table); | |
486 | int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev, | |
487 | uint32_t type, | |
488 | long *input, | |
489 | uint32_t size); | |
490 | int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev, | |
491 | uint32_t type, | |
492 | long *input, | |
493 | uint32_t size); | |
494 | int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev, | |
495 | enum pp_clock_type type, | |
496 | char *buf); | |
5d64f9bb DP |
497 | int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev, |
498 | enum pp_clock_type type, | |
499 | char *buf, | |
500 | int *offset); | |
79c65f3f EQ |
501 | int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev, |
502 | uint64_t ppfeature_masks); | |
503 | int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf); | |
504 | int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev, | |
505 | enum pp_clock_type type, | |
506 | uint32_t mask); | |
507 | int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev); | |
508 | int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value); | |
509 | int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev); | |
510 | int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value); | |
511 | int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev, | |
512 | char *buf); | |
513 | int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev, | |
514 | long *input, uint32_t size); | |
515 | int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table); | |
516 | int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev, | |
517 | uint32_t *fan_mode); | |
518 | int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev, | |
519 | uint32_t speed); | |
520 | int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev, | |
521 | uint32_t *speed); | |
522 | int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev, | |
523 | uint32_t *speed); | |
524 | int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev, | |
525 | uint32_t speed); | |
526 | int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev, | |
527 | uint32_t mode); | |
528 | int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev, | |
529 | uint32_t *limit, | |
530 | enum pp_power_limit_level pp_limit_level, | |
531 | enum pp_power_type power_type); | |
532 | int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev, | |
533 | uint32_t limit); | |
534 | int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev); | |
535 | int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev, | |
536 | struct seq_file *m); | |
537 | int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev, | |
538 | void **addr, | |
539 | size_t *size); | |
540 | int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev); | |
541 | int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev, | |
542 | const char *buf, | |
543 | size_t size); | |
544 | int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev); | |
545 | void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev); | |
13f5dbd6 EQ |
546 | int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev, |
547 | const struct amd_pp_display_configuration *input); | |
548 | int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev, | |
549 | enum amd_pp_clock_type type, | |
550 | struct amd_pp_clocks *clocks); | |
551 | int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev, | |
552 | struct amd_pp_simple_clock_info *clocks); | |
553 | int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev, | |
554 | enum amd_pp_clock_type type, | |
555 | struct pp_clock_levels_with_latency *clocks); | |
556 | int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev, | |
557 | enum amd_pp_clock_type type, | |
558 | struct pp_clock_levels_with_voltage *clocks); | |
559 | int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev, | |
560 | void *clock_ranges); | |
561 | int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev, | |
562 | struct pp_display_clock_request *clock); | |
563 | int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev, | |
564 | struct amd_pp_clock_info *clocks); | |
565 | void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev); | |
566 | int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev, | |
567 | uint32_t count); | |
568 | int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev, | |
569 | uint32_t clock); | |
570 | void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev, | |
571 | uint32_t clock); | |
572 | void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev, | |
573 | uint32_t clock); | |
574 | int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev, | |
575 | bool disable_memory_clock_switch); | |
576 | int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev, | |
577 | struct pp_smu_nv_clock_table *max_clocks); | |
578 | enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev, | |
579 | unsigned int *clock_values_in_khz, | |
580 | unsigned int *num_states); | |
581 | int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, | |
582 | struct dpm_clocks *clock_table); | |
d38ceaf9 | 583 | #endif |