[thirdparty/kernel/linux.git] / drivers / gpu / drm / bridge / analogix / analogix_dp_core.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * Header file for Analogix DP (Display Port) core interface driver.
 *
 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
 * Author: Jingoo Han <jg1.han@samsung.com>
 */

#ifndef _ANALOGIX_DP_CORE_H
#define _ANALOGIX_DP_CORE_H

#include <drm/drm_crtc.h>
#include <drm/drm_dp_helper.h>

#define DP_TIMEOUT_LOOP_COUNT 100
#define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 5
#define MAX_PLL_LOCK_LOOP 5

/* Training takes 22ms if AUX channel comm fails. Use this as retry interval */
#define DP_TIMEOUT_TRAINING_US			22000
#define DP_TIMEOUT_PSR_LOOP_MS			300

/* DP_MAX_LANE_COUNT */
#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)

/* DP_LANE_COUNT_SET */
#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)

/* DP_TRAINING_LANE0_SET */
#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)

enum link_lane_count_type {
	LANE_COUNT1 = 1,
	LANE_COUNT2 = 2,
	LANE_COUNT4 = 4
};

enum link_training_state {
	START,
	CLOCK_RECOVERY,
	EQUALIZER_TRAINING,
	FINISHED,
	FAILED
};

enum voltage_swing_level {
	VOLTAGE_LEVEL_0,
	VOLTAGE_LEVEL_1,
	VOLTAGE_LEVEL_2,
	VOLTAGE_LEVEL_3,
};

enum pre_emphasis_level {
	PRE_EMPHASIS_LEVEL_0,
	PRE_EMPHASIS_LEVEL_1,
	PRE_EMPHASIS_LEVEL_2,
	PRE_EMPHASIS_LEVEL_3,
};

enum pattern_set {
	PRBS7,
	D10_2,
	TRAINING_PTN1,
	TRAINING_PTN2,
	DP_NONE
};

enum color_space {
	COLOR_RGB,
	COLOR_YCBCR422,
	COLOR_YCBCR444
};

enum color_depth {
	COLOR_6,
	COLOR_8,
	COLOR_10,
	COLOR_12
};

enum color_coefficient {
	COLOR_YCBCR601,
	COLOR_YCBCR709
};

enum dynamic_range {
	VESA,
	CEA
};

enum pll_status {
	PLL_UNLOCKED,
	PLL_LOCKED
};

enum clock_recovery_m_value_type {
	CALCULATED_M,
	REGISTER_M
};

enum video_timing_recognition_type {
	VIDEO_TIMING_FROM_CAPTURE,
	VIDEO_TIMING_FROM_REGISTER
};

enum analog_power_block {
	AUX_BLOCK,
	CH0_BLOCK,
	CH1_BLOCK,
	CH2_BLOCK,
	CH3_BLOCK,
	ANALOG_TOTAL,
	POWER_ALL
};

enum dp_irq_type {
	DP_IRQ_TYPE_HP_CABLE_IN  = BIT(0),
	DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1),
	DP_IRQ_TYPE_HP_CHANGE    = BIT(2),
	DP_IRQ_TYPE_UNKNOWN      = BIT(3),
};

struct video_info {
	char *name;

	bool h_sync_polarity;
	bool v_sync_polarity;
	bool interlaced;

	enum color_space color_space;
	enum dynamic_range dynamic_range;
	enum color_coefficient ycbcr_coeff;
	enum color_depth color_depth;

	int max_link_rate;
	enum link_lane_count_type max_lane_count;
};

struct link_train {
	int eq_loop;
	int cr_loop[4];

	u8 link_rate;
	u8 lane_count;
	u8 training_lane[4];

	enum link_training_state lt_state;
};

struct analogix_dp_device {
	struct drm_encoder	*encoder;
	struct device		*dev;
	struct drm_device	*drm_dev;
	struct drm_connector	connector;
	struct drm_bridge	*bridge;
	struct drm_dp_aux       aux;
	struct clk		*clock;
	unsigned int		irq;
	void __iomem		*reg_base;

	struct video_info	video_info;
	struct link_train	link_train;
	struct phy		*phy;
	int			dpms_mode;
	int			hpd_gpio;
	bool                    force_hpd;
	bool			psr_enable;
	bool			fast_train_enable;

	struct mutex		panel_lock;
	bool			panel_is_modeset;

	struct analogix_dp_plat_data *plat_data;
};

/* analogix_dp_reg.c */
void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
void analogix_dp_stop_video(struct analogix_dp_device *dp);
void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
void analogix_dp_reset(struct analogix_dp_device *dp);
void analogix_dp_swreset(struct analogix_dp_device *dp);
void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp);
void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp);
enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
				       enum analog_power_block block,
				       bool enable);
int analogix_dp_init_analog_func(struct analogix_dp_device *dp);
void analogix_dp_init_hpd(struct analogix_dp_device *dp);
void analogix_dp_force_hpd(struct analogix_dp_device *dp);
enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
void analogix_dp_reset_aux(struct analogix_dp_device *dp);
void analogix_dp_init_aux(struct analogix_dp_device *dp);
int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
				      bool enable);
void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
				      enum pattern_set pattern);
void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
					u32 level);
void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
					u32 level);
void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
					u32 level);
void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
					u32 level);
void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
					 u32 training_lane);
void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
					 u32 training_lane);
void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
					 u32 training_lane);
void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
					 u32 training_lane);
u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
void analogix_dp_reset_macro(struct analogix_dp_device *dp);
void analogix_dp_init_video(struct analogix_dp_device *dp);

void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
				 enum clock_recovery_m_value_type type,
				 u32 m_value,
				 u32 n_value);
void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
				     bool enable);
void analogix_dp_start_video(struct analogix_dp_device *dp);
int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp);
int analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
			     struct edp_vsc_psr *vsc, bool blocking);
ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
			     struct drm_dp_aux_msg *msg);

#endif /* _ANALOGIX_DP_CORE_H */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
3424e3a4 YY	2	/*
	3	* Header file for Analogix DP (Display Port) core interface driver.
	4	*
	5	* Copyright (C) 2012 Samsung Electronics Co., Ltd.
	6	* Author: Jingoo Han <jg1.han@samsung.com>
3424e3a4 YY	7	*/
	8
	9	#ifndef _ANALOGIX_DP_CORE_H
	10	#define _ANALOGIX_DP_CORE_H
	11
	12	#include <drm/drm_crtc.h>
	13	#include <drm/drm_dp_helper.h>
	14
	15	#define DP_TIMEOUT_LOOP_COUNT 100
	16	#define MAX_CR_LOOP 5
	17	#define MAX_EQ_LOOP 5
8a335736	18	#define MAX_PLL_LOCK_LOOP 5
3424e3a4	19
f9d56805	20	/* Training takes 22ms if AUX channel comm fails. Use this as retry interval */
f9d56805	21	#define DP_TIMEOUT_TRAINING_US 22000
1d38e421 YY	22	#define DP_TIMEOUT_PSR_LOOP_MS 300
1d38e421 YY	23
398a3995 YY	24	/* DP_MAX_LANE_COUNT */
	25	#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
	26	#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
	27
	28	/* DP_LANE_COUNT_SET */
	29	#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
	30
	31	/* DP_TRAINING_LANE0_SET */
	32	#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
	33	#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
	34	#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
	35	#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
	36
3424e3a4 YY	37	enum link_lane_count_type {
	38	LANE_COUNT1 = 1,
	39	LANE_COUNT2 = 2,
	40	LANE_COUNT4 = 4
	41	};
	42
	43	enum link_training_state {
	44	START,
	45	CLOCK_RECOVERY,
	46	EQUALIZER_TRAINING,
	47	FINISHED,
	48	FAILED
	49	};
	50
	51	enum voltage_swing_level {
	52	VOLTAGE_LEVEL_0,
	53	VOLTAGE_LEVEL_1,
	54	VOLTAGE_LEVEL_2,
	55	VOLTAGE_LEVEL_3,
	56	};
	57
	58	enum pre_emphasis_level {
	59	PRE_EMPHASIS_LEVEL_0,
	60	PRE_EMPHASIS_LEVEL_1,
	61	PRE_EMPHASIS_LEVEL_2,
	62	PRE_EMPHASIS_LEVEL_3,
	63	};
	64
	65	enum pattern_set {
	66	PRBS7,
	67	D10_2,
	68	TRAINING_PTN1,
	69	TRAINING_PTN2,
	70	DP_NONE
	71	};
	72
	73	enum color_space {
	74	COLOR_RGB,
	75	COLOR_YCBCR422,
	76	COLOR_YCBCR444
	77	};
	78
	79	enum color_depth {
	80	COLOR_6,
	81	COLOR_8,
	82	COLOR_10,
	83	COLOR_12
	84	};
	85
	86	enum color_coefficient {
	87	COLOR_YCBCR601,
	88	COLOR_YCBCR709
	89	};
	90
	91	enum dynamic_range {
	92	VESA,
	93	CEA
	94	};
	95
	96	enum pll_status {
	97	PLL_UNLOCKED,
	98	PLL_LOCKED
	99	};
	100
101	enum clock_recovery_m_value_type {
102	CALCULATED_M,
103	REGISTER_M
104	};
105
106	enum video_timing_recognition_type {
107	VIDEO_TIMING_FROM_CAPTURE,
108	VIDEO_TIMING_FROM_REGISTER
109	};
110
111	enum analog_power_block {
112	AUX_BLOCK,
113	CH0_BLOCK,
114	CH1_BLOCK,
115	CH2_BLOCK,
116	CH3_BLOCK,
117	ANALOG_TOTAL,
118	POWER_ALL
119	};
120
121	enum dp_irq_type {
7608a9fb YY	122	DP_IRQ_TYPE_HP_CABLE_IN = BIT(0),
	123	DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1),
	124	DP_IRQ_TYPE_HP_CHANGE = BIT(2),
	125	DP_IRQ_TYPE_UNKNOWN = BIT(3),
3424e3a4 YY	126	};
	127
	128	struct video_info {
	129	char *name;
	130
	131	bool h_sync_polarity;
	132	bool v_sync_polarity;
	133	bool interlaced;
	134
	135	enum color_space color_space;
	136	enum dynamic_range dynamic_range;
	137	enum color_coefficient ycbcr_coeff;
	138	enum color_depth color_depth;
	139
0d0abd89 YY	140	int max_link_rate;
0d0abd89 YY	141	enum link_lane_count_type max_lane_count;
3424e3a4 YY	142	};
	143
	144	struct link_train {
	145	int eq_loop;
	146	int cr_loop[4];
	147
	148	u8 link_rate;
	149	u8 lane_count;
	150	u8 training_lane[4];
	151
	152	enum link_training_state lt_state;
	153	};
	154
	155	struct analogix_dp_device {
	156	struct drm_encoder *encoder;
	157	struct device *dev;
	158	struct drm_device *drm_dev;
	159	struct drm_connector connector;
	160	struct drm_bridge *bridge;
0d97ad03	161	struct drm_dp_aux aux;
3424e3a4 YY	162	struct clk *clock;
	163	unsigned int irq;
	164	void __iomem *reg_base;
	165
793ce4eb	166	struct video_info video_info;
3424e3a4	167	struct link_train link_train;
3424e3a4 YY	168	struct phy *phy;
	169	int dpms_mode;
	170	int hpd_gpio;
5cff007c	171	bool force_hpd;
243e398a	172	bool psr_enable;
7ba8fb57	173	bool fast_train_enable;
3424e3a4	174
0b8b059a SP	175	struct mutex panel_lock;
	176	bool panel_is_modeset;
	177
3424e3a4 YY	178	struct analogix_dp_plat_data *plat_data;
	179	};
	180
	181	/* analogix_dp_reg.c */
	182	void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
	183	void analogix_dp_stop_video(struct analogix_dp_device *dp);
	184	void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
	185	void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
	186	void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
	187	void analogix_dp_reset(struct analogix_dp_device *dp);
	188	void analogix_dp_swreset(struct analogix_dp_device *dp);
	189	void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
7b4b7a8d YY	190	void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp);
7b4b7a8d YY	191	void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp);
3424e3a4 YY	192	enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
	193	void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
	194	void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
	195	enum analog_power_block block,
	196	bool enable);
8a335736	197	int analogix_dp_init_analog_func(struct analogix_dp_device *dp);
3424e3a4	198	void analogix_dp_init_hpd(struct analogix_dp_device *dp);
5cff007c	199	void analogix_dp_force_hpd(struct analogix_dp_device *dp);
3424e3a4 YY	200	enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
	201	void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
	202	void analogix_dp_reset_aux(struct analogix_dp_device *dp);
	203	void analogix_dp_init_aux(struct analogix_dp_device *dp);
	204	int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
	205	void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
3424e3a4 YY	206	void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
	207	void analogix_dp_get_link_bandwidth(struct analogix_dp_device dp, u32 bwtype);
	208	void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
	209	void analogix_dp_get_lane_count(struct analogix_dp_device dp, u32 count);
bcbb7033 YY	210	void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
bcbb7033 YY	211	bool enable);
3424e3a4	212	void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
bcbb7033 YY	213	enum pattern_set pattern);
	214	void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
	215	u32 level);
	216	void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
	217	u32 level);
	218	void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
	219	u32 level);
	220	void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
	221	u32 level);
3424e3a4	222	void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
bcbb7033	223	u32 training_lane);
3424e3a4	224	void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
bcbb7033	225	u32 training_lane);
3424e3a4	226	void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
bcbb7033	227	u32 training_lane);
3424e3a4	228	void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
bcbb7033	229	u32 training_lane);
3424e3a4 YY	230	u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
	231	u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
	232	u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
	233	u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
	234	void analogix_dp_reset_macro(struct analogix_dp_device *dp);
	235	void analogix_dp_init_video(struct analogix_dp_device *dp);
	236
	237	void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
	238	int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
	239	void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
bcbb7033 YY	240	enum clock_recovery_m_value_type type,
	241	u32 m_value,
	242	u32 n_value);
3424e3a4	243	void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
bcbb7033 YY	244	void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
bcbb7033 YY	245	bool enable);
3424e3a4 YY	246	void analogix_dp_start_video(struct analogix_dp_device *dp);
	247	int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
	248	void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
	249	void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
	250	void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
5b3f84f2	251	void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp);
1d38e421	252	int analogix_dp_send_psr_spd(struct analogix_dp_device *dp,
ce31ddd5	253	struct edp_vsc_psr *vsc, bool blocking);
0d97ad03 TV	254	ssize_t analogix_dp_transfer(struct analogix_dp_device *dp,
0d97ad03 TV	255	struct drm_dp_aux_msg *msg);
5b3f84f2	256
3424e3a4	257	#endif /* _ANALOGIX_DP_CORE_H */