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Commit | Line | Data |
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a4fc5ed6 KP |
1 | /* |
2 | * Copyright © 2009 Keith Packard | |
3 | * | |
4 | * Permission to use, copy, modify, distribute, and sell this software and its | |
5 | * documentation for any purpose is hereby granted without fee, provided that | |
6 | * the above copyright notice appear in all copies and that both that copyright | |
7 | * notice and this permission notice appear in supporting documentation, and | |
8 | * that the name of the copyright holders not be used in advertising or | |
9 | * publicity pertaining to distribution of the software without specific, | |
10 | * written prior permission. The copyright holders make no representations | |
11 | * about the suitability of this software for any purpose. It is provided "as | |
12 | * is" without express or implied warranty. | |
13 | * | |
14 | * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, | |
15 | * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO | |
16 | * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR | |
17 | * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, | |
18 | * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER | |
19 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE | |
20 | * OF THIS SOFTWARE. | |
21 | */ | |
22 | ||
a4fc5ed6 | 23 | #include <linux/delay.h> |
a4fc5ed6 | 24 | #include <linux/errno.h> |
a4fc5ed6 | 25 | #include <linux/i2c.h> |
580fc13f JN |
26 | #include <linux/init.h> |
27 | #include <linux/kernel.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/sched.h> | |
96106c97 | 30 | #include <linux/seq_file.h> |
580fc13f | 31 | |
760285e7 | 32 | #include <drm/drm_dp_helper.h> |
580fc13f JN |
33 | #include <drm/drm_print.h> |
34 | #include <drm/drm_vblank.h> | |
a4fc5ed6 | 35 | |
e15c8f4b SV |
36 | #include "drm_crtc_helper_internal.h" |
37 | ||
28164fda SV |
38 | /** |
39 | * DOC: dp helpers | |
40 | * | |
41 | * These functions contain some common logic and helpers at various abstraction | |
42 | * levels to deal with Display Port sink devices and related things like DP aux | |
43 | * channel transfers, EDID reading over DP aux channels, decoding certain DPCD | |
44 | * blocks, ... | |
45 | */ | |
46 | ||
1ffdff13 | 47 | /* Helpers for DP link training */ |
0aec2881 | 48 | static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) |
1ffdff13 SV |
49 | { |
50 | return link_status[r - DP_LANE0_1_STATUS]; | |
51 | } | |
52 | ||
0aec2881 | 53 | static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], |
1ffdff13 SV |
54 | int lane) |
55 | { | |
56 | int i = DP_LANE0_1_STATUS + (lane >> 1); | |
57 | int s = (lane & 1) * 4; | |
58 | u8 l = dp_link_status(link_status, i); | |
59 | return (l >> s) & 0xf; | |
60 | } | |
61 | ||
0aec2881 | 62 | bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
1ffdff13 SV |
63 | int lane_count) |
64 | { | |
65 | u8 lane_align; | |
66 | u8 lane_status; | |
67 | int lane; | |
68 | ||
69 | lane_align = dp_link_status(link_status, | |
70 | DP_LANE_ALIGN_STATUS_UPDATED); | |
71 | if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) | |
72 | return false; | |
73 | for (lane = 0; lane < lane_count; lane++) { | |
74 | lane_status = dp_get_lane_status(link_status, lane); | |
75 | if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) | |
76 | return false; | |
77 | } | |
78 | return true; | |
79 | } | |
80 | EXPORT_SYMBOL(drm_dp_channel_eq_ok); | |
81 | ||
0aec2881 | 82 | bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], |
1ffdff13 SV |
83 | int lane_count) |
84 | { | |
85 | int lane; | |
86 | u8 lane_status; | |
87 | ||
88 | for (lane = 0; lane < lane_count; lane++) { | |
89 | lane_status = dp_get_lane_status(link_status, lane); | |
90 | if ((lane_status & DP_LANE_CR_DONE) == 0) | |
91 | return false; | |
92 | } | |
93 | return true; | |
94 | } | |
95 | EXPORT_SYMBOL(drm_dp_clock_recovery_ok); | |
0f037bde | 96 | |
0aec2881 | 97 | u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], |
0f037bde SV |
98 | int lane) |
99 | { | |
100 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
101 | int s = ((lane & 1) ? | |
102 | DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : | |
103 | DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); | |
104 | u8 l = dp_link_status(link_status, i); | |
105 | ||
106 | return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; | |
107 | } | |
108 | EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); | |
109 | ||
0aec2881 | 110 | u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], |
0f037bde SV |
111 | int lane) |
112 | { | |
113 | int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); | |
114 | int s = ((lane & 1) ? | |
115 | DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : | |
116 | DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); | |
117 | u8 l = dp_link_status(link_status, i); | |
118 | ||
119 | return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; | |
120 | } | |
121 | EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); | |
122 | ||
0aec2881 | 123 | void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { |
2f065d8a MA |
124 | int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & |
125 | DP_TRAINING_AUX_RD_MASK; | |
126 | ||
127 | if (rd_interval > 4) | |
128 | DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n", | |
129 | rd_interval); | |
130 | ||
131 | if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) | |
1a644cd4 SV |
132 | udelay(100); |
133 | else | |
2f065d8a | 134 | mdelay(rd_interval * 4); |
1a644cd4 SV |
135 | } |
136 | EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); | |
137 | ||
0aec2881 | 138 | void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { |
2f065d8a MA |
139 | int rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & |
140 | DP_TRAINING_AUX_RD_MASK; | |
141 | ||
142 | if (rd_interval > 4) | |
143 | DRM_DEBUG_KMS("AUX interval %d, out of range (max 4)\n", | |
144 | rd_interval); | |
145 | ||
146 | if (rd_interval == 0) | |
1a644cd4 SV |
147 | udelay(400); |
148 | else | |
2f065d8a | 149 | mdelay(rd_interval * 4); |
1a644cd4 SV |
150 | } |
151 | EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); | |
3b5c662e SV |
152 | |
153 | u8 drm_dp_link_rate_to_bw_code(int link_rate) | |
154 | { | |
155 | switch (link_rate) { | |
3b5c662e | 156 | default: |
cccf4e3f JN |
157 | WARN(1, "unknown DP link rate %d, using %x\n", link_rate, |
158 | DP_LINK_BW_1_62); | |
e9c0c874 | 159 | /* fall through */ |
cccf4e3f | 160 | case 162000: |
3b5c662e SV |
161 | return DP_LINK_BW_1_62; |
162 | case 270000: | |
163 | return DP_LINK_BW_2_7; | |
164 | case 540000: | |
165 | return DP_LINK_BW_5_4; | |
e0bd878a MN |
166 | case 810000: |
167 | return DP_LINK_BW_8_1; | |
3b5c662e SV |
168 | } |
169 | } | |
170 | EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); | |
171 | ||
172 | int drm_dp_bw_code_to_link_rate(u8 link_bw) | |
173 | { | |
174 | switch (link_bw) { | |
3b5c662e | 175 | default: |
cccf4e3f | 176 | WARN(1, "unknown DP link BW code %x, using 162000\n", link_bw); |
e9c0c874 | 177 | /* fall through */ |
cccf4e3f | 178 | case DP_LINK_BW_1_62: |
3b5c662e SV |
179 | return 162000; |
180 | case DP_LINK_BW_2_7: | |
181 | return 270000; | |
182 | case DP_LINK_BW_5_4: | |
183 | return 540000; | |
e0bd878a MN |
184 | case DP_LINK_BW_8_1: |
185 | return 810000; | |
3b5c662e SV |
186 | } |
187 | } | |
188 | EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); | |
c197db75 | 189 | |
79a2b161 VS |
190 | #define AUX_RETRY_INTERVAL 500 /* us */ |
191 | ||
a18b2192 LP |
192 | static inline void |
193 | drm_dp_dump_access(const struct drm_dp_aux *aux, | |
194 | u8 request, uint offset, void *buffer, int ret) | |
195 | { | |
196 | const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-"; | |
197 | ||
198 | if (ret > 0) | |
b6467446 JN |
199 | DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d) %*ph\n", |
200 | aux->name, offset, arrow, ret, min(ret, 20), buffer); | |
a18b2192 | 201 | else |
b6467446 JN |
202 | DRM_DEBUG_DP("%s: 0x%05x AUX %s (ret=%3d)\n", |
203 | aux->name, offset, arrow, ret); | |
a18b2192 LP |
204 | } |
205 | ||
c197db75 TR |
206 | /** |
207 | * DOC: dp helpers | |
208 | * | |
209 | * The DisplayPort AUX channel is an abstraction to allow generic, driver- | |
210 | * independent access to AUX functionality. Drivers can take advantage of | |
211 | * this by filling in the fields of the drm_dp_aux structure. | |
212 | * | |
213 | * Transactions are described using a hardware-independent drm_dp_aux_msg | |
214 | * structure, which is passed into a driver's .transfer() implementation. | |
215 | * Both native and I2C-over-AUX transactions are supported. | |
c197db75 TR |
216 | */ |
217 | ||
218 | static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, | |
219 | unsigned int offset, void *buffer, size_t size) | |
220 | { | |
221 | struct drm_dp_aux_msg msg; | |
82922da3 L |
222 | unsigned int retry, native_reply; |
223 | int err = 0, ret = 0; | |
c197db75 TR |
224 | |
225 | memset(&msg, 0, sizeof(msg)); | |
226 | msg.address = offset; | |
227 | msg.request = request; | |
228 | msg.buffer = buffer; | |
229 | msg.size = size; | |
230 | ||
7779c5e2 RC |
231 | mutex_lock(&aux->hw_mutex); |
232 | ||
c197db75 TR |
233 | /* |
234 | * The specification doesn't give any recommendation on how often to | |
19a93f04 DA |
235 | * retry native transactions. We used to retry 7 times like for |
236 | * aux i2c transactions but real world devices this wasn't | |
237 | * sufficient, bump to 32 which makes Dell 4k monitors happier. | |
c197db75 | 238 | */ |
19a93f04 | 239 | for (retry = 0; retry < 32; retry++) { |
82922da3 | 240 | if (ret != 0 && ret != -ETIMEDOUT) { |
e1083ff3 L |
241 | usleep_range(AUX_RETRY_INTERVAL, |
242 | AUX_RETRY_INTERVAL + 100); | |
243 | } | |
4f71d0cb | 244 | |
82922da3 | 245 | ret = aux->transfer(aux, &msg); |
c197db75 | 246 | |
a1f5524a | 247 | if (ret >= 0) { |
82922da3 L |
248 | native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; |
249 | if (native_reply == DP_AUX_NATIVE_REPLY_ACK) { | |
250 | if (ret == size) | |
251 | goto unlock; | |
c197db75 | 252 | |
82922da3 L |
253 | ret = -EPROTO; |
254 | } else | |
255 | ret = -EIO; | |
c197db75 | 256 | } |
82922da3 L |
257 | |
258 | /* | |
259 | * We want the error we return to be the error we received on | |
260 | * the first transaction, since we may get a different error the | |
261 | * next time we retry | |
262 | */ | |
263 | if (!err) | |
264 | err = ret; | |
c197db75 TR |
265 | } |
266 | ||
29f21e04 | 267 | DRM_DEBUG_KMS("Too many retries, giving up. First error: %d\n", err); |
82922da3 | 268 | ret = err; |
7779c5e2 RC |
269 | |
270 | unlock: | |
271 | mutex_unlock(&aux->hw_mutex); | |
82922da3 | 272 | return ret; |
c197db75 TR |
273 | } |
274 | ||
275 | /** | |
276 | * drm_dp_dpcd_read() - read a series of bytes from the DPCD | |
277 | * @aux: DisplayPort AUX channel | |
278 | * @offset: address of the (first) register to read | |
279 | * @buffer: buffer to store the register values | |
280 | * @size: number of bytes in @buffer | |
281 | * | |
282 | * Returns the number of bytes transferred on success, or a negative error | |
283 | * code on failure. -EIO is returned if the request was NAKed by the sink or | |
284 | * if the retry count was exceeded. If not all bytes were transferred, this | |
285 | * function returns -EPROTO. Errors from the underlying AUX channel transfer | |
286 | * function, with the exception of -EBUSY (which causes the transaction to | |
287 | * be retried), are propagated to the caller. | |
288 | */ | |
289 | ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, | |
290 | void *buffer, size_t size) | |
291 | { | |
f808f633 L |
292 | int ret; |
293 | ||
294 | /* | |
295 | * HP ZR24w corrupts the first DPCD access after entering power save | |
296 | * mode. Eg. on a read, the entire buffer will be filled with the same | |
297 | * byte. Do a throw away read to avoid corrupting anything we care | |
298 | * about. Afterwards things will work correctly until the monitor | |
299 | * gets woken up and subsequently re-enters power save mode. | |
300 | * | |
301 | * The user pressing any button on the monitor is enough to wake it | |
302 | * up, so there is no particularly good place to do the workaround. | |
303 | * We just have to do it before any DPCD access and hope that the | |
304 | * monitor doesn't power down exactly after the throw away read. | |
305 | */ | |
306 | ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV, buffer, | |
307 | 1); | |
308 | if (ret != 1) | |
a18b2192 | 309 | goto out; |
f808f633 | 310 | |
a18b2192 LP |
311 | ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer, |
312 | size); | |
313 | ||
314 | out: | |
315 | drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret); | |
316 | return ret; | |
c197db75 TR |
317 | } |
318 | EXPORT_SYMBOL(drm_dp_dpcd_read); | |
319 | ||
320 | /** | |
321 | * drm_dp_dpcd_write() - write a series of bytes to the DPCD | |
322 | * @aux: DisplayPort AUX channel | |
323 | * @offset: address of the (first) register to write | |
324 | * @buffer: buffer containing the values to write | |
325 | * @size: number of bytes in @buffer | |
326 | * | |
327 | * Returns the number of bytes transferred on success, or a negative error | |
328 | * code on failure. -EIO is returned if the request was NAKed by the sink or | |
329 | * if the retry count was exceeded. If not all bytes were transferred, this | |
330 | * function returns -EPROTO. Errors from the underlying AUX channel transfer | |
331 | * function, with the exception of -EBUSY (which causes the transaction to | |
332 | * be retried), are propagated to the caller. | |
333 | */ | |
334 | ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, | |
335 | void *buffer, size_t size) | |
336 | { | |
a18b2192 LP |
337 | int ret; |
338 | ||
339 | ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, | |
340 | size); | |
341 | drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret); | |
342 | return ret; | |
c197db75 TR |
343 | } |
344 | EXPORT_SYMBOL(drm_dp_dpcd_write); | |
8d4adc6a TR |
345 | |
346 | /** | |
347 | * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207) | |
348 | * @aux: DisplayPort AUX channel | |
349 | * @status: buffer to store the link status in (must be at least 6 bytes) | |
350 | * | |
351 | * Returns the number of bytes transferred on success or a negative error | |
352 | * code on failure. | |
353 | */ | |
354 | int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, | |
355 | u8 status[DP_LINK_STATUS_SIZE]) | |
356 | { | |
357 | return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, | |
358 | DP_LINK_STATUS_SIZE); | |
359 | } | |
360 | EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); | |
516c0f7c TR |
361 | |
362 | /** | |
363 | * drm_dp_link_probe() - probe a DisplayPort link for capabilities | |
364 | * @aux: DisplayPort AUX channel | |
365 | * @link: pointer to structure in which to return link capabilities | |
366 | * | |
367 | * The structure filled in by this function can usually be passed directly | |
368 | * into drm_dp_link_power_up() and drm_dp_link_configure() to power up and | |
369 | * configure the link based on the link's capabilities. | |
370 | * | |
371 | * Returns 0 on success or a negative error code on failure. | |
372 | */ | |
373 | int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link) | |
374 | { | |
375 | u8 values[3]; | |
376 | int err; | |
377 | ||
378 | memset(link, 0, sizeof(*link)); | |
379 | ||
380 | err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values)); | |
381 | if (err < 0) | |
382 | return err; | |
383 | ||
384 | link->revision = values[0]; | |
385 | link->rate = drm_dp_bw_code_to_link_rate(values[1]); | |
386 | link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK; | |
387 | ||
388 | if (values[2] & DP_ENHANCED_FRAME_CAP) | |
389 | link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING; | |
390 | ||
391 | return 0; | |
392 | } | |
393 | EXPORT_SYMBOL(drm_dp_link_probe); | |
394 | ||
395 | /** | |
396 | * drm_dp_link_power_up() - power up a DisplayPort link | |
397 | * @aux: DisplayPort AUX channel | |
398 | * @link: pointer to a structure containing the link configuration | |
399 | * | |
400 | * Returns 0 on success or a negative error code on failure. | |
401 | */ | |
402 | int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link) | |
403 | { | |
404 | u8 value; | |
405 | int err; | |
406 | ||
407 | /* DP_SET_POWER register is only available on DPCD v1.1 and later */ | |
408 | if (link->revision < 0x11) | |
409 | return 0; | |
410 | ||
411 | err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value); | |
412 | if (err < 0) | |
413 | return err; | |
414 | ||
415 | value &= ~DP_SET_POWER_MASK; | |
416 | value |= DP_SET_POWER_D0; | |
417 | ||
418 | err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value); | |
419 | if (err < 0) | |
420 | return err; | |
421 | ||
422 | /* | |
423 | * According to the DP 1.1 specification, a "Sink Device must exit the | |
424 | * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink | |
425 | * Control Field" (register 0x600). | |
426 | */ | |
427 | usleep_range(1000, 2000); | |
428 | ||
429 | return 0; | |
430 | } | |
431 | EXPORT_SYMBOL(drm_dp_link_power_up); | |
432 | ||
d816f077 RC |
433 | /** |
434 | * drm_dp_link_power_down() - power down a DisplayPort link | |
435 | * @aux: DisplayPort AUX channel | |
436 | * @link: pointer to a structure containing the link configuration | |
437 | * | |
438 | * Returns 0 on success or a negative error code on failure. | |
439 | */ | |
440 | int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link) | |
441 | { | |
442 | u8 value; | |
443 | int err; | |
444 | ||
445 | /* DP_SET_POWER register is only available on DPCD v1.1 and later */ | |
446 | if (link->revision < 0x11) | |
447 | return 0; | |
448 | ||
449 | err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value); | |
450 | if (err < 0) | |
451 | return err; | |
452 | ||
453 | value &= ~DP_SET_POWER_MASK; | |
454 | value |= DP_SET_POWER_D3; | |
455 | ||
456 | err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value); | |
457 | if (err < 0) | |
458 | return err; | |
459 | ||
460 | return 0; | |
461 | } | |
462 | EXPORT_SYMBOL(drm_dp_link_power_down); | |
463 | ||
516c0f7c TR |
464 | /** |
465 | * drm_dp_link_configure() - configure a DisplayPort link | |
466 | * @aux: DisplayPort AUX channel | |
467 | * @link: pointer to a structure containing the link configuration | |
468 | * | |
469 | * Returns 0 on success or a negative error code on failure. | |
470 | */ | |
471 | int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link) | |
472 | { | |
473 | u8 values[2]; | |
474 | int err; | |
475 | ||
476 | values[0] = drm_dp_link_rate_to_bw_code(link->rate); | |
477 | values[1] = link->num_lanes; | |
478 | ||
479 | if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) | |
480 | values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; | |
481 | ||
482 | err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values)); | |
483 | if (err < 0) | |
484 | return err; | |
485 | ||
486 | return 0; | |
487 | } | |
488 | EXPORT_SYMBOL(drm_dp_link_configure); | |
88759686 | 489 | |
1c29bd3d MK |
490 | /** |
491 | * drm_dp_downstream_max_clock() - extract branch device max | |
492 | * pixel rate for legacy VGA | |
493 | * converter or max TMDS clock | |
494 | * rate for others | |
495 | * @dpcd: DisplayPort configuration data | |
496 | * @port_cap: port capabilities | |
497 | * | |
498 | * Returns max clock in kHz on success or 0 if max clock not defined | |
499 | */ | |
500 | int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], | |
501 | const u8 port_cap[4]) | |
502 | { | |
503 | int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; | |
504 | bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
505 | DP_DETAILED_CAP_INFO_AVAILABLE; | |
506 | ||
507 | if (!detailed_cap_info) | |
508 | return 0; | |
509 | ||
510 | switch (type) { | |
511 | case DP_DS_PORT_TYPE_VGA: | |
512 | return port_cap[1] * 8 * 1000; | |
513 | case DP_DS_PORT_TYPE_DVI: | |
514 | case DP_DS_PORT_TYPE_HDMI: | |
515 | case DP_DS_PORT_TYPE_DP_DUALMODE: | |
516 | return port_cap[1] * 2500; | |
517 | default: | |
518 | return 0; | |
519 | } | |
520 | } | |
521 | EXPORT_SYMBOL(drm_dp_downstream_max_clock); | |
522 | ||
7529d6af MK |
523 | /** |
524 | * drm_dp_downstream_max_bpc() - extract branch device max | |
525 | * bits per component | |
526 | * @dpcd: DisplayPort configuration data | |
527 | * @port_cap: port capabilities | |
528 | * | |
529 | * Returns max bpc on success or 0 if max bpc not defined | |
530 | */ | |
531 | int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], | |
532 | const u8 port_cap[4]) | |
533 | { | |
534 | int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; | |
535 | bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
536 | DP_DETAILED_CAP_INFO_AVAILABLE; | |
537 | int bpc; | |
538 | ||
539 | if (!detailed_cap_info) | |
540 | return 0; | |
541 | ||
542 | switch (type) { | |
543 | case DP_DS_PORT_TYPE_VGA: | |
544 | case DP_DS_PORT_TYPE_DVI: | |
545 | case DP_DS_PORT_TYPE_HDMI: | |
546 | case DP_DS_PORT_TYPE_DP_DUALMODE: | |
547 | bpc = port_cap[2] & DP_DS_MAX_BPC_MASK; | |
548 | ||
549 | switch (bpc) { | |
550 | case DP_DS_8BPC: | |
551 | return 8; | |
552 | case DP_DS_10BPC: | |
553 | return 10; | |
554 | case DP_DS_12BPC: | |
555 | return 12; | |
556 | case DP_DS_16BPC: | |
557 | return 16; | |
558 | } | |
e9c0c874 | 559 | /* fall through */ |
7529d6af MK |
560 | default: |
561 | return 0; | |
562 | } | |
563 | } | |
564 | EXPORT_SYMBOL(drm_dp_downstream_max_bpc); | |
565 | ||
266d783b MK |
566 | /** |
567 | * drm_dp_downstream_id() - identify branch device | |
568 | * @aux: DisplayPort AUX channel | |
3442d9ee | 569 | * @id: DisplayPort branch device id |
266d783b MK |
570 | * |
571 | * Returns branch device id on success or NULL on failure | |
572 | */ | |
573 | int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]) | |
574 | { | |
575 | return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6); | |
576 | } | |
577 | EXPORT_SYMBOL(drm_dp_downstream_id); | |
578 | ||
80209e5f MK |
579 | /** |
580 | * drm_dp_downstream_debug() - debug DP branch devices | |
581 | * @m: pointer for debugfs file | |
582 | * @dpcd: DisplayPort configuration data | |
583 | * @port_cap: port capabilities | |
584 | * @aux: DisplayPort AUX channel | |
585 | * | |
586 | */ | |
587 | void drm_dp_downstream_debug(struct seq_file *m, | |
588 | const u8 dpcd[DP_RECEIVER_CAP_SIZE], | |
589 | const u8 port_cap[4], struct drm_dp_aux *aux) | |
590 | { | |
591 | bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
592 | DP_DETAILED_CAP_INFO_AVAILABLE; | |
593 | int clk; | |
594 | int bpc; | |
967003bb | 595 | char id[7]; |
80209e5f MK |
596 | int len; |
597 | uint8_t rev[2]; | |
598 | int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; | |
599 | bool branch_device = dpcd[DP_DOWNSTREAMPORT_PRESENT] & | |
600 | DP_DWN_STRM_PORT_PRESENT; | |
601 | ||
602 | seq_printf(m, "\tDP branch device present: %s\n", | |
603 | branch_device ? "yes" : "no"); | |
604 | ||
605 | if (!branch_device) | |
606 | return; | |
607 | ||
608 | switch (type) { | |
609 | case DP_DS_PORT_TYPE_DP: | |
610 | seq_puts(m, "\t\tType: DisplayPort\n"); | |
611 | break; | |
612 | case DP_DS_PORT_TYPE_VGA: | |
613 | seq_puts(m, "\t\tType: VGA\n"); | |
614 | break; | |
615 | case DP_DS_PORT_TYPE_DVI: | |
616 | seq_puts(m, "\t\tType: DVI\n"); | |
617 | break; | |
618 | case DP_DS_PORT_TYPE_HDMI: | |
619 | seq_puts(m, "\t\tType: HDMI\n"); | |
620 | break; | |
621 | case DP_DS_PORT_TYPE_NON_EDID: | |
622 | seq_puts(m, "\t\tType: others without EDID support\n"); | |
623 | break; | |
624 | case DP_DS_PORT_TYPE_DP_DUALMODE: | |
625 | seq_puts(m, "\t\tType: DP++\n"); | |
626 | break; | |
627 | case DP_DS_PORT_TYPE_WIRELESS: | |
628 | seq_puts(m, "\t\tType: Wireless\n"); | |
629 | break; | |
630 | default: | |
631 | seq_puts(m, "\t\tType: N/A\n"); | |
632 | } | |
633 | ||
967003bb | 634 | memset(id, 0, sizeof(id)); |
80209e5f MK |
635 | drm_dp_downstream_id(aux, id); |
636 | seq_printf(m, "\t\tID: %s\n", id); | |
637 | ||
638 | len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1); | |
639 | if (len > 0) | |
640 | seq_printf(m, "\t\tHW: %d.%d\n", | |
641 | (rev[0] & 0xf0) >> 4, rev[0] & 0xf); | |
642 | ||
c11a93f5 | 643 | len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2); |
80209e5f MK |
644 | if (len > 0) |
645 | seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]); | |
646 | ||
647 | if (detailed_cap_info) { | |
648 | clk = drm_dp_downstream_max_clock(dpcd, port_cap); | |
649 | ||
650 | if (clk > 0) { | |
651 | if (type == DP_DS_PORT_TYPE_VGA) | |
652 | seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk); | |
653 | else | |
654 | seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk); | |
655 | } | |
656 | ||
657 | bpc = drm_dp_downstream_max_bpc(dpcd, port_cap); | |
658 | ||
659 | if (bpc > 0) | |
660 | seq_printf(m, "\t\tMax bpc: %d\n", bpc); | |
661 | } | |
662 | } | |
663 | EXPORT_SYMBOL(drm_dp_downstream_debug); | |
664 | ||
88759686 TR |
665 | /* |
666 | * I2C-over-AUX implementation | |
667 | */ | |
668 | ||
669 | static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter) | |
670 | { | |
671 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | | |
672 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | | |
673 | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | | |
674 | I2C_FUNC_10BIT_ADDR; | |
675 | } | |
676 | ||
68ec2a2a VS |
677 | static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg) |
678 | { | |
679 | /* | |
680 | * In case of i2c defer or short i2c ack reply to a write, | |
681 | * we need to switch to WRITE_STATUS_UPDATE to drain the | |
682 | * rest of the message | |
683 | */ | |
684 | if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { | |
685 | msg->request &= DP_AUX_I2C_MOT; | |
686 | msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; | |
687 | } | |
688 | } | |
689 | ||
4efa83c8 VS |
690 | #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */ |
691 | #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */ | |
692 | #define AUX_STOP_LEN 4 | |
693 | #define AUX_CMD_LEN 4 | |
694 | #define AUX_ADDRESS_LEN 20 | |
695 | #define AUX_REPLY_PAD_LEN 4 | |
696 | #define AUX_LENGTH_LEN 8 | |
697 | ||
698 | /* | |
699 | * Calculate the duration of the AUX request/reply in usec. Gives the | |
700 | * "best" case estimate, ie. successful while as short as possible. | |
701 | */ | |
702 | static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg) | |
703 | { | |
704 | int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + | |
705 | AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN; | |
706 | ||
707 | if ((msg->request & DP_AUX_I2C_READ) == 0) | |
708 | len += msg->size * 8; | |
709 | ||
710 | return len; | |
711 | } | |
712 | ||
713 | static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg) | |
714 | { | |
715 | int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + | |
716 | AUX_CMD_LEN + AUX_REPLY_PAD_LEN; | |
717 | ||
718 | /* | |
719 | * For read we expect what was asked. For writes there will | |
720 | * be 0 or 1 data bytes. Assume 0 for the "best" case. | |
721 | */ | |
722 | if (msg->request & DP_AUX_I2C_READ) | |
723 | len += msg->size * 8; | |
724 | ||
725 | return len; | |
726 | } | |
727 | ||
728 | #define I2C_START_LEN 1 | |
729 | #define I2C_STOP_LEN 1 | |
730 | #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */ | |
731 | #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */ | |
732 | ||
733 | /* | |
734 | * Calculate the length of the i2c transfer in usec, assuming | |
735 | * the i2c bus speed is as specified. Gives the the "worst" | |
736 | * case estimate, ie. successful while as long as possible. | |
737 | * Doesn't account the the "MOT" bit, and instead assumes each | |
738 | * message includes a START, ADDRESS and STOP. Neither does it | |
739 | * account for additional random variables such as clock stretching. | |
740 | */ | |
741 | static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg, | |
742 | int i2c_speed_khz) | |
743 | { | |
744 | /* AUX bitrate is 1MHz, i2c bitrate as specified */ | |
745 | return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN + | |
746 | msg->size * I2C_DATA_LEN + | |
747 | I2C_STOP_LEN) * 1000, i2c_speed_khz); | |
748 | } | |
749 | ||
750 | /* | |
751 | * Deterine how many retries should be attempted to successfully transfer | |
752 | * the specified message, based on the estimated durations of the | |
753 | * i2c and AUX transfers. | |
754 | */ | |
755 | static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg, | |
756 | int i2c_speed_khz) | |
757 | { | |
758 | int aux_time_us = drm_dp_aux_req_duration(msg) + | |
759 | drm_dp_aux_reply_duration(msg); | |
760 | int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz); | |
761 | ||
762 | return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL); | |
763 | } | |
764 | ||
f36203be VS |
765 | /* |
766 | * FIXME currently assumes 10 kHz as some real world devices seem | |
767 | * to require it. We should query/set the speed via DPCD if supported. | |
768 | */ | |
769 | static int dp_aux_i2c_speed_khz __read_mostly = 10; | |
770 | module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644); | |
771 | MODULE_PARM_DESC(dp_aux_i2c_speed_khz, | |
772 | "Assumed speed of the i2c bus in kHz, (1-400, default 10)"); | |
773 | ||
88759686 TR |
774 | /* |
775 | * Transfer a single I2C-over-AUX message and handle various error conditions, | |
732d50b4 | 776 | * retrying the transaction as appropriate. It is assumed that the |
6806cdf9 | 777 | * &drm_dp_aux.transfer function does not modify anything in the msg other than the |
732d50b4 | 778 | * reply field. |
1d002fa7 SF |
779 | * |
780 | * Returns bytes transferred on success, or a negative error code on failure. | |
88759686 TR |
781 | */ |
782 | static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) | |
783 | { | |
396aa445 | 784 | unsigned int retry, defer_i2c; |
1d002fa7 | 785 | int ret; |
88759686 TR |
786 | /* |
787 | * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device | |
788 | * is required to retry at least seven times upon receiving AUX_DEFER | |
789 | * before giving up the AUX transaction. | |
4efa83c8 VS |
790 | * |
791 | * We also try to account for the i2c bus speed. | |
88759686 | 792 | */ |
f36203be | 793 | int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz)); |
4efa83c8 VS |
794 | |
795 | for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) { | |
1d002fa7 | 796 | ret = aux->transfer(aux, msg); |
1d002fa7 SF |
797 | if (ret < 0) { |
798 | if (ret == -EBUSY) | |
88759686 TR |
799 | continue; |
800 | ||
9622c38f L |
801 | /* |
802 | * While timeouts can be errors, they're usually normal | |
803 | * behavior (for instance, when a driver tries to | |
804 | * communicate with a non-existant DisplayPort device). | |
805 | * Avoid spamming the kernel log with timeout errors. | |
806 | */ | |
807 | if (ret == -ETIMEDOUT) | |
808 | DRM_DEBUG_KMS_RATELIMITED("transaction timed out\n"); | |
809 | else | |
810 | DRM_DEBUG_KMS("transaction failed: %d\n", ret); | |
811 | ||
1d002fa7 | 812 | return ret; |
88759686 TR |
813 | } |
814 | ||
88759686 TR |
815 | |
816 | switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { | |
817 | case DP_AUX_NATIVE_REPLY_ACK: | |
818 | /* | |
819 | * For I2C-over-AUX transactions this isn't enough, we | |
820 | * need to check for the I2C ACK reply. | |
821 | */ | |
822 | break; | |
823 | ||
824 | case DP_AUX_NATIVE_REPLY_NACK: | |
fb8c5e49 | 825 | DRM_DEBUG_KMS("native nack (result=%d, size=%zu)\n", ret, msg->size); |
88759686 TR |
826 | return -EREMOTEIO; |
827 | ||
828 | case DP_AUX_NATIVE_REPLY_DEFER: | |
747552b9 | 829 | DRM_DEBUG_KMS("native defer\n"); |
88759686 TR |
830 | /* |
831 | * We could check for I2C bit rate capabilities and if | |
832 | * available adjust this interval. We could also be | |
833 | * more careful with DP-to-legacy adapters where a | |
834 | * long legacy cable may force very low I2C bit rates. | |
835 | * | |
836 | * For now just defer for long enough to hopefully be | |
837 | * safe for all use-cases. | |
838 | */ | |
79a2b161 | 839 | usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); |
88759686 TR |
840 | continue; |
841 | ||
842 | default: | |
843 | DRM_ERROR("invalid native reply %#04x\n", msg->reply); | |
844 | return -EREMOTEIO; | |
845 | } | |
846 | ||
847 | switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { | |
848 | case DP_AUX_I2C_REPLY_ACK: | |
849 | /* | |
850 | * Both native ACK and I2C ACK replies received. We | |
851 | * can assume the transfer was successful. | |
852 | */ | |
68ec2a2a VS |
853 | if (ret != msg->size) |
854 | drm_dp_i2c_msg_write_status_update(msg); | |
1d002fa7 | 855 | return ret; |
88759686 TR |
856 | |
857 | case DP_AUX_I2C_REPLY_NACK: | |
22e6de70 PZ |
858 | DRM_DEBUG_KMS("I2C nack (result=%d, size=%zu)\n", |
859 | ret, msg->size); | |
e9cf6194 | 860 | aux->i2c_nack_count++; |
88759686 TR |
861 | return -EREMOTEIO; |
862 | ||
863 | case DP_AUX_I2C_REPLY_DEFER: | |
864 | DRM_DEBUG_KMS("I2C defer\n"); | |
396aa445 TP |
865 | /* DP Compliance Test 4.2.2.5 Requirement: |
866 | * Must have at least 7 retries for I2C defers on the | |
867 | * transaction to pass this test | |
868 | */ | |
e9cf6194 | 869 | aux->i2c_defer_count++; |
396aa445 TP |
870 | if (defer_i2c < 7) |
871 | defer_i2c++; | |
79a2b161 | 872 | usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); |
68ec2a2a | 873 | drm_dp_i2c_msg_write_status_update(msg); |
646db260 | 874 | |
88759686 TR |
875 | continue; |
876 | ||
877 | default: | |
878 | DRM_ERROR("invalid I2C reply %#04x\n", msg->reply); | |
879 | return -EREMOTEIO; | |
880 | } | |
881 | } | |
882 | ||
743b1e32 | 883 | DRM_DEBUG_KMS("too many retries, giving up\n"); |
88759686 TR |
884 | return -EREMOTEIO; |
885 | } | |
886 | ||
68ec2a2a VS |
887 | static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg, |
888 | const struct i2c_msg *i2c_msg) | |
889 | { | |
890 | msg->request = (i2c_msg->flags & I2C_M_RD) ? | |
891 | DP_AUX_I2C_READ : DP_AUX_I2C_WRITE; | |
da279eb9 VS |
892 | if (!(i2c_msg->flags & I2C_M_STOP)) |
893 | msg->request |= DP_AUX_I2C_MOT; | |
68ec2a2a VS |
894 | } |
895 | ||
1d002fa7 SF |
896 | /* |
897 | * Keep retrying drm_dp_i2c_do_msg until all data has been transferred. | |
898 | * | |
899 | * Returns an error code on failure, or a recommended transfer size on success. | |
900 | */ | |
901 | static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg) | |
902 | { | |
903 | int err, ret = orig_msg->size; | |
904 | struct drm_dp_aux_msg msg = *orig_msg; | |
905 | ||
906 | while (msg.size > 0) { | |
907 | err = drm_dp_i2c_do_msg(aux, &msg); | |
908 | if (err <= 0) | |
909 | return err == 0 ? -EPROTO : err; | |
910 | ||
911 | if (err < msg.size && err < ret) { | |
912 | DRM_DEBUG_KMS("Partial I2C reply: requested %zu bytes got %d bytes\n", | |
913 | msg.size, err); | |
914 | ret = err; | |
915 | } | |
916 | ||
917 | msg.size -= err; | |
918 | msg.buffer += err; | |
919 | } | |
920 | ||
921 | return ret; | |
922 | } | |
923 | ||
924 | /* | |
925 | * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX | |
926 | * packets to be as large as possible. If not, the I2C transactions never | |
927 | * succeed. Hence the default is maximum. | |
928 | */ | |
929 | static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES; | |
930 | module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644); | |
931 | MODULE_PARM_DESC(dp_aux_i2c_transfer_size, | |
932 | "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)"); | |
933 | ||
88759686 TR |
934 | static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, |
935 | int num) | |
936 | { | |
937 | struct drm_dp_aux *aux = adapter->algo_data; | |
938 | unsigned int i, j; | |
1d002fa7 | 939 | unsigned transfer_size; |
ccdb516e AD |
940 | struct drm_dp_aux_msg msg; |
941 | int err = 0; | |
88759686 | 942 | |
1d002fa7 SF |
943 | dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES); |
944 | ||
ccdb516e | 945 | memset(&msg, 0, sizeof(msg)); |
88759686 | 946 | |
ccdb516e AD |
947 | for (i = 0; i < num; i++) { |
948 | msg.address = msgs[i].addr; | |
68ec2a2a | 949 | drm_dp_i2c_msg_set_request(&msg, &msgs[i]); |
ccdb516e AD |
950 | /* Send a bare address packet to start the transaction. |
951 | * Zero sized messages specify an address only (bare | |
952 | * address) transaction. | |
953 | */ | |
954 | msg.buffer = NULL; | |
955 | msg.size = 0; | |
956 | err = drm_dp_i2c_do_msg(aux, &msg); | |
68ec2a2a VS |
957 | |
958 | /* | |
959 | * Reset msg.request in case in case it got | |
960 | * changed into a WRITE_STATUS_UPDATE. | |
961 | */ | |
962 | drm_dp_i2c_msg_set_request(&msg, &msgs[i]); | |
963 | ||
ccdb516e AD |
964 | if (err < 0) |
965 | break; | |
1d002fa7 SF |
966 | /* We want each transaction to be as large as possible, but |
967 | * we'll go to smaller sizes if the hardware gives us a | |
968 | * short reply. | |
88759686 | 969 | */ |
1d002fa7 SF |
970 | transfer_size = dp_aux_i2c_transfer_size; |
971 | for (j = 0; j < msgs[i].len; j += msg.size) { | |
88759686 | 972 | msg.buffer = msgs[i].buf + j; |
1d002fa7 | 973 | msg.size = min(transfer_size, msgs[i].len - j); |
88759686 | 974 | |
1d002fa7 | 975 | err = drm_dp_i2c_drain_msg(aux, &msg); |
68ec2a2a VS |
976 | |
977 | /* | |
978 | * Reset msg.request in case in case it got | |
979 | * changed into a WRITE_STATUS_UPDATE. | |
980 | */ | |
981 | drm_dp_i2c_msg_set_request(&msg, &msgs[i]); | |
982 | ||
88759686 | 983 | if (err < 0) |
ccdb516e | 984 | break; |
1d002fa7 | 985 | transfer_size = err; |
88759686 | 986 | } |
ccdb516e AD |
987 | if (err < 0) |
988 | break; | |
88759686 | 989 | } |
ccdb516e AD |
990 | if (err >= 0) |
991 | err = num; | |
992 | /* Send a bare address packet to close out the transaction. | |
993 | * Zero sized messages specify an address only (bare | |
994 | * address) transaction. | |
995 | */ | |
996 | msg.request &= ~DP_AUX_I2C_MOT; | |
997 | msg.buffer = NULL; | |
998 | msg.size = 0; | |
999 | (void)drm_dp_i2c_do_msg(aux, &msg); | |
88759686 | 1000 | |
ccdb516e | 1001 | return err; |
88759686 TR |
1002 | } |
1003 | ||
1004 | static const struct i2c_algorithm drm_dp_i2c_algo = { | |
1005 | .functionality = drm_dp_i2c_functionality, | |
1006 | .master_xfer = drm_dp_i2c_xfer, | |
1007 | }; | |
1008 | ||
0c2f6f1a CW |
1009 | static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c) |
1010 | { | |
1011 | return container_of(i2c, struct drm_dp_aux, ddc); | |
1012 | } | |
1013 | ||
1014 | static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) | |
1015 | { | |
1016 | mutex_lock(&i2c_to_aux(i2c)->hw_mutex); | |
1017 | } | |
1018 | ||
1019 | static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) | |
1020 | { | |
1021 | return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex); | |
1022 | } | |
1023 | ||
1024 | static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) | |
1025 | { | |
1026 | mutex_unlock(&i2c_to_aux(i2c)->hw_mutex); | |
1027 | } | |
1028 | ||
d1ed7985 PR |
1029 | static const struct i2c_lock_operations drm_dp_i2c_lock_ops = { |
1030 | .lock_bus = lock_bus, | |
1031 | .trylock_bus = trylock_bus, | |
1032 | .unlock_bus = unlock_bus, | |
1033 | }; | |
1034 | ||
79c1da7c TV |
1035 | static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc) |
1036 | { | |
1037 | u8 buf, count; | |
1038 | int ret; | |
1039 | ||
1040 | ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); | |
1041 | if (ret < 0) | |
1042 | return ret; | |
1043 | ||
1044 | WARN_ON(!(buf & DP_TEST_SINK_START)); | |
1045 | ||
1046 | ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf); | |
1047 | if (ret < 0) | |
1048 | return ret; | |
1049 | ||
1050 | count = buf & DP_TEST_COUNT_MASK; | |
1051 | if (count == aux->crc_count) | |
1052 | return -EAGAIN; /* No CRC yet */ | |
1053 | ||
1054 | aux->crc_count = count; | |
1055 | ||
1056 | /* | |
1057 | * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes | |
1058 | * per component (RGB or CrYCb). | |
1059 | */ | |
1060 | ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6); | |
1061 | if (ret < 0) | |
1062 | return ret; | |
1063 | ||
1064 | return 0; | |
1065 | } | |
1066 | ||
1067 | static void drm_dp_aux_crc_work(struct work_struct *work) | |
1068 | { | |
1069 | struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux, | |
1070 | crc_work); | |
1071 | struct drm_crtc *crtc; | |
1072 | u8 crc_bytes[6]; | |
1073 | uint32_t crcs[3]; | |
1074 | int ret; | |
1075 | ||
1076 | if (WARN_ON(!aux->crtc)) | |
1077 | return; | |
1078 | ||
1079 | crtc = aux->crtc; | |
1080 | while (crtc->crc.opened) { | |
1081 | drm_crtc_wait_one_vblank(crtc); | |
1082 | if (!crtc->crc.opened) | |
1083 | break; | |
1084 | ||
1085 | ret = drm_dp_aux_get_crc(aux, crc_bytes); | |
1086 | if (ret == -EAGAIN) { | |
1087 | usleep_range(1000, 2000); | |
1088 | ret = drm_dp_aux_get_crc(aux, crc_bytes); | |
1089 | } | |
1090 | ||
1091 | if (ret == -EAGAIN) { | |
1092 | DRM_DEBUG_KMS("Get CRC failed after retrying: %d\n", | |
1093 | ret); | |
1094 | continue; | |
1095 | } else if (ret) { | |
1096 | DRM_DEBUG_KMS("Failed to get a CRC: %d\n", ret); | |
1097 | continue; | |
1098 | } | |
1099 | ||
1100 | crcs[0] = crc_bytes[0] | crc_bytes[1] << 8; | |
1101 | crcs[1] = crc_bytes[2] | crc_bytes[3] << 8; | |
1102 | crcs[2] = crc_bytes[4] | crc_bytes[5] << 8; | |
1103 | drm_crtc_add_crc_entry(crtc, false, 0, crcs); | |
1104 | } | |
1105 | } | |
1106 | ||
88759686 | 1107 | /** |
acd8f414 | 1108 | * drm_dp_aux_init() - minimally initialise an aux channel |
88759686 TR |
1109 | * @aux: DisplayPort AUX channel |
1110 | * | |
acd8f414 CW |
1111 | * If you need to use the drm_dp_aux's i2c adapter prior to registering it |
1112 | * with the outside world, call drm_dp_aux_init() first. You must still | |
1113 | * call drm_dp_aux_register() once the connector has been registered to | |
1114 | * allow userspace access to the auxiliary DP channel. | |
88759686 | 1115 | */ |
acd8f414 | 1116 | void drm_dp_aux_init(struct drm_dp_aux *aux) |
88759686 | 1117 | { |
4f71d0cb | 1118 | mutex_init(&aux->hw_mutex); |
2c6d1fff | 1119 | mutex_init(&aux->cec.lock); |
79c1da7c | 1120 | INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); |
4f71d0cb | 1121 | |
88759686 TR |
1122 | aux->ddc.algo = &drm_dp_i2c_algo; |
1123 | aux->ddc.algo_data = aux; | |
1124 | aux->ddc.retries = 3; | |
1125 | ||
d1ed7985 | 1126 | aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; |
acd8f414 CW |
1127 | } |
1128 | EXPORT_SYMBOL(drm_dp_aux_init); | |
1129 | ||
1130 | /** | |
1131 | * drm_dp_aux_register() - initialise and register aux channel | |
1132 | * @aux: DisplayPort AUX channel | |
1133 | * | |
1134 | * Automatically calls drm_dp_aux_init() if this hasn't been done yet. | |
1135 | * | |
1136 | * Returns 0 on success or a negative error code on failure. | |
1137 | */ | |
1138 | int drm_dp_aux_register(struct drm_dp_aux *aux) | |
1139 | { | |
1140 | int ret; | |
1141 | ||
1142 | if (!aux->ddc.algo) | |
1143 | drm_dp_aux_init(aux); | |
0c2f6f1a | 1144 | |
88759686 TR |
1145 | aux->ddc.class = I2C_CLASS_DDC; |
1146 | aux->ddc.owner = THIS_MODULE; | |
1147 | aux->ddc.dev.parent = aux->dev; | |
88759686 | 1148 | |
9dc40560 JN |
1149 | strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), |
1150 | sizeof(aux->ddc.name)); | |
88759686 | 1151 | |
e94cb37b RA |
1152 | ret = drm_dp_aux_register_devnode(aux); |
1153 | if (ret) | |
1154 | return ret; | |
1155 | ||
1156 | ret = i2c_add_adapter(&aux->ddc); | |
1157 | if (ret) { | |
1158 | drm_dp_aux_unregister_devnode(aux); | |
1159 | return ret; | |
1160 | } | |
1161 | ||
1162 | return 0; | |
88759686 | 1163 | } |
4f71d0cb | 1164 | EXPORT_SYMBOL(drm_dp_aux_register); |
88759686 TR |
1165 | |
1166 | /** | |
4f71d0cb | 1167 | * drm_dp_aux_unregister() - unregister an AUX adapter |
88759686 TR |
1168 | * @aux: DisplayPort AUX channel |
1169 | */ | |
4f71d0cb | 1170 | void drm_dp_aux_unregister(struct drm_dp_aux *aux) |
88759686 | 1171 | { |
e94cb37b | 1172 | drm_dp_aux_unregister_devnode(aux); |
88759686 TR |
1173 | i2c_del_adapter(&aux->ddc); |
1174 | } | |
4f71d0cb | 1175 | EXPORT_SYMBOL(drm_dp_aux_unregister); |
6608804b VS |
1176 | |
1177 | #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x) | |
1178 | ||
1179 | /** | |
1180 | * drm_dp_psr_setup_time() - PSR setup in time usec | |
1181 | * @psr_cap: PSR capabilities from DPCD | |
1182 | * | |
1183 | * Returns: | |
1184 | * PSR setup time for the panel in microseconds, negative | |
1185 | * error code on failure. | |
1186 | */ | |
1187 | int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]) | |
1188 | { | |
1189 | static const u16 psr_setup_time_us[] = { | |
1190 | PSR_SETUP_TIME(330), | |
1191 | PSR_SETUP_TIME(275), | |
bdcc02cf | 1192 | PSR_SETUP_TIME(220), |
6608804b VS |
1193 | PSR_SETUP_TIME(165), |
1194 | PSR_SETUP_TIME(110), | |
1195 | PSR_SETUP_TIME(55), | |
1196 | PSR_SETUP_TIME(0), | |
1197 | }; | |
1198 | int i; | |
1199 | ||
1200 | i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT; | |
1201 | if (i >= ARRAY_SIZE(psr_setup_time_us)) | |
1202 | return -EINVAL; | |
1203 | ||
1204 | return psr_setup_time_us[i]; | |
1205 | } | |
1206 | EXPORT_SYMBOL(drm_dp_psr_setup_time); | |
1207 | ||
1208 | #undef PSR_SETUP_TIME | |
79c1da7c TV |
1209 | |
1210 | /** | |
1211 | * drm_dp_start_crc() - start capture of frame CRCs | |
1212 | * @aux: DisplayPort AUX channel | |
0621ce1d | 1213 | * @crtc: CRTC displaying the frames whose CRCs are to be captured |
79c1da7c TV |
1214 | * |
1215 | * Returns 0 on success or a negative error code on failure. | |
1216 | */ | |
1217 | int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc) | |
1218 | { | |
1219 | u8 buf; | |
1220 | int ret; | |
1221 | ||
1222 | ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); | |
1223 | if (ret < 0) | |
1224 | return ret; | |
1225 | ||
1226 | ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START); | |
1227 | if (ret < 0) | |
1228 | return ret; | |
1229 | ||
1230 | aux->crc_count = 0; | |
1231 | aux->crtc = crtc; | |
1232 | schedule_work(&aux->crc_work); | |
1233 | ||
1234 | return 0; | |
1235 | } | |
1236 | EXPORT_SYMBOL(drm_dp_start_crc); | |
1237 | ||
1238 | /** | |
1239 | * drm_dp_stop_crc() - stop capture of frame CRCs | |
1240 | * @aux: DisplayPort AUX channel | |
1241 | * | |
1242 | * Returns 0 on success or a negative error code on failure. | |
1243 | */ | |
1244 | int drm_dp_stop_crc(struct drm_dp_aux *aux) | |
1245 | { | |
1246 | u8 buf; | |
1247 | int ret; | |
1248 | ||
1249 | ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); | |
1250 | if (ret < 0) | |
1251 | return ret; | |
1252 | ||
1253 | ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START); | |
1254 | if (ret < 0) | |
1255 | return ret; | |
1256 | ||
1257 | flush_work(&aux->crc_work); | |
1258 | aux->crtc = NULL; | |
1259 | ||
1260 | return 0; | |
1261 | } | |
1262 | EXPORT_SYMBOL(drm_dp_stop_crc); | |
118b90f3 | 1263 | |
76fa998a JN |
1264 | struct dpcd_quirk { |
1265 | u8 oui[3]; | |
0b49bbbd | 1266 | u8 device_id[6]; |
76fa998a JN |
1267 | bool is_branch; |
1268 | u32 quirks; | |
1269 | }; | |
1270 | ||
1271 | #define OUI(first, second, third) { (first), (second), (third) } | |
0b49bbbd LS |
1272 | #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \ |
1273 | { (first), (second), (third), (fourth), (fifth), (sixth) } | |
1274 | ||
1275 | #define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0) | |
76fa998a JN |
1276 | |
1277 | static const struct dpcd_quirk dpcd_quirk_list[] = { | |
1278 | /* Analogix 7737 needs reduced M and N at HBR2 link rates */ | |
53ca2edc | 1279 | { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, |
e884818c LS |
1280 | /* LG LP140WF6-SPM1 eDP panel */ |
1281 | { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, | |
7c5c641a JRS |
1282 | /* Apple panels need some additional handling to support PSR */ |
1283 | { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) } | |
76fa998a JN |
1284 | }; |
1285 | ||
1286 | #undef OUI | |
1287 | ||
1288 | /* | |
1289 | * Get a bit mask of DPCD quirks for the sink/branch device identified by | |
1290 | * ident. The quirk data is shared but it's up to the drivers to act on the | |
1291 | * data. | |
1292 | * | |
1293 | * For now, only the OUI (first three bytes) is used, but this may be extended | |
1294 | * to device identification string and hardware/firmware revisions later. | |
1295 | */ | |
1296 | static u32 | |
1297 | drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch) | |
1298 | { | |
1299 | const struct dpcd_quirk *quirk; | |
1300 | u32 quirks = 0; | |
1301 | int i; | |
0b49bbbd | 1302 | u8 any_device[] = DEVICE_ID_ANY; |
76fa998a JN |
1303 | |
1304 | for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) { | |
1305 | quirk = &dpcd_quirk_list[i]; | |
1306 | ||
1307 | if (quirk->is_branch != is_branch) | |
1308 | continue; | |
1309 | ||
1310 | if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0) | |
1311 | continue; | |
1312 | ||
0b49bbbd LS |
1313 | if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 && |
1314 | memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0) | |
1315 | continue; | |
1316 | ||
76fa998a JN |
1317 | quirks |= quirk->quirks; |
1318 | } | |
1319 | ||
1320 | return quirks; | |
1321 | } | |
1322 | ||
0b49bbbd LS |
1323 | #undef DEVICE_ID_ANY |
1324 | #undef DEVICE_ID | |
1325 | ||
118b90f3 JN |
1326 | /** |
1327 | * drm_dp_read_desc - read sink/branch descriptor from DPCD | |
1328 | * @aux: DisplayPort AUX channel | |
1329 | * @desc: Device decriptor to fill from DPCD | |
1330 | * @is_branch: true for branch devices, false for sink devices | |
1331 | * | |
1332 | * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the | |
1333 | * identification. | |
1334 | * | |
1335 | * Returns 0 on success or a negative error code on failure. | |
1336 | */ | |
1337 | int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, | |
1338 | bool is_branch) | |
1339 | { | |
1340 | struct drm_dp_dpcd_ident *ident = &desc->ident; | |
1341 | unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI; | |
1342 | int ret, dev_id_len; | |
1343 | ||
1344 | ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident)); | |
1345 | if (ret < 0) | |
1346 | return ret; | |
1347 | ||
76fa998a JN |
1348 | desc->quirks = drm_dp_get_quirks(ident, is_branch); |
1349 | ||
118b90f3 JN |
1350 | dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id)); |
1351 | ||
76fa998a | 1352 | DRM_DEBUG_KMS("DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n", |
118b90f3 JN |
1353 | is_branch ? "branch" : "sink", |
1354 | (int)sizeof(ident->oui), ident->oui, | |
1355 | dev_id_len, ident->device_id, | |
1356 | ident->hw_rev >> 4, ident->hw_rev & 0xf, | |
76fa998a JN |
1357 | ident->sw_major_rev, ident->sw_minor_rev, |
1358 | desc->quirks); | |
118b90f3 JN |
1359 | |
1360 | return 0; | |
1361 | } | |
1362 | EXPORT_SYMBOL(drm_dp_read_desc); | |
05756500 MN |
1363 | |
1364 | /** | |
05bad235 MN |
1365 | * drm_dp_dsc_sink_max_slice_count() - Get the max slice count |
1366 | * supported by the DSC sink. | |
1367 | * @dsc_dpcd: DSC capabilities from DPCD | |
1368 | * @is_edp: true if its eDP, false for DP | |
1369 | * | |
1370 | * Read the slice capabilities DPCD register from DSC sink to get | |
1371 | * the maximum slice count supported. This is used to populate | |
1372 | * the DSC parameters in the &struct drm_dsc_config by the driver. | |
1373 | * Driver creates an infoframe using these parameters to populate | |
1374 | * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC | |
1375 | * infoframe using the helper function drm_dsc_pps_infoframe_pack() | |
1376 | * | |
1377 | * Returns: | |
1378 | * Maximum slice count supported by DSC sink or 0 its invalid | |
05756500 MN |
1379 | */ |
1380 | u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], | |
1381 | bool is_edp) | |
1382 | { | |
1383 | u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; | |
1384 | ||
1385 | if (is_edp) { | |
1386 | /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */ | |
1387 | if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) | |
1388 | return 4; | |
1389 | if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) | |
1390 | return 2; | |
1391 | if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) | |
1392 | return 1; | |
1393 | } else { | |
1394 | /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ | |
1395 | u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; | |
1396 | ||
1397 | if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) | |
1398 | return 24; | |
1399 | if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) | |
1400 | return 20; | |
1401 | if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) | |
1402 | return 16; | |
1403 | if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) | |
1404 | return 12; | |
1405 | if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) | |
1406 | return 10; | |
1407 | if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) | |
1408 | return 8; | |
1409 | if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) | |
1410 | return 6; | |
1411 | if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) | |
1412 | return 4; | |
1413 | if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) | |
1414 | return 2; | |
1415 | if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) | |
1416 | return 1; | |
1417 | } | |
1418 | ||
1419 | return 0; | |
1420 | } | |
1421 | EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); | |
1422 | ||
05bad235 MN |
1423 | /** |
1424 | * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits | |
1425 | * @dsc_dpcd: DSC capabilities from DPCD | |
1426 | * | |
1427 | * Read the DSC DPCD register to parse the line buffer depth in bits which is | |
1428 | * number of bits of precision within the decoder line buffer supported by | |
1429 | * the DSC sink. This is used to populate the DSC parameters in the | |
1430 | * &struct drm_dsc_config by the driver. | |
1431 | * Driver creates an infoframe using these parameters to populate | |
1432 | * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC | |
1433 | * infoframe using the helper function drm_dsc_pps_infoframe_pack() | |
1434 | * | |
1435 | * Returns: | |
1436 | * Line buffer depth supported by DSC panel or 0 its invalid | |
1437 | */ | |
05756500 MN |
1438 | u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) |
1439 | { | |
1440 | u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; | |
1441 | ||
1442 | switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) { | |
1443 | case DP_DSC_LINE_BUF_BIT_DEPTH_9: | |
1444 | return 9; | |
1445 | case DP_DSC_LINE_BUF_BIT_DEPTH_10: | |
1446 | return 10; | |
1447 | case DP_DSC_LINE_BUF_BIT_DEPTH_11: | |
1448 | return 11; | |
1449 | case DP_DSC_LINE_BUF_BIT_DEPTH_12: | |
1450 | return 12; | |
1451 | case DP_DSC_LINE_BUF_BIT_DEPTH_13: | |
1452 | return 13; | |
1453 | case DP_DSC_LINE_BUF_BIT_DEPTH_14: | |
1454 | return 14; | |
1455 | case DP_DSC_LINE_BUF_BIT_DEPTH_15: | |
1456 | return 15; | |
1457 | case DP_DSC_LINE_BUF_BIT_DEPTH_16: | |
1458 | return 16; | |
1459 | case DP_DSC_LINE_BUF_BIT_DEPTH_8: | |
1460 | return 8; | |
1461 | } | |
1462 | ||
1463 | return 0; | |
1464 | } | |
1465 | EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth); | |
1466 | ||
05bad235 MN |
1467 | /** |
1468 | * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component | |
1469 | * values supported by the DSC sink. | |
1470 | * @dsc_dpcd: DSC capabilities from DPCD | |
1471 | * @dsc_bpc: An array to be filled by this helper with supported | |
1472 | * input bpcs. | |
1473 | * | |
1474 | * Read the DSC DPCD from the sink device to parse the supported bits per | |
1475 | * component values. This is used to populate the DSC parameters | |
1476 | * in the &struct drm_dsc_config by the driver. | |
1477 | * Driver creates an infoframe using these parameters to populate | |
1478 | * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC | |
1479 | * infoframe using the helper function drm_dsc_pps_infoframe_pack() | |
1480 | * | |
1481 | * Returns: | |
1482 | * Number of input BPC values parsed from the DPCD | |
1483 | */ | |
4d4101c8 MN |
1484 | int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], |
1485 | u8 dsc_bpc[3]) | |
05756500 | 1486 | { |
4d4101c8 | 1487 | int num_bpc = 0; |
05756500 MN |
1488 | u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; |
1489 | ||
1490 | if (color_depth & DP_DSC_12_BPC) | |
4d4101c8 | 1491 | dsc_bpc[num_bpc++] = 12; |
05756500 | 1492 | if (color_depth & DP_DSC_10_BPC) |
4d4101c8 | 1493 | dsc_bpc[num_bpc++] = 10; |
05756500 | 1494 | if (color_depth & DP_DSC_8_BPC) |
4d4101c8 | 1495 | dsc_bpc[num_bpc++] = 8; |
05756500 | 1496 | |
4d4101c8 | 1497 | return num_bpc; |
05756500 | 1498 | } |
4d4101c8 | 1499 | EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs); |