[people/ms/linux.git] / drivers / gpu / drm / gma500 / oaktrail_device.c

// SPDX-License-Identifier: GPL-2.0-only
/**************************************************************************
 * Copyright (c) 2011, Intel Corporation.
 * All Rights Reserved.
 *
 **************************************************************************/

#include <linux/backlight.h>
#include <linux/delay.h>
#include <linux/dmi.h>
#include <linux/module.h>

#include <drm/drm.h>

#include "intel_bios.h"
#include "mid_bios.h"
#include "psb_drv.h"
#include "psb_intel_reg.h"
#include "psb_reg.h"

static int oaktrail_output_init(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
	if (dev_priv->iLVDS_enable)
		oaktrail_lvds_init(dev, &dev_priv->mode_dev);
	else
		dev_err(dev->dev, "DSI is not supported\n");
	if (dev_priv->hdmi_priv)
		oaktrail_hdmi_init(dev, &dev_priv->mode_dev);

	psb_intel_sdvo_init(dev, SDVOB);

	return 0;
}

/*
 *	Provide the low level interfaces for the Moorestown backlight
 */

#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE

#define MRST_BLC_MAX_PWM_REG_FREQ	    0xFFFF
#define BLC_PWM_PRECISION_FACTOR 100	/* 10000000 */
#define BLC_PWM_FREQ_CALC_CONSTANT 32
#define MHz 1000000
#define BLC_ADJUSTMENT_MAX 100

static struct backlight_device *oaktrail_backlight_device;
static int oaktrail_brightness;

static int oaktrail_set_brightness(struct backlight_device *bd)
{
	struct drm_device *dev = bl_get_data(oaktrail_backlight_device);
	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
	int level = bd->props.brightness;
	u32 blc_pwm_ctl;
	u32 max_pwm_blc;

	/* Percentage 1-100% being valid */
	if (level < 1)
		level = 1;

	if (gma_power_begin(dev, 0)) {
		/* Calculate and set the brightness value */
		max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;
		blc_pwm_ctl = level * max_pwm_blc / 100;

		/* Adjust the backlight level with the percent in
		 * dev_priv->blc_adj1;
		 */
		blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
		blc_pwm_ctl = blc_pwm_ctl / 100;

		/* Adjust the backlight level with the percent in
		 * dev_priv->blc_adj2;
		 */
		blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;
		blc_pwm_ctl = blc_pwm_ctl / 100;

		/* force PWM bit on */
		REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
		REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl);
		gma_power_end(dev);
	}
	oaktrail_brightness = level;
	return 0;
}

static int oaktrail_get_brightness(struct backlight_device *bd)
{
	/* return locally cached var instead of HW read (due to DPST etc.) */
	/* FIXME: ideally return actual value in case firmware fiddled with
	   it */
	return oaktrail_brightness;
}

static int device_backlight_init(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
	unsigned long core_clock;
	u16 bl_max_freq;
	uint32_t value;
	uint32_t blc_pwm_precision_factor;

	dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
	dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
	bl_max_freq = 256;
	/* this needs to be set elsewhere */
	blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR;

	core_clock = dev_priv->core_freq;

	value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
	value *= blc_pwm_precision_factor;
	value /= bl_max_freq;
	value /= blc_pwm_precision_factor;

	if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ)
			return -ERANGE;

	if (gma_power_begin(dev, false)) {
		REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
		REG_WRITE(BLC_PWM_CTL, value | (value << 16));
		gma_power_end(dev);
	}
	return 0;
}

static const struct backlight_ops oaktrail_ops = {
	.get_brightness = oaktrail_get_brightness,
	.update_status  = oaktrail_set_brightness,
};

static int oaktrail_backlight_init(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
	int ret;
	struct backlight_properties props;

	memset(&props, 0, sizeof(struct backlight_properties));
	props.max_brightness = 100;
	props.type = BACKLIGHT_PLATFORM;

	oaktrail_backlight_device = backlight_device_register("oaktrail-bl",
				NULL, (void *)dev, &oaktrail_ops, &props);

	if (IS_ERR(oaktrail_backlight_device))
		return PTR_ERR(oaktrail_backlight_device);

	ret = device_backlight_init(dev);
	if (ret < 0) {
		backlight_device_unregister(oaktrail_backlight_device);
		return ret;
	}
	oaktrail_backlight_device->props.brightness = 100;
	oaktrail_backlight_device->props.max_brightness = 100;
	backlight_update_status(oaktrail_backlight_device);
	dev_priv->backlight_device = oaktrail_backlight_device;
	return 0;
}

#endif

/*
 *	Provide the Moorestown specific chip logic and low level methods
 *	for power management
 */

/**
 *	oaktrail_save_display_registers	-	save registers lost on suspend
 *	@dev: our DRM device
 *
 *	Save the state we need in order to be able to restore the interface
 *	upon resume from suspend
 */
static int oaktrail_save_display_registers(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
	struct psb_save_area *regs = &dev_priv->regs;
	struct psb_pipe *p = &regs->pipe[0];
	int i;
	u32 pp_stat;

	/* Display arbitration control + watermarks */
	regs->psb.saveDSPARB = PSB_RVDC32(DSPARB);
	regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1);
	regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2);
	regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3);
	regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4);
	regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5);
	regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6);
	regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);

	/* Pipe & plane A info */
	p->conf = PSB_RVDC32(PIPEACONF);
	p->src = PSB_RVDC32(PIPEASRC);
	p->fp0 = PSB_RVDC32(MRST_FPA0);
	p->fp1 = PSB_RVDC32(MRST_FPA1);
	p->dpll = PSB_RVDC32(MRST_DPLL_A);
	p->htotal = PSB_RVDC32(HTOTAL_A);
	p->hblank = PSB_RVDC32(HBLANK_A);
	p->hsync = PSB_RVDC32(HSYNC_A);
	p->vtotal = PSB_RVDC32(VTOTAL_A);
	p->vblank = PSB_RVDC32(VBLANK_A);
	p->vsync = PSB_RVDC32(VSYNC_A);
	regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
	p->cntr = PSB_RVDC32(DSPACNTR);
	p->stride = PSB_RVDC32(DSPASTRIDE);
	p->addr = PSB_RVDC32(DSPABASE);
	p->surf = PSB_RVDC32(DSPASURF);
	p->linoff = PSB_RVDC32(DSPALINOFF);
	p->tileoff = PSB_RVDC32(DSPATILEOFF);

	/* Save cursor regs */
	regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
	regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
	regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);

	/* Save palette (gamma) */
	for (i = 0; i < 256; i++)
		p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2));

	if (dev_priv->hdmi_priv)
		oaktrail_hdmi_save(dev);

	/* Save performance state */
	regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);

	/* LVDS state */
	regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
	regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
	regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
	regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
	regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
	regs->psb.saveLVDS = PSB_RVDC32(LVDS);
	regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
	regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
	regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
	regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);

	/* HW overlay */
	regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD);
	regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
	regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
	regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
	regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
	regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
	regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);

	/* DPST registers */
	regs->psb.saveHISTOGRAM_INT_CONTROL_REG =
					PSB_RVDC32(HISTOGRAM_INT_CONTROL);
	regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG =
					PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
	regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);

	if (dev_priv->iLVDS_enable) {
		/* Shut down the panel */
		PSB_WVDC32(0, PP_CONTROL);

		do {
			pp_stat = PSB_RVDC32(PP_STATUS);
		} while (pp_stat & 0x80000000);

		/* Turn off the plane */
		PSB_WVDC32(0x58000000, DSPACNTR);
		/* Trigger the plane disable */
		PSB_WVDC32(0, DSPASURF);

		/* Wait ~4 ticks */
		msleep(4);

		/* Turn off pipe */
		PSB_WVDC32(0x0, PIPEACONF);
		/* Wait ~8 ticks */
		msleep(8);

		/* Turn off PLLs */
		PSB_WVDC32(0, MRST_DPLL_A);
	}
	return 0;
}

/**
 *	oaktrail_restore_display_registers	-	restore lost register state
 *	@dev: our DRM device
 *
 *	Restore register state that was lost during suspend and resume.
 */
static int oaktrail_restore_display_registers(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
	struct psb_save_area *regs = &dev_priv->regs;
	struct psb_pipe *p = &regs->pipe[0];
	u32 pp_stat;
	int i;

	/* Display arbitration + watermarks */
	PSB_WVDC32(regs->psb.saveDSPARB, DSPARB);
	PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1);
	PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2);
	PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3);
	PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4);
	PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5);
	PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6);
	PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT);

	/* Make sure VGA plane is off. it initializes to on after reset!*/
	PSB_WVDC32(0x80000000, VGACNTRL);

	/* set the plls */
	PSB_WVDC32(p->fp0, MRST_FPA0);
	PSB_WVDC32(p->fp1, MRST_FPA1);

	/* Actually enable it */
	PSB_WVDC32(p->dpll, MRST_DPLL_A);
	udelay(150);

	/* Restore mode */
	PSB_WVDC32(p->htotal, HTOTAL_A);
	PSB_WVDC32(p->hblank, HBLANK_A);
	PSB_WVDC32(p->hsync, HSYNC_A);
	PSB_WVDC32(p->vtotal, VTOTAL_A);
	PSB_WVDC32(p->vblank, VBLANK_A);
	PSB_WVDC32(p->vsync, VSYNC_A);
	PSB_WVDC32(p->src, PIPEASRC);
	PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A);

	/* Restore performance mode*/
	PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE);

	/* Enable the pipe*/
	if (dev_priv->iLVDS_enable)
		PSB_WVDC32(p->conf, PIPEACONF);

	/* Set up the plane*/
	PSB_WVDC32(p->linoff, DSPALINOFF);
	PSB_WVDC32(p->stride, DSPASTRIDE);
	PSB_WVDC32(p->tileoff, DSPATILEOFF);

	/* Enable the plane */
	PSB_WVDC32(p->cntr, DSPACNTR);
	PSB_WVDC32(p->surf, DSPASURF);

	/* Enable Cursor A */
	PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR);
	PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS);
	PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE);

	/* Restore palette (gamma) */
	for (i = 0; i < 256; i++)
		PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2));

	if (dev_priv->hdmi_priv)
		oaktrail_hdmi_restore(dev);

	if (dev_priv->iLVDS_enable) {
		PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
		PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/
		PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL);
		PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
		PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
		PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL);
		PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON);
		PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF);
		PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE);
		PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);
	}

	/* Wait for cycle delay */
	do {
		pp_stat = PSB_RVDC32(PP_STATUS);
	} while (pp_stat & 0x08000000);

	/* Wait for panel power up */
	do {
		pp_stat = PSB_RVDC32(PP_STATUS);
	} while (pp_stat & 0x10000000);

	/* Restore HW overlay */
	PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD);
	PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0);
	PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1);
	PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2);
	PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3);
	PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4);
	PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5);

	/* DPST registers */
	PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG,
						HISTOGRAM_INT_CONTROL);
	PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG,
						HISTOGRAM_LOGIC_CONTROL);
	PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);

	return 0;
}

/**
 *	oaktrail_power_down	-	power down the display island
 *	@dev: our DRM device
 *
 *	Power down the display interface of our device
 */
static int oaktrail_power_down(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
	u32 pwr_mask ;
	u32 pwr_sts;

	pwr_mask = PSB_PWRGT_DISPLAY_MASK;
	outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);

	while (true) {
		pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
		if ((pwr_sts & pwr_mask) == pwr_mask)
			break;
		else
			udelay(10);
	}
	return 0;
}

/*
 * oaktrail_power_up
 *
 * Restore power to the specified island(s) (powergating)
 */
static int oaktrail_power_up(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
	u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
	u32 pwr_sts, pwr_cnt;

	pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
	pwr_cnt &= ~pwr_mask;
	outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));

	while (true) {
		pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
		if ((pwr_sts & pwr_mask) == 0)
			break;
		else
			udelay(10);
	}
	return 0;
}

/* Oaktrail */
static const struct psb_offset oaktrail_regmap[2] = {
	{
		.fp0 = MRST_FPA0,
		.fp1 = MRST_FPA1,
		.cntr = DSPACNTR,
		.conf = PIPEACONF,
		.src = PIPEASRC,
		.dpll = MRST_DPLL_A,
		.htotal = HTOTAL_A,
		.hblank = HBLANK_A,
		.hsync = HSYNC_A,
		.vtotal = VTOTAL_A,
		.vblank = VBLANK_A,
		.vsync = VSYNC_A,
		.stride = DSPASTRIDE,
		.size = DSPASIZE,
		.pos = DSPAPOS,
		.surf = DSPASURF,
		.addr = MRST_DSPABASE,
		.base = MRST_DSPABASE,
		.status = PIPEASTAT,
		.linoff = DSPALINOFF,
		.tileoff = DSPATILEOFF,
		.palette = PALETTE_A,
	},
	{
		.fp0 = FPB0,
		.fp1 = FPB1,
		.cntr = DSPBCNTR,
		.conf = PIPEBCONF,
		.src = PIPEBSRC,
		.dpll = DPLL_B,
		.htotal = HTOTAL_B,
		.hblank = HBLANK_B,
		.hsync = HSYNC_B,
		.vtotal = VTOTAL_B,
		.vblank = VBLANK_B,
		.vsync = VSYNC_B,
		.stride = DSPBSTRIDE,
		.size = DSPBSIZE,
		.pos = DSPBPOS,
		.surf = DSPBSURF,
		.addr = DSPBBASE,
		.base = DSPBBASE,
		.status = PIPEBSTAT,
		.linoff = DSPBLINOFF,
		.tileoff = DSPBTILEOFF,
		.palette = PALETTE_B,
	},
};

static int oaktrail_chip_setup(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
	int ret;

	dev_priv->use_msi = true;
	dev_priv->regmap = oaktrail_regmap;

	ret = mid_chip_setup(dev);
	if (ret < 0)
		return ret;
	if (!dev_priv->has_gct) {
		/* Now pull the BIOS data */
		psb_intel_opregion_init(dev);
		psb_intel_init_bios(dev);
	}
	gma_intel_setup_gmbus(dev);
	oaktrail_hdmi_setup(dev);
	return 0;
}

static void oaktrail_teardown(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);

	gma_intel_teardown_gmbus(dev);
	oaktrail_hdmi_teardown(dev);
	if (!dev_priv->has_gct)
		psb_intel_destroy_bios(dev);
}

const struct psb_ops oaktrail_chip_ops = {
	.name = "Oaktrail",
	.pipes = 2,
	.crtcs = 2,
	.hdmi_mask = (1 << 1),
	.lvds_mask = (1 << 0),
	.sdvo_mask = (1 << 1),
	.cursor_needs_phys = 0,
	.sgx_offset = MRST_SGX_OFFSET,

	.chip_setup = oaktrail_chip_setup,
	.chip_teardown = oaktrail_teardown,
	.crtc_helper = &oaktrail_helper_funcs,

	.output_init = oaktrail_output_init,

#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	.backlight_init = oaktrail_backlight_init,
#endif

	.save_regs = oaktrail_save_display_registers,
	.restore_regs = oaktrail_restore_display_registers,
	.save_crtc = gma_crtc_save,
	.restore_crtc = gma_crtc_restore,
	.power_down = oaktrail_power_down,
	.power_up = oaktrail_power_up,

	.i2c_bus = 1,
};
Commit	Line	Data
a61127c2	1	// SPDX-License-Identifier: GPL-2.0-only
1b082ccf AC	2	/**************************************************************************
	3	* Copyright (c) 2011, Intel Corporation.
	4	* All Rights Reserved.
	5	*
1b082ccf AC	6	**************************************************************************/
	7
	8	#include <linux/backlight.h>
0c7b178a	9	#include <linux/delay.h>
1b082ccf	10	#include <linux/dmi.h>
0c7b178a	11	#include <linux/module.h>
d825c565	12
0c7b178a SR	13	#include <drm/drm.h>
0c7b178a SR	14
aa0c45fd	15	#include "intel_bios.h"
0c7b178a SR	16	#include "mid_bios.h"
	17	#include "psb_drv.h"
	18	#include "psb_intel_reg.h"
	19	#include "psb_reg.h"
1b082ccf AC	20
	21	static int oaktrail_output_init(struct drm_device *dev)
	22	{
f71635e8	23	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
1b082ccf AC	24	if (dev_priv->iLVDS_enable)
	25	oaktrail_lvds_init(dev, &dev_priv->mode_dev);
	26	else
	27	dev_err(dev->dev, "DSI is not supported\n");
	28	if (dev_priv->hdmi_priv)
	29	oaktrail_hdmi_init(dev, &dev_priv->mode_dev);
cd3fdbe8 PJ	30
	31	psb_intel_sdvo_init(dev, SDVOB);
	32
1b082ccf AC	33	return 0;
	34	}
	35
	36	/*
	37	* Provide the low level interfaces for the Moorestown backlight
	38	*/
	39
	40	#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	41
	42	#define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
	43	#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
	44	#define BLC_PWM_FREQ_CALC_CONSTANT 32
	45	#define MHz 1000000
	46	#define BLC_ADJUSTMENT_MAX 100
	47
	48	static struct backlight_device *oaktrail_backlight_device;
	49	static int oaktrail_brightness;
	50
	51	static int oaktrail_set_brightness(struct backlight_device *bd)
	52	{
	53	struct drm_device *dev = bl_get_data(oaktrail_backlight_device);
f71635e8	54	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
1b082ccf AC	55	int level = bd->props.brightness;
	56	u32 blc_pwm_ctl;
	57	u32 max_pwm_blc;
	58
	59	/* Percentage 1-100% being valid */
	60	if (level < 1)
	61	level = 1;
	62
	63	if (gma_power_begin(dev, 0)) {
	64	/* Calculate and set the brightness value */
	65	max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;
	66	blc_pwm_ctl = level * max_pwm_blc / 100;
	67
	68	/* Adjust the backlight level with the percent in
	69	* dev_priv->blc_adj1;
	70	*/
	71	blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
	72	blc_pwm_ctl = blc_pwm_ctl / 100;
	73
	74	/* Adjust the backlight level with the percent in
	75	* dev_priv->blc_adj2;
	76	*/
	77	blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;
	78	blc_pwm_ctl = blc_pwm_ctl / 100;
	79
	80	/* force PWM bit on */
	81	REG_WRITE(BLC_PWM_CTL2, (0x80000000 \| REG_READ(BLC_PWM_CTL2)));
	82	REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) \| blc_pwm_ctl);
	83	gma_power_end(dev);
	84	}
	85	oaktrail_brightness = level;
	86	return 0;
	87	}
	88
	89	static int oaktrail_get_brightness(struct backlight_device *bd)
	90	{
	91	/* return locally cached var instead of HW read (due to DPST etc.) */
	92	/* FIXME: ideally return actual value in case firmware fiddled with
	93	it */
	94	return oaktrail_brightness;
	95	}
	96
	97	static int device_backlight_init(struct drm_device *dev)
	98	{
f71635e8	99	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
1b082ccf AC	100	unsigned long core_clock;
	101	u16 bl_max_freq;
	102	uint32_t value;
	103	uint32_t blc_pwm_precision_factor;
	104
	105	dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
	106	dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
	107	bl_max_freq = 256;
	108	/* this needs to be set elsewhere */
	109	blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR;
	110
	111	core_clock = dev_priv->core_freq;
	112
	113	value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
	114	value *= blc_pwm_precision_factor;
	115	value /= bl_max_freq;
	116	value /= blc_pwm_precision_factor;
	117
	118	if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ)
	119	return -ERANGE;
	120
	121	if (gma_power_begin(dev, false)) {
	122	REG_WRITE(BLC_PWM_CTL2, (0x80000000 \| REG_READ(BLC_PWM_CTL2)));
	123	REG_WRITE(BLC_PWM_CTL, value \| (value << 16));
	124	gma_power_end(dev);
	125	}
	126	return 0;
	127	}
	128
	129	static const struct backlight_ops oaktrail_ops = {
	130	.get_brightness = oaktrail_get_brightness,
	131	.update_status = oaktrail_set_brightness,
	132	};
	133
771f64d0	134	static int oaktrail_backlight_init(struct drm_device *dev)
1b082ccf	135	{
f71635e8	136	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
1b082ccf AC	137	int ret;
	138	struct backlight_properties props;
	139
	140	memset(&props, 0, sizeof(struct backlight_properties));
	141	props.max_brightness = 100;
	142	props.type = BACKLIGHT_PLATFORM;
	143
	144	oaktrail_backlight_device = backlight_device_register("oaktrail-bl",
	145	NULL, (void *)dev, &oaktrail_ops, &props);
	146
	147	if (IS_ERR(oaktrail_backlight_device))
	148	return PTR_ERR(oaktrail_backlight_device);
	149
	150	ret = device_backlight_init(dev);
	151	if (ret < 0) {
	152	backlight_device_unregister(oaktrail_backlight_device);
	153	return ret;
	154	}
	155	oaktrail_backlight_device->props.brightness = 100;
	156	oaktrail_backlight_device->props.max_brightness = 100;
	157	backlight_update_status(oaktrail_backlight_device);
	158	dev_priv->backlight_device = oaktrail_backlight_device;
	159	return 0;
	160	}
	161
	162	#endif
	163
	164	/*
	165	* Provide the Moorestown specific chip logic and low level methods
	166	* for power management
	167	*/
	168
1b082ccf AC	169	/**
	170	* oaktrail_save_display_registers - save registers lost on suspend
	171	* @dev: our DRM device
	172	*
	173	* Save the state we need in order to be able to restore the interface
	174	* upon resume from suspend
	175	*/
	176	static int oaktrail_save_display_registers(struct drm_device *dev)
	177	{
f71635e8	178	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
c6265ff5	179	struct psb_save_area *regs = &dev_priv->regs;
6256304b	180	struct psb_pipe *p = &regs->pipe[0];
1b082ccf AC	181	int i;
	182	u32 pp_stat;
	183
	184	/* Display arbitration control + watermarks */
c6265ff5 AC	185	regs->psb.saveDSPARB = PSB_RVDC32(DSPARB);
	186	regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1);
	187	regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2);
	188	regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3);
	189	regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4);
	190	regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5);
	191	regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6);
	192	regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
1b082ccf AC	193
1b082ccf AC	194	/* Pipe & plane A info */
6256304b AC	195	p->conf = PSB_RVDC32(PIPEACONF);
	196	p->src = PSB_RVDC32(PIPEASRC);
	197	p->fp0 = PSB_RVDC32(MRST_FPA0);
	198	p->fp1 = PSB_RVDC32(MRST_FPA1);
	199	p->dpll = PSB_RVDC32(MRST_DPLL_A);
	200	p->htotal = PSB_RVDC32(HTOTAL_A);
	201	p->hblank = PSB_RVDC32(HBLANK_A);
	202	p->hsync = PSB_RVDC32(HSYNC_A);
	203	p->vtotal = PSB_RVDC32(VTOTAL_A);
	204	p->vblank = PSB_RVDC32(VBLANK_A);
	205	p->vsync = PSB_RVDC32(VSYNC_A);
c6265ff5	206	regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
6256304b AC	207	p->cntr = PSB_RVDC32(DSPACNTR);
	208	p->stride = PSB_RVDC32(DSPASTRIDE);
	209	p->addr = PSB_RVDC32(DSPABASE);
	210	p->surf = PSB_RVDC32(DSPASURF);
	211	p->linoff = PSB_RVDC32(DSPALINOFF);
	212	p->tileoff = PSB_RVDC32(DSPATILEOFF);
1b082ccf AC	213
1b082ccf AC	214	/* Save cursor regs */
c6265ff5 AC	215	regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
	216	regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
	217	regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);
1b082ccf AC	218
	219	/* Save palette (gamma) */
	220	for (i = 0; i < 256; i++)
6256304b	221	p->palette[i] = PSB_RVDC32(PALETTE_A + (i << 2));
1b082ccf AC	222
	223	if (dev_priv->hdmi_priv)
	224	oaktrail_hdmi_save(dev);
	225
	226	/* Save performance state */
c6265ff5	227	regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);
1b082ccf AC	228
1b082ccf AC	229	/* LVDS state */
c6265ff5 AC	230	regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
	231	regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
	232	regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
648a8e34 AC	233	regs->saveBLC_PWM_CTL = PSB_RVDC32(BLC_PWM_CTL);
648a8e34 AC	234	regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2);
c6265ff5 AC	235	regs->psb.saveLVDS = PSB_RVDC32(LVDS);
	236	regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
	237	regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
	238	regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
	239	regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);
1b082ccf AC	240
1b082ccf AC	241	/* HW overlay */
c6265ff5 AC	242	regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD);
	243	regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
	244	regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
	245	regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
	246	regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
	247	regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
	248	regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);
1b082ccf AC	249
1b082ccf AC	250	/* DPST registers */
c6265ff5	251	regs->psb.saveHISTOGRAM_INT_CONTROL_REG =
1b082ccf	252	PSB_RVDC32(HISTOGRAM_INT_CONTROL);
c6265ff5	253	regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG =
1b082ccf	254	PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
c6265ff5	255	regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);
1b082ccf AC	256
	257	if (dev_priv->iLVDS_enable) {
	258	/* Shut down the panel */
	259	PSB_WVDC32(0, PP_CONTROL);
	260
	261	do {
	262	pp_stat = PSB_RVDC32(PP_STATUS);
	263	} while (pp_stat & 0x80000000);
	264
	265	/* Turn off the plane */
	266	PSB_WVDC32(0x58000000, DSPACNTR);
	267	/* Trigger the plane disable */
	268	PSB_WVDC32(0, DSPASURF);
	269
	270	/* Wait ~4 ticks */
	271	msleep(4);
	272
	273	/* Turn off pipe */
	274	PSB_WVDC32(0x0, PIPEACONF);
	275	/* Wait ~8 ticks */
	276	msleep(8);
	277
	278	/* Turn off PLLs */
	279	PSB_WVDC32(0, MRST_DPLL_A);
	280	}
	281	return 0;
	282	}
	283
	284	/**
	285	* oaktrail_restore_display_registers - restore lost register state
	286	* @dev: our DRM device
	287	*
	288	* Restore register state that was lost during suspend and resume.
	289	*/
	290	static int oaktrail_restore_display_registers(struct drm_device *dev)
	291	{
f71635e8	292	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
c6265ff5	293	struct psb_save_area *regs = &dev_priv->regs;
6256304b	294	struct psb_pipe *p = &regs->pipe[0];
1b082ccf AC	295	u32 pp_stat;
	296	int i;
	297
	298	/* Display arbitration + watermarks */
c6265ff5 AC	299	PSB_WVDC32(regs->psb.saveDSPARB, DSPARB);
	300	PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1);
	301	PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2);
	302	PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3);
	303	PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4);
	304	PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5);
	305	PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6);
	306	PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT);
1b082ccf AC	307
	308	/* Make sure VGA plane is off. it initializes to on after reset!*/
	309	PSB_WVDC32(0x80000000, VGACNTRL);
	310
	311	/* set the plls */
6256304b AC	312	PSB_WVDC32(p->fp0, MRST_FPA0);
6256304b AC	313	PSB_WVDC32(p->fp1, MRST_FPA1);
1b082ccf AC	314
1b082ccf AC	315	/* Actually enable it */
6256304b	316	PSB_WVDC32(p->dpll, MRST_DPLL_A);
bc9f1007	317	udelay(150);
1b082ccf AC	318
1b082ccf AC	319	/* Restore mode */
6256304b AC	320	PSB_WVDC32(p->htotal, HTOTAL_A);
	321	PSB_WVDC32(p->hblank, HBLANK_A);
	322	PSB_WVDC32(p->hsync, HSYNC_A);
	323	PSB_WVDC32(p->vtotal, VTOTAL_A);
	324	PSB_WVDC32(p->vblank, VBLANK_A);
	325	PSB_WVDC32(p->vsync, VSYNC_A);
	326	PSB_WVDC32(p->src, PIPEASRC);
c6265ff5	327	PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A);
1b082ccf AC	328
1b082ccf AC	329	/* Restore performance mode*/
c6265ff5	330	PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE);
1b082ccf AC	331
	332	/* Enable the pipe*/
	333	if (dev_priv->iLVDS_enable)
6256304b	334	PSB_WVDC32(p->conf, PIPEACONF);
1b082ccf AC	335
1b082ccf AC	336	/* Set up the plane*/
6256304b AC	337	PSB_WVDC32(p->linoff, DSPALINOFF);
	338	PSB_WVDC32(p->stride, DSPASTRIDE);
	339	PSB_WVDC32(p->tileoff, DSPATILEOFF);
1b082ccf AC	340
1b082ccf AC	341	/* Enable the plane */
6256304b AC	342	PSB_WVDC32(p->cntr, DSPACNTR);
6256304b AC	343	PSB_WVDC32(p->surf, DSPASURF);
1b082ccf AC	344
1b082ccf AC	345	/* Enable Cursor A */
c6265ff5 AC	346	PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR);
	347	PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS);
	348	PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE);
1b082ccf AC	349
	350	/* Restore palette (gamma) */
	351	for (i = 0; i < 256; i++)
6256304b	352	PSB_WVDC32(p->palette[i], PALETTE_A + (i << 2));
1b082ccf AC	353
	354	if (dev_priv->hdmi_priv)
	355	oaktrail_hdmi_restore(dev);
	356
	357	if (dev_priv->iLVDS_enable) {
648a8e34	358	PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2);
c6265ff5 AC	359	PSB_WVDC32(regs->psb.saveLVDS, LVDS); /port 61180h/
	360	PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL);
	361	PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
	362	PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
648a8e34	363	PSB_WVDC32(regs->saveBLC_PWM_CTL, BLC_PWM_CTL);
c6265ff5 AC	364	PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON);
	365	PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF);
	366	PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE);
	367	PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);
1b082ccf AC	368	}
	369
	370	/* Wait for cycle delay */
	371	do {
	372	pp_stat = PSB_RVDC32(PP_STATUS);
	373	} while (pp_stat & 0x08000000);
	374
	375	/* Wait for panel power up */
	376	do {
	377	pp_stat = PSB_RVDC32(PP_STATUS);
	378	} while (pp_stat & 0x10000000);
	379
	380	/* Restore HW overlay */
c6265ff5 AC	381	PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD);
	382	PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0);
	383	PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1);
	384	PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2);
	385	PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3);
	386	PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4);
	387	PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5);
1b082ccf AC	388
1b082ccf AC	389	/* DPST registers */
c6265ff5	390	PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG,
1b082ccf	391	HISTOGRAM_INT_CONTROL);
c6265ff5	392	PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG,
1b082ccf	393	HISTOGRAM_LOGIC_CONTROL);
c6265ff5	394	PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);
1b082ccf AC	395
	396	return 0;
	397	}
	398
	399	/**
	400	* oaktrail_power_down - power down the display island
	401	* @dev: our DRM device
	402	*
	403	* Power down the display interface of our device
	404	*/
	405	static int oaktrail_power_down(struct drm_device *dev)
	406	{
f71635e8	407	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
1b082ccf AC	408	u32 pwr_mask ;
	409	u32 pwr_sts;
	410
	411	pwr_mask = PSB_PWRGT_DISPLAY_MASK;
	412	outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);
	413
	414	while (true) {
	415	pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
	416	if ((pwr_sts & pwr_mask) == pwr_mask)
	417	break;
	418	else
	419	udelay(10);
	420	}
	421	return 0;
	422	}
	423
	424	/*
	425	* oaktrail_power_up
	426	*
	427	* Restore power to the specified island(s) (powergating)
	428	*/
	429	static int oaktrail_power_up(struct drm_device *dev)
	430	{
f71635e8	431	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
1b082ccf AC	432	u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
	433	u32 pwr_sts, pwr_cnt;
	434
	435	pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
	436	pwr_cnt &= ~pwr_mask;
	437	outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));
	438
	439	while (true) {
	440	pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
	441	if ((pwr_sts & pwr_mask) == 0)
	442	break;
	443	else
	444	udelay(10);
	445	}
	446	return 0;
	447	}
	448
8512e074 AC	449	/* Oaktrail */
	450	static const struct psb_offset oaktrail_regmap[2] = {
	451	{
	452	.fp0 = MRST_FPA0,
	453	.fp1 = MRST_FPA1,
	454	.cntr = DSPACNTR,
	455	.conf = PIPEACONF,
	456	.src = PIPEASRC,
	457	.dpll = MRST_DPLL_A,
	458	.htotal = HTOTAL_A,
	459	.hblank = HBLANK_A,
	460	.hsync = HSYNC_A,
	461	.vtotal = VTOTAL_A,
	462	.vblank = VBLANK_A,
	463	.vsync = VSYNC_A,
	464	.stride = DSPASTRIDE,
	465	.size = DSPASIZE,
	466	.pos = DSPAPOS,
	467	.surf = DSPASURF,
213a8434	468	.addr = MRST_DSPABASE,
26df641e	469	.base = MRST_DSPABASE,
8512e074 AC	470	.status = PIPEASTAT,
	471	.linoff = DSPALINOFF,
	472	.tileoff = DSPATILEOFF,
	473	.palette = PALETTE_A,
	474	},
	475	{
	476	.fp0 = FPB0,
	477	.fp1 = FPB1,
	478	.cntr = DSPBCNTR,
	479	.conf = PIPEBCONF,
	480	.src = PIPEBSRC,
	481	.dpll = DPLL_B,
	482	.htotal = HTOTAL_B,
	483	.hblank = HBLANK_B,
	484	.hsync = HSYNC_B,
	485	.vtotal = VTOTAL_B,
	486	.vblank = VBLANK_B,
	487	.vsync = VSYNC_B,
	488	.stride = DSPBSTRIDE,
	489	.size = DSPBSIZE,
	490	.pos = DSPBPOS,
	491	.surf = DSPBSURF,
	492	.addr = DSPBBASE,
26df641e	493	.base = DSPBBASE,
8512e074 AC	494	.status = PIPEBSTAT,
	495	.linoff = DSPBLINOFF,
	496	.tileoff = DSPBTILEOFF,
	497	.palette = PALETTE_B,
	498	},
	499	};
1b082ccf	500
1b22edfd	501	static int oaktrail_chip_setup(struct drm_device *dev)
aa0c45fd	502	{
f71635e8	503	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
1b22edfd	504	int ret;
ba596ee6	505
235fdbc3	506	dev_priv->use_msi = true;
8512e074	507	dev_priv->regmap = oaktrail_regmap;
4086b1e2	508
1b22edfd	509	ret = mid_chip_setup(dev);
aa0c45fd AC	510	if (ret < 0)
aa0c45fd AC	511	return ret;
4086b1e2	512	if (!dev_priv->has_gct) {
aa0c45fd	513	/* Now pull the BIOS data */
d839ede4	514	psb_intel_opregion_init(dev);
aa0c45fd AC	515	psb_intel_init_bios(dev);
aa0c45fd AC	516	}
6528c897	517	gma_intel_setup_gmbus(dev);
5f503148	518	oaktrail_hdmi_setup(dev);
aa0c45fd AC	519	return 0;
	520	}
	521
1b082ccf AC	522	static void oaktrail_teardown(struct drm_device *dev)
1b082ccf AC	523	{
f71635e8	524	struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
1b22edfd	525
6528c897	526	gma_intel_teardown_gmbus(dev);
1b082ccf	527	oaktrail_hdmi_teardown(dev);
4086b1e2	528	if (!dev_priv->has_gct)
aa0c45fd	529	psb_intel_destroy_bios(dev);
1b082ccf AC	530	}
	531
	532	const struct psb_ops oaktrail_chip_ops = {
	533	.name = "Oaktrail",
1b082ccf AC	534	.pipes = 2,
1b082ccf AC	535	.crtcs = 2,
39ec748f	536	.hdmi_mask = (1 << 1),
d235e64a	537	.lvds_mask = (1 << 0),
cf8efd3a	538	.sdvo_mask = (1 << 1),
bc794829	539	.cursor_needs_phys = 0,
1b082ccf AC	540	.sgx_offset = MRST_SGX_OFFSET,
1b082ccf AC	541
aa0c45fd	542	.chip_setup = oaktrail_chip_setup,
1b082ccf AC	543	.chip_teardown = oaktrail_teardown,
1b082ccf AC	544	.crtc_helper = &oaktrail_helper_funcs,
1b082ccf AC	545
	546	.output_init = oaktrail_output_init,
	547
	548	#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	549	.backlight_init = oaktrail_backlight_init,
	550	#endif
	551
1b082ccf AC	552	.save_regs = oaktrail_save_display_registers,
1b082ccf AC	553	.restore_regs = oaktrail_restore_display_registers,
d56f57ac DV	554	.save_crtc = gma_crtc_save,
d56f57ac DV	555	.restore_crtc = gma_crtc_restore,
1b082ccf AC	556	.power_down = oaktrail_power_down,
	557	.power_up = oaktrail_power_up,
	558
	559	.i2c_bus = 1,
	560	};