]>
Commit | Line | Data |
---|---|---|
79e53945 | 1 | /* |
39507259 | 2 | * Copyright © 2006 Intel Corporation |
79e53945 JB |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
b30581a4 | 27 | |
da68386d | 28 | #include <drm/display/drm_dp_helper.h> |
2a64b147 | 29 | #include <drm/display/drm_dsc_helper.h> |
cfc10489 | 30 | #include <drm/drm_edid.h> |
379bc100 | 31 | |
79e53945 | 32 | #include "i915_drv.h" |
ce2fce25 | 33 | #include "i915_reg.h" |
cfc10489 JN |
34 | #include "intel_display.h" |
35 | #include "intel_display_types.h" | |
36 | #include "intel_gmbus.h" | |
72341af4 JN |
37 | |
38 | #define _INTEL_BIOS_PRIVATE | |
39 | #include "intel_vbt_defs.h" | |
79e53945 | 40 | |
dd97950a JN |
41 | /** |
42 | * DOC: Video BIOS Table (VBT) | |
43 | * | |
44 | * The Video BIOS Table, or VBT, provides platform and board specific | |
45 | * configuration information to the driver that is not discoverable or available | |
46 | * through other means. The configuration is mostly related to display | |
47 | * hardware. The VBT is available via the ACPI OpRegion or, on older systems, in | |
48 | * the PCI ROM. | |
49 | * | |
50 | * The VBT consists of a VBT Header (defined as &struct vbt_header), a BDB | |
51 | * Header (&struct bdb_header), and a number of BIOS Data Blocks (BDB) that | |
52 | * contain the actual configuration information. The VBT Header, and thus the | |
53 | * VBT, begins with "$VBT" signature. The VBT Header contains the offset of the | |
54 | * BDB Header. The data blocks are concatenated after the BDB Header. The data | |
55 | * blocks have a 1-byte Block ID, 2-byte Block Size, and Block Size bytes of | |
56 | * data. (Block 53, the MIPI Sequence Block is an exception.) | |
57 | * | |
58 | * The driver parses the VBT during load. The relevant information is stored in | |
59 | * driver private data for ease of use, and the actual VBT is not read after | |
60 | * that. | |
61 | */ | |
62 | ||
0d9ef19b | 63 | /* Wrapper for VBT child device config */ |
3162d057 | 64 | struct intel_bios_encoder_data { |
7371fa34 JN |
65 | struct drm_i915_private *i915; |
66 | ||
0d9ef19b | 67 | struct child_device_config child; |
6e0d46e9 | 68 | struct dsc_compression_parameters_entry *dsc; |
0d9ef19b JN |
69 | struct list_head node; |
70 | }; | |
71 | ||
9b9d172d | 72 | #define SLAVE_ADDR1 0x70 |
73 | #define SLAVE_ADDR2 0x72 | |
79e53945 | 74 | |
08c0888b JN |
75 | /* Get BDB block size given a pointer to Block ID. */ |
76 | static u32 _get_blocksize(const u8 *block_base) | |
77 | { | |
78 | /* The MIPI Sequence Block v3+ has a separate size field. */ | |
79 | if (*block_base == BDB_MIPI_SEQUENCE && *(block_base + 3) >= 3) | |
80 | return *((const u32 *)(block_base + 4)); | |
81 | else | |
82 | return *((const u16 *)(block_base + 1)); | |
83 | } | |
84 | ||
85 | /* Get BDB block size give a pointer to data after Block ID and Block Size. */ | |
86 | static u32 get_blocksize(const void *block_data) | |
87 | { | |
88 | return _get_blocksize(block_data - 3); | |
89 | } | |
90 | ||
e8ef3b4c | 91 | static const void * |
e163cfb4 | 92 | find_raw_section(const void *_bdb, enum bdb_block_id section_id) |
79e53945 | 93 | { |
e8ef3b4c JN |
94 | const struct bdb_header *bdb = _bdb; |
95 | const u8 *base = _bdb; | |
79e53945 | 96 | int index = 0; |
cd67d226 | 97 | u32 total, current_size; |
f41c6153 | 98 | enum bdb_block_id current_id; |
79e53945 JB |
99 | |
100 | /* skip to first section */ | |
101 | index += bdb->header_size; | |
102 | total = bdb->bdb_size; | |
103 | ||
104 | /* walk the sections looking for section_id */ | |
d1f13fd2 | 105 | while (index + 3 < total) { |
79e53945 | 106 | current_id = *(base + index); |
08c0888b JN |
107 | current_size = _get_blocksize(base + index); |
108 | index += 3; | |
cd67d226 | 109 | |
d1f13fd2 CW |
110 | if (index + current_size > total) |
111 | return NULL; | |
112 | ||
79e53945 JB |
113 | if (current_id == section_id) |
114 | return base + index; | |
d1f13fd2 | 115 | |
79e53945 JB |
116 | index += current_size; |
117 | } | |
118 | ||
119 | return NULL; | |
120 | } | |
121 | ||
e163cfb4 VS |
122 | /* |
123 | * Offset from the start of BDB to the start of the | |
124 | * block data (just past the block header). | |
125 | */ | |
39b1bc4b | 126 | static u32 raw_block_offset(const void *bdb, enum bdb_block_id section_id) |
e163cfb4 VS |
127 | { |
128 | const void *block; | |
129 | ||
130 | block = find_raw_section(bdb, section_id); | |
131 | if (!block) | |
132 | return 0; | |
133 | ||
134 | return block - bdb; | |
135 | } | |
136 | ||
137 | struct bdb_block_entry { | |
138 | struct list_head node; | |
139 | enum bdb_block_id section_id; | |
140 | u8 data[]; | |
141 | }; | |
142 | ||
143 | static const void * | |
0a93eeb5 ML |
144 | bdb_find_section(struct drm_i915_private *i915, |
145 | enum bdb_block_id section_id) | |
e163cfb4 VS |
146 | { |
147 | struct bdb_block_entry *entry; | |
148 | ||
a434689c | 149 | list_for_each_entry(entry, &i915->display.vbt.bdb_blocks, node) { |
e163cfb4 VS |
150 | if (entry->section_id == section_id) |
151 | return entry->data + 3; | |
152 | } | |
153 | ||
154 | return NULL; | |
155 | } | |
156 | ||
157 | static const struct { | |
158 | enum bdb_block_id section_id; | |
159 | size_t min_size; | |
160 | } bdb_blocks[] = { | |
161 | { .section_id = BDB_GENERAL_FEATURES, | |
162 | .min_size = sizeof(struct bdb_general_features), }, | |
163 | { .section_id = BDB_GENERAL_DEFINITIONS, | |
164 | .min_size = sizeof(struct bdb_general_definitions), }, | |
165 | { .section_id = BDB_PSR, | |
166 | .min_size = sizeof(struct bdb_psr), }, | |
167 | { .section_id = BDB_DRIVER_FEATURES, | |
168 | .min_size = sizeof(struct bdb_driver_features), }, | |
169 | { .section_id = BDB_SDVO_LVDS_OPTIONS, | |
170 | .min_size = sizeof(struct bdb_sdvo_lvds_options), }, | |
171 | { .section_id = BDB_SDVO_PANEL_DTDS, | |
172 | .min_size = sizeof(struct bdb_sdvo_panel_dtds), }, | |
173 | { .section_id = BDB_EDP, | |
174 | .min_size = sizeof(struct bdb_edp), }, | |
175 | { .section_id = BDB_LVDS_OPTIONS, | |
176 | .min_size = sizeof(struct bdb_lvds_options), }, | |
901a0cad VS |
177 | /* |
178 | * BDB_LVDS_LFP_DATA depends on BDB_LVDS_LFP_DATA_PTRS, | |
179 | * so keep the two ordered. | |
180 | */ | |
e163cfb4 VS |
181 | { .section_id = BDB_LVDS_LFP_DATA_PTRS, |
182 | .min_size = sizeof(struct bdb_lvds_lfp_data_ptrs), }, | |
183 | { .section_id = BDB_LVDS_LFP_DATA, | |
901a0cad | 184 | .min_size = 0, /* special case */ }, |
e163cfb4 VS |
185 | { .section_id = BDB_LVDS_BACKLIGHT, |
186 | .min_size = sizeof(struct bdb_lfp_backlight_data), }, | |
187 | { .section_id = BDB_LFP_POWER, | |
188 | .min_size = sizeof(struct bdb_lfp_power), }, | |
189 | { .section_id = BDB_MIPI_CONFIG, | |
190 | .min_size = sizeof(struct bdb_mipi_config), }, | |
191 | { .section_id = BDB_MIPI_SEQUENCE, | |
192 | .min_size = sizeof(struct bdb_mipi_sequence) }, | |
193 | { .section_id = BDB_COMPRESSION_PARAMETERS, | |
194 | .min_size = sizeof(struct bdb_compression_parameters), }, | |
195 | { .section_id = BDB_GENERIC_DTD, | |
196 | .min_size = sizeof(struct bdb_generic_dtd), }, | |
197 | }; | |
198 | ||
901a0cad VS |
199 | static size_t lfp_data_min_size(struct drm_i915_private *i915) |
200 | { | |
201 | const struct bdb_lvds_lfp_data_ptrs *ptrs; | |
202 | size_t size; | |
203 | ||
0a93eeb5 | 204 | ptrs = bdb_find_section(i915, BDB_LVDS_LFP_DATA_PTRS); |
901a0cad VS |
205 | if (!ptrs) |
206 | return 0; | |
207 | ||
208 | size = sizeof(struct bdb_lvds_lfp_data); | |
209 | if (ptrs->panel_name.table_size) | |
210 | size = max(size, ptrs->panel_name.offset + | |
211 | sizeof(struct bdb_lvds_lfp_data_tail)); | |
212 | ||
213 | return size; | |
214 | } | |
215 | ||
514003e1 VS |
216 | static bool validate_lfp_data_ptrs(const void *bdb, |
217 | const struct bdb_lvds_lfp_data_ptrs *ptrs) | |
218 | { | |
5ab58d69 | 219 | int fp_timing_size, dvo_timing_size, panel_pnp_id_size, panel_name_size; |
514003e1 | 220 | int data_block_size, lfp_data_size; |
4e78d602 | 221 | const void *data_block; |
514003e1 VS |
222 | int i; |
223 | ||
4e78d602 VS |
224 | data_block = find_raw_section(bdb, BDB_LVDS_LFP_DATA); |
225 | if (!data_block) | |
226 | return false; | |
227 | ||
228 | data_block_size = get_blocksize(data_block); | |
514003e1 VS |
229 | if (data_block_size == 0) |
230 | return false; | |
231 | ||
232 | /* always 3 indicating the presence of fp_timing+dvo_timing+panel_pnp_id */ | |
233 | if (ptrs->lvds_entries != 3) | |
234 | return false; | |
235 | ||
236 | fp_timing_size = ptrs->ptr[0].fp_timing.table_size; | |
237 | dvo_timing_size = ptrs->ptr[0].dvo_timing.table_size; | |
238 | panel_pnp_id_size = ptrs->ptr[0].panel_pnp_id.table_size; | |
5ab58d69 | 239 | panel_name_size = ptrs->panel_name.table_size; |
514003e1 VS |
240 | |
241 | /* fp_timing has variable size */ | |
242 | if (fp_timing_size < 32 || | |
243 | dvo_timing_size != sizeof(struct lvds_dvo_timing) || | |
244 | panel_pnp_id_size != sizeof(struct lvds_pnp_id)) | |
245 | return false; | |
246 | ||
5ab58d69 VS |
247 | /* panel_name is not present in old VBTs */ |
248 | if (panel_name_size != 0 && | |
249 | panel_name_size != sizeof(struct lvds_lfp_panel_name)) | |
250 | return false; | |
251 | ||
514003e1 VS |
252 | lfp_data_size = ptrs->ptr[1].fp_timing.offset - ptrs->ptr[0].fp_timing.offset; |
253 | if (16 * lfp_data_size > data_block_size) | |
254 | return false; | |
255 | ||
514003e1 VS |
256 | /* make sure the table entries have uniform size */ |
257 | for (i = 1; i < 16; i++) { | |
258 | if (ptrs->ptr[i].fp_timing.table_size != fp_timing_size || | |
259 | ptrs->ptr[i].dvo_timing.table_size != dvo_timing_size || | |
260 | ptrs->ptr[i].panel_pnp_id.table_size != panel_pnp_id_size) | |
261 | return false; | |
262 | ||
263 | if (ptrs->ptr[i].fp_timing.offset - ptrs->ptr[i-1].fp_timing.offset != lfp_data_size || | |
264 | ptrs->ptr[i].dvo_timing.offset - ptrs->ptr[i-1].dvo_timing.offset != lfp_data_size || | |
265 | ptrs->ptr[i].panel_pnp_id.offset - ptrs->ptr[i-1].panel_pnp_id.offset != lfp_data_size) | |
266 | return false; | |
267 | } | |
268 | ||
4e78d602 VS |
269 | /* |
270 | * Except for vlv/chv machines all real VBTs seem to have 6 | |
271 | * unaccounted bytes in the fp_timing table. And it doesn't | |
272 | * appear to be a really intentional hole as the fp_timing | |
273 | * 0xffff terminator is always within those 6 missing bytes. | |
274 | */ | |
275 | if (fp_timing_size + 6 + dvo_timing_size + panel_pnp_id_size == lfp_data_size) | |
276 | fp_timing_size += 6; | |
277 | ||
278 | if (fp_timing_size + dvo_timing_size + panel_pnp_id_size != lfp_data_size) | |
279 | return false; | |
280 | ||
281 | if (ptrs->ptr[0].fp_timing.offset + fp_timing_size != ptrs->ptr[0].dvo_timing.offset || | |
282 | ptrs->ptr[0].dvo_timing.offset + dvo_timing_size != ptrs->ptr[0].panel_pnp_id.offset || | |
283 | ptrs->ptr[0].panel_pnp_id.offset + panel_pnp_id_size != lfp_data_size) | |
284 | return false; | |
285 | ||
514003e1 VS |
286 | /* make sure the tables fit inside the data block */ |
287 | for (i = 0; i < 16; i++) { | |
288 | if (ptrs->ptr[i].fp_timing.offset + fp_timing_size > data_block_size || | |
289 | ptrs->ptr[i].dvo_timing.offset + dvo_timing_size > data_block_size || | |
290 | ptrs->ptr[i].panel_pnp_id.offset + panel_pnp_id_size > data_block_size) | |
291 | return false; | |
292 | } | |
293 | ||
5ab58d69 VS |
294 | if (ptrs->panel_name.offset + 16 * panel_name_size > data_block_size) |
295 | return false; | |
296 | ||
4e78d602 VS |
297 | /* make sure fp_timing terminators are present at expected locations */ |
298 | for (i = 0; i < 16; i++) { | |
299 | const u16 *t = data_block + ptrs->ptr[i].fp_timing.offset + | |
300 | fp_timing_size - 2; | |
301 | ||
302 | if (*t != 0xffff) | |
303 | return false; | |
304 | } | |
305 | ||
514003e1 VS |
306 | return true; |
307 | } | |
308 | ||
918f3025 VS |
309 | /* make the data table offsets relative to the data block */ |
310 | static bool fixup_lfp_data_ptrs(const void *bdb, void *ptrs_block) | |
311 | { | |
312 | struct bdb_lvds_lfp_data_ptrs *ptrs = ptrs_block; | |
313 | u32 offset; | |
314 | int i; | |
315 | ||
39b1bc4b | 316 | offset = raw_block_offset(bdb, BDB_LVDS_LFP_DATA); |
918f3025 VS |
317 | |
318 | for (i = 0; i < 16; i++) { | |
319 | if (ptrs->ptr[i].fp_timing.offset < offset || | |
320 | ptrs->ptr[i].dvo_timing.offset < offset || | |
321 | ptrs->ptr[i].panel_pnp_id.offset < offset) | |
322 | return false; | |
323 | ||
324 | ptrs->ptr[i].fp_timing.offset -= offset; | |
325 | ptrs->ptr[i].dvo_timing.offset -= offset; | |
326 | ptrs->ptr[i].panel_pnp_id.offset -= offset; | |
327 | } | |
328 | ||
5ab58d69 VS |
329 | if (ptrs->panel_name.table_size) { |
330 | if (ptrs->panel_name.offset < offset) | |
331 | return false; | |
332 | ||
333 | ptrs->panel_name.offset -= offset; | |
334 | } | |
335 | ||
514003e1 | 336 | return validate_lfp_data_ptrs(bdb, ptrs); |
918f3025 VS |
337 | } |
338 | ||
a87d0a84 VS |
339 | static int make_lfp_data_ptr(struct lvds_lfp_data_ptr_table *table, |
340 | int table_size, int total_size) | |
341 | { | |
342 | if (total_size < table_size) | |
343 | return total_size; | |
344 | ||
345 | table->table_size = table_size; | |
346 | table->offset = total_size - table_size; | |
347 | ||
348 | return total_size - table_size; | |
349 | } | |
350 | ||
351 | static void next_lfp_data_ptr(struct lvds_lfp_data_ptr_table *next, | |
352 | const struct lvds_lfp_data_ptr_table *prev, | |
353 | int size) | |
354 | { | |
355 | next->table_size = prev->table_size; | |
356 | next->offset = prev->offset + size; | |
357 | } | |
358 | ||
359 | static void *generate_lfp_data_ptrs(struct drm_i915_private *i915, | |
360 | const void *bdb) | |
361 | { | |
d3a70518 | 362 | int i, size, table_size, block_size, offset, fp_timing_size; |
a87d0a84 | 363 | struct bdb_lvds_lfp_data_ptrs *ptrs; |
d3a70518 | 364 | const void *block; |
a87d0a84 VS |
365 | void *ptrs_block; |
366 | ||
d3a70518 VS |
367 | /* |
368 | * The hardcoded fp_timing_size is only valid for | |
369 | * modernish VBTs. All older VBTs definitely should | |
370 | * include block 41 and thus we don't need to | |
371 | * generate one. | |
372 | */ | |
373 | if (i915->display.vbt.version < 155) | |
374 | return NULL; | |
375 | ||
376 | fp_timing_size = 38; | |
377 | ||
a87d0a84 VS |
378 | block = find_raw_section(bdb, BDB_LVDS_LFP_DATA); |
379 | if (!block) | |
380 | return NULL; | |
381 | ||
382 | drm_dbg_kms(&i915->drm, "Generating LFP data table pointers\n"); | |
383 | ||
384 | block_size = get_blocksize(block); | |
385 | ||
d3a70518 VS |
386 | size = fp_timing_size + sizeof(struct lvds_dvo_timing) + |
387 | sizeof(struct lvds_pnp_id); | |
a87d0a84 VS |
388 | if (size * 16 > block_size) |
389 | return NULL; | |
390 | ||
391 | ptrs_block = kzalloc(sizeof(*ptrs) + 3, GFP_KERNEL); | |
392 | if (!ptrs_block) | |
393 | return NULL; | |
394 | ||
395 | *(u8 *)(ptrs_block + 0) = BDB_LVDS_LFP_DATA_PTRS; | |
396 | *(u16 *)(ptrs_block + 1) = sizeof(*ptrs); | |
397 | ptrs = ptrs_block + 3; | |
398 | ||
399 | table_size = sizeof(struct lvds_pnp_id); | |
400 | size = make_lfp_data_ptr(&ptrs->ptr[0].panel_pnp_id, table_size, size); | |
401 | ||
402 | table_size = sizeof(struct lvds_dvo_timing); | |
403 | size = make_lfp_data_ptr(&ptrs->ptr[0].dvo_timing, table_size, size); | |
404 | ||
d3a70518 | 405 | table_size = fp_timing_size; |
a87d0a84 VS |
406 | size = make_lfp_data_ptr(&ptrs->ptr[0].fp_timing, table_size, size); |
407 | ||
408 | if (ptrs->ptr[0].fp_timing.table_size) | |
409 | ptrs->lvds_entries++; | |
410 | if (ptrs->ptr[0].dvo_timing.table_size) | |
411 | ptrs->lvds_entries++; | |
412 | if (ptrs->ptr[0].panel_pnp_id.table_size) | |
413 | ptrs->lvds_entries++; | |
414 | ||
415 | if (size != 0 || ptrs->lvds_entries != 3) { | |
7674cd0b | 416 | kfree(ptrs_block); |
a87d0a84 VS |
417 | return NULL; |
418 | } | |
419 | ||
d3a70518 VS |
420 | size = fp_timing_size + sizeof(struct lvds_dvo_timing) + |
421 | sizeof(struct lvds_pnp_id); | |
a87d0a84 VS |
422 | for (i = 1; i < 16; i++) { |
423 | next_lfp_data_ptr(&ptrs->ptr[i].fp_timing, &ptrs->ptr[i-1].fp_timing, size); | |
424 | next_lfp_data_ptr(&ptrs->ptr[i].dvo_timing, &ptrs->ptr[i-1].dvo_timing, size); | |
425 | next_lfp_data_ptr(&ptrs->ptr[i].panel_pnp_id, &ptrs->ptr[i-1].panel_pnp_id, size); | |
426 | } | |
427 | ||
a87d0a84 VS |
428 | table_size = sizeof(struct lvds_lfp_panel_name); |
429 | ||
430 | if (16 * (size + table_size) <= block_size) { | |
431 | ptrs->panel_name.table_size = table_size; | |
432 | ptrs->panel_name.offset = size * 16; | |
433 | } | |
434 | ||
435 | offset = block - bdb; | |
436 | ||
437 | for (i = 0; i < 16; i++) { | |
438 | ptrs->ptr[i].fp_timing.offset += offset; | |
439 | ptrs->ptr[i].dvo_timing.offset += offset; | |
440 | ptrs->ptr[i].panel_pnp_id.offset += offset; | |
441 | } | |
442 | ||
443 | if (ptrs->panel_name.table_size) | |
444 | ptrs->panel_name.offset += offset; | |
445 | ||
446 | return ptrs_block; | |
447 | } | |
448 | ||
e163cfb4 VS |
449 | static void |
450 | init_bdb_block(struct drm_i915_private *i915, | |
451 | const void *bdb, enum bdb_block_id section_id, | |
452 | size_t min_size) | |
453 | { | |
454 | struct bdb_block_entry *entry; | |
a87d0a84 | 455 | void *temp_block = NULL; |
e163cfb4 VS |
456 | const void *block; |
457 | size_t block_size; | |
458 | ||
459 | block = find_raw_section(bdb, section_id); | |
a87d0a84 VS |
460 | |
461 | /* Modern VBTs lack the LFP data table pointers block, make one up */ | |
462 | if (!block && section_id == BDB_LVDS_LFP_DATA_PTRS) { | |
463 | temp_block = generate_lfp_data_ptrs(i915, bdb); | |
464 | if (temp_block) | |
465 | block = temp_block + 3; | |
466 | } | |
e163cfb4 VS |
467 | if (!block) |
468 | return; | |
469 | ||
470 | drm_WARN(&i915->drm, min_size == 0, | |
471 | "Block %d min_size is zero\n", section_id); | |
472 | ||
473 | block_size = get_blocksize(block); | |
474 | ||
a06289f3 VS |
475 | /* |
476 | * Version number and new block size are considered | |
477 | * part of the header for MIPI sequenece block v3+. | |
478 | */ | |
479 | if (section_id == BDB_MIPI_SEQUENCE && *(const u8 *)block >= 3) | |
480 | block_size += 5; | |
481 | ||
e163cfb4 VS |
482 | entry = kzalloc(struct_size(entry, data, max(min_size, block_size) + 3), |
483 | GFP_KERNEL); | |
a87d0a84 VS |
484 | if (!entry) { |
485 | kfree(temp_block); | |
e163cfb4 | 486 | return; |
a87d0a84 | 487 | } |
e163cfb4 VS |
488 | |
489 | entry->section_id = section_id; | |
490 | memcpy(entry->data, block - 3, block_size + 3); | |
491 | ||
a87d0a84 VS |
492 | kfree(temp_block); |
493 | ||
e163cfb4 VS |
494 | drm_dbg_kms(&i915->drm, "Found BDB block %d (size %zu, min size %zu)\n", |
495 | section_id, block_size, min_size); | |
496 | ||
918f3025 VS |
497 | if (section_id == BDB_LVDS_LFP_DATA_PTRS && |
498 | !fixup_lfp_data_ptrs(bdb, entry->data + 3)) { | |
499 | drm_err(&i915->drm, "VBT has malformed LFP data table pointers\n"); | |
500 | kfree(entry); | |
501 | return; | |
502 | } | |
503 | ||
a434689c | 504 | list_add_tail(&entry->node, &i915->display.vbt.bdb_blocks); |
e163cfb4 VS |
505 | } |
506 | ||
507 | static void init_bdb_blocks(struct drm_i915_private *i915, | |
508 | const void *bdb) | |
509 | { | |
510 | int i; | |
511 | ||
512 | for (i = 0; i < ARRAY_SIZE(bdb_blocks); i++) { | |
513 | enum bdb_block_id section_id = bdb_blocks[i].section_id; | |
514 | size_t min_size = bdb_blocks[i].min_size; | |
515 | ||
901a0cad VS |
516 | if (section_id == BDB_LVDS_LFP_DATA) |
517 | min_size = lfp_data_min_size(i915); | |
518 | ||
e163cfb4 VS |
519 | init_bdb_block(i915, bdb, section_id, min_size); |
520 | } | |
521 | } | |
522 | ||
79e53945 | 523 | static void |
bb6f53d4 VS |
524 | fill_detail_timing_data(struct drm_i915_private *i915, |
525 | struct drm_display_mode *panel_fixed_mode, | |
99834ea4 | 526 | const struct lvds_dvo_timing *dvo_timing) |
88631706 ML |
527 | { |
528 | panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) | | |
529 | dvo_timing->hactive_lo; | |
530 | panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay + | |
531 | ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo); | |
532 | panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start + | |
ce2e87b4 VT |
533 | ((dvo_timing->hsync_pulse_width_hi << 8) | |
534 | dvo_timing->hsync_pulse_width_lo); | |
88631706 ML |
535 | panel_fixed_mode->htotal = panel_fixed_mode->hdisplay + |
536 | ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo); | |
537 | ||
538 | panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) | | |
539 | dvo_timing->vactive_lo; | |
540 | panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay + | |
ce2e87b4 | 541 | ((dvo_timing->vsync_off_hi << 4) | dvo_timing->vsync_off_lo); |
88631706 | 542 | panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start + |
ce2e87b4 VT |
543 | ((dvo_timing->vsync_pulse_width_hi << 4) | |
544 | dvo_timing->vsync_pulse_width_lo); | |
88631706 ML |
545 | panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay + |
546 | ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo); | |
547 | panel_fixed_mode->clock = dvo_timing->clock * 10; | |
548 | panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED; | |
549 | ||
9bc35499 AJ |
550 | if (dvo_timing->hsync_positive) |
551 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
552 | else | |
553 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
554 | ||
555 | if (dvo_timing->vsync_positive) | |
556 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
557 | else | |
558 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
559 | ||
df457245 VS |
560 | panel_fixed_mode->width_mm = (dvo_timing->himage_hi << 8) | |
561 | dvo_timing->himage_lo; | |
562 | panel_fixed_mode->height_mm = (dvo_timing->vimage_hi << 8) | | |
563 | dvo_timing->vimage_lo; | |
564 | ||
bb6f53d4 VS |
565 | /* Some VBTs have bogus h/vsync_end values */ |
566 | if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) { | |
567 | drm_dbg_kms(&i915->drm, "reducing hsync_end %d->%d\n", | |
568 | panel_fixed_mode->hsync_end, panel_fixed_mode->htotal); | |
569 | panel_fixed_mode->hsync_end = panel_fixed_mode->htotal; | |
570 | } | |
571 | if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal) { | |
572 | drm_dbg_kms(&i915->drm, "reducing vsync_end %d->%d\n", | |
573 | panel_fixed_mode->vsync_end, panel_fixed_mode->vtotal); | |
574 | panel_fixed_mode->vsync_end = panel_fixed_mode->vtotal; | |
575 | } | |
88631706 ML |
576 | |
577 | drm_mode_set_name(panel_fixed_mode); | |
578 | } | |
579 | ||
99834ea4 | 580 | static const struct lvds_dvo_timing * |
58b2e382 VS |
581 | get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *data, |
582 | const struct bdb_lvds_lfp_data_ptrs *ptrs, | |
99834ea4 CW |
583 | int index) |
584 | { | |
58b2e382 | 585 | return (const void *)data + ptrs->ptr[index].dvo_timing.offset; |
99834ea4 CW |
586 | } |
587 | ||
b0354385 | 588 | static const struct lvds_fp_timing * |
918f3025 | 589 | get_lvds_fp_timing(const struct bdb_lvds_lfp_data *data, |
b0354385 TI |
590 | const struct bdb_lvds_lfp_data_ptrs *ptrs, |
591 | int index) | |
592 | { | |
58b2e382 | 593 | return (const void *)data + ptrs->ptr[index].fp_timing.offset; |
b0354385 TI |
594 | } |
595 | ||
c518a775 VS |
596 | static const struct lvds_pnp_id * |
597 | get_lvds_pnp_id(const struct bdb_lvds_lfp_data *data, | |
598 | const struct bdb_lvds_lfp_data_ptrs *ptrs, | |
599 | int index) | |
600 | { | |
601 | return (const void *)data + ptrs->ptr[index].panel_pnp_id.offset; | |
602 | } | |
603 | ||
901a0cad VS |
604 | static const struct bdb_lvds_lfp_data_tail * |
605 | get_lfp_data_tail(const struct bdb_lvds_lfp_data *data, | |
606 | const struct bdb_lvds_lfp_data_ptrs *ptrs) | |
607 | { | |
608 | if (ptrs->panel_name.table_size) | |
609 | return (const void *)data + ptrs->panel_name.offset; | |
610 | else | |
611 | return NULL; | |
612 | } | |
613 | ||
06bfa86e VS |
614 | static void dump_pnp_id(struct drm_i915_private *i915, |
615 | const struct lvds_pnp_id *pnp_id, | |
616 | const char *name) | |
617 | { | |
618 | u16 mfg_name = be16_to_cpu((__force __be16)pnp_id->mfg_name); | |
619 | char vend[4]; | |
620 | ||
621 | drm_dbg_kms(&i915->drm, "%s PNPID mfg: %s (0x%x), prod: %u, serial: %u, week: %d, year: %d\n", | |
622 | name, drm_edid_decode_mfg_id(mfg_name, vend), | |
623 | pnp_id->mfg_name, pnp_id->product_code, pnp_id->serial, | |
624 | pnp_id->mfg_week, pnp_id->mfg_year + 1990); | |
625 | } | |
626 | ||
c518a775 | 627 | static int opregion_get_panel_type(struct drm_i915_private *i915, |
6434cf63 | 628 | const struct intel_bios_encoder_data *devdata, |
c36225a1 | 629 | const struct drm_edid *drm_edid, bool use_fallback) |
cc589f2d VS |
630 | { |
631 | return intel_opregion_get_panel_type(i915); | |
632 | } | |
633 | ||
c518a775 | 634 | static int vbt_get_panel_type(struct drm_i915_private *i915, |
6434cf63 | 635 | const struct intel_bios_encoder_data *devdata, |
c36225a1 | 636 | const struct drm_edid *drm_edid, bool use_fallback) |
719f4c51 VS |
637 | { |
638 | const struct bdb_lvds_options *lvds_options; | |
639 | ||
0a93eeb5 | 640 | lvds_options = bdb_find_section(i915, BDB_LVDS_OPTIONS); |
719f4c51 VS |
641 | if (!lvds_options) |
642 | return -1; | |
643 | ||
c518a775 VS |
644 | if (lvds_options->panel_type > 0xf && |
645 | lvds_options->panel_type != 0xff) { | |
719f4c51 VS |
646 | drm_dbg_kms(&i915->drm, "Invalid VBT panel type 0x%x\n", |
647 | lvds_options->panel_type); | |
648 | return -1; | |
649 | } | |
650 | ||
6434cf63 AM |
651 | if (devdata && devdata->child.handle == DEVICE_HANDLE_LFP2) |
652 | return lvds_options->panel_type2; | |
653 | ||
654 | drm_WARN_ON(&i915->drm, devdata && devdata->child.handle != DEVICE_HANDLE_LFP1); | |
655 | ||
719f4c51 VS |
656 | return lvds_options->panel_type; |
657 | } | |
658 | ||
c518a775 | 659 | static int pnpid_get_panel_type(struct drm_i915_private *i915, |
6434cf63 | 660 | const struct intel_bios_encoder_data *devdata, |
c36225a1 | 661 | const struct drm_edid *drm_edid, bool use_fallback) |
c518a775 VS |
662 | { |
663 | const struct bdb_lvds_lfp_data *data; | |
664 | const struct bdb_lvds_lfp_data_ptrs *ptrs; | |
665 | const struct lvds_pnp_id *edid_id; | |
666 | struct lvds_pnp_id edid_id_nodate; | |
c36225a1 | 667 | const struct edid *edid = drm_edid_raw(drm_edid); /* FIXME */ |
c518a775 VS |
668 | int i, best = -1; |
669 | ||
670 | if (!edid) | |
671 | return -1; | |
672 | ||
673 | edid_id = (const void *)&edid->mfg_id[0]; | |
674 | ||
675 | edid_id_nodate = *edid_id; | |
676 | edid_id_nodate.mfg_week = 0; | |
677 | edid_id_nodate.mfg_year = 0; | |
678 | ||
06bfa86e VS |
679 | dump_pnp_id(i915, edid_id, "EDID"); |
680 | ||
0a93eeb5 | 681 | ptrs = bdb_find_section(i915, BDB_LVDS_LFP_DATA_PTRS); |
c518a775 VS |
682 | if (!ptrs) |
683 | return -1; | |
684 | ||
0a93eeb5 | 685 | data = bdb_find_section(i915, BDB_LVDS_LFP_DATA); |
c518a775 VS |
686 | if (!data) |
687 | return -1; | |
688 | ||
689 | for (i = 0; i < 16; i++) { | |
690 | const struct lvds_pnp_id *vbt_id = | |
691 | get_lvds_pnp_id(data, ptrs, i); | |
692 | ||
693 | /* full match? */ | |
694 | if (!memcmp(vbt_id, edid_id, sizeof(*vbt_id))) | |
695 | return i; | |
696 | ||
697 | /* | |
698 | * Accept a match w/o date if no full match is found, | |
699 | * and the VBT entry does not specify a date. | |
700 | */ | |
701 | if (best < 0 && | |
702 | !memcmp(vbt_id, &edid_id_nodate, sizeof(*vbt_id))) | |
703 | best = i; | |
704 | } | |
705 | ||
706 | return best; | |
707 | } | |
708 | ||
709 | static int fallback_get_panel_type(struct drm_i915_private *i915, | |
6434cf63 | 710 | const struct intel_bios_encoder_data *devdata, |
c36225a1 | 711 | const struct drm_edid *drm_edid, bool use_fallback) |
cc589f2d | 712 | { |
3f9ffce5 | 713 | return use_fallback ? 0 : -1; |
cc589f2d VS |
714 | } |
715 | ||
716 | enum panel_type { | |
717 | PANEL_TYPE_OPREGION, | |
718 | PANEL_TYPE_VBT, | |
c518a775 | 719 | PANEL_TYPE_PNPID, |
cc589f2d VS |
720 | PANEL_TYPE_FALLBACK, |
721 | }; | |
722 | ||
c518a775 | 723 | static int get_panel_type(struct drm_i915_private *i915, |
6434cf63 | 724 | const struct intel_bios_encoder_data *devdata, |
c36225a1 | 725 | const struct drm_edid *drm_edid, bool use_fallback) |
719f4c51 | 726 | { |
cc589f2d VS |
727 | struct { |
728 | const char *name; | |
c518a775 | 729 | int (*get_panel_type)(struct drm_i915_private *i915, |
6434cf63 | 730 | const struct intel_bios_encoder_data *devdata, |
c36225a1 | 731 | const struct drm_edid *drm_edid, bool use_fallback); |
cc589f2d VS |
732 | int panel_type; |
733 | } panel_types[] = { | |
734 | [PANEL_TYPE_OPREGION] = { | |
735 | .name = "OpRegion", | |
736 | .get_panel_type = opregion_get_panel_type, | |
737 | }, | |
738 | [PANEL_TYPE_VBT] = { | |
739 | .name = "VBT", | |
740 | .get_panel_type = vbt_get_panel_type, | |
741 | }, | |
c518a775 VS |
742 | [PANEL_TYPE_PNPID] = { |
743 | .name = "PNPID", | |
744 | .get_panel_type = pnpid_get_panel_type, | |
745 | }, | |
cc589f2d VS |
746 | [PANEL_TYPE_FALLBACK] = { |
747 | .name = "fallback", | |
748 | .get_panel_type = fallback_get_panel_type, | |
749 | }, | |
750 | }; | |
751 | int i; | |
719f4c51 | 752 | |
cc589f2d | 753 | for (i = 0; i < ARRAY_SIZE(panel_types); i++) { |
3f9ffce5 | 754 | panel_types[i].panel_type = panel_types[i].get_panel_type(i915, devdata, |
c36225a1 | 755 | drm_edid, use_fallback); |
cc589f2d | 756 | |
c518a775 VS |
757 | drm_WARN_ON(&i915->drm, panel_types[i].panel_type > 0xf && |
758 | panel_types[i].panel_type != 0xff); | |
719f4c51 | 759 | |
cc589f2d VS |
760 | if (panel_types[i].panel_type >= 0) |
761 | drm_dbg_kms(&i915->drm, "Panel type (%s): %d\n", | |
762 | panel_types[i].name, panel_types[i].panel_type); | |
719f4c51 VS |
763 | } |
764 | ||
cc589f2d VS |
765 | if (panel_types[PANEL_TYPE_OPREGION].panel_type >= 0) |
766 | i = PANEL_TYPE_OPREGION; | |
c518a775 VS |
767 | else if (panel_types[PANEL_TYPE_VBT].panel_type == 0xff && |
768 | panel_types[PANEL_TYPE_PNPID].panel_type >= 0) | |
769 | i = PANEL_TYPE_PNPID; | |
770 | else if (panel_types[PANEL_TYPE_VBT].panel_type != 0xff && | |
771 | panel_types[PANEL_TYPE_VBT].panel_type >= 0) | |
cc589f2d VS |
772 | i = PANEL_TYPE_VBT; |
773 | else | |
774 | i = PANEL_TYPE_FALLBACK; | |
775 | ||
776 | drm_dbg_kms(&i915->drm, "Selected panel type (%s): %d\n", | |
777 | panel_types[i].name, panel_types[i].panel_type); | |
778 | ||
779 | return panel_types[i].panel_type; | |
719f4c51 VS |
780 | } |
781 | ||
a50cc495 VS |
782 | static unsigned int panel_bits(unsigned int value, int panel_type, int num_bits) |
783 | { | |
784 | return (value >> (panel_type * num_bits)) & (BIT(num_bits) - 1); | |
785 | } | |
786 | ||
787 | static bool panel_bool(unsigned int value, int panel_type) | |
788 | { | |
789 | return panel_bits(value, panel_type, 1); | |
790 | } | |
791 | ||
9e7ecedf | 792 | /* Parse general panel options */ |
88631706 | 793 | static void |
3cf05076 | 794 | parse_panel_options(struct drm_i915_private *i915, |
0256ea13 | 795 | struct intel_panel *panel) |
79e53945 | 796 | { |
99834ea4 | 797 | const struct bdb_lvds_options *lvds_options; |
0256ea13 | 798 | int panel_type = panel->vbt.panel_type; |
c329a4ec | 799 | int drrs_mode; |
79e53945 | 800 | |
0a93eeb5 | 801 | lvds_options = bdb_find_section(i915, BDB_LVDS_OPTIONS); |
79e53945 JB |
802 | if (!lvds_options) |
803 | return; | |
804 | ||
3cf05076 | 805 | panel->vbt.lvds_dither = lvds_options->pixel_dither; |
6a04002b | 806 | |
5c9016b2 VS |
807 | /* |
808 | * Empirical evidence indicates the block size can be | |
809 | * either 4,14,16,24+ bytes. For older VBTs no clear | |
810 | * relationship between the block size vs. BDB version. | |
811 | */ | |
812 | if (get_blocksize(lvds_options) < 16) | |
813 | return; | |
79e53945 | 814 | |
a50cc495 VS |
815 | drrs_mode = panel_bits(lvds_options->dps_panel_type_bits, |
816 | panel_type, 2); | |
83a7280e PB |
817 | /* |
818 | * VBT has static DRRS = 0 and seamless DRRS = 2. | |
819 | * The below piece of code is required to adjust vbt.drrs_type | |
820 | * to match the enum drrs_support_type. | |
821 | */ | |
822 | switch (drrs_mode) { | |
823 | case 0: | |
3cf05076 | 824 | panel->vbt.drrs_type = DRRS_TYPE_STATIC; |
dbd440d8 | 825 | drm_dbg_kms(&i915->drm, "DRRS supported mode is static\n"); |
83a7280e PB |
826 | break; |
827 | case 2: | |
3cf05076 | 828 | panel->vbt.drrs_type = DRRS_TYPE_SEAMLESS; |
dbd440d8 | 829 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 830 | "DRRS supported mode is seamless\n"); |
83a7280e PB |
831 | break; |
832 | default: | |
3cf05076 | 833 | panel->vbt.drrs_type = DRRS_TYPE_NONE; |
dbd440d8 | 834 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 835 | "DRRS not supported (VBT input)\n"); |
83a7280e PB |
836 | break; |
837 | } | |
9e7ecedf MR |
838 | } |
839 | ||
9e7ecedf | 840 | static void |
13367132 | 841 | parse_lfp_panel_dtd(struct drm_i915_private *i915, |
3cf05076 | 842 | struct intel_panel *panel, |
13367132 VS |
843 | const struct bdb_lvds_lfp_data *lvds_lfp_data, |
844 | const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs) | |
9e7ecedf | 845 | { |
9e7ecedf MR |
846 | const struct lvds_dvo_timing *panel_dvo_timing; |
847 | const struct lvds_fp_timing *fp_timing; | |
848 | struct drm_display_mode *panel_fixed_mode; | |
3cf05076 | 849 | int panel_type = panel->vbt.panel_type; |
83a7280e | 850 | |
99834ea4 CW |
851 | panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data, |
852 | lvds_lfp_data_ptrs, | |
3e845c7a | 853 | panel_type); |
79e53945 | 854 | |
9a298b2a | 855 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); |
6edc3242 CW |
856 | if (!panel_fixed_mode) |
857 | return; | |
79e53945 | 858 | |
bb6f53d4 | 859 | fill_detail_timing_data(i915, panel_fixed_mode, panel_dvo_timing); |
79e53945 | 860 | |
3cf05076 | 861 | panel->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; |
79e53945 | 862 | |
dbd440d8 | 863 | drm_dbg_kms(&i915->drm, |
f01bae2d VS |
864 | "Found panel mode in BIOS VBT legacy lfp table: " DRM_MODE_FMT "\n", |
865 | DRM_MODE_ARG(panel_fixed_mode)); | |
37df9673 | 866 | |
918f3025 | 867 | fp_timing = get_lvds_fp_timing(lvds_lfp_data, |
b0354385 | 868 | lvds_lfp_data_ptrs, |
3e845c7a | 869 | panel_type); |
58b2e382 VS |
870 | |
871 | /* check the resolution, just to be sure */ | |
872 | if (fp_timing->x_res == panel_fixed_mode->hdisplay && | |
873 | fp_timing->y_res == panel_fixed_mode->vdisplay) { | |
3cf05076 | 874 | panel->vbt.bios_lvds_val = fp_timing->lvds_reg_val; |
58b2e382 VS |
875 | drm_dbg_kms(&i915->drm, |
876 | "VBT initial LVDS value %x\n", | |
3cf05076 | 877 | panel->vbt.bios_lvds_val); |
b0354385 | 878 | } |
88631706 ML |
879 | } |
880 | ||
13367132 | 881 | static void |
3cf05076 VS |
882 | parse_lfp_data(struct drm_i915_private *i915, |
883 | struct intel_panel *panel) | |
13367132 VS |
884 | { |
885 | const struct bdb_lvds_lfp_data *data; | |
901a0cad | 886 | const struct bdb_lvds_lfp_data_tail *tail; |
13367132 | 887 | const struct bdb_lvds_lfp_data_ptrs *ptrs; |
06bfa86e | 888 | const struct lvds_pnp_id *pnp_id; |
3cf05076 | 889 | int panel_type = panel->vbt.panel_type; |
13367132 | 890 | |
0a93eeb5 | 891 | ptrs = bdb_find_section(i915, BDB_LVDS_LFP_DATA_PTRS); |
13367132 VS |
892 | if (!ptrs) |
893 | return; | |
894 | ||
0a93eeb5 | 895 | data = bdb_find_section(i915, BDB_LVDS_LFP_DATA); |
13367132 VS |
896 | if (!data) |
897 | return; | |
898 | ||
3cf05076 VS |
899 | if (!panel->vbt.lfp_lvds_vbt_mode) |
900 | parse_lfp_panel_dtd(i915, panel, data, ptrs); | |
901a0cad | 901 | |
06bfa86e VS |
902 | pnp_id = get_lvds_pnp_id(data, ptrs, panel_type); |
903 | dump_pnp_id(i915, pnp_id, "Panel"); | |
904 | ||
901a0cad VS |
905 | tail = get_lfp_data_tail(data, ptrs); |
906 | if (!tail) | |
907 | return; | |
908 | ||
06bfa86e VS |
909 | drm_dbg_kms(&i915->drm, "Panel name: %.*s\n", |
910 | (int)sizeof(tail->panel_name[0].name), | |
911 | tail->panel_name[panel_type].name); | |
912 | ||
a434689c | 913 | if (i915->display.vbt.version >= 188) { |
3cf05076 | 914 | panel->vbt.seamless_drrs_min_refresh_rate = |
790b45f1 VS |
915 | tail->seamless_drrs_min_refresh_rate[panel_type]; |
916 | drm_dbg_kms(&i915->drm, | |
917 | "Seamless DRRS min refresh rate: %d Hz\n", | |
3cf05076 | 918 | panel->vbt.seamless_drrs_min_refresh_rate); |
790b45f1 | 919 | } |
13367132 VS |
920 | } |
921 | ||
33ef6d4f | 922 | static void |
3cf05076 VS |
923 | parse_generic_dtd(struct drm_i915_private *i915, |
924 | struct intel_panel *panel) | |
33ef6d4f MR |
925 | { |
926 | const struct bdb_generic_dtd *generic_dtd; | |
927 | const struct generic_dtd_entry *dtd; | |
928 | struct drm_display_mode *panel_fixed_mode; | |
929 | int num_dtd; | |
930 | ||
13367132 VS |
931 | /* |
932 | * Older VBTs provided DTD information for internal displays through | |
933 | * the "LFP panel tables" block (42). As of VBT revision 229 the | |
934 | * DTD information should be provided via a newer "generic DTD" | |
935 | * block (58). Just to be safe, we'll try the new generic DTD block | |
936 | * first on VBT >= 229, but still fall back to trying the old LFP | |
937 | * block if that fails. | |
938 | */ | |
a434689c | 939 | if (i915->display.vbt.version < 229) |
13367132 VS |
940 | return; |
941 | ||
0a93eeb5 | 942 | generic_dtd = bdb_find_section(i915, BDB_GENERIC_DTD); |
33ef6d4f MR |
943 | if (!generic_dtd) |
944 | return; | |
945 | ||
946 | if (generic_dtd->gdtd_size < sizeof(struct generic_dtd_entry)) { | |
dbd440d8 | 947 | drm_err(&i915->drm, "GDTD size %u is too small.\n", |
e92cbf38 | 948 | generic_dtd->gdtd_size); |
33ef6d4f MR |
949 | return; |
950 | } else if (generic_dtd->gdtd_size != | |
951 | sizeof(struct generic_dtd_entry)) { | |
dbd440d8 | 952 | drm_err(&i915->drm, "Unexpected GDTD size %u\n", |
e92cbf38 | 953 | generic_dtd->gdtd_size); |
33ef6d4f MR |
954 | /* DTD has unknown fields, but keep going */ |
955 | } | |
956 | ||
957 | num_dtd = (get_blocksize(generic_dtd) - | |
958 | sizeof(struct bdb_generic_dtd)) / generic_dtd->gdtd_size; | |
3cf05076 | 959 | if (panel->vbt.panel_type >= num_dtd) { |
dbd440d8 | 960 | drm_err(&i915->drm, |
e92cbf38 | 961 | "Panel type %d not found in table of %d DTD's\n", |
3cf05076 | 962 | panel->vbt.panel_type, num_dtd); |
33ef6d4f MR |
963 | return; |
964 | } | |
965 | ||
3cf05076 | 966 | dtd = &generic_dtd->dtd[panel->vbt.panel_type]; |
33ef6d4f MR |
967 | |
968 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); | |
969 | if (!panel_fixed_mode) | |
970 | return; | |
971 | ||
972 | panel_fixed_mode->hdisplay = dtd->hactive; | |
973 | panel_fixed_mode->hsync_start = | |
974 | panel_fixed_mode->hdisplay + dtd->hfront_porch; | |
975 | panel_fixed_mode->hsync_end = | |
976 | panel_fixed_mode->hsync_start + dtd->hsync; | |
ad278f35 VK |
977 | panel_fixed_mode->htotal = |
978 | panel_fixed_mode->hdisplay + dtd->hblank; | |
33ef6d4f MR |
979 | |
980 | panel_fixed_mode->vdisplay = dtd->vactive; | |
981 | panel_fixed_mode->vsync_start = | |
982 | panel_fixed_mode->vdisplay + dtd->vfront_porch; | |
983 | panel_fixed_mode->vsync_end = | |
984 | panel_fixed_mode->vsync_start + dtd->vsync; | |
ad278f35 VK |
985 | panel_fixed_mode->vtotal = |
986 | panel_fixed_mode->vdisplay + dtd->vblank; | |
33ef6d4f MR |
987 | |
988 | panel_fixed_mode->clock = dtd->pixel_clock; | |
989 | panel_fixed_mode->width_mm = dtd->width_mm; | |
990 | panel_fixed_mode->height_mm = dtd->height_mm; | |
991 | ||
992 | panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED; | |
993 | drm_mode_set_name(panel_fixed_mode); | |
994 | ||
995 | if (dtd->hsync_positive_polarity) | |
996 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
997 | else | |
998 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
999 | ||
1000 | if (dtd->vsync_positive_polarity) | |
1001 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
1002 | else | |
1003 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
1004 | ||
dbd440d8 | 1005 | drm_dbg_kms(&i915->drm, |
f01bae2d VS |
1006 | "Found panel mode in BIOS VBT generic dtd table: " DRM_MODE_FMT "\n", |
1007 | DRM_MODE_ARG(panel_fixed_mode)); | |
33ef6d4f | 1008 | |
3cf05076 | 1009 | panel->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; |
33ef6d4f MR |
1010 | } |
1011 | ||
f00076d2 | 1012 | static void |
3cf05076 VS |
1013 | parse_lfp_backlight(struct drm_i915_private *i915, |
1014 | struct intel_panel *panel) | |
f00076d2 JN |
1015 | { |
1016 | const struct bdb_lfp_backlight_data *backlight_data; | |
f87f6599 | 1017 | const struct lfp_backlight_data_entry *entry; |
3cf05076 | 1018 | int panel_type = panel->vbt.panel_type; |
d381baad | 1019 | u16 level; |
f00076d2 | 1020 | |
0a93eeb5 | 1021 | backlight_data = bdb_find_section(i915, BDB_LVDS_BACKLIGHT); |
f00076d2 JN |
1022 | if (!backlight_data) |
1023 | return; | |
1024 | ||
1025 | if (backlight_data->entry_size != sizeof(backlight_data->data[0])) { | |
dbd440d8 | 1026 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1027 | "Unsupported backlight data entry size %u\n", |
1028 | backlight_data->entry_size); | |
f00076d2 JN |
1029 | return; |
1030 | } | |
1031 | ||
1032 | entry = &backlight_data->data[panel_type]; | |
1033 | ||
3cf05076 VS |
1034 | panel->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM; |
1035 | if (!panel->vbt.backlight.present) { | |
dbd440d8 | 1036 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1037 | "PWM backlight not present in VBT (type %u)\n", |
1038 | entry->type); | |
39fbc9c8 JN |
1039 | return; |
1040 | } | |
1041 | ||
3cf05076 | 1042 | panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI; |
a0dcb06d | 1043 | panel->vbt.backlight.controller = 0; |
a434689c | 1044 | if (i915->display.vbt.version >= 191) { |
4378daf5 | 1045 | size_t exp_size; |
9a41e17d | 1046 | |
a434689c | 1047 | if (i915->display.vbt.version >= 236) |
4378daf5 | 1048 | exp_size = sizeof(struct bdb_lfp_backlight_data); |
a434689c | 1049 | else if (i915->display.vbt.version >= 234) |
4378daf5 LM |
1050 | exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234; |
1051 | else | |
1052 | exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191; | |
1053 | ||
1054 | if (get_blocksize(backlight_data) >= exp_size) { | |
1055 | const struct lfp_backlight_control_method *method; | |
1056 | ||
1057 | method = &backlight_data->backlight_control[panel_type]; | |
3cf05076 VS |
1058 | panel->vbt.backlight.type = method->type; |
1059 | panel->vbt.backlight.controller = method->controller; | |
4378daf5 | 1060 | } |
9a41e17d D |
1061 | } |
1062 | ||
3cf05076 VS |
1063 | panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz; |
1064 | panel->vbt.backlight.active_low_pwm = entry->active_low_pwm; | |
d381baad | 1065 | |
a434689c | 1066 | if (i915->display.vbt.version >= 234) { |
d381baad JRS |
1067 | u16 min_level; |
1068 | bool scale; | |
1069 | ||
1070 | level = backlight_data->brightness_level[panel_type].level; | |
1071 | min_level = backlight_data->brightness_min_level[panel_type].level; | |
1072 | ||
a434689c | 1073 | if (i915->display.vbt.version >= 236) |
d381baad JRS |
1074 | scale = backlight_data->brightness_precision_bits[panel_type] == 16; |
1075 | else | |
1076 | scale = level > 255; | |
1077 | ||
1078 | if (scale) | |
1079 | min_level = min_level / 255; | |
1080 | ||
1081 | if (min_level > 255) { | |
dbd440d8 | 1082 | drm_warn(&i915->drm, "Brightness min level > 255\n"); |
d381baad JRS |
1083 | level = 255; |
1084 | } | |
3cf05076 | 1085 | panel->vbt.backlight.min_brightness = min_level; |
84d3d71f | 1086 | |
3cf05076 | 1087 | panel->vbt.backlight.brightness_precision_bits = |
84d3d71f | 1088 | backlight_data->brightness_precision_bits[panel_type]; |
d381baad JRS |
1089 | } else { |
1090 | level = backlight_data->level[panel_type]; | |
3cf05076 | 1091 | panel->vbt.backlight.min_brightness = entry->min_brightness; |
d381baad JRS |
1092 | } |
1093 | ||
fe82b93f VS |
1094 | if (i915->display.vbt.version >= 239) |
1095 | panel->vbt.backlight.hdr_dpcd_refresh_timeout = | |
1096 | DIV_ROUND_UP(backlight_data->hdr_dpcd_refresh_timeout[panel_type], 100); | |
1097 | else | |
1098 | panel->vbt.backlight.hdr_dpcd_refresh_timeout = 30; | |
1099 | ||
dbd440d8 | 1100 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1101 | "VBT backlight PWM modulation frequency %u Hz, " |
1102 | "active %s, min brightness %u, level %u, controller %u\n", | |
3cf05076 VS |
1103 | panel->vbt.backlight.pwm_freq_hz, |
1104 | panel->vbt.backlight.active_low_pwm ? "low" : "high", | |
1105 | panel->vbt.backlight.min_brightness, | |
d381baad | 1106 | level, |
3cf05076 | 1107 | panel->vbt.backlight.controller); |
f00076d2 JN |
1108 | } |
1109 | ||
88631706 ML |
1110 | /* Try to find sdvo panel data */ |
1111 | static void | |
3cf05076 VS |
1112 | parse_sdvo_panel_data(struct drm_i915_private *i915, |
1113 | struct intel_panel *panel) | |
88631706 | 1114 | { |
f87f6599 | 1115 | const struct bdb_sdvo_panel_dtds *dtds; |
88631706 | 1116 | struct drm_display_mode *panel_fixed_mode; |
5a1e5b6c | 1117 | int index; |
79e53945 | 1118 | |
5fb2e673 | 1119 | index = i915->display.params.vbt_sdvo_panel_type; |
c10e408a | 1120 | if (index == -2) { |
dbd440d8 | 1121 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 1122 | "Ignore SDVO panel mode from BIOS VBT tables.\n"); |
c10e408a MF |
1123 | return; |
1124 | } | |
1125 | ||
5a1e5b6c | 1126 | if (index == -1) { |
e8ef3b4c | 1127 | const struct bdb_sdvo_lvds_options *sdvo_lvds_options; |
5a1e5b6c | 1128 | |
0a93eeb5 | 1129 | sdvo_lvds_options = bdb_find_section(i915, BDB_SDVO_LVDS_OPTIONS); |
5a1e5b6c CW |
1130 | if (!sdvo_lvds_options) |
1131 | return; | |
1132 | ||
1133 | index = sdvo_lvds_options->panel_type; | |
1134 | } | |
88631706 | 1135 | |
0a93eeb5 | 1136 | dtds = bdb_find_section(i915, BDB_SDVO_PANEL_DTDS); |
f87f6599 | 1137 | if (!dtds) |
88631706 ML |
1138 | return; |
1139 | ||
9a298b2a | 1140 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); |
88631706 ML |
1141 | if (!panel_fixed_mode) |
1142 | return; | |
1143 | ||
bb6f53d4 | 1144 | fill_detail_timing_data(i915, panel_fixed_mode, &dtds->dtds[index]); |
88631706 | 1145 | |
3cf05076 | 1146 | panel->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode; |
79e53945 | 1147 | |
dbd440d8 | 1148 | drm_dbg_kms(&i915->drm, |
f01bae2d VS |
1149 | "Found SDVO panel mode in BIOS VBT tables: " DRM_MODE_FMT "\n", |
1150 | DRM_MODE_ARG(panel_fixed_mode)); | |
79e53945 JB |
1151 | } |
1152 | ||
dbd440d8 | 1153 | static int intel_bios_ssc_frequency(struct drm_i915_private *i915, |
9a4114ff BF |
1154 | bool alternate) |
1155 | { | |
005e9537 | 1156 | switch (DISPLAY_VER(i915)) { |
9a4114ff | 1157 | case 2: |
e91e941b | 1158 | return alternate ? 66667 : 48000; |
9a4114ff BF |
1159 | case 3: |
1160 | case 4: | |
e91e941b | 1161 | return alternate ? 100000 : 96000; |
9a4114ff | 1162 | default: |
e91e941b | 1163 | return alternate ? 100000 : 120000; |
9a4114ff BF |
1164 | } |
1165 | } | |
1166 | ||
79e53945 | 1167 | static void |
e163cfb4 | 1168 | parse_general_features(struct drm_i915_private *i915) |
79e53945 | 1169 | { |
e8ef3b4c | 1170 | const struct bdb_general_features *general; |
79e53945 | 1171 | |
0a93eeb5 | 1172 | general = bdb_find_section(i915, BDB_GENERAL_FEATURES); |
34957e8c JN |
1173 | if (!general) |
1174 | return; | |
1175 | ||
a434689c | 1176 | i915->display.vbt.int_tv_support = general->int_tv_support; |
34957e8c | 1177 | /* int_crt_support can't be trusted on earlier platforms */ |
a434689c | 1178 | if (i915->display.vbt.version >= 155 && |
dbd440d8 | 1179 | (HAS_DDI(i915) || IS_VALLEYVIEW(i915))) |
a434689c JN |
1180 | i915->display.vbt.int_crt_support = general->int_crt_support; |
1181 | i915->display.vbt.lvds_use_ssc = general->enable_ssc; | |
1182 | i915->display.vbt.lvds_ssc_freq = | |
dbd440d8 | 1183 | intel_bios_ssc_frequency(i915, general->ssc_freq); |
a434689c JN |
1184 | i915->display.vbt.display_clock_mode = general->display_clock_mode; |
1185 | i915->display.vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted; | |
1186 | if (i915->display.vbt.version >= 181) { | |
1187 | i915->display.vbt.orientation = general->rotate_180 ? | |
c1cd5b24 VS |
1188 | DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP : |
1189 | DRM_MODE_PANEL_ORIENTATION_NORMAL; | |
1190 | } else { | |
a434689c | 1191 | i915->display.vbt.orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; |
c1cd5b24 | 1192 | } |
b70ad01a | 1193 | |
a434689c JN |
1194 | if (i915->display.vbt.version >= 249 && general->afc_startup_config) { |
1195 | i915->display.vbt.override_afc_startup = true; | |
1196 | i915->display.vbt.override_afc_startup_val = general->afc_startup_config == 0x1 ? 0x0 : 0x7; | |
b70ad01a JRS |
1197 | } |
1198 | ||
dbd440d8 | 1199 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 1200 | "BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n", |
a434689c JN |
1201 | i915->display.vbt.int_tv_support, |
1202 | i915->display.vbt.int_crt_support, | |
1203 | i915->display.vbt.lvds_use_ssc, | |
1204 | i915->display.vbt.lvds_ssc_freq, | |
1205 | i915->display.vbt.display_clock_mode, | |
1206 | i915->display.vbt.fdi_rx_polarity_inverted); | |
79e53945 JB |
1207 | } |
1208 | ||
cc998589 | 1209 | static const struct child_device_config * |
e192839e | 1210 | child_device_ptr(const struct bdb_general_definitions *defs, int i) |
90e4f159 | 1211 | { |
e192839e | 1212 | return (const void *) &defs->devices[i * defs->child_dev_size]; |
90e4f159 VS |
1213 | } |
1214 | ||
9b9d172d | 1215 | static void |
ef0096e4 | 1216 | parse_sdvo_device_mapping(struct drm_i915_private *i915) |
9b9d172d | 1217 | { |
3162d057 | 1218 | const struct intel_bios_encoder_data *devdata; |
0d9ef19b | 1219 | int count = 0; |
6cc38aca JN |
1220 | |
1221 | /* | |
0ebdabe6 JN |
1222 | * Only parse SDVO mappings on gens that could have SDVO. This isn't |
1223 | * accurate and doesn't have to be, as long as it's not too strict. | |
9b9d172d | 1224 | */ |
93e7e61e | 1225 | if (!IS_DISPLAY_VER(i915, 3, 7)) { |
dbd440d8 | 1226 | drm_dbg_kms(&i915->drm, "Skipping SDVO device mapping\n"); |
9b9d172d | 1227 | return; |
1228 | } | |
0ebdabe6 | 1229 | |
a434689c | 1230 | list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { |
d24b3475 VS |
1231 | const struct child_device_config *child = &devdata->child; |
1232 | struct sdvo_device_mapping *mapping; | |
0ebdabe6 | 1233 | |
6cc38aca JN |
1234 | if (child->slave_addr != SLAVE_ADDR1 && |
1235 | child->slave_addr != SLAVE_ADDR2) { | |
9b9d172d | 1236 | /* |
1237 | * If the slave address is neither 0x70 nor 0x72, | |
1238 | * it is not a SDVO device. Skip it. | |
1239 | */ | |
1240 | continue; | |
1241 | } | |
6cc38aca JN |
1242 | if (child->dvo_port != DEVICE_PORT_DVOB && |
1243 | child->dvo_port != DEVICE_PORT_DVOC) { | |
9b9d172d | 1244 | /* skip the incorrect SDVO port */ |
dbd440d8 | 1245 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 1246 | "Incorrect SDVO port. Skip it\n"); |
9b9d172d | 1247 | continue; |
1248 | } | |
dbd440d8 | 1249 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1250 | "the SDVO device with slave addr %2x is found on" |
1251 | " %s port\n", | |
1252 | child->slave_addr, | |
1253 | (child->dvo_port == DEVICE_PORT_DVOB) ? | |
1254 | "SDVOB" : "SDVOC"); | |
a434689c | 1255 | mapping = &i915->display.vbt.sdvo_mappings[child->dvo_port - 1]; |
e192839e JN |
1256 | if (!mapping->initialized) { |
1257 | mapping->dvo_port = child->dvo_port; | |
1258 | mapping->slave_addr = child->slave_addr; | |
1259 | mapping->dvo_wiring = child->dvo_wiring; | |
1260 | mapping->ddc_pin = child->ddc_pin; | |
1261 | mapping->i2c_pin = child->i2c_pin; | |
1262 | mapping->initialized = 1; | |
dbd440d8 | 1263 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1264 | "SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", |
1265 | mapping->dvo_port, mapping->slave_addr, | |
1266 | mapping->dvo_wiring, mapping->ddc_pin, | |
1267 | mapping->i2c_pin); | |
9b9d172d | 1268 | } else { |
dbd440d8 | 1269 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1270 | "Maybe one SDVO port is shared by " |
1271 | "two SDVO device.\n"); | |
9b9d172d | 1272 | } |
6cc38aca | 1273 | if (child->slave2_addr) { |
9b9d172d | 1274 | /* Maybe this is a SDVO device with multiple inputs */ |
1275 | /* And the mapping info is not added */ | |
dbd440d8 | 1276 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1277 | "there exists the slave2_addr. Maybe this" |
1278 | " is a SDVO device with multiple inputs.\n"); | |
9b9d172d | 1279 | } |
1280 | count++; | |
1281 | } | |
1282 | ||
1283 | if (!count) { | |
1284 | /* No SDVO device info is found */ | |
dbd440d8 | 1285 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 1286 | "No SDVO device info is found in VBT\n"); |
9b9d172d | 1287 | } |
9b9d172d | 1288 | } |
32f9d658 ZW |
1289 | |
1290 | static void | |
e163cfb4 | 1291 | parse_driver_features(struct drm_i915_private *i915) |
32f9d658 | 1292 | { |
e8ef3b4c | 1293 | const struct bdb_driver_features *driver; |
32f9d658 | 1294 | |
0a93eeb5 | 1295 | driver = bdb_find_section(i915, BDB_DRIVER_FEATURES); |
652c393a JB |
1296 | if (!driver) |
1297 | return; | |
1298 | ||
005e9537 | 1299 | if (DISPLAY_VER(i915) >= 5) { |
ca3b3fa3 VS |
1300 | /* |
1301 | * Note that we consider BDB_DRIVER_FEATURE_INT_SDVO_LVDS | |
1302 | * to mean "eDP". The VBT spec doesn't agree with that | |
1303 | * interpretation, but real world VBTs seem to. | |
1304 | */ | |
1305 | if (driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS) | |
a434689c | 1306 | i915->display.vbt.int_lvds_support = 0; |
ca3b3fa3 VS |
1307 | } else { |
1308 | /* | |
1309 | * FIXME it's not clear which BDB version has the LVDS config | |
1310 | * bits defined. Revision history in the VBT spec says: | |
1311 | * "0.92 | Add two definitions for VBT value of LVDS Active | |
1312 | * Config (00b and 11b values defined) | 06/13/2005" | |
1313 | * but does not the specify the BDB version. | |
1314 | * | |
1315 | * So far version 134 (on i945gm) is the oldest VBT observed | |
1316 | * in the wild with the bits correctly populated. Version | |
1317 | * 108 (on i85x) does not have the bits correctly populated. | |
1318 | */ | |
a434689c | 1319 | if (i915->display.vbt.version >= 134 && |
ca3b3fa3 VS |
1320 | driver->lvds_config != BDB_DRIVER_FEATURE_INT_LVDS && |
1321 | driver->lvds_config != BDB_DRIVER_FEATURE_INT_SDVO_LVDS) | |
a434689c | 1322 | i915->display.vbt.int_lvds_support = 0; |
ca3b3fa3 | 1323 | } |
c3fbcf60 VS |
1324 | } |
1325 | ||
1326 | static void | |
3cf05076 VS |
1327 | parse_panel_driver_features(struct drm_i915_private *i915, |
1328 | struct intel_panel *panel) | |
c3fbcf60 VS |
1329 | { |
1330 | const struct bdb_driver_features *driver; | |
1331 | ||
0a93eeb5 | 1332 | driver = bdb_find_section(i915, BDB_DRIVER_FEATURES); |
c3fbcf60 VS |
1333 | if (!driver) |
1334 | return; | |
652c393a | 1335 | |
a434689c | 1336 | if (i915->display.vbt.version < 228) { |
dbd440d8 | 1337 | drm_dbg_kms(&i915->drm, "DRRS State Enabled:%d\n", |
e92cbf38 | 1338 | driver->drrs_enabled); |
551fb93d JRS |
1339 | /* |
1340 | * If DRRS is not supported, drrs_type has to be set to 0. | |
1341 | * This is because, VBT is configured in such a way that | |
1342 | * static DRRS is 0 and DRRS not supported is represented by | |
1343 | * driver->drrs_enabled=false | |
1344 | */ | |
5a18db2e VS |
1345 | if (!driver->drrs_enabled && panel->vbt.drrs_type != DRRS_TYPE_NONE) { |
1346 | /* | |
1347 | * FIXME Should DMRRS perhaps be treated as seamless | |
1348 | * but without the automatic downclocking? | |
1349 | */ | |
1350 | if (driver->dmrrs_enabled) | |
1351 | panel->vbt.drrs_type = DRRS_TYPE_STATIC; | |
1352 | else | |
1353 | panel->vbt.drrs_type = DRRS_TYPE_NONE; | |
1354 | } | |
551fb93d | 1355 | |
3cf05076 | 1356 | panel->vbt.psr.enable = driver->psr_enabled; |
551fb93d JRS |
1357 | } |
1358 | } | |
1359 | ||
1360 | static void | |
3cf05076 VS |
1361 | parse_power_conservation_features(struct drm_i915_private *i915, |
1362 | struct intel_panel *panel) | |
551fb93d JRS |
1363 | { |
1364 | const struct bdb_lfp_power *power; | |
3cf05076 | 1365 | u8 panel_type = panel->vbt.panel_type; |
551fb93d | 1366 | |
fba99b1a | 1367 | panel->vbt.vrr = true; /* matches Windows behaviour */ |
551fb93d | 1368 | |
a434689c | 1369 | if (i915->display.vbt.version < 228) |
551fb93d JRS |
1370 | return; |
1371 | ||
0a93eeb5 | 1372 | power = bdb_find_section(i915, BDB_LFP_POWER); |
551fb93d JRS |
1373 | if (!power) |
1374 | return; | |
1375 | ||
a50cc495 | 1376 | panel->vbt.psr.enable = panel_bool(power->psr, panel_type); |
551fb93d | 1377 | |
83a7280e PB |
1378 | /* |
1379 | * If DRRS is not supported, drrs_type has to be set to 0. | |
1380 | * This is because, VBT is configured in such a way that | |
1381 | * static DRRS is 0 and DRRS not supported is represented by | |
551fb93d | 1382 | * power->drrs & BIT(panel_type)=false |
83a7280e | 1383 | */ |
a50cc495 | 1384 | if (!panel_bool(power->drrs, panel_type) && panel->vbt.drrs_type != DRRS_TYPE_NONE) { |
5a18db2e VS |
1385 | /* |
1386 | * FIXME Should DMRRS perhaps be treated as seamless | |
1387 | * but without the automatic downclocking? | |
1388 | */ | |
a50cc495 | 1389 | if (panel_bool(power->dmrrs, panel_type)) |
5a18db2e VS |
1390 | panel->vbt.drrs_type = DRRS_TYPE_STATIC; |
1391 | else | |
1392 | panel->vbt.drrs_type = DRRS_TYPE_NONE; | |
1393 | } | |
f615cb6a | 1394 | |
a434689c | 1395 | if (i915->display.vbt.version >= 232) |
a50cc495 | 1396 | panel->vbt.edp.hobl = panel_bool(power->hobl, panel_type); |
fba99b1a | 1397 | |
a434689c | 1398 | if (i915->display.vbt.version >= 233) |
a50cc495 VS |
1399 | panel->vbt.vrr = panel_bool(power->vrr_feature_enabled, |
1400 | panel_type); | |
32f9d658 ZW |
1401 | } |
1402 | ||
500a8cc4 | 1403 | static void |
3cf05076 VS |
1404 | parse_edp(struct drm_i915_private *i915, |
1405 | struct intel_panel *panel) | |
500a8cc4 | 1406 | { |
e8ef3b4c JN |
1407 | const struct bdb_edp *edp; |
1408 | const struct edp_power_seq *edp_pps; | |
058727ee | 1409 | const struct edp_fast_link_params *edp_link_params; |
3cf05076 | 1410 | int panel_type = panel->vbt.panel_type; |
500a8cc4 | 1411 | |
0a93eeb5 | 1412 | edp = bdb_find_section(i915, BDB_EDP); |
5255e2f8 | 1413 | if (!edp) |
500a8cc4 | 1414 | return; |
500a8cc4 | 1415 | |
a50cc495 | 1416 | switch (panel_bits(edp->color_depth, panel_type, 2)) { |
500a8cc4 | 1417 | case EDP_18BPP: |
3cf05076 | 1418 | panel->vbt.edp.bpp = 18; |
500a8cc4 ZW |
1419 | break; |
1420 | case EDP_24BPP: | |
3cf05076 | 1421 | panel->vbt.edp.bpp = 24; |
500a8cc4 ZW |
1422 | break; |
1423 | case EDP_30BPP: | |
3cf05076 | 1424 | panel->vbt.edp.bpp = 30; |
500a8cc4 ZW |
1425 | break; |
1426 | } | |
5ceb0f9b | 1427 | |
9f0e7ff4 JB |
1428 | /* Get the eDP sequencing and link info */ |
1429 | edp_pps = &edp->power_seqs[panel_type]; | |
058727ee | 1430 | edp_link_params = &edp->fast_link_params[panel_type]; |
5ceb0f9b | 1431 | |
3cf05076 | 1432 | panel->vbt.edp.pps = *edp_pps; |
5ceb0f9b | 1433 | |
a434689c | 1434 | if (i915->display.vbt.version >= 224) { |
f06d1d66 VS |
1435 | panel->vbt.edp.rate = |
1436 | edp->edp_fast_link_training_rate[panel_type] * 20; | |
1437 | } else { | |
1438 | switch (edp_link_params->rate) { | |
1439 | case EDP_RATE_1_62: | |
1440 | panel->vbt.edp.rate = 162000; | |
1441 | break; | |
1442 | case EDP_RATE_2_7: | |
1443 | panel->vbt.edp.rate = 270000; | |
1444 | break; | |
1445 | case EDP_RATE_5_4: | |
1446 | panel->vbt.edp.rate = 540000; | |
1447 | break; | |
1448 | default: | |
1449 | drm_dbg_kms(&i915->drm, | |
1450 | "VBT has unknown eDP link rate value %u\n", | |
1451 | edp_link_params->rate); | |
1452 | break; | |
1453 | } | |
e13e2b2c JN |
1454 | } |
1455 | ||
9f0e7ff4 | 1456 | switch (edp_link_params->lanes) { |
e13e2b2c | 1457 | case EDP_LANE_1: |
3cf05076 | 1458 | panel->vbt.edp.lanes = 1; |
9f0e7ff4 | 1459 | break; |
e13e2b2c | 1460 | case EDP_LANE_2: |
3cf05076 | 1461 | panel->vbt.edp.lanes = 2; |
9f0e7ff4 | 1462 | break; |
e13e2b2c | 1463 | case EDP_LANE_4: |
3cf05076 | 1464 | panel->vbt.edp.lanes = 4; |
9f0e7ff4 | 1465 | break; |
e13e2b2c | 1466 | default: |
dbd440d8 | 1467 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1468 | "VBT has unknown eDP lane count value %u\n", |
1469 | edp_link_params->lanes); | |
e13e2b2c | 1470 | break; |
9f0e7ff4 | 1471 | } |
e13e2b2c | 1472 | |
9f0e7ff4 | 1473 | switch (edp_link_params->preemphasis) { |
e13e2b2c | 1474 | case EDP_PREEMPHASIS_NONE: |
3cf05076 | 1475 | panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0; |
9f0e7ff4 | 1476 | break; |
e13e2b2c | 1477 | case EDP_PREEMPHASIS_3_5dB: |
3cf05076 | 1478 | panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1; |
9f0e7ff4 | 1479 | break; |
e13e2b2c | 1480 | case EDP_PREEMPHASIS_6dB: |
3cf05076 | 1481 | panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2; |
9f0e7ff4 | 1482 | break; |
e13e2b2c | 1483 | case EDP_PREEMPHASIS_9_5dB: |
3cf05076 | 1484 | panel->vbt.edp.preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3; |
9f0e7ff4 | 1485 | break; |
e13e2b2c | 1486 | default: |
dbd440d8 | 1487 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1488 | "VBT has unknown eDP pre-emphasis value %u\n", |
1489 | edp_link_params->preemphasis); | |
e13e2b2c | 1490 | break; |
9f0e7ff4 | 1491 | } |
e13e2b2c | 1492 | |
9f0e7ff4 | 1493 | switch (edp_link_params->vswing) { |
e13e2b2c | 1494 | case EDP_VSWING_0_4V: |
3cf05076 | 1495 | panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0; |
9f0e7ff4 | 1496 | break; |
e13e2b2c | 1497 | case EDP_VSWING_0_6V: |
3cf05076 | 1498 | panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1; |
9f0e7ff4 | 1499 | break; |
e13e2b2c | 1500 | case EDP_VSWING_0_8V: |
3cf05076 | 1501 | panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
9f0e7ff4 | 1502 | break; |
e13e2b2c | 1503 | case EDP_VSWING_1_2V: |
3cf05076 | 1504 | panel->vbt.edp.vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
9f0e7ff4 | 1505 | break; |
e13e2b2c | 1506 | default: |
dbd440d8 | 1507 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1508 | "VBT has unknown eDP voltage swing value %u\n", |
1509 | edp_link_params->vswing); | |
e13e2b2c | 1510 | break; |
9f0e7ff4 | 1511 | } |
9a57f5bb | 1512 | |
a434689c | 1513 | if (i915->display.vbt.version >= 173) { |
0ede0141 | 1514 | u8 vswing; |
9a57f5bb | 1515 | |
9e458034 | 1516 | /* Don't read from VBT if module parameter has valid value*/ |
87706a67 | 1517 | if (i915->display.params.edp_vswing) { |
3cf05076 | 1518 | panel->vbt.edp.low_vswing = |
87706a67 | 1519 | i915->display.params.edp_vswing == 1; |
9e458034 SJ |
1520 | } else { |
1521 | vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; | |
3cf05076 | 1522 | panel->vbt.edp.low_vswing = vswing == 0; |
9e458034 | 1523 | } |
9a57f5bb | 1524 | } |
b395c29a | 1525 | |
3cf05076 | 1526 | panel->vbt.edp.drrs_msa_timing_delay = |
a50cc495 | 1527 | panel_bits(edp->sdrrs_msa_timing_delay, panel_type, 2); |
24b8b74e | 1528 | |
a434689c | 1529 | if (i915->display.vbt.version >= 244) |
24b8b74e VS |
1530 | panel->vbt.edp.max_link_rate = |
1531 | edp->edp_max_port_link_rate[panel_type] * 20; | |
500a8cc4 ZW |
1532 | } |
1533 | ||
bfd7ebda | 1534 | static void |
3cf05076 VS |
1535 | parse_psr(struct drm_i915_private *i915, |
1536 | struct intel_panel *panel) | |
bfd7ebda | 1537 | { |
e8ef3b4c JN |
1538 | const struct bdb_psr *psr; |
1539 | const struct psr_table *psr_table; | |
3cf05076 | 1540 | int panel_type = panel->vbt.panel_type; |
bfd7ebda | 1541 | |
0a93eeb5 | 1542 | psr = bdb_find_section(i915, BDB_PSR); |
bfd7ebda | 1543 | if (!psr) { |
dbd440d8 | 1544 | drm_dbg_kms(&i915->drm, "No PSR BDB found.\n"); |
bfd7ebda RV |
1545 | return; |
1546 | } | |
1547 | ||
1548 | psr_table = &psr->psr_table[panel_type]; | |
1549 | ||
3cf05076 VS |
1550 | panel->vbt.psr.full_link = psr_table->full_link; |
1551 | panel->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup; | |
bfd7ebda RV |
1552 | |
1553 | /* Allowed VBT values goes from 0 to 15 */ | |
3cf05076 | 1554 | panel->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 : |
bfd7ebda RV |
1555 | psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames; |
1556 | ||
77312ae8 VN |
1557 | /* |
1558 | * New psr options 0=500us, 1=100us, 2=2500us, 3=0us | |
1559 | * Old decimal value is wake up time in multiples of 100 us. | |
1560 | */ | |
a434689c | 1561 | if (i915->display.vbt.version >= 205 && |
2446e1d6 | 1562 | (DISPLAY_VER(i915) >= 9 && !IS_BROXTON(i915))) { |
77312ae8 VN |
1563 | switch (psr_table->tp1_wakeup_time) { |
1564 | case 0: | |
3cf05076 | 1565 | panel->vbt.psr.tp1_wakeup_time_us = 500; |
77312ae8 VN |
1566 | break; |
1567 | case 1: | |
3cf05076 | 1568 | panel->vbt.psr.tp1_wakeup_time_us = 100; |
77312ae8 VN |
1569 | break; |
1570 | case 3: | |
3cf05076 | 1571 | panel->vbt.psr.tp1_wakeup_time_us = 0; |
77312ae8 VN |
1572 | break; |
1573 | default: | |
dbd440d8 | 1574 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1575 | "VBT tp1 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", |
1576 | psr_table->tp1_wakeup_time); | |
df561f66 | 1577 | fallthrough; |
77312ae8 | 1578 | case 2: |
3cf05076 | 1579 | panel->vbt.psr.tp1_wakeup_time_us = 2500; |
77312ae8 VN |
1580 | break; |
1581 | } | |
1582 | ||
1583 | switch (psr_table->tp2_tp3_wakeup_time) { | |
1584 | case 0: | |
3cf05076 | 1585 | panel->vbt.psr.tp2_tp3_wakeup_time_us = 500; |
77312ae8 VN |
1586 | break; |
1587 | case 1: | |
3cf05076 | 1588 | panel->vbt.psr.tp2_tp3_wakeup_time_us = 100; |
77312ae8 VN |
1589 | break; |
1590 | case 3: | |
3cf05076 | 1591 | panel->vbt.psr.tp2_tp3_wakeup_time_us = 0; |
77312ae8 VN |
1592 | break; |
1593 | default: | |
dbd440d8 | 1594 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
1595 | "VBT tp2_tp3 wakeup time value %d is outside range[0-3], defaulting to max value 2500us\n", |
1596 | psr_table->tp2_tp3_wakeup_time); | |
df561f66 | 1597 | fallthrough; |
77312ae8 | 1598 | case 2: |
3cf05076 | 1599 | panel->vbt.psr.tp2_tp3_wakeup_time_us = 2500; |
77312ae8 VN |
1600 | break; |
1601 | } | |
1602 | } else { | |
3cf05076 VS |
1603 | panel->vbt.psr.tp1_wakeup_time_us = psr_table->tp1_wakeup_time * 100; |
1604 | panel->vbt.psr.tp2_tp3_wakeup_time_us = psr_table->tp2_tp3_wakeup_time * 100; | |
77312ae8 | 1605 | } |
88a0d960 | 1606 | |
a434689c | 1607 | if (i915->display.vbt.version >= 226) { |
b5ea9c93 | 1608 | u32 wakeup_time = psr->psr2_tp2_tp3_wakeup_time; |
88a0d960 | 1609 | |
a50cc495 | 1610 | wakeup_time = panel_bits(wakeup_time, panel_type, 2); |
88a0d960 JRS |
1611 | switch (wakeup_time) { |
1612 | case 0: | |
1613 | wakeup_time = 500; | |
1614 | break; | |
1615 | case 1: | |
1616 | wakeup_time = 100; | |
1617 | break; | |
1618 | case 3: | |
1619 | wakeup_time = 50; | |
1620 | break; | |
1621 | default: | |
1622 | case 2: | |
1623 | wakeup_time = 2500; | |
1624 | break; | |
1625 | } | |
3cf05076 | 1626 | panel->vbt.psr.psr2_tp2_tp3_wakeup_time_us = wakeup_time; |
88a0d960 JRS |
1627 | } else { |
1628 | /* Reusing PSR1 wakeup time for PSR2 in older VBTs */ | |
3cf05076 | 1629 | panel->vbt.psr.psr2_tp2_tp3_wakeup_time_us = panel->vbt.psr.tp2_tp3_wakeup_time_us; |
88a0d960 | 1630 | } |
bfd7ebda RV |
1631 | } |
1632 | ||
dbd440d8 | 1633 | static void parse_dsi_backlight_ports(struct drm_i915_private *i915, |
3cf05076 VS |
1634 | struct intel_panel *panel, |
1635 | enum port port) | |
46e58320 | 1636 | { |
ab55165d JN |
1637 | enum port port_bc = DISPLAY_VER(i915) >= 11 ? PORT_B : PORT_C; |
1638 | ||
a434689c | 1639 | if (!panel->vbt.dsi.config->dual_link || i915->display.vbt.version < 197) { |
3cf05076 VS |
1640 | panel->vbt.dsi.bl_ports = BIT(port); |
1641 | if (panel->vbt.dsi.config->cabc_supported) | |
1642 | panel->vbt.dsi.cabc_ports = BIT(port); | |
46e58320 | 1643 | |
46e58320 MC |
1644 | return; |
1645 | } | |
1646 | ||
3cf05076 | 1647 | switch (panel->vbt.dsi.config->dl_dcs_backlight_ports) { |
46e58320 | 1648 | case DL_DCS_PORT_A: |
3cf05076 | 1649 | panel->vbt.dsi.bl_ports = BIT(PORT_A); |
46e58320 MC |
1650 | break; |
1651 | case DL_DCS_PORT_C: | |
ab55165d | 1652 | panel->vbt.dsi.bl_ports = BIT(port_bc); |
46e58320 MC |
1653 | break; |
1654 | default: | |
1655 | case DL_DCS_PORT_A_AND_C: | |
ab55165d | 1656 | panel->vbt.dsi.bl_ports = BIT(PORT_A) | BIT(port_bc); |
46e58320 MC |
1657 | break; |
1658 | } | |
1659 | ||
3cf05076 | 1660 | if (!panel->vbt.dsi.config->cabc_supported) |
46e58320 MC |
1661 | return; |
1662 | ||
3cf05076 | 1663 | switch (panel->vbt.dsi.config->dl_dcs_cabc_ports) { |
46e58320 | 1664 | case DL_DCS_PORT_A: |
3cf05076 | 1665 | panel->vbt.dsi.cabc_ports = BIT(PORT_A); |
46e58320 MC |
1666 | break; |
1667 | case DL_DCS_PORT_C: | |
ab55165d | 1668 | panel->vbt.dsi.cabc_ports = BIT(port_bc); |
46e58320 MC |
1669 | break; |
1670 | default: | |
1671 | case DL_DCS_PORT_A_AND_C: | |
3cf05076 | 1672 | panel->vbt.dsi.cabc_ports = |
ab55165d | 1673 | BIT(PORT_A) | BIT(port_bc); |
46e58320 MC |
1674 | break; |
1675 | } | |
1676 | } | |
1677 | ||
d17c5443 | 1678 | static void |
3cf05076 VS |
1679 | parse_mipi_config(struct drm_i915_private *i915, |
1680 | struct intel_panel *panel) | |
d17c5443 | 1681 | { |
e8ef3b4c | 1682 | const struct bdb_mipi_config *start; |
e8ef3b4c JN |
1683 | const struct mipi_config *config; |
1684 | const struct mipi_pps_data *pps; | |
3cf05076 | 1685 | int panel_type = panel->vbt.panel_type; |
46e58320 | 1686 | enum port port; |
d3b542fc | 1687 | |
3e6bd011 | 1688 | /* parse MIPI blocks only if LFP type is MIPI */ |
dbd440d8 | 1689 | if (!intel_bios_is_dsi_present(i915, &port)) |
3e6bd011 SK |
1690 | return; |
1691 | ||
d3b542fc | 1692 | /* Initialize this to undefined indicating no generic MIPI support */ |
3cf05076 | 1693 | panel->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID; |
d3b542fc SK |
1694 | |
1695 | /* Block #40 is already parsed and panel_fixed_mode is | |
dbd440d8 | 1696 | * stored in i915->lfp_lvds_vbt_mode |
d3b542fc SK |
1697 | * resuse this when needed |
1698 | */ | |
d17c5443 | 1699 | |
d3b542fc SK |
1700 | /* Parse #52 for panel index used from panel_type already |
1701 | * parsed | |
1702 | */ | |
0a93eeb5 | 1703 | start = bdb_find_section(i915, BDB_MIPI_CONFIG); |
d3b542fc | 1704 | if (!start) { |
dbd440d8 | 1705 | drm_dbg_kms(&i915->drm, "No MIPI config BDB found"); |
d17c5443 SK |
1706 | return; |
1707 | } | |
1708 | ||
dbd440d8 | 1709 | drm_dbg(&i915->drm, "Found MIPI Config block, panel index = %d\n", |
e92cbf38 | 1710 | panel_type); |
d3b542fc SK |
1711 | |
1712 | /* | |
1713 | * get hold of the correct configuration block and pps data as per | |
1714 | * the panel_type as index | |
1715 | */ | |
1716 | config = &start->config[panel_type]; | |
1717 | pps = &start->pps[panel_type]; | |
1718 | ||
1719 | /* store as of now full data. Trim when we realise all is not needed */ | |
3cf05076 VS |
1720 | panel->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL); |
1721 | if (!panel->vbt.dsi.config) | |
d3b542fc SK |
1722 | return; |
1723 | ||
3cf05076 VS |
1724 | panel->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL); |
1725 | if (!panel->vbt.dsi.pps) { | |
1726 | kfree(panel->vbt.dsi.config); | |
d3b542fc SK |
1727 | return; |
1728 | } | |
1729 | ||
3cf05076 | 1730 | parse_dsi_backlight_ports(i915, panel, port); |
9f7c5b17 | 1731 | |
c1cd5b24 VS |
1732 | /* FIXME is the 90 vs. 270 correct? */ |
1733 | switch (config->rotation) { | |
1734 | case ENABLE_ROTATION_0: | |
1735 | /* | |
1736 | * Most (all?) VBTs claim 0 degrees despite having | |
1737 | * an upside down panel, thus we do not trust this. | |
1738 | */ | |
3cf05076 | 1739 | panel->vbt.dsi.orientation = |
c1cd5b24 VS |
1740 | DRM_MODE_PANEL_ORIENTATION_UNKNOWN; |
1741 | break; | |
1742 | case ENABLE_ROTATION_90: | |
3cf05076 | 1743 | panel->vbt.dsi.orientation = |
c1cd5b24 VS |
1744 | DRM_MODE_PANEL_ORIENTATION_RIGHT_UP; |
1745 | break; | |
1746 | case ENABLE_ROTATION_180: | |
3cf05076 | 1747 | panel->vbt.dsi.orientation = |
c1cd5b24 VS |
1748 | DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; |
1749 | break; | |
1750 | case ENABLE_ROTATION_270: | |
3cf05076 | 1751 | panel->vbt.dsi.orientation = |
c1cd5b24 VS |
1752 | DRM_MODE_PANEL_ORIENTATION_LEFT_UP; |
1753 | break; | |
1754 | } | |
1755 | ||
d3b542fc | 1756 | /* We have mandatory mipi config blocks. Initialize as generic panel */ |
3cf05076 | 1757 | panel->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID; |
0f8689f5 JN |
1758 | } |
1759 | ||
5db72099 JN |
1760 | /* Find the sequence block and size for the given panel. */ |
1761 | static const u8 * | |
ff9bc20c VS |
1762 | find_panel_sequence_block(struct drm_i915_private *i915, |
1763 | const struct bdb_mipi_sequence *sequence, | |
2a33d934 | 1764 | u16 panel_id, u32 *seq_size) |
5db72099 JN |
1765 | { |
1766 | u32 total = get_blocksize(sequence); | |
1767 | const u8 *data = &sequence->data[0]; | |
1768 | u8 current_id; | |
2a33d934 JN |
1769 | u32 current_size; |
1770 | int header_size = sequence->version >= 3 ? 5 : 3; | |
5db72099 JN |
1771 | int index = 0; |
1772 | int i; | |
1773 | ||
2a33d934 JN |
1774 | /* skip new block size */ |
1775 | if (sequence->version >= 3) | |
1776 | data += 4; | |
1777 | ||
1778 | for (i = 0; i < MAX_MIPI_CONFIGURATIONS && index < total; i++) { | |
1779 | if (index + header_size > total) { | |
ff9bc20c | 1780 | drm_err(&i915->drm, "Invalid sequence block (header)\n"); |
2a33d934 JN |
1781 | return NULL; |
1782 | } | |
1783 | ||
5db72099 | 1784 | current_id = *(data + index); |
2a33d934 JN |
1785 | if (sequence->version >= 3) |
1786 | current_size = *((const u32 *)(data + index + 1)); | |
1787 | else | |
1788 | current_size = *((const u16 *)(data + index + 1)); | |
5db72099 | 1789 | |
2a33d934 | 1790 | index += header_size; |
5db72099 JN |
1791 | |
1792 | if (index + current_size > total) { | |
ff9bc20c | 1793 | drm_err(&i915->drm, "Invalid sequence block\n"); |
5db72099 JN |
1794 | return NULL; |
1795 | } | |
1796 | ||
1797 | if (current_id == panel_id) { | |
1798 | *seq_size = current_size; | |
1799 | return data + index; | |
1800 | } | |
1801 | ||
1802 | index += current_size; | |
1803 | } | |
1804 | ||
ff9bc20c | 1805 | drm_err(&i915->drm, "Sequence block detected but no valid configuration\n"); |
5db72099 JN |
1806 | |
1807 | return NULL; | |
1808 | } | |
1809 | ||
ff9bc20c VS |
1810 | static int goto_next_sequence(struct drm_i915_private *i915, |
1811 | const u8 *data, int index, int total) | |
8d3ed2f3 JN |
1812 | { |
1813 | u16 len; | |
1814 | ||
1815 | /* Skip Sequence Byte. */ | |
1816 | for (index = index + 1; index < total; index += len) { | |
1817 | u8 operation_byte = *(data + index); | |
1818 | index++; | |
1819 | ||
1820 | switch (operation_byte) { | |
1821 | case MIPI_SEQ_ELEM_END: | |
1822 | return index; | |
1823 | case MIPI_SEQ_ELEM_SEND_PKT: | |
1824 | if (index + 4 > total) | |
1825 | return 0; | |
1826 | ||
1827 | len = *((const u16 *)(data + index + 2)) + 4; | |
1828 | break; | |
1829 | case MIPI_SEQ_ELEM_DELAY: | |
1830 | len = 4; | |
1831 | break; | |
1832 | case MIPI_SEQ_ELEM_GPIO: | |
1833 | len = 2; | |
1834 | break; | |
f4d64936 JN |
1835 | case MIPI_SEQ_ELEM_I2C: |
1836 | if (index + 7 > total) | |
1837 | return 0; | |
1838 | len = *(data + index + 6) + 7; | |
1839 | break; | |
8d3ed2f3 | 1840 | default: |
ff9bc20c | 1841 | drm_err(&i915->drm, "Unknown operation byte\n"); |
8d3ed2f3 JN |
1842 | return 0; |
1843 | } | |
1844 | } | |
1845 | ||
1846 | return 0; | |
1847 | } | |
1848 | ||
ff9bc20c VS |
1849 | static int goto_next_sequence_v3(struct drm_i915_private *i915, |
1850 | const u8 *data, int index, int total) | |
2a33d934 JN |
1851 | { |
1852 | int seq_end; | |
1853 | u16 len; | |
6765bd6d | 1854 | u32 size_of_sequence; |
2a33d934 JN |
1855 | |
1856 | /* | |
1857 | * Could skip sequence based on Size of Sequence alone, but also do some | |
1858 | * checking on the structure. | |
1859 | */ | |
1860 | if (total < 5) { | |
ff9bc20c | 1861 | drm_err(&i915->drm, "Too small sequence size\n"); |
2a33d934 JN |
1862 | return 0; |
1863 | } | |
1864 | ||
6765bd6d JN |
1865 | /* Skip Sequence Byte. */ |
1866 | index++; | |
1867 | ||
1868 | /* | |
1869 | * Size of Sequence. Excludes the Sequence Byte and the size itself, | |
1870 | * includes MIPI_SEQ_ELEM_END byte, excludes the final MIPI_SEQ_END | |
1871 | * byte. | |
1872 | */ | |
0ede0141 | 1873 | size_of_sequence = *((const u32 *)(data + index)); |
6765bd6d JN |
1874 | index += 4; |
1875 | ||
1876 | seq_end = index + size_of_sequence; | |
2a33d934 | 1877 | if (seq_end > total) { |
ff9bc20c | 1878 | drm_err(&i915->drm, "Invalid sequence size\n"); |
2a33d934 JN |
1879 | return 0; |
1880 | } | |
1881 | ||
6765bd6d | 1882 | for (; index < total; index += len) { |
2a33d934 JN |
1883 | u8 operation_byte = *(data + index); |
1884 | index++; | |
1885 | ||
1886 | if (operation_byte == MIPI_SEQ_ELEM_END) { | |
1887 | if (index != seq_end) { | |
ff9bc20c | 1888 | drm_err(&i915->drm, "Invalid element structure\n"); |
2a33d934 JN |
1889 | return 0; |
1890 | } | |
1891 | return index; | |
1892 | } | |
1893 | ||
1894 | len = *(data + index); | |
1895 | index++; | |
1896 | ||
1897 | /* | |
1898 | * FIXME: Would be nice to check elements like for v1/v2 in | |
1899 | * goto_next_sequence() above. | |
1900 | */ | |
1901 | switch (operation_byte) { | |
1902 | case MIPI_SEQ_ELEM_SEND_PKT: | |
1903 | case MIPI_SEQ_ELEM_DELAY: | |
1904 | case MIPI_SEQ_ELEM_GPIO: | |
1905 | case MIPI_SEQ_ELEM_I2C: | |
1906 | case MIPI_SEQ_ELEM_SPI: | |
1907 | case MIPI_SEQ_ELEM_PMIC: | |
1908 | break; | |
1909 | default: | |
ff9bc20c VS |
1910 | drm_err(&i915->drm, "Unknown operation byte %u\n", |
1911 | operation_byte); | |
2a33d934 JN |
1912 | break; |
1913 | } | |
1914 | } | |
1915 | ||
1916 | return 0; | |
1917 | } | |
1918 | ||
fb38e7ad HG |
1919 | /* |
1920 | * Get len of pre-fixed deassert fragment from a v1 init OTP sequence, | |
1921 | * skip all delay + gpio operands and stop at the first DSI packet op. | |
1922 | */ | |
3cf05076 VS |
1923 | static int get_init_otp_deassert_fragment_len(struct drm_i915_private *i915, |
1924 | struct intel_panel *panel) | |
fb38e7ad | 1925 | { |
3cf05076 | 1926 | const u8 *data = panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; |
fb38e7ad HG |
1927 | int index, len; |
1928 | ||
dbd440d8 | 1929 | if (drm_WARN_ON(&i915->drm, |
3cf05076 | 1930 | !data || panel->vbt.dsi.seq_version != 1)) |
fb38e7ad HG |
1931 | return 0; |
1932 | ||
1933 | /* index = 1 to skip sequence byte */ | |
1934 | for (index = 1; data[index] != MIPI_SEQ_ELEM_END; index += len) { | |
1935 | switch (data[index]) { | |
1936 | case MIPI_SEQ_ELEM_SEND_PKT: | |
1937 | return index == 1 ? 0 : index; | |
1938 | case MIPI_SEQ_ELEM_DELAY: | |
1939 | len = 5; /* 1 byte for operand + uint32 */ | |
1940 | break; | |
1941 | case MIPI_SEQ_ELEM_GPIO: | |
1942 | len = 3; /* 1 byte for op, 1 for gpio_nr, 1 for value */ | |
1943 | break; | |
1944 | default: | |
1945 | return 0; | |
1946 | } | |
1947 | } | |
1948 | ||
1949 | return 0; | |
1950 | } | |
1951 | ||
1952 | /* | |
1953 | * Some v1 VBT MIPI sequences do the deassert in the init OTP sequence. | |
1954 | * The deassert must be done before calling intel_dsi_device_ready, so for | |
1955 | * these devices we split the init OTP sequence into a deassert sequence and | |
1956 | * the actual init OTP part. | |
1957 | */ | |
3cf05076 VS |
1958 | static void fixup_mipi_sequences(struct drm_i915_private *i915, |
1959 | struct intel_panel *panel) | |
fb38e7ad HG |
1960 | { |
1961 | u8 *init_otp; | |
1962 | int len; | |
1963 | ||
1964 | /* Limit this to VLV for now. */ | |
dbd440d8 | 1965 | if (!IS_VALLEYVIEW(i915)) |
fb38e7ad HG |
1966 | return; |
1967 | ||
1968 | /* Limit this to v1 vid-mode sequences */ | |
3cf05076 VS |
1969 | if (panel->vbt.dsi.config->is_cmd_mode || |
1970 | panel->vbt.dsi.seq_version != 1) | |
fb38e7ad HG |
1971 | return; |
1972 | ||
1973 | /* Only do this if there are otp and assert seqs and no deassert seq */ | |
3cf05076 VS |
1974 | if (!panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] || |
1975 | !panel->vbt.dsi.sequence[MIPI_SEQ_ASSERT_RESET] || | |
1976 | panel->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) | |
fb38e7ad HG |
1977 | return; |
1978 | ||
1979 | /* The deassert-sequence ends at the first DSI packet */ | |
3cf05076 | 1980 | len = get_init_otp_deassert_fragment_len(i915, panel); |
fb38e7ad HG |
1981 | if (!len) |
1982 | return; | |
1983 | ||
dbd440d8 | 1984 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 1985 | "Using init OTP fragment to deassert reset\n"); |
fb38e7ad HG |
1986 | |
1987 | /* Copy the fragment, update seq byte and terminate it */ | |
3cf05076 VS |
1988 | init_otp = (u8 *)panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP]; |
1989 | panel->vbt.dsi.deassert_seq = kmemdup(init_otp, len + 1, GFP_KERNEL); | |
1990 | if (!panel->vbt.dsi.deassert_seq) | |
fb38e7ad | 1991 | return; |
3cf05076 VS |
1992 | panel->vbt.dsi.deassert_seq[0] = MIPI_SEQ_DEASSERT_RESET; |
1993 | panel->vbt.dsi.deassert_seq[len] = MIPI_SEQ_ELEM_END; | |
fb38e7ad | 1994 | /* Use the copy for deassert */ |
3cf05076 VS |
1995 | panel->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET] = |
1996 | panel->vbt.dsi.deassert_seq; | |
fb38e7ad HG |
1997 | /* Replace the last byte of the fragment with init OTP seq byte */ |
1998 | init_otp[len - 1] = MIPI_SEQ_INIT_OTP; | |
1999 | /* And make MIPI_MIPI_SEQ_INIT_OTP point to it */ | |
3cf05076 | 2000 | panel->vbt.dsi.sequence[MIPI_SEQ_INIT_OTP] = init_otp + len - 1; |
fb38e7ad HG |
2001 | } |
2002 | ||
0f8689f5 | 2003 | static void |
3cf05076 VS |
2004 | parse_mipi_sequence(struct drm_i915_private *i915, |
2005 | struct intel_panel *panel) | |
0f8689f5 | 2006 | { |
3cf05076 | 2007 | int panel_type = panel->vbt.panel_type; |
0f8689f5 JN |
2008 | const struct bdb_mipi_sequence *sequence; |
2009 | const u8 *seq_data; | |
2a33d934 | 2010 | u32 seq_size; |
0f8689f5 | 2011 | u8 *data; |
8d3ed2f3 | 2012 | int index = 0; |
0f8689f5 JN |
2013 | |
2014 | /* Only our generic panel driver uses the sequence block. */ | |
3cf05076 | 2015 | if (panel->vbt.dsi.panel_id != MIPI_DSI_GENERIC_PANEL_ID) |
0f8689f5 | 2016 | return; |
d3b542fc | 2017 | |
0a93eeb5 | 2018 | sequence = bdb_find_section(i915, BDB_MIPI_SEQUENCE); |
d3b542fc | 2019 | if (!sequence) { |
dbd440d8 | 2020 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 2021 | "No MIPI Sequence found, parsing complete\n"); |
d3b542fc SK |
2022 | return; |
2023 | } | |
2024 | ||
cd67d226 | 2025 | /* Fail gracefully for forward incompatible sequence block. */ |
2a33d934 | 2026 | if (sequence->version >= 4) { |
dbd440d8 | 2027 | drm_err(&i915->drm, |
e92cbf38 WK |
2028 | "Unable to parse MIPI Sequence Block v%u\n", |
2029 | sequence->version); | |
cd67d226 JN |
2030 | return; |
2031 | } | |
2032 | ||
dbd440d8 | 2033 | drm_dbg(&i915->drm, "Found MIPI sequence block v%u\n", |
e92cbf38 | 2034 | sequence->version); |
d3b542fc | 2035 | |
ff9bc20c | 2036 | seq_data = find_panel_sequence_block(i915, sequence, panel_type, &seq_size); |
5db72099 | 2037 | if (!seq_data) |
d3b542fc | 2038 | return; |
d3b542fc | 2039 | |
8d3ed2f3 JN |
2040 | data = kmemdup(seq_data, seq_size, GFP_KERNEL); |
2041 | if (!data) | |
d3b542fc SK |
2042 | return; |
2043 | ||
8d3ed2f3 JN |
2044 | /* Parse the sequences, store pointers to each sequence. */ |
2045 | for (;;) { | |
2046 | u8 seq_id = *(data + index); | |
2047 | if (seq_id == MIPI_SEQ_END) | |
2048 | break; | |
d3b542fc | 2049 | |
8d3ed2f3 | 2050 | if (seq_id >= MIPI_SEQ_MAX) { |
dbd440d8 | 2051 | drm_err(&i915->drm, "Unknown sequence %u\n", |
e92cbf38 | 2052 | seq_id); |
d3b542fc SK |
2053 | goto err; |
2054 | } | |
2055 | ||
4b4f497e JN |
2056 | /* Log about presence of sequences we won't run. */ |
2057 | if (seq_id == MIPI_SEQ_TEAR_ON || seq_id == MIPI_SEQ_TEAR_OFF) | |
dbd440d8 | 2058 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 2059 | "Unsupported sequence %u\n", seq_id); |
4b4f497e | 2060 | |
3cf05076 | 2061 | panel->vbt.dsi.sequence[seq_id] = data + index; |
d3b542fc | 2062 | |
2a33d934 | 2063 | if (sequence->version >= 3) |
ff9bc20c | 2064 | index = goto_next_sequence_v3(i915, data, index, seq_size); |
2a33d934 | 2065 | else |
ff9bc20c | 2066 | index = goto_next_sequence(i915, data, index, seq_size); |
8d3ed2f3 | 2067 | if (!index) { |
dbd440d8 | 2068 | drm_err(&i915->drm, "Invalid sequence %u\n", |
e92cbf38 | 2069 | seq_id); |
d3b542fc SK |
2070 | goto err; |
2071 | } | |
d3b542fc SK |
2072 | } |
2073 | ||
3cf05076 VS |
2074 | panel->vbt.dsi.data = data; |
2075 | panel->vbt.dsi.size = seq_size; | |
2076 | panel->vbt.dsi.seq_version = sequence->version; | |
8d3ed2f3 | 2077 | |
3cf05076 | 2078 | fixup_mipi_sequences(i915, panel); |
fb38e7ad | 2079 | |
dbd440d8 | 2080 | drm_dbg(&i915->drm, "MIPI related VBT parsing complete\n"); |
d3b542fc | 2081 | return; |
d3b542fc | 2082 | |
8d3ed2f3 JN |
2083 | err: |
2084 | kfree(data); | |
3cf05076 | 2085 | memset(panel->vbt.dsi.sequence, 0, sizeof(panel->vbt.dsi.sequence)); |
d17c5443 SK |
2086 | } |
2087 | ||
6e0d46e9 | 2088 | static void |
e163cfb4 | 2089 | parse_compression_parameters(struct drm_i915_private *i915) |
6e0d46e9 JN |
2090 | { |
2091 | const struct bdb_compression_parameters *params; | |
3162d057 | 2092 | struct intel_bios_encoder_data *devdata; |
6e0d46e9 JN |
2093 | u16 block_size; |
2094 | int index; | |
2095 | ||
a434689c | 2096 | if (i915->display.vbt.version < 198) |
6e0d46e9 JN |
2097 | return; |
2098 | ||
0a93eeb5 | 2099 | params = bdb_find_section(i915, BDB_COMPRESSION_PARAMETERS); |
6e0d46e9 JN |
2100 | if (params) { |
2101 | /* Sanity checks */ | |
2102 | if (params->entry_size != sizeof(params->data[0])) { | |
e92cbf38 WK |
2103 | drm_dbg_kms(&i915->drm, |
2104 | "VBT: unsupported compression param entry size\n"); | |
6e0d46e9 JN |
2105 | return; |
2106 | } | |
2107 | ||
2108 | block_size = get_blocksize(params); | |
2109 | if (block_size < sizeof(*params)) { | |
e92cbf38 WK |
2110 | drm_dbg_kms(&i915->drm, |
2111 | "VBT: expected 16 compression param entries\n"); | |
6e0d46e9 JN |
2112 | return; |
2113 | } | |
2114 | } | |
2115 | ||
a434689c | 2116 | list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { |
d24b3475 | 2117 | const struct child_device_config *child = &devdata->child; |
6e0d46e9 JN |
2118 | |
2119 | if (!child->compression_enable) | |
2120 | continue; | |
2121 | ||
2122 | if (!params) { | |
e92cbf38 WK |
2123 | drm_dbg_kms(&i915->drm, |
2124 | "VBT: compression params not available\n"); | |
6e0d46e9 JN |
2125 | continue; |
2126 | } | |
2127 | ||
2128 | if (child->compression_method_cps) { | |
e92cbf38 WK |
2129 | drm_dbg_kms(&i915->drm, |
2130 | "VBT: CPS compression not supported\n"); | |
6e0d46e9 JN |
2131 | continue; |
2132 | } | |
2133 | ||
2134 | index = child->compression_structure_index; | |
2135 | ||
2136 | devdata->dsc = kmemdup(¶ms->data[index], | |
2137 | sizeof(*devdata->dsc), GFP_KERNEL); | |
2138 | } | |
2139 | } | |
2140 | ||
ff9bc20c | 2141 | static u8 translate_iboost(struct drm_i915_private *i915, u8 val) |
75067dde AK |
2142 | { |
2143 | static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */ | |
2144 | ||
2145 | if (val >= ARRAY_SIZE(mapping)) { | |
ff9bc20c VS |
2146 | drm_dbg_kms(&i915->drm, |
2147 | "Unsupported I_boost value found in VBT (%d), display may not work properly\n", val); | |
75067dde AK |
2148 | return 0; |
2149 | } | |
2150 | return mapping[val]; | |
2151 | } | |
2152 | ||
9e1dbc1a JN |
2153 | static const u8 cnp_ddc_pin_map[] = { |
2154 | [0] = 0, /* N/A */ | |
3d7af6cf VS |
2155 | [GMBUS_PIN_1_BXT] = DDC_BUS_DDI_B, |
2156 | [GMBUS_PIN_2_BXT] = DDC_BUS_DDI_C, | |
2157 | [GMBUS_PIN_4_CNP] = DDC_BUS_DDI_D, /* sic */ | |
2158 | [GMBUS_PIN_3_BXT] = DDC_BUS_DDI_F, /* sic */ | |
9e1dbc1a JN |
2159 | }; |
2160 | ||
2161 | static const u8 icp_ddc_pin_map[] = { | |
3d7af6cf VS |
2162 | [GMBUS_PIN_1_BXT] = ICL_DDC_BUS_DDI_A, |
2163 | [GMBUS_PIN_2_BXT] = ICL_DDC_BUS_DDI_B, | |
2164 | [GMBUS_PIN_3_BXT] = TGL_DDC_BUS_DDI_C, | |
2165 | [GMBUS_PIN_9_TC1_ICP] = ICL_DDC_BUS_PORT_1, | |
2166 | [GMBUS_PIN_10_TC2_ICP] = ICL_DDC_BUS_PORT_2, | |
2167 | [GMBUS_PIN_11_TC3_ICP] = ICL_DDC_BUS_PORT_3, | |
2168 | [GMBUS_PIN_12_TC4_ICP] = ICL_DDC_BUS_PORT_4, | |
2169 | [GMBUS_PIN_13_TC5_TGP] = TGL_DDC_BUS_PORT_5, | |
2170 | [GMBUS_PIN_14_TC6_TGP] = TGL_DDC_BUS_PORT_6, | |
9e1dbc1a JN |
2171 | }; |
2172 | ||
2173 | static const u8 rkl_pch_tgp_ddc_pin_map[] = { | |
3d7af6cf VS |
2174 | [GMBUS_PIN_1_BXT] = ICL_DDC_BUS_DDI_A, |
2175 | [GMBUS_PIN_2_BXT] = ICL_DDC_BUS_DDI_B, | |
2176 | [GMBUS_PIN_9_TC1_ICP] = RKL_DDC_BUS_DDI_D, | |
2177 | [GMBUS_PIN_10_TC2_ICP] = RKL_DDC_BUS_DDI_E, | |
9e1dbc1a JN |
2178 | }; |
2179 | ||
2180 | static const u8 adls_ddc_pin_map[] = { | |
3d7af6cf VS |
2181 | [GMBUS_PIN_1_BXT] = ICL_DDC_BUS_DDI_A, |
2182 | [GMBUS_PIN_9_TC1_ICP] = ADLS_DDC_BUS_PORT_TC1, | |
2183 | [GMBUS_PIN_10_TC2_ICP] = ADLS_DDC_BUS_PORT_TC2, | |
2184 | [GMBUS_PIN_11_TC3_ICP] = ADLS_DDC_BUS_PORT_TC3, | |
2185 | [GMBUS_PIN_12_TC4_ICP] = ADLS_DDC_BUS_PORT_TC4, | |
9e1dbc1a JN |
2186 | }; |
2187 | ||
2188 | static const u8 gen9bc_tgp_ddc_pin_map[] = { | |
3d7af6cf VS |
2189 | [GMBUS_PIN_2_BXT] = DDC_BUS_DDI_B, |
2190 | [GMBUS_PIN_9_TC1_ICP] = DDC_BUS_DDI_C, | |
2191 | [GMBUS_PIN_10_TC2_ICP] = DDC_BUS_DDI_D, | |
9e1dbc1a JN |
2192 | }; |
2193 | ||
af10ec31 | 2194 | static const u8 adlp_ddc_pin_map[] = { |
3d7af6cf VS |
2195 | [GMBUS_PIN_1_BXT] = ICL_DDC_BUS_DDI_A, |
2196 | [GMBUS_PIN_2_BXT] = ICL_DDC_BUS_DDI_B, | |
2197 | [GMBUS_PIN_9_TC1_ICP] = ADLP_DDC_BUS_PORT_TC1, | |
2198 | [GMBUS_PIN_10_TC2_ICP] = ADLP_DDC_BUS_PORT_TC2, | |
2199 | [GMBUS_PIN_11_TC3_ICP] = ADLP_DDC_BUS_PORT_TC3, | |
2200 | [GMBUS_PIN_12_TC4_ICP] = ADLP_DDC_BUS_PORT_TC4, | |
af10ec31 TU |
2201 | }; |
2202 | ||
9e1dbc1a JN |
2203 | static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) |
2204 | { | |
2205 | const u8 *ddc_pin_map; | |
3d7af6cf | 2206 | int i, n_entries; |
9e1dbc1a | 2207 | |
562f3383 CT |
2208 | if (IS_DGFX(i915)) |
2209 | return vbt_pin; | |
2210 | ||
93cbc1ac | 2211 | if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) { |
af10ec31 TU |
2212 | ddc_pin_map = adlp_ddc_pin_map; |
2213 | n_entries = ARRAY_SIZE(adlp_ddc_pin_map); | |
2214 | } else if (IS_ALDERLAKE_S(i915)) { | |
9e1dbc1a JN |
2215 | ddc_pin_map = adls_ddc_pin_map; |
2216 | n_entries = ARRAY_SIZE(adls_ddc_pin_map); | |
9e1dbc1a JN |
2217 | } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) { |
2218 | ddc_pin_map = rkl_pch_tgp_ddc_pin_map; | |
2219 | n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); | |
2220 | } else if (HAS_PCH_TGP(i915) && DISPLAY_VER(i915) == 9) { | |
2221 | ddc_pin_map = gen9bc_tgp_ddc_pin_map; | |
2222 | n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map); | |
2223 | } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { | |
2224 | ddc_pin_map = icp_ddc_pin_map; | |
2225 | n_entries = ARRAY_SIZE(icp_ddc_pin_map); | |
2226 | } else if (HAS_PCH_CNP(i915)) { | |
2227 | ddc_pin_map = cnp_ddc_pin_map; | |
2228 | n_entries = ARRAY_SIZE(cnp_ddc_pin_map); | |
2229 | } else { | |
2230 | /* Assuming direct map */ | |
2231 | return vbt_pin; | |
2232 | } | |
2233 | ||
3d7af6cf VS |
2234 | for (i = 0; i < n_entries; i++) { |
2235 | if (ddc_pin_map[i] == vbt_pin) | |
2236 | return i; | |
2237 | } | |
9e1dbc1a JN |
2238 | |
2239 | drm_dbg_kms(&i915->drm, | |
2240 | "Ignoring alternate pin: VBT claims DDC pin %d, which is not valid for this platform\n", | |
2241 | vbt_pin); | |
2242 | return 0; | |
2243 | } | |
2244 | ||
32c2bc89 VS |
2245 | static u8 dvo_port_type(u8 dvo_port) |
2246 | { | |
2247 | switch (dvo_port) { | |
2248 | case DVO_PORT_HDMIA: | |
2249 | case DVO_PORT_HDMIB: | |
2250 | case DVO_PORT_HDMIC: | |
2251 | case DVO_PORT_HDMID: | |
2252 | case DVO_PORT_HDMIE: | |
2253 | case DVO_PORT_HDMIF: | |
2254 | case DVO_PORT_HDMIG: | |
2255 | case DVO_PORT_HDMIH: | |
2256 | case DVO_PORT_HDMII: | |
2257 | return DVO_PORT_HDMIA; | |
2258 | case DVO_PORT_DPA: | |
2259 | case DVO_PORT_DPB: | |
2260 | case DVO_PORT_DPC: | |
2261 | case DVO_PORT_DPD: | |
2262 | case DVO_PORT_DPE: | |
2263 | case DVO_PORT_DPF: | |
2264 | case DVO_PORT_DPG: | |
2265 | case DVO_PORT_DPH: | |
2266 | case DVO_PORT_DPI: | |
2267 | return DVO_PORT_DPA; | |
2268 | case DVO_PORT_MIPIA: | |
2269 | case DVO_PORT_MIPIB: | |
2270 | case DVO_PORT_MIPIC: | |
2271 | case DVO_PORT_MIPID: | |
2272 | return DVO_PORT_MIPIA; | |
2273 | default: | |
2274 | return dvo_port; | |
2275 | } | |
2276 | } | |
2277 | ||
4628142a LDM |
2278 | static enum port __dvo_port_to_port(int n_ports, int n_dvo, |
2279 | const int port_mapping[][3], u8 dvo_port) | |
6acab15a | 2280 | { |
b024ab9b JN |
2281 | enum port port; |
2282 | int i; | |
6acab15a | 2283 | |
4628142a LDM |
2284 | for (port = PORT_A; port < n_ports; port++) { |
2285 | for (i = 0; i < n_dvo; i++) { | |
2286 | if (port_mapping[port][i] == -1) | |
6acab15a PZ |
2287 | break; |
2288 | ||
4628142a | 2289 | if (dvo_port == port_mapping[port][i]) |
b024ab9b | 2290 | return port; |
6acab15a PZ |
2291 | } |
2292 | } | |
b024ab9b JN |
2293 | |
2294 | return PORT_NONE; | |
2295 | } | |
2296 | ||
dbd440d8 | 2297 | static enum port dvo_port_to_port(struct drm_i915_private *i915, |
4628142a LDM |
2298 | u8 dvo_port) |
2299 | { | |
2300 | /* | |
2301 | * Each DDI port can have more than one value on the "DVO Port" field, | |
2302 | * so look for all the possible values for each port. | |
2303 | */ | |
2304 | static const int port_mapping[][3] = { | |
2305 | [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, | |
2306 | [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, | |
2307 | [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, | |
2308 | [PORT_D] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, | |
8c1a8f12 | 2309 | [PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT }, |
4628142a LDM |
2310 | [PORT_F] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 }, |
2311 | [PORT_G] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 }, | |
176430cc VS |
2312 | [PORT_H] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 }, |
2313 | [PORT_I] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 }, | |
4628142a LDM |
2314 | }; |
2315 | /* | |
1d8ca002 VS |
2316 | * RKL VBT uses PHY based mapping. Combo PHYs A,B,C,D |
2317 | * map to DDI A,B,TC1,TC2 respectively. | |
4628142a LDM |
2318 | */ |
2319 | static const int rkl_port_mapping[][3] = { | |
2320 | [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, | |
2321 | [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, | |
2322 | [PORT_C] = { -1 }, | |
1d8ca002 VS |
2323 | [PORT_TC1] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, |
2324 | [PORT_TC2] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, | |
4628142a | 2325 | }; |
18c283df AS |
2326 | /* |
2327 | * Alderlake S ports used in the driver are PORT_A, PORT_D, PORT_E, | |
2328 | * PORT_F and PORT_G, we need to map that to correct VBT sections. | |
2329 | */ | |
2330 | static const int adls_port_mapping[][3] = { | |
2331 | [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, | |
2332 | [PORT_B] = { -1 }, | |
2333 | [PORT_C] = { -1 }, | |
2334 | [PORT_TC1] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, | |
2335 | [PORT_TC2] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, | |
2336 | [PORT_TC3] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, | |
2337 | [PORT_TC4] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 }, | |
2338 | }; | |
eeb63c54 JRS |
2339 | static const int xelpd_port_mapping[][3] = { |
2340 | [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, | |
2341 | [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, | |
2342 | [PORT_C] = { DVO_PORT_HDMIC, DVO_PORT_DPC, -1 }, | |
2343 | [PORT_D_XELPD] = { DVO_PORT_HDMID, DVO_PORT_DPD, -1 }, | |
2344 | [PORT_E_XELPD] = { DVO_PORT_HDMIE, DVO_PORT_DPE, -1 }, | |
2345 | [PORT_TC1] = { DVO_PORT_HDMIF, DVO_PORT_DPF, -1 }, | |
2346 | [PORT_TC2] = { DVO_PORT_HDMIG, DVO_PORT_DPG, -1 }, | |
2347 | [PORT_TC3] = { DVO_PORT_HDMIH, DVO_PORT_DPH, -1 }, | |
2348 | [PORT_TC4] = { DVO_PORT_HDMII, DVO_PORT_DPI, -1 }, | |
2349 | }; | |
4628142a | 2350 | |
612dc414 | 2351 | if (DISPLAY_VER(i915) >= 13) |
eeb63c54 JRS |
2352 | return __dvo_port_to_port(ARRAY_SIZE(xelpd_port_mapping), |
2353 | ARRAY_SIZE(xelpd_port_mapping[0]), | |
2354 | xelpd_port_mapping, | |
2355 | dvo_port); | |
2356 | else if (IS_ALDERLAKE_S(i915)) | |
18c283df AS |
2357 | return __dvo_port_to_port(ARRAY_SIZE(adls_port_mapping), |
2358 | ARRAY_SIZE(adls_port_mapping[0]), | |
2359 | adls_port_mapping, | |
2360 | dvo_port); | |
dbd440d8 | 2361 | else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) |
4628142a LDM |
2362 | return __dvo_port_to_port(ARRAY_SIZE(rkl_port_mapping), |
2363 | ARRAY_SIZE(rkl_port_mapping[0]), | |
2364 | rkl_port_mapping, | |
2365 | dvo_port); | |
2366 | else | |
2367 | return __dvo_port_to_port(ARRAY_SIZE(port_mapping), | |
2368 | ARRAY_SIZE(port_mapping[0]), | |
2369 | port_mapping, | |
2370 | dvo_port); | |
2371 | } | |
2372 | ||
118b5c13 VS |
2373 | static enum port |
2374 | dsi_dvo_port_to_port(struct drm_i915_private *i915, u8 dvo_port) | |
2375 | { | |
2376 | switch (dvo_port) { | |
2377 | case DVO_PORT_MIPIA: | |
2378 | return PORT_A; | |
2379 | case DVO_PORT_MIPIC: | |
2380 | if (DISPLAY_VER(i915) >= 11) | |
2381 | return PORT_B; | |
2382 | else | |
2383 | return PORT_C; | |
2384 | default: | |
2385 | return PORT_NONE; | |
2386 | } | |
2387 | } | |
2388 | ||
021a62a5 | 2389 | enum port intel_bios_encoder_port(const struct intel_bios_encoder_data *devdata) |
d84b1945 VS |
2390 | { |
2391 | struct drm_i915_private *i915 = devdata->i915; | |
2392 | const struct child_device_config *child = &devdata->child; | |
2393 | enum port port; | |
2394 | ||
2395 | port = dvo_port_to_port(i915, child->dvo_port); | |
2396 | if (port == PORT_NONE && DISPLAY_VER(i915) >= 11) | |
2397 | port = dsi_dvo_port_to_port(i915, child->dvo_port); | |
2398 | ||
2399 | return port; | |
2400 | } | |
2401 | ||
b60e320b LS |
2402 | static int parse_bdb_230_dp_max_link_rate(const int vbt_max_link_rate) |
2403 | { | |
2404 | switch (vbt_max_link_rate) { | |
2405 | default: | |
2406 | case BDB_230_VBT_DP_MAX_LINK_RATE_DEF: | |
2407 | return 0; | |
2408 | case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR20: | |
2409 | return 2000000; | |
2410 | case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR13P5: | |
2411 | return 1350000; | |
2412 | case BDB_230_VBT_DP_MAX_LINK_RATE_UHBR10: | |
2413 | return 1000000; | |
2414 | case BDB_230_VBT_DP_MAX_LINK_RATE_HBR3: | |
2415 | return 810000; | |
2416 | case BDB_230_VBT_DP_MAX_LINK_RATE_HBR2: | |
2417 | return 540000; | |
2418 | case BDB_230_VBT_DP_MAX_LINK_RATE_HBR: | |
2419 | return 270000; | |
2420 | case BDB_230_VBT_DP_MAX_LINK_RATE_LBR: | |
2421 | return 162000; | |
2422 | } | |
2423 | } | |
2424 | ||
2425 | static int parse_bdb_216_dp_max_link_rate(const int vbt_max_link_rate) | |
2426 | { | |
2427 | switch (vbt_max_link_rate) { | |
2428 | default: | |
2429 | case BDB_216_VBT_DP_MAX_LINK_RATE_HBR3: | |
2430 | return 810000; | |
2431 | case BDB_216_VBT_DP_MAX_LINK_RATE_HBR2: | |
2432 | return 540000; | |
2433 | case BDB_216_VBT_DP_MAX_LINK_RATE_HBR: | |
2434 | return 270000; | |
2435 | case BDB_216_VBT_DP_MAX_LINK_RATE_LBR: | |
2436 | return 162000; | |
2437 | } | |
2438 | } | |
2439 | ||
02107ef1 | 2440 | int intel_bios_dp_max_link_rate(const struct intel_bios_encoder_data *devdata) |
72337aac | 2441 | { |
a434689c | 2442 | if (!devdata || devdata->i915->display.vbt.version < 216) |
72337aac JN |
2443 | return 0; |
2444 | ||
a434689c | 2445 | if (devdata->i915->display.vbt.version >= 230) |
72337aac JN |
2446 | return parse_bdb_230_dp_max_link_rate(devdata->child.dp_max_link_rate); |
2447 | else | |
2448 | return parse_bdb_216_dp_max_link_rate(devdata->child.dp_max_link_rate); | |
2449 | } | |
2450 | ||
02107ef1 | 2451 | int intel_bios_dp_max_lane_count(const struct intel_bios_encoder_data *devdata) |
4182a311 VS |
2452 | { |
2453 | if (!devdata || devdata->i915->display.vbt.version < 244) | |
2454 | return 0; | |
2455 | ||
2456 | return devdata->child.dp_max_lane_count + 1; | |
2457 | } | |
2458 | ||
d0ab409d JN |
2459 | static void sanitize_device_type(struct intel_bios_encoder_data *devdata, |
2460 | enum port port) | |
2461 | { | |
2462 | struct drm_i915_private *i915 = devdata->i915; | |
2463 | bool is_hdmi; | |
2464 | ||
005e9537 | 2465 | if (port != PORT_A || DISPLAY_VER(i915) >= 12) |
d0ab409d JN |
2466 | return; |
2467 | ||
86996822 | 2468 | if (!intel_bios_encoder_supports_dvi(devdata)) |
d0ab409d JN |
2469 | return; |
2470 | ||
86996822 | 2471 | is_hdmi = intel_bios_encoder_supports_hdmi(devdata); |
d0ab409d JN |
2472 | |
2473 | drm_dbg_kms(&i915->drm, "VBT claims port A supports DVI%s, ignoring\n", | |
2474 | is_hdmi ? "/HDMI" : ""); | |
2475 | ||
2476 | devdata->child.device_type &= ~DEVICE_TYPE_TMDS_DVI_SIGNALING; | |
2477 | devdata->child.device_type |= DEVICE_TYPE_NOT_HDMI_OUTPUT; | |
2478 | } | |
2479 | ||
9e372744 VS |
2480 | static void sanitize_hdmi_level_shift(struct intel_bios_encoder_data *devdata, |
2481 | enum port port) | |
2482 | { | |
2483 | struct drm_i915_private *i915 = devdata->i915; | |
2484 | ||
2485 | if (!intel_bios_encoder_supports_dvi(devdata)) | |
2486 | return; | |
2487 | ||
2488 | /* | |
2489 | * Some BDW machines (eg. HP Pavilion 15-ab) shipped | |
2490 | * with a HSW VBT where the level shifter value goes | |
2491 | * up to 11, whereas the BDW max is 9. | |
2492 | */ | |
2493 | if (IS_BROADWELL(i915) && devdata->child.hdmi_level_shifter_value > 9) { | |
2494 | drm_dbg_kms(&i915->drm, "Bogus port %c VBT HDMI level shift %d, adjusting to %d\n", | |
2495 | port_name(port), devdata->child.hdmi_level_shifter_value, 9); | |
2496 | ||
2497 | devdata->child.hdmi_level_shifter_value = 9; | |
2498 | } | |
2499 | } | |
2500 | ||
d0ab409d JN |
2501 | static bool |
2502 | intel_bios_encoder_supports_crt(const struct intel_bios_encoder_data *devdata) | |
2503 | { | |
2504 | return devdata->child.device_type & DEVICE_TYPE_ANALOG_OUTPUT; | |
2505 | } | |
2506 | ||
45c0673a | 2507 | bool |
d0ab409d JN |
2508 | intel_bios_encoder_supports_dvi(const struct intel_bios_encoder_data *devdata) |
2509 | { | |
2510 | return devdata->child.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; | |
2511 | } | |
2512 | ||
45c0673a | 2513 | bool |
d0ab409d JN |
2514 | intel_bios_encoder_supports_hdmi(const struct intel_bios_encoder_data *devdata) |
2515 | { | |
2516 | return intel_bios_encoder_supports_dvi(devdata) && | |
2517 | (devdata->child.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0; | |
2518 | } | |
2519 | ||
45c0673a | 2520 | bool |
d0ab409d JN |
2521 | intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdata) |
2522 | { | |
2523 | return devdata->child.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT; | |
2524 | } | |
2525 | ||
9d4b7af5 | 2526 | bool |
d0ab409d JN |
2527 | intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata) |
2528 | { | |
2529 | return intel_bios_encoder_supports_dp(devdata) && | |
2530 | devdata->child.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR; | |
2531 | } | |
2532 | ||
021a62a5 | 2533 | bool |
ba00eb6a VS |
2534 | intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata) |
2535 | { | |
2536 | return devdata->child.device_type & DEVICE_TYPE_MIPI_OUTPUT; | |
2537 | } | |
2538 | ||
db5d650f VS |
2539 | bool |
2540 | intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata) | |
2541 | { | |
2542 | return devdata && HAS_LSPCON(devdata->i915) && devdata->child.lspcon; | |
2543 | } | |
2544 | ||
02107ef1 VS |
2545 | /* This is an index in the HDMI/DVI DDI buffer translation table, or -1 */ |
2546 | int intel_bios_hdmi_level_shift(const struct intel_bios_encoder_data *devdata) | |
a9a56e76 | 2547 | { |
d9c078d3 RS |
2548 | if (!devdata || devdata->i915->display.vbt.version < 158 || |
2549 | DISPLAY_VER(devdata->i915) >= 14) | |
a9a56e76 JN |
2550 | return -1; |
2551 | ||
2552 | return devdata->child.hdmi_level_shifter_value; | |
2553 | } | |
2554 | ||
02107ef1 | 2555 | int intel_bios_hdmi_max_tmds_clock(const struct intel_bios_encoder_data *devdata) |
6ba69981 | 2556 | { |
a434689c | 2557 | if (!devdata || devdata->i915->display.vbt.version < 204) |
6ba69981 JN |
2558 | return 0; |
2559 | ||
2560 | switch (devdata->child.hdmi_max_data_rate) { | |
2561 | default: | |
2562 | MISSING_CASE(devdata->child.hdmi_max_data_rate); | |
2563 | fallthrough; | |
2564 | case HDMI_MAX_DATA_RATE_PLATFORM: | |
2565 | return 0; | |
5708fe0d LS |
2566 | case HDMI_MAX_DATA_RATE_594: |
2567 | return 594000; | |
2568 | case HDMI_MAX_DATA_RATE_340: | |
2569 | return 340000; | |
2570 | case HDMI_MAX_DATA_RATE_300: | |
2571 | return 300000; | |
6ba69981 JN |
2572 | case HDMI_MAX_DATA_RATE_297: |
2573 | return 297000; | |
2574 | case HDMI_MAX_DATA_RATE_165: | |
2575 | return 165000; | |
2576 | } | |
2577 | } | |
2578 | ||
5a9d38b2 LDM |
2579 | static bool is_port_valid(struct drm_i915_private *i915, enum port port) |
2580 | { | |
2581 | /* | |
cad83b40 | 2582 | * On some ICL SKUs port F is not present, but broken VBTs mark |
5a9d38b2 LDM |
2583 | * the port as present. Only try to initialize port F for the |
2584 | * SKUs that may actually have it. | |
2585 | */ | |
cad83b40 LDM |
2586 | if (port == PORT_F && IS_ICELAKE(i915)) |
2587 | return IS_ICL_WITH_PORT_F(i915); | |
5a9d38b2 LDM |
2588 | |
2589 | return true; | |
2590 | } | |
2591 | ||
021a62a5 | 2592 | static void print_ddi_port(const struct intel_bios_encoder_data *devdata) |
b024ab9b | 2593 | { |
c78783f3 | 2594 | struct drm_i915_private *i915 = devdata->i915; |
d1dad6f4 | 2595 | const struct child_device_config *child = &devdata->child; |
ba00eb6a | 2596 | bool is_dvi, is_hdmi, is_dp, is_edp, is_dsi, is_crt, supports_typec_usb, supports_tbt; |
72337aac | 2597 | int dp_boost_level, dp_max_link_rate, hdmi_boost_level, hdmi_level_shift, max_tmds_clock; |
021a62a5 VS |
2598 | enum port port; |
2599 | ||
2600 | port = intel_bios_encoder_port(devdata); | |
2601 | if (port == PORT_NONE) | |
2602 | return; | |
554d6af5 | 2603 | |
d0ab409d JN |
2604 | is_dvi = intel_bios_encoder_supports_dvi(devdata); |
2605 | is_dp = intel_bios_encoder_supports_dp(devdata); | |
2606 | is_crt = intel_bios_encoder_supports_crt(devdata); | |
2607 | is_hdmi = intel_bios_encoder_supports_hdmi(devdata); | |
2608 | is_edp = intel_bios_encoder_supports_edp(devdata); | |
ba00eb6a | 2609 | is_dsi = intel_bios_encoder_supports_dsi(devdata); |
2ba7d7e0 | 2610 | |
f08fbe6a JN |
2611 | supports_typec_usb = intel_bios_encoder_supports_typec_usb(devdata); |
2612 | supports_tbt = intel_bios_encoder_supports_tbt(devdata); | |
38b3416f | 2613 | |
dbd440d8 | 2614 | drm_dbg_kms(&i915->drm, |
2bea1d7c | 2615 | "Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d DSI:%d DP++:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n", |
ba00eb6a | 2616 | port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp, is_dsi, |
2bea1d7c | 2617 | intel_bios_encoder_supports_dp_dual_mode(devdata), |
db5d650f | 2618 | intel_bios_encoder_is_lspcon(devdata), |
f08fbe6a | 2619 | supports_typec_usb, supports_tbt, |
e92cbf38 | 2620 | devdata->dsc != NULL); |
554d6af5 | 2621 | |
02107ef1 | 2622 | hdmi_level_shift = intel_bios_hdmi_level_shift(devdata); |
a9a56e76 | 2623 | if (hdmi_level_shift >= 0) { |
dbd440d8 | 2624 | drm_dbg_kms(&i915->drm, |
6ee8d381 | 2625 | "Port %c VBT HDMI level shift: %d\n", |
a9a56e76 | 2626 | port_name(port), hdmi_level_shift); |
6acab15a | 2627 | } |
75067dde | 2628 | |
02107ef1 | 2629 | max_tmds_clock = intel_bios_hdmi_max_tmds_clock(devdata); |
6ba69981 JN |
2630 | if (max_tmds_clock) |
2631 | drm_dbg_kms(&i915->drm, | |
2632 | "Port %c VBT HDMI max TMDS clock: %d kHz\n", | |
2633 | port_name(port), max_tmds_clock); | |
d6038611 | 2634 | |
c0a950d1 | 2635 | /* I_boost config for SKL and above */ |
02107ef1 | 2636 | dp_boost_level = intel_bios_dp_boost_level(devdata); |
c0a950d1 | 2637 | if (dp_boost_level) |
dbd440d8 | 2638 | drm_dbg_kms(&i915->drm, |
6ee8d381 | 2639 | "Port %c VBT (e)DP boost level: %d\n", |
c0a950d1 JN |
2640 | port_name(port), dp_boost_level); |
2641 | ||
02107ef1 | 2642 | hdmi_boost_level = intel_bios_hdmi_boost_level(devdata); |
c0a950d1 | 2643 | if (hdmi_boost_level) |
dbd440d8 | 2644 | drm_dbg_kms(&i915->drm, |
6ee8d381 | 2645 | "Port %c VBT HDMI boost level: %d\n", |
c0a950d1 | 2646 | port_name(port), hdmi_boost_level); |
99b91bda | 2647 | |
02107ef1 | 2648 | dp_max_link_rate = intel_bios_dp_max_link_rate(devdata); |
72337aac | 2649 | if (dp_max_link_rate) |
dbd440d8 | 2650 | drm_dbg_kms(&i915->drm, |
6ee8d381 | 2651 | "Port %c VBT DP max link rate: %d\n", |
72337aac | 2652 | port_name(port), dp_max_link_rate); |
429a0955 VS |
2653 | |
2654 | /* | |
2655 | * FIXME need to implement support for VBT | |
2656 | * vswing/preemph tables should this ever trigger. | |
2657 | */ | |
2658 | drm_WARN(&i915->drm, child->use_vbt_vswing, | |
2659 | "Port %c asks to use VBT vswing/preemph tables\n", | |
2660 | port_name(port)); | |
8d2ba05b JN |
2661 | } |
2662 | ||
2663 | static void parse_ddi_port(struct intel_bios_encoder_data *devdata) | |
2664 | { | |
2665 | struct drm_i915_private *i915 = devdata->i915; | |
8d2ba05b JN |
2666 | enum port port; |
2667 | ||
d84b1945 | 2668 | port = intel_bios_encoder_port(devdata); |
8d2ba05b JN |
2669 | if (port == PORT_NONE) |
2670 | return; | |
2671 | ||
2672 | if (!is_port_valid(i915, port)) { | |
2673 | drm_dbg_kms(&i915->drm, | |
2674 | "VBT reports port %c as supported, but that can't be true: skipping\n", | |
2675 | port_name(port)); | |
2676 | return; | |
2677 | } | |
2678 | ||
8d2ba05b | 2679 | sanitize_device_type(devdata, port); |
9e372744 | 2680 | sanitize_hdmi_level_shift(devdata, port); |
6acab15a PZ |
2681 | } |
2682 | ||
b90b6e41 VS |
2683 | static bool has_ddi_port_info(struct drm_i915_private *i915) |
2684 | { | |
594c504d | 2685 | return DISPLAY_VER(i915) >= 5 || IS_G4X(i915); |
b90b6e41 VS |
2686 | } |
2687 | ||
ef0096e4 | 2688 | static void parse_ddi_ports(struct drm_i915_private *i915) |
6acab15a | 2689 | { |
3162d057 | 2690 | struct intel_bios_encoder_data *devdata; |
6acab15a | 2691 | |
eb9fcf63 | 2692 | if (!has_ddi_port_info(i915)) |
6acab15a PZ |
2693 | return; |
2694 | ||
a434689c | 2695 | list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) |
c78783f3 | 2696 | parse_ddi_port(devdata); |
e61f294c | 2697 | |
021a62a5 VS |
2698 | list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) |
2699 | print_ddi_port(devdata); | |
6acab15a PZ |
2700 | } |
2701 | ||
6363ee6f | 2702 | static void |
e163cfb4 | 2703 | parse_general_definitions(struct drm_i915_private *i915) |
6363ee6f | 2704 | { |
e192839e | 2705 | const struct bdb_general_definitions *defs; |
3162d057 | 2706 | struct intel_bios_encoder_data *devdata; |
e192839e | 2707 | const struct child_device_config *child; |
0d9ef19b | 2708 | int i, child_device_num; |
e2d6cf7f DW |
2709 | u8 expected_size; |
2710 | u16 block_size; | |
b3ca1f43 | 2711 | int bus_pin; |
6363ee6f | 2712 | |
0a93eeb5 | 2713 | defs = bdb_find_section(i915, BDB_GENERAL_DEFINITIONS); |
e192839e | 2714 | if (!defs) { |
dbd440d8 | 2715 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 2716 | "No general definition block is found, no devices defined.\n"); |
6363ee6f ZY |
2717 | return; |
2718 | } | |
b3ca1f43 JN |
2719 | |
2720 | block_size = get_blocksize(defs); | |
2721 | if (block_size < sizeof(*defs)) { | |
dbd440d8 | 2722 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
2723 | "General definitions block too small (%u)\n", |
2724 | block_size); | |
b3ca1f43 JN |
2725 | return; |
2726 | } | |
2727 | ||
2728 | bus_pin = defs->crt_ddc_gmbus_pin; | |
dbd440d8 JN |
2729 | drm_dbg_kms(&i915->drm, "crt_ddc_bus_pin: %d\n", bus_pin); |
2730 | if (intel_gmbus_is_valid_pin(i915, bus_pin)) | |
a434689c | 2731 | i915->display.vbt.crt_ddc_pin = bus_pin; |
b3ca1f43 | 2732 | |
a434689c | 2733 | if (i915->display.vbt.version < 106) { |
7244f309 | 2734 | expected_size = 22; |
a434689c | 2735 | } else if (i915->display.vbt.version < 111) { |
52b69c84 | 2736 | expected_size = 27; |
a434689c | 2737 | } else if (i915->display.vbt.version < 195) { |
21907e72 | 2738 | expected_size = LEGACY_CHILD_DEVICE_CONFIG_SIZE; |
a434689c | 2739 | } else if (i915->display.vbt.version == 195) { |
e2d6cf7f | 2740 | expected_size = 37; |
a434689c | 2741 | } else if (i915->display.vbt.version <= 215) { |
e2d6cf7f | 2742 | expected_size = 38; |
0eaca1ed | 2743 | } else if (i915->display.vbt.version <= 250) { |
c4fb60b9 | 2744 | expected_size = 39; |
e2d6cf7f | 2745 | } else { |
c4fb60b9 JN |
2746 | expected_size = sizeof(*child); |
2747 | BUILD_BUG_ON(sizeof(*child) < 39); | |
dbd440d8 | 2748 | drm_dbg(&i915->drm, |
e92cbf38 | 2749 | "Expected child device config size for VBT version %u not known; assuming %u\n", |
a434689c | 2750 | i915->display.vbt.version, expected_size); |
e2d6cf7f DW |
2751 | } |
2752 | ||
e2d6cf7f | 2753 | /* Flag an error for unexpected size, but continue anyway. */ |
e192839e | 2754 | if (defs->child_dev_size != expected_size) |
dbd440d8 | 2755 | drm_err(&i915->drm, |
e92cbf38 | 2756 | "Unexpected child device config size %u (expected %u for VBT version %u)\n", |
a434689c | 2757 | defs->child_dev_size, expected_size, i915->display.vbt.version); |
e2d6cf7f | 2758 | |
52b69c84 | 2759 | /* The legacy sized child device config is the minimum we need. */ |
e192839e | 2760 | if (defs->child_dev_size < LEGACY_CHILD_DEVICE_CONFIG_SIZE) { |
dbd440d8 | 2761 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
2762 | "Child device config size %u is too small.\n", |
2763 | defs->child_dev_size); | |
52b69c84 VS |
2764 | return; |
2765 | } | |
2766 | ||
6363ee6f | 2767 | /* get the number of child device */ |
e192839e | 2768 | child_device_num = (block_size - sizeof(*defs)) / defs->child_dev_size; |
6363ee6f | 2769 | |
6363ee6f | 2770 | for (i = 0; i < child_device_num; i++) { |
e192839e | 2771 | child = child_device_ptr(defs, i); |
53f6b243 | 2772 | if (!child->device_type) |
6363ee6f | 2773 | continue; |
3e6bd011 | 2774 | |
dbd440d8 | 2775 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
2776 | "Found VBT child device with type 0x%x\n", |
2777 | child->device_type); | |
bdeb18db | 2778 | |
0d9ef19b JN |
2779 | devdata = kzalloc(sizeof(*devdata), GFP_KERNEL); |
2780 | if (!devdata) | |
2781 | break; | |
2782 | ||
7371fa34 JN |
2783 | devdata->i915 = i915; |
2784 | ||
e2d6cf7f DW |
2785 | /* |
2786 | * Copy as much as we know (sizeof) and is available | |
0d9ef19b JN |
2787 | * (child_dev_size) of the child device config. Accessing the |
2788 | * data must depend on VBT version. | |
e2d6cf7f | 2789 | */ |
0d9ef19b | 2790 | memcpy(&devdata->child, child, |
e192839e | 2791 | min_t(size_t, defs->child_dev_size, sizeof(*child))); |
0d9ef19b | 2792 | |
a434689c | 2793 | list_add_tail(&devdata->node, &i915->display.vbt.display_devices); |
6363ee6f | 2794 | } |
0d9ef19b | 2795 | |
a434689c | 2796 | if (list_empty(&i915->display.vbt.display_devices)) |
dbd440d8 | 2797 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 2798 | "no child dev is parsed from VBT\n"); |
6363ee6f | 2799 | } |
44834a67 | 2800 | |
bb1d1329 | 2801 | /* Common defaults which may be overridden by VBT. */ |
6a04002b | 2802 | static void |
dbd440d8 | 2803 | init_vbt_defaults(struct drm_i915_private *i915) |
6a04002b | 2804 | { |
a434689c | 2805 | i915->display.vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; |
6a04002b | 2806 | |
6a04002b | 2807 | /* general features */ |
a434689c JN |
2808 | i915->display.vbt.int_tv_support = 1; |
2809 | i915->display.vbt.int_crt_support = 1; | |
9a4114ff | 2810 | |
5255e2f8 | 2811 | /* driver features */ |
a434689c | 2812 | i915->display.vbt.int_lvds_support = 1; |
5255e2f8 | 2813 | |
9a4114ff | 2814 | /* Default to using SSC */ |
a434689c | 2815 | i915->display.vbt.lvds_use_ssc = 1; |
f69e5156 DL |
2816 | /* |
2817 | * Core/SandyBridge/IvyBridge use alternative (120MHz) reference | |
2818 | * clock for LVDS. | |
2819 | */ | |
a434689c JN |
2820 | i915->display.vbt.lvds_ssc_freq = intel_bios_ssc_frequency(i915, |
2821 | !HAS_PCH_SPLIT(i915)); | |
dbd440d8 | 2822 | drm_dbg_kms(&i915->drm, "Set default to SSC at %d kHz\n", |
a434689c | 2823 | i915->display.vbt.lvds_ssc_freq); |
bb1d1329 JN |
2824 | } |
2825 | ||
3cf05076 VS |
2826 | /* Common defaults which may be overridden by VBT. */ |
2827 | static void | |
2828 | init_vbt_panel_defaults(struct intel_panel *panel) | |
2829 | { | |
2830 | /* Default to having backlight */ | |
2831 | panel->vbt.backlight.present = true; | |
2832 | ||
2833 | /* LFP panel data */ | |
2834 | panel->vbt.lvds_dither = true; | |
2835 | } | |
2836 | ||
bb1d1329 JN |
2837 | /* Defaults to initialize only if there is no VBT. */ |
2838 | static void | |
dbd440d8 | 2839 | init_vbt_missing_defaults(struct drm_i915_private *i915) |
bb1d1329 JN |
2840 | { |
2841 | enum port port; | |
9b52aa72 RV |
2842 | int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | |
2843 | BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F); | |
bb1d1329 | 2844 | |
e20e4037 JN |
2845 | if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915)) |
2846 | return; | |
2847 | ||
3ae04c0c | 2848 | for_each_port_masked(port, ports) { |
3162d057 | 2849 | struct intel_bios_encoder_data *devdata; |
51f57481 | 2850 | struct child_device_config *child; |
dbd440d8 | 2851 | enum phy phy = intel_port_to_phy(i915, port); |
311a2094 | 2852 | |
828ccb31 ID |
2853 | /* |
2854 | * VBT has the TypeC mode (native,TBT/USB) and we don't want | |
2855 | * to detect it. | |
2856 | */ | |
dbd440d8 | 2857 | if (intel_phy_is_tc(i915, phy)) |
828ccb31 ID |
2858 | continue; |
2859 | ||
51f57481 JN |
2860 | /* Create fake child device config */ |
2861 | devdata = kzalloc(sizeof(*devdata), GFP_KERNEL); | |
2862 | if (!devdata) | |
2863 | break; | |
2864 | ||
7371fa34 | 2865 | devdata->i915 = i915; |
51f57481 JN |
2866 | child = &devdata->child; |
2867 | ||
2868 | if (port == PORT_F) | |
2869 | child->dvo_port = DVO_PORT_HDMIF; | |
2870 | else if (port == PORT_E) | |
2871 | child->dvo_port = DVO_PORT_HDMIE; | |
2872 | else | |
2873 | child->dvo_port = DVO_PORT_HDMIA + port; | |
2874 | ||
2875 | if (port != PORT_A && port != PORT_E) | |
2876 | child->device_type |= DEVICE_TYPE_TMDS_DVI_SIGNALING; | |
2877 | ||
2878 | if (port != PORT_E) | |
2879 | child->device_type |= DEVICE_TYPE_DISPLAYPORT_OUTPUT; | |
2880 | ||
2881 | if (port == PORT_A) | |
2882 | child->device_type |= DEVICE_TYPE_INTERNAL_CONNECTOR; | |
2883 | ||
a434689c | 2884 | list_add_tail(&devdata->node, &i915->display.vbt.display_devices); |
51f57481 JN |
2885 | |
2886 | drm_dbg_kms(&i915->drm, | |
2887 | "Generating default VBT child device with type 0x04%x on port %c\n", | |
2888 | child->device_type, port_name(port)); | |
6acab15a | 2889 | } |
51f57481 JN |
2890 | |
2891 | /* Bypass some minimum baseline VBT version checks */ | |
a434689c | 2892 | i915->display.vbt.version = 155; |
6a04002b SQ |
2893 | } |
2894 | ||
caf37fa4 JN |
2895 | static const struct bdb_header *get_bdb_header(const struct vbt_header *vbt) |
2896 | { | |
2897 | const void *_vbt = vbt; | |
2898 | ||
2899 | return _vbt + vbt->bdb_offset; | |
2900 | } | |
2901 | ||
f0067a31 JN |
2902 | /** |
2903 | * intel_bios_is_valid_vbt - does the given buffer contain a valid VBT | |
ff9bc20c | 2904 | * @i915: the device |
f0067a31 JN |
2905 | * @buf: pointer to a buffer to validate |
2906 | * @size: size of the buffer | |
2907 | * | |
2908 | * Returns true on valid VBT. | |
2909 | */ | |
ff9bc20c VS |
2910 | bool intel_bios_is_valid_vbt(struct drm_i915_private *i915, |
2911 | const void *buf, size_t size) | |
3dd4e846 | 2912 | { |
f0067a31 | 2913 | const struct vbt_header *vbt = buf; |
dcb58a40 | 2914 | const struct bdb_header *bdb; |
3dd4e846 | 2915 | |
caf37fa4 | 2916 | if (!vbt) |
f0067a31 | 2917 | return false; |
caf37fa4 | 2918 | |
f0067a31 | 2919 | if (sizeof(struct vbt_header) > size) { |
ff9bc20c | 2920 | drm_dbg_kms(&i915->drm, "VBT header incomplete\n"); |
f0067a31 | 2921 | return false; |
3dd4e846 CW |
2922 | } |
2923 | ||
2924 | if (memcmp(vbt->signature, "$VBT", 4)) { | |
ff9bc20c | 2925 | drm_dbg_kms(&i915->drm, "VBT invalid signature\n"); |
f0067a31 | 2926 | return false; |
3dd4e846 CW |
2927 | } |
2928 | ||
ff00ff96 | 2929 | if (vbt->vbt_size > size) { |
ff9bc20c | 2930 | drm_dbg_kms(&i915->drm, "VBT incomplete (vbt_size overflows)\n"); |
ff00ff96 LDM |
2931 | return false; |
2932 | } | |
2933 | ||
2934 | size = vbt->vbt_size; | |
2935 | ||
e8f9ae9b CW |
2936 | if (range_overflows_t(size_t, |
2937 | vbt->bdb_offset, | |
2938 | sizeof(struct bdb_header), | |
2939 | size)) { | |
ff9bc20c | 2940 | drm_dbg_kms(&i915->drm, "BDB header incomplete\n"); |
f0067a31 | 2941 | return false; |
3dd4e846 CW |
2942 | } |
2943 | ||
caf37fa4 | 2944 | bdb = get_bdb_header(vbt); |
e8f9ae9b | 2945 | if (range_overflows_t(size_t, vbt->bdb_offset, bdb->bdb_size, size)) { |
ff9bc20c | 2946 | drm_dbg_kms(&i915->drm, "BDB incomplete\n"); |
f0067a31 | 2947 | return false; |
3dd4e846 CW |
2948 | } |
2949 | ||
caf37fa4 | 2950 | return vbt; |
3dd4e846 CW |
2951 | } |
2952 | ||
3631c363 JN |
2953 | static u32 intel_spi_read(struct intel_uncore *uncore, u32 offset) |
2954 | { | |
2955 | intel_uncore_write(uncore, PRIMARY_SPI_ADDRESS, offset); | |
2956 | ||
2957 | return intel_uncore_read(uncore, PRIMARY_SPI_TRIGGER); | |
2958 | } | |
2959 | ||
a36e7dc0 CT |
2960 | static struct vbt_header *spi_oprom_get_vbt(struct drm_i915_private *i915) |
2961 | { | |
2962 | u32 count, data, found, store = 0; | |
2963 | u32 static_region, oprom_offset; | |
2964 | u32 oprom_size = 0x200000; | |
2965 | u16 vbt_size; | |
2966 | u32 *vbt; | |
2967 | ||
2968 | static_region = intel_uncore_read(&i915->uncore, SPI_STATIC_REGIONS); | |
2969 | static_region &= OPTIONROM_SPI_REGIONID_MASK; | |
2970 | intel_uncore_write(&i915->uncore, PRIMARY_SPI_REGIONID, static_region); | |
2971 | ||
2972 | oprom_offset = intel_uncore_read(&i915->uncore, OROM_OFFSET); | |
2973 | oprom_offset &= OROM_OFFSET_MASK; | |
2974 | ||
2975 | for (count = 0; count < oprom_size; count += 4) { | |
3631c363 | 2976 | data = intel_spi_read(&i915->uncore, oprom_offset + count); |
a36e7dc0 CT |
2977 | if (data == *((const u32 *)"$VBT")) { |
2978 | found = oprom_offset + count; | |
2979 | break; | |
2980 | } | |
2981 | } | |
2982 | ||
2983 | if (count >= oprom_size) | |
2984 | goto err_not_found; | |
2985 | ||
2986 | /* Get VBT size and allocate space for the VBT */ | |
3631c363 JN |
2987 | vbt_size = intel_spi_read(&i915->uncore, |
2988 | found + offsetof(struct vbt_header, vbt_size)); | |
a36e7dc0 CT |
2989 | vbt_size &= 0xffff; |
2990 | ||
980f42e7 | 2991 | vbt = kzalloc(round_up(vbt_size, 4), GFP_KERNEL); |
a36e7dc0 CT |
2992 | if (!vbt) |
2993 | goto err_not_found; | |
2994 | ||
3631c363 JN |
2995 | for (count = 0; count < vbt_size; count += 4) |
2996 | *(vbt + store++) = intel_spi_read(&i915->uncore, found + count); | |
a36e7dc0 | 2997 | |
ff9bc20c | 2998 | if (!intel_bios_is_valid_vbt(i915, vbt, vbt_size)) |
a36e7dc0 CT |
2999 | goto err_free_vbt; |
3000 | ||
3001 | drm_dbg_kms(&i915->drm, "Found valid VBT in SPI flash\n"); | |
3002 | ||
3003 | return (struct vbt_header *)vbt; | |
3004 | ||
3005 | err_free_vbt: | |
3006 | kfree(vbt); | |
3007 | err_not_found: | |
3008 | return NULL; | |
3009 | } | |
3010 | ||
dbd440d8 | 3011 | static struct vbt_header *oprom_get_vbt(struct drm_i915_private *i915) |
b34a991a | 3012 | { |
dbd440d8 | 3013 | struct pci_dev *pdev = to_pci_dev(i915->drm.dev); |
2cded152 | 3014 | void __iomem *p = NULL, *oprom; |
fd0186ce LDM |
3015 | struct vbt_header *vbt; |
3016 | u16 vbt_size; | |
2cded152 LDM |
3017 | size_t i, size; |
3018 | ||
3019 | oprom = pci_map_rom(pdev, &size); | |
3020 | if (!oprom) | |
3021 | return NULL; | |
b34a991a JN |
3022 | |
3023 | /* Scour memory looking for the VBT signature. */ | |
98cf5c9a | 3024 | for (i = 0; i + 4 < size; i += 4) { |
496f50a6 | 3025 | if (ioread32(oprom + i) != *((const u32 *)"$VBT")) |
f0067a31 JN |
3026 | continue; |
3027 | ||
fd0186ce LDM |
3028 | p = oprom + i; |
3029 | size -= i; | |
f0067a31 | 3030 | break; |
b34a991a JN |
3031 | } |
3032 | ||
fd0186ce | 3033 | if (!p) |
2cded152 | 3034 | goto err_unmap_oprom; |
fd0186ce LDM |
3035 | |
3036 | if (sizeof(struct vbt_header) > size) { | |
dbd440d8 | 3037 | drm_dbg(&i915->drm, "VBT header incomplete\n"); |
2cded152 | 3038 | goto err_unmap_oprom; |
fd0186ce LDM |
3039 | } |
3040 | ||
3041 | vbt_size = ioread16(p + offsetof(struct vbt_header, vbt_size)); | |
3042 | if (vbt_size > size) { | |
dbd440d8 | 3043 | drm_dbg(&i915->drm, |
e92cbf38 | 3044 | "VBT incomplete (vbt_size overflows)\n"); |
2cded152 | 3045 | goto err_unmap_oprom; |
fd0186ce LDM |
3046 | } |
3047 | ||
3048 | /* The rest will be validated by intel_bios_is_valid_vbt() */ | |
3049 | vbt = kmalloc(vbt_size, GFP_KERNEL); | |
3050 | if (!vbt) | |
2cded152 | 3051 | goto err_unmap_oprom; |
fd0186ce LDM |
3052 | |
3053 | memcpy_fromio(vbt, p, vbt_size); | |
3054 | ||
ff9bc20c | 3055 | if (!intel_bios_is_valid_vbt(i915, vbt, vbt_size)) |
fd0186ce LDM |
3056 | goto err_free_vbt; |
3057 | ||
2cded152 LDM |
3058 | pci_unmap_rom(pdev, oprom); |
3059 | ||
a36e7dc0 CT |
3060 | drm_dbg_kms(&i915->drm, "Found valid VBT in PCI ROM\n"); |
3061 | ||
fd0186ce LDM |
3062 | return vbt; |
3063 | ||
3064 | err_free_vbt: | |
3065 | kfree(vbt); | |
2cded152 LDM |
3066 | err_unmap_oprom: |
3067 | pci_unmap_rom(pdev, oprom); | |
fd0186ce | 3068 | |
f0067a31 | 3069 | return NULL; |
b34a991a JN |
3070 | } |
3071 | ||
79e53945 | 3072 | /** |
8b8e1a89 | 3073 | * intel_bios_init - find VBT and initialize settings from the BIOS |
dbd440d8 | 3074 | * @i915: i915 device instance |
79e53945 | 3075 | * |
66578857 JN |
3076 | * Parse and initialize settings from the Video BIOS Tables (VBT). If the VBT |
3077 | * was not found in ACPI OpRegion, try to find it in PCI ROM first. Also | |
3078 | * initialize some defaults if the VBT is not present at all. | |
79e53945 | 3079 | */ |
dbd440d8 | 3080 | void intel_bios_init(struct drm_i915_private *i915) |
79e53945 | 3081 | { |
37e21003 | 3082 | const struct vbt_header *vbt; |
2cded152 | 3083 | struct vbt_header *oprom_vbt = NULL; |
caf37fa4 | 3084 | const struct bdb_header *bdb; |
44834a67 | 3085 | |
a434689c JN |
3086 | INIT_LIST_HEAD(&i915->display.vbt.display_devices); |
3087 | INIT_LIST_HEAD(&i915->display.vbt.bdb_blocks); | |
0d9ef19b | 3088 | |
dbd440d8 JN |
3089 | if (!HAS_DISPLAY(i915)) { |
3090 | drm_dbg_kms(&i915->drm, | |
e92cbf38 | 3091 | "Skipping VBT init due to disabled display.\n"); |
66578857 JN |
3092 | return; |
3093 | } | |
ab5c608b | 3094 | |
dbd440d8 | 3095 | init_vbt_defaults(i915); |
f899fc64 | 3096 | |
37e21003 JN |
3097 | vbt = intel_opregion_get_vbt(i915, NULL); |
3098 | ||
a36e7dc0 CT |
3099 | /* |
3100 | * If the OpRegion does not have VBT, look in SPI flash through MMIO or | |
3101 | * PCI mapping | |
3102 | */ | |
3103 | if (!vbt && IS_DGFX(i915)) { | |
3104 | oprom_vbt = spi_oprom_get_vbt(i915); | |
3105 | vbt = oprom_vbt; | |
3106 | } | |
3107 | ||
f0067a31 | 3108 | if (!vbt) { |
dbd440d8 | 3109 | oprom_vbt = oprom_get_vbt(i915); |
2cded152 | 3110 | vbt = oprom_vbt; |
44834a67 | 3111 | } |
79e53945 | 3112 | |
a36e7dc0 CT |
3113 | if (!vbt) |
3114 | goto out; | |
3115 | ||
caf37fa4 | 3116 | bdb = get_bdb_header(vbt); |
a434689c | 3117 | i915->display.vbt.version = bdb->version; |
caf37fa4 | 3118 | |
dbd440d8 | 3119 | drm_dbg_kms(&i915->drm, |
e92cbf38 | 3120 | "VBT signature \"%.*s\", BDB version %d\n", |
a434689c | 3121 | (int)sizeof(vbt->signature), vbt->signature, i915->display.vbt.version); |
e2051c44 | 3122 | |
e163cfb4 VS |
3123 | init_bdb_blocks(i915, bdb); |
3124 | ||
79e53945 | 3125 | /* Grab useful general definitions */ |
e163cfb4 VS |
3126 | parse_general_features(i915); |
3127 | parse_general_definitions(i915); | |
e163cfb4 | 3128 | parse_driver_features(i915); |
0ebdabe6 | 3129 | |
6e0d46e9 | 3130 | /* Depends on child device list */ |
e163cfb4 | 3131 | parse_compression_parameters(i915); |
6e0d46e9 | 3132 | |
66578857 | 3133 | out: |
bb1d1329 | 3134 | if (!vbt) { |
dbd440d8 | 3135 | drm_info(&i915->drm, |
e92cbf38 | 3136 | "Failed to find VBIOS tables (VBT)\n"); |
dbd440d8 | 3137 | init_vbt_missing_defaults(i915); |
bb1d1329 | 3138 | } |
66578857 | 3139 | |
51f57481 JN |
3140 | /* Further processing on pre-parsed or generated child device data */ |
3141 | parse_sdvo_device_mapping(i915); | |
3142 | parse_ddi_ports(i915); | |
3143 | ||
2cded152 | 3144 | kfree(oprom_vbt); |
79e53945 | 3145 | } |
3bdd14d5 | 3146 | |
3f9ffce5 VS |
3147 | static void intel_bios_init_panel(struct drm_i915_private *i915, |
3148 | struct intel_panel *panel, | |
3149 | const struct intel_bios_encoder_data *devdata, | |
c36225a1 | 3150 | const struct drm_edid *drm_edid, |
3f9ffce5 | 3151 | bool use_fallback) |
c2fdb424 | 3152 | { |
3f9ffce5 VS |
3153 | /* already have it? */ |
3154 | if (panel->vbt.panel_type >= 0) { | |
3155 | drm_WARN_ON(&i915->drm, !use_fallback); | |
3156 | return; | |
3157 | } | |
3cf05076 | 3158 | |
3f9ffce5 | 3159 | panel->vbt.panel_type = get_panel_type(i915, devdata, |
c36225a1 | 3160 | drm_edid, use_fallback); |
3f9ffce5 VS |
3161 | if (panel->vbt.panel_type < 0) { |
3162 | drm_WARN_ON(&i915->drm, use_fallback); | |
3163 | return; | |
3164 | } | |
3165 | ||
3166 | init_vbt_panel_defaults(panel); | |
0256ea13 VS |
3167 | |
3168 | parse_panel_options(i915, panel); | |
3cf05076 VS |
3169 | parse_generic_dtd(i915, panel); |
3170 | parse_lfp_data(i915, panel); | |
3171 | parse_lfp_backlight(i915, panel); | |
3172 | parse_sdvo_panel_data(i915, panel); | |
3173 | parse_panel_driver_features(i915, panel); | |
3174 | parse_power_conservation_features(i915, panel); | |
3175 | parse_edp(i915, panel); | |
3176 | parse_psr(i915, panel); | |
3177 | parse_mipi_config(i915, panel); | |
3178 | parse_mipi_sequence(i915, panel); | |
c2fdb424 VS |
3179 | } |
3180 | ||
3f9ffce5 VS |
3181 | void intel_bios_init_panel_early(struct drm_i915_private *i915, |
3182 | struct intel_panel *panel, | |
3183 | const struct intel_bios_encoder_data *devdata) | |
3184 | { | |
3185 | intel_bios_init_panel(i915, panel, devdata, NULL, false); | |
3186 | } | |
3187 | ||
3188 | void intel_bios_init_panel_late(struct drm_i915_private *i915, | |
3189 | struct intel_panel *panel, | |
3190 | const struct intel_bios_encoder_data *devdata, | |
c36225a1 | 3191 | const struct drm_edid *drm_edid) |
3f9ffce5 | 3192 | { |
c36225a1 | 3193 | intel_bios_init_panel(i915, panel, devdata, drm_edid, true); |
3f9ffce5 VS |
3194 | } |
3195 | ||
785f076b | 3196 | /** |
78dae1ac | 3197 | * intel_bios_driver_remove - Free any resources allocated by intel_bios_init() |
dbd440d8 | 3198 | * @i915: i915 device instance |
785f076b | 3199 | */ |
dbd440d8 | 3200 | void intel_bios_driver_remove(struct drm_i915_private *i915) |
785f076b | 3201 | { |
e163cfb4 VS |
3202 | struct intel_bios_encoder_data *devdata, *nd; |
3203 | struct bdb_block_entry *entry, *ne; | |
0d9ef19b | 3204 | |
a434689c | 3205 | list_for_each_entry_safe(devdata, nd, &i915->display.vbt.display_devices, node) { |
0d9ef19b | 3206 | list_del(&devdata->node); |
6e0d46e9 | 3207 | kfree(devdata->dsc); |
0d9ef19b JN |
3208 | kfree(devdata); |
3209 | } | |
3210 | ||
a434689c | 3211 | list_for_each_entry_safe(entry, ne, &i915->display.vbt.bdb_blocks, node) { |
e163cfb4 VS |
3212 | list_del(&entry->node); |
3213 | kfree(entry); | |
3214 | } | |
3cf05076 | 3215 | } |
e163cfb4 | 3216 | |
3cf05076 VS |
3217 | void intel_bios_fini_panel(struct intel_panel *panel) |
3218 | { | |
3219 | kfree(panel->vbt.sdvo_lvds_vbt_mode); | |
3220 | panel->vbt.sdvo_lvds_vbt_mode = NULL; | |
3221 | kfree(panel->vbt.lfp_lvds_vbt_mode); | |
3222 | panel->vbt.lfp_lvds_vbt_mode = NULL; | |
3223 | kfree(panel->vbt.dsi.data); | |
3224 | panel->vbt.dsi.data = NULL; | |
3225 | kfree(panel->vbt.dsi.pps); | |
3226 | panel->vbt.dsi.pps = NULL; | |
3227 | kfree(panel->vbt.dsi.config); | |
3228 | panel->vbt.dsi.config = NULL; | |
3229 | kfree(panel->vbt.dsi.deassert_seq); | |
3230 | panel->vbt.dsi.deassert_seq = NULL; | |
785f076b HG |
3231 | } |
3232 | ||
3bdd14d5 JN |
3233 | /** |
3234 | * intel_bios_is_tv_present - is integrated TV present in VBT | |
dbd440d8 | 3235 | * @i915: i915 device instance |
3bdd14d5 JN |
3236 | * |
3237 | * Return true if TV is present. If no child devices were parsed from VBT, | |
3238 | * assume TV is present. | |
3239 | */ | |
dbd440d8 | 3240 | bool intel_bios_is_tv_present(struct drm_i915_private *i915) |
3bdd14d5 | 3241 | { |
3162d057 | 3242 | const struct intel_bios_encoder_data *devdata; |
3bdd14d5 | 3243 | |
a434689c | 3244 | if (!i915->display.vbt.int_tv_support) |
3bdd14d5 JN |
3245 | return false; |
3246 | ||
a434689c | 3247 | if (list_empty(&i915->display.vbt.display_devices)) |
3bdd14d5 JN |
3248 | return true; |
3249 | ||
a434689c | 3250 | list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { |
d24b3475 | 3251 | const struct child_device_config *child = &devdata->child; |
0d9ef19b | 3252 | |
3bdd14d5 JN |
3253 | /* |
3254 | * If the device type is not TV, continue. | |
3255 | */ | |
cc998589 | 3256 | switch (child->device_type) { |
3bdd14d5 JN |
3257 | case DEVICE_TYPE_INT_TV: |
3258 | case DEVICE_TYPE_TV: | |
3259 | case DEVICE_TYPE_TV_SVIDEO_COMPOSITE: | |
3260 | break; | |
3261 | default: | |
3262 | continue; | |
3263 | } | |
3264 | /* Only when the addin_offset is non-zero, it is regarded | |
3265 | * as present. | |
3266 | */ | |
cc998589 | 3267 | if (child->addin_offset) |
3bdd14d5 JN |
3268 | return true; |
3269 | } | |
3270 | ||
3271 | return false; | |
3272 | } | |
5a69d13d JN |
3273 | |
3274 | /** | |
3275 | * intel_bios_is_lvds_present - is LVDS present in VBT | |
dbd440d8 | 3276 | * @i915: i915 device instance |
5a69d13d JN |
3277 | * @i2c_pin: i2c pin for LVDS if present |
3278 | * | |
3279 | * Return true if LVDS is present. If no child devices were parsed from VBT, | |
3280 | * assume LVDS is present. | |
3281 | */ | |
dbd440d8 | 3282 | bool intel_bios_is_lvds_present(struct drm_i915_private *i915, u8 *i2c_pin) |
5a69d13d | 3283 | { |
3162d057 | 3284 | const struct intel_bios_encoder_data *devdata; |
5a69d13d | 3285 | |
a434689c | 3286 | if (list_empty(&i915->display.vbt.display_devices)) |
5a69d13d JN |
3287 | return true; |
3288 | ||
a434689c | 3289 | list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { |
d24b3475 | 3290 | const struct child_device_config *child = &devdata->child; |
5a69d13d JN |
3291 | |
3292 | /* If the device type is not LFP, continue. | |
3293 | * We have to check both the new identifiers as well as the | |
3294 | * old for compatibility with some BIOSes. | |
3295 | */ | |
3296 | if (child->device_type != DEVICE_TYPE_INT_LFP && | |
3297 | child->device_type != DEVICE_TYPE_LFP) | |
3298 | continue; | |
3299 | ||
dbd440d8 | 3300 | if (intel_gmbus_is_valid_pin(i915, child->i2c_pin)) |
5a69d13d JN |
3301 | *i2c_pin = child->i2c_pin; |
3302 | ||
3303 | /* However, we cannot trust the BIOS writers to populate | |
3304 | * the VBT correctly. Since LVDS requires additional | |
3305 | * information from AIM blocks, a non-zero addin offset is | |
3306 | * a good indicator that the LVDS is actually present. | |
3307 | */ | |
3308 | if (child->addin_offset) | |
3309 | return true; | |
3310 | ||
3311 | /* But even then some BIOS writers perform some black magic | |
3312 | * and instantiate the device without reference to any | |
3313 | * additional data. Trust that if the VBT was written into | |
3314 | * the OpRegion then they have validated the LVDS's existence. | |
3315 | */ | |
37e21003 | 3316 | if (intel_opregion_get_vbt(i915, NULL)) |
5a69d13d JN |
3317 | return true; |
3318 | } | |
3319 | ||
3320 | return false; | |
3321 | } | |
951d9efe | 3322 | |
22f35042 VS |
3323 | /** |
3324 | * intel_bios_is_port_present - is the specified digital port present | |
dbd440d8 | 3325 | * @i915: i915 device instance |
22f35042 VS |
3326 | * @port: port to check |
3327 | * | |
3328 | * Return true if the device in %port is present. | |
3329 | */ | |
dbd440d8 | 3330 | bool intel_bios_is_port_present(struct drm_i915_private *i915, enum port port) |
22f35042 | 3331 | { |
b17a15d6 VS |
3332 | const struct intel_bios_encoder_data *devdata; |
3333 | ||
a868a1e5 VS |
3334 | if (WARN_ON(!has_ddi_port_info(i915))) |
3335 | return true; | |
22f35042 | 3336 | |
b17a15d6 VS |
3337 | if (!is_port_valid(i915, port)) |
3338 | return false; | |
3339 | ||
3340 | list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { | |
3341 | const struct child_device_config *child = &devdata->child; | |
3342 | ||
3343 | if (dvo_port_to_port(i915, child->dvo_port) == port) | |
3344 | return true; | |
3345 | } | |
3346 | ||
3347 | return false; | |
22f35042 VS |
3348 | } |
3349 | ||
2bea1d7c | 3350 | bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata) |
d6199256 | 3351 | { |
044cbc7a VS |
3352 | const struct child_device_config *child = &devdata->child; |
3353 | ||
3354 | if (!intel_bios_encoder_supports_dp(devdata) || | |
3355 | !intel_bios_encoder_supports_hdmi(devdata)) | |
d6199256 VS |
3356 | return false; |
3357 | ||
32c2bc89 | 3358 | if (dvo_port_type(child->dvo_port) == DVO_PORT_DPA) |
7a17995a VS |
3359 | return true; |
3360 | ||
3361 | /* Only accept a HDMI dvo_port as DP++ if it has an AUX channel */ | |
32c2bc89 | 3362 | if (dvo_port_type(child->dvo_port) == DVO_PORT_HDMIA && |
cc998589 | 3363 | child->aux_channel != 0) |
7a17995a VS |
3364 | return true; |
3365 | ||
3366 | return false; | |
3367 | } | |
3368 | ||
7137aec1 JN |
3369 | /** |
3370 | * intel_bios_is_dsi_present - is DSI present in VBT | |
dbd440d8 | 3371 | * @i915: i915 device instance |
7137aec1 JN |
3372 | * @port: port for DSI if present |
3373 | * | |
3374 | * Return true if DSI is present, and return the port in %port. | |
3375 | */ | |
dbd440d8 | 3376 | bool intel_bios_is_dsi_present(struct drm_i915_private *i915, |
7137aec1 JN |
3377 | enum port *port) |
3378 | { | |
3162d057 | 3379 | const struct intel_bios_encoder_data *devdata; |
7137aec1 | 3380 | |
a434689c | 3381 | list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { |
d24b3475 VS |
3382 | const struct child_device_config *child = &devdata->child; |
3383 | u8 dvo_port = child->dvo_port; | |
7137aec1 | 3384 | |
cc998589 | 3385 | if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) |
7137aec1 JN |
3386 | continue; |
3387 | ||
118b5c13 | 3388 | if (dsi_dvo_port_to_port(i915, dvo_port) == PORT_NONE) { |
dbd440d8 | 3389 | drm_dbg_kms(&i915->drm, |
e92cbf38 WK |
3390 | "VBT has unsupported DSI port %c\n", |
3391 | port_name(dvo_port - DVO_PORT_MIPIA)); | |
118b5c13 | 3392 | continue; |
7137aec1 | 3393 | } |
118b5c13 VS |
3394 | |
3395 | if (port) | |
3396 | *port = dsi_dvo_port_to_port(i915, dvo_port); | |
3397 | return true; | |
7137aec1 JN |
3398 | } |
3399 | ||
3400 | return false; | |
3401 | } | |
d252bf68 | 3402 | |
1bf2f3bf JN |
3403 | static void fill_dsc(struct intel_crtc_state *crtc_state, |
3404 | struct dsc_compression_parameters_entry *dsc, | |
3405 | int dsc_max_bpc) | |
3406 | { | |
ff9bc20c | 3407 | struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); |
1bf2f3bf JN |
3408 | struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; |
3409 | int bpc = 8; | |
3410 | ||
3411 | vdsc_cfg->dsc_version_major = dsc->version_major; | |
3412 | vdsc_cfg->dsc_version_minor = dsc->version_minor; | |
3413 | ||
3414 | if (dsc->support_12bpc && dsc_max_bpc >= 12) | |
3415 | bpc = 12; | |
3416 | else if (dsc->support_10bpc && dsc_max_bpc >= 10) | |
3417 | bpc = 10; | |
3418 | else if (dsc->support_8bpc && dsc_max_bpc >= 8) | |
3419 | bpc = 8; | |
3420 | else | |
ff9bc20c VS |
3421 | drm_dbg_kms(&i915->drm, "VBT: Unsupported BPC %d for DCS\n", |
3422 | dsc_max_bpc); | |
1bf2f3bf JN |
3423 | |
3424 | crtc_state->pipe_bpp = bpc * 3; | |
3425 | ||
59a266f0 AN |
3426 | crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(min(crtc_state->pipe_bpp, |
3427 | VBT_DSC_MAX_BPP(dsc->max_bpp))); | |
1bf2f3bf JN |
3428 | |
3429 | /* | |
3430 | * FIXME: This is ugly, and slice count should take DSC engine | |
3431 | * throughput etc. into account. | |
3432 | * | |
3433 | * Also, per spec DSI supports 1, 2, 3 or 4 horizontal slices. | |
3434 | */ | |
3435 | if (dsc->slices_per_line & BIT(2)) { | |
3436 | crtc_state->dsc.slice_count = 4; | |
3437 | } else if (dsc->slices_per_line & BIT(1)) { | |
3438 | crtc_state->dsc.slice_count = 2; | |
3439 | } else { | |
3440 | /* FIXME */ | |
3441 | if (!(dsc->slices_per_line & BIT(0))) | |
ff9bc20c | 3442 | drm_dbg_kms(&i915->drm, "VBT: Unsupported DSC slice count for DSI\n"); |
1bf2f3bf JN |
3443 | |
3444 | crtc_state->dsc.slice_count = 1; | |
3445 | } | |
3446 | ||
3447 | if (crtc_state->hw.adjusted_mode.crtc_hdisplay % | |
3448 | crtc_state->dsc.slice_count != 0) | |
ff9bc20c VS |
3449 | drm_dbg_kms(&i915->drm, "VBT: DSC hdisplay %d not divisible by slice count %d\n", |
3450 | crtc_state->hw.adjusted_mode.crtc_hdisplay, | |
3451 | crtc_state->dsc.slice_count); | |
1bf2f3bf JN |
3452 | |
3453 | /* | |
1bf2f3bf | 3454 | * The VBT rc_buffer_block_size and rc_buffer_size definitions |
fd8a5b27 | 3455 | * correspond to DP 1.4 DPCD offsets 0x62 and 0x63. |
1bf2f3bf | 3456 | */ |
fd8a5b27 JN |
3457 | vdsc_cfg->rc_model_size = drm_dsc_dp_rc_buffer_size(dsc->rc_buffer_block_size, |
3458 | dsc->rc_buffer_size); | |
1bf2f3bf JN |
3459 | |
3460 | /* FIXME: DSI spec says bpc + 1 for this one */ | |
3461 | vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth); | |
3462 | ||
3463 | vdsc_cfg->block_pred_enable = dsc->block_prediction_enable; | |
3464 | ||
3465 | vdsc_cfg->slice_height = dsc->slice_height; | |
3466 | } | |
3467 | ||
3468 | /* FIXME: initially DSI specific */ | |
3469 | bool intel_bios_get_dsc_params(struct intel_encoder *encoder, | |
3470 | struct intel_crtc_state *crtc_state, | |
3471 | int dsc_max_bpc) | |
3472 | { | |
3473 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); | |
3162d057 | 3474 | const struct intel_bios_encoder_data *devdata; |
1bf2f3bf | 3475 | |
a434689c | 3476 | list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { |
d24b3475 | 3477 | const struct child_device_config *child = &devdata->child; |
1bf2f3bf JN |
3478 | |
3479 | if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT)) | |
3480 | continue; | |
3481 | ||
118b5c13 | 3482 | if (dsi_dvo_port_to_port(i915, child->dvo_port) == encoder->port) { |
1bf2f3bf JN |
3483 | if (!devdata->dsc) |
3484 | return false; | |
3485 | ||
f175de44 | 3486 | fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc); |
1bf2f3bf JN |
3487 | |
3488 | return true; | |
3489 | } | |
3490 | } | |
3491 | ||
3492 | return false; | |
3493 | } | |
3494 | ||
5a0fc7a0 VS |
3495 | static const u8 adlp_aux_ch_map[] = { |
3496 | [AUX_CH_A] = DP_AUX_A, | |
3497 | [AUX_CH_B] = DP_AUX_B, | |
3498 | [AUX_CH_C] = DP_AUX_C, | |
3499 | [AUX_CH_D_XELPD] = DP_AUX_D, | |
3500 | [AUX_CH_E_XELPD] = DP_AUX_E, | |
3501 | [AUX_CH_USBC1] = DP_AUX_F, | |
3502 | [AUX_CH_USBC2] = DP_AUX_G, | |
3503 | [AUX_CH_USBC3] = DP_AUX_H, | |
3504 | [AUX_CH_USBC4] = DP_AUX_I, | |
3505 | }; | |
3506 | ||
3507 | /* | |
3508 | * ADL-S VBT uses PHY based mapping. Combo PHYs A,B,C,D,E | |
3509 | * map to DDI A,TC1,TC2,TC3,TC4 respectively. | |
3510 | */ | |
3511 | static const u8 adls_aux_ch_map[] = { | |
3512 | [AUX_CH_A] = DP_AUX_A, | |
3513 | [AUX_CH_USBC1] = DP_AUX_B, | |
3514 | [AUX_CH_USBC2] = DP_AUX_C, | |
3515 | [AUX_CH_USBC3] = DP_AUX_D, | |
3516 | [AUX_CH_USBC4] = DP_AUX_E, | |
3517 | }; | |
3518 | ||
3519 | /* | |
3520 | * RKL/DG1 VBT uses PHY based mapping. Combo PHYs A,B,C,D | |
3521 | * map to DDI A,B,TC1,TC2 respectively. | |
3522 | */ | |
3523 | static const u8 rkl_aux_ch_map[] = { | |
3524 | [AUX_CH_A] = DP_AUX_A, | |
3525 | [AUX_CH_B] = DP_AUX_B, | |
3526 | [AUX_CH_USBC1] = DP_AUX_C, | |
3527 | [AUX_CH_USBC2] = DP_AUX_D, | |
3528 | }; | |
3529 | ||
3530 | static const u8 direct_aux_ch_map[] = { | |
3531 | [AUX_CH_A] = DP_AUX_A, | |
3532 | [AUX_CH_B] = DP_AUX_B, | |
3533 | [AUX_CH_C] = DP_AUX_C, | |
3534 | [AUX_CH_D] = DP_AUX_D, /* aka AUX_CH_USBC1 */ | |
3535 | [AUX_CH_E] = DP_AUX_E, /* aka AUX_CH_USBC2 */ | |
3536 | [AUX_CH_F] = DP_AUX_F, /* aka AUX_CH_USBC3 */ | |
3537 | [AUX_CH_G] = DP_AUX_G, /* aka AUX_CH_USBC4 */ | |
3538 | [AUX_CH_H] = DP_AUX_H, /* aka AUX_CH_USBC5 */ | |
3539 | [AUX_CH_I] = DP_AUX_I, /* aka AUX_CH_USBC6 */ | |
3540 | }; | |
3541 | ||
bb45217f | 3542 | static enum aux_ch map_aux_ch(struct drm_i915_private *i915, u8 aux_channel) |
15d248ae | 3543 | { |
5a0fc7a0 VS |
3544 | const u8 *aux_ch_map; |
3545 | int i, n_entries; | |
15d248ae | 3546 | |
5a0fc7a0 VS |
3547 | if (DISPLAY_VER(i915) >= 13) { |
3548 | aux_ch_map = adlp_aux_ch_map; | |
3549 | n_entries = ARRAY_SIZE(adlp_aux_ch_map); | |
3550 | } else if (IS_ALDERLAKE_S(i915)) { | |
3551 | aux_ch_map = adls_aux_ch_map; | |
3552 | n_entries = ARRAY_SIZE(adls_aux_ch_map); | |
3553 | } else if (IS_DG1(i915) || IS_ROCKETLAKE(i915)) { | |
3554 | aux_ch_map = rkl_aux_ch_map; | |
3555 | n_entries = ARRAY_SIZE(rkl_aux_ch_map); | |
3556 | } else { | |
3557 | aux_ch_map = direct_aux_ch_map; | |
3558 | n_entries = ARRAY_SIZE(direct_aux_ch_map); | |
15d248ae ID |
3559 | } |
3560 | ||
5a0fc7a0 VS |
3561 | for (i = 0; i < n_entries; i++) { |
3562 | if (aux_ch_map[i] == aux_channel) | |
3563 | return i; | |
3564 | } | |
3565 | ||
3566 | drm_dbg_kms(&i915->drm, | |
3567 | "Ignoring alternate AUX CH: VBT claims AUX 0x%x, which is not valid for this platform\n", | |
3568 | aux_channel); | |
3569 | ||
3570 | return AUX_CH_NONE; | |
15d248ae | 3571 | } |
d9ee2111 | 3572 | |
bb45217f VS |
3573 | enum aux_ch intel_bios_dp_aux_ch(const struct intel_bios_encoder_data *devdata) |
3574 | { | |
3575 | if (!devdata || !devdata->child.aux_channel) | |
3576 | return AUX_CH_NONE; | |
3577 | ||
3578 | return map_aux_ch(devdata->i915, devdata->child.aux_channel); | |
3579 | } | |
0aed3bde | 3580 | |
70052100 VS |
3581 | bool intel_bios_dp_has_shared_aux_ch(const struct intel_bios_encoder_data *devdata) |
3582 | { | |
3583 | struct drm_i915_private *i915; | |
3584 | u8 aux_channel; | |
3585 | int count = 0; | |
3586 | ||
3587 | if (!devdata || !devdata->child.aux_channel) | |
3588 | return false; | |
3589 | ||
3590 | i915 = devdata->i915; | |
3591 | aux_channel = devdata->child.aux_channel; | |
3592 | ||
3593 | list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { | |
3594 | if (intel_bios_encoder_supports_dp(devdata) && | |
3595 | aux_channel == devdata->child.aux_channel) | |
3596 | count++; | |
3597 | } | |
3598 | ||
3599 | return count > 1; | |
3600 | } | |
3601 | ||
02107ef1 | 3602 | int intel_bios_dp_boost_level(const struct intel_bios_encoder_data *devdata) |
605a1872 | 3603 | { |
a434689c | 3604 | if (!devdata || devdata->i915->display.vbt.version < 196 || !devdata->child.iboost) |
c0a950d1 | 3605 | return 0; |
605a1872 | 3606 | |
ff9bc20c | 3607 | return translate_iboost(devdata->i915, devdata->child.dp_iboost_level); |
605a1872 | 3608 | } |
01a60883 | 3609 | |
02107ef1 | 3610 | int intel_bios_hdmi_boost_level(const struct intel_bios_encoder_data *devdata) |
01a60883 | 3611 | { |
a434689c | 3612 | if (!devdata || devdata->i915->display.vbt.version < 196 || !devdata->child.iboost) |
c0a950d1 | 3613 | return 0; |
01a60883 | 3614 | |
ff9bc20c | 3615 | return translate_iboost(devdata->i915, devdata->child.hdmi_iboost_level); |
01a60883 | 3616 | } |
f83acdab | 3617 | |
02107ef1 | 3618 | int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata) |
f83acdab | 3619 | { |
dab8477b JN |
3620 | if (!devdata || !devdata->child.ddc_pin) |
3621 | return 0; | |
17004bfb | 3622 | |
02107ef1 | 3623 | return map_ddc_pin(devdata->i915, devdata->child.ddc_pin); |
17004bfb | 3624 | } |
c5faae5a | 3625 | |
f08fbe6a | 3626 | bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata) |
c5faae5a | 3627 | { |
a434689c | 3628 | return devdata->i915->display.vbt.version >= 195 && devdata->child.dp_usb_type_c; |
c5faae5a JN |
3629 | } |
3630 | ||
f08fbe6a | 3631 | bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata) |
c5faae5a | 3632 | { |
a434689c | 3633 | return devdata->i915->display.vbt.version >= 209 && devdata->child.tbt; |
c5faae5a | 3634 | } |
45c0673a | 3635 | |
5f42196d VS |
3636 | bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata) |
3637 | { | |
3638 | return devdata && devdata->child.lane_reversal; | |
3639 | } | |
3640 | ||
9151c85c VS |
3641 | bool intel_bios_encoder_hpd_invert(const struct intel_bios_encoder_data *devdata) |
3642 | { | |
3643 | return devdata && devdata->child.hpd_invert; | |
3644 | } | |
3645 | ||
45c0673a JN |
3646 | const struct intel_bios_encoder_data * |
3647 | intel_bios_encoder_data_lookup(struct drm_i915_private *i915, enum port port) | |
3648 | { | |
021a62a5 VS |
3649 | struct intel_bios_encoder_data *devdata; |
3650 | ||
3651 | list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) { | |
3652 | if (intel_bios_encoder_port(devdata) == port) | |
3653 | return devdata; | |
3654 | } | |
3655 | ||
3656 | return NULL; | |
3657 | } | |
3658 | ||
3659 | void intel_bios_for_each_encoder(struct drm_i915_private *i915, | |
3660 | void (*func)(struct drm_i915_private *i915, | |
3661 | const struct intel_bios_encoder_data *devdata)) | |
3662 | { | |
3663 | struct intel_bios_encoder_data *devdata; | |
3664 | ||
3665 | list_for_each_entry(devdata, &i915->display.vbt.display_devices, node) | |
3666 | func(i915, devdata); | |
45c0673a | 3667 | } |
30ef2627 JN |
3668 | |
3669 | static int intel_bios_vbt_show(struct seq_file *m, void *unused) | |
3670 | { | |
3671 | struct drm_i915_private *i915 = m->private; | |
37e21003 JN |
3672 | const void *vbt; |
3673 | size_t vbt_size; | |
30ef2627 JN |
3674 | |
3675 | /* | |
3676 | * FIXME: VBT might originate from other places than opregion, and then | |
3677 | * this would be incorrect. | |
3678 | */ | |
37e21003 JN |
3679 | vbt = intel_opregion_get_vbt(i915, &vbt_size); |
3680 | if (vbt) | |
3681 | seq_write(m, vbt, vbt_size); | |
30ef2627 JN |
3682 | |
3683 | return 0; | |
3684 | } | |
3685 | ||
3686 | DEFINE_SHOW_ATTRIBUTE(intel_bios_vbt); | |
3687 | ||
3688 | void intel_bios_debugfs_register(struct drm_i915_private *i915) | |
3689 | { | |
3690 | struct drm_minor *minor = i915->drm.primary; | |
3691 | ||
3692 | debugfs_create_file("i915_vbt", 0444, minor->debugfs_root, | |
3693 | i915, &intel_bios_vbt_fops); | |
3694 | } |