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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
d2ee2e8a | 30 | |
c6f95f27 | 31 | #include <drm/drm_atomic_helper.h> |
760285e7 | 32 | #include <drm/drm_crtc.h> |
760285e7 | 33 | #include <drm/drm_edid.h> |
fcd70cd3 | 34 | #include <drm/drm_probe_helper.h> |
d2ee2e8a | 35 | |
79e53945 | 36 | #include "i915_drv.h" |
801543b2 JN |
37 | #include "i915_irq.h" |
38 | #include "i915_reg.h" | |
ec7f29ff | 39 | #include "intel_connector.h" |
d2ee2e8a | 40 | #include "intel_crt.h" |
7c53e628 | 41 | #include "intel_crtc.h" |
fdc24cf3 | 42 | #include "intel_ddi.h" |
c40a253b | 43 | #include "intel_ddi_buf_trans.h" |
7785ae0b | 44 | #include "intel_de.h" |
1d455f8d | 45 | #include "intel_display_types.h" |
dcb38f79 | 46 | #include "intel_fdi.h" |
04500bfd | 47 | #include "intel_fdi_regs.h" |
8834e365 | 48 | #include "intel_fifo_underrun.h" |
3ce2ea65 | 49 | #include "intel_gmbus.h" |
dbeb38d9 | 50 | #include "intel_hotplug.h" |
da38ba98 | 51 | #include "intel_hotplug_irq.h" |
b13604c0 | 52 | #include "intel_load_detect.h" |
b2de2d00 | 53 | #include "intel_pch_display.h" |
665a7b04 | 54 | #include "intel_pch_refclk.h" |
79e53945 | 55 | |
e7dbb2f2 KP |
56 | /* Here's the desired hotplug mode */ |
57 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
58 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
59 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
60 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
61 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
62 | ADPA_CRT_HOTPLUG_ENABLE) | |
63 | ||
c9a1c4cd CW |
64 | struct intel_crt { |
65 | struct intel_encoder base; | |
637f44d2 AJ |
66 | /* DPMS state is stored in the connector, which we need in the |
67 | * encoder's enable/disable callbacks */ | |
68 | struct intel_connector *connector; | |
e7dbb2f2 | 69 | bool force_hotplug_required; |
f0f59a00 | 70 | i915_reg_t adpa_reg; |
c9a1c4cd CW |
71 | }; |
72 | ||
eebe6f0b | 73 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
c9a1c4cd | 74 | { |
eebe6f0b | 75 | return container_of(encoder, struct intel_crt, base); |
c9a1c4cd CW |
76 | } |
77 | ||
43a6d19c | 78 | static struct intel_crt *intel_attached_crt(struct intel_connector *connector) |
79e53945 | 79 | { |
eebe6f0b | 80 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
540a8950 DV |
81 | } |
82 | ||
6102a8ee VS |
83 | bool intel_crt_port_enabled(struct drm_i915_private *dev_priv, |
84 | i915_reg_t adpa_reg, enum pipe *pipe) | |
85 | { | |
86 | u32 val; | |
87 | ||
5b770f18 | 88 | val = intel_de_read(dev_priv, adpa_reg); |
6102a8ee VS |
89 | |
90 | /* asserts want to know the pipe even if the port is disabled */ | |
91 | if (HAS_PCH_CPT(dev_priv)) | |
92 | *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT; | |
93 | else | |
94 | *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT; | |
95 | ||
96 | return val & ADPA_DAC_ENABLE; | |
97 | } | |
98 | ||
e403fc94 DV |
99 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
100 | enum pipe *pipe) | |
79e53945 | 101 | { |
6102a8ee | 102 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e403fc94 | 103 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
0e6e0be4 | 104 | intel_wakeref_t wakeref; |
1c8fdda1 | 105 | bool ret; |
e403fc94 | 106 | |
0e6e0be4 CW |
107 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
108 | encoder->power_domain); | |
109 | if (!wakeref) | |
6d129bea ID |
110 | return false; |
111 | ||
6102a8ee | 112 | ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); |
e403fc94 | 113 | |
0e6e0be4 | 114 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
1c8fdda1 ID |
115 | |
116 | return ret; | |
e403fc94 DV |
117 | } |
118 | ||
6801c18c | 119 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
045ac3b5 | 120 | { |
fac5e23e | 121 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
045ac3b5 JB |
122 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
123 | u32 tmp, flags = 0; | |
124 | ||
5b770f18 | 125 | tmp = intel_de_read(dev_priv, crt->adpa_reg); |
045ac3b5 JB |
126 | |
127 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) | |
128 | flags |= DRM_MODE_FLAG_PHSYNC; | |
129 | else | |
130 | flags |= DRM_MODE_FLAG_NHSYNC; | |
131 | ||
132 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) | |
133 | flags |= DRM_MODE_FLAG_PVSYNC; | |
134 | else | |
135 | flags |= DRM_MODE_FLAG_NVSYNC; | |
136 | ||
6801c18c VS |
137 | return flags; |
138 | } | |
139 | ||
140 | static void intel_crt_get_config(struct intel_encoder *encoder, | |
5cec258b | 141 | struct intel_crtc_state *pipe_config) |
6801c18c | 142 | { |
e1214b95 VS |
143 | pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); |
144 | ||
1326a92c | 145 | pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
18442d08 | 146 | |
1326a92c | 147 | pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; |
045ac3b5 JB |
148 | } |
149 | ||
6801c18c | 150 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
5cec258b | 151 | struct intel_crtc_state *pipe_config) |
6801c18c | 152 | { |
f45d2252 VS |
153 | lpt_pch_get_config(pipe_config); |
154 | ||
351221ff | 155 | hsw_ddi_get_config(encoder, pipe_config); |
6801c18c | 156 | |
1326a92c | 157 | pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
6801c18c VS |
158 | DRM_MODE_FLAG_NHSYNC | |
159 | DRM_MODE_FLAG_PVSYNC | | |
160 | DRM_MODE_FLAG_NVSYNC); | |
1326a92c | 161 | pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
6801c18c VS |
162 | } |
163 | ||
b2cabb0e DV |
164 | /* Note: The caller is required to filter out dpms modes not supported by the |
165 | * platform. */ | |
225cc348 | 166 | static void intel_crt_set_dpms(struct intel_encoder *encoder, |
5f88a9c6 | 167 | const struct intel_crtc_state *crtc_state, |
225cc348 | 168 | int mode) |
df0323c4 | 169 | { |
66478475 | 170 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b2cabb0e | 171 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
2225f3c6 | 172 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
1326a92c | 173 | const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; |
894ed1ec DV |
174 | u32 adpa; |
175 | ||
005e9537 | 176 | if (DISPLAY_VER(dev_priv) >= 5) |
894ed1ec DV |
177 | adpa = ADPA_HOTPLUG_BITS; |
178 | else | |
179 | adpa = 0; | |
df0323c4 | 180 | |
894ed1ec DV |
181 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
182 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
183 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
184 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
185 | ||
186 | /* For CPT allow 3 pipe config, for others just use A or B */ | |
6e266956 | 187 | if (HAS_PCH_LPT(dev_priv)) |
894ed1ec | 188 | ; /* Those bits don't exist here */ |
6e266956 | 189 | else if (HAS_PCH_CPT(dev_priv)) |
6102a8ee | 190 | adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); |
894ed1ec | 191 | else |
6102a8ee | 192 | adpa |= ADPA_PIPE_SEL(crtc->pipe); |
894ed1ec | 193 | |
6e266956 | 194 | if (!HAS_PCH_SPLIT(dev_priv)) |
5b770f18 | 195 | intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); |
79e53945 | 196 | |
0206e353 | 197 | switch (mode) { |
79e53945 | 198 | case DRM_MODE_DPMS_ON: |
894ed1ec | 199 | adpa |= ADPA_DAC_ENABLE; |
79e53945 JB |
200 | break; |
201 | case DRM_MODE_DPMS_STANDBY: | |
894ed1ec | 202 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
79e53945 JB |
203 | break; |
204 | case DRM_MODE_DPMS_SUSPEND: | |
894ed1ec | 205 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
206 | break; |
207 | case DRM_MODE_DPMS_OFF: | |
894ed1ec | 208 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
209 | break; |
210 | } | |
211 | ||
5b770f18 | 212 | intel_de_write(dev_priv, crt->adpa_reg, adpa); |
df0323c4 | 213 | } |
2c07245f | 214 | |
ede9771d VS |
215 | static void intel_disable_crt(struct intel_atomic_state *state, |
216 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
217 | const struct intel_crtc_state *old_crtc_state, |
218 | const struct drm_connector_state *old_conn_state) | |
637f44d2 | 219 | { |
225cc348 | 220 | intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF); |
637f44d2 AJ |
221 | } |
222 | ||
ede9771d VS |
223 | static void pch_disable_crt(struct intel_atomic_state *state, |
224 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
225 | const struct intel_crtc_state *old_crtc_state, |
226 | const struct drm_connector_state *old_conn_state) | |
1ea56e26 VS |
227 | { |
228 | } | |
229 | ||
ede9771d VS |
230 | static void pch_post_disable_crt(struct intel_atomic_state *state, |
231 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
232 | const struct intel_crtc_state *old_crtc_state, |
233 | const struct drm_connector_state *old_conn_state) | |
1ea56e26 | 234 | { |
ede9771d | 235 | intel_disable_crt(state, encoder, old_crtc_state, old_conn_state); |
1ea56e26 | 236 | } |
abfdc1e3 | 237 | |
ede9771d VS |
238 | static void hsw_disable_crt(struct intel_atomic_state *state, |
239 | struct intel_encoder *encoder, | |
3daa3cee JN |
240 | const struct intel_crtc_state *old_crtc_state, |
241 | const struct drm_connector_state *old_conn_state) | |
242 | { | |
c249f1f4 | 243 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
3daa3cee | 244 | |
6a79c289 | 245 | drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); |
3daa3cee JN |
246 | |
247 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
248 | } | |
249 | ||
ede9771d VS |
250 | static void hsw_post_disable_crt(struct intel_atomic_state *state, |
251 | struct intel_encoder *encoder, | |
5f88a9c6 VS |
252 | const struct intel_crtc_state *old_crtc_state, |
253 | const struct drm_connector_state *old_conn_state) | |
b7076546 | 254 | { |
718cc87e | 255 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
b7076546 ML |
256 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
257 | ||
773b4b54 VS |
258 | intel_crtc_vblank_off(old_crtc_state); |
259 | ||
8c66081b | 260 | intel_disable_transcoder(old_crtc_state); |
773b4b54 VS |
261 | |
262 | intel_ddi_disable_transcoder_func(old_crtc_state); | |
263 | ||
9eae5e27 | 264 | ilk_pfit_disable(old_crtc_state); |
773b4b54 | 265 | |
55a4679e | 266 | intel_ddi_disable_transcoder_clock(old_crtc_state); |
afb2c443 | 267 | |
ede9771d | 268 | pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state); |
b7076546 | 269 | |
718cc87e | 270 | lpt_pch_disable(state, crtc); |
b7076546 | 271 | |
d39ef5d5 | 272 | hsw_fdi_disable(encoder); |
3daa3cee | 273 | |
6a79c289 | 274 | drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); |
3daa3cee JN |
275 | |
276 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
b7076546 ML |
277 | } |
278 | ||
ede9771d VS |
279 | static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state, |
280 | struct intel_encoder *encoder, | |
c249f1f4 | 281 | const struct intel_crtc_state *crtc_state, |
51c4fa69 JN |
282 | const struct drm_connector_state *conn_state) |
283 | { | |
c249f1f4 | 284 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
51c4fa69 | 285 | |
6a79c289 | 286 | drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); |
51c4fa69 JN |
287 | |
288 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
289 | } | |
290 | ||
ede9771d VS |
291 | static void hsw_pre_enable_crt(struct intel_atomic_state *state, |
292 | struct intel_encoder *encoder, | |
c249f1f4 | 293 | const struct intel_crtc_state *crtc_state, |
51c4fa69 JN |
294 | const struct drm_connector_state *conn_state) |
295 | { | |
c249f1f4 | 296 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2225f3c6 | 297 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
c249f1f4 | 298 | enum pipe pipe = crtc->pipe; |
51c4fa69 | 299 | |
6a79c289 | 300 | drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); |
51c4fa69 JN |
301 | |
302 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
27d81c28 | 303 | |
6a6d79de | 304 | hsw_fdi_link_train(encoder, crtc_state); |
afb2c443 | 305 | |
55a4679e | 306 | intel_ddi_enable_transcoder_clock(encoder, crtc_state); |
51c4fa69 JN |
307 | } |
308 | ||
ede9771d VS |
309 | static void hsw_enable_crt(struct intel_atomic_state *state, |
310 | struct intel_encoder *encoder, | |
c249f1f4 | 311 | const struct intel_crtc_state *crtc_state, |
51c4fa69 JN |
312 | const struct drm_connector_state *conn_state) |
313 | { | |
c249f1f4 | 314 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2225f3c6 | 315 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
c249f1f4 | 316 | enum pipe pipe = crtc->pipe; |
51c4fa69 | 317 | |
6a79c289 | 318 | drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); |
51c4fa69 | 319 | |
eed22a46 | 320 | intel_ddi_enable_transcoder_func(encoder, crtc_state); |
7c2fedd7 | 321 | |
8c66081b | 322 | intel_enable_transcoder(crtc_state); |
21fd23ac | 323 | |
ccebd0e4 | 324 | lpt_pch_enable(state, crtc); |
21fd23ac JN |
325 | |
326 | intel_crtc_vblank_on(crtc_state); | |
327 | ||
c249f1f4 | 328 | intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); |
51c4fa69 | 329 | |
7b06894b JN |
330 | intel_crtc_wait_for_next_vblank(crtc); |
331 | intel_crtc_wait_for_next_vblank(crtc); | |
51c4fa69 JN |
332 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
333 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
334 | } | |
335 | ||
ede9771d VS |
336 | static void intel_enable_crt(struct intel_atomic_state *state, |
337 | struct intel_encoder *encoder, | |
c249f1f4 | 338 | const struct intel_crtc_state *crtc_state, |
5f88a9c6 | 339 | const struct drm_connector_state *conn_state) |
637f44d2 | 340 | { |
c249f1f4 | 341 | intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON); |
637f44d2 AJ |
342 | } |
343 | ||
c19de8eb DL |
344 | static enum drm_mode_status |
345 | intel_crt_mode_valid(struct drm_connector *connector, | |
346 | struct drm_display_mode *mode) | |
79e53945 | 347 | { |
6bcdcd9e | 348 | struct drm_device *dev = connector->dev; |
6e266956 TU |
349 | struct drm_i915_private *dev_priv = to_i915(dev); |
350 | int max_dotclk = dev_priv->max_dotclk_freq; | |
20c2dbff | 351 | enum drm_mode_status status; |
debded84 | 352 | int max_clock; |
6bcdcd9e | 353 | |
20c2dbff VS |
354 | status = intel_cpu_transcoder_mode_valid(dev_priv, mode); |
355 | if (status != MODE_OK) | |
356 | return status; | |
357 | ||
e4dd27aa VS |
358 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
359 | return MODE_NO_DBLESCAN; | |
360 | ||
6bcdcd9e ZY |
361 | if (mode->clock < 25000) |
362 | return MODE_CLOCK_LOW; | |
363 | ||
6e266956 | 364 | if (HAS_PCH_LPT(dev_priv)) |
debded84 | 365 | max_clock = 180000; |
11a914c2 | 366 | else if (IS_VALLEYVIEW(dev_priv)) |
debded84 VS |
367 | /* |
368 | * 270 MHz due to current DPLL limits, | |
369 | * DAC limit supposedly 355 MHz. | |
370 | */ | |
371 | max_clock = 270000; | |
93e7e61e | 372 | else if (IS_DISPLAY_VER(dev_priv, 3, 4)) |
6bcdcd9e | 373 | max_clock = 400000; |
debded84 VS |
374 | else |
375 | max_clock = 350000; | |
6bcdcd9e ZY |
376 | if (mode->clock > max_clock) |
377 | return MODE_CLOCK_HIGH; | |
79e53945 | 378 | |
f8700b34 MK |
379 | if (mode->clock > max_dotclk) |
380 | return MODE_CLOCK_HIGH; | |
381 | ||
d4b1931c | 382 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
6e266956 | 383 | if (HAS_PCH_LPT(dev_priv) && |
9eae5e27 | 384 | ilk_get_lanes_required(mode->clock, 270000, 24) > 2) |
d4b1931c PZ |
385 | return MODE_CLOCK_HIGH; |
386 | ||
ad193bc6 VS |
387 | /* HSW/BDW FDI limited to 4k */ |
388 | if (mode->hdisplay > 4096) | |
389 | return MODE_H_ILLEGAL; | |
390 | ||
79e53945 JB |
391 | return MODE_OK; |
392 | } | |
393 | ||
204474a6 LP |
394 | static int intel_crt_compute_config(struct intel_encoder *encoder, |
395 | struct intel_crtc_state *pipe_config, | |
396 | struct drm_connector_state *conn_state) | |
2f26cdc0 | 397 | { |
e4dd27aa | 398 | struct drm_display_mode *adjusted_mode = |
1326a92c | 399 | &pipe_config->hw.adjusted_mode; |
e4dd27aa VS |
400 | |
401 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
204474a6 | 402 | return -EINVAL; |
e4dd27aa | 403 | |
a04d27cd | 404 | pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; |
d9facae6 | 405 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
204474a6 LP |
406 | |
407 | return 0; | |
2f26cdc0 JN |
408 | } |
409 | ||
204474a6 LP |
410 | static int pch_crt_compute_config(struct intel_encoder *encoder, |
411 | struct intel_crtc_state *pipe_config, | |
412 | struct drm_connector_state *conn_state) | |
2f26cdc0 | 413 | { |
e4dd27aa | 414 | struct drm_display_mode *adjusted_mode = |
1326a92c | 415 | &pipe_config->hw.adjusted_mode; |
e4dd27aa VS |
416 | |
417 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
204474a6 | 418 | return -EINVAL; |
e4dd27aa | 419 | |
2f26cdc0 | 420 | pipe_config->has_pch_encoder = true; |
998d2cd3 ID |
421 | if (!intel_fdi_compute_pipe_bpp(pipe_config)) |
422 | return -EINVAL; | |
423 | ||
d9facae6 | 424 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
2f26cdc0 | 425 | |
204474a6 | 426 | return 0; |
2f26cdc0 JN |
427 | } |
428 | ||
204474a6 LP |
429 | static int hsw_crt_compute_config(struct intel_encoder *encoder, |
430 | struct intel_crtc_state *pipe_config, | |
431 | struct drm_connector_state *conn_state) | |
79e53945 | 432 | { |
4f8036a2 | 433 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e4dd27aa | 434 | struct drm_display_mode *adjusted_mode = |
1326a92c | 435 | &pipe_config->hw.adjusted_mode; |
e4dd27aa VS |
436 | |
437 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
204474a6 | 438 | return -EINVAL; |
5bfe2ac0 | 439 | |
ad193bc6 VS |
440 | /* HSW/BDW FDI limited to 4k */ |
441 | if (adjusted_mode->crtc_hdisplay > 4096 || | |
442 | adjusted_mode->crtc_hblank_start > 4096) | |
204474a6 | 443 | return -EINVAL; |
ad193bc6 | 444 | |
2f26cdc0 | 445 | pipe_config->has_pch_encoder = true; |
998d2cd3 ID |
446 | if (!intel_fdi_compute_pipe_bpp(pipe_config)) |
447 | return -EINVAL; | |
448 | ||
d9facae6 | 449 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
5bfe2ac0 | 450 | |
2a7aceec | 451 | /* LPT FDI RX only supports 8bpc. */ |
4f8036a2 | 452 | if (HAS_PCH_LPT(dev_priv)) { |
998d2cd3 | 453 | /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */ |
f58a1acc | 454 | if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { |
57a333f8 WK |
455 | drm_dbg_kms(&dev_priv->drm, |
456 | "LPT only supports 24bpp\n"); | |
204474a6 | 457 | return -EINVAL; |
f58a1acc DV |
458 | } |
459 | ||
2a7aceec | 460 | pipe_config->pipe_bpp = 24; |
f58a1acc | 461 | } |
2a7aceec | 462 | |
8f7abfd8 | 463 | /* FDI must always be 2.7 GHz */ |
2f26cdc0 | 464 | pipe_config->port_clock = 135000 * 2; |
00490c22 | 465 | |
3072a24c VS |
466 | pipe_config->enhanced_framing = true; |
467 | ||
665a7b04 VS |
468 | adjusted_mode->crtc_clock = lpt_iclkip(pipe_config); |
469 | ||
204474a6 | 470 | return 0; |
79e53945 JB |
471 | } |
472 | ||
9eae5e27 | 473 | static bool ilk_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
474 | { |
475 | struct drm_device *dev = connector->dev; | |
43a6d19c | 476 | struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); |
fac5e23e | 477 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7dbb2f2 | 478 | u32 adpa; |
2c07245f ZW |
479 | bool ret; |
480 | ||
e7dbb2f2 KP |
481 | /* The first time through, trigger an explicit detection cycle */ |
482 | if (crt->force_hotplug_required) { | |
6e266956 | 483 | bool turn_off_dac = HAS_PCH_SPLIT(dev_priv); |
e7dbb2f2 | 484 | u32 save_adpa; |
67941da2 | 485 | |
6251215f | 486 | crt->force_hotplug_required = false; |
e7dbb2f2 | 487 | |
5b770f18 | 488 | save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); |
57a333f8 WK |
489 | drm_dbg_kms(&dev_priv->drm, |
490 | "trigger hotplug detect cycle: adpa=0x%x\n", adpa); | |
e7dbb2f2 KP |
491 | |
492 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
493 | if (turn_off_dac) | |
494 | adpa &= ~ADPA_DAC_ENABLE; | |
495 | ||
5b770f18 | 496 | intel_de_write(dev_priv, crt->adpa_reg, adpa); |
e7dbb2f2 | 497 | |
4cb3b44d | 498 | if (intel_de_wait_for_clear(dev_priv, |
e1672d1c | 499 | crt->adpa_reg, |
4cb3b44d | 500 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER, |
e1672d1c | 501 | 1000)) |
57a333f8 WK |
502 | drm_dbg_kms(&dev_priv->drm, |
503 | "timed out waiting for FORCE_TRIGGER"); | |
e7dbb2f2 KP |
504 | |
505 | if (turn_off_dac) { | |
5b770f18 JN |
506 | intel_de_write(dev_priv, crt->adpa_reg, save_adpa); |
507 | intel_de_posting_read(dev_priv, crt->adpa_reg); | |
e7dbb2f2 | 508 | } |
a4a6b901 ZW |
509 | } |
510 | ||
2c07245f | 511 | /* Check the status to see if both blue and green are on now */ |
5b770f18 | 512 | adpa = intel_de_read(dev_priv, crt->adpa_reg); |
e7dbb2f2 | 513 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
514 | ret = true; |
515 | else | |
516 | ret = false; | |
57a333f8 WK |
517 | drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n", |
518 | adpa, ret); | |
2c07245f | 519 | |
2c07245f | 520 | return ret; |
79e53945 JB |
521 | } |
522 | ||
7d2c24e8 JB |
523 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
524 | { | |
525 | struct drm_device *dev = connector->dev; | |
43a6d19c | 526 | struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); |
fac5e23e | 527 | struct drm_i915_private *dev_priv = to_i915(dev); |
b236d7c8 | 528 | bool reenable_hpd; |
7d2c24e8 JB |
529 | u32 adpa; |
530 | bool ret; | |
531 | u32 save_adpa; | |
532 | ||
b236d7c8 L |
533 | /* |
534 | * Doing a force trigger causes a hpd interrupt to get sent, which can | |
535 | * get us stuck in a loop if we're polling: | |
536 | * - We enable power wells and reset the ADPA | |
537 | * - output_poll_exec does force probe on VGA, triggering a hpd | |
538 | * - HPD handler waits for poll to unlock dev->mode_config.mutex | |
539 | * - output_poll_exec shuts off the ADPA, unlocks | |
540 | * dev->mode_config.mutex | |
541 | * - HPD handler runs, resets ADPA and brings us back to the start | |
542 | * | |
543 | * Just disable HPD interrupts here to prevent this | |
544 | */ | |
545 | reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); | |
546 | ||
5b770f18 | 547 | save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); |
57a333f8 WK |
548 | drm_dbg_kms(&dev_priv->drm, |
549 | "trigger hotplug detect cycle: adpa=0x%x\n", adpa); | |
7d2c24e8 JB |
550 | |
551 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
552 | ||
5b770f18 | 553 | intel_de_write(dev_priv, crt->adpa_reg, adpa); |
7d2c24e8 | 554 | |
4cb3b44d DCS |
555 | if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg, |
556 | ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) { | |
57a333f8 WK |
557 | drm_dbg_kms(&dev_priv->drm, |
558 | "timed out waiting for FORCE_TRIGGER"); | |
5b770f18 | 559 | intel_de_write(dev_priv, crt->adpa_reg, save_adpa); |
7d2c24e8 JB |
560 | } |
561 | ||
562 | /* Check the status to see if both blue and green are on now */ | |
5b770f18 | 563 | adpa = intel_de_read(dev_priv, crt->adpa_reg); |
7d2c24e8 JB |
564 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
565 | ret = true; | |
566 | else | |
567 | ret = false; | |
568 | ||
57a333f8 WK |
569 | drm_dbg_kms(&dev_priv->drm, |
570 | "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); | |
7d2c24e8 | 571 | |
b236d7c8 L |
572 | if (reenable_hpd) |
573 | intel_hpd_enable(dev_priv, crt->base.hpd_pin); | |
574 | ||
7d2c24e8 JB |
575 | return ret; |
576 | } | |
577 | ||
79e53945 JB |
578 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
579 | { | |
580 | struct drm_device *dev = connector->dev; | |
fac5e23e | 581 | struct drm_i915_private *dev_priv = to_i915(dev); |
0706f17c | 582 | u32 stat; |
7a772c49 | 583 | bool ret = false; |
771cb081 | 584 | int i, tries = 0; |
2c07245f | 585 | |
6e266956 | 586 | if (HAS_PCH_SPLIT(dev_priv)) |
9eae5e27 | 587 | return ilk_crt_detect_hotplug(connector); |
2c07245f | 588 | |
11a914c2 | 589 | if (IS_VALLEYVIEW(dev_priv)) |
7d2c24e8 JB |
590 | return valleyview_crt_detect_hotplug(connector); |
591 | ||
771cb081 ZY |
592 | /* |
593 | * On 4 series desktop, CRT detect sequence need to be done twice | |
594 | * to get a reliable result. | |
595 | */ | |
79e53945 | 596 | |
1c0f1b3d | 597 | if (IS_G45(dev_priv)) |
771cb081 ZY |
598 | tries = 2; |
599 | else | |
600 | tries = 1; | |
771cb081 | 601 | |
771cb081 | 602 | for (i = 0; i < tries ; i++) { |
771cb081 | 603 | /* turn on the FORCE_DETECT */ |
0706f17c EE |
604 | i915_hotplug_interrupt_update(dev_priv, |
605 | CRT_HOTPLUG_FORCE_DETECT, | |
606 | CRT_HOTPLUG_FORCE_DETECT); | |
771cb081 | 607 | /* wait for FORCE_DETECT to go off */ |
4cb3b44d DCS |
608 | if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN, |
609 | CRT_HOTPLUG_FORCE_DETECT, 1000)) | |
57a333f8 WK |
610 | drm_dbg_kms(&dev_priv->drm, |
611 | "timed out waiting for FORCE_DETECT to go off"); | |
771cb081 | 612 | } |
79e53945 | 613 | |
5b770f18 | 614 | stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT); |
7a772c49 AJ |
615 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
616 | ret = true; | |
617 | ||
618 | /* clear the interrupt we just generated, if any */ | |
5b770f18 | 619 | intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
79e53945 | 620 | |
0706f17c | 621 | i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); |
7a772c49 AJ |
622 | |
623 | return ret; | |
79e53945 JB |
624 | } |
625 | ||
27cbdc6b | 626 | static const struct drm_edid *intel_crt_get_edid(struct drm_connector *connector, |
30b98ecb | 627 | struct i2c_adapter *ddc) |
f1a2f5b7 | 628 | { |
27cbdc6b | 629 | const struct drm_edid *drm_edid; |
f1a2f5b7 | 630 | |
30b98ecb | 631 | drm_edid = drm_edid_read_ddc(connector, ddc); |
f1a2f5b7 | 632 | |
30b98ecb | 633 | if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { |
d518a20b JN |
634 | drm_dbg_kms(connector->dev, |
635 | "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
30b98ecb VS |
636 | intel_gmbus_force_bit(ddc, true); |
637 | drm_edid = drm_edid_read_ddc(connector, ddc); | |
638 | intel_gmbus_force_bit(ddc, false); | |
f1a2f5b7 JN |
639 | } |
640 | ||
27cbdc6b | 641 | return drm_edid; |
f1a2f5b7 JN |
642 | } |
643 | ||
644 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ | |
645 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, | |
30b98ecb | 646 | struct i2c_adapter *ddc) |
f1a2f5b7 | 647 | { |
27cbdc6b | 648 | const struct drm_edid *drm_edid; |
ebda95a9 | 649 | int ret; |
f1a2f5b7 | 650 | |
30b98ecb | 651 | drm_edid = intel_crt_get_edid(connector, ddc); |
27cbdc6b | 652 | if (!drm_edid) |
f1a2f5b7 JN |
653 | return 0; |
654 | ||
27cbdc6b JN |
655 | ret = intel_connector_update_modes(connector, drm_edid); |
656 | ||
657 | drm_edid_free(drm_edid); | |
ebda95a9 JN |
658 | |
659 | return ret; | |
f1a2f5b7 JN |
660 | } |
661 | ||
f5afcd3d | 662 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 663 | { |
43a6d19c | 664 | struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); |
fac5e23e | 665 | struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); |
27cbdc6b | 666 | const struct drm_edid *drm_edid; |
c96b63a6 | 667 | bool ret = false; |
79e53945 | 668 | |
96f0ef50 | 669 | drm_edid = intel_crt_get_edid(connector, connector->ddc); |
a2bd1f54 | 670 | |
27cbdc6b | 671 | if (drm_edid) { |
f5afcd3d DM |
672 | /* |
673 | * This may be a DVI-I connector with a shared DDC | |
674 | * link between analog and digital outputs, so we | |
675 | * have to check the EDID input spec of the attached device. | |
676 | */ | |
e1039cde | 677 | if (drm_edid_is_digital(drm_edid)) { |
57a333f8 | 678 | drm_dbg_kms(&dev_priv->drm, |
e1039cde | 679 | "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
c96b63a6 | 680 | } else { |
57a333f8 | 681 | drm_dbg_kms(&dev_priv->drm, |
e1039cde JN |
682 | "CRT detected via DDC:0x50 [EDID]\n"); |
683 | ret = true; | |
f5afcd3d | 684 | } |
a2bd1f54 | 685 | } else { |
57a333f8 WK |
686 | drm_dbg_kms(&dev_priv->drm, |
687 | "CRT not detected via DDC:0x50 [no valid EDID found]\n"); | |
6ec3d0c0 CW |
688 | } |
689 | ||
27cbdc6b | 690 | drm_edid_free(drm_edid); |
a2bd1f54 | 691 | |
c96b63a6 | 692 | return ret; |
79e53945 JB |
693 | } |
694 | ||
e4a5d54f | 695 | static enum drm_connector_status |
5ac421a9 | 696 | intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) |
e4a5d54f | 697 | { |
7173188d | 698 | struct drm_device *dev = crt->base.base.dev; |
fac5e23e | 699 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ac421a9 | 700 | enum transcoder cpu_transcoder = (enum transcoder)pipe; |
c7cc5216 JN |
701 | u32 save_bclrpat; |
702 | u32 save_vtotal; | |
703 | u32 vtotal, vactive; | |
704 | u32 vsample; | |
705 | u32 vblank, vblank_start, vblank_end; | |
706 | u32 dsl; | |
c7cc5216 | 707 | u8 st00; |
e4a5d54f ML |
708 | enum drm_connector_status status; |
709 | ||
57a333f8 | 710 | drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n"); |
6ec3d0c0 | 711 | |
5ac421a9 VS |
712 | save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder)); |
713 | save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); | |
714 | vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); | |
e4a5d54f | 715 | |
050db7d7 VS |
716 | vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1; |
717 | vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1; | |
e4a5d54f | 718 | |
050db7d7 VS |
719 | vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1; |
720 | vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1; | |
e4a5d54f ML |
721 | |
722 | /* Set the border color to purple. */ | |
5ac421a9 | 723 | intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050); |
e4a5d54f | 724 | |
93e7e61e | 725 | if (DISPLAY_VER(dev_priv) != 2) { |
3eb08ea5 | 726 | u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); |
f0798d8f | 727 | |
3eb08ea5 VS |
728 | intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), |
729 | transconf | TRANSCONF_FORCE_BORDER); | |
730 | intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); | |
e4a5d54f ML |
731 | /* Wait for next Vblank to substitue |
732 | * border color for Color info */ | |
f35ed346 | 733 | intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); |
f0798d8f | 734 | st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE); |
e4a5d54f ML |
735 | status = ((st00 & (1 << 4)) != 0) ? |
736 | connector_status_connected : | |
737 | connector_status_disconnected; | |
738 | ||
3eb08ea5 | 739 | intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), transconf); |
e4a5d54f ML |
740 | } else { |
741 | bool restore_vblank = false; | |
742 | int count, detect; | |
743 | ||
744 | /* | |
745 | * If there isn't any border, add some. | |
746 | * Yes, this will flicker | |
747 | */ | |
748 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
5ac421a9 | 749 | u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); |
050db7d7 | 750 | u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1; |
e4a5d54f ML |
751 | |
752 | vblank_start = vsync_start; | |
5ac421a9 | 753 | intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), |
050db7d7 VS |
754 | VBLANK_START(vblank_start - 1) | |
755 | VBLANK_END(vblank_end - 1)); | |
e4a5d54f ML |
756 | restore_vblank = true; |
757 | } | |
758 | /* sample in the vertical border, selecting the larger one */ | |
759 | if (vblank_start - vactive >= vtotal - vblank_end) | |
760 | vsample = (vblank_start + vactive) >> 1; | |
761 | else | |
762 | vsample = (vtotal + vblank_end) >> 1; | |
763 | ||
764 | /* | |
765 | * Wait for the border to be displayed | |
766 | */ | |
f0798d8f | 767 | while (intel_de_read(dev_priv, PIPEDSL(pipe)) >= vactive) |
e4a5d54f | 768 | ; |
f0798d8f | 769 | while ((dsl = intel_de_read(dev_priv, PIPEDSL(pipe))) <= vsample) |
e4a5d54f ML |
770 | ; |
771 | /* | |
772 | * Watch ST00 for an entire scanline | |
773 | */ | |
774 | detect = 0; | |
775 | count = 0; | |
776 | do { | |
777 | count++; | |
778 | /* Read the ST00 VGA status register */ | |
f0798d8f | 779 | st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE); |
e4a5d54f ML |
780 | if (st00 & (1 << 4)) |
781 | detect++; | |
f0798d8f | 782 | } while ((intel_de_read(dev_priv, PIPEDSL(pipe)) == dsl)); |
e4a5d54f ML |
783 | |
784 | /* restore vblank if necessary */ | |
785 | if (restore_vblank) | |
5ac421a9 | 786 | intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), vblank); |
e4a5d54f ML |
787 | /* |
788 | * If more than 3/4 of the scanline detected a monitor, | |
789 | * then it is assumed to be present. This works even on i830, | |
790 | * where there isn't any way to force the border color across | |
791 | * the screen | |
792 | */ | |
793 | status = detect * 4 > count * 3 ? | |
794 | connector_status_connected : | |
795 | connector_status_disconnected; | |
796 | } | |
797 | ||
798 | /* Restore previous settings */ | |
5ac421a9 | 799 | intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), save_bclrpat); |
e4a5d54f ML |
800 | |
801 | return status; | |
802 | } | |
803 | ||
f0dfb1a8 VS |
804 | static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id) |
805 | { | |
806 | DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); | |
807 | return 1; | |
808 | } | |
809 | ||
810 | static const struct dmi_system_id intel_spurious_crt_detect[] = { | |
811 | { | |
812 | .callback = intel_spurious_crt_detect_dmi_callback, | |
813 | .ident = "ACER ZGB", | |
814 | .matches = { | |
815 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
816 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
817 | }, | |
818 | }, | |
69a44b16 VS |
819 | { |
820 | .callback = intel_spurious_crt_detect_dmi_callback, | |
821 | .ident = "Intel DZ77BH-55K", | |
822 | .matches = { | |
823 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"), | |
824 | DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"), | |
825 | }, | |
826 | }, | |
f0dfb1a8 VS |
827 | { } |
828 | }; | |
829 | ||
6c5ed5ae ML |
830 | static int |
831 | intel_crt_detect(struct drm_connector *connector, | |
832 | struct drm_modeset_acquire_ctx *ctx, | |
833 | bool force) | |
79e53945 | 834 | { |
66478475 | 835 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
43a6d19c | 836 | struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); |
671dedd2 | 837 | struct intel_encoder *intel_encoder = &crt->base; |
8902a55d | 838 | struct drm_atomic_state *state; |
0e6e0be4 | 839 | intel_wakeref_t wakeref; |
8902a55d | 840 | int status; |
79e53945 | 841 | |
57a333f8 WK |
842 | drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n", |
843 | connector->base.id, connector->name, | |
844 | force); | |
164c8598 | 845 | |
fe63ea7c | 846 | if (!intel_display_device_enabled(dev_priv)) |
b81dddb9 VS |
847 | return connector_status_disconnected; |
848 | ||
8a25c4be | 849 | if (dev_priv->params.load_detect_test) { |
0e6e0be4 CW |
850 | wakeref = intel_display_power_get(dev_priv, |
851 | intel_encoder->power_domain); | |
4165791d VS |
852 | goto load_detect; |
853 | } | |
854 | ||
f0dfb1a8 VS |
855 | /* Skip machines without VGA that falsely report hotplug events */ |
856 | if (dmi_check_system(intel_spurious_crt_detect)) | |
857 | return connector_status_disconnected; | |
858 | ||
0e6e0be4 CW |
859 | wakeref = intel_display_power_get(dev_priv, |
860 | intel_encoder->power_domain); | |
671dedd2 | 861 | |
56b857a5 | 862 | if (I915_HAS_HOTPLUG(dev_priv)) { |
aaa37730 DV |
863 | /* We can not rely on the HPD pin always being correctly wired |
864 | * up, for example many KVM do not pass it through, and so | |
865 | * only trust an assertion that the monitor is connected. | |
866 | */ | |
6ec3d0c0 | 867 | if (intel_crt_detect_hotplug(connector)) { |
57a333f8 WK |
868 | drm_dbg_kms(&dev_priv->drm, |
869 | "CRT detected via hotplug\n"); | |
c19a0df2 PZ |
870 | status = connector_status_connected; |
871 | goto out; | |
aaa37730 | 872 | } else |
57a333f8 WK |
873 | drm_dbg_kms(&dev_priv->drm, |
874 | "CRT not detected via hotplug\n"); | |
79e53945 JB |
875 | } |
876 | ||
c19a0df2 PZ |
877 | if (intel_crt_detect_ddc(connector)) { |
878 | status = connector_status_connected; | |
879 | goto out; | |
880 | } | |
79e53945 | 881 | |
aaa37730 DV |
882 | /* Load detection is broken on HPD capable machines. Whoever wants a |
883 | * broken monitor (without edid) to work behind a broken kvm (that fails | |
884 | * to have the right resistors for HP detection) needs to fix this up. | |
885 | * For now just bail out. */ | |
4165791d | 886 | if (I915_HAS_HOTPLUG(dev_priv)) { |
c19a0df2 PZ |
887 | status = connector_status_disconnected; |
888 | goto out; | |
889 | } | |
aaa37730 | 890 | |
4165791d | 891 | load_detect: |
c19a0df2 PZ |
892 | if (!force) { |
893 | status = connector->status; | |
894 | goto out; | |
895 | } | |
7b334fcb | 896 | |
e4a5d54f | 897 | /* for pre-945g platforms use load detect */ |
8902a55d JN |
898 | state = intel_load_detect_get_pipe(connector, ctx); |
899 | if (IS_ERR(state)) { | |
900 | status = PTR_ERR(state); | |
901 | } else if (!state) { | |
902 | status = connector_status_unknown; | |
903 | } else { | |
e95c8438 DV |
904 | if (intel_crt_detect_ddc(connector)) |
905 | status = connector_status_connected; | |
005e9537 | 906 | else if (DISPLAY_VER(dev_priv) < 4) |
c8ecb2f1 ML |
907 | status = intel_crt_load_detect(crt, |
908 | to_intel_crtc(connector->state->crtc)->pipe); | |
8a25c4be | 909 | else if (dev_priv->params.load_detect_test) |
32fff610 | 910 | status = connector_status_disconnected; |
5bedeb2d DV |
911 | else |
912 | status = connector_status_unknown; | |
8902a55d | 913 | intel_load_detect_release_pipe(connector, state, ctx); |
2927e421 | 914 | } |
208bf9fd | 915 | |
c19a0df2 | 916 | out: |
0e6e0be4 | 917 | intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); |
a8ddac7c | 918 | |
e4a5d54f | 919 | return status; |
79e53945 JB |
920 | } |
921 | ||
79e53945 JB |
922 | static int intel_crt_get_modes(struct drm_connector *connector) |
923 | { | |
8e4d36b9 | 924 | struct drm_device *dev = connector->dev; |
fac5e23e | 925 | struct drm_i915_private *dev_priv = to_i915(dev); |
43a6d19c | 926 | struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector)); |
671dedd2 | 927 | struct intel_encoder *intel_encoder = &crt->base; |
0e6e0be4 | 928 | intel_wakeref_t wakeref; |
30b98ecb | 929 | struct i2c_adapter *ddc; |
0e6e0be4 | 930 | int ret; |
8e4d36b9 | 931 | |
0e6e0be4 CW |
932 | wakeref = intel_display_power_get(dev_priv, |
933 | intel_encoder->power_domain); | |
671dedd2 | 934 | |
96f0ef50 | 935 | ret = intel_crt_ddc_get_modes(connector, connector->ddc); |
9beb5fea | 936 | if (ret || !IS_G4X(dev_priv)) |
671dedd2 | 937 | goto out; |
8e4d36b9 | 938 | |
8e4d36b9 | 939 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
30b98ecb VS |
940 | ddc = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); |
941 | ret = intel_crt_ddc_get_modes(connector, ddc); | |
671dedd2 ID |
942 | |
943 | out: | |
0e6e0be4 | 944 | intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); |
671dedd2 ID |
945 | |
946 | return ret; | |
79e53945 JB |
947 | } |
948 | ||
9504a892 | 949 | void intel_crt_reset(struct drm_encoder *encoder) |
f3269058 | 950 | { |
66478475 | 951 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
28cf71ce | 952 | struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); |
f3269058 | 953 | |
005e9537 | 954 | if (DISPLAY_VER(dev_priv) >= 5) { |
2e938892 DV |
955 | u32 adpa; |
956 | ||
5b770f18 | 957 | adpa = intel_de_read(dev_priv, crt->adpa_reg); |
2e938892 DV |
958 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
959 | adpa |= ADPA_HOTPLUG_BITS; | |
5b770f18 JN |
960 | intel_de_write(dev_priv, crt->adpa_reg, adpa); |
961 | intel_de_posting_read(dev_priv, crt->adpa_reg); | |
2e938892 | 962 | |
57a333f8 | 963 | drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa); |
6251215f | 964 | crt->force_hotplug_required = true; |
2e938892 DV |
965 | } |
966 | ||
f3269058 CW |
967 | } |
968 | ||
79e53945 JB |
969 | /* |
970 | * Routines for controlling stuff on the analog port | |
971 | */ | |
972 | ||
79e53945 | 973 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
79e53945 | 974 | .fill_modes = drm_helper_probe_single_connector_modes, |
1ebaa0b9 | 975 | .late_register = intel_connector_register, |
c191eca1 | 976 | .early_unregister = intel_connector_unregister, |
d4b26e4f | 977 | .destroy = intel_connector_destroy, |
c6f95f27 | 978 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 979 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
79e53945 JB |
980 | }; |
981 | ||
982 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
6c5ed5ae | 983 | .detect_ctx = intel_crt_detect, |
79e53945 JB |
984 | .mode_valid = intel_crt_mode_valid, |
985 | .get_modes = intel_crt_get_modes, | |
79e53945 JB |
986 | }; |
987 | ||
79e53945 | 988 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
28cf71ce | 989 | .reset = intel_crt_reset, |
ea5b213a | 990 | .destroy = intel_encoder_destroy, |
79e53945 JB |
991 | }; |
992 | ||
c39055b0 | 993 | void intel_crt_init(struct drm_i915_private *dev_priv) |
79e53945 JB |
994 | { |
995 | struct drm_connector *connector; | |
c9a1c4cd | 996 | struct intel_crt *crt; |
454c1ca8 | 997 | struct intel_connector *intel_connector; |
6c03a6bd | 998 | i915_reg_t adpa_reg; |
96f0ef50 | 999 | u8 ddc_pin; |
6c03a6bd | 1000 | u32 adpa; |
79e53945 | 1001 | |
6e266956 | 1002 | if (HAS_PCH_SPLIT(dev_priv)) |
6c03a6bd | 1003 | adpa_reg = PCH_ADPA; |
11a914c2 | 1004 | else if (IS_VALLEYVIEW(dev_priv)) |
6c03a6bd VS |
1005 | adpa_reg = VLV_ADPA; |
1006 | else | |
1007 | adpa_reg = ADPA; | |
1008 | ||
5b770f18 | 1009 | adpa = intel_de_read(dev_priv, adpa_reg); |
6c03a6bd VS |
1010 | if ((adpa & ADPA_DAC_ENABLE) == 0) { |
1011 | /* | |
1012 | * On some machines (some IVB at least) CRT can be | |
1013 | * fused off, but there's no known fuse bit to | |
1014 | * indicate that. On these machine the ADPA register | |
1015 | * works normally, except the DAC enable bit won't | |
1016 | * take. So the only way to tell is attempt to enable | |
1017 | * it and see what happens. | |
1018 | */ | |
5b770f18 JN |
1019 | intel_de_write(dev_priv, adpa_reg, |
1020 | adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); | |
1021 | if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0) | |
6c03a6bd | 1022 | return; |
5b770f18 | 1023 | intel_de_write(dev_priv, adpa_reg, adpa); |
6c03a6bd VS |
1024 | } |
1025 | ||
c9a1c4cd CW |
1026 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
1027 | if (!crt) | |
79e53945 JB |
1028 | return; |
1029 | ||
9bdbd0b9 | 1030 | intel_connector = intel_connector_alloc(); |
454c1ca8 | 1031 | if (!intel_connector) { |
c9a1c4cd | 1032 | kfree(crt); |
454c1ca8 ZW |
1033 | return; |
1034 | } | |
1035 | ||
96f0ef50 VS |
1036 | ddc_pin = dev_priv->display.vbt.crt_ddc_pin; |
1037 | ||
454c1ca8 | 1038 | connector = &intel_connector->base; |
637f44d2 | 1039 | crt->connector = intel_connector; |
96f0ef50 VS |
1040 | drm_connector_init_with_ddc(&dev_priv->drm, connector, |
1041 | &intel_crt_connector_funcs, | |
1042 | DRM_MODE_CONNECTOR_VGA, | |
1043 | intel_gmbus_get_adapter(dev_priv, ddc_pin)); | |
79e53945 | 1044 | |
c39055b0 | 1045 | drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, |
580d8ed5 | 1046 | DRM_MODE_ENCODER_DAC, "CRT"); |
79e53945 | 1047 | |
c9a1c4cd | 1048 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 1049 | |
c9a1c4cd | 1050 | crt->base.type = INTEL_OUTPUT_ANALOG; |
49fd5403 | 1051 | crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI); |
50a0bc90 | 1052 | if (IS_I830(dev_priv)) |
981329ce | 1053 | crt->base.pipe_mask = BIT(PIPE_A); |
59c859d6 | 1054 | else |
34053ee1 | 1055 | crt->base.pipe_mask = ~0; |
59c859d6 | 1056 | |
8648c604 VS |
1057 | if (DISPLAY_VER(dev_priv) != 2) |
1058 | connector->interlace_allowed = true; | |
79e53945 | 1059 | |
6c03a6bd | 1060 | crt->adpa_reg = adpa_reg; |
540a8950 | 1061 | |
79f255a0 ACO |
1062 | crt->base.power_domain = POWER_DOMAIN_PORT_CRT; |
1063 | ||
56b857a5 | 1064 | if (I915_HAS_HOTPLUG(dev_priv) && |
dba14b27 | 1065 | !dmi_check_system(intel_spurious_crt_detect)) { |
1d843f9d | 1066 | crt->base.hpd_pin = HPD_CRT; |
dba14b27 | 1067 | crt->base.hotplug = intel_encoder_hotplug; |
5fb908eb | 1068 | intel_connector->polled = DRM_CONNECTOR_POLL_HPD; |
9d552c22 VS |
1069 | } else { |
1070 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
dba14b27 | 1071 | } |
c5ce4ef3 | 1072 | |
4f8036a2 | 1073 | if (HAS_DDI(dev_priv)) { |
679df6f1 VS |
1074 | assert_port_valid(dev_priv, PORT_E); |
1075 | ||
03cdc1d4 | 1076 | crt->base.port = PORT_E; |
a2985791 | 1077 | crt->base.get_config = hsw_crt_get_config; |
4eda01b2 | 1078 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
2f26cdc0 | 1079 | crt->base.compute_config = hsw_crt_compute_config; |
51c4fa69 JN |
1080 | crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; |
1081 | crt->base.pre_enable = hsw_pre_enable_crt; | |
1082 | crt->base.enable = hsw_enable_crt; | |
3daa3cee | 1083 | crt->base.disable = hsw_disable_crt; |
b7076546 | 1084 | crt->base.post_disable = hsw_post_disable_crt; |
d135368d VS |
1085 | crt->base.enable_clock = hsw_ddi_enable_clock; |
1086 | crt->base.disable_clock = hsw_ddi_disable_clock; | |
0fbd8694 | 1087 | crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled; |
c40a253b VS |
1088 | |
1089 | intel_ddi_buf_trans_init(&crt->base); | |
a2985791 | 1090 | } else { |
c5ce4ef3 | 1091 | if (HAS_PCH_SPLIT(dev_priv)) { |
2f26cdc0 | 1092 | crt->base.compute_config = pch_crt_compute_config; |
c5ce4ef3 JN |
1093 | crt->base.disable = pch_disable_crt; |
1094 | crt->base.post_disable = pch_post_disable_crt; | |
1095 | } else { | |
2f26cdc0 | 1096 | crt->base.compute_config = intel_crt_compute_config; |
c5ce4ef3 JN |
1097 | crt->base.disable = intel_disable_crt; |
1098 | } | |
03cdc1d4 | 1099 | crt->base.port = PORT_NONE; |
a2985791 | 1100 | crt->base.get_config = intel_crt_get_config; |
4eda01b2 | 1101 | crt->base.get_hw_state = intel_crt_get_hw_state; |
51c4fa69 | 1102 | crt->base.enable = intel_enable_crt; |
a2985791 | 1103 | } |
e403fc94 | 1104 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
df0323c4 | 1105 | |
79e53945 JB |
1106 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
1107 | ||
68d18ad7 | 1108 | /* |
3e68320e DL |
1109 | * TODO: find a proper way to discover whether we need to set the the |
1110 | * polarity and link reversal bits or not, instead of relying on the | |
1111 | * BIOS. | |
68d18ad7 | 1112 | */ |
6e266956 | 1113 | if (HAS_PCH_LPT(dev_priv)) { |
3e68320e DL |
1114 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
1115 | FDI_RX_LINK_REVERSAL_OVERRIDE; | |
1116 | ||
20478b88 JN |
1117 | dev_priv->display.fdi.rx_config = intel_de_read(dev_priv, |
1118 | FDI_RX_CTL(PIPE_A)) & fdi_config; | |
3e68320e | 1119 | } |
754970ee | 1120 | |
28cf71ce | 1121 | intel_crt_reset(&crt->base.base); |
79e53945 | 1122 | } |