[thirdparty/kernel/stable.git] / drivers / gpu / drm / i915 / display / intel_dpll_mgr.h

/*
 * Copyright © 2012-2016 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 */

#ifndef _INTEL_DPLL_MGR_H_
#define _INTEL_DPLL_MGR_H_

#include <linux/types.h>

#include "intel_display_power.h"
#include "intel_wakeref.h"

#define for_each_shared_dpll(__i915, __pll, __i) \
	for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \
		     ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)

enum tc_port;
struct drm_i915_private;
struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_encoder;
struct intel_shared_dpll;
struct intel_shared_dpll_funcs;

/**
 * enum intel_dpll_id - possible DPLL ids
 *
 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
 */
enum intel_dpll_id {
	/**
	 * @DPLL_ID_PRIVATE: non-shared dpll in use
	 */
	DPLL_ID_PRIVATE = -1,

	/**
	 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
	 */
	DPLL_ID_PCH_PLL_A = 0,
	/**
	 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
	 */
	DPLL_ID_PCH_PLL_B = 1,


	/**
	 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1
	 */
	DPLL_ID_WRPLL1 = 0,
	/**
	 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2
	 */
	DPLL_ID_WRPLL2 = 1,
	/**
	 * @DPLL_ID_SPLL: HSW and BDW SPLL
	 */
	DPLL_ID_SPLL = 2,
	/**
	 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL
	 */
	DPLL_ID_LCPLL_810 = 3,
	/**
	 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL
	 */
	DPLL_ID_LCPLL_1350 = 4,
	/**
	 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL
	 */
	DPLL_ID_LCPLL_2700 = 5,


	/**
	 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0
	 */
	DPLL_ID_SKL_DPLL0 = 0,
	/**
	 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1
	 */
	DPLL_ID_SKL_DPLL1 = 1,
	/**
	 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2
	 */
	DPLL_ID_SKL_DPLL2 = 2,
	/**
	 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3
	 */
	DPLL_ID_SKL_DPLL3 = 3,


	/**
	 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
	 */
	DPLL_ID_ICL_DPLL0 = 0,
	/**
	 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
	 */
	DPLL_ID_ICL_DPLL1 = 1,
	/**
	 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
	 */
	DPLL_ID_EHL_DPLL4 = 2,
	/**
	 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
	 */
	DPLL_ID_ICL_TBTPLL = 2,
	/**
	 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
	 *                      TGL TC PLL 1 port 1 (TC1)
	 */
	DPLL_ID_ICL_MGPLL1 = 3,
	/**
	 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
	 *                      TGL TC PLL 1 port 2 (TC2)
	 */
	DPLL_ID_ICL_MGPLL2 = 4,
	/**
	 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
	 *                      TGL TC PLL 1 port 3 (TC3)
	 */
	DPLL_ID_ICL_MGPLL3 = 5,
	/**
	 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
	 *                      TGL TC PLL 1 port 4 (TC4)
	 */
	DPLL_ID_ICL_MGPLL4 = 6,
	/**
	 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
	 */
	DPLL_ID_TGL_MGPLL5 = 7,
	/**
	 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
	 */
	DPLL_ID_TGL_MGPLL6 = 8,

	/**
	 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
	 */
	DPLL_ID_DG1_DPLL0 = 0,
	/**
	 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
	 */
	DPLL_ID_DG1_DPLL1 = 1,
	/**
	 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
	 */
	DPLL_ID_DG1_DPLL2 = 2,
	/**
	 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
	 */
	DPLL_ID_DG1_DPLL3 = 3,
};

#define I915_NUM_PLLS 9

enum icl_port_dpll_id {
	ICL_PORT_DPLL_DEFAULT,
	ICL_PORT_DPLL_MG_PHY,

	ICL_PORT_DPLL_COUNT,
};

struct intel_dpll_hw_state {
	/* i9xx, pch plls */
	u32 dpll;
	u32 dpll_md;
	u32 fp0;
	u32 fp1;

	/* hsw, bdw */
	u32 wrpll;
	u32 spll;

	/* skl */
	/*
	 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
	 * lower part of ctrl1 and they get shifted into position when writing
	 * the register.  This allows us to easily compare the state to share
	 * the DPLL.
	 */
	u32 ctrl1;
	/* HDMI only, 0 when used for DP */
	u32 cfgcr1, cfgcr2;

	/* icl */
	u32 cfgcr0;

	/* tgl */
	u32 div0;

	/* bxt */
	u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;

	/*
	 * ICL uses the following, already defined:
	 * u32 cfgcr0, cfgcr1;
	 */
	u32 mg_refclkin_ctl;
	u32 mg_clktop2_coreclkctl1;
	u32 mg_clktop2_hsclkctl;
	u32 mg_pll_div0;
	u32 mg_pll_div1;
	u32 mg_pll_lf;
	u32 mg_pll_frac_lock;
	u32 mg_pll_ssc;
	u32 mg_pll_bias;
	u32 mg_pll_tdc_coldst_bias;
	u32 mg_pll_bias_mask;
	u32 mg_pll_tdc_coldst_bias_mask;
};

/**
 * struct intel_shared_dpll_state - hold the DPLL atomic state
 *
 * This structure holds an atomic state for the DPLL, that can represent
 * either its current state (in struct &intel_shared_dpll) or a desired
 * future state which would be applied by an atomic mode set (stored in
 * a struct &intel_atomic_state).
 *
 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
 */
struct intel_shared_dpll_state {
	/**
	 * @pipe_mask: mask of pipes using this DPLL, active or not
	 */
	u8 pipe_mask;

	/**
	 * @hw_state: hardware configuration for the DPLL stored in
	 * struct &intel_dpll_hw_state.
	 */
	struct intel_dpll_hw_state hw_state;
};

/**
 * struct dpll_info - display PLL platform specific info
 */
struct dpll_info {
	/**
	 * @name: DPLL name; used for logging
	 */
	const char *name;

	/**
	 * @funcs: platform specific hooks
	 */
	const struct intel_shared_dpll_funcs *funcs;

	/**
	 * @id: unique indentifier for this DPLL
	 */
	enum intel_dpll_id id;

	/**
	 * @power_domain: extra power domain required by the DPLL
	 */
	enum intel_display_power_domain power_domain;

	/**
	 * @always_on:
	 *
	 * Inform the state checker that the DPLL is kept enabled even if
	 * not in use by any CRTC.
	 */
	bool always_on;

	/**
	 * @is_alt_port_dpll:
	 *
	 * Inform the state checker that the DPLL can be used as a fallback
	 * (for TC->TBT fallback).
	 */
	bool is_alt_port_dpll;
};

/**
 * struct intel_shared_dpll - display PLL with tracked state and users
 */
struct intel_shared_dpll {
	/**
	 * @state:
	 *
	 * Store the state for the pll, including its hw state
	 * and CRTCs using it.
	 */
	struct intel_shared_dpll_state state;

	/**
	 * @index: index for atomic state
	 */
	u8 index;

	/**
	 * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL
	 */
	u8 active_mask;

	/**
	 * @on: is the PLL actually active? Disabled during modeset
	 */
	bool on;

	/**
	 * @info: platform specific info
	 */
	const struct dpll_info *info;

	/**
	 * @wakeref: In some platforms a device-level runtime pm reference may
	 * need to be grabbed to disable DC states while this DPLL is enabled
	 */
	intel_wakeref_t wakeref;
};

#define SKL_DPLL0 0
#define SKL_DPLL1 1
#define SKL_DPLL2 2
#define SKL_DPLL3 3

/* shared dpll functions */
struct intel_shared_dpll *
intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
			    enum intel_dpll_id id);
void assert_shared_dpll(struct drm_i915_private *i915,
			struct intel_shared_dpll *pll,
			bool state);
#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
int intel_compute_shared_dplls(struct intel_atomic_state *state,
			       struct intel_crtc *crtc,
			       struct intel_encoder *encoder);
int intel_reserve_shared_dplls(struct intel_atomic_state *state,
			       struct intel_crtc *crtc,
			       struct intel_encoder *encoder);
void intel_release_shared_dplls(struct intel_atomic_state *state,
				struct intel_crtc *crtc);
void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
					const struct intel_shared_dpll *pll,
					struct intel_shared_dpll_state *shared_dpll_state);
void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
			      enum icl_port_dpll_id port_dpll_id);
void intel_update_active_dpll(struct intel_atomic_state *state,
			      struct intel_crtc *crtc,
			      struct intel_encoder *encoder);
int intel_dpll_get_freq(struct drm_i915_private *i915,
			const struct intel_shared_dpll *pll,
			const struct intel_dpll_hw_state *pll_state);
bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
			     struct intel_shared_dpll *pll,
			     struct intel_dpll_hw_state *hw_state);
void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
void intel_shared_dpll_init(struct drm_i915_private *i915);
void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
void intel_dpll_readout_hw_state(struct drm_i915_private *i915);
void intel_dpll_sanitize_state(struct drm_i915_private *i915);

void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
			      const struct intel_dpll_hw_state *hw_state);
bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
				 const struct intel_dpll_hw_state *a,
				 const struct intel_dpll_hw_state *b);
enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
bool intel_dpll_is_combophy(enum intel_dpll_id id);

void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
				    struct intel_crtc *crtc);
void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state);

#endif /* _INTEL_DPLL_MGR_H_ */
Commit	Line	Data
ac7f11c6 ACO	1	/*
	2	* Copyright © 2012-2016 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	*/
	24
	25	#ifndef _INTEL_DPLL_MGR_H_
	26	#define _INTEL_DPLL_MGR_H_
	27
f4be705f JN	28	#include <linux/types.h>
f4be705f JN	29
7e72cd6c	30	#include "intel_display_power.h"
eef037ea	31	#include "intel_wakeref.h"
f4be705f	32
51d3e629 VS	33	#define for_each_shared_dpll(__i915, __pll, __i) \
	34	for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \
	35	((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)
	36
497520ca	37	enum tc_port;
ac7f11c6	38	struct drm_i915_private;
866955fa	39	struct intel_atomic_state;
c2a9fcd6 ACO	40	struct intel_crtc;
c2a9fcd6 ACO	41	struct intel_crtc_state;
daedf20a	42	struct intel_encoder;
daedf20a	43	struct intel_shared_dpll;
d39bc5c5	44	struct intel_shared_dpll_funcs;
f9476a6c	45
294591cf ACO	46	/**
	47	* enum intel_dpll_id - possible DPLL ids
	48	*
	49	* Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
	50	*/
ac7f11c6	51	enum intel_dpll_id {
294591cf ACO	52	/**
	53	* @DPLL_ID_PRIVATE: non-shared dpll in use
	54	*/
	55	DPLL_ID_PRIVATE = -1,
	56
	57	/**
	58	* @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
	59	*/
ac7f11c6	60	DPLL_ID_PCH_PLL_A = 0,
294591cf ACO	61	/**
	62	* @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
	63	*/
ac7f11c6	64	DPLL_ID_PCH_PLL_B = 1,
294591cf ACO	65
	66
	67	/**
	68	* @DPLL_ID_WRPLL1: HSW and BDW WRPLL1
	69	*/
ac7f11c6	70	DPLL_ID_WRPLL1 = 0,
294591cf ACO	71	/**
	72	* @DPLL_ID_WRPLL2: HSW and BDW WRPLL2
	73	*/
ac7f11c6	74	DPLL_ID_WRPLL2 = 1,
294591cf ACO	75	/**
	76	* @DPLL_ID_SPLL: HSW and BDW SPLL
	77	*/
ac7f11c6	78	DPLL_ID_SPLL = 2,
294591cf ACO	79	/**
	80	* @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL
	81	*/
9d16da65	82	DPLL_ID_LCPLL_810 = 3,
294591cf ACO	83	/**
	84	* @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL
	85	*/
9d16da65	86	DPLL_ID_LCPLL_1350 = 4,
294591cf ACO	87	/**
	88	* @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL
	89	*/
9d16da65	90	DPLL_ID_LCPLL_2700 = 5,
ac7f11c6	91
294591cf ACO	92
	93	/**
	94	* @DPLL_ID_SKL_DPLL0: SKL and later DPLL0
	95	*/
a3c988ea	96	DPLL_ID_SKL_DPLL0 = 0,
294591cf ACO	97	/**
	98	* @DPLL_ID_SKL_DPLL1: SKL and later DPLL1
	99	*/
a3c988ea	100	DPLL_ID_SKL_DPLL1 = 1,
294591cf ACO	101	/**
	102	* @DPLL_ID_SKL_DPLL2: SKL and later DPLL2
	103	*/
a3c988ea	104	DPLL_ID_SKL_DPLL2 = 2,
294591cf ACO	105	/**
	106	* @DPLL_ID_SKL_DPLL3: SKL and later DPLL3
	107	*/
a3c988ea	108	DPLL_ID_SKL_DPLL3 = 3,
c27e917e PZ	109
	110
	111	/**
68ff39c3	112	* @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
c27e917e PZ	113	*/
	114	DPLL_ID_ICL_DPLL0 = 0,
	115	/**
68ff39c3	116	* @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
c27e917e PZ	117	*/
c27e917e PZ	118	DPLL_ID_ICL_DPLL1 = 1,
eef037ea VK	119	/**
	120	* @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
	121	*/
	122	DPLL_ID_EHL_DPLL4 = 2,
1fa11ee2	123	/**
68ff39c3	124	* @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
1fa11ee2 PZ	125	*/
1fa11ee2 PZ	126	DPLL_ID_ICL_TBTPLL = 2,
c27e917e	127	/**
68ff39c3 VK	128	* @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
68ff39c3 VK	129	* TGL TC PLL 1 port 1 (TC1)
c27e917e	130	*/
1fa11ee2	131	DPLL_ID_ICL_MGPLL1 = 3,
c27e917e PZ	132	/**
c27e917e PZ	133	* @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
68ff39c3	134	* TGL TC PLL 1 port 2 (TC2)
c27e917e	135	*/
1fa11ee2	136	DPLL_ID_ICL_MGPLL2 = 4,
c27e917e PZ	137	/**
c27e917e PZ	138	* @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
68ff39c3	139	* TGL TC PLL 1 port 3 (TC3)
c27e917e	140	*/
1fa11ee2	141	DPLL_ID_ICL_MGPLL3 = 5,
c27e917e PZ	142	/**
c27e917e PZ	143	* @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
68ff39c3	144	* TGL TC PLL 1 port 4 (TC4)
c27e917e	145	*/
1fa11ee2	146	DPLL_ID_ICL_MGPLL4 = 6,
68ff39c3	147	/**
d328bd4f	148	* @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
68ff39c3 VK	149	*/
	150	DPLL_ID_TGL_MGPLL5 = 7,
	151	/**
d328bd4f	152	* @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
68ff39c3 VK	153	*/
68ff39c3 VK	154	DPLL_ID_TGL_MGPLL6 = 8,
049c651b AS	155
	156	/**
	157	* @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
	158	*/
	159	DPLL_ID_DG1_DPLL0 = 0,
	160	/**
	161	* @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
	162	*/
	163	DPLL_ID_DG1_DPLL1 = 1,
	164	/**
	165	* @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
	166	*/
	167	DPLL_ID_DG1_DPLL2 = 2,
	168	/**
	169	* @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
	170	*/
	171	DPLL_ID_DG1_DPLL3 = 3,
ac7f11c6	172	};
68ff39c3 VK	173
68ff39c3 VK	174	#define I915_NUM_PLLS 9
9d16da65	175
eea72c4c ID	176	enum icl_port_dpll_id {
	177	ICL_PORT_DPLL_DEFAULT,
	178	ICL_PORT_DPLL_MG_PHY,
	179
	180	ICL_PORT_DPLL_COUNT,
	181	};
	182
ac7f11c6 ACO	183	struct intel_dpll_hw_state {
ac7f11c6 ACO	184	/* i9xx, pch plls */
990290d1 JN	185	u32 dpll;
	186	u32 dpll_md;
	187	u32 fp0;
	188	u32 fp1;
ac7f11c6 ACO	189
ac7f11c6 ACO	190	/* hsw, bdw */
990290d1 JN	191	u32 wrpll;
990290d1 JN	192	u32 spll;
ac7f11c6 ACO	193
	194	/* skl */
	195	/*
	196	* DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
	197	* lower part of ctrl1 and they get shifted into position when writing
	198	* the register. This allows us to easily compare the state to share
	199	* the DPLL.
	200	*/
990290d1	201	u32 ctrl1;
ac7f11c6	202	/* HDMI only, 0 when used for DP */
990290d1	203	u32 cfgcr1, cfgcr2;
ac7f11c6	204
244dba4c	205	/* icl */
990290d1	206	u32 cfgcr0;
a927c927	207
b70ad01a JRS	208	/* tgl */
	209	u32 div0;
	210
ac7f11c6	211	/* bxt */
990290d1	212	u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
c27e917e PZ	213
	214	/*
	215	* ICL uses the following, already defined:
990290d1 JN	216	* u32 cfgcr0, cfgcr1;
	217	*/
	218	u32 mg_refclkin_ctl;
	219	u32 mg_clktop2_coreclkctl1;
	220	u32 mg_clktop2_hsclkctl;
	221	u32 mg_pll_div0;
	222	u32 mg_pll_div1;
	223	u32 mg_pll_lf;
	224	u32 mg_pll_frac_lock;
	225	u32 mg_pll_ssc;
	226	u32 mg_pll_bias;
	227	u32 mg_pll_tdc_coldst_bias;
	228	u32 mg_pll_bias_mask;
	229	u32 mg_pll_tdc_coldst_bias_mask;
ac7f11c6 ACO	230	};
ac7f11c6 ACO	231
294591cf ACO	232	/**
	233	* struct intel_shared_dpll_state - hold the DPLL atomic state
	234	*
	235	* This structure holds an atomic state for the DPLL, that can represent
	236	* either its current state (in struct &intel_shared_dpll) or a desired
	237	* future state which would be applied by an atomic mode set (stored in
	238	* a struct &intel_atomic_state).
	239	*
866955fa	240	* See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
294591cf	241	*/
2c42e535	242	struct intel_shared_dpll_state {
294591cf	243	/**
d0f1bfc6	244	* @pipe_mask: mask of pipes using this DPLL, active or not
294591cf	245	*/
d0f1bfc6	246	u8 pipe_mask;
294591cf ACO	247
	248	/**
	249	* @hw_state: hardware configuration for the DPLL stored in
	250	* struct &intel_dpll_hw_state.
	251	*/
ac7f11c6 ACO	252	struct intel_dpll_hw_state hw_state;
	253	};
	254
47aa1e73 LDM	255	/**
	256	* struct dpll_info - display PLL platform specific info
	257	*/
	258	struct dpll_info {
72f775fa LDM	259	/**
	260	* @name: DPLL name; used for logging
	261	*/
47aa1e73	262	const char *name;
7fd9e829	263
ee1398ba LDM	264	/**
	265	* @funcs: platform specific hooks
	266	*/
47aa1e73	267	const struct intel_shared_dpll_funcs *funcs;
7fd9e829 LDM	268
7fd9e829 LDM	269	/**
027c5701	270	* @id: unique indentifier for this DPLL
7fd9e829 LDM	271	*/
	272	enum intel_dpll_id id;
	273
7e72cd6c VS	274	/**
	275	* @power_domain: extra power domain required by the DPLL
	276	*/
	277	enum intel_display_power_domain power_domain;
	278
5cd281f6	279	/**
4073dbbc	280	* @always_on:
5cd281f6	281	*
4073dbbc VS	282	* Inform the state checker that the DPLL is kept enabled even if
	283	* not in use by any CRTC.
	284	*/
	285	bool always_on;
	286
	287	/**
	288	* @is_alt_port_dpll:
	289	*
	290	* Inform the state checker that the DPLL can be used as a fallback
	291	* (for TC->TBT fallback).
	292	*/
	293	bool is_alt_port_dpll;
47aa1e73 LDM	294	};
47aa1e73 LDM	295
294591cf ACO	296	/**
	297	* struct intel_shared_dpll - display PLL with tracked state and users
	298	*/
2edd6443	299	struct intel_shared_dpll {
294591cf ACO	300	/**
	301	* @state:
	302	*
cf20b411	303	* Store the state for the pll, including its hw state
294591cf ACO	304	* and CRTCs using it.
294591cf ACO	305	*/
2c42e535	306	struct intel_shared_dpll_state state;
2edd6443	307
027c5701 VS	308	/**
	309	* @index: index for atomic state
	310	*/
	311	u8 index;
	312
294591cf	313	/**
d0f1bfc6	314	* @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL
294591cf	315	*/
d0f1bfc6	316	u8 active_mask;
294591cf ACO	317
	318	/**
	319	* @on: is the PLL actually active? Disabled during modeset
	320	*/
	321	bool on;
	322
e3037963 LDM	323	/**
	324	* @info: platform specific info
	325	*/
	326	const struct dpll_info *info;
900554dc AK	327
	328	/**
	329	* @wakeref: In some platforms a device-level runtime pm reference may
	330	* need to be grabbed to disable DC states while this DPLL is enabled
	331	*/
eef037ea	332	intel_wakeref_t wakeref;
2edd6443 ACO	333	};
2edd6443 ACO	334
ac7f11c6 ACO	335	#define SKL_DPLL0 0
	336	#define SKL_DPLL1 1
	337	#define SKL_DPLL2 2
	338	#define SKL_DPLL3 3
	339
c2a9fcd6 ACO	340	/* shared dpll functions */
c2a9fcd6 ACO	341	struct intel_shared_dpll *
25591b66	342	intel_get_shared_dpll_by_id(struct drm_i915_private *i915,
c2a9fcd6	343	enum intel_dpll_id id);
25591b66	344	void assert_shared_dpll(struct drm_i915_private *i915,
c2a9fcd6 ACO	345	struct intel_shared_dpll *pll,
	346	bool state);
	347	#define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
	348	#define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
92a02074 VS	349	int intel_compute_shared_dplls(struct intel_atomic_state *state,
	350	struct intel_crtc *crtc,
	351	struct intel_encoder *encoder);
9274229a VS	352	int intel_reserve_shared_dplls(struct intel_atomic_state *state,
	353	struct intel_crtc *crtc,
	354	struct intel_encoder *encoder);
866955fa ID	355	void intel_release_shared_dplls(struct intel_atomic_state *state,
866955fa ID	356	struct intel_crtc *crtc);
7ff9a17e ID	357	void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
	358	const struct intel_shared_dpll *pll,
	359	struct intel_shared_dpll_state *shared_dpll_state);
eea72c4c ID	360	void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
eea72c4c ID	361	enum icl_port_dpll_id port_dpll_id);
24a7bfe0 ID	362	void intel_update_active_dpll(struct intel_atomic_state *state,
	363	struct intel_crtc *crtc,
	364	struct intel_encoder *encoder);
b953eb21	365	int intel_dpll_get_freq(struct drm_i915_private *i915,
3749de07 VS	366	const struct intel_shared_dpll *pll,
3749de07 VS	367	const struct intel_dpll_hw_state *pll_state);
fdbc5d68 VS	368	bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
	369	struct intel_shared_dpll *pll,
	370	struct intel_dpll_hw_state *hw_state);
65c307fd ML	371	void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
65c307fd ML	372	void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
13d723a1	373	void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
25591b66 VS	374	void intel_shared_dpll_init(struct drm_i915_private *i915);
	375	void intel_dpll_update_ref_clks(struct drm_i915_private *i915);
	376	void intel_dpll_readout_hw_state(struct drm_i915_private *i915);
	377	void intel_dpll_sanitize_state(struct drm_i915_private *i915);
c2a9fcd6	378
25591b66	379	void intel_dpll_dump_hw_state(struct drm_i915_private *i915,
926878fb	380	const struct intel_dpll_hw_state *hw_state);
7ab52cb3 VS	381	bool intel_dpll_compare_hw_state(struct drm_i915_private *i915,
	382	const struct intel_dpll_hw_state *a,
	383	const struct intel_dpll_hw_state *b);
584fca11	384	enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
a54270d3	385	bool intel_dpll_is_combophy(enum intel_dpll_id id);
f50b79f0	386
4d6e198a VS	387	void intel_shared_dpll_state_verify(struct intel_atomic_state *state,
	388	struct intel_crtc *crtc);
	389	void intel_shared_dpll_verify_disabled(struct intel_atomic_state *state);
f0978e92	390
ac7f11c6	391	#endif /* _INTEL_DPLL_MGR_H_ */