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ee5e5e7a SP |
1 | /* SPDX-License-Identifier: MIT */ |
2 | /* | |
3 | * Copyright (C) 2017 Google, Inc. | |
0dcceb35 | 4 | * Copyright _ 2017-2019, Intel Corporation. |
ee5e5e7a SP |
5 | * |
6 | * Authors: | |
7 | * Sean Paul <seanpaul@chromium.org> | |
0dcceb35 | 8 | * Ramalingam C <ramalingam.c@intel.com> |
ee5e5e7a SP |
9 | */ |
10 | ||
408bd917 | 11 | #include <linux/component.h> |
ee5e5e7a SP |
12 | #include <linux/i2c.h> |
13 | #include <linux/random.h> | |
14 | ||
6a99099f | 15 | #include <drm/display/drm_hdcp_helper.h> |
408bd917 JN |
16 | #include <drm/i915_component.h> |
17 | ||
a6c6eac9 | 18 | #include "i915_drv.h" |
ee5e5e7a | 19 | #include "i915_reg.h" |
4dd4375b | 20 | #include "intel_connector.h" |
7785ae0b | 21 | #include "intel_de.h" |
4dd4375b | 22 | #include "intel_display_power.h" |
47f16fe5 | 23 | #include "intel_display_power_well.h" |
1d455f8d | 24 | #include "intel_display_types.h" |
408bd917 | 25 | #include "intel_hdcp.h" |
88363177 | 26 | #include "intel_hdcp_gsc.h" |
9e6a82b9 | 27 | #include "intel_hdcp_regs.h" |
4dd4375b | 28 | #include "intel_pcode.h" |
ee5e5e7a SP |
29 | |
30 | #define KEY_LOAD_TRIES 5 | |
bd90d7c7 | 31 | #define HDCP2_LC_RETRY_CNT 3 |
ee5e5e7a | 32 | |
66bd6924 | 33 | static int intel_conn_to_vcpi(struct intel_atomic_state *state, |
a6d82f1b | 34 | struct intel_connector *connector) |
e03187e1 | 35 | { |
4d07b0bc LP |
36 | struct drm_dp_mst_topology_mgr *mgr; |
37 | struct drm_dp_mst_atomic_payload *payload; | |
38 | struct drm_dp_mst_topology_state *mst_state; | |
39 | int vcpi = 0; | |
40 | ||
e03187e1 | 41 | /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */ |
4d07b0bc LP |
42 | if (!connector->port) |
43 | return 0; | |
44 | mgr = connector->port->mgr; | |
45 | ||
66bd6924 | 46 | drm_modeset_lock(&mgr->base.lock, state->base.acquire_ctx); |
4d07b0bc LP |
47 | mst_state = to_drm_dp_mst_topology_state(mgr->base.state); |
48 | payload = drm_atomic_get_mst_payload_state(mst_state, connector->port); | |
49 | if (drm_WARN_ON(mgr->dev, !payload)) | |
50 | goto out; | |
51 | ||
52 | vcpi = payload->vcpi; | |
53 | if (drm_WARN_ON(mgr->dev, vcpi < 0)) { | |
54 | vcpi = 0; | |
55 | goto out; | |
56 | } | |
57 | out: | |
4d07b0bc | 58 | return vcpi; |
e03187e1 AG |
59 | } |
60 | ||
61 | /* | |
62 | * intel_hdcp_required_content_stream selects the most highest common possible HDCP | |
63 | * content_type for all streams in DP MST topology because security f/w doesn't | |
64 | * have any provision to mark content_type for each stream separately, it marks | |
65 | * all available streams with the content_type proivided at the time of port | |
66 | * authentication. This may prohibit the userspace to use type1 content on | |
67 | * HDCP 2.2 capable sink because of other sink are not capable of HDCP 2.2 in | |
68 | * DP MST topology. Though it is not compulsory, security fw should change its | |
69 | * policy to mark different content_types for different streams. | |
70 | */ | |
66bd6924 SK |
71 | static int |
72 | intel_hdcp_required_content_stream(struct intel_atomic_state *state, | |
73 | struct intel_digital_port *dig_port) | |
e03187e1 | 74 | { |
66bd6924 SK |
75 | struct drm_connector_list_iter conn_iter; |
76 | struct intel_digital_port *conn_dig_port; | |
77 | struct intel_connector *connector; | |
78 | struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); | |
e03187e1 AG |
79 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; |
80 | bool enforce_type0 = false; | |
81 | int k; | |
82 | ||
83 | if (dig_port->hdcp_auth_status) | |
66bd6924 SK |
84 | return 0; |
85 | ||
86 | data->k = 0; | |
e03187e1 | 87 | |
415beb1f SK |
88 | if (!dig_port->hdcp_mst_type1_capable) |
89 | enforce_type0 = true; | |
90 | ||
66bd6924 SK |
91 | drm_connector_list_iter_begin(&i915->drm, &conn_iter); |
92 | for_each_intel_connector_iter(connector, &conn_iter) { | |
93 | if (connector->base.status == connector_status_disconnected) | |
94 | continue; | |
95 | ||
96 | if (!intel_encoder_is_mst(intel_attached_encoder(connector))) | |
97 | continue; | |
98 | ||
99 | conn_dig_port = intel_attached_dig_port(connector); | |
100 | if (conn_dig_port != dig_port) | |
101 | continue; | |
102 | ||
103 | data->streams[data->k].stream_id = | |
104 | intel_conn_to_vcpi(state, connector); | |
105 | data->k++; | |
106 | ||
107 | /* if there is only one active stream */ | |
108 | if (dig_port->dp.active_mst_links <= 1) | |
109 | break; | |
110 | } | |
111 | drm_connector_list_iter_end(&conn_iter); | |
112 | ||
113 | if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915) || data->k == 0)) | |
114 | return -EINVAL; | |
115 | ||
e03187e1 AG |
116 | /* |
117 | * Apply common protection level across all streams in DP MST Topology. | |
118 | * Use highest supported content type for all streams in DP MST Topology. | |
119 | */ | |
120 | for (k = 0; k < data->k; k++) | |
121 | data->streams[k].stream_type = | |
122 | enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE0 : DRM_MODE_HDCP_CONTENT_TYPE1; | |
66bd6924 SK |
123 | |
124 | return 0; | |
e03187e1 AG |
125 | } |
126 | ||
66bd6924 SK |
127 | static int intel_hdcp_prepare_streams(struct intel_atomic_state *state, |
128 | struct intel_connector *connector) | |
3e31d057 JL |
129 | { |
130 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); | |
131 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; | |
132 | struct intel_hdcp *hdcp = &connector->hdcp; | |
3e31d057 | 133 | |
66bd6924 SK |
134 | if (intel_encoder_is_mst(intel_attached_encoder(connector))) |
135 | return intel_hdcp_required_content_stream(state, dig_port); | |
136 | ||
137 | data->k = 1; | |
138 | data->streams[0].stream_id = 0; | |
139 | data->streams[0].stream_type = hdcp->content_type; | |
140 | ||
141 | return 0; | |
3e31d057 JL |
142 | } |
143 | ||
f106d100 R |
144 | static |
145 | bool intel_hdcp_is_ksv_valid(u8 *ksv) | |
146 | { | |
147 | int i, ones = 0; | |
148 | /* KSV has 20 1's and 20 0's */ | |
149 | for (i = 0; i < DRM_HDCP_KSV_LEN; i++) | |
150 | ones += hweight8(ksv[i]); | |
151 | if (ones != 20) | |
152 | return false; | |
153 | ||
154 | return true; | |
155 | } | |
156 | ||
157 | static | |
7801f3b7 | 158 | int intel_hdcp_read_valid_bksv(struct intel_digital_port *dig_port, |
f106d100 R |
159 | const struct intel_hdcp_shim *shim, u8 *bksv) |
160 | { | |
7801f3b7 | 161 | struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); |
f106d100 R |
162 | int ret, i, tries = 2; |
163 | ||
164 | /* HDCP spec states that we must retry the bksv if it is invalid */ | |
165 | for (i = 0; i < tries; i++) { | |
7801f3b7 | 166 | ret = shim->read_bksv(dig_port, bksv); |
f106d100 R |
167 | if (ret) |
168 | return ret; | |
169 | if (intel_hdcp_is_ksv_valid(bksv)) | |
170 | break; | |
171 | } | |
172 | if (i == tries) { | |
51279100 | 173 | drm_dbg_kms(&i915->drm, "Bksv is invalid\n"); |
f106d100 R |
174 | return -ENODEV; |
175 | } | |
176 | ||
177 | return 0; | |
178 | } | |
179 | ||
bdc93fe0 | 180 | /* Is HDCP1.4 capable on Platform and Sink */ |
8e754d9e | 181 | bool intel_hdcp_get_capability(struct intel_connector *connector) |
bdc93fe0 | 182 | { |
7801f3b7 | 183 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
d3dacc70 | 184 | const struct intel_hdcp_shim *shim = connector->hdcp.shim; |
bdc93fe0 R |
185 | bool capable = false; |
186 | u8 bksv[5]; | |
187 | ||
188 | if (!shim) | |
189 | return capable; | |
190 | ||
8e754d9e SK |
191 | if (shim->hdcp_get_capability) { |
192 | shim->hdcp_get_capability(dig_port, &capable); | |
bdc93fe0 | 193 | } else { |
7801f3b7 | 194 | if (!intel_hdcp_read_valid_bksv(dig_port, shim, bksv)) |
bdc93fe0 R |
195 | capable = true; |
196 | } | |
197 | ||
198 | return capable; | |
199 | } | |
200 | ||
26f7d01c SK |
201 | /* |
202 | * Check if the source has all the building blocks ready to make | |
203 | * HDCP 2.2 work | |
204 | */ | |
205 | static bool intel_hdcp2_prerequisite(struct intel_connector *connector) | |
49a630b0 | 206 | { |
401e6cd9 | 207 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
49a630b0 | 208 | struct intel_hdcp *hdcp = &connector->hdcp; |
49a630b0 R |
209 | |
210 | /* I915 support for HDCP2.2 */ | |
211 | if (!hdcp->hdcp2_supported) | |
212 | return false; | |
213 | ||
88363177 | 214 | /* If MTL+ make sure gsc is loaded and proxy is setup */ |
401e6cd9 | 215 | if (intel_hdcp_gsc_cs_required(i915)) { |
99f106ad | 216 | if (!intel_hdcp_gsc_check_status(i915)) |
88363177 | 217 | return false; |
6986f05b | 218 | } |
88363177 SK |
219 | |
220 | /* MEI/GSC interface is solid depending on which is used */ | |
3e36c490 | 221 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
5c8ec987 | 222 | if (!i915->display.hdcp.comp_added || !i915->display.hdcp.arbiter) { |
3e36c490 | 223 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
c5568ed2 CW |
224 | return false; |
225 | } | |
3e36c490 | 226 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
49a630b0 | 227 | |
26f7d01c SK |
228 | return true; |
229 | } | |
230 | ||
231 | /* Is HDCP2.2 capable on Platform and Sink */ | |
8e754d9e | 232 | bool intel_hdcp2_get_capability(struct intel_connector *connector) |
26f7d01c SK |
233 | { |
234 | struct intel_hdcp *hdcp = &connector->hdcp; | |
235 | bool capable = false; | |
236 | ||
237 | if (!intel_hdcp2_prerequisite(connector)) | |
238 | return false; | |
239 | ||
49a630b0 | 240 | /* Sink's capability for HDCP2.2 */ |
8e754d9e | 241 | hdcp->shim->hdcp_2_2_get_capability(connector, &capable); |
49a630b0 R |
242 | |
243 | return capable; | |
244 | } | |
245 | ||
813cca96 SK |
246 | void intel_hdcp_get_remote_capability(struct intel_connector *connector, |
247 | bool *hdcp_capable, | |
248 | bool *hdcp2_capable) | |
249 | { | |
250 | struct intel_hdcp *hdcp = &connector->hdcp; | |
251 | ||
252 | if (!hdcp->shim->get_remote_hdcp_capability) | |
253 | return; | |
254 | ||
255 | hdcp->shim->get_remote_hdcp_capability(connector, hdcp_capable, | |
256 | hdcp2_capable); | |
257 | ||
258 | if (!intel_hdcp2_prerequisite(connector)) | |
259 | *hdcp2_capable = false; | |
260 | } | |
261 | ||
401e6cd9 | 262 | static bool intel_hdcp_in_use(struct drm_i915_private *i915, |
81b55ef1 | 263 | enum transcoder cpu_transcoder, enum port port) |
09d56393 | 264 | { |
401e6cd9 SK |
265 | return intel_de_read(i915, |
266 | HDCP_STATUS(i915, cpu_transcoder, port)) & | |
267 | HDCP_STATUS_ENC; | |
09d56393 R |
268 | } |
269 | ||
401e6cd9 | 270 | static bool intel_hdcp2_in_use(struct drm_i915_private *i915, |
81b55ef1 | 271 | enum transcoder cpu_transcoder, enum port port) |
22ce2d94 | 272 | { |
401e6cd9 SK |
273 | return intel_de_read(i915, |
274 | HDCP2_STATUS(i915, cpu_transcoder, port)) & | |
275 | LINK_ENCRYPTION_STATUS; | |
22ce2d94 R |
276 | } |
277 | ||
7801f3b7 | 278 | static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *dig_port, |
ee5e5e7a SP |
279 | const struct intel_hdcp_shim *shim) |
280 | { | |
281 | int ret, read_ret; | |
282 | bool ksv_ready; | |
283 | ||
284 | /* Poll for ksv list ready (spec says max time allowed is 5s) */ | |
7801f3b7 | 285 | ret = __wait_for(read_ret = shim->read_ksv_ready(dig_port, |
ee5e5e7a SP |
286 | &ksv_ready), |
287 | read_ret || ksv_ready, 5 * 1000 * 1000, 1000, | |
288 | 100 * 1000); | |
289 | if (ret) | |
290 | return ret; | |
291 | if (read_ret) | |
292 | return read_ret; | |
293 | if (!ksv_ready) | |
294 | return -ETIMEDOUT; | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
401e6cd9 | 299 | static bool hdcp_key_loadable(struct drm_i915_private *i915) |
6308a315 | 300 | { |
6308a315 | 301 | enum i915_power_well_id id; |
4fcee7be | 302 | intel_wakeref_t wakeref; |
6308a315 R |
303 | bool enabled = false; |
304 | ||
305 | /* | |
306 | * On HSW and BDW, Display HW loads the Key as soon as Display resumes. | |
307 | * On all BXT+, SW can load the keys only when the PW#1 is turned on. | |
308 | */ | |
401e6cd9 | 309 | if (IS_HASWELL(i915) || IS_BROADWELL(i915)) |
6308a315 R |
310 | id = HSW_DISP_PW_GLOBAL; |
311 | else | |
312 | id = SKL_DISP_PW_1; | |
313 | ||
6308a315 | 314 | /* PG1 (power well #1) needs to be enabled */ |
401e6cd9 SK |
315 | with_intel_runtime_pm(&i915->runtime_pm, wakeref) |
316 | enabled = intel_display_power_well_is_enabled(i915, id); | |
6308a315 R |
317 | |
318 | /* | |
319 | * Another req for hdcp key loadability is enabled state of pll for | |
320 | * cdclk. Without active crtc we wont land here. So we are assuming that | |
321 | * cdclk is already on. | |
322 | */ | |
323 | ||
324 | return enabled; | |
325 | } | |
326 | ||
401e6cd9 | 327 | static void intel_hdcp_clear_keys(struct drm_i915_private *i915) |
ee5e5e7a | 328 | { |
401e6cd9 SK |
329 | intel_de_write(i915, HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER); |
330 | intel_de_write(i915, HDCP_KEY_STATUS, | |
667944ad | 331 | HDCP_KEY_LOAD_DONE | HDCP_KEY_LOAD_STATUS | HDCP_FUSE_IN_PROGRESS | HDCP_FUSE_ERROR | HDCP_FUSE_DONE); |
ee5e5e7a SP |
332 | } |
333 | ||
401e6cd9 | 334 | static int intel_hdcp_load_keys(struct drm_i915_private *i915) |
ee5e5e7a SP |
335 | { |
336 | int ret; | |
337 | u32 val; | |
338 | ||
401e6cd9 | 339 | val = intel_de_read(i915, HDCP_KEY_STATUS); |
7ee57988 R |
340 | if ((val & HDCP_KEY_LOAD_DONE) && (val & HDCP_KEY_LOAD_STATUS)) |
341 | return 0; | |
342 | ||
fdddd08c R |
343 | /* |
344 | * On HSW and BDW HW loads the HDCP1.4 Key when Display comes | |
345 | * out of reset. So if Key is not already loaded, its an error state. | |
346 | */ | |
401e6cd9 SK |
347 | if (IS_HASWELL(i915) || IS_BROADWELL(i915)) |
348 | if (!(intel_de_read(i915, HDCP_KEY_STATUS) & HDCP_KEY_LOAD_DONE)) | |
fdddd08c R |
349 | return -ENXIO; |
350 | ||
351 | /* | |
352 | * Initiate loading the HDCP key from fuses. | |
353 | * | |
2446e1d6 MR |
354 | * BXT+ platforms, HDCP key needs to be loaded by SW. Only display |
355 | * version 9 platforms (minus BXT) differ in the key load trigger | |
356 | * process from other platforms. These platforms use the GT Driver | |
357 | * Mailbox interface. | |
fdddd08c | 358 | */ |
401e6cd9 SK |
359 | if (DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915)) { |
360 | ret = snb_pcode_write(&i915->uncore, SKL_PCODE_LOAD_HDCP_KEYS, 1); | |
fdddd08c | 361 | if (ret) { |
401e6cd9 | 362 | drm_err(&i915->drm, |
65833c46 WK |
363 | "Failed to initiate HDCP key load (%d)\n", |
364 | ret); | |
fdddd08c R |
365 | return ret; |
366 | } | |
367 | } else { | |
401e6cd9 | 368 | intel_de_write(i915, HDCP_KEY_CONF, HDCP_KEY_LOAD_TRIGGER); |
ee5e5e7a SP |
369 | } |
370 | ||
371 | /* Wait for the keys to load (500us) */ | |
401e6cd9 | 372 | ret = __intel_wait_for_register(&i915->uncore, HDCP_KEY_STATUS, |
ee5e5e7a SP |
373 | HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE, |
374 | 10, 1, &val); | |
375 | if (ret) | |
376 | return ret; | |
377 | else if (!(val & HDCP_KEY_LOAD_STATUS)) | |
378 | return -ENXIO; | |
379 | ||
380 | /* Send Aksv over to PCH display for use in authentication */ | |
401e6cd9 | 381 | intel_de_write(i915, HDCP_KEY_CONF, HDCP_AKSV_SEND_TRIGGER); |
ee5e5e7a SP |
382 | |
383 | return 0; | |
384 | } | |
385 | ||
386 | /* Returns updated SHA-1 index */ | |
401e6cd9 | 387 | static int intel_write_sha_text(struct drm_i915_private *i915, u32 sha_text) |
ee5e5e7a | 388 | { |
401e6cd9 SK |
389 | intel_de_write(i915, HDCP_SHA_TEXT, sha_text); |
390 | if (intel_de_wait_for_set(i915, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) { | |
391 | drm_err(&i915->drm, "Timed out waiting for SHA1 ready\n"); | |
ee5e5e7a SP |
392 | return -ETIMEDOUT; |
393 | } | |
394 | return 0; | |
395 | } | |
396 | ||
397 | static | |
401e6cd9 | 398 | u32 intel_hdcp_get_repeater_ctl(struct drm_i915_private *i915, |
69205931 | 399 | enum transcoder cpu_transcoder, enum port port) |
ee5e5e7a | 400 | { |
401e6cd9 | 401 | if (DISPLAY_VER(i915) >= 12) { |
69205931 R |
402 | switch (cpu_transcoder) { |
403 | case TRANSCODER_A: | |
404 | return HDCP_TRANSA_REP_PRESENT | | |
405 | HDCP_TRANSA_SHA1_M0; | |
406 | case TRANSCODER_B: | |
407 | return HDCP_TRANSB_REP_PRESENT | | |
408 | HDCP_TRANSB_SHA1_M0; | |
409 | case TRANSCODER_C: | |
410 | return HDCP_TRANSC_REP_PRESENT | | |
411 | HDCP_TRANSC_SHA1_M0; | |
412 | case TRANSCODER_D: | |
413 | return HDCP_TRANSD_REP_PRESENT | | |
414 | HDCP_TRANSD_SHA1_M0; | |
415 | default: | |
401e6cd9 | 416 | drm_err(&i915->drm, "Unknown transcoder %d\n", |
65833c46 | 417 | cpu_transcoder); |
547a720e | 418 | return 0; |
69205931 R |
419 | } |
420 | } | |
421 | ||
ee5e5e7a SP |
422 | switch (port) { |
423 | case PORT_A: | |
424 | return HDCP_DDIA_REP_PRESENT | HDCP_DDIA_SHA1_M0; | |
425 | case PORT_B: | |
426 | return HDCP_DDIB_REP_PRESENT | HDCP_DDIB_SHA1_M0; | |
427 | case PORT_C: | |
428 | return HDCP_DDIC_REP_PRESENT | HDCP_DDIC_SHA1_M0; | |
429 | case PORT_D: | |
430 | return HDCP_DDID_REP_PRESENT | HDCP_DDID_SHA1_M0; | |
431 | case PORT_E: | |
432 | return HDCP_DDIE_REP_PRESENT | HDCP_DDIE_SHA1_M0; | |
433 | default: | |
401e6cd9 | 434 | drm_err(&i915->drm, "Unknown port %d\n", port); |
547a720e | 435 | return 0; |
ee5e5e7a | 436 | } |
ee5e5e7a SP |
437 | } |
438 | ||
ee5e5e7a | 439 | static |
69205931 | 440 | int intel_hdcp_validate_v_prime(struct intel_connector *connector, |
41baafae R |
441 | const struct intel_hdcp_shim *shim, |
442 | u8 *ksv_fifo, u8 num_downstream, u8 *bstatus) | |
ee5e5e7a | 443 | { |
7801f3b7 | 444 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
401e6cd9 | 445 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
69205931 | 446 | enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; |
7801f3b7 | 447 | enum port port = dig_port->base.port; |
ee5e5e7a | 448 | u32 vprime, sha_text, sha_leftovers, rep_ctl; |
ee5e5e7a SP |
449 | int ret, i, j, sha_idx; |
450 | ||
ee5e5e7a SP |
451 | /* Process V' values from the receiver */ |
452 | for (i = 0; i < DRM_HDCP_V_PRIME_NUM_PARTS; i++) { | |
7801f3b7 | 453 | ret = shim->read_v_prime_part(dig_port, i, &vprime); |
ee5e5e7a SP |
454 | if (ret) |
455 | return ret; | |
401e6cd9 | 456 | intel_de_write(i915, HDCP_SHA_V_PRIME(i), vprime); |
ee5e5e7a SP |
457 | } |
458 | ||
459 | /* | |
460 | * We need to write the concatenation of all device KSVs, BINFO (DP) || | |
461 | * BSTATUS (HDMI), and M0 (which is added via HDCP_REP_CTL). This byte | |
462 | * stream is written via the HDCP_SHA_TEXT register in 32-bit | |
463 | * increments. Every 64 bytes, we need to write HDCP_REP_CTL again. This | |
464 | * index will keep track of our progress through the 64 bytes as well as | |
465 | * helping us work the 40-bit KSVs through our 32-bit register. | |
466 | * | |
467 | * NOTE: data passed via HDCP_SHA_TEXT should be big-endian | |
468 | */ | |
469 | sha_idx = 0; | |
470 | sha_text = 0; | |
471 | sha_leftovers = 0; | |
401e6cd9 SK |
472 | rep_ctl = intel_hdcp_get_repeater_ctl(i915, cpu_transcoder, port); |
473 | intel_de_write(i915, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); | |
ee5e5e7a SP |
474 | for (i = 0; i < num_downstream; i++) { |
475 | unsigned int sha_empty; | |
476 | u8 *ksv = &ksv_fifo[i * DRM_HDCP_KSV_LEN]; | |
477 | ||
478 | /* Fill up the empty slots in sha_text and write it out */ | |
479 | sha_empty = sizeof(sha_text) - sha_leftovers; | |
1f088221 SP |
480 | for (j = 0; j < sha_empty; j++) { |
481 | u8 off = ((sizeof(sha_text) - j - 1 - sha_leftovers) * 8); | |
482 | sha_text |= ksv[j] << off; | |
483 | } | |
ee5e5e7a | 484 | |
401e6cd9 | 485 | ret = intel_write_sha_text(i915, sha_text); |
ee5e5e7a SP |
486 | if (ret < 0) |
487 | return ret; | |
488 | ||
489 | /* Programming guide writes this every 64 bytes */ | |
490 | sha_idx += sizeof(sha_text); | |
491 | if (!(sha_idx % 64)) | |
401e6cd9 | 492 | intel_de_write(i915, HDCP_REP_CTL, |
667944ad | 493 | rep_ctl | HDCP_SHA1_TEXT_32); |
ee5e5e7a SP |
494 | |
495 | /* Store the leftover bytes from the ksv in sha_text */ | |
496 | sha_leftovers = DRM_HDCP_KSV_LEN - sha_empty; | |
497 | sha_text = 0; | |
498 | for (j = 0; j < sha_leftovers; j++) | |
499 | sha_text |= ksv[sha_empty + j] << | |
500 | ((sizeof(sha_text) - j - 1) * 8); | |
501 | ||
502 | /* | |
503 | * If we still have room in sha_text for more data, continue. | |
504 | * Otherwise, write it out immediately. | |
505 | */ | |
506 | if (sizeof(sha_text) > sha_leftovers) | |
507 | continue; | |
508 | ||
401e6cd9 | 509 | ret = intel_write_sha_text(i915, sha_text); |
ee5e5e7a SP |
510 | if (ret < 0) |
511 | return ret; | |
512 | sha_leftovers = 0; | |
513 | sha_text = 0; | |
514 | sha_idx += sizeof(sha_text); | |
515 | } | |
516 | ||
517 | /* | |
518 | * We need to write BINFO/BSTATUS, and M0 now. Depending on how many | |
519 | * bytes are leftover from the last ksv, we might be able to fit them | |
520 | * all in sha_text (first 2 cases), or we might need to split them up | |
521 | * into 2 writes (last 2 cases). | |
522 | */ | |
523 | if (sha_leftovers == 0) { | |
524 | /* Write 16 bits of text, 16 bits of M0 */ | |
401e6cd9 | 525 | intel_de_write(i915, HDCP_REP_CTL, |
667944ad | 526 | rep_ctl | HDCP_SHA1_TEXT_16); |
401e6cd9 | 527 | ret = intel_write_sha_text(i915, |
ee5e5e7a SP |
528 | bstatus[0] << 8 | bstatus[1]); |
529 | if (ret < 0) | |
530 | return ret; | |
531 | sha_idx += sizeof(sha_text); | |
532 | ||
533 | /* Write 32 bits of M0 */ | |
401e6cd9 | 534 | intel_de_write(i915, HDCP_REP_CTL, |
667944ad | 535 | rep_ctl | HDCP_SHA1_TEXT_0); |
401e6cd9 | 536 | ret = intel_write_sha_text(i915, 0); |
ee5e5e7a SP |
537 | if (ret < 0) |
538 | return ret; | |
539 | sha_idx += sizeof(sha_text); | |
540 | ||
541 | /* Write 16 bits of M0 */ | |
401e6cd9 | 542 | intel_de_write(i915, HDCP_REP_CTL, |
667944ad | 543 | rep_ctl | HDCP_SHA1_TEXT_16); |
401e6cd9 | 544 | ret = intel_write_sha_text(i915, 0); |
ee5e5e7a SP |
545 | if (ret < 0) |
546 | return ret; | |
547 | sha_idx += sizeof(sha_text); | |
548 | ||
549 | } else if (sha_leftovers == 1) { | |
550 | /* Write 24 bits of text, 8 bits of M0 */ | |
401e6cd9 | 551 | intel_de_write(i915, HDCP_REP_CTL, |
667944ad | 552 | rep_ctl | HDCP_SHA1_TEXT_24); |
ee5e5e7a SP |
553 | sha_text |= bstatus[0] << 16 | bstatus[1] << 8; |
554 | /* Only 24-bits of data, must be in the LSB */ | |
555 | sha_text = (sha_text & 0xffffff00) >> 8; | |
401e6cd9 | 556 | ret = intel_write_sha_text(i915, sha_text); |
ee5e5e7a SP |
557 | if (ret < 0) |
558 | return ret; | |
559 | sha_idx += sizeof(sha_text); | |
560 | ||
561 | /* Write 32 bits of M0 */ | |
401e6cd9 | 562 | intel_de_write(i915, HDCP_REP_CTL, |
667944ad | 563 | rep_ctl | HDCP_SHA1_TEXT_0); |
401e6cd9 | 564 | ret = intel_write_sha_text(i915, 0); |
ee5e5e7a SP |
565 | if (ret < 0) |
566 | return ret; | |
567 | sha_idx += sizeof(sha_text); | |
568 | ||
569 | /* Write 24 bits of M0 */ | |
401e6cd9 | 570 | intel_de_write(i915, HDCP_REP_CTL, |
667944ad | 571 | rep_ctl | HDCP_SHA1_TEXT_8); |
401e6cd9 | 572 | ret = intel_write_sha_text(i915, 0); |
ee5e5e7a SP |
573 | if (ret < 0) |
574 | return ret; | |
575 | sha_idx += sizeof(sha_text); | |
576 | ||
577 | } else if (sha_leftovers == 2) { | |
578 | /* Write 32 bits of text */ | |
401e6cd9 | 579 | intel_de_write(i915, HDCP_REP_CTL, |
667944ad | 580 | rep_ctl | HDCP_SHA1_TEXT_32); |
1f088221 | 581 | sha_text |= bstatus[0] << 8 | bstatus[1]; |
401e6cd9 | 582 | ret = intel_write_sha_text(i915, sha_text); |
ee5e5e7a SP |
583 | if (ret < 0) |
584 | return ret; | |
585 | sha_idx += sizeof(sha_text); | |
586 | ||
587 | /* Write 64 bits of M0 */ | |
401e6cd9 | 588 | intel_de_write(i915, HDCP_REP_CTL, |
667944ad | 589 | rep_ctl | HDCP_SHA1_TEXT_0); |
ee5e5e7a | 590 | for (i = 0; i < 2; i++) { |
401e6cd9 | 591 | ret = intel_write_sha_text(i915, 0); |
ee5e5e7a SP |
592 | if (ret < 0) |
593 | return ret; | |
594 | sha_idx += sizeof(sha_text); | |
595 | } | |
1f088221 SP |
596 | |
597 | /* | |
598 | * Terminate the SHA-1 stream by hand. For the other leftover | |
599 | * cases this is appended by the hardware. | |
600 | */ | |
401e6cd9 | 601 | intel_de_write(i915, HDCP_REP_CTL, |
1f088221 SP |
602 | rep_ctl | HDCP_SHA1_TEXT_32); |
603 | sha_text = DRM_HDCP_SHA1_TERMINATOR << 24; | |
401e6cd9 | 604 | ret = intel_write_sha_text(i915, sha_text); |
1f088221 SP |
605 | if (ret < 0) |
606 | return ret; | |
607 | sha_idx += sizeof(sha_text); | |
ee5e5e7a | 608 | } else if (sha_leftovers == 3) { |
1f088221 | 609 | /* Write 32 bits of text (filled from LSB) */ |
401e6cd9 | 610 | intel_de_write(i915, HDCP_REP_CTL, |
667944ad | 611 | rep_ctl | HDCP_SHA1_TEXT_32); |
1f088221 | 612 | sha_text |= bstatus[0]; |
401e6cd9 | 613 | ret = intel_write_sha_text(i915, sha_text); |
ee5e5e7a SP |
614 | if (ret < 0) |
615 | return ret; | |
616 | sha_idx += sizeof(sha_text); | |
617 | ||
1f088221 | 618 | /* Write 8 bits of text (filled from LSB), 24 bits of M0 */ |
401e6cd9 | 619 | intel_de_write(i915, HDCP_REP_CTL, |
667944ad | 620 | rep_ctl | HDCP_SHA1_TEXT_8); |
401e6cd9 | 621 | ret = intel_write_sha_text(i915, bstatus[1]); |
ee5e5e7a SP |
622 | if (ret < 0) |
623 | return ret; | |
624 | sha_idx += sizeof(sha_text); | |
625 | ||
626 | /* Write 32 bits of M0 */ | |
401e6cd9 | 627 | intel_de_write(i915, HDCP_REP_CTL, |
667944ad | 628 | rep_ctl | HDCP_SHA1_TEXT_0); |
401e6cd9 | 629 | ret = intel_write_sha_text(i915, 0); |
ee5e5e7a SP |
630 | if (ret < 0) |
631 | return ret; | |
632 | sha_idx += sizeof(sha_text); | |
633 | ||
634 | /* Write 8 bits of M0 */ | |
401e6cd9 | 635 | intel_de_write(i915, HDCP_REP_CTL, |
667944ad | 636 | rep_ctl | HDCP_SHA1_TEXT_24); |
401e6cd9 | 637 | ret = intel_write_sha_text(i915, 0); |
ee5e5e7a SP |
638 | if (ret < 0) |
639 | return ret; | |
640 | sha_idx += sizeof(sha_text); | |
641 | } else { | |
401e6cd9 | 642 | drm_dbg_kms(&i915->drm, "Invalid number of leftovers %d\n", |
51279100 | 643 | sha_leftovers); |
ee5e5e7a SP |
644 | return -EINVAL; |
645 | } | |
646 | ||
401e6cd9 | 647 | intel_de_write(i915, HDCP_REP_CTL, rep_ctl | HDCP_SHA1_TEXT_32); |
ee5e5e7a SP |
648 | /* Fill up to 64-4 bytes with zeros (leave the last write for length) */ |
649 | while ((sha_idx % 64) < (64 - sizeof(sha_text))) { | |
401e6cd9 | 650 | ret = intel_write_sha_text(i915, 0); |
ee5e5e7a SP |
651 | if (ret < 0) |
652 | return ret; | |
653 | sha_idx += sizeof(sha_text); | |
654 | } | |
655 | ||
656 | /* | |
657 | * Last write gets the length of the concatenation in bits. That is: | |
658 | * - 5 bytes per device | |
659 | * - 10 bytes for BINFO/BSTATUS(2), M0(8) | |
660 | */ | |
661 | sha_text = (num_downstream * 5 + 10) * 8; | |
401e6cd9 | 662 | ret = intel_write_sha_text(i915, sha_text); |
ee5e5e7a SP |
663 | if (ret < 0) |
664 | return ret; | |
665 | ||
666 | /* Tell the HW we're done with the hash and wait for it to ACK */ | |
401e6cd9 | 667 | intel_de_write(i915, HDCP_REP_CTL, |
667944ad | 668 | rep_ctl | HDCP_SHA1_COMPLETE_HASH); |
401e6cd9 | 669 | if (intel_de_wait_for_set(i915, HDCP_REP_CTL, |
4cb3b44d | 670 | HDCP_SHA1_COMPLETE, 1)) { |
401e6cd9 | 671 | drm_err(&i915->drm, "Timed out waiting for SHA1 complete\n"); |
ee5e5e7a SP |
672 | return -ETIMEDOUT; |
673 | } | |
401e6cd9 SK |
674 | if (!(intel_de_read(i915, HDCP_REP_CTL) & HDCP_SHA1_V_MATCH)) { |
675 | drm_dbg_kms(&i915->drm, "SHA-1 mismatch, HDCP failed\n"); | |
ee5e5e7a SP |
676 | return -ENXIO; |
677 | } | |
678 | ||
41baafae R |
679 | return 0; |
680 | } | |
681 | ||
682 | /* Implements Part 2 of the HDCP authorization procedure */ | |
683 | static | |
f26ae6a6 | 684 | int intel_hdcp_auth_downstream(struct intel_connector *connector) |
41baafae | 685 | { |
7801f3b7 | 686 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
401e6cd9 | 687 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
f26ae6a6 | 688 | const struct intel_hdcp_shim *shim = connector->hdcp.shim; |
41baafae R |
689 | u8 bstatus[2], num_downstream, *ksv_fifo; |
690 | int ret, i, tries = 3; | |
691 | ||
7801f3b7 | 692 | ret = intel_hdcp_poll_ksv_fifo(dig_port, shim); |
41baafae | 693 | if (ret) { |
401e6cd9 | 694 | drm_dbg_kms(&i915->drm, |
51279100 | 695 | "KSV list failed to become ready (%d)\n", ret); |
41baafae R |
696 | return ret; |
697 | } | |
698 | ||
7801f3b7 | 699 | ret = shim->read_bstatus(dig_port, bstatus); |
41baafae R |
700 | if (ret) |
701 | return ret; | |
702 | ||
703 | if (DRM_HDCP_MAX_DEVICE_EXCEEDED(bstatus[0]) || | |
704 | DRM_HDCP_MAX_CASCADE_EXCEEDED(bstatus[1])) { | |
401e6cd9 | 705 | drm_dbg_kms(&i915->drm, "Max Topology Limit Exceeded\n"); |
41baafae R |
706 | return -EPERM; |
707 | } | |
708 | ||
709 | /* | |
710 | * When repeater reports 0 device count, HDCP1.4 spec allows disabling | |
711 | * the HDCP encryption. That implies that repeater can't have its own | |
712 | * display. As there is no consumption of encrypted content in the | |
713 | * repeater with 0 downstream devices, we are failing the | |
714 | * authentication. | |
715 | */ | |
716 | num_downstream = DRM_HDCP_NUM_DOWNSTREAM(bstatus[0]); | |
4fb76782 | 717 | if (num_downstream == 0) { |
401e6cd9 | 718 | drm_dbg_kms(&i915->drm, |
51279100 | 719 | "Repeater with zero downstream devices\n"); |
41baafae | 720 | return -EINVAL; |
4fb76782 | 721 | } |
41baafae | 722 | |
6396bb22 | 723 | ksv_fifo = kcalloc(DRM_HDCP_KSV_LEN, num_downstream, GFP_KERNEL); |
4fb76782 | 724 | if (!ksv_fifo) { |
401e6cd9 | 725 | drm_dbg_kms(&i915->drm, "Out of mem: ksv_fifo\n"); |
41baafae | 726 | return -ENOMEM; |
4fb76782 | 727 | } |
41baafae | 728 | |
7801f3b7 | 729 | ret = shim->read_ksv_fifo(dig_port, num_downstream, ksv_fifo); |
41baafae | 730 | if (ret) |
46a67c4d | 731 | goto err; |
41baafae | 732 | |
401e6cd9 | 733 | if (drm_hdcp_check_ksvs_revoked(&i915->drm, ksv_fifo, |
018532e9 | 734 | num_downstream) > 0) { |
401e6cd9 | 735 | drm_err(&i915->drm, "Revoked Ksv(s) in ksv_fifo\n"); |
de70fdd7 WY |
736 | ret = -EPERM; |
737 | goto err; | |
f26ae6a6 R |
738 | } |
739 | ||
41baafae R |
740 | /* |
741 | * When V prime mismatches, DP Spec mandates re-read of | |
742 | * V prime atleast twice. | |
743 | */ | |
744 | for (i = 0; i < tries; i++) { | |
69205931 | 745 | ret = intel_hdcp_validate_v_prime(connector, shim, |
41baafae R |
746 | ksv_fifo, num_downstream, |
747 | bstatus); | |
748 | if (!ret) | |
749 | break; | |
750 | } | |
751 | ||
752 | if (i == tries) { | |
401e6cd9 | 753 | drm_dbg_kms(&i915->drm, |
51279100 | 754 | "V Prime validation failed.(%d)\n", ret); |
46a67c4d | 755 | goto err; |
41baafae R |
756 | } |
757 | ||
401e6cd9 | 758 | drm_dbg_kms(&i915->drm, "HDCP is enabled (%d downstream devices)\n", |
51279100 | 759 | num_downstream); |
46a67c4d RS |
760 | ret = 0; |
761 | err: | |
762 | kfree(ksv_fifo); | |
763 | return ret; | |
ee5e5e7a SP |
764 | } |
765 | ||
766 | /* Implements Part 1 of the HDCP authorization procedure */ | |
f26ae6a6 | 767 | static int intel_hdcp_auth(struct intel_connector *connector) |
ee5e5e7a | 768 | { |
7801f3b7 | 769 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
401e6cd9 | 770 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
f26ae6a6 | 771 | struct intel_hdcp *hdcp = &connector->hdcp; |
f26ae6a6 | 772 | const struct intel_hdcp_shim *shim = hdcp->shim; |
69205931 | 773 | enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; |
7801f3b7 | 774 | enum port port = dig_port->base.port; |
ee5e5e7a | 775 | unsigned long r0_prime_gen_start; |
f622a71d | 776 | int ret, i, tries = 2; |
ee5e5e7a SP |
777 | union { |
778 | u32 reg[2]; | |
779 | u8 shim[DRM_HDCP_AN_LEN]; | |
780 | } an; | |
781 | union { | |
782 | u32 reg[2]; | |
783 | u8 shim[DRM_HDCP_KSV_LEN]; | |
784 | } bksv; | |
785 | union { | |
786 | u32 reg; | |
787 | u8 shim[DRM_HDCP_RI_LEN]; | |
788 | } ri; | |
791a98dd | 789 | bool repeater_present, hdcp_capable; |
ee5e5e7a | 790 | |
791a98dd R |
791 | /* |
792 | * Detects whether the display is HDCP capable. Although we check for | |
793 | * valid Bksv below, the HDCP over DP spec requires that we check | |
794 | * whether the display supports HDCP before we write An. For HDMI | |
795 | * displays, this is not necessary. | |
796 | */ | |
8e754d9e SK |
797 | if (shim->hdcp_get_capability) { |
798 | ret = shim->hdcp_get_capability(dig_port, &hdcp_capable); | |
791a98dd R |
799 | if (ret) |
800 | return ret; | |
801 | if (!hdcp_capable) { | |
401e6cd9 | 802 | drm_dbg_kms(&i915->drm, |
51279100 | 803 | "Panel is not HDCP capable\n"); |
791a98dd R |
804 | return -EINVAL; |
805 | } | |
806 | } | |
807 | ||
ee5e5e7a SP |
808 | /* Initialize An with 2 random values and acquire it */ |
809 | for (i = 0; i < 2; i++) | |
401e6cd9 SK |
810 | intel_de_write(i915, |
811 | HDCP_ANINIT(i915, cpu_transcoder, port), | |
667944ad | 812 | get_random_u32()); |
401e6cd9 | 813 | intel_de_write(i915, HDCP_CONF(i915, cpu_transcoder, port), |
667944ad | 814 | HDCP_CONF_CAPTURE_AN); |
ee5e5e7a SP |
815 | |
816 | /* Wait for An to be acquired */ | |
401e6cd9 SK |
817 | if (intel_de_wait_for_set(i915, |
818 | HDCP_STATUS(i915, cpu_transcoder, port), | |
4cb3b44d | 819 | HDCP_STATUS_AN_READY, 1)) { |
401e6cd9 | 820 | drm_err(&i915->drm, "Timed out waiting for An\n"); |
ee5e5e7a SP |
821 | return -ETIMEDOUT; |
822 | } | |
823 | ||
401e6cd9 SK |
824 | an.reg[0] = intel_de_read(i915, |
825 | HDCP_ANLO(i915, cpu_transcoder, port)); | |
826 | an.reg[1] = intel_de_read(i915, | |
827 | HDCP_ANHI(i915, cpu_transcoder, port)); | |
7801f3b7 | 828 | ret = shim->write_an_aksv(dig_port, an.shim); |
ee5e5e7a SP |
829 | if (ret) |
830 | return ret; | |
831 | ||
832 | r0_prime_gen_start = jiffies; | |
833 | ||
834 | memset(&bksv, 0, sizeof(bksv)); | |
f622a71d | 835 | |
7801f3b7 | 836 | ret = intel_hdcp_read_valid_bksv(dig_port, shim, bksv.shim); |
f106d100 R |
837 | if (ret < 0) |
838 | return ret; | |
ee5e5e7a | 839 | |
401e6cd9 SK |
840 | if (drm_hdcp_check_ksvs_revoked(&i915->drm, bksv.shim, 1) > 0) { |
841 | drm_err(&i915->drm, "BKSV is revoked\n"); | |
f26ae6a6 R |
842 | return -EPERM; |
843 | } | |
844 | ||
401e6cd9 | 845 | intel_de_write(i915, HDCP_BKSVLO(i915, cpu_transcoder, port), |
667944ad | 846 | bksv.reg[0]); |
401e6cd9 | 847 | intel_de_write(i915, HDCP_BKSVHI(i915, cpu_transcoder, port), |
667944ad | 848 | bksv.reg[1]); |
ee5e5e7a | 849 | |
7801f3b7 | 850 | ret = shim->repeater_present(dig_port, &repeater_present); |
ee5e5e7a SP |
851 | if (ret) |
852 | return ret; | |
853 | if (repeater_present) | |
401e6cd9 SK |
854 | intel_de_write(i915, HDCP_REP_CTL, |
855 | intel_hdcp_get_repeater_ctl(i915, cpu_transcoder, port)); | |
ee5e5e7a | 856 | |
0b9c9290 | 857 | ret = shim->toggle_signalling(dig_port, cpu_transcoder, true); |
ee5e5e7a SP |
858 | if (ret) |
859 | return ret; | |
860 | ||
401e6cd9 | 861 | intel_de_write(i915, HDCP_CONF(i915, cpu_transcoder, port), |
667944ad | 862 | HDCP_CONF_AUTH_AND_ENC); |
ee5e5e7a SP |
863 | |
864 | /* Wait for R0 ready */ | |
401e6cd9 | 865 | if (wait_for(intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & |
ee5e5e7a | 866 | (HDCP_STATUS_R0_READY | HDCP_STATUS_ENC), 1)) { |
401e6cd9 | 867 | drm_err(&i915->drm, "Timed out waiting for R0 ready\n"); |
ee5e5e7a SP |
868 | return -ETIMEDOUT; |
869 | } | |
870 | ||
871 | /* | |
872 | * Wait for R0' to become available. The spec says 100ms from Aksv, but | |
873 | * some monitors can take longer than this. We'll set the timeout at | |
874 | * 300ms just to be sure. | |
875 | * | |
876 | * On DP, there's an R0_READY bit available but no such bit | |
877 | * exists on HDMI. Since the upper-bound is the same, we'll just do | |
878 | * the stupid thing instead of polling on one and not the other. | |
879 | */ | |
880 | wait_remaining_ms_from_jiffies(r0_prime_gen_start, 300); | |
881 | ||
4bfbec68 | 882 | tries = 3; |
ee5e5e7a | 883 | |
4bfbec68 R |
884 | /* |
885 | * DP HDCP Spec mandates the two more reattempt to read R0, incase | |
886 | * of R0 mismatch. | |
887 | */ | |
888 | for (i = 0; i < tries; i++) { | |
889 | ri.reg = 0; | |
7801f3b7 | 890 | ret = shim->read_ri_prime(dig_port, ri.shim); |
4bfbec68 R |
891 | if (ret) |
892 | return ret; | |
401e6cd9 SK |
893 | intel_de_write(i915, |
894 | HDCP_RPRIME(i915, cpu_transcoder, port), | |
667944ad | 895 | ri.reg); |
4bfbec68 R |
896 | |
897 | /* Wait for Ri prime match */ | |
401e6cd9 | 898 | if (!wait_for(intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & |
667944ad | 899 | (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) |
4bfbec68 R |
900 | break; |
901 | } | |
902 | ||
903 | if (i == tries) { | |
401e6cd9 | 904 | drm_dbg_kms(&i915->drm, |
51279100 | 905 | "Timed out waiting for Ri prime match (%x)\n", |
401e6cd9 SK |
906 | intel_de_read(i915, |
907 | HDCP_STATUS(i915, cpu_transcoder, port))); | |
ee5e5e7a SP |
908 | return -ETIMEDOUT; |
909 | } | |
910 | ||
911 | /* Wait for encryption confirmation */ | |
401e6cd9 SK |
912 | if (intel_de_wait_for_set(i915, |
913 | HDCP_STATUS(i915, cpu_transcoder, port), | |
4cb3b44d | 914 | HDCP_STATUS_ENC, |
fbf652bd | 915 | HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { |
401e6cd9 | 916 | drm_err(&i915->drm, "Timed out waiting for encryption\n"); |
ee5e5e7a SP |
917 | return -ETIMEDOUT; |
918 | } | |
919 | ||
2a743b7b AG |
920 | /* DP MST Auth Part 1 Step 2.a and Step 2.b */ |
921 | if (shim->stream_encryption) { | |
922 | ret = shim->stream_encryption(connector, true); | |
923 | if (ret) { | |
4773293b JN |
924 | drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 1.4 stream enc\n", |
925 | connector->base.base.id, connector->base.name); | |
2a743b7b AG |
926 | return ret; |
927 | } | |
401e6cd9 | 928 | drm_dbg_kms(&i915->drm, "HDCP 1.4 transcoder: %s stream encrypted\n", |
2a743b7b AG |
929 | transcoder_name(hdcp->stream_transcoder)); |
930 | } | |
ee5e5e7a | 931 | |
87eb3ec8 | 932 | if (repeater_present) |
f26ae6a6 | 933 | return intel_hdcp_auth_downstream(connector); |
87eb3ec8 | 934 | |
401e6cd9 | 935 | drm_dbg_kms(&i915->drm, "HDCP is enabled (no repeater present)\n"); |
87eb3ec8 | 936 | return 0; |
ee5e5e7a SP |
937 | } |
938 | ||
ee5e5e7a SP |
939 | static int _intel_hdcp_disable(struct intel_connector *connector) |
940 | { | |
7801f3b7 | 941 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
401e6cd9 | 942 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
486bba45 | 943 | struct intel_hdcp *hdcp = &connector->hdcp; |
7801f3b7 | 944 | enum port port = dig_port->base.port; |
69205931 | 945 | enum transcoder cpu_transcoder = hdcp->cpu_transcoder; |
2cc0c7b5 | 946 | u32 repeater_ctl; |
ee5e5e7a SP |
947 | int ret; |
948 | ||
4773293b JN |
949 | drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] HDCP is being disabled...\n", |
950 | connector->base.base.id, connector->base.name); | |
cb340bf3 | 951 | |
2a743b7b AG |
952 | if (hdcp->shim->stream_encryption) { |
953 | ret = hdcp->shim->stream_encryption(connector, false); | |
954 | if (ret) { | |
4773293b JN |
955 | drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 1.4 stream enc\n", |
956 | connector->base.base.id, connector->base.name); | |
2a743b7b AG |
957 | return ret; |
958 | } | |
401e6cd9 | 959 | drm_dbg_kms(&i915->drm, "HDCP 1.4 transcoder: %s stream encryption disabled\n", |
2a743b7b | 960 | transcoder_name(hdcp->stream_transcoder)); |
40a6cead AG |
961 | /* |
962 | * If there are other connectors on this port using HDCP, | |
963 | * don't disable it until it disabled HDCP encryption for | |
964 | * all connectors in MST topology. | |
965 | */ | |
966 | if (dig_port->num_hdcp_streams > 0) | |
967 | return 0; | |
2a743b7b AG |
968 | } |
969 | ||
09d56393 | 970 | hdcp->hdcp_encrypted = false; |
401e6cd9 SK |
971 | intel_de_write(i915, HDCP_CONF(i915, cpu_transcoder, port), 0); |
972 | if (intel_de_wait_for_clear(i915, | |
973 | HDCP_STATUS(i915, cpu_transcoder, port), | |
fbf652bd | 974 | ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { |
401e6cd9 | 975 | drm_err(&i915->drm, |
65833c46 | 976 | "Failed to disable HDCP, timeout clearing status\n"); |
ee5e5e7a SP |
977 | return -ETIMEDOUT; |
978 | } | |
979 | ||
401e6cd9 | 980 | repeater_ctl = intel_hdcp_get_repeater_ctl(i915, cpu_transcoder, |
2cc0c7b5 | 981 | port); |
401e6cd9 | 982 | intel_de_rmw(i915, HDCP_REP_CTL, repeater_ctl, 0); |
2cc0c7b5 | 983 | |
0b9c9290 | 984 | ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, false); |
ee5e5e7a | 985 | if (ret) { |
401e6cd9 | 986 | drm_err(&i915->drm, "Failed to disable HDCP signalling\n"); |
ee5e5e7a SP |
987 | return ret; |
988 | } | |
989 | ||
401e6cd9 | 990 | drm_dbg_kms(&i915->drm, "HDCP is disabled\n"); |
ee5e5e7a SP |
991 | return 0; |
992 | } | |
993 | ||
da36ce00 | 994 | static int intel_hdcp1_enable(struct intel_connector *connector) |
ee5e5e7a | 995 | { |
401e6cd9 | 996 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
d3dacc70 | 997 | struct intel_hdcp *hdcp = &connector->hdcp; |
6d983946 | 998 | int i, ret, tries = 3; |
ee5e5e7a | 999 | |
4773293b JN |
1000 | drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] HDCP is being enabled...\n", |
1001 | connector->base.base.id, connector->base.name); | |
cb340bf3 | 1002 | |
401e6cd9 SK |
1003 | if (!hdcp_key_loadable(i915)) { |
1004 | drm_err(&i915->drm, "HDCP key Load is not possible\n"); | |
ee5e5e7a SP |
1005 | return -ENXIO; |
1006 | } | |
1007 | ||
1008 | for (i = 0; i < KEY_LOAD_TRIES; i++) { | |
401e6cd9 | 1009 | ret = intel_hdcp_load_keys(i915); |
ee5e5e7a SP |
1010 | if (!ret) |
1011 | break; | |
401e6cd9 | 1012 | intel_hdcp_clear_keys(i915); |
ee5e5e7a SP |
1013 | } |
1014 | if (ret) { | |
401e6cd9 | 1015 | drm_err(&i915->drm, "Could not load HDCP keys, (%d)\n", |
65833c46 | 1016 | ret); |
ee5e5e7a SP |
1017 | return ret; |
1018 | } | |
1019 | ||
6d983946 R |
1020 | /* Incase of authentication failures, HDCP spec expects reauth. */ |
1021 | for (i = 0; i < tries; i++) { | |
f26ae6a6 | 1022 | ret = intel_hdcp_auth(connector); |
09d56393 R |
1023 | if (!ret) { |
1024 | hdcp->hdcp_encrypted = true; | |
6d983946 | 1025 | return 0; |
09d56393 | 1026 | } |
6d983946 | 1027 | |
401e6cd9 | 1028 | drm_dbg_kms(&i915->drm, "HDCP Auth failure (%d)\n", ret); |
a0124496 R |
1029 | |
1030 | /* Ensuring HDCP encryption and signalling are stopped. */ | |
1031 | _intel_hdcp_disable(connector); | |
ee5e5e7a SP |
1032 | } |
1033 | ||
401e6cd9 | 1034 | drm_dbg_kms(&i915->drm, |
65833c46 | 1035 | "HDCP authentication failed (%d tries/%d)\n", tries, ret); |
6d983946 | 1036 | return ret; |
ee5e5e7a SP |
1037 | } |
1038 | ||
81b55ef1 | 1039 | static struct intel_connector *intel_hdcp_to_connector(struct intel_hdcp *hdcp) |
d3dacc70 R |
1040 | { |
1041 | return container_of(hdcp, struct intel_connector, hdcp); | |
1042 | } | |
1043 | ||
a72394e4 SP |
1044 | static void intel_hdcp_update_value(struct intel_connector *connector, |
1045 | u64 value, bool update_property) | |
1046 | { | |
36e5e704 SP |
1047 | struct drm_device *dev = connector->base.dev; |
1048 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); | |
a72394e4 | 1049 | struct intel_hdcp *hdcp = &connector->hdcp; |
848a4e5c | 1050 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
a72394e4 SP |
1051 | |
1052 | drm_WARN_ON(connector->base.dev, !mutex_is_locked(&hdcp->mutex)); | |
1053 | ||
1054 | if (hdcp->value == value) | |
1055 | return; | |
1056 | ||
36e5e704 SP |
1057 | drm_WARN_ON(dev, !mutex_is_locked(&dig_port->hdcp_mutex)); |
1058 | ||
1059 | if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { | |
1060 | if (!drm_WARN_ON(dev, dig_port->num_hdcp_streams == 0)) | |
1061 | dig_port->num_hdcp_streams--; | |
1062 | } else if (value == DRM_MODE_CONTENT_PROTECTION_ENABLED) { | |
1063 | dig_port->num_hdcp_streams++; | |
1064 | } | |
1065 | ||
a72394e4 | 1066 | hdcp->value = value; |
a6597faa SP |
1067 | if (update_property) { |
1068 | drm_connector_get(&connector->base); | |
848a4e5c | 1069 | queue_work(i915->unordered_wq, &hdcp->prop_work); |
a6597faa | 1070 | } |
a72394e4 SP |
1071 | } |
1072 | ||
4c719c25 | 1073 | /* Implements Part 3 of the HDCP authorization procedure */ |
c5568ed2 | 1074 | static int intel_hdcp_check_link(struct intel_connector *connector) |
4c719c25 | 1075 | { |
7801f3b7 | 1076 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
401e6cd9 | 1077 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
486bba45 | 1078 | struct intel_hdcp *hdcp = &connector->hdcp; |
7801f3b7 | 1079 | enum port port = dig_port->base.port; |
69205931 | 1080 | enum transcoder cpu_transcoder; |
4c719c25 R |
1081 | int ret = 0; |
1082 | ||
4c719c25 | 1083 | mutex_lock(&hdcp->mutex); |
36e5e704 SP |
1084 | mutex_lock(&dig_port->hdcp_mutex); |
1085 | ||
69205931 | 1086 | cpu_transcoder = hdcp->cpu_transcoder; |
4c719c25 | 1087 | |
09d56393 R |
1088 | /* Check_link valid only when HDCP1.4 is enabled */ |
1089 | if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || | |
1090 | !hdcp->hdcp_encrypted) { | |
1091 | ret = -EINVAL; | |
4c719c25 | 1092 | goto out; |
09d56393 | 1093 | } |
4c719c25 | 1094 | |
401e6cd9 SK |
1095 | if (drm_WARN_ON(&i915->drm, |
1096 | !intel_hdcp_in_use(i915, cpu_transcoder, port))) { | |
1097 | drm_err(&i915->drm, | |
4773293b JN |
1098 | "[CONNECTOR:%d:%s] HDCP link stopped encryption,%x\n", |
1099 | connector->base.base.id, connector->base.name, | |
401e6cd9 | 1100 | intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port))); |
4c719c25 | 1101 | ret = -ENXIO; |
a72394e4 SP |
1102 | intel_hdcp_update_value(connector, |
1103 | DRM_MODE_CONTENT_PROTECTION_DESIRED, | |
1104 | true); | |
4c719c25 R |
1105 | goto out; |
1106 | } | |
1107 | ||
038bac89 | 1108 | if (hdcp->shim->check_link(dig_port, connector)) { |
4c719c25 | 1109 | if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { |
a72394e4 SP |
1110 | intel_hdcp_update_value(connector, |
1111 | DRM_MODE_CONTENT_PROTECTION_ENABLED, true); | |
4c719c25 R |
1112 | } |
1113 | goto out; | |
1114 | } | |
1115 | ||
401e6cd9 | 1116 | drm_dbg_kms(&i915->drm, |
4773293b JN |
1117 | "[CONNECTOR:%d:%s] HDCP link failed, retrying authentication\n", |
1118 | connector->base.base.id, connector->base.name); | |
4c719c25 R |
1119 | |
1120 | ret = _intel_hdcp_disable(connector); | |
1121 | if (ret) { | |
401e6cd9 | 1122 | drm_err(&i915->drm, "Failed to disable hdcp (%d)\n", ret); |
a72394e4 SP |
1123 | intel_hdcp_update_value(connector, |
1124 | DRM_MODE_CONTENT_PROTECTION_DESIRED, | |
1125 | true); | |
4c719c25 R |
1126 | goto out; |
1127 | } | |
1128 | ||
483f7d94 SK |
1129 | intel_hdcp_update_value(connector, |
1130 | DRM_MODE_CONTENT_PROTECTION_DESIRED, | |
1131 | true); | |
4c719c25 | 1132 | out: |
36e5e704 | 1133 | mutex_unlock(&dig_port->hdcp_mutex); |
4c719c25 R |
1134 | mutex_unlock(&hdcp->mutex); |
1135 | return ret; | |
1136 | } | |
1137 | ||
ee5e5e7a SP |
1138 | static void intel_hdcp_prop_work(struct work_struct *work) |
1139 | { | |
d3dacc70 R |
1140 | struct intel_hdcp *hdcp = container_of(work, struct intel_hdcp, |
1141 | prop_work); | |
1142 | struct intel_connector *connector = intel_hdcp_to_connector(hdcp); | |
401e6cd9 | 1143 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
ee5e5e7a | 1144 | |
401e6cd9 | 1145 | drm_modeset_lock(&i915->drm.mode_config.connection_mutex, NULL); |
d3dacc70 | 1146 | mutex_lock(&hdcp->mutex); |
ee5e5e7a SP |
1147 | |
1148 | /* | |
1149 | * This worker is only used to flip between ENABLED/DESIRED. Either of | |
d3dacc70 | 1150 | * those to UNDESIRED is handled by core. If value == UNDESIRED, |
ee5e5e7a SP |
1151 | * we're running just after hdcp has been disabled, so just exit |
1152 | */ | |
a41e71f4 R |
1153 | if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) |
1154 | drm_hdcp_update_content_protection(&connector->base, | |
1155 | hdcp->value); | |
ee5e5e7a | 1156 | |
d3dacc70 | 1157 | mutex_unlock(&hdcp->mutex); |
401e6cd9 | 1158 | drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); |
a6597faa SP |
1159 | |
1160 | drm_connector_put(&connector->base); | |
ee5e5e7a SP |
1161 | } |
1162 | ||
401e6cd9 | 1163 | bool is_hdcp_supported(struct drm_i915_private *i915, enum port port) |
fdddd08c | 1164 | { |
401e6cd9 SK |
1165 | return DISPLAY_RUNTIME_INFO(i915)->has_hdcp && |
1166 | (DISPLAY_VER(i915) >= 12 || port < PORT_E); | |
fdddd08c R |
1167 | } |
1168 | ||
bd90d7c7 | 1169 | static int |
9055aac7 R |
1170 | hdcp2_prepare_ake_init(struct intel_connector *connector, |
1171 | struct hdcp2_ake_init *ake_data) | |
1172 | { | |
a6c6eac9 AG |
1173 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
1174 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; | |
401e6cd9 | 1175 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
5c8ec987 | 1176 | struct i915_hdcp_arbiter *arbiter; |
9055aac7 R |
1177 | int ret; |
1178 | ||
3e36c490 | 1179 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
5c8ec987 | 1180 | arbiter = i915->display.hdcp.arbiter; |
9055aac7 | 1181 | |
4f73dc7a | 1182 | if (!arbiter || !arbiter->ops) { |
3e36c490 | 1183 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1184 | return -EINVAL; |
1185 | } | |
1186 | ||
4f73dc7a | 1187 | ret = arbiter->ops->initiate_hdcp2_session(arbiter->hdcp_dev, data, ake_data); |
9055aac7 | 1188 | if (ret) |
401e6cd9 | 1189 | drm_dbg_kms(&i915->drm, "Prepare_ake_init failed. %d\n", |
65833c46 | 1190 | ret); |
3e36c490 | 1191 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1192 | |
1193 | return ret; | |
1194 | } | |
1195 | ||
bd90d7c7 | 1196 | static int |
9055aac7 R |
1197 | hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector, |
1198 | struct hdcp2_ake_send_cert *rx_cert, | |
1199 | bool *paired, | |
1200 | struct hdcp2_ake_no_stored_km *ek_pub_km, | |
1201 | size_t *msg_sz) | |
1202 | { | |
a6c6eac9 AG |
1203 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
1204 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; | |
401e6cd9 | 1205 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
5c8ec987 | 1206 | struct i915_hdcp_arbiter *arbiter; |
9055aac7 R |
1207 | int ret; |
1208 | ||
3e36c490 | 1209 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
5c8ec987 | 1210 | arbiter = i915->display.hdcp.arbiter; |
9055aac7 | 1211 | |
4f73dc7a | 1212 | if (!arbiter || !arbiter->ops) { |
3e36c490 | 1213 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1214 | return -EINVAL; |
1215 | } | |
1216 | ||
4f73dc7a | 1217 | ret = arbiter->ops->verify_receiver_cert_prepare_km(arbiter->hdcp_dev, data, |
9055aac7 R |
1218 | rx_cert, paired, |
1219 | ek_pub_km, msg_sz); | |
1220 | if (ret < 0) | |
401e6cd9 | 1221 | drm_dbg_kms(&i915->drm, "Verify rx_cert failed. %d\n", |
65833c46 | 1222 | ret); |
3e36c490 | 1223 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1224 | |
1225 | return ret; | |
1226 | } | |
1227 | ||
bd90d7c7 R |
1228 | static int hdcp2_verify_hprime(struct intel_connector *connector, |
1229 | struct hdcp2_ake_send_hprime *rx_hprime) | |
9055aac7 | 1230 | { |
a6c6eac9 AG |
1231 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
1232 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; | |
401e6cd9 | 1233 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
5c8ec987 | 1234 | struct i915_hdcp_arbiter *arbiter; |
9055aac7 R |
1235 | int ret; |
1236 | ||
3e36c490 | 1237 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
5c8ec987 | 1238 | arbiter = i915->display.hdcp.arbiter; |
9055aac7 | 1239 | |
4f73dc7a | 1240 | if (!arbiter || !arbiter->ops) { |
3e36c490 | 1241 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1242 | return -EINVAL; |
1243 | } | |
1244 | ||
4f73dc7a | 1245 | ret = arbiter->ops->verify_hprime(arbiter->hdcp_dev, data, rx_hprime); |
9055aac7 | 1246 | if (ret < 0) |
401e6cd9 | 1247 | drm_dbg_kms(&i915->drm, "Verify hprime failed. %d\n", ret); |
3e36c490 | 1248 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1249 | |
1250 | return ret; | |
1251 | } | |
1252 | ||
bd90d7c7 | 1253 | static int |
9055aac7 R |
1254 | hdcp2_store_pairing_info(struct intel_connector *connector, |
1255 | struct hdcp2_ake_send_pairing_info *pairing_info) | |
1256 | { | |
a6c6eac9 AG |
1257 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
1258 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; | |
401e6cd9 | 1259 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
5c8ec987 | 1260 | struct i915_hdcp_arbiter *arbiter; |
9055aac7 R |
1261 | int ret; |
1262 | ||
3e36c490 | 1263 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
5c8ec987 | 1264 | arbiter = i915->display.hdcp.arbiter; |
9055aac7 | 1265 | |
4f73dc7a | 1266 | if (!arbiter || !arbiter->ops) { |
3e36c490 | 1267 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1268 | return -EINVAL; |
1269 | } | |
1270 | ||
4f73dc7a | 1271 | ret = arbiter->ops->store_pairing_info(arbiter->hdcp_dev, data, pairing_info); |
9055aac7 | 1272 | if (ret < 0) |
401e6cd9 | 1273 | drm_dbg_kms(&i915->drm, "Store pairing info failed. %d\n", |
65833c46 | 1274 | ret); |
3e36c490 | 1275 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1276 | |
1277 | return ret; | |
1278 | } | |
1279 | ||
bd90d7c7 | 1280 | static int |
9055aac7 R |
1281 | hdcp2_prepare_lc_init(struct intel_connector *connector, |
1282 | struct hdcp2_lc_init *lc_init) | |
1283 | { | |
a6c6eac9 AG |
1284 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
1285 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; | |
401e6cd9 | 1286 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
5c8ec987 | 1287 | struct i915_hdcp_arbiter *arbiter; |
9055aac7 R |
1288 | int ret; |
1289 | ||
3e36c490 | 1290 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
5c8ec987 | 1291 | arbiter = i915->display.hdcp.arbiter; |
9055aac7 | 1292 | |
4f73dc7a | 1293 | if (!arbiter || !arbiter->ops) { |
3e36c490 | 1294 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1295 | return -EINVAL; |
1296 | } | |
1297 | ||
4f73dc7a | 1298 | ret = arbiter->ops->initiate_locality_check(arbiter->hdcp_dev, data, lc_init); |
9055aac7 | 1299 | if (ret < 0) |
401e6cd9 | 1300 | drm_dbg_kms(&i915->drm, "Prepare lc_init failed. %d\n", |
65833c46 | 1301 | ret); |
3e36c490 | 1302 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1303 | |
1304 | return ret; | |
1305 | } | |
1306 | ||
bd90d7c7 | 1307 | static int |
9055aac7 R |
1308 | hdcp2_verify_lprime(struct intel_connector *connector, |
1309 | struct hdcp2_lc_send_lprime *rx_lprime) | |
1310 | { | |
a6c6eac9 AG |
1311 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
1312 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; | |
401e6cd9 | 1313 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
5c8ec987 | 1314 | struct i915_hdcp_arbiter *arbiter; |
9055aac7 R |
1315 | int ret; |
1316 | ||
3e36c490 | 1317 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
5c8ec987 | 1318 | arbiter = i915->display.hdcp.arbiter; |
9055aac7 | 1319 | |
4f73dc7a | 1320 | if (!arbiter || !arbiter->ops) { |
3e36c490 | 1321 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1322 | return -EINVAL; |
1323 | } | |
1324 | ||
4f73dc7a | 1325 | ret = arbiter->ops->verify_lprime(arbiter->hdcp_dev, data, rx_lprime); |
9055aac7 | 1326 | if (ret < 0) |
401e6cd9 | 1327 | drm_dbg_kms(&i915->drm, "Verify L_Prime failed. %d\n", |
65833c46 | 1328 | ret); |
3e36c490 | 1329 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1330 | |
1331 | return ret; | |
1332 | } | |
1333 | ||
bd90d7c7 R |
1334 | static int hdcp2_prepare_skey(struct intel_connector *connector, |
1335 | struct hdcp2_ske_send_eks *ske_data) | |
9055aac7 | 1336 | { |
a6c6eac9 AG |
1337 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
1338 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; | |
401e6cd9 | 1339 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
5c8ec987 | 1340 | struct i915_hdcp_arbiter *arbiter; |
9055aac7 R |
1341 | int ret; |
1342 | ||
3e36c490 | 1343 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
5c8ec987 | 1344 | arbiter = i915->display.hdcp.arbiter; |
9055aac7 | 1345 | |
4f73dc7a | 1346 | if (!arbiter || !arbiter->ops) { |
3e36c490 | 1347 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1348 | return -EINVAL; |
1349 | } | |
1350 | ||
4f73dc7a | 1351 | ret = arbiter->ops->get_session_key(arbiter->hdcp_dev, data, ske_data); |
9055aac7 | 1352 | if (ret < 0) |
401e6cd9 | 1353 | drm_dbg_kms(&i915->drm, "Get session key failed. %d\n", |
65833c46 | 1354 | ret); |
3e36c490 | 1355 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1356 | |
1357 | return ret; | |
1358 | } | |
1359 | ||
d849178e | 1360 | static int |
9055aac7 R |
1361 | hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector, |
1362 | struct hdcp2_rep_send_receiverid_list | |
1363 | *rep_topology, | |
1364 | struct hdcp2_rep_send_ack *rep_send_ack) | |
1365 | { | |
a6c6eac9 AG |
1366 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
1367 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; | |
401e6cd9 | 1368 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
5c8ec987 | 1369 | struct i915_hdcp_arbiter *arbiter; |
9055aac7 R |
1370 | int ret; |
1371 | ||
3e36c490 | 1372 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
5c8ec987 | 1373 | arbiter = i915->display.hdcp.arbiter; |
9055aac7 | 1374 | |
4f73dc7a | 1375 | if (!arbiter || !arbiter->ops) { |
3e36c490 | 1376 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1377 | return -EINVAL; |
1378 | } | |
1379 | ||
4f73dc7a AG |
1380 | ret = arbiter->ops->repeater_check_flow_prepare_ack(arbiter->hdcp_dev, |
1381 | data, | |
1382 | rep_topology, | |
1383 | rep_send_ack); | |
9055aac7 | 1384 | if (ret < 0) |
401e6cd9 | 1385 | drm_dbg_kms(&i915->drm, |
65833c46 | 1386 | "Verify rep topology failed. %d\n", ret); |
3e36c490 | 1387 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1388 | |
1389 | return ret; | |
1390 | } | |
1391 | ||
d849178e | 1392 | static int |
9055aac7 R |
1393 | hdcp2_verify_mprime(struct intel_connector *connector, |
1394 | struct hdcp2_rep_stream_ready *stream_ready) | |
1395 | { | |
a6c6eac9 AG |
1396 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
1397 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; | |
401e6cd9 | 1398 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
5c8ec987 | 1399 | struct i915_hdcp_arbiter *arbiter; |
9055aac7 R |
1400 | int ret; |
1401 | ||
3e36c490 | 1402 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
5c8ec987 | 1403 | arbiter = i915->display.hdcp.arbiter; |
9055aac7 | 1404 | |
4f73dc7a | 1405 | if (!arbiter || !arbiter->ops) { |
3e36c490 | 1406 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1407 | return -EINVAL; |
1408 | } | |
1409 | ||
4f73dc7a | 1410 | ret = arbiter->ops->verify_mprime(arbiter->hdcp_dev, data, stream_ready); |
9055aac7 | 1411 | if (ret < 0) |
401e6cd9 | 1412 | drm_dbg_kms(&i915->drm, "Verify mprime failed. %d\n", ret); |
3e36c490 | 1413 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1414 | |
1415 | return ret; | |
1416 | } | |
1417 | ||
bd90d7c7 | 1418 | static int hdcp2_authenticate_port(struct intel_connector *connector) |
9055aac7 | 1419 | { |
a6c6eac9 AG |
1420 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
1421 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; | |
401e6cd9 | 1422 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
5c8ec987 | 1423 | struct i915_hdcp_arbiter *arbiter; |
9055aac7 R |
1424 | int ret; |
1425 | ||
3e36c490 | 1426 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
5c8ec987 | 1427 | arbiter = i915->display.hdcp.arbiter; |
9055aac7 | 1428 | |
4f73dc7a | 1429 | if (!arbiter || !arbiter->ops) { |
3e36c490 | 1430 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1431 | return -EINVAL; |
1432 | } | |
1433 | ||
4f73dc7a | 1434 | ret = arbiter->ops->enable_hdcp_authentication(arbiter->hdcp_dev, data); |
9055aac7 | 1435 | if (ret < 0) |
401e6cd9 | 1436 | drm_dbg_kms(&i915->drm, "Enable hdcp auth failed. %d\n", |
65833c46 | 1437 | ret); |
3e36c490 | 1438 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1439 | |
1440 | return ret; | |
1441 | } | |
1442 | ||
f210d8d2 | 1443 | static int hdcp2_close_session(struct intel_connector *connector) |
9055aac7 | 1444 | { |
a6c6eac9 | 1445 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
401e6cd9 | 1446 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
5c8ec987 | 1447 | struct i915_hdcp_arbiter *arbiter; |
9055aac7 R |
1448 | int ret; |
1449 | ||
3e36c490 | 1450 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
5c8ec987 | 1451 | arbiter = i915->display.hdcp.arbiter; |
9055aac7 | 1452 | |
4f73dc7a | 1453 | if (!arbiter || !arbiter->ops) { |
3e36c490 | 1454 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1455 | return -EINVAL; |
1456 | } | |
1457 | ||
4f73dc7a | 1458 | ret = arbiter->ops->close_hdcp_session(arbiter->hdcp_dev, |
a6c6eac9 | 1459 | &dig_port->hdcp_port_data); |
3e36c490 | 1460 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
1461 | |
1462 | return ret; | |
1463 | } | |
1464 | ||
49a630b0 | 1465 | static int hdcp2_deauthenticate_port(struct intel_connector *connector) |
9055aac7 | 1466 | { |
f210d8d2 | 1467 | return hdcp2_close_session(connector); |
9055aac7 R |
1468 | } |
1469 | ||
bd90d7c7 R |
1470 | /* Authentication flow starts from here */ |
1471 | static int hdcp2_authentication_key_exchange(struct intel_connector *connector) | |
1472 | { | |
401e6cd9 | 1473 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
bd90d7c7 R |
1474 | struct intel_hdcp *hdcp = &connector->hdcp; |
1475 | union { | |
1476 | struct hdcp2_ake_init ake_init; | |
1477 | struct hdcp2_ake_send_cert send_cert; | |
1478 | struct hdcp2_ake_no_stored_km no_stored_km; | |
1479 | struct hdcp2_ake_send_hprime send_hprime; | |
1480 | struct hdcp2_ake_send_pairing_info pairing_info; | |
1481 | } msgs; | |
1482 | const struct intel_hdcp_shim *shim = hdcp->shim; | |
1483 | size_t size; | |
1484 | int ret; | |
1485 | ||
1486 | /* Init for seq_num */ | |
1487 | hdcp->seq_num_v = 0; | |
1488 | hdcp->seq_num_m = 0; | |
1489 | ||
1490 | ret = hdcp2_prepare_ake_init(connector, &msgs.ake_init); | |
1491 | if (ret < 0) | |
1492 | return ret; | |
1493 | ||
51152acf | 1494 | ret = shim->write_2_2_msg(connector, &msgs.ake_init, |
bd90d7c7 R |
1495 | sizeof(msgs.ake_init)); |
1496 | if (ret < 0) | |
1497 | return ret; | |
1498 | ||
51152acf | 1499 | ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_CERT, |
bd90d7c7 R |
1500 | &msgs.send_cert, sizeof(msgs.send_cert)); |
1501 | if (ret < 0) | |
1502 | return ret; | |
1503 | ||
4fb76782 | 1504 | if (msgs.send_cert.rx_caps[0] != HDCP_2_2_RX_CAPS_VERSION_VAL) { |
401e6cd9 | 1505 | drm_dbg_kms(&i915->drm, "cert.rx_caps dont claim HDCP2.2\n"); |
bd90d7c7 | 1506 | return -EINVAL; |
4fb76782 | 1507 | } |
bd90d7c7 R |
1508 | |
1509 | hdcp->is_repeater = HDCP_2_2_RX_REPEATER(msgs.send_cert.rx_caps[2]); | |
1510 | ||
401e6cd9 | 1511 | if (drm_hdcp_check_ksvs_revoked(&i915->drm, |
486bba45 | 1512 | msgs.send_cert.cert_rx.receiver_id, |
018532e9 | 1513 | 1) > 0) { |
401e6cd9 | 1514 | drm_err(&i915->drm, "Receiver ID is revoked\n"); |
f26ae6a6 R |
1515 | return -EPERM; |
1516 | } | |
1517 | ||
bd90d7c7 R |
1518 | /* |
1519 | * Here msgs.no_stored_km will hold msgs corresponding to the km | |
1520 | * stored also. | |
1521 | */ | |
1522 | ret = hdcp2_verify_rx_cert_prepare_km(connector, &msgs.send_cert, | |
1523 | &hdcp->is_paired, | |
1524 | &msgs.no_stored_km, &size); | |
1525 | if (ret < 0) | |
1526 | return ret; | |
1527 | ||
51152acf | 1528 | ret = shim->write_2_2_msg(connector, &msgs.no_stored_km, size); |
bd90d7c7 R |
1529 | if (ret < 0) |
1530 | return ret; | |
1531 | ||
51152acf | 1532 | ret = shim->read_2_2_msg(connector, HDCP_2_2_AKE_SEND_HPRIME, |
bd90d7c7 R |
1533 | &msgs.send_hprime, sizeof(msgs.send_hprime)); |
1534 | if (ret < 0) | |
1535 | return ret; | |
1536 | ||
1537 | ret = hdcp2_verify_hprime(connector, &msgs.send_hprime); | |
1538 | if (ret < 0) | |
1539 | return ret; | |
1540 | ||
1541 | if (!hdcp->is_paired) { | |
1542 | /* Pairing is required */ | |
51152acf | 1543 | ret = shim->read_2_2_msg(connector, |
bd90d7c7 R |
1544 | HDCP_2_2_AKE_SEND_PAIRING_INFO, |
1545 | &msgs.pairing_info, | |
1546 | sizeof(msgs.pairing_info)); | |
1547 | if (ret < 0) | |
1548 | return ret; | |
1549 | ||
1550 | ret = hdcp2_store_pairing_info(connector, &msgs.pairing_info); | |
1551 | if (ret < 0) | |
1552 | return ret; | |
1553 | hdcp->is_paired = true; | |
1554 | } | |
1555 | ||
1556 | return 0; | |
1557 | } | |
1558 | ||
1559 | static int hdcp2_locality_check(struct intel_connector *connector) | |
1560 | { | |
bd90d7c7 R |
1561 | struct intel_hdcp *hdcp = &connector->hdcp; |
1562 | union { | |
1563 | struct hdcp2_lc_init lc_init; | |
1564 | struct hdcp2_lc_send_lprime send_lprime; | |
1565 | } msgs; | |
1566 | const struct intel_hdcp_shim *shim = hdcp->shim; | |
1567 | int tries = HDCP2_LC_RETRY_CNT, ret, i; | |
1568 | ||
1569 | for (i = 0; i < tries; i++) { | |
1570 | ret = hdcp2_prepare_lc_init(connector, &msgs.lc_init); | |
1571 | if (ret < 0) | |
1572 | continue; | |
1573 | ||
51152acf | 1574 | ret = shim->write_2_2_msg(connector, &msgs.lc_init, |
bd90d7c7 R |
1575 | sizeof(msgs.lc_init)); |
1576 | if (ret < 0) | |
1577 | continue; | |
1578 | ||
51152acf | 1579 | ret = shim->read_2_2_msg(connector, |
bd90d7c7 R |
1580 | HDCP_2_2_LC_SEND_LPRIME, |
1581 | &msgs.send_lprime, | |
1582 | sizeof(msgs.send_lprime)); | |
1583 | if (ret < 0) | |
1584 | continue; | |
1585 | ||
1586 | ret = hdcp2_verify_lprime(connector, &msgs.send_lprime); | |
1587 | if (!ret) | |
1588 | break; | |
1589 | } | |
1590 | ||
1591 | return ret; | |
1592 | } | |
1593 | ||
1594 | static int hdcp2_session_key_exchange(struct intel_connector *connector) | |
1595 | { | |
bd90d7c7 R |
1596 | struct intel_hdcp *hdcp = &connector->hdcp; |
1597 | struct hdcp2_ske_send_eks send_eks; | |
1598 | int ret; | |
1599 | ||
1600 | ret = hdcp2_prepare_skey(connector, &send_eks); | |
1601 | if (ret < 0) | |
1602 | return ret; | |
1603 | ||
51152acf | 1604 | ret = hdcp->shim->write_2_2_msg(connector, &send_eks, |
bd90d7c7 R |
1605 | sizeof(send_eks)); |
1606 | if (ret < 0) | |
1607 | return ret; | |
1608 | ||
1609 | return 0; | |
1610 | } | |
1611 | ||
d849178e | 1612 | static |
cb88d1fa | 1613 | int _hdcp2_propagate_stream_management_info(struct intel_connector *connector) |
d849178e | 1614 | { |
7801f3b7 | 1615 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
e03187e1 | 1616 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; |
d849178e R |
1617 | struct intel_hdcp *hdcp = &connector->hdcp; |
1618 | union { | |
1619 | struct hdcp2_rep_stream_manage stream_manage; | |
1620 | struct hdcp2_rep_stream_ready stream_ready; | |
1621 | } msgs; | |
1622 | const struct intel_hdcp_shim *shim = hdcp->shim; | |
e03187e1 | 1623 | int ret, streams_size_delta, i; |
d849178e | 1624 | |
bff88b1c R |
1625 | if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) |
1626 | return -ERANGE; | |
1627 | ||
d849178e R |
1628 | /* Prepare RepeaterAuth_Stream_Manage msg */ |
1629 | msgs.stream_manage.msg_id = HDCP_2_2_REP_STREAM_MANAGE; | |
0de655ca | 1630 | drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m); |
d849178e | 1631 | |
e03187e1 | 1632 | msgs.stream_manage.k = cpu_to_be16(data->k); |
d849178e | 1633 | |
e03187e1 AG |
1634 | for (i = 0; i < data->k; i++) { |
1635 | msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id; | |
1636 | msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type; | |
1637 | } | |
d849178e | 1638 | |
e03187e1 AG |
1639 | streams_size_delta = (HDCP_2_2_MAX_CONTENT_STREAMS_CNT - data->k) * |
1640 | sizeof(struct hdcp2_streamid_type); | |
d849178e | 1641 | /* Send it to Repeater */ |
51152acf | 1642 | ret = shim->write_2_2_msg(connector, &msgs.stream_manage, |
e03187e1 | 1643 | sizeof(msgs.stream_manage) - streams_size_delta); |
d849178e | 1644 | if (ret < 0) |
cb88d1fa | 1645 | goto out; |
d849178e | 1646 | |
51152acf | 1647 | ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_STREAM_READY, |
d849178e R |
1648 | &msgs.stream_ready, sizeof(msgs.stream_ready)); |
1649 | if (ret < 0) | |
cb88d1fa | 1650 | goto out; |
d849178e | 1651 | |
e03187e1 | 1652 | data->seq_num_m = hdcp->seq_num_m; |
a6c6eac9 | 1653 | |
d849178e | 1654 | ret = hdcp2_verify_mprime(connector, &msgs.stream_ready); |
d849178e | 1655 | |
cb88d1fa | 1656 | out: |
d849178e | 1657 | hdcp->seq_num_m++; |
d849178e | 1658 | |
cb88d1fa | 1659 | return ret; |
d849178e R |
1660 | } |
1661 | ||
1662 | static | |
1663 | int hdcp2_authenticate_repeater_topology(struct intel_connector *connector) | |
1664 | { | |
7801f3b7 | 1665 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
401e6cd9 | 1666 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
d849178e R |
1667 | struct intel_hdcp *hdcp = &connector->hdcp; |
1668 | union { | |
1669 | struct hdcp2_rep_send_receiverid_list recvid_list; | |
1670 | struct hdcp2_rep_send_ack rep_ack; | |
1671 | } msgs; | |
1672 | const struct intel_hdcp_shim *shim = hdcp->shim; | |
f26ae6a6 | 1673 | u32 seq_num_v, device_cnt; |
d849178e | 1674 | u8 *rx_info; |
d849178e R |
1675 | int ret; |
1676 | ||
51152acf | 1677 | ret = shim->read_2_2_msg(connector, HDCP_2_2_REP_SEND_RECVID_LIST, |
d849178e R |
1678 | &msgs.recvid_list, sizeof(msgs.recvid_list)); |
1679 | if (ret < 0) | |
1680 | return ret; | |
1681 | ||
1682 | rx_info = msgs.recvid_list.rx_info; | |
1683 | ||
1684 | if (HDCP_2_2_MAX_CASCADE_EXCEEDED(rx_info[1]) || | |
1685 | HDCP_2_2_MAX_DEVS_EXCEEDED(rx_info[1])) { | |
401e6cd9 | 1686 | drm_dbg_kms(&i915->drm, "Topology Max Size Exceeded\n"); |
d849178e R |
1687 | return -EINVAL; |
1688 | } | |
1689 | ||
3e31d057 JL |
1690 | /* |
1691 | * MST topology is not Type 1 capable if it contains a downstream | |
1692 | * device that is only HDCP 1.x or Legacy HDCP 2.0/2.1 compliant. | |
1693 | */ | |
1694 | dig_port->hdcp_mst_type1_capable = | |
1695 | !HDCP_2_2_HDCP1_DEVICE_CONNECTED(rx_info[1]) && | |
1696 | !HDCP_2_2_HDCP_2_0_REP_CONNECTED(rx_info[1]); | |
1697 | ||
da2d6684 SK |
1698 | if (!dig_port->hdcp_mst_type1_capable && hdcp->content_type) { |
1699 | drm_dbg_kms(&i915->drm, | |
1700 | "HDCP1.x or 2.0 Legacy Device Downstream\n"); | |
1701 | return -EINVAL; | |
1702 | } | |
1703 | ||
d849178e | 1704 | /* Converting and Storing the seq_num_v to local variable as DWORD */ |
0de655ca R |
1705 | seq_num_v = |
1706 | drm_hdcp_be24_to_cpu((const u8 *)msgs.recvid_list.seq_num_v); | |
d849178e | 1707 | |
beb77129 | 1708 | if (!hdcp->hdcp2_encrypted && seq_num_v) { |
401e6cd9 | 1709 | drm_dbg_kms(&i915->drm, |
beb77129 AG |
1710 | "Non zero Seq_num_v at first RecvId_List msg\n"); |
1711 | return -EINVAL; | |
1712 | } | |
1713 | ||
d849178e R |
1714 | if (seq_num_v < hdcp->seq_num_v) { |
1715 | /* Roll over of the seq_num_v from repeater. Reauthenticate. */ | |
401e6cd9 | 1716 | drm_dbg_kms(&i915->drm, "Seq_num_v roll over.\n"); |
d849178e R |
1717 | return -EINVAL; |
1718 | } | |
1719 | ||
af461ff3 CW |
1720 | device_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | |
1721 | HDCP_2_2_DEV_COUNT_LO(rx_info[1])); | |
401e6cd9 | 1722 | if (drm_hdcp_check_ksvs_revoked(&i915->drm, |
486bba45 | 1723 | msgs.recvid_list.receiver_ids, |
018532e9 | 1724 | device_cnt) > 0) { |
401e6cd9 | 1725 | drm_err(&i915->drm, "Revoked receiver ID(s) is in list\n"); |
f26ae6a6 R |
1726 | return -EPERM; |
1727 | } | |
1728 | ||
d849178e R |
1729 | ret = hdcp2_verify_rep_topology_prepare_ack(connector, |
1730 | &msgs.recvid_list, | |
1731 | &msgs.rep_ack); | |
1732 | if (ret < 0) | |
1733 | return ret; | |
1734 | ||
1735 | hdcp->seq_num_v = seq_num_v; | |
51152acf | 1736 | ret = shim->write_2_2_msg(connector, &msgs.rep_ack, |
d849178e R |
1737 | sizeof(msgs.rep_ack)); |
1738 | if (ret < 0) | |
1739 | return ret; | |
1740 | ||
1741 | return 0; | |
1742 | } | |
1743 | ||
49a630b0 R |
1744 | static int hdcp2_authenticate_sink(struct intel_connector *connector) |
1745 | { | |
51279100 | 1746 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
bd90d7c7 R |
1747 | struct intel_hdcp *hdcp = &connector->hdcp; |
1748 | const struct intel_hdcp_shim *shim = hdcp->shim; | |
1749 | int ret; | |
49a630b0 | 1750 | |
bd90d7c7 R |
1751 | ret = hdcp2_authentication_key_exchange(connector); |
1752 | if (ret < 0) { | |
51279100 | 1753 | drm_dbg_kms(&i915->drm, "AKE Failed. Err : %d\n", ret); |
bd90d7c7 R |
1754 | return ret; |
1755 | } | |
1756 | ||
1757 | ret = hdcp2_locality_check(connector); | |
1758 | if (ret < 0) { | |
51279100 R |
1759 | drm_dbg_kms(&i915->drm, |
1760 | "Locality Check failed. Err : %d\n", ret); | |
bd90d7c7 R |
1761 | return ret; |
1762 | } | |
1763 | ||
1764 | ret = hdcp2_session_key_exchange(connector); | |
1765 | if (ret < 0) { | |
51279100 | 1766 | drm_dbg_kms(&i915->drm, "SKE Failed. Err : %d\n", ret); |
bd90d7c7 R |
1767 | return ret; |
1768 | } | |
1769 | ||
1770 | if (shim->config_stream_type) { | |
51152acf | 1771 | ret = shim->config_stream_type(connector, |
bd90d7c7 R |
1772 | hdcp->is_repeater, |
1773 | hdcp->content_type); | |
1774 | if (ret < 0) | |
1775 | return ret; | |
1776 | } | |
1777 | ||
d849178e | 1778 | if (hdcp->is_repeater) { |
cb88d1fa | 1779 | ret = hdcp2_authenticate_repeater_topology(connector); |
d849178e | 1780 | if (ret < 0) { |
51279100 R |
1781 | drm_dbg_kms(&i915->drm, |
1782 | "Repeater Auth Failed. Err: %d\n", ret); | |
d849178e R |
1783 | return ret; |
1784 | } | |
1785 | } | |
1786 | ||
bd90d7c7 | 1787 | return ret; |
49a630b0 R |
1788 | } |
1789 | ||
899c8762 AG |
1790 | static int hdcp2_enable_stream_encryption(struct intel_connector *connector) |
1791 | { | |
1792 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); | |
401e6cd9 | 1793 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
8b06f6d8 | 1794 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; |
899c8762 AG |
1795 | struct intel_hdcp *hdcp = &connector->hdcp; |
1796 | enum transcoder cpu_transcoder = hdcp->cpu_transcoder; | |
1797 | enum port port = dig_port->base.port; | |
1798 | int ret = 0; | |
1799 | ||
401e6cd9 | 1800 | if (!(intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port)) & |
899c8762 | 1801 | LINK_ENCRYPTION_STATUS)) { |
4773293b JN |
1802 | drm_err(&i915->drm, "[CONNECTOR:%d:%s] HDCP 2.2 Link is not encrypted\n", |
1803 | connector->base.base.id, connector->base.name); | |
8b06f6d8 AG |
1804 | ret = -EPERM; |
1805 | goto link_recover; | |
899c8762 AG |
1806 | } |
1807 | ||
1808 | if (hdcp->shim->stream_2_2_encryption) { | |
1809 | ret = hdcp->shim->stream_2_2_encryption(connector, true); | |
1810 | if (ret) { | |
4773293b JN |
1811 | drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to enable HDCP 2.2 stream enc\n", |
1812 | connector->base.base.id, connector->base.name); | |
899c8762 AG |
1813 | return ret; |
1814 | } | |
401e6cd9 | 1815 | drm_dbg_kms(&i915->drm, "HDCP 2.2 transcoder: %s stream encrypted\n", |
899c8762 AG |
1816 | transcoder_name(hdcp->stream_transcoder)); |
1817 | } | |
1818 | ||
8b06f6d8 AG |
1819 | return 0; |
1820 | ||
1821 | link_recover: | |
1822 | if (hdcp2_deauthenticate_port(connector) < 0) | |
401e6cd9 | 1823 | drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); |
8b06f6d8 AG |
1824 | |
1825 | dig_port->hdcp_auth_status = false; | |
1826 | data->k = 0; | |
1827 | ||
899c8762 AG |
1828 | return ret; |
1829 | } | |
1830 | ||
49a630b0 R |
1831 | static int hdcp2_enable_encryption(struct intel_connector *connector) |
1832 | { | |
7801f3b7 | 1833 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
401e6cd9 | 1834 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
49a630b0 | 1835 | struct intel_hdcp *hdcp = &connector->hdcp; |
7801f3b7 | 1836 | enum port port = dig_port->base.port; |
69205931 | 1837 | enum transcoder cpu_transcoder = hdcp->cpu_transcoder; |
49a630b0 R |
1838 | int ret; |
1839 | ||
401e6cd9 SK |
1840 | drm_WARN_ON(&i915->drm, |
1841 | intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port)) & | |
bb393dc5 | 1842 | LINK_ENCRYPTION_STATUS); |
49a630b0 | 1843 | if (hdcp->shim->toggle_signalling) { |
0b9c9290 SP |
1844 | ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, |
1845 | true); | |
49a630b0 | 1846 | if (ret) { |
401e6cd9 | 1847 | drm_err(&i915->drm, |
65833c46 WK |
1848 | "Failed to enable HDCP signalling. %d\n", |
1849 | ret); | |
49a630b0 R |
1850 | return ret; |
1851 | } | |
1852 | } | |
1853 | ||
401e6cd9 | 1854 | if (intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port)) & |
cd5103ee | 1855 | LINK_AUTH_STATUS) |
49a630b0 | 1856 | /* Link is Authenticated. Now set for Encryption */ |
401e6cd9 | 1857 | intel_de_rmw(i915, HDCP2_CTL(i915, cpu_transcoder, port), |
cd5103ee | 1858 | 0, CTL_LINK_ENCRYPTION_REQ); |
49a630b0 | 1859 | |
401e6cd9 SK |
1860 | ret = intel_de_wait_for_set(i915, |
1861 | HDCP2_STATUS(i915, cpu_transcoder, | |
69205931 | 1862 | port), |
4cb3b44d | 1863 | LINK_ENCRYPTION_STATUS, |
fbf652bd | 1864 | HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); |
e03187e1 | 1865 | dig_port->hdcp_auth_status = true; |
49a630b0 R |
1866 | |
1867 | return ret; | |
1868 | } | |
1869 | ||
1870 | static int hdcp2_disable_encryption(struct intel_connector *connector) | |
1871 | { | |
7801f3b7 | 1872 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
401e6cd9 | 1873 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
49a630b0 | 1874 | struct intel_hdcp *hdcp = &connector->hdcp; |
7801f3b7 | 1875 | enum port port = dig_port->base.port; |
69205931 | 1876 | enum transcoder cpu_transcoder = hdcp->cpu_transcoder; |
49a630b0 R |
1877 | int ret; |
1878 | ||
401e6cd9 | 1879 | drm_WARN_ON(&i915->drm, !(intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port)) & |
bb393dc5 | 1880 | LINK_ENCRYPTION_STATUS)); |
49a630b0 | 1881 | |
401e6cd9 | 1882 | intel_de_rmw(i915, HDCP2_CTL(i915, cpu_transcoder, port), |
cd5103ee | 1883 | CTL_LINK_ENCRYPTION_REQ, 0); |
49a630b0 | 1884 | |
401e6cd9 SK |
1885 | ret = intel_de_wait_for_clear(i915, |
1886 | HDCP2_STATUS(i915, cpu_transcoder, | |
69205931 | 1887 | port), |
4cb3b44d | 1888 | LINK_ENCRYPTION_STATUS, |
fbf652bd | 1889 | HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS); |
49a630b0 | 1890 | if (ret == -ETIMEDOUT) |
401e6cd9 | 1891 | drm_dbg_kms(&i915->drm, "Disable Encryption Timedout"); |
49a630b0 R |
1892 | |
1893 | if (hdcp->shim->toggle_signalling) { | |
0b9c9290 SP |
1894 | ret = hdcp->shim->toggle_signalling(dig_port, cpu_transcoder, |
1895 | false); | |
49a630b0 | 1896 | if (ret) { |
401e6cd9 | 1897 | drm_err(&i915->drm, |
65833c46 WK |
1898 | "Failed to disable HDCP signalling. %d\n", |
1899 | ret); | |
49a630b0 R |
1900 | return ret; |
1901 | } | |
1902 | } | |
1903 | ||
1904 | return ret; | |
1905 | } | |
1906 | ||
cb88d1fa R |
1907 | static int |
1908 | hdcp2_propagate_stream_management_info(struct intel_connector *connector) | |
1909 | { | |
1910 | struct drm_i915_private *i915 = to_i915(connector->base.dev); | |
1911 | int i, tries = 3, ret; | |
1912 | ||
1913 | if (!connector->hdcp.is_repeater) | |
1914 | return 0; | |
1915 | ||
1916 | for (i = 0; i < tries; i++) { | |
1917 | ret = _hdcp2_propagate_stream_management_info(connector); | |
1918 | if (!ret) | |
1919 | break; | |
1920 | ||
bff88b1c R |
1921 | /* Lets restart the auth incase of seq_num_m roll over */ |
1922 | if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX) { | |
1923 | drm_dbg_kms(&i915->drm, | |
1924 | "seq_num_m roll over.(%d)\n", ret); | |
1925 | break; | |
1926 | } | |
1927 | ||
cb88d1fa R |
1928 | drm_dbg_kms(&i915->drm, |
1929 | "HDCP2 stream management %d of %d Failed.(%d)\n", | |
1930 | i + 1, tries, ret); | |
1931 | } | |
1932 | ||
1933 | return ret; | |
1934 | } | |
1935 | ||
66bd6924 SK |
1936 | static int hdcp2_authenticate_and_encrypt(struct intel_atomic_state *state, |
1937 | struct intel_connector *connector) | |
49a630b0 | 1938 | { |
a6c6eac9 | 1939 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
51279100 | 1940 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
e03187e1 | 1941 | int ret = 0, i, tries = 3; |
49a630b0 | 1942 | |
e03187e1 | 1943 | for (i = 0; i < tries && !dig_port->hdcp_auth_status; i++) { |
49a630b0 | 1944 | ret = hdcp2_authenticate_sink(connector); |
cb88d1fa | 1945 | if (!ret) { |
66bd6924 SK |
1946 | ret = intel_hdcp_prepare_streams(state, connector); |
1947 | if (ret) { | |
1948 | drm_dbg_kms(&i915->drm, | |
1949 | "Prepare stream failed.(%d)\n", | |
1950 | ret); | |
1951 | break; | |
1952 | } | |
3e31d057 | 1953 | |
cb88d1fa R |
1954 | ret = hdcp2_propagate_stream_management_info(connector); |
1955 | if (ret) { | |
1956 | drm_dbg_kms(&i915->drm, | |
1957 | "Stream management failed.(%d)\n", | |
1958 | ret); | |
1959 | break; | |
1960 | } | |
e03187e1 | 1961 | |
cb88d1fa R |
1962 | ret = hdcp2_authenticate_port(connector); |
1963 | if (!ret) | |
1964 | break; | |
1965 | drm_dbg_kms(&i915->drm, "HDCP2 port auth failed.(%d)\n", | |
1966 | ret); | |
1967 | } | |
49a630b0 R |
1968 | |
1969 | /* Clearing the mei hdcp session */ | |
51279100 R |
1970 | drm_dbg_kms(&i915->drm, "HDCP2.2 Auth %d of %d Failed.(%d)\n", |
1971 | i + 1, tries, ret); | |
49a630b0 | 1972 | if (hdcp2_deauthenticate_port(connector) < 0) |
51279100 | 1973 | drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); |
49a630b0 R |
1974 | } |
1975 | ||
899c8762 | 1976 | if (!ret && !dig_port->hdcp_auth_status) { |
49a630b0 R |
1977 | /* |
1978 | * Ensuring the required 200mSec min time interval between | |
1979 | * Session Key Exchange and encryption. | |
1980 | */ | |
1981 | msleep(HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN); | |
1982 | ret = hdcp2_enable_encryption(connector); | |
1983 | if (ret < 0) { | |
51279100 R |
1984 | drm_dbg_kms(&i915->drm, |
1985 | "Encryption Enable Failed.(%d)\n", ret); | |
49a630b0 | 1986 | if (hdcp2_deauthenticate_port(connector) < 0) |
51279100 | 1987 | drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); |
49a630b0 R |
1988 | } |
1989 | } | |
1990 | ||
3a913fa5 AG |
1991 | if (!ret) |
1992 | ret = hdcp2_enable_stream_encryption(connector); | |
899c8762 | 1993 | |
49a630b0 R |
1994 | return ret; |
1995 | } | |
1996 | ||
66bd6924 SK |
1997 | static int _intel_hdcp2_enable(struct intel_atomic_state *state, |
1998 | struct intel_connector *connector) | |
49a630b0 | 1999 | { |
51279100 | 2000 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
49a630b0 R |
2001 | struct intel_hdcp *hdcp = &connector->hdcp; |
2002 | int ret; | |
2003 | ||
4773293b JN |
2004 | drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being enabled. Type: %d\n", |
2005 | connector->base.base.id, connector->base.name, | |
51279100 | 2006 | hdcp->content_type); |
49a630b0 | 2007 | |
66bd6924 | 2008 | ret = hdcp2_authenticate_and_encrypt(state, connector); |
49a630b0 | 2009 | if (ret) { |
51279100 R |
2010 | drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n", |
2011 | hdcp->content_type, ret); | |
49a630b0 R |
2012 | return ret; |
2013 | } | |
2014 | ||
4773293b JN |
2015 | drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] HDCP2.2 is enabled. Type %d\n", |
2016 | connector->base.base.id, connector->base.name, | |
51279100 | 2017 | hdcp->content_type); |
49a630b0 R |
2018 | |
2019 | hdcp->hdcp2_encrypted = true; | |
2020 | return 0; | |
2021 | } | |
2022 | ||
ee912b55 AG |
2023 | static int |
2024 | _intel_hdcp2_disable(struct intel_connector *connector, bool hdcp2_link_recovery) | |
49a630b0 | 2025 | { |
e03187e1 | 2026 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
51279100 | 2027 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
e03187e1 | 2028 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; |
899c8762 | 2029 | struct intel_hdcp *hdcp = &connector->hdcp; |
49a630b0 R |
2030 | int ret; |
2031 | ||
4773293b JN |
2032 | drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] HDCP2.2 is being Disabled\n", |
2033 | connector->base.base.id, connector->base.name); | |
49a630b0 | 2034 | |
899c8762 AG |
2035 | if (hdcp->shim->stream_2_2_encryption) { |
2036 | ret = hdcp->shim->stream_2_2_encryption(connector, false); | |
2037 | if (ret) { | |
4773293b JN |
2038 | drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to disable HDCP 2.2 stream enc\n", |
2039 | connector->base.base.id, connector->base.name); | |
899c8762 AG |
2040 | return ret; |
2041 | } | |
2042 | drm_dbg_kms(&i915->drm, "HDCP 2.2 transcoder: %s stream encryption disabled\n", | |
2043 | transcoder_name(hdcp->stream_transcoder)); | |
899c8762 | 2044 | |
ee912b55 | 2045 | if (dig_port->num_hdcp_streams > 0 && !hdcp2_link_recovery) |
40a6cead AG |
2046 | return 0; |
2047 | } | |
899c8762 | 2048 | |
49a630b0 R |
2049 | ret = hdcp2_disable_encryption(connector); |
2050 | ||
2051 | if (hdcp2_deauthenticate_port(connector) < 0) | |
51279100 | 2052 | drm_dbg_kms(&i915->drm, "Port deauth failed.\n"); |
49a630b0 R |
2053 | |
2054 | connector->hdcp.hdcp2_encrypted = false; | |
e03187e1 AG |
2055 | dig_port->hdcp_auth_status = false; |
2056 | data->k = 0; | |
49a630b0 R |
2057 | |
2058 | return ret; | |
2059 | } | |
2060 | ||
22ce2d94 R |
2061 | /* Implements the Link Integrity Check for HDCP2.2 */ |
2062 | static int intel_hdcp2_check_link(struct intel_connector *connector) | |
2063 | { | |
7801f3b7 | 2064 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
401e6cd9 | 2065 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
22ce2d94 | 2066 | struct intel_hdcp *hdcp = &connector->hdcp; |
7801f3b7 | 2067 | enum port port = dig_port->base.port; |
69205931 | 2068 | enum transcoder cpu_transcoder; |
22ce2d94 R |
2069 | int ret = 0; |
2070 | ||
2071 | mutex_lock(&hdcp->mutex); | |
899c8762 | 2072 | mutex_lock(&dig_port->hdcp_mutex); |
69205931 | 2073 | cpu_transcoder = hdcp->cpu_transcoder; |
22ce2d94 R |
2074 | |
2075 | /* hdcp2_check_link is expected only when HDCP2.2 is Enabled */ | |
2076 | if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED || | |
2077 | !hdcp->hdcp2_encrypted) { | |
2078 | ret = -EINVAL; | |
2079 | goto out; | |
2080 | } | |
2081 | ||
401e6cd9 SK |
2082 | if (drm_WARN_ON(&i915->drm, |
2083 | !intel_hdcp2_in_use(i915, cpu_transcoder, port))) { | |
2084 | drm_err(&i915->drm, | |
65833c46 | 2085 | "HDCP2.2 link stopped the encryption, %x\n", |
401e6cd9 | 2086 | intel_de_read(i915, HDCP2_STATUS(i915, cpu_transcoder, port))); |
22ce2d94 | 2087 | ret = -ENXIO; |
ee912b55 | 2088 | _intel_hdcp2_disable(connector, true); |
a72394e4 SP |
2089 | intel_hdcp_update_value(connector, |
2090 | DRM_MODE_CONTENT_PROTECTION_DESIRED, | |
2091 | true); | |
22ce2d94 R |
2092 | goto out; |
2093 | } | |
2094 | ||
5bd29e32 | 2095 | ret = hdcp->shim->check_2_2_link(dig_port, connector); |
22ce2d94 R |
2096 | if (ret == HDCP_LINK_PROTECTED) { |
2097 | if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { | |
a72394e4 SP |
2098 | intel_hdcp_update_value(connector, |
2099 | DRM_MODE_CONTENT_PROTECTION_ENABLED, | |
2100 | true); | |
22ce2d94 R |
2101 | } |
2102 | goto out; | |
2103 | } | |
2104 | ||
dfe4cbc2 R |
2105 | if (ret == HDCP_TOPOLOGY_CHANGE) { |
2106 | if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) | |
2107 | goto out; | |
2108 | ||
401e6cd9 | 2109 | drm_dbg_kms(&i915->drm, |
65833c46 | 2110 | "HDCP2.2 Downstream topology change\n"); |
dfe4cbc2 | 2111 | } else { |
401e6cd9 | 2112 | drm_dbg_kms(&i915->drm, |
4773293b JN |
2113 | "[CONNECTOR:%d:%s] HDCP2.2 link failed, retrying auth\n", |
2114 | connector->base.base.id, connector->base.name); | |
dfe4cbc2 | 2115 | } |
22ce2d94 | 2116 | |
ee912b55 | 2117 | ret = _intel_hdcp2_disable(connector, true); |
22ce2d94 | 2118 | if (ret) { |
401e6cd9 | 2119 | drm_err(&i915->drm, |
4773293b JN |
2120 | "[CONNECTOR:%d:%s] Failed to disable hdcp2.2 (%d)\n", |
2121 | connector->base.base.id, connector->base.name, ret); | |
a72394e4 SP |
2122 | intel_hdcp_update_value(connector, |
2123 | DRM_MODE_CONTENT_PROTECTION_DESIRED, true); | |
22ce2d94 R |
2124 | goto out; |
2125 | } | |
2126 | ||
47ef55a8 SK |
2127 | intel_hdcp_update_value(connector, |
2128 | DRM_MODE_CONTENT_PROTECTION_DESIRED, true); | |
22ce2d94 | 2129 | out: |
899c8762 | 2130 | mutex_unlock(&dig_port->hdcp_mutex); |
22ce2d94 R |
2131 | mutex_unlock(&hdcp->mutex); |
2132 | return ret; | |
2133 | } | |
2134 | ||
09d56393 R |
2135 | static void intel_hdcp_check_work(struct work_struct *work) |
2136 | { | |
2137 | struct intel_hdcp *hdcp = container_of(to_delayed_work(work), | |
2138 | struct intel_hdcp, | |
2139 | check_work); | |
2140 | struct intel_connector *connector = intel_hdcp_to_connector(hdcp); | |
848a4e5c | 2141 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
09d56393 | 2142 | |
a6597faa SP |
2143 | if (drm_connector_is_unregistered(&connector->base)) |
2144 | return; | |
2145 | ||
22ce2d94 | 2146 | if (!intel_hdcp2_check_link(connector)) |
848a4e5c LC |
2147 | queue_delayed_work(i915->unordered_wq, &hdcp->check_work, |
2148 | DRM_HDCP2_CHECK_PERIOD_MS); | |
22ce2d94 | 2149 | else if (!intel_hdcp_check_link(connector)) |
848a4e5c LC |
2150 | queue_delayed_work(i915->unordered_wq, &hdcp->check_work, |
2151 | DRM_HDCP_CHECK_PERIOD_MS); | |
09d56393 R |
2152 | } |
2153 | ||
9055aac7 R |
2154 | static int i915_hdcp_component_bind(struct device *i915_kdev, |
2155 | struct device *mei_kdev, void *data) | |
2156 | { | |
401e6cd9 | 2157 | struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); |
9055aac7 | 2158 | |
401e6cd9 | 2159 | drm_dbg(&i915->drm, "I915 HDCP comp bind\n"); |
3e36c490 | 2160 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
5c8ec987 SK |
2161 | i915->display.hdcp.arbiter = (struct i915_hdcp_arbiter *)data; |
2162 | i915->display.hdcp.arbiter->hdcp_dev = mei_kdev; | |
3e36c490 | 2163 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
2164 | |
2165 | return 0; | |
2166 | } | |
2167 | ||
2168 | static void i915_hdcp_component_unbind(struct device *i915_kdev, | |
2169 | struct device *mei_kdev, void *data) | |
2170 | { | |
401e6cd9 | 2171 | struct drm_i915_private *i915 = kdev_to_i915(i915_kdev); |
9055aac7 | 2172 | |
401e6cd9 | 2173 | drm_dbg(&i915->drm, "I915 HDCP comp unbind\n"); |
3e36c490 | 2174 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
5c8ec987 | 2175 | i915->display.hdcp.arbiter = NULL; |
3e36c490 | 2176 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
2177 | } |
2178 | ||
4f73dc7a | 2179 | static const struct component_ops i915_hdcp_ops = { |
9055aac7 R |
2180 | .bind = i915_hdcp_component_bind, |
2181 | .unbind = i915_hdcp_component_unbind, | |
2182 | }; | |
2183 | ||
4f73dc7a | 2184 | static enum hdcp_ddi intel_get_hdcp_ddi_index(enum port port) |
0dcceb35 R |
2185 | { |
2186 | switch (port) { | |
2187 | case PORT_A: | |
4f73dc7a | 2188 | return HDCP_DDI_A; |
0dcceb35 | 2189 | case PORT_B ... PORT_F: |
4f73dc7a | 2190 | return (enum hdcp_ddi)port; |
0dcceb35 | 2191 | default: |
4f73dc7a | 2192 | return HDCP_DDI_INVALID_PORT; |
0dcceb35 R |
2193 | } |
2194 | } | |
2195 | ||
4f73dc7a | 2196 | static enum hdcp_transcoder intel_get_hdcp_transcoder(enum transcoder cpu_transcoder) |
39e2df09 R |
2197 | { |
2198 | switch (cpu_transcoder) { | |
2199 | case TRANSCODER_A ... TRANSCODER_D: | |
4f73dc7a | 2200 | return (enum hdcp_transcoder)(cpu_transcoder | 0x10); |
39e2df09 | 2201 | default: /* eDP, DSI TRANSCODERS are non HDCP capable */ |
4f73dc7a | 2202 | return HDCP_INVALID_TRANSCODER; |
39e2df09 R |
2203 | } |
2204 | } | |
2205 | ||
81b55ef1 | 2206 | static int initialize_hdcp_port_data(struct intel_connector *connector, |
29b283a4 | 2207 | struct intel_digital_port *dig_port, |
81b55ef1 | 2208 | const struct intel_hdcp_shim *shim) |
9055aac7 | 2209 | { |
401e6cd9 | 2210 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
a6c6eac9 | 2211 | struct hdcp_port_data *data = &dig_port->hdcp_port_data; |
29b283a4 | 2212 | enum port port = dig_port->base.port; |
9055aac7 | 2213 | |
401e6cd9 | 2214 | if (DISPLAY_VER(i915) < 12) |
4f73dc7a | 2215 | data->hdcp_ddi = intel_get_hdcp_ddi_index(port); |
39e2df09 R |
2216 | else |
2217 | /* | |
4f73dc7a | 2218 | * As per ME FW API expectation, for GEN 12+, hdcp_ddi is filled |
39e2df09 R |
2219 | * with zero(INVALID PORT index). |
2220 | */ | |
4f73dc7a | 2221 | data->hdcp_ddi = HDCP_DDI_INVALID_PORT; |
39e2df09 R |
2222 | |
2223 | /* | |
4f73dc7a | 2224 | * As associated transcoder is set and modified at modeset, here hdcp_transcoder |
39e2df09 R |
2225 | * is initialized to zero (invalid transcoder index). This will be |
2226 | * retained for <Gen12 forever. | |
2227 | */ | |
4f73dc7a | 2228 | data->hdcp_transcoder = HDCP_INVALID_TRANSCODER; |
39e2df09 | 2229 | |
9055aac7 | 2230 | data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED; |
d456512c | 2231 | data->protocol = (u8)shim->protocol; |
9055aac7 | 2232 | |
9055aac7 | 2233 | if (!data->streams) |
401e6cd9 | 2234 | data->streams = kcalloc(INTEL_NUM_PIPES(i915), |
9055aac7 R |
2235 | sizeof(struct hdcp2_streamid_type), |
2236 | GFP_KERNEL); | |
2237 | if (!data->streams) { | |
401e6cd9 | 2238 | drm_err(&i915->drm, "Out of Memory\n"); |
9055aac7 R |
2239 | return -ENOMEM; |
2240 | } | |
9055aac7 R |
2241 | |
2242 | return 0; | |
2243 | } | |
2244 | ||
401e6cd9 | 2245 | static bool is_hdcp2_supported(struct drm_i915_private *i915) |
04707f97 | 2246 | { |
401e6cd9 | 2247 | if (intel_hdcp_gsc_cs_required(i915)) |
88363177 SK |
2248 | return true; |
2249 | ||
04707f97 R |
2250 | if (!IS_ENABLED(CONFIG_INTEL_MEI_HDCP)) |
2251 | return false; | |
2252 | ||
401e6cd9 SK |
2253 | return (DISPLAY_VER(i915) >= 10 || |
2254 | IS_KABYLAKE(i915) || | |
2255 | IS_COFFEELAKE(i915) || | |
2256 | IS_COMETLAKE(i915)); | |
04707f97 R |
2257 | } |
2258 | ||
401e6cd9 | 2259 | void intel_hdcp_component_init(struct drm_i915_private *i915) |
9055aac7 R |
2260 | { |
2261 | int ret; | |
2262 | ||
401e6cd9 | 2263 | if (!is_hdcp2_supported(i915)) |
9055aac7 R |
2264 | return; |
2265 | ||
3e36c490 | 2266 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
401e6cd9 | 2267 | drm_WARN_ON(&i915->drm, i915->display.hdcp.comp_added); |
9055aac7 | 2268 | |
401e6cd9 | 2269 | i915->display.hdcp.comp_added = true; |
3e36c490 | 2270 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
401e6cd9 SK |
2271 | if (intel_hdcp_gsc_cs_required(i915)) |
2272 | ret = intel_hdcp_gsc_init(i915); | |
88363177 | 2273 | else |
401e6cd9 | 2274 | ret = component_add_typed(i915->drm.dev, &i915_hdcp_ops, |
88363177 SK |
2275 | I915_COMPONENT_HDCP); |
2276 | ||
9055aac7 | 2277 | if (ret < 0) { |
401e6cd9 | 2278 | drm_dbg_kms(&i915->drm, "Failed at fw component add(%d)\n", |
65833c46 | 2279 | ret); |
3e36c490 | 2280 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
401e6cd9 | 2281 | i915->display.hdcp.comp_added = false; |
3e36c490 | 2282 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
2283 | return; |
2284 | } | |
2285 | } | |
2286 | ||
29b283a4 AG |
2287 | static void intel_hdcp2_init(struct intel_connector *connector, |
2288 | struct intel_digital_port *dig_port, | |
d456512c | 2289 | const struct intel_hdcp_shim *shim) |
04707f97 | 2290 | { |
51279100 | 2291 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
04707f97 | 2292 | struct intel_hdcp *hdcp = &connector->hdcp; |
9055aac7 R |
2293 | int ret; |
2294 | ||
29b283a4 | 2295 | ret = initialize_hdcp_port_data(connector, dig_port, shim); |
9055aac7 | 2296 | if (ret) { |
51279100 | 2297 | drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n"); |
9055aac7 R |
2298 | return; |
2299 | } | |
04707f97 | 2300 | |
04707f97 R |
2301 | hdcp->hdcp2_supported = true; |
2302 | } | |
2303 | ||
ee5e5e7a | 2304 | int intel_hdcp_init(struct intel_connector *connector, |
29b283a4 | 2305 | struct intel_digital_port *dig_port, |
d3dacc70 | 2306 | const struct intel_hdcp_shim *shim) |
ee5e5e7a | 2307 | { |
401e6cd9 | 2308 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
d3dacc70 | 2309 | struct intel_hdcp *hdcp = &connector->hdcp; |
ee5e5e7a SP |
2310 | int ret; |
2311 | ||
04707f97 R |
2312 | if (!shim) |
2313 | return -EINVAL; | |
2314 | ||
401e6cd9 | 2315 | if (is_hdcp2_supported(i915)) |
29b283a4 | 2316 | intel_hdcp2_init(connector, dig_port, shim); |
d456512c | 2317 | |
7672dbba R |
2318 | ret = |
2319 | drm_connector_attach_content_protection_property(&connector->base, | |
d456512c R |
2320 | hdcp->hdcp2_supported); |
2321 | if (ret) { | |
2322 | hdcp->hdcp2_supported = false; | |
a6c6eac9 | 2323 | kfree(dig_port->hdcp_port_data.streams); |
ee5e5e7a | 2324 | return ret; |
d456512c | 2325 | } |
ee5e5e7a | 2326 | |
d3dacc70 R |
2327 | hdcp->shim = shim; |
2328 | mutex_init(&hdcp->mutex); | |
2329 | INIT_DELAYED_WORK(&hdcp->check_work, intel_hdcp_check_work); | |
2330 | INIT_WORK(&hdcp->prop_work, intel_hdcp_prop_work); | |
cf9cb35f | 2331 | init_waitqueue_head(&hdcp->cp_irq_queue); |
04707f97 | 2332 | |
ee5e5e7a SP |
2333 | return 0; |
2334 | } | |
2335 | ||
4f60f06a SK |
2336 | static int _intel_hdcp_enable(struct intel_atomic_state *state, |
2337 | struct intel_encoder *encoder, | |
2338 | const struct intel_crtc_state *pipe_config, | |
2339 | const struct drm_connector_state *conn_state) | |
ee5e5e7a | 2340 | { |
401e6cd9 | 2341 | struct drm_i915_private *i915 = to_i915(encoder->base.dev); |
4c4279a8 SK |
2342 | struct intel_connector *connector = |
2343 | to_intel_connector(conn_state->connector); | |
36e5e704 | 2344 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
d3dacc70 | 2345 | struct intel_hdcp *hdcp = &connector->hdcp; |
22ce2d94 | 2346 | unsigned long check_link_interval = DRM_HDCP_CHECK_PERIOD_MS; |
49a630b0 | 2347 | int ret = -EINVAL; |
ee5e5e7a | 2348 | |
d3dacc70 | 2349 | if (!hdcp->shim) |
ee5e5e7a SP |
2350 | return -ENOENT; |
2351 | ||
6c63e6e1 | 2352 | if (!connector->encoder) { |
4773293b JN |
2353 | drm_err(&i915->drm, "[CONNECTOR:%d:%s] encoder is not initialized\n", |
2354 | connector->base.base.id, connector->base.name); | |
6c63e6e1 AG |
2355 | return -ENODEV; |
2356 | } | |
2357 | ||
d3dacc70 | 2358 | mutex_lock(&hdcp->mutex); |
36e5e704 | 2359 | mutex_lock(&dig_port->hdcp_mutex); |
401e6cd9 | 2360 | drm_WARN_ON(&i915->drm, |
bb393dc5 | 2361 | hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED); |
86a12442 | 2362 | hdcp->content_type = (u8)conn_state->hdcp_content_type; |
fc6097d4 AG |
2363 | |
2364 | if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) { | |
2365 | hdcp->cpu_transcoder = pipe_config->mst_master_transcoder; | |
2366 | hdcp->stream_transcoder = pipe_config->cpu_transcoder; | |
2367 | } else { | |
2368 | hdcp->cpu_transcoder = pipe_config->cpu_transcoder; | |
2369 | hdcp->stream_transcoder = INVALID_TRANSCODER; | |
2370 | } | |
ee5e5e7a | 2371 | |
401e6cd9 | 2372 | if (DISPLAY_VER(i915) >= 12) |
4f73dc7a AG |
2373 | dig_port->hdcp_port_data.hdcp_transcoder = |
2374 | intel_get_hdcp_transcoder(hdcp->cpu_transcoder); | |
67e1d5ed | 2375 | |
49a630b0 R |
2376 | /* |
2377 | * Considering that HDCP2.2 is more secure than HDCP1.4, If the setup | |
2378 | * is capable of HDCP2.2, it is preferred to use HDCP2.2. | |
2379 | */ | |
8e754d9e | 2380 | if (intel_hdcp2_get_capability(connector)) { |
66bd6924 SK |
2381 | ret = _intel_hdcp2_enable(state, connector); |
2382 | if (!ret) | |
2383 | check_link_interval = | |
2384 | DRM_HDCP2_CHECK_PERIOD_MS; | |
22ce2d94 | 2385 | } |
49a630b0 | 2386 | |
d456512c R |
2387 | /* |
2388 | * When HDCP2.2 fails and Content Type is not Type1, HDCP1.4 will | |
2389 | * be attempted. | |
2390 | */ | |
8e754d9e | 2391 | if (ret && intel_hdcp_get_capability(connector) && |
d456512c | 2392 | hdcp->content_type != DRM_MODE_HDCP_CONTENT_TYPE1) { |
da36ce00 | 2393 | ret = intel_hdcp1_enable(connector); |
49a630b0 R |
2394 | } |
2395 | ||
2396 | if (!ret) { | |
848a4e5c LC |
2397 | queue_delayed_work(i915->unordered_wq, &hdcp->check_work, |
2398 | check_link_interval); | |
a72394e4 SP |
2399 | intel_hdcp_update_value(connector, |
2400 | DRM_MODE_CONTENT_PROTECTION_ENABLED, | |
2401 | true); | |
49a630b0 | 2402 | } |
ee5e5e7a | 2403 | |
36e5e704 | 2404 | mutex_unlock(&dig_port->hdcp_mutex); |
d3dacc70 | 2405 | mutex_unlock(&hdcp->mutex); |
ee5e5e7a SP |
2406 | return ret; |
2407 | } | |
2408 | ||
4f60f06a SK |
2409 | void intel_hdcp_enable(struct intel_atomic_state *state, |
2410 | struct intel_encoder *encoder, | |
2411 | const struct intel_crtc_state *crtc_state, | |
2412 | const struct drm_connector_state *conn_state) | |
2413 | { | |
3b9bbd79 SK |
2414 | struct intel_connector *connector = |
2415 | to_intel_connector(conn_state->connector); | |
2416 | struct intel_hdcp *hdcp = &connector->hdcp; | |
2417 | ||
2418 | /* | |
2419 | * Enable hdcp if it's desired or if userspace is enabled and | |
2420 | * driver set its state to undesired | |
2421 | */ | |
4f60f06a | 2422 | if (conn_state->content_protection == |
3b9bbd79 SK |
2423 | DRM_MODE_CONTENT_PROTECTION_DESIRED || |
2424 | (conn_state->content_protection == | |
2425 | DRM_MODE_CONTENT_PROTECTION_ENABLED && hdcp->value == | |
2426 | DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) | |
4f60f06a SK |
2427 | _intel_hdcp_enable(state, encoder, crtc_state, conn_state); |
2428 | } | |
2429 | ||
ee5e5e7a SP |
2430 | int intel_hdcp_disable(struct intel_connector *connector) |
2431 | { | |
36e5e704 | 2432 | struct intel_digital_port *dig_port = intel_attached_dig_port(connector); |
d3dacc70 | 2433 | struct intel_hdcp *hdcp = &connector->hdcp; |
01468d6c | 2434 | int ret = 0; |
ee5e5e7a | 2435 | |
d3dacc70 | 2436 | if (!hdcp->shim) |
ee5e5e7a SP |
2437 | return -ENOENT; |
2438 | ||
d3dacc70 | 2439 | mutex_lock(&hdcp->mutex); |
36e5e704 | 2440 | mutex_lock(&dig_port->hdcp_mutex); |
ee5e5e7a | 2441 | |
a1de8685 SP |
2442 | if (hdcp->value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) |
2443 | goto out; | |
ee5e5e7a | 2444 | |
a1de8685 SP |
2445 | intel_hdcp_update_value(connector, |
2446 | DRM_MODE_CONTENT_PROTECTION_UNDESIRED, false); | |
2447 | if (hdcp->hdcp2_encrypted) | |
ee912b55 | 2448 | ret = _intel_hdcp2_disable(connector, false); |
a1de8685 SP |
2449 | else if (hdcp->hdcp_encrypted) |
2450 | ret = _intel_hdcp_disable(connector); | |
2451 | ||
2452 | out: | |
36e5e704 | 2453 | mutex_unlock(&dig_port->hdcp_mutex); |
d3dacc70 R |
2454 | mutex_unlock(&hdcp->mutex); |
2455 | cancel_delayed_work_sync(&hdcp->check_work); | |
ee5e5e7a SP |
2456 | return ret; |
2457 | } | |
2458 | ||
ede9771d VS |
2459 | void intel_hdcp_update_pipe(struct intel_atomic_state *state, |
2460 | struct intel_encoder *encoder, | |
5758e073 JN |
2461 | const struct intel_crtc_state *crtc_state, |
2462 | const struct drm_connector_state *conn_state) | |
2463 | { | |
2464 | struct intel_connector *connector = | |
2465 | to_intel_connector(conn_state->connector); | |
2466 | struct intel_hdcp *hdcp = &connector->hdcp; | |
dbda9580 | 2467 | bool content_protection_type_changed, desired_and_not_enabled = false; |
848a4e5c | 2468 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
dbda9580 AG |
2469 | |
2470 | if (!connector->hdcp.shim) | |
2471 | return; | |
2472 | ||
2473 | content_protection_type_changed = | |
5758e073 JN |
2474 | (conn_state->hdcp_content_type != hdcp->content_type && |
2475 | conn_state->content_protection != | |
2476 | DRM_MODE_CONTENT_PROTECTION_UNDESIRED); | |
2477 | ||
2478 | /* | |
2479 | * During the HDCP encryption session if Type change is requested, | |
2480 | * disable the HDCP and reenable it with new TYPE value. | |
2481 | */ | |
2482 | if (conn_state->content_protection == | |
2483 | DRM_MODE_CONTENT_PROTECTION_UNDESIRED || | |
2484 | content_protection_type_changed) | |
2485 | intel_hdcp_disable(connector); | |
2486 | ||
2487 | /* | |
2488 | * Mark the hdcp state as DESIRED after the hdcp disable of type | |
2489 | * change procedure. | |
2490 | */ | |
2491 | if (content_protection_type_changed) { | |
2492 | mutex_lock(&hdcp->mutex); | |
2493 | hdcp->value = DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
b3c6661a | 2494 | drm_connector_get(&connector->base); |
848a4e5c | 2495 | queue_work(i915->unordered_wq, &hdcp->prop_work); |
5758e073 JN |
2496 | mutex_unlock(&hdcp->mutex); |
2497 | } | |
2498 | ||
2499 | if (conn_state->content_protection == | |
33f9a623 AG |
2500 | DRM_MODE_CONTENT_PROTECTION_DESIRED) { |
2501 | mutex_lock(&hdcp->mutex); | |
2502 | /* Avoid enabling hdcp, if it already ENABLED */ | |
2503 | desired_and_not_enabled = | |
2504 | hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED; | |
2505 | mutex_unlock(&hdcp->mutex); | |
d276e167 AG |
2506 | /* |
2507 | * If HDCP already ENABLED and CP property is DESIRED, schedule | |
2508 | * prop_work to update correct CP property to user space. | |
2509 | */ | |
2510 | if (!desired_and_not_enabled && !content_protection_type_changed) { | |
2511 | drm_connector_get(&connector->base); | |
848a4e5c | 2512 | queue_work(i915->unordered_wq, &hdcp->prop_work); |
d276e167 | 2513 | } |
33f9a623 AG |
2514 | } |
2515 | ||
2516 | if (desired_and_not_enabled || content_protection_type_changed) | |
4f60f06a | 2517 | _intel_hdcp_enable(state, encoder, crtc_state, conn_state); |
5758e073 JN |
2518 | } |
2519 | ||
401e6cd9 | 2520 | void intel_hdcp_component_fini(struct drm_i915_private *i915) |
9055aac7 | 2521 | { |
3e36c490 | 2522 | mutex_lock(&i915->display.hdcp.hdcp_mutex); |
401e6cd9 | 2523 | if (!i915->display.hdcp.comp_added) { |
3e36c490 | 2524 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 R |
2525 | return; |
2526 | } | |
2527 | ||
401e6cd9 | 2528 | i915->display.hdcp.comp_added = false; |
3e36c490 | 2529 | mutex_unlock(&i915->display.hdcp.hdcp_mutex); |
9055aac7 | 2530 | |
401e6cd9 SK |
2531 | if (intel_hdcp_gsc_cs_required(i915)) |
2532 | intel_hdcp_gsc_fini(i915); | |
88363177 | 2533 | else |
401e6cd9 | 2534 | component_del(i915->drm.dev, &i915_hdcp_ops); |
9055aac7 R |
2535 | } |
2536 | ||
2537 | void intel_hdcp_cleanup(struct intel_connector *connector) | |
2538 | { | |
a6597faa SP |
2539 | struct intel_hdcp *hdcp = &connector->hdcp; |
2540 | ||
2541 | if (!hdcp->shim) | |
9055aac7 R |
2542 | return; |
2543 | ||
a6597faa SP |
2544 | /* |
2545 | * If the connector is registered, it's possible userspace could kick | |
2546 | * off another HDCP enable, which would re-spawn the workers. | |
2547 | */ | |
2548 | drm_WARN_ON(connector->base.dev, | |
2549 | connector->base.registration_state == DRM_CONNECTOR_REGISTERED); | |
2550 | ||
2551 | /* | |
2552 | * Now that the connector is not registered, check_work won't be run, | |
2553 | * but cancel any outstanding instances of it | |
2554 | */ | |
2555 | cancel_delayed_work_sync(&hdcp->check_work); | |
2556 | ||
2557 | /* | |
2558 | * We don't cancel prop_work in the same way as check_work since it | |
2559 | * requires connection_mutex which could be held while calling this | |
2560 | * function. Instead, we rely on the connector references grabbed before | |
2561 | * scheduling prop_work to ensure the connector is alive when prop_work | |
2562 | * is run. So if we're in the destroy path (which is where this | |
2563 | * function should be called), we're "guaranteed" that prop_work is not | |
2564 | * active (tl;dr This Should Never Happen). | |
2565 | */ | |
2566 | drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work)); | |
2567 | ||
2568 | mutex_lock(&hdcp->mutex); | |
a6597faa SP |
2569 | hdcp->shim = NULL; |
2570 | mutex_unlock(&hdcp->mutex); | |
9055aac7 R |
2571 | } |
2572 | ||
ee5e5e7a SP |
2573 | void intel_hdcp_atomic_check(struct drm_connector *connector, |
2574 | struct drm_connector_state *old_state, | |
2575 | struct drm_connector_state *new_state) | |
2576 | { | |
739f3abd JN |
2577 | u64 old_cp = old_state->content_protection; |
2578 | u64 new_cp = new_state->content_protection; | |
ee5e5e7a SP |
2579 | struct drm_crtc_state *crtc_state; |
2580 | ||
2581 | if (!new_state->crtc) { | |
2582 | /* | |
2583 | * If the connector is being disabled with CP enabled, mark it | |
2584 | * desired so it's re-enabled when the connector is brought back | |
2585 | */ | |
2586 | if (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) | |
2587 | new_state->content_protection = | |
2588 | DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
2589 | return; | |
2590 | } | |
2591 | ||
33f9a623 AG |
2592 | crtc_state = drm_atomic_get_new_crtc_state(new_state->state, |
2593 | new_state->crtc); | |
2594 | /* | |
2595 | * Fix the HDCP uapi content protection state in case of modeset. | |
2596 | * FIXME: As per HDCP content protection property uapi doc, an uevent() | |
2597 | * need to be sent if there is transition from ENABLED->DESIRED. | |
2598 | */ | |
2599 | if (drm_atomic_crtc_needs_modeset(crtc_state) && | |
2600 | (old_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED && | |
2601 | new_cp != DRM_MODE_CONTENT_PROTECTION_UNDESIRED)) | |
2602 | new_state->content_protection = | |
2603 | DRM_MODE_CONTENT_PROTECTION_DESIRED; | |
2604 | ||
ee5e5e7a SP |
2605 | /* |
2606 | * Nothing to do if the state didn't change, or HDCP was activated since | |
d456512c | 2607 | * the last commit. And also no change in hdcp content type. |
ee5e5e7a SP |
2608 | */ |
2609 | if (old_cp == new_cp || | |
2610 | (old_cp == DRM_MODE_CONTENT_PROTECTION_DESIRED && | |
d456512c R |
2611 | new_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED)) { |
2612 | if (old_state->hdcp_content_type == | |
2613 | new_state->hdcp_content_type) | |
2614 | return; | |
2615 | } | |
ee5e5e7a | 2616 | |
ee5e5e7a SP |
2617 | crtc_state->mode_changed = true; |
2618 | } | |
09d56393 R |
2619 | |
2620 | /* Handles the CP_IRQ raised from the DP HDCP sink */ | |
2621 | void intel_hdcp_handle_cp_irq(struct intel_connector *connector) | |
2622 | { | |
2623 | struct intel_hdcp *hdcp = &connector->hdcp; | |
848a4e5c | 2624 | struct drm_i915_private *i915 = to_i915(connector->base.dev); |
09d56393 R |
2625 | |
2626 | if (!hdcp->shim) | |
2627 | return; | |
2628 | ||
cf9cb35f R |
2629 | atomic_inc(&connector->hdcp.cp_irq_count); |
2630 | wake_up_all(&connector->hdcp.cp_irq_queue); | |
2631 | ||
848a4e5c | 2632 | queue_delayed_work(i915->unordered_wq, &hdcp->check_work, 0); |
09d56393 | 2633 | } |