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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
7d57382e | 29 | #include <linux/delay.h> |
178f736a | 30 | #include <linux/hdmi.h> |
331c201a JN |
31 | #include <linux/i2c.h> |
32 | #include <linux/slab.h> | |
33 | ||
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
2320175f | 37 | #include <drm/drm_hdcp.h> |
15953637 | 38 | #include <drm/drm_scdc_helper.h> |
46d196ec | 39 | #include <drm/intel_lpe_audio.h> |
331c201a | 40 | |
2126d3e9 | 41 | #include "i915_debugfs.h" |
7d57382e | 42 | #include "i915_drv.h" |
12392a74 | 43 | #include "intel_atomic.h" |
331c201a | 44 | #include "intel_audio.h" |
ec7f29ff | 45 | #include "intel_connector.h" |
fdc24cf3 | 46 | #include "intel_ddi.h" |
926b005c | 47 | #include "intel_display_debugfs.h" |
1d455f8d | 48 | #include "intel_display_types.h" |
27fec1f9 | 49 | #include "intel_dp.h" |
b1ad4c39 | 50 | #include "intel_dpio_phy.h" |
8834e365 | 51 | #include "intel_fifo_underrun.h" |
3ce2ea65 | 52 | #include "intel_gmbus.h" |
408bd917 | 53 | #include "intel_hdcp.h" |
0550691d | 54 | #include "intel_hdmi.h" |
dbeb38d9 | 55 | #include "intel_hotplug.h" |
f3e18947 | 56 | #include "intel_lspcon.h" |
44c1220a | 57 | #include "intel_panel.h" |
1d455f8d | 58 | #include "intel_sdvo.h" |
56c5098f | 59 | #include "intel_sideband.h" |
7d57382e | 60 | |
30add22d PZ |
61 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
62 | { | |
da63a9f2 | 63 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
64 | } |
65 | ||
afba0188 SV |
66 | static void |
67 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
68 | { | |
30add22d | 69 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
fac5e23e | 70 | struct drm_i915_private *dev_priv = to_i915(dev); |
faa087c4 | 71 | u32 enabled_bits; |
afba0188 | 72 | |
4f8036a2 | 73 | enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 74 | |
10d4e146 PB |
75 | drm_WARN(dev, |
76 | intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, | |
77 | "HDMI port enabled, expecting disabled\n"); | |
afba0188 SV |
78 | } |
79 | ||
8fc0aa6e ID |
80 | static void |
81 | assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, | |
82 | enum transcoder cpu_transcoder) | |
83 | { | |
10d4e146 PB |
84 | drm_WARN(&dev_priv->drm, |
85 | intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & | |
86 | TRANS_DDI_FUNC_ENABLE, | |
87 | "HDMI transcoder function enabled, expecting disabled\n"); | |
8fc0aa6e ID |
88 | } |
89 | ||
b7d02c3a | 90 | struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder) |
ea5b213a | 91 | { |
da63a9f2 | 92 | struct intel_digital_port *intel_dig_port = |
b7d02c3a VS |
93 | container_of(&encoder->base, struct intel_digital_port, |
94 | base.base); | |
da63a9f2 | 95 | return &intel_dig_port->hdmi; |
ea5b213a CW |
96 | } |
97 | ||
43a6d19c | 98 | static struct intel_hdmi *intel_attached_hdmi(struct intel_connector *connector) |
df0e9248 | 99 | { |
b7d02c3a | 100 | return enc_to_intel_hdmi(intel_attached_encoder(connector)); |
df0e9248 CW |
101 | } |
102 | ||
1d776538 | 103 | static u32 g4x_infoframe_index(unsigned int type) |
3c17fe4b | 104 | { |
178f736a | 105 | switch (type) { |
5cb3c1a1 VS |
106 | case HDMI_PACKET_TYPE_GAMUT_METADATA: |
107 | return VIDEO_DIP_SELECT_GAMUT; | |
178f736a | 108 | case HDMI_INFOFRAME_TYPE_AVI: |
ed517fbb | 109 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 110 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 111 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
112 | case HDMI_INFOFRAME_TYPE_VENDOR: |
113 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 114 | default: |
ffc85dab | 115 | MISSING_CASE(type); |
ed517fbb | 116 | return 0; |
45187ace | 117 | } |
45187ace JB |
118 | } |
119 | ||
1d776538 | 120 | static u32 g4x_infoframe_enable(unsigned int type) |
45187ace | 121 | { |
178f736a | 122 | switch (type) { |
5cb3c1a1 VS |
123 | case HDMI_PACKET_TYPE_GENERAL_CONTROL: |
124 | return VIDEO_DIP_ENABLE_GCP; | |
125 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
126 | return VIDEO_DIP_ENABLE_GAMUT; | |
509efa2b VS |
127 | case DP_SDP_VSC: |
128 | return 0; | |
178f736a | 129 | case HDMI_INFOFRAME_TYPE_AVI: |
ed517fbb | 130 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 131 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 132 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
133 | case HDMI_INFOFRAME_TYPE_VENDOR: |
134 | return VIDEO_DIP_ENABLE_VENDOR; | |
c0560fab US |
135 | case HDMI_INFOFRAME_TYPE_DRM: |
136 | return 0; | |
fa193ff7 | 137 | default: |
ffc85dab | 138 | MISSING_CASE(type); |
ed517fbb | 139 | return 0; |
fa193ff7 | 140 | } |
fa193ff7 PZ |
141 | } |
142 | ||
1d776538 | 143 | static u32 hsw_infoframe_enable(unsigned int type) |
2da8af54 | 144 | { |
178f736a | 145 | switch (type) { |
5cb3c1a1 VS |
146 | case HDMI_PACKET_TYPE_GENERAL_CONTROL: |
147 | return VIDEO_DIP_ENABLE_GCP_HSW; | |
148 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
149 | return VIDEO_DIP_ENABLE_GMP_HSW; | |
1d776538 VS |
150 | case DP_SDP_VSC: |
151 | return VIDEO_DIP_ENABLE_VSC_HSW; | |
4c614831 MN |
152 | case DP_SDP_PPS: |
153 | return VDIP_ENABLE_PPS; | |
178f736a | 154 | case HDMI_INFOFRAME_TYPE_AVI: |
2da8af54 | 155 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 156 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 157 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
158 | case HDMI_INFOFRAME_TYPE_VENDOR: |
159 | return VIDEO_DIP_ENABLE_VS_HSW; | |
44b42ebf VS |
160 | case HDMI_INFOFRAME_TYPE_DRM: |
161 | return VIDEO_DIP_ENABLE_DRM_GLK; | |
2da8af54 | 162 | default: |
ffc85dab | 163 | MISSING_CASE(type); |
2da8af54 PZ |
164 | return 0; |
165 | } | |
166 | } | |
167 | ||
f0f59a00 VS |
168 | static i915_reg_t |
169 | hsw_dip_data_reg(struct drm_i915_private *dev_priv, | |
170 | enum transcoder cpu_transcoder, | |
1d776538 | 171 | unsigned int type, |
f0f59a00 | 172 | int i) |
2da8af54 | 173 | { |
178f736a | 174 | switch (type) { |
5cb3c1a1 VS |
175 | case HDMI_PACKET_TYPE_GAMUT_METADATA: |
176 | return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); | |
1d776538 VS |
177 | case DP_SDP_VSC: |
178 | return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); | |
4c614831 MN |
179 | case DP_SDP_PPS: |
180 | return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); | |
178f736a | 181 | case HDMI_INFOFRAME_TYPE_AVI: |
436c6d4a | 182 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
178f736a | 183 | case HDMI_INFOFRAME_TYPE_SPD: |
436c6d4a | 184 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
c8bb75af | 185 | case HDMI_INFOFRAME_TYPE_VENDOR: |
436c6d4a | 186 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
44b42ebf VS |
187 | case HDMI_INFOFRAME_TYPE_DRM: |
188 | return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); | |
2da8af54 | 189 | default: |
ffc85dab | 190 | MISSING_CASE(type); |
f0f59a00 | 191 | return INVALID_MMIO_REG; |
2da8af54 PZ |
192 | } |
193 | } | |
194 | ||
922430dd GM |
195 | static int hsw_dip_data_size(struct drm_i915_private *dev_priv, |
196 | unsigned int type) | |
4c614831 MN |
197 | { |
198 | switch (type) { | |
199 | case DP_SDP_VSC: | |
200 | return VIDEO_DIP_VSC_DATA_SIZE; | |
201 | case DP_SDP_PPS: | |
202 | return VIDEO_DIP_PPS_DATA_SIZE; | |
922430dd GM |
203 | case HDMI_PACKET_TYPE_GAMUT_METADATA: |
204 | if (INTEL_GEN(dev_priv) >= 11) | |
205 | return VIDEO_DIP_GMP_DATA_SIZE; | |
206 | else | |
207 | return VIDEO_DIP_DATA_SIZE; | |
4c614831 MN |
208 | default: |
209 | return VIDEO_DIP_DATA_SIZE; | |
210 | } | |
211 | } | |
212 | ||
790ea70c | 213 | static void g4x_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 214 | const struct intel_crtc_state *crtc_state, |
1d776538 | 215 | unsigned int type, |
fff63867 | 216 | const void *frame, ssize_t len) |
45187ace | 217 | { |
faa087c4 | 218 | const u32 *data = frame; |
790ea70c | 219 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
8192c82c | 220 | u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); |
178f736a | 221 | int i; |
3c17fe4b | 222 | |
10d4e146 PB |
223 | drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), |
224 | "Writing DIP with CTL reg disabled\n"); | |
822974ae | 225 | |
1d4f85ac | 226 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 227 | val |= g4x_infoframe_index(type); |
22509ec8 | 228 | |
178f736a | 229 | val &= ~g4x_infoframe_enable(type); |
45187ace | 230 | |
8192c82c | 231 | intel_de_write(dev_priv, VIDEO_DIP_CTL, val); |
3c17fe4b | 232 | |
45187ace | 233 | for (i = 0; i < len; i += 4) { |
8192c82c | 234 | intel_de_write(dev_priv, VIDEO_DIP_DATA, *data); |
3c17fe4b DH |
235 | data++; |
236 | } | |
adf00b26 PZ |
237 | /* Write every possible data byte to force correct ECC calculation. */ |
238 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
8192c82c | 239 | intel_de_write(dev_priv, VIDEO_DIP_DATA, 0); |
3c17fe4b | 240 | |
178f736a | 241 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 242 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 243 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 244 | |
8192c82c JN |
245 | intel_de_write(dev_priv, VIDEO_DIP_CTL, val); |
246 | intel_de_posting_read(dev_priv, VIDEO_DIP_CTL); | |
3c17fe4b DH |
247 | } |
248 | ||
f2a10d61 VS |
249 | static void g4x_read_infoframe(struct intel_encoder *encoder, |
250 | const struct intel_crtc_state *crtc_state, | |
251 | unsigned int type, | |
252 | void *frame, ssize_t len) | |
253 | { | |
254 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
255 | u32 val, *data = frame; | |
256 | int i; | |
257 | ||
8192c82c | 258 | val = intel_de_read(dev_priv, VIDEO_DIP_CTL); |
f2a10d61 VS |
259 | |
260 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
261 | val |= g4x_infoframe_index(type); | |
262 | ||
8192c82c | 263 | intel_de_write(dev_priv, VIDEO_DIP_CTL, val); |
f2a10d61 VS |
264 | |
265 | for (i = 0; i < len; i += 4) | |
8192c82c | 266 | *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); |
f2a10d61 VS |
267 | } |
268 | ||
509efa2b | 269 | static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 270 | const struct intel_crtc_state *pipe_config) |
e43823ec | 271 | { |
790ea70c | 272 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
8192c82c | 273 | u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); |
e43823ec | 274 | |
ec1dc603 | 275 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 276 | return 0; |
89a35ecd | 277 | |
790ea70c | 278 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 279 | return 0; |
ec1dc603 VS |
280 | |
281 | return val & (VIDEO_DIP_ENABLE_AVI | | |
282 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
283 | } |
284 | ||
790ea70c | 285 | static void ibx_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 286 | const struct intel_crtc_state *crtc_state, |
1d776538 | 287 | unsigned int type, |
fff63867 | 288 | const void *frame, ssize_t len) |
fdf1250a | 289 | { |
faa087c4 | 290 | const u32 *data = frame; |
790ea70c | 291 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2225f3c6 | 292 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); |
f0f59a00 | 293 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
8192c82c | 294 | u32 val = intel_de_read(dev_priv, reg); |
f0f59a00 | 295 | int i; |
fdf1250a | 296 | |
10d4e146 PB |
297 | drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), |
298 | "Writing DIP with CTL reg disabled\n"); | |
822974ae | 299 | |
fdf1250a | 300 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 301 | val |= g4x_infoframe_index(type); |
fdf1250a | 302 | |
178f736a | 303 | val &= ~g4x_infoframe_enable(type); |
fdf1250a | 304 | |
8192c82c | 305 | intel_de_write(dev_priv, reg, val); |
fdf1250a PZ |
306 | |
307 | for (i = 0; i < len; i += 4) { | |
8192c82c JN |
308 | intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), |
309 | *data); | |
fdf1250a PZ |
310 | data++; |
311 | } | |
adf00b26 PZ |
312 | /* Write every possible data byte to force correct ECC calculation. */ |
313 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
8192c82c | 314 | intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
fdf1250a | 315 | |
178f736a | 316 | val |= g4x_infoframe_enable(type); |
fdf1250a | 317 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 318 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a | 319 | |
8192c82c JN |
320 | intel_de_write(dev_priv, reg, val); |
321 | intel_de_posting_read(dev_priv, reg); | |
fdf1250a PZ |
322 | } |
323 | ||
f2a10d61 VS |
324 | static void ibx_read_infoframe(struct intel_encoder *encoder, |
325 | const struct intel_crtc_state *crtc_state, | |
326 | unsigned int type, | |
327 | void *frame, ssize_t len) | |
328 | { | |
329 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
2225f3c6 | 330 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
f2a10d61 VS |
331 | u32 val, *data = frame; |
332 | int i; | |
333 | ||
8192c82c | 334 | val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); |
f2a10d61 VS |
335 | |
336 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
337 | val |= g4x_infoframe_index(type); | |
338 | ||
8192c82c | 339 | intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); |
f2a10d61 VS |
340 | |
341 | for (i = 0; i < len; i += 4) | |
8192c82c | 342 | *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); |
f2a10d61 VS |
343 | } |
344 | ||
509efa2b | 345 | static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 346 | const struct intel_crtc_state *pipe_config) |
e43823ec | 347 | { |
790ea70c | 348 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2225f3c6 | 349 | enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; |
cda0aaaf | 350 | i915_reg_t reg = TVIDEO_DIP_CTL(pipe); |
8192c82c | 351 | u32 val = intel_de_read(dev_priv, reg); |
e43823ec | 352 | |
ec1dc603 | 353 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 354 | return 0; |
ec1dc603 | 355 | |
790ea70c | 356 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 357 | return 0; |
052f62f7 | 358 | |
ec1dc603 VS |
359 | return val & (VIDEO_DIP_ENABLE_AVI | |
360 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
361 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
362 | } |
363 | ||
790ea70c | 364 | static void cpt_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 365 | const struct intel_crtc_state *crtc_state, |
1d776538 | 366 | unsigned int type, |
fff63867 | 367 | const void *frame, ssize_t len) |
b055c8f3 | 368 | { |
faa087c4 | 369 | const u32 *data = frame; |
790ea70c | 370 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2225f3c6 | 371 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); |
f0f59a00 | 372 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
8192c82c | 373 | u32 val = intel_de_read(dev_priv, reg); |
f0f59a00 | 374 | int i; |
b055c8f3 | 375 | |
10d4e146 PB |
376 | drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), |
377 | "Writing DIP with CTL reg disabled\n"); | |
822974ae | 378 | |
64a8fc01 | 379 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 380 | val |= g4x_infoframe_index(type); |
45187ace | 381 | |
ecb97851 PZ |
382 | /* The DIP control register spec says that we need to update the AVI |
383 | * infoframe without clearing its enable bit */ | |
178f736a DL |
384 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
385 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 386 | |
8192c82c | 387 | intel_de_write(dev_priv, reg, val); |
45187ace JB |
388 | |
389 | for (i = 0; i < len; i += 4) { | |
8192c82c JN |
390 | intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), |
391 | *data); | |
b055c8f3 JB |
392 | data++; |
393 | } | |
adf00b26 PZ |
394 | /* Write every possible data byte to force correct ECC calculation. */ |
395 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
8192c82c | 396 | intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0); |
b055c8f3 | 397 | |
178f736a | 398 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 399 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 400 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 401 | |
8192c82c JN |
402 | intel_de_write(dev_priv, reg, val); |
403 | intel_de_posting_read(dev_priv, reg); | |
45187ace | 404 | } |
90b107c8 | 405 | |
f2a10d61 VS |
406 | static void cpt_read_infoframe(struct intel_encoder *encoder, |
407 | const struct intel_crtc_state *crtc_state, | |
408 | unsigned int type, | |
409 | void *frame, ssize_t len) | |
410 | { | |
411 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
2225f3c6 | 412 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
f2a10d61 VS |
413 | u32 val, *data = frame; |
414 | int i; | |
415 | ||
8192c82c | 416 | val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe)); |
f2a10d61 VS |
417 | |
418 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
419 | val |= g4x_infoframe_index(type); | |
420 | ||
8192c82c | 421 | intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val); |
f2a10d61 VS |
422 | |
423 | for (i = 0; i < len; i += 4) | |
8192c82c | 424 | *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); |
f2a10d61 VS |
425 | } |
426 | ||
509efa2b | 427 | static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 428 | const struct intel_crtc_state *pipe_config) |
e43823ec | 429 | { |
790ea70c | 430 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2225f3c6 | 431 | enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; |
8192c82c | 432 | u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe)); |
e43823ec | 433 | |
ec1dc603 | 434 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 435 | return 0; |
ec1dc603 VS |
436 | |
437 | return val & (VIDEO_DIP_ENABLE_AVI | | |
438 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
439 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
440 | } |
441 | ||
790ea70c | 442 | static void vlv_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 443 | const struct intel_crtc_state *crtc_state, |
1d776538 | 444 | unsigned int type, |
fff63867 | 445 | const void *frame, ssize_t len) |
90b107c8 | 446 | { |
faa087c4 | 447 | const u32 *data = frame; |
790ea70c | 448 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2225f3c6 | 449 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); |
f0f59a00 | 450 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
8192c82c | 451 | u32 val = intel_de_read(dev_priv, reg); |
f0f59a00 | 452 | int i; |
90b107c8 | 453 | |
10d4e146 PB |
454 | drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), |
455 | "Writing DIP with CTL reg disabled\n"); | |
822974ae | 456 | |
90b107c8 | 457 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 458 | val |= g4x_infoframe_index(type); |
22509ec8 | 459 | |
178f736a | 460 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 461 | |
8192c82c | 462 | intel_de_write(dev_priv, reg, val); |
90b107c8 SK |
463 | |
464 | for (i = 0; i < len; i += 4) { | |
8192c82c JN |
465 | intel_de_write(dev_priv, |
466 | VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
90b107c8 SK |
467 | data++; |
468 | } | |
adf00b26 PZ |
469 | /* Write every possible data byte to force correct ECC calculation. */ |
470 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
8192c82c JN |
471 | intel_de_write(dev_priv, |
472 | VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
90b107c8 | 473 | |
178f736a | 474 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 475 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 476 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 477 | |
8192c82c JN |
478 | intel_de_write(dev_priv, reg, val); |
479 | intel_de_posting_read(dev_priv, reg); | |
90b107c8 SK |
480 | } |
481 | ||
f2a10d61 VS |
482 | static void vlv_read_infoframe(struct intel_encoder *encoder, |
483 | const struct intel_crtc_state *crtc_state, | |
484 | unsigned int type, | |
485 | void *frame, ssize_t len) | |
486 | { | |
487 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
2225f3c6 | 488 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
f2a10d61 VS |
489 | u32 val, *data = frame; |
490 | int i; | |
491 | ||
8192c82c | 492 | val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe)); |
f2a10d61 VS |
493 | |
494 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
495 | val |= g4x_infoframe_index(type); | |
496 | ||
8192c82c | 497 | intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val); |
f2a10d61 VS |
498 | |
499 | for (i = 0; i < len; i += 4) | |
8192c82c JN |
500 | *data++ = intel_de_read(dev_priv, |
501 | VLV_TVIDEO_DIP_DATA(crtc->pipe)); | |
f2a10d61 VS |
502 | } |
503 | ||
509efa2b | 504 | static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 505 | const struct intel_crtc_state *pipe_config) |
e43823ec | 506 | { |
790ea70c | 507 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2225f3c6 | 508 | enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; |
8192c82c | 509 | u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe)); |
e43823ec | 510 | |
ec1dc603 | 511 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 512 | return 0; |
ec1dc603 | 513 | |
790ea70c | 514 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 515 | return 0; |
535afa2e | 516 | |
ec1dc603 VS |
517 | return val & (VIDEO_DIP_ENABLE_AVI | |
518 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
519 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
520 | } |
521 | ||
790ea70c | 522 | static void hsw_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 523 | const struct intel_crtc_state *crtc_state, |
1d776538 | 524 | unsigned int type, |
fff63867 | 525 | const void *frame, ssize_t len) |
8c5f5f7c | 526 | { |
faa087c4 | 527 | const u32 *data = frame; |
790ea70c | 528 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 529 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
f0f59a00 | 530 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
4c614831 | 531 | int data_size; |
178f736a | 532 | int i; |
8192c82c | 533 | u32 val = intel_de_read(dev_priv, ctl_reg); |
8c5f5f7c | 534 | |
922430dd GM |
535 | data_size = hsw_dip_data_size(dev_priv, type); |
536 | ||
10d4e146 | 537 | drm_WARN_ON(&dev_priv->drm, len > data_size); |
4c614831 | 538 | |
178f736a | 539 | val &= ~hsw_infoframe_enable(type); |
8192c82c | 540 | intel_de_write(dev_priv, ctl_reg, val); |
2da8af54 PZ |
541 | |
542 | for (i = 0; i < len; i += 4) { | |
8192c82c JN |
543 | intel_de_write(dev_priv, |
544 | hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), | |
545 | *data); | |
2da8af54 PZ |
546 | data++; |
547 | } | |
adf00b26 | 548 | /* Write every possible data byte to force correct ECC calculation. */ |
1d776538 | 549 | for (; i < data_size; i += 4) |
8192c82c JN |
550 | intel_de_write(dev_priv, |
551 | hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2), | |
552 | 0); | |
8c5f5f7c | 553 | |
178f736a | 554 | val |= hsw_infoframe_enable(type); |
8192c82c JN |
555 | intel_de_write(dev_priv, ctl_reg, val); |
556 | intel_de_posting_read(dev_priv, ctl_reg); | |
8c5f5f7c ED |
557 | } |
558 | ||
f2a10d61 VS |
559 | static void hsw_read_infoframe(struct intel_encoder *encoder, |
560 | const struct intel_crtc_state *crtc_state, | |
561 | unsigned int type, | |
562 | void *frame, ssize_t len) | |
563 | { | |
564 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
565 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
566 | u32 val, *data = frame; | |
567 | int i; | |
568 | ||
8192c82c | 569 | val = intel_de_read(dev_priv, HSW_TVIDEO_DIP_CTL(cpu_transcoder)); |
f2a10d61 VS |
570 | |
571 | for (i = 0; i < len; i += 4) | |
8192c82c JN |
572 | *data++ = intel_de_read(dev_priv, |
573 | hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2)); | |
f2a10d61 VS |
574 | } |
575 | ||
509efa2b | 576 | static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 577 | const struct intel_crtc_state *pipe_config) |
e43823ec | 578 | { |
790ea70c | 579 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
8192c82c JN |
580 | u32 val = intel_de_read(dev_priv, |
581 | HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); | |
44b42ebf VS |
582 | u32 mask; |
583 | ||
584 | mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | | |
585 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
586 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
587 | ||
588 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) | |
589 | mask |= VIDEO_DIP_ENABLE_DRM_GLK; | |
e43823ec | 590 | |
44b42ebf | 591 | return val & mask; |
e43823ec JB |
592 | } |
593 | ||
509efa2b VS |
594 | static const u8 infoframe_type_to_idx[] = { |
595 | HDMI_PACKET_TYPE_GENERAL_CONTROL, | |
596 | HDMI_PACKET_TYPE_GAMUT_METADATA, | |
597 | DP_SDP_VSC, | |
598 | HDMI_INFOFRAME_TYPE_AVI, | |
599 | HDMI_INFOFRAME_TYPE_SPD, | |
600 | HDMI_INFOFRAME_TYPE_VENDOR, | |
5a0200f6 | 601 | HDMI_INFOFRAME_TYPE_DRM, |
509efa2b VS |
602 | }; |
603 | ||
fbf08556 VS |
604 | u32 intel_hdmi_infoframe_enable(unsigned int type) |
605 | { | |
606 | int i; | |
607 | ||
608 | for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { | |
609 | if (infoframe_type_to_idx[i] == type) | |
610 | return BIT(i); | |
611 | } | |
612 | ||
613 | return 0; | |
614 | } | |
615 | ||
509efa2b VS |
616 | u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, |
617 | const struct intel_crtc_state *crtc_state) | |
618 | { | |
619 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
b7d02c3a | 620 | struct intel_digital_port *dig_port = enc_to_dig_port(encoder); |
509efa2b VS |
621 | u32 val, ret = 0; |
622 | int i; | |
623 | ||
624 | val = dig_port->infoframes_enabled(encoder, crtc_state); | |
625 | ||
626 | /* map from hardware bits to dip idx */ | |
627 | for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { | |
628 | unsigned int type = infoframe_type_to_idx[i]; | |
629 | ||
630 | if (HAS_DDI(dev_priv)) { | |
631 | if (val & hsw_infoframe_enable(type)) | |
632 | ret |= BIT(i); | |
633 | } else { | |
634 | if (val & g4x_infoframe_enable(type)) | |
635 | ret |= BIT(i); | |
636 | } | |
637 | } | |
638 | ||
639 | return ret; | |
640 | } | |
641 | ||
5adaea79 DL |
642 | /* |
643 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
644 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
645 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
646 | * used for both technologies. | |
647 | * | |
648 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
649 | * DW1: DB3 | DB2 | DB1 | DB0 | |
650 | * DW2: DB7 | DB6 | DB5 | DB4 | |
651 | * DW3: ... | |
652 | * | |
653 | * (HB is Header Byte, DB is Data Byte) | |
654 | * | |
655 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
656 | * trick them by giving an offset into the buffer and moving back the header | |
657 | * bytes by one. | |
658 | */ | |
790ea70c | 659 | static void intel_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 660 | const struct intel_crtc_state *crtc_state, |
fbf08556 VS |
661 | enum hdmi_infoframe_type type, |
662 | const union hdmi_infoframe *frame) | |
45187ace | 663 | { |
b7d02c3a | 664 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
faa087c4 | 665 | u8 buffer[VIDEO_DIP_DATA_SIZE]; |
5adaea79 | 666 | ssize_t len; |
45187ace | 667 | |
fbf08556 VS |
668 | if ((crtc_state->infoframes.enable & |
669 | intel_hdmi_infoframe_enable(type)) == 0) | |
670 | return; | |
671 | ||
3a47ae20 | 672 | if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) |
fbf08556 VS |
673 | return; |
674 | ||
5adaea79 | 675 | /* see comment above for the reason for this offset */ |
fbf08556 | 676 | len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); |
3a47ae20 | 677 | if (drm_WARN_ON(encoder->base.dev, len < 0)) |
5adaea79 DL |
678 | return; |
679 | ||
680 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
121f0ff5 | 681 | memmove(&buffer[0], &buffer[1], 3); |
5adaea79 DL |
682 | buffer[3] = 0; |
683 | len++; | |
45187ace | 684 | |
fbf08556 | 685 | intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); |
45187ace JB |
686 | } |
687 | ||
f2a10d61 VS |
688 | void intel_read_infoframe(struct intel_encoder *encoder, |
689 | const struct intel_crtc_state *crtc_state, | |
690 | enum hdmi_infoframe_type type, | |
691 | union hdmi_infoframe *frame) | |
692 | { | |
b7d02c3a | 693 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
f2a10d61 VS |
694 | u8 buffer[VIDEO_DIP_DATA_SIZE]; |
695 | int ret; | |
696 | ||
697 | if ((crtc_state->infoframes.enable & | |
698 | intel_hdmi_infoframe_enable(type)) == 0) | |
699 | return; | |
700 | ||
701 | intel_dig_port->read_infoframe(encoder, crtc_state, | |
702 | type, buffer, sizeof(buffer)); | |
703 | ||
704 | /* Fill the 'hole' (see big comment above) at position 3 */ | |
705 | memmove(&buffer[1], &buffer[0], 3); | |
706 | ||
707 | /* see comment above for the reason for this offset */ | |
708 | ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); | |
709 | if (ret) { | |
710 | DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type); | |
711 | return; | |
712 | } | |
713 | ||
714 | if (frame->any.type != type) | |
715 | DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", | |
716 | frame->any.type, type); | |
717 | } | |
718 | ||
fbf08556 VS |
719 | static bool |
720 | intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, | |
721 | struct intel_crtc_state *crtc_state, | |
722 | struct drm_connector_state *conn_state) | |
45187ace | 723 | { |
fbf08556 | 724 | struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; |
779c4c28 | 725 | const struct drm_display_mode *adjusted_mode = |
1326a92c | 726 | &crtc_state->hw.adjusted_mode; |
fbf08556 | 727 | struct drm_connector *connector = conn_state->connector; |
5adaea79 | 728 | int ret; |
45187ace | 729 | |
fbf08556 VS |
730 | if (!crtc_state->has_infoframe) |
731 | return true; | |
732 | ||
733 | crtc_state->infoframes.enable |= | |
734 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); | |
735 | ||
736 | ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, | |
13d0add3 | 737 | adjusted_mode); |
fbf08556 VS |
738 | if (ret) |
739 | return false; | |
c846b619 | 740 | |
33b7f3ee | 741 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) |
fbf08556 | 742 | frame->colorspace = HDMI_COLORSPACE_YUV420; |
8c79f844 | 743 | else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) |
fbf08556 | 744 | frame->colorspace = HDMI_COLORSPACE_YUV444; |
2d8bd2bf | 745 | else |
fbf08556 | 746 | frame->colorspace = HDMI_COLORSPACE_RGB; |
2d8bd2bf | 747 | |
0e2f54f8 | 748 | drm_hdmi_avi_infoframe_colorspace(frame, conn_state); |
2d8bd2bf | 749 | |
cae154fc | 750 | /* nonsense combination */ |
3a47ae20 PB |
751 | drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && |
752 | crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); | |
cae154fc | 753 | |
791ad5f1 VS |
754 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { |
755 | drm_hdmi_avi_infoframe_quant_range(frame, connector, | |
756 | adjusted_mode, | |
757 | crtc_state->limited_color_range ? | |
758 | HDMI_QUANTIZATION_RANGE_LIMITED : | |
759 | HDMI_QUANTIZATION_RANGE_FULL); | |
760 | } else { | |
761 | frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; | |
762 | frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; | |
763 | } | |
abedc077 | 764 | |
fbf08556 | 765 | drm_hdmi_avi_infoframe_content_type(frame, conn_state); |
6553b123 | 766 | |
2d8bd2bf | 767 | /* TODO: handle pixel repetition for YCBCR420 outputs */ |
fbf08556 VS |
768 | |
769 | ret = hdmi_avi_infoframe_check(frame); | |
3a47ae20 | 770 | if (drm_WARN_ON(encoder->base.dev, ret)) |
fbf08556 VS |
771 | return false; |
772 | ||
773 | return true; | |
b055c8f3 JB |
774 | } |
775 | ||
fbf08556 VS |
776 | static bool |
777 | intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, | |
778 | struct intel_crtc_state *crtc_state, | |
779 | struct drm_connector_state *conn_state) | |
c0864cb3 | 780 | { |
fbf08556 | 781 | struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; |
5adaea79 DL |
782 | int ret; |
783 | ||
fbf08556 VS |
784 | if (!crtc_state->has_infoframe) |
785 | return true; | |
c0864cb3 | 786 | |
fbf08556 VS |
787 | crtc_state->infoframes.enable |= |
788 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); | |
c0864cb3 | 789 | |
fbf08556 | 790 | ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); |
3a47ae20 | 791 | if (drm_WARN_ON(encoder->base.dev, ret)) |
fbf08556 VS |
792 | return false; |
793 | ||
794 | frame->sdi = HDMI_SPD_SDI_PC; | |
795 | ||
796 | ret = hdmi_spd_infoframe_check(frame); | |
3a47ae20 | 797 | if (drm_WARN_ON(encoder->base.dev, ret)) |
fbf08556 VS |
798 | return false; |
799 | ||
800 | return true; | |
c0864cb3 JB |
801 | } |
802 | ||
fbf08556 VS |
803 | static bool |
804 | intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, | |
805 | struct intel_crtc_state *crtc_state, | |
806 | struct drm_connector_state *conn_state) | |
807 | { | |
808 | struct hdmi_vendor_infoframe *frame = | |
809 | &crtc_state->infoframes.hdmi.vendor.hdmi; | |
810 | const struct drm_display_info *info = | |
811 | &conn_state->connector->display_info; | |
c8bb75af LD |
812 | int ret; |
813 | ||
fbf08556 VS |
814 | if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) |
815 | return true; | |
816 | ||
817 | crtc_state->infoframes.enable |= | |
818 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); | |
819 | ||
820 | ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, | |
f1781e9b | 821 | conn_state->connector, |
1326a92c | 822 | &crtc_state->hw.adjusted_mode); |
3a47ae20 | 823 | if (drm_WARN_ON(encoder->base.dev, ret)) |
fbf08556 | 824 | return false; |
c8bb75af | 825 | |
fbf08556 | 826 | ret = hdmi_vendor_infoframe_check(frame); |
3a47ae20 | 827 | if (drm_WARN_ON(encoder->base.dev, ret)) |
fbf08556 VS |
828 | return false; |
829 | ||
830 | return true; | |
c8bb75af LD |
831 | } |
832 | ||
5a0200f6 US |
833 | static bool |
834 | intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, | |
835 | struct intel_crtc_state *crtc_state, | |
836 | struct drm_connector_state *conn_state) | |
837 | { | |
838 | struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; | |
839 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
840 | int ret; | |
841 | ||
842 | if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))) | |
843 | return true; | |
844 | ||
845 | if (!crtc_state->has_infoframe) | |
846 | return true; | |
847 | ||
848 | if (!conn_state->hdr_output_metadata) | |
849 | return true; | |
850 | ||
851 | crtc_state->infoframes.enable |= | |
852 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM); | |
853 | ||
854 | ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state); | |
855 | if (ret < 0) { | |
856 | DRM_DEBUG_KMS("couldn't set HDR metadata in infoframe\n"); | |
857 | return false; | |
858 | } | |
859 | ||
860 | ret = hdmi_drm_infoframe_check(frame); | |
10d4e146 | 861 | if (drm_WARN_ON(&dev_priv->drm, ret)) |
5a0200f6 US |
862 | return false; |
863 | ||
864 | return true; | |
865 | } | |
866 | ||
790ea70c | 867 | static void g4x_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 868 | bool enable, |
ac240288 ML |
869 | const struct intel_crtc_state *crtc_state, |
870 | const struct drm_connector_state *conn_state) | |
687f4d06 | 871 | { |
790ea70c | 872 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 873 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
69fde0a6 | 874 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
f0f59a00 | 875 | i915_reg_t reg = VIDEO_DIP_CTL; |
8192c82c | 876 | u32 val = intel_de_read(dev_priv, reg); |
790ea70c | 877 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 878 | |
afba0188 SV |
879 | assert_hdmi_port_disabled(intel_hdmi); |
880 | ||
0c14c7f9 PZ |
881 | /* If the registers were not initialized yet, they might be zeroes, |
882 | * which means we're selecting the AVI DIP and we're setting its | |
883 | * frequency to once. This seems to really confuse the HW and make | |
884 | * things stop working (the register spec says the AVI always needs to | |
885 | * be sent every VSync). So here we avoid writing to the register more | |
886 | * than we need and also explicitly select the AVI DIP and explicitly | |
887 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
888 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
889 | * either. */ | |
890 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
891 | ||
6897b4b5 | 892 | if (!enable) { |
0c14c7f9 PZ |
893 | if (!(val & VIDEO_DIP_ENABLE)) |
894 | return; | |
0be6f0c8 VS |
895 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
896 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
897 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
898 | return; | |
899 | } | |
900 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
901 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
8192c82c JN |
902 | intel_de_write(dev_priv, reg, val); |
903 | intel_de_posting_read(dev_priv, reg); | |
0c14c7f9 PZ |
904 | return; |
905 | } | |
906 | ||
72b78c9d PZ |
907 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
908 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
909 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
910 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
911 | return; | |
72b78c9d PZ |
912 | } |
913 | val &= ~VIDEO_DIP_PORT_MASK; | |
914 | val |= port; | |
915 | } | |
916 | ||
822974ae | 917 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
918 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
919 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 920 | |
8192c82c JN |
921 | intel_de_write(dev_priv, reg, val); |
922 | intel_de_posting_read(dev_priv, reg); | |
f278d972 | 923 | |
fbf08556 VS |
924 | intel_write_infoframe(encoder, crtc_state, |
925 | HDMI_INFOFRAME_TYPE_AVI, | |
926 | &crtc_state->infoframes.avi); | |
927 | intel_write_infoframe(encoder, crtc_state, | |
928 | HDMI_INFOFRAME_TYPE_SPD, | |
929 | &crtc_state->infoframes.spd); | |
930 | intel_write_infoframe(encoder, crtc_state, | |
931 | HDMI_INFOFRAME_TYPE_VENDOR, | |
932 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
933 | } |
934 | ||
12aa3290 VS |
935 | /* |
936 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
937 | * | |
938 | * From HDMI specification 1.4a: | |
939 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
940 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
941 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
942 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
943 | * phase of 0 | |
944 | */ | |
945 | static bool gcp_default_phase_possible(int pipe_bpp, | |
946 | const struct drm_display_mode *mode) | |
947 | { | |
948 | unsigned int pixels_per_group; | |
949 | ||
950 | switch (pipe_bpp) { | |
951 | case 30: | |
952 | /* 4 pixels in 5 clocks */ | |
953 | pixels_per_group = 4; | |
954 | break; | |
955 | case 36: | |
956 | /* 2 pixels in 3 clocks */ | |
957 | pixels_per_group = 2; | |
958 | break; | |
959 | case 48: | |
960 | /* 1 pixel in 2 clocks */ | |
961 | pixels_per_group = 1; | |
962 | break; | |
963 | default: | |
964 | /* phase information not relevant for 8bpc */ | |
965 | return false; | |
966 | } | |
967 | ||
968 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
969 | mode->crtc_htotal % pixels_per_group == 0 && | |
970 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
971 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
972 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
973 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
974 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
975 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
976 | } | |
977 | ||
790ea70c | 978 | static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, |
ac240288 ML |
979 | const struct intel_crtc_state *crtc_state, |
980 | const struct drm_connector_state *conn_state) | |
6d67415f | 981 | { |
790ea70c | 982 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2225f3c6 | 983 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
f0f59a00 | 984 | i915_reg_t reg; |
fbf08556 VS |
985 | |
986 | if ((crtc_state->infoframes.enable & | |
987 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) | |
988 | return false; | |
6d67415f VS |
989 | |
990 | if (HAS_DDI(dev_priv)) | |
ac240288 | 991 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); |
666a4537 | 992 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6d67415f | 993 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
2d1fe073 | 994 | else if (HAS_PCH_SPLIT(dev_priv)) |
6d67415f VS |
995 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
996 | else | |
997 | return false; | |
998 | ||
8192c82c | 999 | intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp); |
fbf08556 VS |
1000 | |
1001 | return true; | |
1002 | } | |
1003 | ||
f2a10d61 VS |
1004 | void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, |
1005 | struct intel_crtc_state *crtc_state) | |
1006 | { | |
1007 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
2225f3c6 | 1008 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
f2a10d61 VS |
1009 | i915_reg_t reg; |
1010 | ||
1011 | if ((crtc_state->infoframes.enable & | |
1012 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) | |
1013 | return; | |
1014 | ||
1015 | if (HAS_DDI(dev_priv)) | |
1016 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); | |
1017 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
1018 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); | |
1019 | else if (HAS_PCH_SPLIT(dev_priv)) | |
1020 | reg = TVIDEO_DIP_GCP(crtc->pipe); | |
1021 | else | |
1022 | return; | |
1023 | ||
8192c82c | 1024 | crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg); |
f2a10d61 VS |
1025 | } |
1026 | ||
fbf08556 VS |
1027 | static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, |
1028 | struct intel_crtc_state *crtc_state, | |
1029 | struct drm_connector_state *conn_state) | |
1030 | { | |
1031 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1032 | ||
1033 | if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) | |
1034 | return; | |
1035 | ||
1036 | crtc_state->infoframes.enable |= | |
1037 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); | |
1038 | ||
05d9c878 CT |
1039 | /* Indicate color indication for deep color mode */ |
1040 | if (crtc_state->pipe_bpp > 24) | |
fbf08556 | 1041 | crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; |
6d67415f | 1042 | |
12aa3290 | 1043 | /* Enable default_phase whenever the display mode is suitably aligned */ |
ac240288 | 1044 | if (gcp_default_phase_possible(crtc_state->pipe_bpp, |
1326a92c | 1045 | &crtc_state->hw.adjusted_mode)) |
fbf08556 | 1046 | crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; |
6d67415f VS |
1047 | } |
1048 | ||
790ea70c | 1049 | static void ibx_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1050 | bool enable, |
ac240288 ML |
1051 | const struct intel_crtc_state *crtc_state, |
1052 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1053 | { |
790ea70c | 1054 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2225f3c6 | 1055 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b7d02c3a | 1056 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
69fde0a6 | 1057 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
f0f59a00 | 1058 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
8192c82c | 1059 | u32 val = intel_de_read(dev_priv, reg); |
790ea70c | 1060 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 1061 | |
afba0188 SV |
1062 | assert_hdmi_port_disabled(intel_hdmi); |
1063 | ||
0c14c7f9 PZ |
1064 | /* See the big comment in g4x_set_infoframes() */ |
1065 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1066 | ||
6897b4b5 | 1067 | if (!enable) { |
0c14c7f9 PZ |
1068 | if (!(val & VIDEO_DIP_ENABLE)) |
1069 | return; | |
0be6f0c8 VS |
1070 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1071 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1072 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
8192c82c JN |
1073 | intel_de_write(dev_priv, reg, val); |
1074 | intel_de_posting_read(dev_priv, reg); | |
0c14c7f9 PZ |
1075 | return; |
1076 | } | |
1077 | ||
72b78c9d | 1078 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
10d4e146 PB |
1079 | drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, |
1080 | "DIP already enabled on port %c\n", | |
1081 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
1082 | val &= ~VIDEO_DIP_PORT_MASK; |
1083 | val |= port; | |
1084 | } | |
1085 | ||
822974ae | 1086 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
1087 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
1088 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1089 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 1090 | |
ac240288 | 1091 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1092 | val |= VIDEO_DIP_ENABLE_GCP; |
1093 | ||
8192c82c JN |
1094 | intel_de_write(dev_priv, reg, val); |
1095 | intel_de_posting_read(dev_priv, reg); | |
f278d972 | 1096 | |
fbf08556 VS |
1097 | intel_write_infoframe(encoder, crtc_state, |
1098 | HDMI_INFOFRAME_TYPE_AVI, | |
1099 | &crtc_state->infoframes.avi); | |
1100 | intel_write_infoframe(encoder, crtc_state, | |
1101 | HDMI_INFOFRAME_TYPE_SPD, | |
1102 | &crtc_state->infoframes.spd); | |
1103 | intel_write_infoframe(encoder, crtc_state, | |
1104 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1105 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1106 | } |
1107 | ||
790ea70c | 1108 | static void cpt_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1109 | bool enable, |
ac240288 ML |
1110 | const struct intel_crtc_state *crtc_state, |
1111 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1112 | { |
790ea70c | 1113 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2225f3c6 | 1114 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b7d02c3a | 1115 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
f0f59a00 | 1116 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
8192c82c | 1117 | u32 val = intel_de_read(dev_priv, reg); |
0c14c7f9 | 1118 | |
afba0188 SV |
1119 | assert_hdmi_port_disabled(intel_hdmi); |
1120 | ||
0c14c7f9 PZ |
1121 | /* See the big comment in g4x_set_infoframes() */ |
1122 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1123 | ||
6897b4b5 | 1124 | if (!enable) { |
0c14c7f9 PZ |
1125 | if (!(val & VIDEO_DIP_ENABLE)) |
1126 | return; | |
0be6f0c8 VS |
1127 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1128 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1129 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
8192c82c JN |
1130 | intel_de_write(dev_priv, reg, val); |
1131 | intel_de_posting_read(dev_priv, reg); | |
0c14c7f9 PZ |
1132 | return; |
1133 | } | |
1134 | ||
822974ae PZ |
1135 | /* Set both together, unset both together: see the spec. */ |
1136 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 1137 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 1138 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 1139 | |
ac240288 | 1140 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1141 | val |= VIDEO_DIP_ENABLE_GCP; |
1142 | ||
8192c82c JN |
1143 | intel_de_write(dev_priv, reg, val); |
1144 | intel_de_posting_read(dev_priv, reg); | |
822974ae | 1145 | |
fbf08556 VS |
1146 | intel_write_infoframe(encoder, crtc_state, |
1147 | HDMI_INFOFRAME_TYPE_AVI, | |
1148 | &crtc_state->infoframes.avi); | |
1149 | intel_write_infoframe(encoder, crtc_state, | |
1150 | HDMI_INFOFRAME_TYPE_SPD, | |
1151 | &crtc_state->infoframes.spd); | |
1152 | intel_write_infoframe(encoder, crtc_state, | |
1153 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1154 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1155 | } |
1156 | ||
790ea70c | 1157 | static void vlv_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1158 | bool enable, |
ac240288 ML |
1159 | const struct intel_crtc_state *crtc_state, |
1160 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1161 | { |
790ea70c | 1162 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2225f3c6 | 1163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b7d02c3a | 1164 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
f0f59a00 | 1165 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
8192c82c | 1166 | u32 val = intel_de_read(dev_priv, reg); |
790ea70c | 1167 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 1168 | |
afba0188 SV |
1169 | assert_hdmi_port_disabled(intel_hdmi); |
1170 | ||
0c14c7f9 PZ |
1171 | /* See the big comment in g4x_set_infoframes() */ |
1172 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1173 | ||
6897b4b5 | 1174 | if (!enable) { |
0c14c7f9 PZ |
1175 | if (!(val & VIDEO_DIP_ENABLE)) |
1176 | return; | |
0be6f0c8 VS |
1177 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1178 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1179 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
8192c82c JN |
1180 | intel_de_write(dev_priv, reg, val); |
1181 | intel_de_posting_read(dev_priv, reg); | |
0c14c7f9 PZ |
1182 | return; |
1183 | } | |
1184 | ||
6a2b8021 | 1185 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
10d4e146 PB |
1186 | drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, |
1187 | "DIP already enabled on port %c\n", | |
1188 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
1189 | val &= ~VIDEO_DIP_PORT_MASK; |
1190 | val |= port; | |
1191 | } | |
1192 | ||
822974ae | 1193 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
1194 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
1195 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1196 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 1197 | |
ac240288 | 1198 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1199 | val |= VIDEO_DIP_ENABLE_GCP; |
1200 | ||
8192c82c JN |
1201 | intel_de_write(dev_priv, reg, val); |
1202 | intel_de_posting_read(dev_priv, reg); | |
822974ae | 1203 | |
fbf08556 VS |
1204 | intel_write_infoframe(encoder, crtc_state, |
1205 | HDMI_INFOFRAME_TYPE_AVI, | |
1206 | &crtc_state->infoframes.avi); | |
1207 | intel_write_infoframe(encoder, crtc_state, | |
1208 | HDMI_INFOFRAME_TYPE_SPD, | |
1209 | &crtc_state->infoframes.spd); | |
1210 | intel_write_infoframe(encoder, crtc_state, | |
1211 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1212 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1213 | } |
1214 | ||
790ea70c | 1215 | static void hsw_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1216 | bool enable, |
ac240288 ML |
1217 | const struct intel_crtc_state *crtc_state, |
1218 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1219 | { |
790ea70c | 1220 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1221 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); |
8192c82c | 1222 | u32 val = intel_de_read(dev_priv, reg); |
0c14c7f9 | 1223 | |
8fc0aa6e ID |
1224 | assert_hdmi_transcoder_func_disabled(dev_priv, |
1225 | crtc_state->cpu_transcoder); | |
afba0188 | 1226 | |
0be6f0c8 VS |
1227 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
1228 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
44b42ebf VS |
1229 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | |
1230 | VIDEO_DIP_ENABLE_DRM_GLK); | |
0be6f0c8 | 1231 | |
6897b4b5 | 1232 | if (!enable) { |
8192c82c JN |
1233 | intel_de_write(dev_priv, reg, val); |
1234 | intel_de_posting_read(dev_priv, reg); | |
0c14c7f9 PZ |
1235 | return; |
1236 | } | |
1237 | ||
ac240288 | 1238 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1239 | val |= VIDEO_DIP_ENABLE_GCP_HSW; |
1240 | ||
8192c82c JN |
1241 | intel_de_write(dev_priv, reg, val); |
1242 | intel_de_posting_read(dev_priv, reg); | |
0dd87d20 | 1243 | |
fbf08556 VS |
1244 | intel_write_infoframe(encoder, crtc_state, |
1245 | HDMI_INFOFRAME_TYPE_AVI, | |
1246 | &crtc_state->infoframes.avi); | |
1247 | intel_write_infoframe(encoder, crtc_state, | |
1248 | HDMI_INFOFRAME_TYPE_SPD, | |
1249 | &crtc_state->infoframes.spd); | |
1250 | intel_write_infoframe(encoder, crtc_state, | |
1251 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1252 | &crtc_state->infoframes.hdmi); | |
5a0200f6 US |
1253 | intel_write_infoframe(encoder, crtc_state, |
1254 | HDMI_INFOFRAME_TYPE_DRM, | |
1255 | &crtc_state->infoframes.drm); | |
687f4d06 PZ |
1256 | } |
1257 | ||
b2ccb822 VS |
1258 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) |
1259 | { | |
1260 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); | |
1261 | struct i2c_adapter *adapter = | |
1262 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
1263 | ||
1264 | if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) | |
1265 | return; | |
1266 | ||
1267 | DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", | |
1268 | enable ? "Enabling" : "Disabling"); | |
1269 | ||
1270 | drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, | |
1271 | adapter, enable); | |
1272 | } | |
1273 | ||
2320175f SP |
1274 | static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, |
1275 | unsigned int offset, void *buffer, size_t size) | |
1276 | { | |
067dde90 | 1277 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
2320175f | 1278 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; |
067dde90 | 1279 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, |
2320175f SP |
1280 | hdmi->ddc_bus); |
1281 | int ret; | |
1282 | u8 start = offset & 0xff; | |
1283 | struct i2c_msg msgs[] = { | |
1284 | { | |
1285 | .addr = DRM_HDCP_DDC_ADDR, | |
1286 | .flags = 0, | |
1287 | .len = 1, | |
1288 | .buf = &start, | |
1289 | }, | |
1290 | { | |
1291 | .addr = DRM_HDCP_DDC_ADDR, | |
1292 | .flags = I2C_M_RD, | |
1293 | .len = size, | |
1294 | .buf = buffer | |
1295 | } | |
1296 | }; | |
1297 | ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); | |
1298 | if (ret == ARRAY_SIZE(msgs)) | |
1299 | return 0; | |
1300 | return ret >= 0 ? -EIO : ret; | |
1301 | } | |
1302 | ||
1303 | static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, | |
1304 | unsigned int offset, void *buffer, size_t size) | |
1305 | { | |
067dde90 | 1306 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
2320175f | 1307 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; |
067dde90 | 1308 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, |
2320175f SP |
1309 | hdmi->ddc_bus); |
1310 | int ret; | |
1311 | u8 *write_buf; | |
1312 | struct i2c_msg msg; | |
1313 | ||
1314 | write_buf = kzalloc(size + 1, GFP_KERNEL); | |
1315 | if (!write_buf) | |
1316 | return -ENOMEM; | |
1317 | ||
1318 | write_buf[0] = offset & 0xff; | |
1319 | memcpy(&write_buf[1], buffer, size); | |
1320 | ||
1321 | msg.addr = DRM_HDCP_DDC_ADDR; | |
1322 | msg.flags = 0, | |
1323 | msg.len = size + 1, | |
1324 | msg.buf = write_buf; | |
1325 | ||
1326 | ret = i2c_transfer(adapter, &msg, 1); | |
1327 | if (ret == 1) | |
1b1b1162 RV |
1328 | ret = 0; |
1329 | else if (ret >= 0) | |
1330 | ret = -EIO; | |
1331 | ||
1332 | kfree(write_buf); | |
1333 | return ret; | |
2320175f SP |
1334 | } |
1335 | ||
1336 | static | |
1337 | int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, | |
1338 | u8 *an) | |
1339 | { | |
067dde90 | 1340 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
2320175f | 1341 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; |
067dde90 | 1342 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915, |
2320175f SP |
1343 | hdmi->ddc_bus); |
1344 | int ret; | |
1345 | ||
1346 | ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, | |
1347 | DRM_HDCP_AN_LEN); | |
1348 | if (ret) { | |
3aae21fc | 1349 | DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret); |
2320175f SP |
1350 | return ret; |
1351 | } | |
1352 | ||
1353 | ret = intel_gmbus_output_aksv(adapter); | |
1354 | if (ret < 0) { | |
3aae21fc | 1355 | DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret); |
2320175f SP |
1356 | return ret; |
1357 | } | |
1358 | return 0; | |
1359 | } | |
1360 | ||
1361 | static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, | |
1362 | u8 *bksv) | |
1363 | { | |
1364 | int ret; | |
1365 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, | |
1366 | DRM_HDCP_KSV_LEN); | |
1367 | if (ret) | |
3aae21fc | 1368 | DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret); |
2320175f SP |
1369 | return ret; |
1370 | } | |
1371 | ||
1372 | static | |
1373 | int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, | |
1374 | u8 *bstatus) | |
1375 | { | |
1376 | int ret; | |
1377 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, | |
1378 | bstatus, DRM_HDCP_BSTATUS_LEN); | |
1379 | if (ret) | |
3aae21fc | 1380 | DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret); |
2320175f SP |
1381 | return ret; |
1382 | } | |
1383 | ||
1384 | static | |
1385 | int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, | |
1386 | bool *repeater_present) | |
1387 | { | |
1388 | int ret; | |
1389 | u8 val; | |
1390 | ||
1391 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); | |
1392 | if (ret) { | |
3aae21fc | 1393 | DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); |
2320175f SP |
1394 | return ret; |
1395 | } | |
1396 | *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; | |
1397 | return 0; | |
1398 | } | |
1399 | ||
1400 | static | |
1401 | int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, | |
1402 | u8 *ri_prime) | |
1403 | { | |
1404 | int ret; | |
1405 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, | |
1406 | ri_prime, DRM_HDCP_RI_LEN); | |
1407 | if (ret) | |
3aae21fc | 1408 | DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret); |
2320175f SP |
1409 | return ret; |
1410 | } | |
1411 | ||
1412 | static | |
1413 | int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, | |
1414 | bool *ksv_ready) | |
1415 | { | |
1416 | int ret; | |
1417 | u8 val; | |
1418 | ||
1419 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); | |
1420 | if (ret) { | |
3aae21fc | 1421 | DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); |
2320175f SP |
1422 | return ret; |
1423 | } | |
1424 | *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; | |
1425 | return 0; | |
1426 | } | |
1427 | ||
1428 | static | |
1429 | int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, | |
1430 | int num_downstream, u8 *ksv_fifo) | |
1431 | { | |
1432 | int ret; | |
1433 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, | |
1434 | ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); | |
1435 | if (ret) { | |
3aae21fc | 1436 | DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret); |
2320175f SP |
1437 | return ret; |
1438 | } | |
1439 | return 0; | |
1440 | } | |
1441 | ||
1442 | static | |
1443 | int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, | |
1444 | int i, u32 *part) | |
1445 | { | |
1446 | int ret; | |
1447 | ||
1448 | if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) | |
1449 | return -EINVAL; | |
1450 | ||
1451 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), | |
1452 | part, DRM_HDCP_V_PRIME_PART_LEN); | |
1453 | if (ret) | |
3aae21fc | 1454 | DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret); |
2320175f SP |
1455 | return ret; |
1456 | } | |
1457 | ||
7412826c R |
1458 | static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) |
1459 | { | |
1460 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); | |
5d1db3f6 | 1461 | struct intel_digital_port *intel_dig_port = intel_attached_dig_port(connector); |
7412826c R |
1462 | struct drm_crtc *crtc = connector->base.state->crtc; |
1463 | struct intel_crtc *intel_crtc = container_of(crtc, | |
1464 | struct intel_crtc, base); | |
1465 | u32 scanline; | |
1466 | int ret; | |
1467 | ||
1468 | for (;;) { | |
8192c82c | 1469 | scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe)); |
7412826c R |
1470 | if (scanline > 100 && scanline < 200) |
1471 | break; | |
1472 | usleep_range(25, 50); | |
1473 | } | |
1474 | ||
1475 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false); | |
1476 | if (ret) { | |
1477 | DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret); | |
1478 | return ret; | |
1479 | } | |
1480 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true); | |
1481 | if (ret) { | |
1482 | DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret); | |
1483 | return ret; | |
1484 | } | |
1485 | ||
1486 | return 0; | |
1487 | } | |
1488 | ||
2320175f SP |
1489 | static |
1490 | int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, | |
1491 | bool enable) | |
1492 | { | |
7412826c R |
1493 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; |
1494 | struct intel_connector *connector = hdmi->attached_connector; | |
1495 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); | |
2320175f SP |
1496 | int ret; |
1497 | ||
1498 | if (!enable) | |
1499 | usleep_range(6, 60); /* Bspec says >= 6us */ | |
1500 | ||
1501 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); | |
1502 | if (ret) { | |
1503 | DRM_ERROR("%s HDCP signalling failed (%d)\n", | |
1504 | enable ? "Enable" : "Disable", ret); | |
1505 | return ret; | |
1506 | } | |
7412826c R |
1507 | |
1508 | /* | |
1509 | * WA: To fix incorrect positioning of the window of | |
1510 | * opportunity and enc_en signalling in KABYLAKE. | |
1511 | */ | |
1512 | if (IS_KABYLAKE(dev_priv) && enable) | |
1513 | return kbl_repositioning_enc_en_signal(connector); | |
1514 | ||
2320175f SP |
1515 | return 0; |
1516 | } | |
1517 | ||
1518 | static | |
1519 | bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) | |
1520 | { | |
067dde90 | 1521 | struct drm_i915_private *i915 = to_i915(intel_dig_port->base.base.dev); |
69205931 R |
1522 | struct intel_connector *connector = |
1523 | intel_dig_port->hdmi.attached_connector; | |
2320175f | 1524 | enum port port = intel_dig_port->base.port; |
69205931 | 1525 | enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; |
2320175f SP |
1526 | int ret; |
1527 | union { | |
1528 | u32 reg; | |
1529 | u8 shim[DRM_HDCP_RI_LEN]; | |
1530 | } ri; | |
1531 | ||
1532 | ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); | |
1533 | if (ret) | |
1534 | return false; | |
1535 | ||
067dde90 | 1536 | intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); |
2320175f SP |
1537 | |
1538 | /* Wait for Ri prime match */ | |
ced63326 OB |
1539 | if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & |
1540 | (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) == | |
2320175f SP |
1541 | (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { |
1542 | DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n", | |
067dde90 | 1543 | intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port))); |
2320175f SP |
1544 | return false; |
1545 | } | |
1546 | return true; | |
1547 | } | |
1548 | ||
67fdd8ea | 1549 | struct hdcp2_hdmi_msg_timeout { |
2d4254e5 | 1550 | u8 msg_id; |
0b7b6966 | 1551 | u16 timeout; |
032048db JN |
1552 | }; |
1553 | ||
67fdd8ea | 1554 | static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = { |
eac03efd VS |
1555 | { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, }, |
1556 | { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, }, | |
1557 | { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, }, | |
1558 | { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, }, | |
1559 | { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, }, | |
032048db | 1560 | }; |
2d4254e5 R |
1561 | |
1562 | static | |
1563 | int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, | |
126d0a94 | 1564 | u8 *rx_status) |
2d4254e5 R |
1565 | { |
1566 | return intel_hdmi_hdcp_read(intel_dig_port, | |
1567 | HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, | |
1568 | rx_status, | |
1569 | HDCP_2_2_HDMI_RXSTATUS_LEN); | |
1570 | } | |
1571 | ||
1572 | static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) | |
1573 | { | |
1574 | int i; | |
1575 | ||
eac03efd VS |
1576 | if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) { |
1577 | if (is_paired) | |
1578 | return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS; | |
1579 | else | |
1580 | return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS; | |
1581 | } | |
1582 | ||
1583 | for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) { | |
1584 | if (hdcp2_msg_timeout[i].msg_id == msg_id) | |
67fdd8ea | 1585 | return hdcp2_msg_timeout[i].timeout; |
eac03efd | 1586 | } |
2d4254e5 R |
1587 | |
1588 | return -EINVAL; | |
1589 | } | |
1590 | ||
1591 | static inline | |
1592 | int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port, | |
1593 | u8 msg_id, bool *msg_ready, | |
1594 | ssize_t *msg_sz) | |
1595 | { | |
1596 | u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; | |
1597 | int ret; | |
1598 | ||
1599 | ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status); | |
1600 | if (ret < 0) { | |
1601 | DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret); | |
1602 | return ret; | |
1603 | } | |
1604 | ||
1605 | *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | | |
1606 | rx_status[0]); | |
1607 | ||
1608 | if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) | |
1609 | *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && | |
1610 | *msg_sz); | |
1611 | else | |
1612 | *msg_ready = *msg_sz; | |
1613 | ||
1614 | return 0; | |
1615 | } | |
1616 | ||
1617 | static ssize_t | |
1618 | intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, | |
1619 | u8 msg_id, bool paired) | |
1620 | { | |
1621 | bool msg_ready = false; | |
1622 | int timeout, ret; | |
1623 | ssize_t msg_sz = 0; | |
1624 | ||
1625 | timeout = get_hdcp2_msg_timeout(msg_id, paired); | |
1626 | if (timeout < 0) | |
1627 | return timeout; | |
1628 | ||
1629 | ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port, | |
1630 | msg_id, &msg_ready, | |
1631 | &msg_sz), | |
1632 | !ret && msg_ready && msg_sz, timeout * 1000, | |
1633 | 1000, 5 * 1000); | |
1634 | if (ret) | |
1635 | DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n", | |
1636 | msg_id, ret, timeout); | |
1637 | ||
1638 | return ret ? ret : msg_sz; | |
1639 | } | |
1640 | ||
1641 | static | |
1642 | int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, | |
1643 | void *buf, size_t size) | |
1644 | { | |
1645 | unsigned int offset; | |
1646 | ||
1647 | offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; | |
1648 | return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size); | |
1649 | } | |
1650 | ||
1651 | static | |
1652 | int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, | |
1653 | u8 msg_id, void *buf, size_t size) | |
1654 | { | |
1655 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1656 | struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; | |
1657 | unsigned int offset; | |
1658 | ssize_t ret; | |
1659 | ||
1660 | ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id, | |
1661 | hdcp->is_paired); | |
1662 | if (ret < 0) | |
1663 | return ret; | |
1664 | ||
1665 | /* | |
1666 | * Available msg size should be equal to or lesser than the | |
1667 | * available buffer. | |
1668 | */ | |
1669 | if (ret > size) { | |
1670 | DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n", | |
1671 | ret, size); | |
1672 | return -1; | |
1673 | } | |
1674 | ||
1675 | offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; | |
1676 | ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret); | |
1677 | if (ret) | |
1678 | DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret); | |
1679 | ||
1680 | return ret; | |
1681 | } | |
1682 | ||
1683 | static | |
1684 | int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) | |
1685 | { | |
1686 | u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; | |
1687 | int ret; | |
1688 | ||
1689 | ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); | |
1690 | if (ret) | |
1691 | return ret; | |
1692 | ||
1693 | /* | |
1694 | * Re-auth request and Link Integrity Failures are represented by | |
1695 | * same bit. i.e reauth_req. | |
1696 | */ | |
1697 | if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) | |
1698 | ret = HDCP_REAUTH_REQUEST; | |
1699 | else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) | |
1700 | ret = HDCP_TOPOLOGY_CHANGE; | |
1701 | ||
1702 | return ret; | |
1703 | } | |
1704 | ||
1705 | static | |
1706 | int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port, | |
1707 | bool *capable) | |
1708 | { | |
1709 | u8 hdcp2_version; | |
1710 | int ret; | |
1711 | ||
1712 | *capable = false; | |
1713 | ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, | |
1714 | &hdcp2_version, sizeof(hdcp2_version)); | |
1715 | if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) | |
1716 | *capable = true; | |
1717 | ||
1718 | return ret; | |
1719 | } | |
1720 | ||
1721 | static inline | |
1722 | enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void) | |
1723 | { | |
1724 | return HDCP_PROTOCOL_HDMI; | |
1725 | } | |
1726 | ||
2320175f SP |
1727 | static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { |
1728 | .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, | |
1729 | .read_bksv = intel_hdmi_hdcp_read_bksv, | |
1730 | .read_bstatus = intel_hdmi_hdcp_read_bstatus, | |
1731 | .repeater_present = intel_hdmi_hdcp_repeater_present, | |
1732 | .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, | |
1733 | .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, | |
1734 | .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, | |
1735 | .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, | |
1736 | .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, | |
1737 | .check_link = intel_hdmi_hdcp_check_link, | |
2d4254e5 R |
1738 | .write_2_2_msg = intel_hdmi_hdcp2_write_msg, |
1739 | .read_2_2_msg = intel_hdmi_hdcp2_read_msg, | |
1740 | .check_2_2_link = intel_hdmi_hdcp2_check_link, | |
1741 | .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, | |
1742 | .protocol = HDCP_PROTOCOL_HDMI, | |
2320175f SP |
1743 | }; |
1744 | ||
ac240288 ML |
1745 | static void intel_hdmi_prepare(struct intel_encoder *encoder, |
1746 | const struct intel_crtc_state *crtc_state) | |
7d57382e | 1747 | { |
c59423a3 | 1748 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1749 | struct drm_i915_private *dev_priv = to_i915(dev); |
2225f3c6 | 1750 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); |
b7d02c3a | 1751 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
1326a92c | 1752 | const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; |
b242b7f7 | 1753 | u32 hdmi_val; |
7d57382e | 1754 | |
b2ccb822 VS |
1755 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
1756 | ||
b242b7f7 | 1757 | hdmi_val = SDVO_ENCODING_HDMI; |
ac240288 | 1758 | if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) |
0f2a2a75 | 1759 | hdmi_val |= HDMI_COLOR_RANGE_16_235; |
b599c0bc | 1760 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 1761 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 1762 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 1763 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 1764 | |
ac240288 | 1765 | if (crtc_state->pipe_bpp > 24) |
4f3a8bc7 | 1766 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 1767 | else |
4f3a8bc7 | 1768 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 1769 | |
ac240288 | 1770 | if (crtc_state->has_hdmi_sink) |
dc0fa718 | 1771 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 1772 | |
6e266956 | 1773 | if (HAS_PCH_CPT(dev_priv)) |
c59423a3 | 1774 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
920a14b2 | 1775 | else if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 1776 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); |
dc0fa718 | 1777 | else |
c59423a3 | 1778 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 1779 | |
8192c82c JN |
1780 | intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val); |
1781 | intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); | |
7d57382e EA |
1782 | } |
1783 | ||
85234cdc SV |
1784 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
1785 | enum pipe *pipe) | |
7d57382e | 1786 | { |
76203467 | 1787 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 1788 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
0e6e0be4 | 1789 | intel_wakeref_t wakeref; |
5b092174 | 1790 | bool ret; |
85234cdc | 1791 | |
0e6e0be4 CW |
1792 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
1793 | encoder->power_domain); | |
1794 | if (!wakeref) | |
6d129bea ID |
1795 | return false; |
1796 | ||
76203467 | 1797 | ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); |
5b092174 | 1798 | |
0e6e0be4 | 1799 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
5b092174 ID |
1800 | |
1801 | return ret; | |
85234cdc SV |
1802 | } |
1803 | ||
045ac3b5 | 1804 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 1805 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 1806 | { |
b7d02c3a | 1807 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
8c875fca | 1808 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1809 | struct drm_i915_private *dev_priv = to_i915(dev); |
045ac3b5 | 1810 | u32 tmp, flags = 0; |
18442d08 | 1811 | int dotclock; |
045ac3b5 | 1812 | |
e1214b95 VS |
1813 | pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); |
1814 | ||
8192c82c | 1815 | tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); |
045ac3b5 JB |
1816 | |
1817 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
1818 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1819 | else | |
1820 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1821 | ||
1822 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
1823 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1824 | else | |
1825 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1826 | ||
6897b4b5 SV |
1827 | if (tmp & HDMI_MODE_SELECT_HDMI) |
1828 | pipe_config->has_hdmi_sink = true; | |
1829 | ||
e5e70d4a VS |
1830 | pipe_config->infoframes.enable |= |
1831 | intel_hdmi_infoframes_enabled(encoder, pipe_config); | |
1832 | ||
1833 | if (pipe_config->infoframes.enable) | |
e43823ec JB |
1834 | pipe_config->has_infoframe = true; |
1835 | ||
dd6090f8 | 1836 | if (tmp & HDMI_AUDIO_ENABLE) |
9ed109a7 SV |
1837 | pipe_config->has_audio = true; |
1838 | ||
6e266956 | 1839 | if (!HAS_PCH_SPLIT(dev_priv) && |
8c875fca VS |
1840 | tmp & HDMI_COLOR_RANGE_16_235) |
1841 | pipe_config->limited_color_range = true; | |
1842 | ||
1326a92c | 1843 | pipe_config->hw.adjusted_mode.flags |= flags; |
18442d08 VS |
1844 | |
1845 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
1846 | dotclock = pipe_config->port_clock * 2 / 3; | |
1847 | else | |
1848 | dotclock = pipe_config->port_clock; | |
1849 | ||
be69a133 VS |
1850 | if (pipe_config->pixel_multiplier) |
1851 | dotclock /= pipe_config->pixel_multiplier; | |
1852 | ||
1326a92c | 1853 | pipe_config->hw.adjusted_mode.crtc_clock = dotclock; |
d4d6279a ACO |
1854 | |
1855 | pipe_config->lane_count = 4; | |
f2a10d61 VS |
1856 | |
1857 | intel_hdmi_read_gcp_infoframe(encoder, pipe_config); | |
1858 | ||
1859 | intel_read_infoframe(encoder, pipe_config, | |
1860 | HDMI_INFOFRAME_TYPE_AVI, | |
1861 | &pipe_config->infoframes.avi); | |
1862 | intel_read_infoframe(encoder, pipe_config, | |
1863 | HDMI_INFOFRAME_TYPE_SPD, | |
1864 | &pipe_config->infoframes.spd); | |
1865 | intel_read_infoframe(encoder, pipe_config, | |
1866 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1867 | &pipe_config->infoframes.hdmi); | |
045ac3b5 JB |
1868 | } |
1869 | ||
df18e721 | 1870 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder, |
5f88a9c6 VS |
1871 | const struct intel_crtc_state *pipe_config, |
1872 | const struct drm_connector_state *conn_state) | |
d1b1589c | 1873 | { |
2225f3c6 | 1874 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
d1b1589c | 1875 | |
3a47ae20 | 1876 | drm_WARN_ON(encoder->base.dev, !pipe_config->has_hdmi_sink); |
d1b1589c VS |
1877 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
1878 | pipe_name(crtc->pipe)); | |
bbf35e9d | 1879 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
d1b1589c VS |
1880 | } |
1881 | ||
fd6bbda9 | 1882 | static void g4x_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1883 | const struct intel_crtc_state *pipe_config, |
1884 | const struct drm_connector_state *conn_state) | |
7d57382e | 1885 | { |
5ab432ef | 1886 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1887 | struct drm_i915_private *dev_priv = to_i915(dev); |
b7d02c3a | 1888 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
1889 | u32 temp; |
1890 | ||
8192c82c | 1891 | temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); |
d8a2d0e0 | 1892 | |
bf868c7d | 1893 | temp |= SDVO_ENABLE; |
df18e721 | 1894 | if (pipe_config->has_audio) |
dd6090f8 | 1895 | temp |= HDMI_AUDIO_ENABLE; |
7a87c289 | 1896 | |
8192c82c JN |
1897 | intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); |
1898 | intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); | |
bf868c7d | 1899 | |
df18e721 ML |
1900 | if (pipe_config->has_audio) |
1901 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
bf868c7d VS |
1902 | } |
1903 | ||
fd6bbda9 | 1904 | static void ibx_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1905 | const struct intel_crtc_state *pipe_config, |
1906 | const struct drm_connector_state *conn_state) | |
bf868c7d VS |
1907 | { |
1908 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1909 | struct drm_i915_private *dev_priv = to_i915(dev); |
b7d02c3a | 1910 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
bf868c7d VS |
1911 | u32 temp; |
1912 | ||
8192c82c | 1913 | temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); |
d8a2d0e0 | 1914 | |
bf868c7d | 1915 | temp |= SDVO_ENABLE; |
ac240288 | 1916 | if (pipe_config->has_audio) |
dd6090f8 | 1917 | temp |= HDMI_AUDIO_ENABLE; |
5ab432ef | 1918 | |
bf868c7d VS |
1919 | /* |
1920 | * HW workaround, need to write this twice for issue | |
1921 | * that may result in first write getting masked. | |
1922 | */ | |
8192c82c JN |
1923 | intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); |
1924 | intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); | |
1925 | intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); | |
1926 | intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); | |
5ab432ef | 1927 | |
bf868c7d VS |
1928 | /* |
1929 | * HW workaround, need to toggle enable bit off and on | |
1930 | * for 12bpc with pixel repeat. | |
1931 | * | |
1932 | * FIXME: BSpec says this should be done at the end of | |
1933 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1934 | */ |
df18e721 ML |
1935 | if (pipe_config->pipe_bpp > 24 && |
1936 | pipe_config->pixel_multiplier > 1) { | |
8192c82c JN |
1937 | intel_de_write(dev_priv, intel_hdmi->hdmi_reg, |
1938 | temp & ~SDVO_ENABLE); | |
1939 | intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); | |
bf868c7d VS |
1940 | |
1941 | /* | |
1942 | * HW workaround, need to write this twice for issue | |
1943 | * that may result in first write getting masked. | |
1944 | */ | |
8192c82c JN |
1945 | intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); |
1946 | intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); | |
1947 | intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); | |
1948 | intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); | |
7d57382e | 1949 | } |
c1dec79a | 1950 | |
df18e721 ML |
1951 | if (pipe_config->has_audio) |
1952 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
d1b1589c VS |
1953 | } |
1954 | ||
fd6bbda9 | 1955 | static void cpt_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1956 | const struct intel_crtc_state *pipe_config, |
1957 | const struct drm_connector_state *conn_state) | |
d1b1589c VS |
1958 | { |
1959 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1960 | struct drm_i915_private *dev_priv = to_i915(dev); |
2225f3c6 | 1961 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); |
b7d02c3a | 1962 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
d1b1589c VS |
1963 | enum pipe pipe = crtc->pipe; |
1964 | u32 temp; | |
1965 | ||
8192c82c | 1966 | temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); |
d1b1589c VS |
1967 | |
1968 | temp |= SDVO_ENABLE; | |
df18e721 | 1969 | if (pipe_config->has_audio) |
dd6090f8 | 1970 | temp |= HDMI_AUDIO_ENABLE; |
d1b1589c VS |
1971 | |
1972 | /* | |
1973 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1974 | * | |
1975 | * The procedure for 12bpc is as follows: | |
1976 | * 1. disable HDMI clock gating | |
1977 | * 2. enable HDMI with 8bpc | |
1978 | * 3. enable HDMI with 12bpc | |
1979 | * 4. enable HDMI clock gating | |
1980 | */ | |
1981 | ||
df18e721 | 1982 | if (pipe_config->pipe_bpp > 24) { |
8192c82c JN |
1983 | intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), |
1984 | intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
d1b1589c VS |
1985 | |
1986 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1987 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1988 | } |
d1b1589c | 1989 | |
8192c82c JN |
1990 | intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); |
1991 | intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); | |
d1b1589c | 1992 | |
df18e721 | 1993 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1994 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1995 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1996 | ||
8192c82c JN |
1997 | intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); |
1998 | intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); | |
d1b1589c | 1999 | |
8192c82c JN |
2000 | intel_de_write(dev_priv, TRANS_CHICKEN1(pipe), |
2001 | intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
d1b1589c VS |
2002 | } |
2003 | ||
df18e721 ML |
2004 | if (pipe_config->has_audio) |
2005 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
b76cf76b | 2006 | } |
89b667f8 | 2007 | |
fd6bbda9 | 2008 | static void vlv_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2009 | const struct intel_crtc_state *pipe_config, |
2010 | const struct drm_connector_state *conn_state) | |
b76cf76b | 2011 | { |
5ab432ef SV |
2012 | } |
2013 | ||
fd6bbda9 | 2014 | static void intel_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2015 | const struct intel_crtc_state *old_crtc_state, |
2016 | const struct drm_connector_state *old_conn_state) | |
5ab432ef SV |
2017 | { |
2018 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2019 | struct drm_i915_private *dev_priv = to_i915(dev); |
b7d02c3a | 2020 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
f99be1b3 VS |
2021 | struct intel_digital_port *intel_dig_port = |
2022 | hdmi_to_dig_port(intel_hdmi); | |
2225f3c6 | 2023 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); |
5ab432ef | 2024 | u32 temp; |
5ab432ef | 2025 | |
8192c82c | 2026 | temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg); |
5ab432ef | 2027 | |
dd6090f8 | 2028 | temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE); |
8192c82c JN |
2029 | intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); |
2030 | intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); | |
1612c8bd VS |
2031 | |
2032 | /* | |
2033 | * HW workaround for IBX, we need to move the port | |
2034 | * to transcoder A after disabling it to allow the | |
2035 | * matching DP port to be enabled on transcoder A. | |
2036 | */ | |
6e266956 | 2037 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { |
0c241d5b VS |
2038 | /* |
2039 | * We get CPU/PCH FIFO underruns on the other pipe when | |
2040 | * doing the workaround. Sweep them under the rug. | |
2041 | */ | |
2042 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
2043 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
2044 | ||
76203467 VS |
2045 | temp &= ~SDVO_PIPE_SEL_MASK; |
2046 | temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); | |
1612c8bd VS |
2047 | /* |
2048 | * HW workaround, need to write this twice for issue | |
2049 | * that may result in first write getting masked. | |
2050 | */ | |
8192c82c JN |
2051 | intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); |
2052 | intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); | |
2053 | intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); | |
2054 | intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); | |
1612c8bd VS |
2055 | |
2056 | temp &= ~SDVO_ENABLE; | |
8192c82c JN |
2057 | intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp); |
2058 | intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg); | |
0c241d5b | 2059 | |
0f0f74bc | 2060 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
2061 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
2062 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1612c8bd | 2063 | } |
6d67415f | 2064 | |
790ea70c VS |
2065 | intel_dig_port->set_infoframes(encoder, |
2066 | false, | |
f99be1b3 | 2067 | old_crtc_state, old_conn_state); |
b2ccb822 VS |
2068 | |
2069 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
7d57382e EA |
2070 | } |
2071 | ||
fd6bbda9 | 2072 | static void g4x_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2073 | const struct intel_crtc_state *old_crtc_state, |
2074 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2075 | { |
df18e721 | 2076 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
2077 | intel_audio_codec_disable(encoder, |
2078 | old_crtc_state, old_conn_state); | |
a4790cec | 2079 | |
fd6bbda9 | 2080 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
2081 | } |
2082 | ||
fd6bbda9 | 2083 | static void pch_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2084 | const struct intel_crtc_state *old_crtc_state, |
2085 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2086 | { |
df18e721 | 2087 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
2088 | intel_audio_codec_disable(encoder, |
2089 | old_crtc_state, old_conn_state); | |
a4790cec VS |
2090 | } |
2091 | ||
fd6bbda9 | 2092 | static void pch_post_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2093 | const struct intel_crtc_state *old_crtc_state, |
2094 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2095 | { |
fd6bbda9 | 2096 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
2097 | } |
2098 | ||
d6038611 | 2099 | static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) |
7d148ef5 | 2100 | { |
d6038611 | 2101 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
d9ee2111 | 2102 | int max_tmds_clock, vbt_max_tmds_clock; |
d6038611 | 2103 | |
9672a69c | 2104 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
d6038611 VS |
2105 | max_tmds_clock = 594000; |
2106 | else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) | |
2107 | max_tmds_clock = 300000; | |
2108 | else if (INTEL_GEN(dev_priv) >= 5) | |
2109 | max_tmds_clock = 225000; | |
7d148ef5 | 2110 | else |
d6038611 VS |
2111 | max_tmds_clock = 165000; |
2112 | ||
d9ee2111 JN |
2113 | vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder); |
2114 | if (vbt_max_tmds_clock) | |
2115 | max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock); | |
d6038611 VS |
2116 | |
2117 | return max_tmds_clock; | |
7d148ef5 SV |
2118 | } |
2119 | ||
b1040461 VS |
2120 | static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, |
2121 | const struct drm_connector_state *conn_state) | |
2122 | { | |
2123 | return hdmi->has_hdmi_sink && | |
2124 | READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; | |
2125 | } | |
2126 | ||
b1ba124d | 2127 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, |
7a5ca19f | 2128 | bool respect_downstream_limits, |
b1040461 | 2129 | bool has_hdmi_sink) |
b1ba124d | 2130 | { |
d6038611 VS |
2131 | struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; |
2132 | int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); | |
b1ba124d VS |
2133 | |
2134 | if (respect_downstream_limits) { | |
8cadab0a VS |
2135 | struct intel_connector *connector = hdmi->attached_connector; |
2136 | const struct drm_display_info *info = &connector->base.display_info; | |
2137 | ||
b1ba124d VS |
2138 | if (hdmi->dp_dual_mode.max_tmds_clock) |
2139 | max_tmds_clock = min(max_tmds_clock, | |
2140 | hdmi->dp_dual_mode.max_tmds_clock); | |
8cadab0a VS |
2141 | |
2142 | if (info->max_tmds_clock) | |
2143 | max_tmds_clock = min(max_tmds_clock, | |
2144 | info->max_tmds_clock); | |
b1040461 | 2145 | else if (!has_hdmi_sink) |
b1ba124d VS |
2146 | max_tmds_clock = min(max_tmds_clock, 165000); |
2147 | } | |
2148 | ||
2149 | return max_tmds_clock; | |
2150 | } | |
2151 | ||
e64e739e VS |
2152 | static enum drm_mode_status |
2153 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
7a5ca19f | 2154 | int clock, bool respect_downstream_limits, |
b1040461 | 2155 | bool has_hdmi_sink) |
e64e739e | 2156 | { |
e2d214ae | 2157 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); |
e64e739e VS |
2158 | |
2159 | if (clock < 25000) | |
2160 | return MODE_CLOCK_LOW; | |
b1040461 VS |
2161 | if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, |
2162 | has_hdmi_sink)) | |
e64e739e VS |
2163 | return MODE_CLOCK_HIGH; |
2164 | ||
5e6ccc0b | 2165 | /* BXT DPLL can't generate 223-240 MHz */ |
cc3f90f0 | 2166 | if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) |
5e6ccc0b VS |
2167 | return MODE_CLOCK_RANGE; |
2168 | ||
2169 | /* CHV DPLL can't generate 216-240 MHz */ | |
e2d214ae | 2170 | if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) |
e64e739e VS |
2171 | return MODE_CLOCK_RANGE; |
2172 | ||
2173 | return MODE_OK; | |
2174 | } | |
2175 | ||
c19de8eb DL |
2176 | static enum drm_mode_status |
2177 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
2178 | struct drm_display_mode *mode) | |
7d57382e | 2179 | { |
43a6d19c | 2180 | struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); |
e64e739e | 2181 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); |
49cff963 | 2182 | struct drm_i915_private *dev_priv = to_i915(dev); |
e64e739e | 2183 | enum drm_mode_status status; |
b1040461 | 2184 | int clock = mode->clock; |
587bf496 | 2185 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
b1040461 | 2186 | bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); |
e64e739e | 2187 | |
e4dd27aa VS |
2188 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
2189 | return MODE_NO_DBLESCAN; | |
2190 | ||
587bf496 MK |
2191 | if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) |
2192 | clock *= 2; | |
2193 | ||
2194 | if (clock > max_dotclk) | |
2195 | return MODE_CLOCK_HIGH; | |
2196 | ||
697c4078 CT |
2197 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
2198 | clock *= 2; | |
2199 | ||
b22ca995 SS |
2200 | if (drm_mode_is_420_only(&connector->display_info, mode)) |
2201 | clock /= 2; | |
2202 | ||
e64e739e | 2203 | /* check if we can do 8bpc */ |
b1040461 | 2204 | status = hdmi_port_clock_valid(hdmi, clock, true, has_hdmi_sink); |
7d57382e | 2205 | |
b1040461 | 2206 | if (has_hdmi_sink) { |
cd9e11a8 | 2207 | /* if we can't do 8bpc we may still be able to do 12bpc */ |
b2ae318a | 2208 | if (status != MODE_OK && !HAS_GMCH(dev_priv)) |
cd9e11a8 | 2209 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, |
b1040461 | 2210 | true, has_hdmi_sink); |
cd9e11a8 RS |
2211 | |
2212 | /* if we can't do 8,12bpc we may still be able to do 10bpc */ | |
2213 | if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) | |
2214 | status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, | |
b1040461 | 2215 | true, has_hdmi_sink); |
cd9e11a8 | 2216 | } |
2d20411e VS |
2217 | if (status != MODE_OK) |
2218 | return status; | |
7d57382e | 2219 | |
2d20411e | 2220 | return intel_mode_valid_max_plane_size(dev_priv, mode); |
7d57382e EA |
2221 | } |
2222 | ||
cd9e11a8 RS |
2223 | static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, |
2224 | int bpc) | |
71800632 | 2225 | { |
c750bdd3 | 2226 | struct drm_i915_private *dev_priv = |
2225f3c6 ML |
2227 | to_i915(crtc_state->uapi.crtc->dev); |
2228 | struct drm_atomic_state *state = crtc_state->uapi.state; | |
c750bdd3 VS |
2229 | struct drm_connector_state *connector_state; |
2230 | struct drm_connector *connector; | |
22dae8a0 | 2231 | const struct drm_display_mode *adjusted_mode = |
1326a92c | 2232 | &crtc_state->hw.adjusted_mode; |
c750bdd3 | 2233 | int i; |
71800632 | 2234 | |
b2ae318a | 2235 | if (HAS_GMCH(dev_priv)) |
71800632 VS |
2236 | return false; |
2237 | ||
cd9e11a8 RS |
2238 | if (bpc == 10 && INTEL_GEN(dev_priv) < 11) |
2239 | return false; | |
2240 | ||
3fad10db | 2241 | if (crtc_state->pipe_bpp < bpc * 3) |
be33be5d VS |
2242 | return false; |
2243 | ||
2244 | if (!crtc_state->has_hdmi_sink) | |
2245 | return false; | |
2246 | ||
71800632 | 2247 | /* |
cd9e11a8 | 2248 | * HDMI deep color affects the clocks, so it's only possible |
71800632 VS |
2249 | * when not cloning with other encoder types. |
2250 | */ | |
c750bdd3 VS |
2251 | if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) |
2252 | return false; | |
2253 | ||
fe5f6b1f | 2254 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
c750bdd3 VS |
2255 | const struct drm_display_info *info = &connector->display_info; |
2256 | ||
2225f3c6 | 2257 | if (connector_state->crtc != crtc_state->uapi.crtc) |
c750bdd3 VS |
2258 | continue; |
2259 | ||
33b7f3ee | 2260 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { |
60436fd4 SS |
2261 | const struct drm_hdmi_info *hdmi = &info->hdmi; |
2262 | ||
cd9e11a8 RS |
2263 | if (bpc == 12 && !(hdmi->y420_dc_modes & |
2264 | DRM_EDID_YCBCR420_DC_36)) | |
2265 | return false; | |
2266 | else if (bpc == 10 && !(hdmi->y420_dc_modes & | |
2267 | DRM_EDID_YCBCR420_DC_30)) | |
60436fd4 SS |
2268 | return false; |
2269 | } else { | |
cd9e11a8 RS |
2270 | if (bpc == 12 && !(info->edid_hdmi_dc_modes & |
2271 | DRM_EDID_HDMI_DC_36)) | |
2272 | return false; | |
2273 | else if (bpc == 10 && !(info->edid_hdmi_dc_modes & | |
2274 | DRM_EDID_HDMI_DC_30)) | |
60436fd4 SS |
2275 | return false; |
2276 | } | |
c750bdd3 VS |
2277 | } |
2278 | ||
1c5fad61 | 2279 | /* Display Wa_1405510057:icl,ehl */ |
22dae8a0 | 2280 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && |
1c5fad61 | 2281 | bpc == 10 && IS_GEN(dev_priv, 11) && |
22dae8a0 RS |
2282 | (adjusted_mode->crtc_hblank_end - |
2283 | adjusted_mode->crtc_hblank_start) % 8 == 2) | |
46649d8b ACO |
2284 | return false; |
2285 | ||
c750bdd3 | 2286 | return true; |
71800632 VS |
2287 | } |
2288 | ||
60436fd4 SS |
2289 | static bool |
2290 | intel_hdmi_ycbcr420_config(struct drm_connector *connector, | |
9e362992 | 2291 | struct intel_crtc_state *config) |
60436fd4 | 2292 | { |
2225f3c6 | 2293 | struct intel_crtc *intel_crtc = to_intel_crtc(config->uapi.crtc); |
e5c05931 | 2294 | |
60436fd4 SS |
2295 | if (!connector->ycbcr_420_allowed) { |
2296 | DRM_ERROR("Platform doesn't support YCBCR420 output\n"); | |
2297 | return false; | |
2298 | } | |
2299 | ||
33b7f3ee | 2300 | config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; |
e5c05931 SS |
2301 | |
2302 | /* YCBCR 420 output conversion needs a scaler */ | |
2303 | if (skl_update_scaler_crtc(config)) { | |
2304 | DRM_DEBUG_KMS("Scaler allocation for output failed\n"); | |
2305 | return false; | |
2306 | } | |
2307 | ||
2308 | intel_pch_panel_fitting(intel_crtc, config, | |
2309 | DRM_MODE_SCALE_FULLSCREEN); | |
2310 | ||
60436fd4 SS |
2311 | return true; |
2312 | } | |
2313 | ||
9e362992 VS |
2314 | static int intel_hdmi_port_clock(int clock, int bpc) |
2315 | { | |
2316 | /* | |
2317 | * Need to adjust the port link by: | |
2318 | * 1.5x for 12bpc | |
2319 | * 1.25x for 10bpc | |
2320 | */ | |
2321 | return clock * bpc / 8; | |
2322 | } | |
2323 | ||
2324 | static int intel_hdmi_compute_bpc(struct intel_encoder *encoder, | |
2325 | struct intel_crtc_state *crtc_state, | |
b1040461 | 2326 | int clock) |
9e362992 | 2327 | { |
b7d02c3a | 2328 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
9e362992 VS |
2329 | int bpc; |
2330 | ||
2331 | for (bpc = 12; bpc >= 10; bpc -= 2) { | |
2332 | if (hdmi_deep_color_possible(crtc_state, bpc) && | |
2333 | hdmi_port_clock_valid(intel_hdmi, | |
2334 | intel_hdmi_port_clock(clock, bpc), | |
b1040461 | 2335 | true, crtc_state->has_hdmi_sink) == MODE_OK) |
9e362992 VS |
2336 | return bpc; |
2337 | } | |
2338 | ||
2339 | return 8; | |
2340 | } | |
2341 | ||
2342 | static int intel_hdmi_compute_clock(struct intel_encoder *encoder, | |
b1040461 | 2343 | struct intel_crtc_state *crtc_state) |
9e362992 | 2344 | { |
b7d02c3a | 2345 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
9e362992 | 2346 | const struct drm_display_mode *adjusted_mode = |
1326a92c | 2347 | &crtc_state->hw.adjusted_mode; |
9e362992 VS |
2348 | int bpc, clock = adjusted_mode->crtc_clock; |
2349 | ||
2350 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) | |
2351 | clock *= 2; | |
2352 | ||
2353 | /* YCBCR420 TMDS rate requirement is half the pixel clock */ | |
2354 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) | |
2355 | clock /= 2; | |
2356 | ||
b1040461 | 2357 | bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock); |
9e362992 VS |
2358 | |
2359 | crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc); | |
2360 | ||
2361 | /* | |
2362 | * pipe_bpp could already be below 8bpc due to | |
2363 | * FDI bandwidth constraints. We shouldn't bump it | |
2364 | * back up to 8bpc in that case. | |
2365 | */ | |
2366 | if (crtc_state->pipe_bpp > bpc * 3) | |
2367 | crtc_state->pipe_bpp = bpc * 3; | |
2368 | ||
2369 | DRM_DEBUG_KMS("picking %d bpc for HDMI output (pipe bpp: %d)\n", | |
2370 | bpc, crtc_state->pipe_bpp); | |
2371 | ||
2372 | if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock, | |
b1040461 | 2373 | false, crtc_state->has_hdmi_sink) != MODE_OK) { |
9e362992 VS |
2374 | DRM_DEBUG_KMS("unsupported HDMI clock (%d kHz), rejecting mode\n", |
2375 | crtc_state->port_clock); | |
2376 | return -EINVAL; | |
2377 | } | |
2378 | ||
2379 | return 0; | |
2380 | } | |
2381 | ||
ba2d08c2 VS |
2382 | static bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state, |
2383 | const struct drm_connector_state *conn_state) | |
2384 | { | |
2385 | const struct intel_digital_connector_state *intel_conn_state = | |
2386 | to_intel_digital_connector_state(conn_state); | |
2387 | const struct drm_display_mode *adjusted_mode = | |
1326a92c | 2388 | &crtc_state->hw.adjusted_mode; |
ba2d08c2 | 2389 | |
cae154fc VS |
2390 | /* |
2391 | * Our YCbCr output is always limited range. | |
2392 | * crtc_state->limited_color_range only applies to RGB, | |
2393 | * and it must never be set for YCbCr or we risk setting | |
2394 | * some conflicting bits in PIPECONF which will mess up | |
2395 | * the colors on the monitor. | |
2396 | */ | |
2397 | if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) | |
2398 | return false; | |
2399 | ||
ba2d08c2 VS |
2400 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
2401 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
2402 | return crtc_state->has_hdmi_sink && | |
2403 | drm_default_rgb_quant_range(adjusted_mode) == | |
2404 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
2405 | } else { | |
2406 | return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; | |
2407 | } | |
2408 | } | |
2409 | ||
204474a6 LP |
2410 | int intel_hdmi_compute_config(struct intel_encoder *encoder, |
2411 | struct intel_crtc_state *pipe_config, | |
2412 | struct drm_connector_state *conn_state) | |
7d57382e | 2413 | { |
b7d02c3a | 2414 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
4f8036a2 | 2415 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1326a92c | 2416 | struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; |
60436fd4 SS |
2417 | struct drm_connector *connector = conn_state->connector; |
2418 | struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; | |
7a5ca19f ML |
2419 | struct intel_digital_connector_state *intel_conn_state = |
2420 | to_intel_digital_connector_state(conn_state); | |
9e362992 | 2421 | int ret; |
3685a8f3 | 2422 | |
e4dd27aa | 2423 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
204474a6 | 2424 | return -EINVAL; |
e4dd27aa | 2425 | |
d9facae6 | 2426 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
b1040461 VS |
2427 | pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi, |
2428 | conn_state); | |
6897b4b5 | 2429 | |
e43823ec JB |
2430 | if (pipe_config->has_hdmi_sink) |
2431 | pipe_config->has_infoframe = true; | |
2432 | ||
9e362992 | 2433 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
697c4078 | 2434 | pipe_config->pixel_multiplier = 2; |
697c4078 | 2435 | |
60436fd4 | 2436 | if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { |
9e362992 | 2437 | if (!intel_hdmi_ycbcr420_config(connector, pipe_config)) { |
60436fd4 | 2438 | DRM_ERROR("Can't support YCBCR420 output\n"); |
204474a6 | 2439 | return -EINVAL; |
60436fd4 SS |
2440 | } |
2441 | } | |
2442 | ||
cae154fc VS |
2443 | pipe_config->limited_color_range = |
2444 | intel_hdmi_limited_color_range(pipe_config, conn_state); | |
2445 | ||
4f8036a2 | 2446 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) |
5bfe2ac0 SV |
2447 | pipe_config->has_pch_encoder = true; |
2448 | ||
7a5ca19f ML |
2449 | if (pipe_config->has_hdmi_sink) { |
2450 | if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
2451 | pipe_config->has_audio = intel_hdmi->has_audio; | |
2452 | else | |
2453 | pipe_config->has_audio = | |
2454 | intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
2455 | } | |
9ed109a7 | 2456 | |
b1040461 | 2457 | ret = intel_hdmi_compute_clock(encoder, pipe_config); |
9e362992 VS |
2458 | if (ret) |
2459 | return ret; | |
325b9d04 | 2460 | |
c504f4df VS |
2461 | if (conn_state->picture_aspect_ratio) |
2462 | adjusted_mode->picture_aspect_ratio = | |
2463 | conn_state->picture_aspect_ratio; | |
28b468a0 | 2464 | |
d4d6279a ACO |
2465 | pipe_config->lane_count = 4; |
2466 | ||
9672a69c RV |
2467 | if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || |
2468 | IS_GEMINILAKE(dev_priv))) { | |
15953637 SS |
2469 | if (scdc->scrambling.low_rates) |
2470 | pipe_config->hdmi_scrambling = true; | |
2471 | ||
2472 | if (pipe_config->port_clock > 340000) { | |
2473 | pipe_config->hdmi_scrambling = true; | |
2474 | pipe_config->hdmi_high_tmds_clock_ratio = true; | |
2475 | } | |
2476 | } | |
2477 | ||
fbf08556 VS |
2478 | intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state); |
2479 | ||
2480 | if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { | |
2481 | DRM_DEBUG_KMS("bad AVI infoframe\n"); | |
2482 | return -EINVAL; | |
2483 | } | |
2484 | ||
2485 | if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { | |
2486 | DRM_DEBUG_KMS("bad SPD infoframe\n"); | |
2487 | return -EINVAL; | |
2488 | } | |
2489 | ||
2490 | if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { | |
2491 | DRM_DEBUG_KMS("bad HDMI infoframe\n"); | |
2492 | return -EINVAL; | |
2493 | } | |
2494 | ||
5a0200f6 US |
2495 | if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) { |
2496 | DRM_DEBUG_KMS("bad DRM infoframe\n"); | |
2497 | return -EINVAL; | |
2498 | } | |
2499 | ||
204474a6 | 2500 | return 0; |
7d57382e EA |
2501 | } |
2502 | ||
953ece69 CW |
2503 | static void |
2504 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 2505 | { |
43a6d19c | 2506 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); |
9dff6af8 | 2507 | |
953ece69 CW |
2508 | intel_hdmi->has_hdmi_sink = false; |
2509 | intel_hdmi->has_audio = false; | |
953ece69 | 2510 | |
b1ba124d VS |
2511 | intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; |
2512 | intel_hdmi->dp_dual_mode.max_tmds_clock = 0; | |
2513 | ||
953ece69 CW |
2514 | kfree(to_intel_connector(connector)->detect_edid); |
2515 | to_intel_connector(connector)->detect_edid = NULL; | |
2516 | } | |
2517 | ||
b1ba124d | 2518 | static void |
d6199256 | 2519 | intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) |
b1ba124d VS |
2520 | { |
2521 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
43a6d19c | 2522 | struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); |
8f4f2797 | 2523 | enum port port = hdmi_to_dig_port(hdmi)->base.port; |
b1ba124d VS |
2524 | struct i2c_adapter *adapter = |
2525 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
2526 | enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); | |
2527 | ||
d6199256 VS |
2528 | /* |
2529 | * Type 1 DVI adaptors are not required to implement any | |
2530 | * registers, so we can't always detect their presence. | |
2531 | * Ideally we should be able to check the state of the | |
2532 | * CONFIG1 pin, but no such luck on our hardware. | |
2533 | * | |
2534 | * The only method left to us is to check the VBT to see | |
2535 | * if the port is a dual mode capable DP port. But let's | |
2536 | * only do that when we sucesfully read the EDID, to avoid | |
2537 | * confusing log messages about DP dual mode adaptors when | |
2538 | * there's nothing connected to the port. | |
2539 | */ | |
2540 | if (type == DRM_DP_DUAL_MODE_UNKNOWN) { | |
30190629 AJ |
2541 | /* An overridden EDID imply that we want this port for testing. |
2542 | * Make sure not to set limits for that port. | |
2543 | */ | |
2544 | if (has_edid && !connector->override_edid && | |
d6199256 VS |
2545 | intel_bios_is_port_dp_dual_mode(dev_priv, port)) { |
2546 | DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); | |
2547 | type = DRM_DP_DUAL_MODE_TYPE1_DVI; | |
2548 | } else { | |
2549 | type = DRM_DP_DUAL_MODE_NONE; | |
2550 | } | |
2551 | } | |
2552 | ||
2553 | if (type == DRM_DP_DUAL_MODE_NONE) | |
b1ba124d VS |
2554 | return; |
2555 | ||
2556 | hdmi->dp_dual_mode.type = type; | |
2557 | hdmi->dp_dual_mode.max_tmds_clock = | |
2558 | drm_dp_dual_mode_max_tmds_clock(type, adapter); | |
2559 | ||
2560 | DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", | |
2561 | drm_dp_get_dual_mode_type_name(type), | |
2562 | hdmi->dp_dual_mode.max_tmds_clock); | |
2563 | } | |
2564 | ||
953ece69 | 2565 | static bool |
23f889bd | 2566 | intel_hdmi_set_edid(struct drm_connector *connector) |
953ece69 CW |
2567 | { |
2568 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
43a6d19c | 2569 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); |
0e6e0be4 | 2570 | intel_wakeref_t wakeref; |
23f889bd | 2571 | struct edid *edid; |
953ece69 | 2572 | bool connected = false; |
cfb926e1 | 2573 | struct i2c_adapter *i2c; |
164c8598 | 2574 | |
0e6e0be4 | 2575 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
671dedd2 | 2576 | |
cfb926e1 SB |
2577 | i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); |
2578 | ||
2579 | edid = drm_get_edid(connector, i2c); | |
2580 | ||
2581 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
2582 | DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
2583 | intel_gmbus_force_bit(i2c, true); | |
2584 | edid = drm_get_edid(connector, i2c); | |
2585 | intel_gmbus_force_bit(i2c, false); | |
2586 | } | |
2ded9e27 | 2587 | |
23f889bd | 2588 | intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); |
b1ba124d | 2589 | |
0e6e0be4 | 2590 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); |
30ad48b7 | 2591 | |
953ece69 CW |
2592 | to_intel_connector(connector)->detect_edid = edid; |
2593 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
953ece69 | 2594 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
7a5ca19f | 2595 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
953ece69 CW |
2596 | |
2597 | connected = true; | |
55b7d6e8 CW |
2598 | } |
2599 | ||
9c229127 NA |
2600 | cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); |
2601 | ||
953ece69 CW |
2602 | return connected; |
2603 | } | |
2604 | ||
8166fcea SV |
2605 | static enum drm_connector_status |
2606 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
953ece69 | 2607 | { |
39d1e234 | 2608 | enum drm_connector_status status = connector_status_disconnected; |
8166fcea | 2609 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
43a6d19c | 2610 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); |
39d1e234 | 2611 | struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; |
0e6e0be4 | 2612 | intel_wakeref_t wakeref; |
953ece69 | 2613 | |
8166fcea SV |
2614 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
2615 | connector->base.id, connector->name); | |
2616 | ||
0e6e0be4 | 2617 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
29bb94bb | 2618 | |
2dd24a9c | 2619 | if (INTEL_GEN(dev_priv) >= 11 && |
39d1e234 PZ |
2620 | !intel_digital_port_connected(encoder)) |
2621 | goto out; | |
2622 | ||
8166fcea | 2623 | intel_hdmi_unset_edid(connector); |
0b5e88dc | 2624 | |
7e732cac | 2625 | if (intel_hdmi_set_edid(connector)) |
953ece69 | 2626 | status = connector_status_connected; |
671dedd2 | 2627 | |
39d1e234 | 2628 | out: |
0e6e0be4 | 2629 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); |
29bb94bb | 2630 | |
9c229127 NA |
2631 | if (status != connector_status_connected) |
2632 | cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); | |
2633 | ||
a8ddac7c ID |
2634 | /* |
2635 | * Make sure the refs for power wells enabled during detect are | |
2636 | * dropped to avoid a new detect cycle triggered by HPD polling. | |
2637 | */ | |
2638 | intel_display_power_flush_work(dev_priv); | |
2639 | ||
2ded9e27 | 2640 | return status; |
7d57382e EA |
2641 | } |
2642 | ||
953ece69 CW |
2643 | static void |
2644 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 2645 | { |
953ece69 CW |
2646 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
2647 | connector->base.id, connector->name); | |
7d57382e | 2648 | |
953ece69 | 2649 | intel_hdmi_unset_edid(connector); |
671dedd2 | 2650 | |
953ece69 CW |
2651 | if (connector->status != connector_status_connected) |
2652 | return; | |
671dedd2 | 2653 | |
23f889bd | 2654 | intel_hdmi_set_edid(connector); |
953ece69 | 2655 | } |
671dedd2 | 2656 | |
953ece69 CW |
2657 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
2658 | { | |
2659 | struct edid *edid; | |
2660 | ||
2661 | edid = to_intel_connector(connector)->detect_edid; | |
2662 | if (edid == NULL) | |
2663 | return 0; | |
671dedd2 | 2664 | |
953ece69 | 2665 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
2666 | } |
2667 | ||
fd6bbda9 | 2668 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2669 | const struct intel_crtc_state *pipe_config, |
2670 | const struct drm_connector_state *conn_state) | |
13732ba7 | 2671 | { |
f99be1b3 | 2672 | struct intel_digital_port *intel_dig_port = |
b7d02c3a | 2673 | enc_to_dig_port(encoder); |
13732ba7 | 2674 | |
ac240288 | 2675 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 2676 | |
790ea70c | 2677 | intel_dig_port->set_infoframes(encoder, |
f99be1b3 VS |
2678 | pipe_config->has_infoframe, |
2679 | pipe_config, conn_state); | |
13732ba7 JB |
2680 | } |
2681 | ||
fd6bbda9 | 2682 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2683 | const struct intel_crtc_state *pipe_config, |
2684 | const struct drm_connector_state *conn_state) | |
89b667f8 | 2685 | { |
b7d02c3a | 2686 | struct intel_digital_port *dport = enc_to_dig_port(encoder); |
2e1029c6 | 2687 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5f68c275 | 2688 | |
2e1029c6 | 2689 | vlv_phy_pre_encoder_enable(encoder, pipe_config); |
b76cf76b | 2690 | |
53d98725 ACO |
2691 | /* HDMI 1.0V-2dB */ |
2692 | vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, | |
2693 | 0x2b247878); | |
2694 | ||
790ea70c | 2695 | dport->set_infoframes(encoder, |
f99be1b3 VS |
2696 | pipe_config->has_infoframe, |
2697 | pipe_config, conn_state); | |
13732ba7 | 2698 | |
fd6bbda9 | 2699 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
b76cf76b | 2700 | |
9b6de0a1 | 2701 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
2702 | } |
2703 | ||
fd6bbda9 | 2704 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2705 | const struct intel_crtc_state *pipe_config, |
2706 | const struct drm_connector_state *conn_state) | |
89b667f8 | 2707 | { |
ac240288 | 2708 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 2709 | |
2e1029c6 | 2710 | vlv_phy_pre_pll_enable(encoder, pipe_config); |
89b667f8 JB |
2711 | } |
2712 | ||
fd6bbda9 | 2713 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2714 | const struct intel_crtc_state *pipe_config, |
2715 | const struct drm_connector_state *conn_state) | |
9197c88b | 2716 | { |
ac240288 | 2717 | intel_hdmi_prepare(encoder, pipe_config); |
625695f8 | 2718 | |
2e1029c6 | 2719 | chv_phy_pre_pll_enable(encoder, pipe_config); |
9197c88b VS |
2720 | } |
2721 | ||
fd6bbda9 | 2722 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2723 | const struct intel_crtc_state *old_crtc_state, |
2724 | const struct drm_connector_state *old_conn_state) | |
d6db995f | 2725 | { |
2e1029c6 | 2726 | chv_phy_post_pll_disable(encoder, old_crtc_state); |
d6db995f VS |
2727 | } |
2728 | ||
fd6bbda9 | 2729 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2730 | const struct intel_crtc_state *old_crtc_state, |
2731 | const struct drm_connector_state *old_conn_state) | |
89b667f8 | 2732 | { |
89b667f8 | 2733 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
2e1029c6 | 2734 | vlv_phy_reset_lanes(encoder, old_crtc_state); |
89b667f8 JB |
2735 | } |
2736 | ||
fd6bbda9 | 2737 | static void chv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2738 | const struct intel_crtc_state *old_crtc_state, |
2739 | const struct drm_connector_state *old_conn_state) | |
580d3811 | 2740 | { |
580d3811 | 2741 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2742 | struct drm_i915_private *dev_priv = to_i915(dev); |
580d3811 | 2743 | |
221c7862 | 2744 | vlv_dpio_get(dev_priv); |
580d3811 | 2745 | |
a8f327fb | 2746 | /* Assert data lane reset */ |
2e1029c6 | 2747 | chv_data_lane_soft_reset(encoder, old_crtc_state, true); |
580d3811 | 2748 | |
221c7862 | 2749 | vlv_dpio_put(dev_priv); |
580d3811 VS |
2750 | } |
2751 | ||
fd6bbda9 | 2752 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2753 | const struct intel_crtc_state *pipe_config, |
2754 | const struct drm_connector_state *conn_state) | |
e4a1d846 | 2755 | { |
b7d02c3a | 2756 | struct intel_digital_port *dport = enc_to_dig_port(encoder); |
e4a1d846 | 2757 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2758 | struct drm_i915_private *dev_priv = to_i915(dev); |
2e523e98 | 2759 | |
2e1029c6 | 2760 | chv_phy_pre_encoder_enable(encoder, pipe_config); |
a02ef3c7 | 2761 | |
e4a1d846 CML |
2762 | /* FIXME: Program the support xxx V-dB */ |
2763 | /* Use 800mV-0dB */ | |
b7fa22d8 | 2764 | chv_set_phy_signal_level(encoder, 128, 102, false); |
e4a1d846 | 2765 | |
790ea70c | 2766 | dport->set_infoframes(encoder, |
f99be1b3 VS |
2767 | pipe_config->has_infoframe, |
2768 | pipe_config, conn_state); | |
b4eb1564 | 2769 | |
fd6bbda9 | 2770 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
e4a1d846 | 2771 | |
9b6de0a1 | 2772 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
b0b33846 VS |
2773 | |
2774 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 2775 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
2776 | } |
2777 | ||
7d09888e OV |
2778 | static struct i2c_adapter * |
2779 | intel_hdmi_get_i2c_adapter(struct drm_connector *connector) | |
2780 | { | |
2781 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
43a6d19c | 2782 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); |
7d09888e OV |
2783 | |
2784 | return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); | |
2785 | } | |
2786 | ||
2787 | static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector) | |
2788 | { | |
2789 | struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); | |
2790 | struct kobject *i2c_kobj = &adapter->dev.kobj; | |
2791 | struct kobject *connector_kobj = &connector->kdev->kobj; | |
2792 | int ret; | |
2793 | ||
2794 | ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name); | |
2795 | if (ret) | |
2796 | DRM_ERROR("Failed to create i2c symlink (%d)\n", ret); | |
2797 | } | |
2798 | ||
2799 | static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector) | |
2800 | { | |
2801 | struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector); | |
2802 | struct kobject *i2c_kobj = &adapter->dev.kobj; | |
2803 | struct kobject *connector_kobj = &connector->kdev->kobj; | |
2804 | ||
2805 | sysfs_remove_link(connector_kobj, i2c_kobj->name); | |
2806 | } | |
2807 | ||
bdc93fe0 R |
2808 | static int |
2809 | intel_hdmi_connector_register(struct drm_connector *connector) | |
2810 | { | |
2811 | int ret; | |
2812 | ||
2813 | ret = intel_connector_register(connector); | |
2814 | if (ret) | |
2815 | return ret; | |
2816 | ||
926b005c | 2817 | intel_connector_debugfs_add(connector); |
bdc93fe0 | 2818 | |
7d09888e OV |
2819 | intel_hdmi_create_i2c_symlink(connector); |
2820 | ||
bdc93fe0 R |
2821 | return ret; |
2822 | } | |
2823 | ||
7d57382e EA |
2824 | static void intel_hdmi_destroy(struct drm_connector *connector) |
2825 | { | |
43a6d19c | 2826 | struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; |
5558f3d5 DM |
2827 | |
2828 | cec_notifier_conn_unregister(n); | |
d4b26e4f JN |
2829 | |
2830 | intel_connector_destroy(connector); | |
7d57382e EA |
2831 | } |
2832 | ||
7d09888e OV |
2833 | static void intel_hdmi_connector_unregister(struct drm_connector *connector) |
2834 | { | |
2835 | intel_hdmi_remove_i2c_symlink(connector); | |
2836 | ||
2837 | intel_connector_unregister(connector); | |
2838 | } | |
2839 | ||
7d57382e | 2840 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
7d57382e | 2841 | .detect = intel_hdmi_detect, |
953ece69 | 2842 | .force = intel_hdmi_force, |
7d57382e | 2843 | .fill_modes = drm_helper_probe_single_connector_modes, |
7a5ca19f ML |
2844 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
2845 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
bdc93fe0 | 2846 | .late_register = intel_hdmi_connector_register, |
7d09888e | 2847 | .early_unregister = intel_hdmi_connector_unregister, |
7d57382e | 2848 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 2849 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
7a5ca19f | 2850 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
7d57382e EA |
2851 | }; |
2852 | ||
2853 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
2854 | .get_modes = intel_hdmi_get_modes, | |
2855 | .mode_valid = intel_hdmi_mode_valid, | |
7a5ca19f | 2856 | .atomic_check = intel_digital_connector_atomic_check, |
7d57382e EA |
2857 | }; |
2858 | ||
7d57382e | 2859 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 2860 | .destroy = intel_encoder_destroy, |
7d57382e EA |
2861 | }; |
2862 | ||
55b7d6e8 CW |
2863 | static void |
2864 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
2865 | { | |
f1a12172 | 2866 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
2f146b78 US |
2867 | struct intel_digital_port *intel_dig_port = |
2868 | hdmi_to_dig_port(intel_hdmi); | |
f1a12172 | 2869 | |
3f43c48d | 2870 | intel_attach_force_audio_property(connector); |
e953fd7b | 2871 | intel_attach_broadcast_rgb_property(connector); |
94a11ddc | 2872 | intel_attach_aspect_ratio_property(connector); |
2f146b78 US |
2873 | |
2874 | /* | |
2875 | * Attach Colorspace property for Non LSPCON based device | |
2876 | * ToDo: This needs to be extended for LSPCON implementation | |
2877 | * as well. Will be implemented separately. | |
2878 | */ | |
2879 | if (!intel_dig_port->lspcon.active) | |
2880 | intel_attach_colorspace_property(connector); | |
2881 | ||
6553b123 | 2882 | drm_connector_attach_content_type_property(connector); |
f1a12172 | 2883 | |
b7bedf31 US |
2884 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
2885 | drm_object_attach_property(&connector->base, | |
2886 | connector->dev->mode_config.hdr_output_metadata_property, 0); | |
2887 | ||
b2ae318a | 2888 | if (!HAS_GMCH(dev_priv)) |
f1a12172 | 2889 | drm_connector_attach_max_bpc_property(connector, 8, 12); |
55b7d6e8 CW |
2890 | } |
2891 | ||
15953637 SS |
2892 | /* |
2893 | * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup | |
2894 | * @encoder: intel_encoder | |
2895 | * @connector: drm_connector | |
2896 | * @high_tmds_clock_ratio = bool to indicate if the function needs to set | |
2897 | * or reset the high tmds clock ratio for scrambling | |
2898 | * @scrambling: bool to Indicate if the function needs to set or reset | |
2899 | * sink scrambling | |
2900 | * | |
2901 | * This function handles scrambling on HDMI 2.0 capable sinks. | |
2902 | * If required clock rate is > 340 Mhz && scrambling is supported by sink | |
2903 | * it enables scrambling. This should be called before enabling the HDMI | |
2904 | * 2.0 port, as the sink can choose to disable the scrambling if it doesn't | |
2905 | * detect a scrambled clock within 100 ms. | |
277ab5ab VS |
2906 | * |
2907 | * Returns: | |
2908 | * True on success, false on failure. | |
15953637 | 2909 | */ |
277ab5ab | 2910 | bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, |
15953637 SS |
2911 | struct drm_connector *connector, |
2912 | bool high_tmds_clock_ratio, | |
2913 | bool scrambling) | |
2914 | { | |
277ab5ab | 2915 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
b7d02c3a | 2916 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
15953637 | 2917 | struct drm_scrambling *sink_scrambling = |
277ab5ab VS |
2918 | &connector->display_info.hdmi.scdc.scrambling; |
2919 | struct i2c_adapter *adapter = | |
2920 | intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); | |
15953637 SS |
2921 | |
2922 | if (!sink_scrambling->supported) | |
277ab5ab | 2923 | return true; |
15953637 | 2924 | |
277ab5ab VS |
2925 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", |
2926 | connector->base.id, connector->name, | |
2927 | yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); | |
15953637 | 2928 | |
277ab5ab VS |
2929 | /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ |
2930 | return drm_scdc_set_high_tmds_clock_ratio(adapter, | |
2931 | high_tmds_clock_ratio) && | |
2932 | drm_scdc_set_scrambling(adapter, scrambling); | |
15953637 SS |
2933 | } |
2934 | ||
cec3bb01 | 2935 | static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
e4ab73a1 | 2936 | { |
e4ab73a1 VS |
2937 | u8 ddc_pin; |
2938 | ||
cec3bb01 AS |
2939 | switch (port) { |
2940 | case PORT_B: | |
2941 | ddc_pin = GMBUS_PIN_DPB; | |
2942 | break; | |
2943 | case PORT_C: | |
2944 | ddc_pin = GMBUS_PIN_DPC; | |
2945 | break; | |
2946 | case PORT_D: | |
2947 | ddc_pin = GMBUS_PIN_DPD_CHV; | |
2948 | break; | |
2949 | default: | |
2950 | MISSING_CASE(port); | |
2951 | ddc_pin = GMBUS_PIN_DPB; | |
2952 | break; | |
e4ab73a1 | 2953 | } |
cec3bb01 AS |
2954 | return ddc_pin; |
2955 | } | |
2956 | ||
2957 | static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) | |
2958 | { | |
2959 | u8 ddc_pin; | |
e4ab73a1 VS |
2960 | |
2961 | switch (port) { | |
2962 | case PORT_B: | |
cec3bb01 | 2963 | ddc_pin = GMBUS_PIN_1_BXT; |
e4ab73a1 VS |
2964 | break; |
2965 | case PORT_C: | |
cec3bb01 AS |
2966 | ddc_pin = GMBUS_PIN_2_BXT; |
2967 | break; | |
2968 | default: | |
2969 | MISSING_CASE(port); | |
2970 | ddc_pin = GMBUS_PIN_1_BXT; | |
2971 | break; | |
2972 | } | |
2973 | return ddc_pin; | |
2974 | } | |
2975 | ||
2976 | static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, | |
2977 | enum port port) | |
2978 | { | |
2979 | u8 ddc_pin; | |
2980 | ||
2981 | switch (port) { | |
2982 | case PORT_B: | |
2983 | ddc_pin = GMBUS_PIN_1_BXT; | |
2984 | break; | |
2985 | case PORT_C: | |
2986 | ddc_pin = GMBUS_PIN_2_BXT; | |
e4ab73a1 VS |
2987 | break; |
2988 | case PORT_D: | |
cec3bb01 AS |
2989 | ddc_pin = GMBUS_PIN_4_CNP; |
2990 | break; | |
3a2a59cc RV |
2991 | case PORT_F: |
2992 | ddc_pin = GMBUS_PIN_3_BXT; | |
2993 | break; | |
cec3bb01 AS |
2994 | default: |
2995 | MISSING_CASE(port); | |
2996 | ddc_pin = GMBUS_PIN_1_BXT; | |
2997 | break; | |
2998 | } | |
2999 | return ddc_pin; | |
3000 | } | |
3001 | ||
5c749c52 AS |
3002 | static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
3003 | { | |
fb81cbe4 | 3004 | enum phy phy = intel_port_to_phy(dev_priv, port); |
5c749c52 | 3005 | |
fb81cbe4 LDM |
3006 | if (intel_phy_is_combo(dev_priv, phy)) |
3007 | return GMBUS_PIN_1_BXT + port; | |
3008 | else if (intel_phy_is_tc(dev_priv, phy)) | |
3009 | return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); | |
3010 | ||
10d4e146 | 3011 | drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); |
fb81cbe4 | 3012 | return GMBUS_PIN_2_BXT; |
5c749c52 AS |
3013 | } |
3014 | ||
c6f7acb8 MR |
3015 | static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
3016 | { | |
48cf0a1e | 3017 | enum phy phy = intel_port_to_phy(dev_priv, port); |
c6f7acb8 MR |
3018 | u8 ddc_pin; |
3019 | ||
48cf0a1e MR |
3020 | switch (phy) { |
3021 | case PHY_A: | |
c6f7acb8 MR |
3022 | ddc_pin = GMBUS_PIN_1_BXT; |
3023 | break; | |
48cf0a1e | 3024 | case PHY_B: |
c6f7acb8 MR |
3025 | ddc_pin = GMBUS_PIN_2_BXT; |
3026 | break; | |
48cf0a1e | 3027 | case PHY_C: |
c6f7acb8 MR |
3028 | ddc_pin = GMBUS_PIN_9_TC1_ICP; |
3029 | break; | |
3030 | default: | |
48cf0a1e | 3031 | MISSING_CASE(phy); |
c6f7acb8 MR |
3032 | ddc_pin = GMBUS_PIN_1_BXT; |
3033 | break; | |
3034 | } | |
3035 | return ddc_pin; | |
3036 | } | |
3037 | ||
cec3bb01 AS |
3038 | static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, |
3039 | enum port port) | |
3040 | { | |
3041 | u8 ddc_pin; | |
3042 | ||
3043 | switch (port) { | |
3044 | case PORT_B: | |
3045 | ddc_pin = GMBUS_PIN_DPB; | |
3046 | break; | |
3047 | case PORT_C: | |
3048 | ddc_pin = GMBUS_PIN_DPC; | |
3049 | break; | |
3050 | case PORT_D: | |
3051 | ddc_pin = GMBUS_PIN_DPD; | |
e4ab73a1 VS |
3052 | break; |
3053 | default: | |
3054 | MISSING_CASE(port); | |
3055 | ddc_pin = GMBUS_PIN_DPB; | |
3056 | break; | |
3057 | } | |
cec3bb01 AS |
3058 | return ddc_pin; |
3059 | } | |
3060 | ||
17004bfb | 3061 | static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) |
cec3bb01 | 3062 | { |
17004bfb JN |
3063 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
3064 | enum port port = encoder->port; | |
cec3bb01 AS |
3065 | u8 ddc_pin; |
3066 | ||
17004bfb JN |
3067 | ddc_pin = intel_bios_alternate_ddc_pin(encoder); |
3068 | if (ddc_pin) { | |
cec3bb01 | 3069 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", |
17004bfb JN |
3070 | ddc_pin, port_name(port)); |
3071 | return ddc_pin; | |
cec3bb01 AS |
3072 | } |
3073 | ||
c6f7acb8 MR |
3074 | if (HAS_PCH_MCC(dev_priv)) |
3075 | ddc_pin = mcc_port_to_ddc_pin(dev_priv, port); | |
b01a3ef3 | 3076 | else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) |
e0f83eb5 | 3077 | ddc_pin = icl_port_to_ddc_pin(dev_priv, port); |
cec3bb01 AS |
3078 | else if (HAS_PCH_CNP(dev_priv)) |
3079 | ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); | |
e0f83eb5 RV |
3080 | else if (IS_GEN9_LP(dev_priv)) |
3081 | ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); | |
3082 | else if (IS_CHERRYVIEW(dev_priv)) | |
3083 | ddc_pin = chv_port_to_ddc_pin(dev_priv, port); | |
cec3bb01 AS |
3084 | else |
3085 | ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); | |
e4ab73a1 VS |
3086 | |
3087 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", | |
3088 | ddc_pin, port_name(port)); | |
3089 | ||
3090 | return ddc_pin; | |
3091 | } | |
3092 | ||
385e4de0 VS |
3093 | void intel_infoframe_init(struct intel_digital_port *intel_dig_port) |
3094 | { | |
3095 | struct drm_i915_private *dev_priv = | |
3096 | to_i915(intel_dig_port->base.base.dev); | |
3097 | ||
3098 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
3099 | intel_dig_port->write_infoframe = vlv_write_infoframe; | |
f2a10d61 | 3100 | intel_dig_port->read_infoframe = vlv_read_infoframe; |
385e4de0 | 3101 | intel_dig_port->set_infoframes = vlv_set_infoframes; |
509efa2b | 3102 | intel_dig_port->infoframes_enabled = vlv_infoframes_enabled; |
385e4de0 VS |
3103 | } else if (IS_G4X(dev_priv)) { |
3104 | intel_dig_port->write_infoframe = g4x_write_infoframe; | |
f2a10d61 | 3105 | intel_dig_port->read_infoframe = g4x_read_infoframe; |
385e4de0 | 3106 | intel_dig_port->set_infoframes = g4x_set_infoframes; |
509efa2b | 3107 | intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; |
385e4de0 | 3108 | } else if (HAS_DDI(dev_priv)) { |
06c812d7 | 3109 | if (intel_dig_port->lspcon.active) { |
509efa2b | 3110 | intel_dig_port->write_infoframe = lspcon_write_infoframe; |
f2a10d61 | 3111 | intel_dig_port->read_infoframe = lspcon_read_infoframe; |
06c812d7 | 3112 | intel_dig_port->set_infoframes = lspcon_set_infoframes; |
509efa2b | 3113 | intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled; |
06c812d7 | 3114 | } else { |
06c812d7 | 3115 | intel_dig_port->write_infoframe = hsw_write_infoframe; |
f2a10d61 | 3116 | intel_dig_port->read_infoframe = hsw_read_infoframe; |
509efa2b VS |
3117 | intel_dig_port->set_infoframes = hsw_set_infoframes; |
3118 | intel_dig_port->infoframes_enabled = hsw_infoframes_enabled; | |
06c812d7 | 3119 | } |
385e4de0 VS |
3120 | } else if (HAS_PCH_IBX(dev_priv)) { |
3121 | intel_dig_port->write_infoframe = ibx_write_infoframe; | |
f2a10d61 | 3122 | intel_dig_port->read_infoframe = ibx_read_infoframe; |
385e4de0 | 3123 | intel_dig_port->set_infoframes = ibx_set_infoframes; |
509efa2b | 3124 | intel_dig_port->infoframes_enabled = ibx_infoframes_enabled; |
385e4de0 VS |
3125 | } else { |
3126 | intel_dig_port->write_infoframe = cpt_write_infoframe; | |
f2a10d61 | 3127 | intel_dig_port->read_infoframe = cpt_read_infoframe; |
385e4de0 | 3128 | intel_dig_port->set_infoframes = cpt_set_infoframes; |
509efa2b | 3129 | intel_dig_port->infoframes_enabled = cpt_infoframes_enabled; |
385e4de0 VS |
3130 | } |
3131 | } | |
3132 | ||
00c09d70 PZ |
3133 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
3134 | struct intel_connector *intel_connector) | |
7d57382e | 3135 | { |
b9cb234c PZ |
3136 | struct drm_connector *connector = &intel_connector->base; |
3137 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
3138 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
3139 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 3140 | struct drm_i915_private *dev_priv = to_i915(dev); |
c360824a | 3141 | struct i2c_adapter *ddc; |
8f4f2797 | 3142 | enum port port = intel_encoder->port; |
5558f3d5 | 3143 | struct cec_connector_info conn_info; |
373a3cf7 | 3144 | |
66a990dd VS |
3145 | DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n", |
3146 | intel_encoder->base.base.id, intel_encoder->base.name); | |
22f35042 | 3147 | |
10d4e146 | 3148 | if (INTEL_GEN(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) |
d6707194 LDM |
3149 | return; |
3150 | ||
10d4e146 PB |
3151 | if (drm_WARN(dev, intel_dig_port->max_lanes < 4, |
3152 | "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", | |
3153 | intel_dig_port->max_lanes, intel_encoder->base.base.id, | |
3154 | intel_encoder->base.name)) | |
ccb1a831 VS |
3155 | return; |
3156 | ||
17004bfb | 3157 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder); |
c360824a AP |
3158 | ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); |
3159 | ||
3160 | drm_connector_init_with_ddc(dev, connector, | |
3161 | &intel_hdmi_connector_funcs, | |
3162 | DRM_MODE_CONNECTOR_HDMIA, | |
3163 | ddc); | |
7d57382e EA |
3164 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
3165 | ||
c3febcc4 | 3166 | connector->interlace_allowed = 1; |
7d57382e | 3167 | connector->doublescan_allowed = 0; |
573e74ad | 3168 | connector->stereo_allowed = 1; |
66a9278e | 3169 | |
9672a69c | 3170 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
eadc2e51 SS |
3171 | connector->ycbcr_420_allowed = true; |
3172 | ||
cf53902f | 3173 | intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); |
5fb908eb | 3174 | intel_connector->polled = DRM_CONNECTOR_POLL_HPD; |
7d57382e | 3175 | |
4f8036a2 | 3176 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
3177 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
3178 | else | |
3179 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
3180 | |
3181 | intel_hdmi_add_properties(intel_hdmi, connector); | |
3182 | ||
04707f97 R |
3183 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
3184 | intel_hdmi->attached_connector = intel_connector; | |
3185 | ||
fdddd08c | 3186 | if (is_hdcp_supported(dev_priv, port)) { |
2320175f SP |
3187 | int ret = intel_hdcp_init(intel_connector, |
3188 | &intel_hdmi_hdcp_shim); | |
3189 | if (ret) | |
3190 | DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); | |
3191 | } | |
3192 | ||
b9cb234c PZ |
3193 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
3194 | * 0xd. Failure to do so will result in spurious interrupts being | |
3195 | * generated on the port when a cable is not attached. | |
3196 | */ | |
1c0f1b3d | 3197 | if (IS_G45(dev_priv)) { |
8192c82c JN |
3198 | u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); |
3199 | intel_de_write(dev_priv, PEG_BAND_GAP_DATA, | |
3200 | (temp & ~0xf) | 0xd); | |
b9cb234c | 3201 | } |
9c229127 | 3202 | |
5558f3d5 DM |
3203 | cec_fill_conn_info_from_drm(&conn_info, connector); |
3204 | ||
3205 | intel_hdmi->cec_notifier = | |
3206 | cec_notifier_conn_register(dev->dev, port_identifier(port), | |
3207 | &conn_info); | |
9c229127 NA |
3208 | if (!intel_hdmi->cec_notifier) |
3209 | DRM_DEBUG_KMS("CEC notifier get failed\n"); | |
b9cb234c PZ |
3210 | } |
3211 | ||
bb80c925 JRS |
3212 | static enum intel_hotplug_state |
3213 | intel_hdmi_hotplug(struct intel_encoder *encoder, | |
3214 | struct intel_connector *connector, bool irq_received) | |
3215 | { | |
3216 | enum intel_hotplug_state state; | |
3217 | ||
3218 | state = intel_encoder_hotplug(encoder, connector, irq_received); | |
3219 | ||
3220 | /* | |
3221 | * On many platforms the HDMI live state signal is known to be | |
3222 | * unreliable, so we can't use it to detect if a sink is connected or | |
3223 | * not. Instead we detect if it's connected based on whether we can | |
3224 | * read the EDID or not. That in turn has a problem during disconnect, | |
3225 | * since the HPD interrupt may be raised before the DDC lines get | |
3226 | * disconnected (due to how the required length of DDC vs. HPD | |
3227 | * connector pins are specified) and so we'll still be able to get a | |
3228 | * valid EDID. To solve this schedule another detection cycle if this | |
3229 | * time around we didn't detect any change in the sink's connection | |
3230 | * status. | |
3231 | */ | |
3232 | if (state == INTEL_HOTPLUG_UNCHANGED && irq_received) | |
3233 | state = INTEL_HOTPLUG_RETRY; | |
3234 | ||
3235 | return state; | |
3236 | } | |
3237 | ||
c39055b0 | 3238 | void intel_hdmi_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 3239 | i915_reg_t hdmi_reg, enum port port) |
b9cb234c PZ |
3240 | { |
3241 | struct intel_digital_port *intel_dig_port; | |
3242 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
3243 | struct intel_connector *intel_connector; |
3244 | ||
b14c5679 | 3245 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
3246 | if (!intel_dig_port) |
3247 | return; | |
3248 | ||
08d9bc92 | 3249 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
3250 | if (!intel_connector) { |
3251 | kfree(intel_dig_port); | |
3252 | return; | |
3253 | } | |
3254 | ||
3255 | intel_encoder = &intel_dig_port->base; | |
b9cb234c | 3256 | |
c39055b0 ACO |
3257 | drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
3258 | &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
3259 | "HDMI %c", port_name(port)); | |
00c09d70 | 3260 | |
bb80c925 | 3261 | intel_encoder->hotplug = intel_hdmi_hotplug; |
5bfe2ac0 | 3262 | intel_encoder->compute_config = intel_hdmi_compute_config; |
6e266956 | 3263 | if (HAS_PCH_SPLIT(dev_priv)) { |
a4790cec VS |
3264 | intel_encoder->disable = pch_disable_hdmi; |
3265 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
3266 | } else { | |
3267 | intel_encoder->disable = g4x_disable_hdmi; | |
3268 | } | |
00c09d70 | 3269 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 3270 | intel_encoder->get_config = intel_hdmi_get_config; |
920a14b2 | 3271 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 3272 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
3273 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
3274 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 3275 | intel_encoder->post_disable = chv_hdmi_post_disable; |
d6db995f | 3276 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
11a914c2 | 3277 | } else if (IS_VALLEYVIEW(dev_priv)) { |
9514ac6e CML |
3278 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
3279 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 3280 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 3281 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 3282 | } else { |
13732ba7 | 3283 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
6e266956 | 3284 | if (HAS_PCH_CPT(dev_priv)) |
d1b1589c | 3285 | intel_encoder->enable = cpt_enable_hdmi; |
6e266956 | 3286 | else if (HAS_PCH_IBX(dev_priv)) |
bf868c7d | 3287 | intel_encoder->enable = ibx_enable_hdmi; |
d1b1589c | 3288 | else |
bf868c7d | 3289 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 3290 | } |
5ab432ef | 3291 | |
b9cb234c | 3292 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
79f255a0 | 3293 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
03cdc1d4 | 3294 | intel_encoder->port = port; |
920a14b2 | 3295 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 | 3296 | if (port == PORT_D) |
981329ce | 3297 | intel_encoder->pipe_mask = BIT(PIPE_C); |
882ec384 | 3298 | else |
981329ce | 3299 | intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); |
882ec384 | 3300 | } else { |
34053ee1 | 3301 | intel_encoder->pipe_mask = ~0; |
882ec384 | 3302 | } |
301ea74a | 3303 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
3304 | /* |
3305 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
3306 | * to work on real hardware. And since g4x can send infoframes to | |
3307 | * only one port anyway, nothing is lost by allowing it. | |
3308 | */ | |
9beb5fea | 3309 | if (IS_G4X(dev_priv)) |
c6f1495d | 3310 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
7d57382e | 3311 | |
b242b7f7 | 3312 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
f0f59a00 | 3313 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
ccb1a831 | 3314 | intel_dig_port->max_lanes = 4; |
55b7d6e8 | 3315 | |
385e4de0 VS |
3316 | intel_infoframe_init(intel_dig_port); |
3317 | ||
39053089 | 3318 | intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); |
b9cb234c | 3319 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 3320 | } |