[thirdparty/linux.git] / drivers / gpu / drm / i915 / gvt / display.c

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Ke Yu
 *    Zhiyuan Lv <zhiyuan.lv@intel.com>
 *
 * Contributors:
 *    Terrence Xu <terrence.xu@intel.com>
 *    Changbin Du <changbin.du@intel.com>
 *    Bing Niu <bing.niu@intel.com>
 *    Zhi Wang <zhi.a.wang@intel.com>
 *
 */

#include "i915_drv.h"
#include "gvt.h"

static int get_edp_pipe(struct intel_vgpu *vgpu)
{
	u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
	int pipe = -1;

	switch (data & TRANS_DDI_EDP_INPUT_MASK) {
	case TRANS_DDI_EDP_INPUT_A_ON:
	case TRANS_DDI_EDP_INPUT_A_ONOFF:
		pipe = PIPE_A;
		break;
	case TRANS_DDI_EDP_INPUT_B_ONOFF:
		pipe = PIPE_B;
		break;
	case TRANS_DDI_EDP_INPUT_C_ONOFF:
		pipe = PIPE_C;
		break;
	}
	return pipe;
}

static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

	if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
		return 0;

	if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
		return 0;
	return 1;
}

int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

	if (drm_WARN_ON(&dev_priv->drm,
			pipe < PIPE_A || pipe >= I915_MAX_PIPES))
		return -EINVAL;

	if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
		return 1;

	if (edp_pipe_is_enabled(vgpu) &&
			get_edp_pipe(vgpu) == pipe)
		return 1;
	return 0;
}

static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
	{
/* EDID with 1024x768 as its resolution */
		/*Header*/
		0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
		/* Vendor & Product Identification */
		0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
		/* Version & Revision */
		0x01, 0x04,
		/* Basic Display Parameters & Features */
		0xa5, 0x34, 0x20, 0x78, 0x23,
		/* Color Characteristics */
		0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
		/* Established Timings: maximum resolution is 1024x768 */
		0x21, 0x08, 0x00,
		/* Standard Timings. All invalid */
		0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
		0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
		/* 18 Byte Data Blocks 1: invalid */
		0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
		0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
		/* 18 Byte Data Blocks 2: invalid */
		0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
		0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
		/* 18 Byte Data Blocks 3: invalid */
		0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
		0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
		/* 18 Byte Data Blocks 4: invalid */
		0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
		0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
		/* Extension Block Count */
		0x00,
		/* Checksum */
		0xef,
	},
	{
/* EDID with 1920x1200 as its resolution */
		/*Header*/
		0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
		/* Vendor & Product Identification */
		0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
		/* Version & Revision */
		0x01, 0x04,
		/* Basic Display Parameters & Features */
		0xa5, 0x34, 0x20, 0x78, 0x23,
		/* Color Characteristics */
		0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
		/* Established Timings: maximum resolution is 1024x768 */
		0x21, 0x08, 0x00,
		/*
		 * Standard Timings.
		 * below new resolutions can be supported:
		 * 1920x1080, 1280x720, 1280x960, 1280x1024,
		 * 1440x900, 1600x1200, 1680x1050
		 */
		0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
		0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
		/* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
		0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
		0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
		/* 18 Byte Data Blocks 2: invalid */
		0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
		0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
		/* 18 Byte Data Blocks 3: invalid */
		0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
		0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
		/* 18 Byte Data Blocks 4: invalid */
		0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
		0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
		/* Extension Block Count */
		0x00,
		/* Checksum */
		0x45,
	},
};

#define DPCD_HEADER_SIZE        0xb

/* let the virtual display supports DP1.2 */
static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
	0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
};

static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
	int pipe;

	if (IS_BROXTON(dev_priv)) {
		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
			BXT_DE_PORT_HP_DDIB |
			BXT_DE_PORT_HP_DDIC);

		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
				BXT_DE_PORT_HP_DDIA;
		}

		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
				BXT_DE_PORT_HP_DDIB;
		}

		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
				BXT_DE_PORT_HP_DDIC;
		}

		return;
	}

	vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
			SDE_PORTC_HOTPLUG_CPT |
			SDE_PORTD_HOTPLUG_CPT);

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
	    IS_COFFEELAKE(dev_priv)) {
		vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
				SDE_PORTE_HOTPLUG_SPT);
		vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
				SKL_FUSE_DOWNLOAD_STATUS |
				SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
				SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
				SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
		/*
		 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
		 *  tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
		 *   TRANSCODER_A can be enabled. PORT_x depends on the input of
		 *   setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
		 *   so we fixed to DPLL0 here.
		 * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
		 */
		vgpu_vreg_t(vgpu, DPLL_CTRL1) =
			DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);
		vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
			DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);
		vgpu_vreg_t(vgpu, LCPLL1_CTL) =
			LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK;
		vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
		/*
		 * Golden M/N are calculated based on:
		 *   24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
		 *   DP link clk 1620 MHz and non-constant_n.
		 * TODO: calculate DP link symbol clk and stream clk m/n.
		 */
		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
	}

	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
		vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
			~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);
		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
			DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);
		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
			TRANS_DDI_PORT_MASK);
		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
			(PORT_B << TRANS_DDI_PORT_SHIFT) |
			TRANS_DDI_FUNC_ENABLE);
		if (IS_BROADWELL(dev_priv)) {
			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
				~PORT_CLK_SEL_MASK;
			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
				PORT_CLK_SEL_LCPLL_810;
		}
		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
	}

	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
		vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
			~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
			DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
			TRANS_DDI_PORT_MASK);
		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
			(PORT_C << TRANS_DDI_PORT_SHIFT) |
			TRANS_DDI_FUNC_ENABLE);
		if (IS_BROADWELL(dev_priv)) {
			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
				~PORT_CLK_SEL_MASK;
			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
				PORT_CLK_SEL_LCPLL_810;
		}
		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
	}

	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
		vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
			~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
			DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
		vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
			DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
			TRANS_DDI_PORT_MASK);
		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
			(PORT_D << TRANS_DDI_PORT_SHIFT) |
			TRANS_DDI_FUNC_ENABLE);
		if (IS_BROADWELL(dev_priv)) {
			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
				~PORT_CLK_SEL_MASK;
			vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
				PORT_CLK_SEL_LCPLL_810;
		}
		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
	}

	if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
	     IS_COFFEELAKE(dev_priv)) &&
			intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
	}

	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
		if (IS_BROADWELL(dev_priv))
			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
				GEN8_PORT_DP_A_HOTPLUG;
		else
			vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;

		vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
	}

	/* Clear host CRT status, so guest couldn't detect this host CRT. */
	if (IS_BROADWELL(dev_priv))
		vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;

	/* Disable Primary/Sprite/Cursor plane */
	for_each_pipe(dev_priv, pipe) {
		vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
		vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
		vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
		vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
	}

	vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
}

static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
{
	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);

	kfree(port->edid);
	port->edid = NULL;

	kfree(port->dpcd);
	port->dpcd = NULL;
}

static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
				    int type, unsigned int resolution)
{
	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);

	if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))
		return -EINVAL;

	port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
	if (!port->edid)
		return -ENOMEM;

	port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
	if (!port->dpcd) {
		kfree(port->edid);
		return -ENOMEM;
	}

	memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
			EDID_SIZE);
	port->edid->data_valid = true;

	memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
	port->dpcd->data_valid = true;
	port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
	port->type = type;
	port->id = resolution;

	emulate_monitor_status_change(vgpu);

	return 0;
}

/**
 * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
 * be turned on/off when a virtual pipe is enabled/disabled.
 * @gvt: a GVT device
 *
 * This function is used to turn on/off vblank timer according to currently
 * enabled/disabled virtual pipes.
 *
 */
void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
{
	struct intel_gvt_irq *irq = &gvt->irq;
	struct intel_vgpu *vgpu;
	int pipe, id;
	int found = false;

	mutex_lock(&gvt->lock);
	for_each_active_vgpu(gvt, vgpu, id) {
		for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
			if (pipe_is_enabled(vgpu, pipe)) {
				found = true;
				break;
			}
		}
		if (found)
			break;
	}

	/* all the pipes are disabled */
	if (!found)
		hrtimer_cancel(&irq->vblank_timer.timer);
	else
		hrtimer_start(&irq->vblank_timer.timer,
			ktime_add_ns(ktime_get(), irq->vblank_timer.period),
			HRTIMER_MODE_ABS);
	mutex_unlock(&gvt->lock);
}

static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
	struct intel_vgpu_irq *irq = &vgpu->irq;
	int vblank_event[] = {
		[PIPE_A] = PIPE_A_VBLANK,
		[PIPE_B] = PIPE_B_VBLANK,
		[PIPE_C] = PIPE_C_VBLANK,
	};
	int event;

	if (pipe < PIPE_A || pipe > PIPE_C)
		return;

	for_each_set_bit(event, irq->flip_done_event[pipe],
			INTEL_GVT_EVENT_MAX) {
		clear_bit(event, irq->flip_done_event[pipe]);
		if (!pipe_is_enabled(vgpu, pipe))
			continue;

		intel_vgpu_trigger_virtual_event(vgpu, event);
	}

	if (pipe_is_enabled(vgpu, pipe)) {
		vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
		intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
	}
}

static void emulate_vblank(struct intel_vgpu *vgpu)
{
	int pipe;

	mutex_lock(&vgpu->vgpu_lock);
	for_each_pipe(vgpu->gvt->gt->i915, pipe)
		emulate_vblank_on_pipe(vgpu, pipe);
	mutex_unlock(&vgpu->vgpu_lock);
}

/**
 * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
 * @gvt: a GVT device
 *
 * This function is used to trigger vblank interrupts for vGPUs on GVT device
 *
 */
void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
{
	struct intel_vgpu *vgpu;
	int id;

	mutex_lock(&gvt->lock);
	for_each_active_vgpu(gvt, vgpu, id)
		emulate_vblank(vgpu);
	mutex_unlock(&gvt->lock);
}

/**
 * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
 * @vgpu: a vGPU
 * @connected: link state
 *
 * This function is used to trigger hotplug interrupt for vGPU
 *
 */
void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
{
	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;

	/* TODO: add more platforms support */
	if (IS_SKYLAKE(i915) || IS_KABYLAKE(i915) ||
	    IS_COFFEELAKE(i915)) {
		if (connected) {
			vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
				SFUSE_STRAP_DDID_DETECTED;
			vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
		} else {
			vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
				~SFUSE_STRAP_DDID_DETECTED;
			vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
		}
		vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;
		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
				PORTD_HOTPLUG_STATUS_MASK;
		intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
	}
}

/**
 * intel_vgpu_clean_display - clean vGPU virtual display emulation
 * @vgpu: a vGPU
 *
 * This function is used to clean vGPU virtual display emulation stuffs
 *
 */
void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
	    IS_COFFEELAKE(dev_priv))
		clean_virtual_dp_monitor(vgpu, PORT_D);
	else
		clean_virtual_dp_monitor(vgpu, PORT_B);
}

/**
 * intel_vgpu_init_display- initialize vGPU virtual display emulation
 * @vgpu: a vGPU
 * @resolution: resolution index for intel_vgpu_edid
 *
 * This function is used to initialize vGPU virtual display emulation stuffs
 *
 * Returns:
 * Zero on success, negative error code if failed.
 *
 */
int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
{
	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;

	intel_vgpu_init_i2c_edid(vgpu);

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ||
	    IS_COFFEELAKE(dev_priv))
		return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
						resolution);
	else
		return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
						resolution);
}

/**
 * intel_vgpu_reset_display- reset vGPU virtual display emulation
 * @vgpu: a vGPU
 *
 * This function is used to reset vGPU virtual display emulation stuffs
 *
 */
void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
{
	emulate_monitor_status_change(vgpu);
}
Commit	Line	Data
04d348ae ZW	1	/*
	2	* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
	22	*
	23	* Authors:
	24	* Ke Yu
	25	* Zhiyuan Lv <zhiyuan.lv@intel.com>
	26	*
	27	* Contributors:
	28	* Terrence Xu <terrence.xu@intel.com>
	29	* Changbin Du <changbin.du@intel.com>
	30	* Bing Niu <bing.niu@intel.com>
	31	* Zhi Wang <zhi.a.wang@intel.com>
	32	*
	33	*/
	34
	35	#include "i915_drv.h"
feddf6e8	36	#include "gvt.h"
04d348ae ZW	37
	38	static int get_edp_pipe(struct intel_vgpu *vgpu)
	39	{
	40	u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
	41	int pipe = -1;
	42
	43	switch (data & TRANS_DDI_EDP_INPUT_MASK) {
	44	case TRANS_DDI_EDP_INPUT_A_ON:
	45	case TRANS_DDI_EDP_INPUT_A_ONOFF:
	46	pipe = PIPE_A;
	47	break;
	48	case TRANS_DDI_EDP_INPUT_B_ONOFF:
	49	pipe = PIPE_B;
	50	break;
	51	case TRANS_DDI_EDP_INPUT_C_ONOFF:
	52	pipe = PIPE_C;
	53	break;
	54	}
	55	return pipe;
	56	}
	57
	58	static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
	59	{
a61ac1e7	60	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
04d348ae	61
90551a12	62	if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
04d348ae ZW	63	return 0;
	64
	65	if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
	66	return 0;
	67	return 1;
	68	}
	69
9f31d106	70	int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
04d348ae	71	{
a61ac1e7	72	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
04d348ae	73
db19c724 PB	74	if (drm_WARN_ON(&dev_priv->drm,
db19c724 PB	75	pipe < PIPE_A \|\| pipe >= I915_MAX_PIPES))
04d348ae ZW	76	return -EINVAL;
04d348ae ZW	77
90551a12	78	if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
04d348ae ZW	79	return 1;
	80
	81	if (edp_pipe_is_enabled(vgpu) &&
	82	get_edp_pipe(vgpu) == pipe)
	83	return 1;
	84	return 0;
	85	}
	86
bca5609f ZW	87	static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
	88	{
	89	/* EDID with 1024x768 as its resolution */
	90	/Header/
	91	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
	92	/* Vendor & Product Identification */
	93	0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
	94	/* Version & Revision */
	95	0x01, 0x04,
	96	/* Basic Display Parameters & Features */
	97	0xa5, 0x34, 0x20, 0x78, 0x23,
	98	/* Color Characteristics */
	99	0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
	100	/* Established Timings: maximum resolution is 1024x768 */
	101	0x21, 0x08, 0x00,
	102	/* Standard Timings. All invalid */
	103	0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
	104	0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
	105	/* 18 Byte Data Blocks 1: invalid */
	106	0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
	107	0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
	108	/* 18 Byte Data Blocks 2: invalid */
	109	0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
	110	0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
	111	/* 18 Byte Data Blocks 3: invalid */
	112	0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
	113	0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
	114	/* 18 Byte Data Blocks 4: invalid */
	115	0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
	116	0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
	117	/* Extension Block Count */
	118	0x00,
	119	/* Checksum */
	120	0xef,
	121	},
	122	{
2c883136	123	/* EDID with 1920x1200 as its resolution */
bca5609f ZW	124	/Header/
	125	0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
	126	/* Vendor & Product Identification */
	127	0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
	128	/* Version & Revision */
	129	0x01, 0x04,
	130	/* Basic Display Parameters & Features */
	131	0xa5, 0x34, 0x20, 0x78, 0x23,
	132	/* Color Characteristics */
	133	0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
	134	/* Established Timings: maximum resolution is 1024x768 */
	135	0x21, 0x08, 0x00,
	136	/*
	137	* Standard Timings.
	138	* below new resolutions can be supported:
	139	* 1920x1080, 1280x720, 1280x960, 1280x1024,
	140	* 1440x900, 1600x1200, 1680x1050
	141	*/
	142	0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
	143	0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
	144	/* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
	145	0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
	146	0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
	147	/* 18 Byte Data Blocks 2: invalid */
	148	0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
	149	0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
	150	/* 18 Byte Data Blocks 3: invalid */
	151	0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
	152	0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
	153	/* 18 Byte Data Blocks 4: invalid */
	154	0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
	155	0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
	156	/* Extension Block Count */
	157	0x00,
	158	/* Checksum */
	159	0x45,
	160	},
04d348ae ZW	161	};
	162
	163	#define DPCD_HEADER_SIZE 0xb
	164
e2e02cbb	165	/* let the virtual display supports DP1.2 */
999ccb40	166	static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
e2e02cbb	167	0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
04d348ae ZW	168	};
	169
	170	static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
	171	{
a61ac1e7	172	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
65eff272 XZ	173	int pipe;
65eff272 XZ	174
72bad997 CX	175	if (IS_BROXTON(dev_priv)) {
	176	vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA \|
	177	BXT_DE_PORT_HP_DDIB \|
	178	BXT_DE_PORT_HP_DDIC);
	179
	180	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
	181	vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) \|=
	182	BXT_DE_PORT_HP_DDIA;
	183	}
	184
	185	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
	186	vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) \|=
	187	BXT_DE_PORT_HP_DDIB;
	188	}
	189
	190	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
	191	vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) \|=
	192	BXT_DE_PORT_HP_DDIC;
	193	}
	194
	195	return;
	196	}
	197
90551a12	198	vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT \|
04d348ae ZW	199	SDE_PORTC_HOTPLUG_CPT \|
	200	SDE_PORTD_HOTPLUG_CPT);
	201
c3b5a843	202	if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv) \|\|
c3b5a843	203	IS_COFFEELAKE(dev_priv)) {
90551a12	204	vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT \|
04d348ae	205	SDE_PORTE_HOTPLUG_SPT);
90551a12	206	vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) \|=
88a16b64	207	SKL_FUSE_DOWNLOAD_STATUS \|
b2891eb2 ID	208	SKL_FUSE_PG_DIST_STATUS(SKL_PG0) \|
	209	SKL_FUSE_PG_DIST_STATUS(SKL_PG1) \|
	210	SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
f965b681 CX	211	/*
	212	* Only 1 PIPE enabled in current vGPU display and PIPE_A is
	213	* tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
	214	* TRANSCODER_A can be enabled. PORT_x depends on the input of
	215	* setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
	216	* so we fixed to DPLL0 here.
	217	* Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
	218	*/
	219	vgpu_vreg_t(vgpu, DPLL_CTRL1) =
	220	DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);
	221	vgpu_vreg_t(vgpu, DPLL_CTRL1) \|=
	222	DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);
	223	vgpu_vreg_t(vgpu, LCPLL1_CTL) =
	224	LCPLL_PLL_ENABLE \| LCPLL_PLL_LOCK;
	225	vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
	226	/*
	227	* Golden M/N are calculated based on:
	228	* 24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
	229	* DP link clk 1620 MHz and non-constant_n.
	230	* TODO: calculate DP link symbol clk and stream clk m/n.
	231	*/
	232	vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
	233	vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) \|= 0x5b425e;
	234	vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
	235	vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
	236	vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
88a16b64	237	}
04d348ae	238
858b0f57	239	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
f965b681 CX	240	vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
	241	~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);
	242	vgpu_vreg_t(vgpu, DPLL_CTRL2) \|=
	243	DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);
	244	vgpu_vreg_t(vgpu, DPLL_CTRL2) \|=
	245	DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
90551a12 ZW	246	vgpu_vreg_t(vgpu, SFUSE_STRAP) \|= SFUSE_STRAP_DDIB_DETECTED;
90551a12 ZW	247	vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d73 PZ	248	~(TRANS_DDI_BPC_MASK \| TRANS_DDI_MODE_SELECT_MASK \|
efa69d73 PZ	249	TRANS_DDI_PORT_MASK);
90551a12	250	vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) \|=
75db1a5b	251	(TRANS_DDI_BPC_8 \| TRANS_DDI_MODE_SELECT_DP_SST \|
efa69d73 PZ	252	(PORT_B << TRANS_DDI_PORT_SHIFT) \|
efa69d73 PZ	253	TRANS_DDI_FUNC_ENABLE);
295a0d0b	254	if (IS_BROADWELL(dev_priv)) {
90551a12	255	vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
295a0d0b	256	~PORT_CLK_SEL_MASK;
90551a12	257	vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) \|=
295a0d0b XZ	258	PORT_CLK_SEL_LCPLL_810;
295a0d0b XZ	259	}
90551a12 ZW	260	vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) \|= DDI_BUF_CTL_ENABLE;
	261	vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
	262	vgpu_vreg_t(vgpu, SDEISR) \|= SDE_PORTB_HOTPLUG_CPT;
858b0f57	263	}
04d348ae	264
858b0f57	265	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
f965b681 CX	266	vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
	267	~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
	268	vgpu_vreg_t(vgpu, DPLL_CTRL2) \|=
	269	DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
	270	vgpu_vreg_t(vgpu, DPLL_CTRL2) \|=
	271	DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
90551a12 ZW	272	vgpu_vreg_t(vgpu, SDEISR) \|= SDE_PORTC_HOTPLUG_CPT;
90551a12 ZW	273	vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d73 PZ	274	~(TRANS_DDI_BPC_MASK \| TRANS_DDI_MODE_SELECT_MASK \|
efa69d73 PZ	275	TRANS_DDI_PORT_MASK);
90551a12	276	vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) \|=
75db1a5b	277	(TRANS_DDI_BPC_8 \| TRANS_DDI_MODE_SELECT_DP_SST \|
efa69d73 PZ	278	(PORT_C << TRANS_DDI_PORT_SHIFT) \|
efa69d73 PZ	279	TRANS_DDI_FUNC_ENABLE);
295a0d0b	280	if (IS_BROADWELL(dev_priv)) {
90551a12	281	vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
295a0d0b	282	~PORT_CLK_SEL_MASK;
90551a12	283	vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) \|=
295a0d0b XZ	284	PORT_CLK_SEL_LCPLL_810;
295a0d0b XZ	285	}
90551a12 ZW	286	vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) \|= DDI_BUF_CTL_ENABLE;
	287	vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
	288	vgpu_vreg_t(vgpu, SFUSE_STRAP) \|= SFUSE_STRAP_DDIC_DETECTED;
858b0f57	289	}
04d348ae	290
858b0f57	291	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
f965b681 CX	292	vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
	293	~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
	294	vgpu_vreg_t(vgpu, DPLL_CTRL2) \|=
	295	DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
	296	vgpu_vreg_t(vgpu, DPLL_CTRL2) \|=
	297	DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
90551a12 ZW	298	vgpu_vreg_t(vgpu, SDEISR) \|= SDE_PORTD_HOTPLUG_CPT;
90551a12 ZW	299	vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
efa69d73 PZ	300	~(TRANS_DDI_BPC_MASK \| TRANS_DDI_MODE_SELECT_MASK \|
efa69d73 PZ	301	TRANS_DDI_PORT_MASK);
90551a12	302	vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) \|=
75db1a5b	303	(TRANS_DDI_BPC_8 \| TRANS_DDI_MODE_SELECT_DP_SST \|
efa69d73 PZ	304	(PORT_D << TRANS_DDI_PORT_SHIFT) \|
efa69d73 PZ	305	TRANS_DDI_FUNC_ENABLE);
295a0d0b	306	if (IS_BROADWELL(dev_priv)) {
90551a12	307	vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
295a0d0b	308	~PORT_CLK_SEL_MASK;
90551a12	309	vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) \|=
295a0d0b XZ	310	PORT_CLK_SEL_LCPLL_810;
295a0d0b XZ	311	}
90551a12 ZW	312	vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) \|= DDI_BUF_CTL_ENABLE;
	313	vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
	314	vgpu_vreg_t(vgpu, SFUSE_STRAP) \|= SFUSE_STRAP_DDID_DETECTED;
858b0f57	315	}
04d348ae	316
c3b5a843	317	if ((IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv) \|\|
c3b5a843	318	IS_COFFEELAKE(dev_priv)) &&
04d348ae	319	intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
90551a12	320	vgpu_vreg_t(vgpu, SDEISR) \|= SDE_PORTE_HOTPLUG_SPT;
04d348ae ZW	321	}
	322
	323	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
	324	if (IS_BROADWELL(dev_priv))
90551a12	325	vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) \|=
04d348ae ZW	326	GEN8_PORT_DP_A_HOTPLUG;
04d348ae ZW	327	else
90551a12	328	vgpu_vreg_t(vgpu, SDEISR) \|= SDE_PORTA_HOTPLUG_SPT;
858b0f57	329
90551a12	330	vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) \|= DDI_INIT_DISPLAY_DETECTED;
04d348ae	331	}
75e64ff2 XZ	332
	333	/* Clear host CRT status, so guest couldn't detect this host CRT. */
	334	if (IS_BROADWELL(dev_priv))
90551a12	335	vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
4e889d62	336
65eff272 XZ	337	/* Disable Primary/Sprite/Cursor plane */
	338	for_each_pipe(dev_priv, pipe) {
	339	vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
	340	vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
b99b9ec1 VS	341	vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
b99b9ec1 VS	342	vgpu_vreg_t(vgpu, CURCNTR(pipe)) \|= MCURSOR_MODE_DISABLE;
65eff272 XZ	343	}
65eff272 XZ	344
90551a12	345	vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) \|= PIPECONF_ENABLE;
04d348ae ZW	346	}
	347
	348	static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
	349	{
	350	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
	351
	352	kfree(port->edid);
	353	port->edid = NULL;
	354
	355	kfree(port->dpcd);
	356	port->dpcd = NULL;
	357	}
	358
	359	static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
d1a513be	360	int type, unsigned int resolution)
04d348ae	361	{
a61ac1e7	362	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
04d348ae ZW	363	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
04d348ae ZW	364
12d58619	365	if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))
d1a513be ZW	366	return -EINVAL;
d1a513be ZW	367
04d348ae ZW	368	port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
	369	if (!port->edid)
	370	return -ENOMEM;
	371
	372	port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
	373	if (!port->dpcd) {
	374	kfree(port->edid);
	375	return -ENOMEM;
	376	}
	377
d1a513be	378	memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
04d348ae ZW	379	EDID_SIZE);
	380	port->edid->data_valid = true;
	381
	382	memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
	383	port->dpcd->data_valid = true;
	384	port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
	385	port->type = type;
49220789	386	port->id = resolution;
04d348ae ZW	387
04d348ae ZW	388	emulate_monitor_status_change(vgpu);
4e889d62	389
04d348ae ZW	390	return 0;
	391	}
	392
	393	/**
	394	* intel_gvt_check_vblank_emulation - check if vblank emulation timer should
	395	* be turned on/off when a virtual pipe is enabled/disabled.
	396	* @gvt: a GVT device
	397	*
	398	* This function is used to turn on/off vblank timer according to currently
	399	* enabled/disabled virtual pipes.
	400	*
	401	*/
	402	void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
	403	{
	404	struct intel_gvt_irq *irq = &gvt->irq;
	405	struct intel_vgpu *vgpu;
04d348ae	406	int pipe, id;
f25a49ab	407	int found = false;
04d348ae	408
f25a49ab	409	mutex_lock(&gvt->lock);
04d348ae ZW	410	for_each_active_vgpu(gvt, vgpu, id) {
04d348ae ZW	411	for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
f25a49ab CX	412	if (pipe_is_enabled(vgpu, pipe)) {
	413	found = true;
	414	break;
	415	}
04d348ae	416	}
f25a49ab CX	417	if (found)
f25a49ab CX	418	break;
04d348ae ZW	419	}
04d348ae ZW	420
f43aa31f	421	/* all the pipes are disabled */
f25a49ab CX	422	if (!found)
	423	hrtimer_cancel(&irq->vblank_timer.timer);
	424	else
	425	hrtimer_start(&irq->vblank_timer.timer,
	426	ktime_add_ns(ktime_get(), irq->vblank_timer.period),
	427	HRTIMER_MODE_ABS);
	428	mutex_unlock(&gvt->lock);
04d348ae ZW	429	}
	430
	431	static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
	432	{
a61ac1e7	433	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
04d348ae ZW	434	struct intel_vgpu_irq *irq = &vgpu->irq;
	435	int vblank_event[] = {
	436	[PIPE_A] = PIPE_A_VBLANK,
	437	[PIPE_B] = PIPE_B_VBLANK,
	438	[PIPE_C] = PIPE_C_VBLANK,
	439	};
	440	int event;
	441
	442	if (pipe < PIPE_A \|\| pipe > PIPE_C)
	443	return;
	444
	445	for_each_set_bit(event, irq->flip_done_event[pipe],
	446	INTEL_GVT_EVENT_MAX) {
	447	clear_bit(event, irq->flip_done_event[pipe]);
	448	if (!pipe_is_enabled(vgpu, pipe))
	449	continue;
	450
04d348ae ZW	451	intel_vgpu_trigger_virtual_event(vgpu, event);
	452	}
	453
	454	if (pipe_is_enabled(vgpu, pipe)) {
90551a12	455	vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
04d348ae ZW	456	intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
	457	}
	458	}
	459
	460	static void emulate_vblank(struct intel_vgpu *vgpu)
	461	{
	462	int pipe;
	463
f25a49ab	464	mutex_lock(&vgpu->vgpu_lock);
a61ac1e7	465	for_each_pipe(vgpu->gvt->gt->i915, pipe)
04d348ae	466	emulate_vblank_on_pipe(vgpu, pipe);
f25a49ab	467	mutex_unlock(&vgpu->vgpu_lock);
04d348ae ZW	468	}
	469
	470	/**
	471	* intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
	472	* @gvt: a GVT device
	473	*
	474	* This function is used to trigger vblank interrupts for vGPUs on GVT device
	475	*
	476	*/
	477	void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
	478	{
	479	struct intel_vgpu *vgpu;
	480	int id;
	481
f25a49ab	482	mutex_lock(&gvt->lock);
04d348ae ZW	483	for_each_active_vgpu(gvt, vgpu, id)
04d348ae ZW	484	emulate_vblank(vgpu);
f25a49ab	485	mutex_unlock(&gvt->lock);
04d348ae ZW	486	}
04d348ae ZW	487
1ca20f33 HY	488	/**
	489	* intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
	490	* @vgpu: a vGPU
cf9ed666	491	* @connected: link state
1ca20f33 HY	492	*
	493	* This function is used to trigger hotplug interrupt for vGPU
	494	*
	495	*/
	496	void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
	497	{
a61ac1e7	498	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1ca20f33 HY	499
1ca20f33 HY	500	/* TODO: add more platforms support */
a61ac1e7 CW	501	if (IS_SKYLAKE(i915) \|\| IS_KABYLAKE(i915) \|\|
a61ac1e7 CW	502	IS_COFFEELAKE(i915)) {
1ca20f33 HY	503	if (connected) {
	504	vgpu_vreg_t(vgpu, SFUSE_STRAP) \|=
	505	SFUSE_STRAP_DDID_DETECTED;
	506	vgpu_vreg_t(vgpu, SDEISR) \|= SDE_PORTD_HOTPLUG_CPT;
	507	} else {
	508	vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
	509	~SFUSE_STRAP_DDID_DETECTED;
	510	vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
	511	}
	512	vgpu_vreg_t(vgpu, SDEIIR) \|= SDE_PORTD_HOTPLUG_CPT;
	513	vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) \|=
	514	PORTD_HOTPLUG_STATUS_MASK;
	515	intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
	516	}
	517	}
	518
04d348ae ZW	519	/**
	520	* intel_vgpu_clean_display - clean vGPU virtual display emulation
	521	* @vgpu: a vGPU
	522	*
	523	* This function is used to clean vGPU virtual display emulation stuffs
	524	*
	525	*/
	526	void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
	527	{
a61ac1e7	528	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
04d348ae	529
c3b5a843	530	if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv) \|\|
c3b5a843	531	IS_COFFEELAKE(dev_priv))
04d348ae ZW	532	clean_virtual_dp_monitor(vgpu, PORT_D);
	533	else
	534	clean_virtual_dp_monitor(vgpu, PORT_B);
	535	}
	536
	537	/**
	538	* intel_vgpu_init_display- initialize vGPU virtual display emulation
	539	* @vgpu: a vGPU
a752b070	540	* @resolution: resolution index for intel_vgpu_edid
04d348ae ZW	541	*
	542	* This function is used to initialize vGPU virtual display emulation stuffs
	543	*
	544	* Returns:
	545	* Zero on success, negative error code if failed.
	546	*
	547	*/
d1a513be	548	int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
04d348ae	549	{
a61ac1e7	550	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
04d348ae ZW	551
	552	intel_vgpu_init_i2c_edid(vgpu);
	553
c3b5a843	554	if (IS_SKYLAKE(dev_priv) \|\| IS_KABYLAKE(dev_priv) \|\|
c3b5a843	555	IS_COFFEELAKE(dev_priv))
d1a513be ZW	556	return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
d1a513be ZW	557	resolution);
04d348ae	558	else
d1a513be ZW	559	return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
d1a513be ZW	560	resolution);
04d348ae	561	}
6294b61b CD	562
	563	/**
	564	* intel_vgpu_reset_display- reset vGPU virtual display emulation
	565	* @vgpu: a vGPU
	566	*
	567	* This function is used to reset vGPU virtual display emulation stuffs
	568	*
	569	*/
	570	void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
	571	{
	572	emulate_monitor_status_change(vgpu);
	573	}