projects / thirdparty / kernel / stable.git / blame
| Commit | Line | Data |
|---|---|---|
| 12d14cc4 ZW |
1 | /* |
| 2 | * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. | |
| 3 | * | |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | * copy of this software and associated documentation files (the "Software"), | |
| 6 | * to deal in the Software without restriction, including without limitation | |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | * Software is furnished to do so, subject to the following conditions: | |
| 10 | * | |
| 11 | * The above copyright notice and this permission notice (including the next | |
| 12 | * paragraph) shall be included in all copies or substantial portions of the | |
| 13 | * Software. | |
| 14 | * | |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
| 21 | * SOFTWARE. | |
| 22 | * | |
| 23 | * Authors: | |
| 24 | * Ke Yu | |
| 25 | * Kevin Tian <kevin.tian@intel.com> | |
| 26 | * Dexuan Cui | |
| 27 | * | |
| 28 | * Contributors: | |
| 29 | * Tina Zhang <tina.zhang@intel.com> | |
| 30 | * Min He <min.he@intel.com> | |
| 31 | * Niu Bing <bing.niu@intel.com> | |
| 32 | * Zhi Wang <zhi.a.wang@intel.com> | |
| 33 | * | |
| 34 | */ | |
| 35 | ||
| 36 | #ifndef _GVT_MMIO_H_ | |
| 37 | #define _GVT_MMIO_H_ | |
| 38 | ||
| ab11a927 MY |
39 | #include <linux/types.h> |
| 40 | ||
| 12d14cc4 ZW |
41 | struct intel_gvt; |
| 42 | struct intel_vgpu; | |
| 43 | ||
| a1dcba90 | 44 | #define D_BDW (1 << 0) |
| 45 | #define D_SKL (1 << 1) | |
| 46 | #define D_KBL (1 << 2) | |
| 2939db9e | 47 | #define D_BXT (1 << 3) |
| 36520ed0 | 48 | #define D_CFL (1 << 4) |
| 12d14cc4 | 49 | |
| 36520ed0 | 50 | #define D_GEN9PLUS (D_SKL | D_KBL | D_BXT | D_CFL) |
| 51 | #define D_GEN8PLUS (D_BDW | D_SKL | D_KBL | D_BXT | D_CFL) | |
| 12d14cc4 | 52 | |
| 36520ed0 | 53 | #define D_SKL_PLUS (D_SKL | D_KBL | D_BXT | D_CFL) |
| 54 | #define D_BDW_PLUS (D_BDW | D_SKL | D_KBL | D_BXT | D_CFL) | |
| 12d14cc4 | 55 | |
| a1dcba90 | 56 | #define D_PRE_SKL (D_BDW) |
| 36520ed0 | 57 | #define D_ALL (D_BDW | D_SKL | D_KBL | D_BXT | D_CFL) |
| 12d14cc4 | 58 | |
| 65f9f6fe CD |
59 | typedef int (*gvt_mmio_func)(struct intel_vgpu *, unsigned int, void *, |
| 60 | unsigned int); | |
| 61 | ||
| 12d14cc4 ZW |
62 | struct intel_gvt_mmio_info { |
| 63 | u32 offset; | |
| 12d14cc4 | 64 | u64 ro_mask; |
| 65f9f6fe CD |
65 | gvt_mmio_func read; |
| 66 | gvt_mmio_func write; | |
| 12d14cc4 ZW |
67 | struct hlist_node node; |
| 68 | }; | |
| 69 | ||
| 8fde4107 CW |
70 | const struct intel_engine_cs * |
| 71 | intel_gvt_render_mmio_to_engine(struct intel_gvt *gvt, unsigned int reg); | |
| 12d14cc4 | 72 | unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt); |
| 12d14cc4 ZW |
73 | |
| 74 | int intel_gvt_setup_mmio_info(struct intel_gvt *gvt); | |
| 75 | void intel_gvt_clean_mmio_info(struct intel_gvt *gvt); | |
| 7cb16018 CD |
76 | int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt, |
| 77 | int (*handler)(struct intel_gvt *gvt, u32 offset, void *data), | |
| 78 | void *data); | |
| 79 | ||
| 70add39f YZ |
80 | struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt, |
| 81 | unsigned int offset); | |
| 82 | ||
| cdcc4347 | 83 | int intel_vgpu_init_mmio(struct intel_vgpu *vgpu); |
| 615c16a9 | 84 | void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr); |
| cdcc4347 CD |
85 | void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu); |
| 86 | ||
| e39c5add | 87 | int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa); |
| 9ec1e66b JS |
88 | |
| 89 | int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa, | |
| 90 | void *p_data, unsigned int bytes); | |
| 91 | int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa, | |
| 92 | void *p_data, unsigned int bytes); | |
| 5c6d4c67 | 93 | |
| e39c5add ZW |
94 | int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset, |
| 95 | void *p_data, unsigned int bytes); | |
| 96 | int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, | |
| 97 | void *p_data, unsigned int bytes); | |
| 4938ca90 ZY |
98 | |
| 99 | bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt, | |
| 100 | unsigned int offset); | |
| 65f9f6fe CD |
101 | |
| 102 | int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset, | |
| 103 | void *pdata, unsigned int bytes, bool is_read); | |
| 104 | ||
| 6cef21a1 HY |
105 | int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, |
| 106 | void *p_data, unsigned int bytes); | |
| 5f60b12e CX |
107 | |
| 108 | void intel_gvt_restore_fence(struct intel_gvt *gvt); | |
| 109 | void intel_gvt_restore_mmio(struct intel_gvt *gvt); | |
| 110 | ||
| 12d14cc4 | 111 | #endif |