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drm/i915: add DP 1.2 MST support (v0.7)
[people/ms/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
05394f39 99 if (obj->user_pin_count > 0)
a6172a80 100 return "P";
d7f46fc4 101 else if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 102 return "p";
103 else
104 return " ";
105}
106
05394f39 107static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 108{
0206e353
AJ		 109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
a6172a80
CW		 115}
116
1d693bcc
BW		 117static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118{
119 return obj->has_global_gtt_mapping ? "g" : " ";
120}
121
37811fcc
CW		 122static void
123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124{
1d693bcc 125 struct i915_vma *vma;
d7f46fc4
BW		 126 int pin_count = 0;
127
fb1ae911 128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
1d693bcc 132 get_global_flag(obj),
a05a5862 133 obj->base.size / 1024,
37811fcc
CW		 134 obj->base.read_domains,
135 obj->base.write_domain,
0201f1ec
CW		 136 obj->last_read_seqno,
137 obj->last_write_seqno,
caea7476 138 obj->last_fenced_seqno,
84734a04 139 i915_cache_level_str(obj->cache_level),
37811fcc
CW		 140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 148 if (obj->pin_display)
149 seq_printf(m, " (display)");
37811fcc
CW		 150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
c1ad11fc
CW		 160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
69dc4987
CW		 171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
d5a81ef1
DV		 173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 175}
176
273497e5 177static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 178{
ea0c76f8 179 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
181 seq_putc(m, ' ');
182}
183
433e12f7 184static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 185{
9f25d007 186 struct drm_info_node *node = m->private;
433e12f7
BG		 187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
2017263e 189 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 192 struct i915_vma *vma;
8f2480fb
CW		 193 size_t total_obj_size, total_gtt_size;
194 int count, ret;
de227ef0
CW		 195
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
197 if (ret)
198 return ret;
2017263e 199
ca191b13 200 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 201 switch (list) {
202 case ACTIVE_LIST:
267f0c90 203 seq_puts(m, "Active:\n");
5cef07e1 204 head = &vm->active_list;
433e12f7
BG		 205 break;
206 case INACTIVE_LIST:
267f0c90 207 seq_puts(m, "Inactive:\n");
5cef07e1 208 head = &vm->inactive_list;
433e12f7 209 break;
433e12f7 210 default:
de227ef0
CW		 211 mutex_unlock(&dev->struct_mutex);
212 return -EINVAL;
2017263e 213 }
2017263e 214
8f2480fb 215 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 216 list_for_each_entry(vma, head, mm_list) {
217 seq_printf(m, " ");
218 describe_obj(m, vma->obj);
219 seq_printf(m, "\n");
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
8f2480fb 222 count++;
2017263e 223 }
de227ef0 224 mutex_unlock(&dev->struct_mutex);
5e118f41 225
8f2480fb
CW		 226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
2017263e
BG		 228 return 0;
229}
230
6d2b8885
CW		 231static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
233{
234 struct drm_i915_gem_object *a =
b25cb2f8 235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 236 struct drm_i915_gem_object *b =
b25cb2f8 237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 238
239 return a->stolen->start - b->stolen->start;
240}
241
242static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
243{
9f25d007 244 struct drm_info_node *node = m->private;
6d2b8885
CW		 245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
249 LIST_HEAD(stolen);
250 int count, ret;
251
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
253 if (ret)
254 return ret;
255
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
259 continue;
260
b25cb2f8 261 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 262
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 count++;
266 }
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
269 continue;
270
b25cb2f8 271 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 272
273 total_obj_size += obj->base.size;
274 count++;
275 }
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
b25cb2f8 279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 280 seq_puts(m, " ");
281 describe_obj(m, obj);
282 seq_putc(m, '\n');
b25cb2f8 283 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 284 }
285 mutex_unlock(&dev->struct_mutex);
286
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
289 return 0;
290}
291
6299f992
CW		 292#define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
f343c5f6 294 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 295 ++count; \
296 if (obj->map_and_fenceable) { \
f343c5f6 297 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 298 ++mappable_count; \
299 } \
300 } \
0206e353 301} while (0)
6299f992 302
2db8e9d6 303struct file_stats {
6313c204 304 struct drm_i915_file_private *file_priv;
2db8e9d6 305 int count;
c67a17e9
CW		 306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
2db8e9d6
CW		 309};
310
311static int per_file_stats(int id, void *ptr, void *data)
312{
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
6313c204 315 struct i915_vma *vma;
2db8e9d6
CW		 316
317 stats->count++;
318 stats->total += obj->base.size;
319
c67a17e9
CW		 320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
322
6313c204
CW		 323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
326
327 if (!drm_mm_node_allocated(&vma->node))
328 continue;
329
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
332 continue;
333 }
334
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
336 if (ppgtt->ctx && ppgtt->ctx->file_priv != stats->file_priv)
337 continue;
338
339 if (obj->ring) /* XXX per-vma statistic */
340 stats->active += obj->base.size;
341 else
342 stats->inactive += obj->base.size;
343
344 return 0;
345 }
2db8e9d6 346 } else {
6313c204
CW		 347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
349 if (obj->ring)
350 stats->active += obj->base.size;
351 else
352 stats->inactive += obj->base.size;
353 return 0;
354 }
2db8e9d6
CW		 355 }
356
6313c204
CW		 357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
359
2db8e9d6
CW		 360 return 0;
361}
362
ca191b13
BW		 363#define count_vmas(list, member) do { \
364 list_for_each_entry(vma, list, member) { \
365 size += i915_gem_obj_ggtt_size(vma->obj); \
366 ++count; \
367 if (vma->obj->map_and_fenceable) { \
368 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
369 ++mappable_count; \
370 } \
371 } \
372} while (0)
373
374static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 375{
9f25d007 376 struct drm_info_node *node = m->private;
73aa808f
CW		 377 struct drm_device *dev = node->minor->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 379 u32 count, mappable_count, purgeable_count;
380 size_t size, mappable_size, purgeable_size;
6299f992 381 struct drm_i915_gem_object *obj;
5cef07e1 382 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 383 struct drm_file *file;
ca191b13 384 struct i915_vma *vma;
73aa808f
CW		 385 int ret;
386
387 ret = mutex_lock_interruptible(&dev->struct_mutex);
388 if (ret)
389 return ret;
390
6299f992
CW		 391 seq_printf(m, "%u objects, %zu bytes\n",
392 dev_priv->mm.object_count,
393 dev_priv->mm.object_memory);
394
395 size = count = mappable_size = mappable_count = 0;
35c20a60 396 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 397 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
398 count, mappable_count, size, mappable_size);
399
400 size = count = mappable_size = mappable_count = 0;
ca191b13 401 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 402 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
403 count, mappable_count, size, mappable_size);
404
6299f992 405 size = count = mappable_size = mappable_count = 0;
ca191b13 406 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 407 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
408 count, mappable_count, size, mappable_size);
409
b7abb714 410 size = count = purgeable_size = purgeable_count = 0;
35c20a60 411 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 412 size += obj->base.size, ++count;
b7abb714
CW		 413 if (obj->madv == I915_MADV_DONTNEED)
414 purgeable_size += obj->base.size, ++purgeable_count;
415 }
6c085a72
CW		 416 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
417
6299f992 418 size = count = mappable_size = mappable_count = 0;
35c20a60 419 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 420 if (obj->fault_mappable) {
f343c5f6 421 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 422 ++count;
423 }
424 if (obj->pin_mappable) {
f343c5f6 425 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 426 ++mappable_count;
427 }
b7abb714
CW		 428 if (obj->madv == I915_MADV_DONTNEED) {
429 purgeable_size += obj->base.size;
430 ++purgeable_count;
431 }
6299f992 432 }
b7abb714
CW		 433 seq_printf(m, "%u purgeable objects, %zu bytes\n",
434 purgeable_count, purgeable_size);
6299f992
CW		 435 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
436 mappable_count, mappable_size);
437 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
438 count, size);
439
93d18799 440 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 441 dev_priv->gtt.base.total,
442 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 443
267f0c90 444 seq_putc(m, '\n');
2db8e9d6
CW		 445 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
446 struct file_stats stats;
3ec2f427 447 struct task_struct *task;
2db8e9d6
CW		 448
449 memset(&stats, 0, sizeof(stats));
6313c204 450 stats.file_priv = file->driver_priv;
5b5ffff0 451 spin_lock(&file->table_lock);
2db8e9d6 452 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 453 spin_unlock(&file->table_lock);
3ec2f427
TH		 454 /*
455 * Although we have a valid reference on file->pid, that does
456 * not guarantee that the task_struct who called get_pid() is
457 * still alive (e.g. get_pid(current) => fork() => exit()).
458 * Therefore, we need to protect this ->comm access using RCU.
459 */
460 rcu_read_lock();
461 task = pid_task(file->pid, PIDTYPE_PID);
c67a17e9 462 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
3ec2f427 463 task ? task->comm : "<unknown>",
2db8e9d6
CW		 464 stats.count,
465 stats.total,
466 stats.active,
467 stats.inactive,
6313c204 468 stats.global,
c67a17e9 469 stats.shared,
2db8e9d6 470 stats.unbound);
3ec2f427 471 rcu_read_unlock();
2db8e9d6
CW		 472 }
473
73aa808f
CW		 474 mutex_unlock(&dev->struct_mutex);
475
476 return 0;
477}
478
aee56cff 479static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 480{
9f25d007 481 struct drm_info_node *node = m->private;
08c18323 482 struct drm_device *dev = node->minor->dev;
1b50247a 483 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 484 struct drm_i915_private *dev_priv = dev->dev_private;
485 struct drm_i915_gem_object *obj;
486 size_t total_obj_size, total_gtt_size;
487 int count, ret;
488
489 ret = mutex_lock_interruptible(&dev->struct_mutex);
490 if (ret)
491 return ret;
492
493 total_obj_size = total_gtt_size = count = 0;
35c20a60 494 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 495 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 496 continue;
497
267f0c90 498 seq_puts(m, " ");
08c18323 499 describe_obj(m, obj);
267f0c90 500 seq_putc(m, '\n');
08c18323 501 total_obj_size += obj->base.size;
f343c5f6 502 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 503 count++;
504 }
505
506 mutex_unlock(&dev->struct_mutex);
507
508 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
509 count, total_obj_size, total_gtt_size);
510
511 return 0;
512}
513
4e5359cd
SF		 514static int i915_gem_pageflip_info(struct seq_file *m, void *data)
515{
9f25d007 516 struct drm_info_node *node = m->private;
4e5359cd
SF		 517 struct drm_device *dev = node->minor->dev;
518 unsigned long flags;
519 struct intel_crtc *crtc;
8a270ebf
DV		 520 int ret;
521
522 ret = mutex_lock_interruptible(&dev->struct_mutex);
523 if (ret)
524 return ret;
4e5359cd 525
d3fcc808 526 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 527 const char pipe = pipe_name(crtc->pipe);
528 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 529 struct intel_unpin_work *work;
530
531 spin_lock_irqsave(&dev->event_lock, flags);
532 work = crtc->unpin_work;
533 if (work == NULL) {
9db4a9c7 534 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 535 pipe, plane);
536 } else {
e7d841ca 537 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 538 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 539 pipe, plane);
540 } else {
9db4a9c7 541 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 542 pipe, plane);
543 }
544 if (work->enable_stall_check)
267f0c90 545 seq_puts(m, "Stall check enabled, ");
4e5359cd 546 else
267f0c90 547 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 548 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd
SF		 549
550 if (work->old_fb_obj) {
05394f39
CW		 551 struct drm_i915_gem_object *obj = work->old_fb_obj;
552 if (obj)
f343c5f6
BW		 553 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
554 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 555 }
556 if (work->pending_flip_obj) {
05394f39
CW		 557 struct drm_i915_gem_object *obj = work->pending_flip_obj;
558 if (obj)
f343c5f6
BW		 559 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
560 i915_gem_obj_ggtt_offset(obj));
4e5359cd
SF		 561 }
562 }
563 spin_unlock_irqrestore(&dev->event_lock, flags);
564 }
565
8a270ebf
DV		 566 mutex_unlock(&dev->struct_mutex);
567
4e5359cd
SF		 568 return 0;
569}
570
2017263e
BG		 571static int i915_gem_request_info(struct seq_file *m, void *data)
572{
9f25d007 573 struct drm_info_node *node = m->private;
2017263e 574 struct drm_device *dev = node->minor->dev;
e277a1f8 575 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 576 struct intel_engine_cs *ring;
2017263e 577 struct drm_i915_gem_request *gem_request;
a2c7f6fd 578 int ret, count, i;
de227ef0
CW		 579
580 ret = mutex_lock_interruptible(&dev->struct_mutex);
581 if (ret)
582 return ret;
2017263e 583
c2c347a9 584 count = 0;
a2c7f6fd
CW		 585 for_each_ring(ring, dev_priv, i) {
586 if (list_empty(&ring->request_list))
587 continue;
588
589 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 590 list_for_each_entry(gem_request,
a2c7f6fd 591 &ring->request_list,
c2c347a9
CW		 592 list) {
593 seq_printf(m, " %d @ %d\n",
594 gem_request->seqno,
595 (int) (jiffies - gem_request->emitted_jiffies));
596 }
597 count++;
2017263e 598 }
de227ef0
CW		 599 mutex_unlock(&dev->struct_mutex);
600
c2c347a9 601 if (count == 0)
267f0c90 602 seq_puts(m, "No requests\n");
c2c347a9 603
2017263e
BG		 604 return 0;
605}
606
b2223497 607static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 608 struct intel_engine_cs *ring)
b2223497
CW		 609{
610 if (ring->get_seqno) {
43a7b924 611 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 612 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 613 }
614}
615
2017263e
BG		 616static int i915_gem_seqno_info(struct seq_file *m, void *data)
617{
9f25d007 618 struct drm_info_node *node = m->private;
2017263e 619 struct drm_device *dev = node->minor->dev;
e277a1f8 620 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 621 struct intel_engine_cs *ring;
1ec14ad3 622 int ret, i;
de227ef0
CW		 623
624 ret = mutex_lock_interruptible(&dev->struct_mutex);
625 if (ret)
626 return ret;
c8c8fb33 627 intel_runtime_pm_get(dev_priv);
2017263e 628
a2c7f6fd
CW		 629 for_each_ring(ring, dev_priv, i)
630 i915_ring_seqno_info(m, ring);
de227ef0 631
c8c8fb33 632 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 633 mutex_unlock(&dev->struct_mutex);
634
2017263e
BG		 635 return 0;
636}
637
638
639static int i915_interrupt_info(struct seq_file *m, void *data)
640{
9f25d007 641 struct drm_info_node *node = m->private;
2017263e 642 struct drm_device *dev = node->minor->dev;
e277a1f8 643 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 644 struct intel_engine_cs *ring;
9db4a9c7 645 int ret, i, pipe;
de227ef0
CW		 646
647 ret = mutex_lock_interruptible(&dev->struct_mutex);
648 if (ret)
649 return ret;
c8c8fb33 650 intel_runtime_pm_get(dev_priv);
2017263e 651
74e1ca8c
VS		 652 if (IS_CHERRYVIEW(dev)) {
653 int i;
654 seq_printf(m, "Master Interrupt Control:\t%08x\n",
655 I915_READ(GEN8_MASTER_IRQ));
656
657 seq_printf(m, "Display IER:\t%08x\n",
658 I915_READ(VLV_IER));
659 seq_printf(m, "Display IIR:\t%08x\n",
660 I915_READ(VLV_IIR));
661 seq_printf(m, "Display IIR_RW:\t%08x\n",
662 I915_READ(VLV_IIR_RW));
663 seq_printf(m, "Display IMR:\t%08x\n",
664 I915_READ(VLV_IMR));
665 for_each_pipe(pipe)
666 seq_printf(m, "Pipe %c stat:\t%08x\n",
667 pipe_name(pipe),
668 I915_READ(PIPESTAT(pipe)));
669
670 seq_printf(m, "Port hotplug:\t%08x\n",
671 I915_READ(PORT_HOTPLUG_EN));
672 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
673 I915_READ(VLV_DPFLIPSTAT));
674 seq_printf(m, "DPINVGTT:\t%08x\n",
675 I915_READ(DPINVGTT));
676
677 for (i = 0; i < 4; i++) {
678 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
679 i, I915_READ(GEN8_GT_IMR(i)));
680 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
681 i, I915_READ(GEN8_GT_IIR(i)));
682 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
683 i, I915_READ(GEN8_GT_IER(i)));
684 }
685
686 seq_printf(m, "PCU interrupt mask:\t%08x\n",
687 I915_READ(GEN8_PCU_IMR));
688 seq_printf(m, "PCU interrupt identity:\t%08x\n",
689 I915_READ(GEN8_PCU_IIR));
690 seq_printf(m, "PCU interrupt enable:\t%08x\n",
691 I915_READ(GEN8_PCU_IER));
692 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 693 seq_printf(m, "Master Interrupt Control:\t%08x\n",
694 I915_READ(GEN8_MASTER_IRQ));
695
696 for (i = 0; i < 4; i++) {
697 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
698 i, I915_READ(GEN8_GT_IMR(i)));
699 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
700 i, I915_READ(GEN8_GT_IIR(i)));
701 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
702 i, I915_READ(GEN8_GT_IER(i)));
703 }
704
07d27e20 705 for_each_pipe(pipe) {
a123f157 706 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 707 pipe_name(pipe),
708 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 709 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 710 pipe_name(pipe),
711 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 712 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 713 pipe_name(pipe),
714 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 715 }
716
717 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
718 I915_READ(GEN8_DE_PORT_IMR));
719 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
720 I915_READ(GEN8_DE_PORT_IIR));
721 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
722 I915_READ(GEN8_DE_PORT_IER));
723
724 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
725 I915_READ(GEN8_DE_MISC_IMR));
726 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
727 I915_READ(GEN8_DE_MISC_IIR));
728 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
729 I915_READ(GEN8_DE_MISC_IER));
730
731 seq_printf(m, "PCU interrupt mask:\t%08x\n",
732 I915_READ(GEN8_PCU_IMR));
733 seq_printf(m, "PCU interrupt identity:\t%08x\n",
734 I915_READ(GEN8_PCU_IIR));
735 seq_printf(m, "PCU interrupt enable:\t%08x\n",
736 I915_READ(GEN8_PCU_IER));
737 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 738 seq_printf(m, "Display IER:\t%08x\n",
739 I915_READ(VLV_IER));
740 seq_printf(m, "Display IIR:\t%08x\n",
741 I915_READ(VLV_IIR));
742 seq_printf(m, "Display IIR_RW:\t%08x\n",
743 I915_READ(VLV_IIR_RW));
744 seq_printf(m, "Display IMR:\t%08x\n",
745 I915_READ(VLV_IMR));
746 for_each_pipe(pipe)
747 seq_printf(m, "Pipe %c stat:\t%08x\n",
748 pipe_name(pipe),
749 I915_READ(PIPESTAT(pipe)));
750
751 seq_printf(m, "Master IER:\t%08x\n",
752 I915_READ(VLV_MASTER_IER));
753
754 seq_printf(m, "Render IER:\t%08x\n",
755 I915_READ(GTIER));
756 seq_printf(m, "Render IIR:\t%08x\n",
757 I915_READ(GTIIR));
758 seq_printf(m, "Render IMR:\t%08x\n",
759 I915_READ(GTIMR));
760
761 seq_printf(m, "PM IER:\t\t%08x\n",
762 I915_READ(GEN6_PMIER));
763 seq_printf(m, "PM IIR:\t\t%08x\n",
764 I915_READ(GEN6_PMIIR));
765 seq_printf(m, "PM IMR:\t\t%08x\n",
766 I915_READ(GEN6_PMIMR));
767
768 seq_printf(m, "Port hotplug:\t%08x\n",
769 I915_READ(PORT_HOTPLUG_EN));
770 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
771 I915_READ(VLV_DPFLIPSTAT));
772 seq_printf(m, "DPINVGTT:\t%08x\n",
773 I915_READ(DPINVGTT));
774
775 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 776 seq_printf(m, "Interrupt enable: %08x\n",
777 I915_READ(IER));
778 seq_printf(m, "Interrupt identity: %08x\n",
779 I915_READ(IIR));
780 seq_printf(m, "Interrupt mask: %08x\n",
781 I915_READ(IMR));
9db4a9c7
JB		 782 for_each_pipe(pipe)
783 seq_printf(m, "Pipe %c stat: %08x\n",
784 pipe_name(pipe),
785 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 786 } else {
787 seq_printf(m, "North Display Interrupt enable: %08x\n",
788 I915_READ(DEIER));
789 seq_printf(m, "North Display Interrupt identity: %08x\n",
790 I915_READ(DEIIR));
791 seq_printf(m, "North Display Interrupt mask: %08x\n",
792 I915_READ(DEIMR));
793 seq_printf(m, "South Display Interrupt enable: %08x\n",
794 I915_READ(SDEIER));
795 seq_printf(m, "South Display Interrupt identity: %08x\n",
796 I915_READ(SDEIIR));
797 seq_printf(m, "South Display Interrupt mask: %08x\n",
798 I915_READ(SDEIMR));
799 seq_printf(m, "Graphics Interrupt enable: %08x\n",
800 I915_READ(GTIER));
801 seq_printf(m, "Graphics Interrupt identity: %08x\n",
802 I915_READ(GTIIR));
803 seq_printf(m, "Graphics Interrupt mask: %08x\n",
804 I915_READ(GTIMR));
805 }
a2c7f6fd 806 for_each_ring(ring, dev_priv, i) {
a123f157 807 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 808 seq_printf(m,
809 "Graphics Interrupt mask (%s): %08x\n",
810 ring->name, I915_READ_IMR(ring));
9862e600 811 }
a2c7f6fd 812 i915_ring_seqno_info(m, ring);
9862e600 813 }
c8c8fb33 814 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 815 mutex_unlock(&dev->struct_mutex);
816
2017263e
BG		 817 return 0;
818}
819
a6172a80
CW		 820static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
821{
9f25d007 822 struct drm_info_node *node = m->private;
a6172a80 823 struct drm_device *dev = node->minor->dev;
e277a1f8 824 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 825 int i, ret;
826
827 ret = mutex_lock_interruptible(&dev->struct_mutex);
828 if (ret)
829 return ret;
a6172a80
CW		 830
831 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
832 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
833 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 834 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 835
6c085a72
CW		 836 seq_printf(m, "Fence %d, pin count = %d, object = ",
837 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 838 if (obj == NULL)
267f0c90 839 seq_puts(m, "unused");
c2c347a9 840 else
05394f39 841 describe_obj(m, obj);
267f0c90 842 seq_putc(m, '\n');
a6172a80
CW		 843 }
844
05394f39 845 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 846 return 0;
847}
848
2017263e
BG		 849static int i915_hws_info(struct seq_file *m, void *data)
850{
9f25d007 851 struct drm_info_node *node = m->private;
2017263e 852 struct drm_device *dev = node->minor->dev;
e277a1f8 853 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 854 struct intel_engine_cs *ring;
1a240d4d 855 const u32 *hws;
4066c0ae
CW		 856 int i;
857
1ec14ad3 858 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 859 hws = ring->status_page.page_addr;
2017263e
BG		 860 if (hws == NULL)
861 return 0;
862
863 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
864 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
865 i * 4,
866 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
867 }
868 return 0;
869}
870
d5442303
DV		 871static ssize_t
872i915_error_state_write(struct file *filp,
873 const char __user *ubuf,
874 size_t cnt,
875 loff_t *ppos)
876{
edc3d884 877 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 878 struct drm_device *dev = error_priv->dev;
22bcfc6a 879 int ret;
d5442303
DV		 880
881 DRM_DEBUG_DRIVER("Resetting error state\n");
882
22bcfc6a
DV		 883 ret = mutex_lock_interruptible(&dev->struct_mutex);
884 if (ret)
885 return ret;
886
d5442303
DV		 887 i915_destroy_error_state(dev);
888 mutex_unlock(&dev->struct_mutex);
889
890 return cnt;
891}
892
893static int i915_error_state_open(struct inode *inode, struct file *file)
894{
895 struct drm_device *dev = inode->i_private;
d5442303 896 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 897
898 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
899 if (!error_priv)
900 return -ENOMEM;
901
902 error_priv->dev = dev;
903
95d5bfb3 904 i915_error_state_get(dev, error_priv);
d5442303 905
edc3d884
MK		 906 file->private_data = error_priv;
907
908 return 0;
d5442303
DV		 909}
910
911static int i915_error_state_release(struct inode *inode, struct file *file)
912{
edc3d884 913 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 914
95d5bfb3 915 i915_error_state_put(error_priv);
d5442303
DV		 916 kfree(error_priv);
917
edc3d884
MK		 918 return 0;
919}
920
4dc955f7
MK		 921static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
922 size_t count, loff_t *pos)
923{
924 struct i915_error_state_file_priv *error_priv = file->private_data;
925 struct drm_i915_error_state_buf error_str;
926 loff_t tmp_pos = 0;
927 ssize_t ret_count = 0;
928 int ret;
929
930 ret = i915_error_state_buf_init(&error_str, count, *pos);
931 if (ret)
932 return ret;
edc3d884 933
fc16b48b 934 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 935 if (ret)
936 goto out;
937
edc3d884
MK		 938 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
939 error_str.buf,
940 error_str.bytes);
941
942 if (ret_count < 0)
943 ret = ret_count;
944 else
945 *pos = error_str.start + ret_count;
946out:
4dc955f7 947 i915_error_state_buf_release(&error_str);
edc3d884 948 return ret ?: ret_count;
d5442303
DV		 949}
950
951static const struct file_operations i915_error_state_fops = {
952 .owner = THIS_MODULE,
953 .open = i915_error_state_open,
edc3d884 954 .read = i915_error_state_read,
d5442303
DV		 955 .write = i915_error_state_write,
956 .llseek = default_llseek,
957 .release = i915_error_state_release,
958};
959
647416f9
KC		 960static int
961i915_next_seqno_get(void *data, u64 *val)
40633219 962{
647416f9 963 struct drm_device *dev = data;
e277a1f8 964 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 965 int ret;
966
967 ret = mutex_lock_interruptible(&dev->struct_mutex);
968 if (ret)
969 return ret;
970
647416f9 971 *val = dev_priv->next_seqno;
40633219
MK		 972 mutex_unlock(&dev->struct_mutex);
973
647416f9 974 return 0;
40633219
MK		 975}
976
647416f9
KC		 977static int
978i915_next_seqno_set(void *data, u64 val)
979{
980 struct drm_device *dev = data;
40633219
MK		 981 int ret;
982
40633219
MK		 983 ret = mutex_lock_interruptible(&dev->struct_mutex);
984 if (ret)
985 return ret;
986
e94fbaa8 987 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 988 mutex_unlock(&dev->struct_mutex);
989
647416f9 990 return ret;
40633219
MK		 991}
992
647416f9
KC		 993DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
994 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 995 "0x%llx\n");
40633219 996
adb4bd12 997static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 998{
9f25d007 999 struct drm_info_node *node = m->private;
f97108d1 1000 struct drm_device *dev = node->minor->dev;
e277a1f8 1001 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1002 int ret = 0;
1003
1004 intel_runtime_pm_get(dev_priv);
3b8d8d91 1005
5c9669ce
TR		 1006 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1007
3b8d8d91
JB		 1008 if (IS_GEN5(dev)) {
1009 u16 rgvswctl = I915_READ16(MEMSWCTL);
1010 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1011
1012 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1013 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1014 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1015 MEMSTAT_VID_SHIFT);
1016 seq_printf(m, "Current P-state: %d\n",
1017 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2
TR		 1018 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1019 IS_BROADWELL(dev)) {
3b8d8d91
JB		 1020 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1021 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1022 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1023 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1024 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1025 u32 rpupei, rpcurup, rpprevup;
1026 u32 rpdownei, rpcurdown, rpprevdown;
3b8d8d91
JB		 1027 int max_freq;
1028
1029 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1030 ret = mutex_lock_interruptible(&dev->struct_mutex);
1031 if (ret)
c8c8fb33 1032 goto out;
d1ebd816 1033
c8d9a590 1034 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1035
8e8c06cd
CW		 1036 reqf = I915_READ(GEN6_RPNSWREQ);
1037 reqf &= ~GEN6_TURBO_DISABLE;
daa3afb2 1038 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8e8c06cd
CW		 1039 reqf >>= 24;
1040 else
1041 reqf >>= 25;
1042 reqf *= GT_FREQUENCY_MULTIPLIER;
1043
0d8f9491
CW		 1044 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1045 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1046 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1047
ccab5c82
JB		 1048 rpstat = I915_READ(GEN6_RPSTAT1);
1049 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1050 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1051 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1052 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1053 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1054 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
daa3afb2 1055 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1056 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1057 else
1058 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1059 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 1060
c8d9a590 1061 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1062 mutex_unlock(&dev->struct_mutex);
1063
0d8f9491
CW		 1064 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1065 I915_READ(GEN6_PMIER),
1066 I915_READ(GEN6_PMIMR),
1067 I915_READ(GEN6_PMISR),
1068 I915_READ(GEN6_PMIIR),
1069 I915_READ(GEN6_PMINTRMSK));
3b8d8d91 1070 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1071 seq_printf(m, "Render p-state ratio: %d\n",
1072 (gt_perf_status & 0xff00) >> 8);
1073 seq_printf(m, "Render p-state VID: %d\n",
1074 gt_perf_status & 0xff);
1075 seq_printf(m, "Render p-state limit: %d\n",
1076 rp_state_limits & 0xff);
0d8f9491
CW		 1077 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1078 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1079 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1080 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1081 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1082 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1083 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1084 GEN6_CURICONT_MASK);
1085 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1086 GEN6_CURBSYTAVG_MASK);
1087 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1088 GEN6_CURBSYTAVG_MASK);
1089 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1090 GEN6_CURIAVG_MASK);
1091 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1092 GEN6_CURBSYTAVG_MASK);
1093 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1094 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1095
1096 max_freq = (rp_state_cap & 0xff0000) >> 16;
1097 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1098 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1099
1100 max_freq = (rp_state_cap & 0xff00) >> 8;
1101 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1102 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1103
1104 max_freq = rp_state_cap & 0xff;
1105 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1106 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1107
1108 seq_printf(m, "Max overclocked frequency: %dMHz\n",
b39fb297 1109 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
0a073b84
JB		 1110 } else if (IS_VALLEYVIEW(dev)) {
1111 u32 freq_sts, val;
1112
259bd5d4 1113 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1114 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1115 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1116 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1117
c5bd2bf6 1118 val = valleyview_rps_max_freq(dev_priv);
0a073b84 1119 seq_printf(m, "max GPU freq: %d MHz\n",
2ec3815f 1120 vlv_gpu_freq(dev_priv, val));
0a073b84 1121
c5bd2bf6 1122 val = valleyview_rps_min_freq(dev_priv);
0a073b84 1123 seq_printf(m, "min GPU freq: %d MHz\n",
2ec3815f 1124 vlv_gpu_freq(dev_priv, val));
0a073b84
JB		 1125
1126 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1127 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1128 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1129 } else {
267f0c90 1130 seq_puts(m, "no P-state info available\n");
3b8d8d91 1131 }
f97108d1 1132
c8c8fb33
PZ		 1133out:
1134 intel_runtime_pm_put(dev_priv);
1135 return ret;
f97108d1
JB		 1136}
1137
4d85529d 1138static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1139{
9f25d007 1140 struct drm_info_node *node = m->private;
f97108d1 1141 struct drm_device *dev = node->minor->dev;
e277a1f8 1142 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1143 u32 rgvmodectl, rstdbyctl;
1144 u16 crstandvid;
1145 int ret;
1146
1147 ret = mutex_lock_interruptible(&dev->struct_mutex);
1148 if (ret)
1149 return ret;
c8c8fb33 1150 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1151
1152 rgvmodectl = I915_READ(MEMMODECTL);
1153 rstdbyctl = I915_READ(RSTDBYCTL);
1154 crstandvid = I915_READ16(CRSTANDVID);
1155
c8c8fb33 1156 intel_runtime_pm_put(dev_priv);
616fdb5a 1157 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1158
1159 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1160 "yes" : "no");
1161 seq_printf(m, "Boost freq: %d\n",
1162 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1163 MEMMODE_BOOST_FREQ_SHIFT);
1164 seq_printf(m, "HW control enabled: %s\n",
1165 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1166 seq_printf(m, "SW control enabled: %s\n",
1167 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1168 seq_printf(m, "Gated voltage change: %s\n",
1169 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1170 seq_printf(m, "Starting frequency: P%d\n",
1171 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1172 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1173 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1174 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1175 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1176 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1177 seq_printf(m, "Render standby enabled: %s\n",
1178 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1179 seq_puts(m, "Current RS state: ");
88271da3
JB		 1180 switch (rstdbyctl & RSX_STATUS_MASK) {
1181 case RSX_STATUS_ON:
267f0c90 1182 seq_puts(m, "on\n");
88271da3
JB		 1183 break;
1184 case RSX_STATUS_RC1:
267f0c90 1185 seq_puts(m, "RC1\n");
88271da3
JB		 1186 break;
1187 case RSX_STATUS_RC1E:
267f0c90 1188 seq_puts(m, "RC1E\n");
88271da3
JB		 1189 break;
1190 case RSX_STATUS_RS1:
267f0c90 1191 seq_puts(m, "RS1\n");
88271da3
JB		 1192 break;
1193 case RSX_STATUS_RS2:
267f0c90 1194 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1195 break;
1196 case RSX_STATUS_RS3:
267f0c90 1197 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1198 break;
1199 default:
267f0c90 1200 seq_puts(m, "unknown\n");
88271da3
JB		 1201 break;
1202 }
f97108d1
JB		 1203
1204 return 0;
1205}
1206
669ab5aa
D		 1207static int vlv_drpc_info(struct seq_file *m)
1208{
1209
9f25d007 1210 struct drm_info_node *node = m->private;
669ab5aa
D		 1211 struct drm_device *dev = node->minor->dev;
1212 struct drm_i915_private *dev_priv = dev->dev_private;
1213 u32 rpmodectl1, rcctl1;
1214 unsigned fw_rendercount = 0, fw_mediacount = 0;
1215
d46c0517
ID		 1216 intel_runtime_pm_get(dev_priv);
1217
669ab5aa
D		 1218 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1219 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1220
d46c0517
ID		 1221 intel_runtime_pm_put(dev_priv);
1222
669ab5aa
D		 1223 seq_printf(m, "Video Turbo Mode: %s\n",
1224 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1225 seq_printf(m, "Turbo enabled: %s\n",
1226 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1227 seq_printf(m, "HW control enabled: %s\n",
1228 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1229 seq_printf(m, "SW control enabled: %s\n",
1230 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1231 GEN6_RP_MEDIA_SW_MODE));
1232 seq_printf(m, "RC6 Enabled: %s\n",
1233 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1234 GEN6_RC_CTL_EI_MODE(1))));
1235 seq_printf(m, "Render Power Well: %s\n",
1236 (I915_READ(VLV_GTLC_PW_STATUS) &
1237 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1238 seq_printf(m, "Media Power Well: %s\n",
1239 (I915_READ(VLV_GTLC_PW_STATUS) &
1240 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1241
9cc19be5
ID		 1242 seq_printf(m, "Render RC6 residency since boot: %u\n",
1243 I915_READ(VLV_GT_RENDER_RC6));
1244 seq_printf(m, "Media RC6 residency since boot: %u\n",
1245 I915_READ(VLV_GT_MEDIA_RC6));
1246
669ab5aa
D		 1247 spin_lock_irq(&dev_priv->uncore.lock);
1248 fw_rendercount = dev_priv->uncore.fw_rendercount;
1249 fw_mediacount = dev_priv->uncore.fw_mediacount;
1250 spin_unlock_irq(&dev_priv->uncore.lock);
1251
1252 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1253 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1254
1255
1256 return 0;
1257}
1258
1259
4d85529d
BW		 1260static int gen6_drpc_info(struct seq_file *m)
1261{
1262
9f25d007 1263 struct drm_info_node *node = m->private;
4d85529d
BW		 1264 struct drm_device *dev = node->minor->dev;
1265 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1266 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1267 unsigned forcewake_count;
aee56cff 1268 int count = 0, ret;
4d85529d
BW		 1269
1270 ret = mutex_lock_interruptible(&dev->struct_mutex);
1271 if (ret)
1272 return ret;
c8c8fb33 1273 intel_runtime_pm_get(dev_priv);
4d85529d 1274
907b28c5
CW		 1275 spin_lock_irq(&dev_priv->uncore.lock);
1276 forcewake_count = dev_priv->uncore.forcewake_count;
1277 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1278
1279 if (forcewake_count) {
267f0c90
DL		 1280 seq_puts(m, "RC information inaccurate because somebody "
1281 "holds a forcewake reference \n");
4d85529d
BW		 1282 } else {
1283 /* NB: we cannot use forcewake, else we read the wrong values */
1284 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1285 udelay(10);
1286 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1287 }
1288
1289 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1290 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1291
1292 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1293 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1294 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1295 mutex_lock(&dev_priv->rps.hw_lock);
1296 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1297 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1298
c8c8fb33
PZ		 1299 intel_runtime_pm_put(dev_priv);
1300
4d85529d
BW		 1301 seq_printf(m, "Video Turbo Mode: %s\n",
1302 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1303 seq_printf(m, "HW control enabled: %s\n",
1304 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1305 seq_printf(m, "SW control enabled: %s\n",
1306 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1307 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1308 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1309 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1310 seq_printf(m, "RC6 Enabled: %s\n",
1311 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1312 seq_printf(m, "Deep RC6 Enabled: %s\n",
1313 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1314 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1315 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1316 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1317 switch (gt_core_status & GEN6_RCn_MASK) {
1318 case GEN6_RC0:
1319 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1320 seq_puts(m, "Core Power Down\n");
4d85529d 1321 else
267f0c90 1322 seq_puts(m, "on\n");
4d85529d
BW		 1323 break;
1324 case GEN6_RC3:
267f0c90 1325 seq_puts(m, "RC3\n");
4d85529d
BW		 1326 break;
1327 case GEN6_RC6:
267f0c90 1328 seq_puts(m, "RC6\n");
4d85529d
BW		 1329 break;
1330 case GEN6_RC7:
267f0c90 1331 seq_puts(m, "RC7\n");
4d85529d
BW		 1332 break;
1333 default:
267f0c90 1334 seq_puts(m, "Unknown\n");
4d85529d
BW		 1335 break;
1336 }
1337
1338 seq_printf(m, "Core Power Down: %s\n",
1339 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1340
1341 /* Not exactly sure what this is */
1342 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1343 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1344 seq_printf(m, "RC6 residency since boot: %u\n",
1345 I915_READ(GEN6_GT_GFX_RC6));
1346 seq_printf(m, "RC6+ residency since boot: %u\n",
1347 I915_READ(GEN6_GT_GFX_RC6p));
1348 seq_printf(m, "RC6++ residency since boot: %u\n",
1349 I915_READ(GEN6_GT_GFX_RC6pp));
1350
ecd8faea
BW		 1351 seq_printf(m, "RC6 voltage: %dmV\n",
1352 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1353 seq_printf(m, "RC6+ voltage: %dmV\n",
1354 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1355 seq_printf(m, "RC6++ voltage: %dmV\n",
1356 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1357 return 0;
1358}
1359
1360static int i915_drpc_info(struct seq_file *m, void *unused)
1361{
9f25d007 1362 struct drm_info_node *node = m->private;
4d85529d
BW		 1363 struct drm_device *dev = node->minor->dev;
1364
669ab5aa
D		 1365 if (IS_VALLEYVIEW(dev))
1366 return vlv_drpc_info(m);
1367 else if (IS_GEN6(dev) || IS_GEN7(dev))
4d85529d
BW		 1368 return gen6_drpc_info(m);
1369 else
1370 return ironlake_drpc_info(m);
1371}
1372
b5e50c3f
JB		 1373static int i915_fbc_status(struct seq_file *m, void *unused)
1374{
9f25d007 1375 struct drm_info_node *node = m->private;
b5e50c3f 1376 struct drm_device *dev = node->minor->dev;
e277a1f8 1377 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1378
3a77c4c4 1379 if (!HAS_FBC(dev)) {
267f0c90 1380 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1381 return 0;
1382 }
1383
36623ef8
PZ		 1384 intel_runtime_pm_get(dev_priv);
1385
ee5382ae 1386 if (intel_fbc_enabled(dev)) {
267f0c90 1387 seq_puts(m, "FBC enabled\n");
b5e50c3f 1388 } else {
267f0c90 1389 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1390 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1391 case FBC_OK:
1392 seq_puts(m, "FBC actived, but currently disabled in hardware");
1393 break;
1394 case FBC_UNSUPPORTED:
1395 seq_puts(m, "unsupported by this chipset");
1396 break;
bed4a673 1397 case FBC_NO_OUTPUT:
267f0c90 1398 seq_puts(m, "no outputs");
bed4a673 1399 break;
b5e50c3f 1400 case FBC_STOLEN_TOO_SMALL:
267f0c90 1401 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1402 break;
1403 case FBC_UNSUPPORTED_MODE:
267f0c90 1404 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1405 break;
1406 case FBC_MODE_TOO_LARGE:
267f0c90 1407 seq_puts(m, "mode too large");
b5e50c3f
JB		 1408 break;
1409 case FBC_BAD_PLANE:
267f0c90 1410 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1411 break;
1412 case FBC_NOT_TILED:
267f0c90 1413 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1414 break;
9c928d16 1415 case FBC_MULTIPLE_PIPES:
267f0c90 1416 seq_puts(m, "multiple pipes are enabled");
9c928d16 1417 break;
c1a9f047 1418 case FBC_MODULE_PARAM:
267f0c90 1419 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1420 break;
8a5729a3 1421 case FBC_CHIP_DEFAULT:
267f0c90 1422 seq_puts(m, "disabled per chip default");
8a5729a3 1423 break;
b5e50c3f 1424 default:
267f0c90 1425 seq_puts(m, "unknown reason");
b5e50c3f 1426 }
267f0c90 1427 seq_putc(m, '\n');
b5e50c3f 1428 }
36623ef8
PZ		 1429
1430 intel_runtime_pm_put(dev_priv);
1431
b5e50c3f
JB		 1432 return 0;
1433}
1434
92d44621
PZ		 1435static int i915_ips_status(struct seq_file *m, void *unused)
1436{
9f25d007 1437 struct drm_info_node *node = m->private;
92d44621
PZ		 1438 struct drm_device *dev = node->minor->dev;
1439 struct drm_i915_private *dev_priv = dev->dev_private;
1440
f5adf94e 1441 if (!HAS_IPS(dev)) {
92d44621
PZ		 1442 seq_puts(m, "not supported\n");
1443 return 0;
1444 }
1445
36623ef8
PZ		 1446 intel_runtime_pm_get(dev_priv);
1447
0eaa53f0
RV		 1448 seq_printf(m, "Enabled by kernel parameter: %s\n",
1449 yesno(i915.enable_ips));
1450
1451 if (INTEL_INFO(dev)->gen >= 8) {
1452 seq_puts(m, "Currently: unknown\n");
1453 } else {
1454 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1455 seq_puts(m, "Currently: enabled\n");
1456 else
1457 seq_puts(m, "Currently: disabled\n");
1458 }
92d44621 1459
36623ef8
PZ		 1460 intel_runtime_pm_put(dev_priv);
1461
92d44621
PZ		 1462 return 0;
1463}
1464
4a9bef37
JB		 1465static int i915_sr_status(struct seq_file *m, void *unused)
1466{
9f25d007 1467 struct drm_info_node *node = m->private;
4a9bef37 1468 struct drm_device *dev = node->minor->dev;
e277a1f8 1469 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1470 bool sr_enabled = false;
1471
36623ef8
PZ		 1472 intel_runtime_pm_get(dev_priv);
1473
1398261a 1474 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1475 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1476 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1477 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1478 else if (IS_I915GM(dev))
1479 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1480 else if (IS_PINEVIEW(dev))
1481 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1482
36623ef8
PZ		 1483 intel_runtime_pm_put(dev_priv);
1484
5ba2aaaa
CW		 1485 seq_printf(m, "self-refresh: %s\n",
1486 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1487
1488 return 0;
1489}
1490
7648fa99
JB		 1491static int i915_emon_status(struct seq_file *m, void *unused)
1492{
9f25d007 1493 struct drm_info_node *node = m->private;
7648fa99 1494 struct drm_device *dev = node->minor->dev;
e277a1f8 1495 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1496 unsigned long temp, chipset, gfx;
de227ef0
CW		 1497 int ret;
1498
582be6b4
CW		 1499 if (!IS_GEN5(dev))
1500 return -ENODEV;
1501
de227ef0
CW		 1502 ret = mutex_lock_interruptible(&dev->struct_mutex);
1503 if (ret)
1504 return ret;
7648fa99
JB		 1505
1506 temp = i915_mch_val(dev_priv);
1507 chipset = i915_chipset_val(dev_priv);
1508 gfx = i915_gfx_val(dev_priv);
de227ef0 1509 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1510
1511 seq_printf(m, "GMCH temp: %ld\n", temp);
1512 seq_printf(m, "Chipset power: %ld\n", chipset);
1513 seq_printf(m, "GFX power: %ld\n", gfx);
1514 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1515
1516 return 0;
1517}
1518
23b2f8bb
JB		 1519static int i915_ring_freq_table(struct seq_file *m, void *unused)
1520{
9f25d007 1521 struct drm_info_node *node = m->private;
23b2f8bb 1522 struct drm_device *dev = node->minor->dev;
e277a1f8 1523 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1524 int ret = 0;
23b2f8bb
JB		 1525 int gpu_freq, ia_freq;
1526
1c70c0ce 1527 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1528 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1529 return 0;
1530 }
1531
5bfa0199
PZ		 1532 intel_runtime_pm_get(dev_priv);
1533
5c9669ce
TR		 1534 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1535
4fc688ce 1536 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1537 if (ret)
5bfa0199 1538 goto out;
23b2f8bb 1539
267f0c90 1540 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1541
b39fb297
BW		 1542 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1543 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1544 gpu_freq++) {
42c0526c
BW		 1545 ia_freq = gpu_freq;
1546 sandybridge_pcode_read(dev_priv,
1547 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1548 &ia_freq);
3ebecd07
CW		 1549 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1550 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1551 ((ia_freq >> 0) & 0xff) * 100,
1552 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1553 }
1554
4fc688ce 1555 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1556
5bfa0199
PZ		 1557out:
1558 intel_runtime_pm_put(dev_priv);
1559 return ret;
23b2f8bb
JB		 1560}
1561
44834a67
CW		 1562static int i915_opregion(struct seq_file *m, void *unused)
1563{
9f25d007 1564 struct drm_info_node *node = m->private;
44834a67 1565 struct drm_device *dev = node->minor->dev;
e277a1f8 1566 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1567 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1568 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1569 int ret;
1570
0d38f009
DV		 1571 if (data == NULL)
1572 return -ENOMEM;
1573
44834a67
CW		 1574 ret = mutex_lock_interruptible(&dev->struct_mutex);
1575 if (ret)
0d38f009 1576 goto out;
44834a67 1577
0d38f009
DV		 1578 if (opregion->header) {
1579 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1580 seq_write(m, data, OPREGION_SIZE);
1581 }
44834a67
CW		 1582
1583 mutex_unlock(&dev->struct_mutex);
1584
0d38f009
DV		 1585out:
1586 kfree(data);
44834a67
CW		 1587 return 0;
1588}
1589
37811fcc
CW		 1590static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1591{
9f25d007 1592 struct drm_info_node *node = m->private;
37811fcc 1593 struct drm_device *dev = node->minor->dev;
4520f53a 1594 struct intel_fbdev *ifbdev = NULL;
37811fcc 1595 struct intel_framebuffer *fb;
37811fcc 1596
4520f53a
DV		 1597#ifdef CONFIG_DRM_I915_FBDEV
1598 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1599
1600 ifbdev = dev_priv->fbdev;
1601 fb = to_intel_framebuffer(ifbdev->helper.fb);
1602
623f9783 1603 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1604 fb->base.width,
1605 fb->base.height,
1606 fb->base.depth,
623f9783
DV		 1607 fb->base.bits_per_pixel,
1608 atomic_read(&fb->base.refcount.refcount));
05394f39 1609 describe_obj(m, fb->obj);
267f0c90 1610 seq_putc(m, '\n');
4520f53a 1611#endif
37811fcc 1612
4b096ac1 1613 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1614 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1615 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1616 continue;
1617
623f9783 1618 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1619 fb->base.width,
1620 fb->base.height,
1621 fb->base.depth,
623f9783
DV		 1622 fb->base.bits_per_pixel,
1623 atomic_read(&fb->base.refcount.refcount));
05394f39 1624 describe_obj(m, fb->obj);
267f0c90 1625 seq_putc(m, '\n');
37811fcc 1626 }
4b096ac1 1627 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1628
1629 return 0;
1630}
1631
e76d3630
BW		 1632static int i915_context_status(struct seq_file *m, void *unused)
1633{
9f25d007 1634 struct drm_info_node *node = m->private;
e76d3630 1635 struct drm_device *dev = node->minor->dev;
e277a1f8 1636 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1637 struct intel_engine_cs *ring;
273497e5 1638 struct intel_context *ctx;
a168c293 1639 int ret, i;
e76d3630 1640
f3d28878 1641 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1642 if (ret)
1643 return ret;
1644
3e373948 1645 if (dev_priv->ips.pwrctx) {
267f0c90 1646 seq_puts(m, "power context ");
3e373948 1647 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1648 seq_putc(m, '\n');
dc501fbc 1649 }
e76d3630 1650
3e373948 1651 if (dev_priv->ips.renderctx) {
267f0c90 1652 seq_puts(m, "render context ");
3e373948 1653 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1654 seq_putc(m, '\n');
dc501fbc 1655 }
e76d3630 1656
a33afea5 1657 list_for_each_entry(ctx, &dev_priv->context_list, link) {
ea0c76f8 1658 if (ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1659 continue;
1660
a33afea5 1661 seq_puts(m, "HW context ");
3ccfd19d 1662 describe_ctx(m, ctx);
a33afea5
BW		 1663 for_each_ring(ring, dev_priv, i)
1664 if (ring->default_context == ctx)
1665 seq_printf(m, "(default context %s) ", ring->name);
1666
ea0c76f8 1667 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
a33afea5 1668 seq_putc(m, '\n');
a168c293
BW		 1669 }
1670
f3d28878 1671 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1672
1673 return 0;
1674}
1675
6d794d42
BW		 1676static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1677{
9f25d007 1678 struct drm_info_node *node = m->private;
6d794d42
BW		 1679 struct drm_device *dev = node->minor->dev;
1680 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1681 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1682
907b28c5 1683 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1684 if (IS_VALLEYVIEW(dev)) {
1685 fw_rendercount = dev_priv->uncore.fw_rendercount;
1686 fw_mediacount = dev_priv->uncore.fw_mediacount;
1687 } else
1688 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1689 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1690
43709ba0
D		 1691 if (IS_VALLEYVIEW(dev)) {
1692 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1693 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1694 } else
1695 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1696
1697 return 0;
1698}
1699
ea16a3cd
DV		 1700static const char *swizzle_string(unsigned swizzle)
1701{
aee56cff 1702 switch (swizzle) {
ea16a3cd
DV		 1703 case I915_BIT_6_SWIZZLE_NONE:
1704 return "none";
1705 case I915_BIT_6_SWIZZLE_9:
1706 return "bit9";
1707 case I915_BIT_6_SWIZZLE_9_10:
1708 return "bit9/bit10";
1709 case I915_BIT_6_SWIZZLE_9_11:
1710 return "bit9/bit11";
1711 case I915_BIT_6_SWIZZLE_9_10_11:
1712 return "bit9/bit10/bit11";
1713 case I915_BIT_6_SWIZZLE_9_17:
1714 return "bit9/bit17";
1715 case I915_BIT_6_SWIZZLE_9_10_17:
1716 return "bit9/bit10/bit17";
1717 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1718 return "unknown";
ea16a3cd
DV		 1719 }
1720
1721 return "bug";
1722}
1723
1724static int i915_swizzle_info(struct seq_file *m, void *data)
1725{
9f25d007 1726 struct drm_info_node *node = m->private;
ea16a3cd
DV		 1727 struct drm_device *dev = node->minor->dev;
1728 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1729 int ret;
1730
1731 ret = mutex_lock_interruptible(&dev->struct_mutex);
1732 if (ret)
1733 return ret;
c8c8fb33 1734 intel_runtime_pm_get(dev_priv);
ea16a3cd 1735
ea16a3cd
DV		 1736 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1737 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1738 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1739 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1740
1741 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1742 seq_printf(m, "DDC = 0x%08x\n",
1743 I915_READ(DCC));
1744 seq_printf(m, "C0DRB3 = 0x%04x\n",
1745 I915_READ16(C0DRB3));
1746 seq_printf(m, "C1DRB3 = 0x%04x\n",
1747 I915_READ16(C1DRB3));
9d3203e1 1748 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 1749 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1750 I915_READ(MAD_DIMM_C0));
1751 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1752 I915_READ(MAD_DIMM_C1));
1753 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1754 I915_READ(MAD_DIMM_C2));
1755 seq_printf(m, "TILECTL = 0x%08x\n",
1756 I915_READ(TILECTL));
9d3203e1
BW		 1757 if (IS_GEN8(dev))
1758 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1759 I915_READ(GAMTARBMODE));
1760 else
1761 seq_printf(m, "ARB_MODE = 0x%08x\n",
1762 I915_READ(ARB_MODE));
3fa7d235
DV		 1763 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1764 I915_READ(DISP_ARB_CTL));
ea16a3cd 1765 }
c8c8fb33 1766 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 1767 mutex_unlock(&dev->struct_mutex);
1768
1769 return 0;
1770}
1771
1c60fef5
BW		 1772static int per_file_ctx(int id, void *ptr, void *data)
1773{
273497e5 1774 struct intel_context *ctx = ptr;
1c60fef5
BW		 1775 struct seq_file *m = data;
1776 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1777
f83d6518
OM		 1778 if (i915_gem_context_is_default(ctx))
1779 seq_puts(m, " default context:\n");
1780 else
821d66dd 1781 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 1782 ppgtt->debug_dump(ppgtt, m);
1783
1784 return 0;
1785}
1786
77df6772 1787static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 1788{
3cf17fc5 1789 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1790 struct intel_engine_cs *ring;
77df6772
BW		 1791 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1792 int unused, i;
3cf17fc5 1793
77df6772
BW		 1794 if (!ppgtt)
1795 return;
1796
1797 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 1798 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 1799 for_each_ring(ring, dev_priv, unused) {
1800 seq_printf(m, "%s\n", ring->name);
1801 for (i = 0; i < 4; i++) {
1802 u32 offset = 0x270 + i * 8;
1803 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1804 pdp <<= 32;
1805 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 1806 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 1807 }
1808 }
1809}
1810
1811static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1812{
1813 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1814 struct intel_engine_cs *ring;
1c60fef5 1815 struct drm_file *file;
77df6772 1816 int i;
3cf17fc5 1817
3cf17fc5
DV		 1818 if (INTEL_INFO(dev)->gen == 6)
1819 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1820
a2c7f6fd 1821 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 1822 seq_printf(m, "%s\n", ring->name);
1823 if (INTEL_INFO(dev)->gen == 7)
1824 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1825 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1826 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1827 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1828 }
1829 if (dev_priv->mm.aliasing_ppgtt) {
1830 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1831
267f0c90 1832 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 1833 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 1834
87d60b63 1835 ppgtt->debug_dump(ppgtt, m);
1c60fef5
BW		 1836 } else
1837 return;
1838
1839 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1840 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 1841
1c60fef5
BW		 1842 seq_printf(m, "proc: %s\n",
1843 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 1844 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 1845 }
1846 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 1847}
1848
1849static int i915_ppgtt_info(struct seq_file *m, void *data)
1850{
9f25d007 1851 struct drm_info_node *node = m->private;
77df6772 1852 struct drm_device *dev = node->minor->dev;
c8c8fb33 1853 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 1854
1855 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1856 if (ret)
1857 return ret;
c8c8fb33 1858 intel_runtime_pm_get(dev_priv);
77df6772
BW		 1859
1860 if (INTEL_INFO(dev)->gen >= 8)
1861 gen8_ppgtt_info(m, dev);
1862 else if (INTEL_INFO(dev)->gen >= 6)
1863 gen6_ppgtt_info(m, dev);
1864
c8c8fb33 1865 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 1866 mutex_unlock(&dev->struct_mutex);
1867
1868 return 0;
1869}
1870
63573eb7
BW		 1871static int i915_llc(struct seq_file *m, void *data)
1872{
9f25d007 1873 struct drm_info_node *node = m->private;
63573eb7
BW		 1874 struct drm_device *dev = node->minor->dev;
1875 struct drm_i915_private *dev_priv = dev->dev_private;
1876
1877 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1878 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1879 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1880
1881 return 0;
1882}
1883
e91fd8c6
RV		 1884static int i915_edp_psr_status(struct seq_file *m, void *data)
1885{
1886 struct drm_info_node *node = m->private;
1887 struct drm_device *dev = node->minor->dev;
1888 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709
RV		 1889 u32 psrperf = 0;
1890 bool enabled = false;
e91fd8c6 1891
c8c8fb33
PZ		 1892 intel_runtime_pm_get(dev_priv);
1893
a031d709
RV		 1894 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1895 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
5755c78f
RV		 1896 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->psr.enabled));
1897 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
e91fd8c6 1898
a031d709
RV		 1899 enabled = HAS_PSR(dev) &&
1900 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
5755c78f 1901 seq_printf(m, "HW Enabled & Active bit: %s\n", yesno(enabled));
e91fd8c6 1902
a031d709
RV		 1903 if (HAS_PSR(dev))
1904 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1905 EDP_PSR_PERF_CNT_MASK;
1906 seq_printf(m, "Performance_Counter: %u\n", psrperf);
e91fd8c6 1907
c8c8fb33 1908 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 1909 return 0;
1910}
1911
d2e216d0
RV		 1912static int i915_sink_crc(struct seq_file *m, void *data)
1913{
1914 struct drm_info_node *node = m->private;
1915 struct drm_device *dev = node->minor->dev;
1916 struct intel_encoder *encoder;
1917 struct intel_connector *connector;
1918 struct intel_dp *intel_dp = NULL;
1919 int ret;
1920 u8 crc[6];
1921
1922 drm_modeset_lock_all(dev);
1923 list_for_each_entry(connector, &dev->mode_config.connector_list,
1924 base.head) {
1925
1926 if (connector->base.dpms != DRM_MODE_DPMS_ON)
1927 continue;
1928
b6ae3c7c
PZ		 1929 if (!connector->base.encoder)
1930 continue;
1931
d2e216d0
RV		 1932 encoder = to_intel_encoder(connector->base.encoder);
1933 if (encoder->type != INTEL_OUTPUT_EDP)
1934 continue;
1935
1936 intel_dp = enc_to_intel_dp(&encoder->base);
1937
1938 ret = intel_dp_sink_crc(intel_dp, crc);
1939 if (ret)
1940 goto out;
1941
1942 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
1943 crc[0], crc[1], crc[2],
1944 crc[3], crc[4], crc[5]);
1945 goto out;
1946 }
1947 ret = -ENODEV;
1948out:
1949 drm_modeset_unlock_all(dev);
1950 return ret;
1951}
1952
ec013e7f
JB		 1953static int i915_energy_uJ(struct seq_file *m, void *data)
1954{
1955 struct drm_info_node *node = m->private;
1956 struct drm_device *dev = node->minor->dev;
1957 struct drm_i915_private *dev_priv = dev->dev_private;
1958 u64 power;
1959 u32 units;
1960
1961 if (INTEL_INFO(dev)->gen < 6)
1962 return -ENODEV;
1963
36623ef8
PZ		 1964 intel_runtime_pm_get(dev_priv);
1965
ec013e7f
JB		 1966 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1967 power = (power & 0x1f00) >> 8;
1968 units = 1000000 / (1 << power); /* convert to uJ */
1969 power = I915_READ(MCH_SECP_NRG_STTS);
1970 power *= units;
1971
36623ef8
PZ		 1972 intel_runtime_pm_put(dev_priv);
1973
ec013e7f 1974 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 1975
1976 return 0;
1977}
1978
1979static int i915_pc8_status(struct seq_file *m, void *unused)
1980{
9f25d007 1981 struct drm_info_node *node = m->private;
371db66a
PZ		 1982 struct drm_device *dev = node->minor->dev;
1983 struct drm_i915_private *dev_priv = dev->dev_private;
1984
85b8d5c2 1985 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 1986 seq_puts(m, "not supported\n");
1987 return 0;
1988 }
1989
86c4ec0d 1990 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 1991 seq_printf(m, "IRQs disabled: %s\n",
5d584b2e 1992 yesno(dev_priv->pm.irqs_disabled));
371db66a 1993
ec013e7f
JB		 1994 return 0;
1995}
1996
1da51581
ID		 1997static const char *power_domain_str(enum intel_display_power_domain domain)
1998{
1999 switch (domain) {
2000 case POWER_DOMAIN_PIPE_A:
2001 return "PIPE_A";
2002 case POWER_DOMAIN_PIPE_B:
2003 return "PIPE_B";
2004 case POWER_DOMAIN_PIPE_C:
2005 return "PIPE_C";
2006 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2007 return "PIPE_A_PANEL_FITTER";
2008 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2009 return "PIPE_B_PANEL_FITTER";
2010 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2011 return "PIPE_C_PANEL_FITTER";
2012 case POWER_DOMAIN_TRANSCODER_A:
2013 return "TRANSCODER_A";
2014 case POWER_DOMAIN_TRANSCODER_B:
2015 return "TRANSCODER_B";
2016 case POWER_DOMAIN_TRANSCODER_C:
2017 return "TRANSCODER_C";
2018 case POWER_DOMAIN_TRANSCODER_EDP:
2019 return "TRANSCODER_EDP";
319be8ae
ID		 2020 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2021 return "PORT_DDI_A_2_LANES";
2022 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2023 return "PORT_DDI_A_4_LANES";
2024 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2025 return "PORT_DDI_B_2_LANES";
2026 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2027 return "PORT_DDI_B_4_LANES";
2028 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2029 return "PORT_DDI_C_2_LANES";
2030 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2031 return "PORT_DDI_C_4_LANES";
2032 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2033 return "PORT_DDI_D_2_LANES";
2034 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2035 return "PORT_DDI_D_4_LANES";
2036 case POWER_DOMAIN_PORT_DSI:
2037 return "PORT_DSI";
2038 case POWER_DOMAIN_PORT_CRT:
2039 return "PORT_CRT";
2040 case POWER_DOMAIN_PORT_OTHER:
2041 return "PORT_OTHER";
1da51581
ID		 2042 case POWER_DOMAIN_VGA:
2043 return "VGA";
2044 case POWER_DOMAIN_AUDIO:
2045 return "AUDIO";
bd2bb1b9
PZ		 2046 case POWER_DOMAIN_PLLS:
2047 return "PLLS";
1da51581
ID		 2048 case POWER_DOMAIN_INIT:
2049 return "INIT";
2050 default:
2051 WARN_ON(1);
2052 return "?";
2053 }
2054}
2055
2056static int i915_power_domain_info(struct seq_file *m, void *unused)
2057{
9f25d007 2058 struct drm_info_node *node = m->private;
1da51581
ID		 2059 struct drm_device *dev = node->minor->dev;
2060 struct drm_i915_private *dev_priv = dev->dev_private;
2061 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2062 int i;
2063
2064 mutex_lock(&power_domains->lock);
2065
2066 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2067 for (i = 0; i < power_domains->power_well_count; i++) {
2068 struct i915_power_well *power_well;
2069 enum intel_display_power_domain power_domain;
2070
2071 power_well = &power_domains->power_wells[i];
2072 seq_printf(m, "%-25s %d\n", power_well->name,
2073 power_well->count);
2074
2075 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2076 power_domain++) {
2077 if (!(BIT(power_domain) & power_well->domains))
2078 continue;
2079
2080 seq_printf(m, " %-23s %d\n",
2081 power_domain_str(power_domain),
2082 power_domains->domain_use_count[power_domain]);
2083 }
2084 }
2085
2086 mutex_unlock(&power_domains->lock);
2087
2088 return 0;
2089}
2090
53f5e3ca
JB		 2091static void intel_seq_print_mode(struct seq_file *m, int tabs,
2092 struct drm_display_mode *mode)
2093{
2094 int i;
2095
2096 for (i = 0; i < tabs; i++)
2097 seq_putc(m, '\t');
2098
2099 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2100 mode->base.id, mode->name,
2101 mode->vrefresh, mode->clock,
2102 mode->hdisplay, mode->hsync_start,
2103 mode->hsync_end, mode->htotal,
2104 mode->vdisplay, mode->vsync_start,
2105 mode->vsync_end, mode->vtotal,
2106 mode->type, mode->flags);
2107}
2108
2109static void intel_encoder_info(struct seq_file *m,
2110 struct intel_crtc *intel_crtc,
2111 struct intel_encoder *intel_encoder)
2112{
9f25d007 2113 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2114 struct drm_device *dev = node->minor->dev;
2115 struct drm_crtc *crtc = &intel_crtc->base;
2116 struct intel_connector *intel_connector;
2117 struct drm_encoder *encoder;
2118
2119 encoder = &intel_encoder->base;
2120 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2121 encoder->base.id, encoder->name);
53f5e3ca
JB		 2122 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2123 struct drm_connector *connector = &intel_connector->base;
2124 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2125 connector->base.id,
c23cc417 2126 connector->name,
53f5e3ca
JB		 2127 drm_get_connector_status_name(connector->status));
2128 if (connector->status == connector_status_connected) {
2129 struct drm_display_mode *mode = &crtc->mode;
2130 seq_printf(m, ", mode:\n");
2131 intel_seq_print_mode(m, 2, mode);
2132 } else {
2133 seq_putc(m, '\n');
2134 }
2135 }
2136}
2137
2138static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2139{
9f25d007 2140 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2141 struct drm_device *dev = node->minor->dev;
2142 struct drm_crtc *crtc = &intel_crtc->base;
2143 struct intel_encoder *intel_encoder;
2144
5aa8a937
MR		 2145 if (crtc->primary->fb)
2146 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2147 crtc->primary->fb->base.id, crtc->x, crtc->y,
2148 crtc->primary->fb->width, crtc->primary->fb->height);
2149 else
2150 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2151 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2152 intel_encoder_info(m, intel_crtc, intel_encoder);
2153}
2154
2155static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2156{
2157 struct drm_display_mode *mode = panel->fixed_mode;
2158
2159 seq_printf(m, "\tfixed mode:\n");
2160 intel_seq_print_mode(m, 2, mode);
2161}
2162
2163static void intel_dp_info(struct seq_file *m,
2164 struct intel_connector *intel_connector)
2165{
2166 struct intel_encoder *intel_encoder = intel_connector->encoder;
2167 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2168
2169 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2170 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2171 "no");
2172 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2173 intel_panel_info(m, &intel_connector->panel);
2174}
2175
2176static void intel_hdmi_info(struct seq_file *m,
2177 struct intel_connector *intel_connector)
2178{
2179 struct intel_encoder *intel_encoder = intel_connector->encoder;
2180 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2181
2182 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2183 "no");
2184}
2185
2186static void intel_lvds_info(struct seq_file *m,
2187 struct intel_connector *intel_connector)
2188{
2189 intel_panel_info(m, &intel_connector->panel);
2190}
2191
2192static void intel_connector_info(struct seq_file *m,
2193 struct drm_connector *connector)
2194{
2195 struct intel_connector *intel_connector = to_intel_connector(connector);
2196 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2197 struct drm_display_mode *mode;
53f5e3ca
JB		 2198
2199 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2200 connector->base.id, connector->name,
53f5e3ca
JB		 2201 drm_get_connector_status_name(connector->status));
2202 if (connector->status == connector_status_connected) {
2203 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2204 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2205 connector->display_info.width_mm,
2206 connector->display_info.height_mm);
2207 seq_printf(m, "\tsubpixel order: %s\n",
2208 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2209 seq_printf(m, "\tCEA rev: %d\n",
2210 connector->display_info.cea_rev);
2211 }
36cd7444
DA		 2212 if (intel_encoder) {
2213 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2214 intel_encoder->type == INTEL_OUTPUT_EDP)
2215 intel_dp_info(m, intel_connector);
2216 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2217 intel_hdmi_info(m, intel_connector);
2218 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2219 intel_lvds_info(m, intel_connector);
2220 }
53f5e3ca 2221
f103fc7d
JB		 2222 seq_printf(m, "\tmodes:\n");
2223 list_for_each_entry(mode, &connector->modes, head)
2224 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2225}
2226
065f2ec2
CW		 2227static bool cursor_active(struct drm_device *dev, int pipe)
2228{
2229 struct drm_i915_private *dev_priv = dev->dev_private;
2230 u32 state;
2231
2232 if (IS_845G(dev) || IS_I865G(dev))
2233 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2234 else
5efb3e28 2235 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2236
2237 return state;
2238}
2239
2240static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2241{
2242 struct drm_i915_private *dev_priv = dev->dev_private;
2243 u32 pos;
2244
5efb3e28 2245 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2246
2247 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2248 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2249 *x = -*x;
2250
2251 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2252 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2253 *y = -*y;
2254
2255 return cursor_active(dev, pipe);
2256}
2257
53f5e3ca
JB		 2258static int i915_display_info(struct seq_file *m, void *unused)
2259{
9f25d007 2260 struct drm_info_node *node = m->private;
53f5e3ca 2261 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2262 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2263 struct intel_crtc *crtc;
53f5e3ca
JB		 2264 struct drm_connector *connector;
2265
b0e5ddf3 2266 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2267 drm_modeset_lock_all(dev);
2268 seq_printf(m, "CRTC info\n");
2269 seq_printf(m, "---------\n");
d3fcc808 2270 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2271 bool active;
2272 int x, y;
53f5e3ca 2273
57127efa 2274 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2275 crtc->base.base.id, pipe_name(crtc->pipe),
57127efa 2276 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
a23dc658 2277 if (crtc->active) {
065f2ec2
CW		 2278 intel_crtc_info(m, crtc);
2279
a23dc658 2280 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2281 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2282 yesno(crtc->cursor_base),
57127efa
CW		 2283 x, y, crtc->cursor_width, crtc->cursor_height,
2284 crtc->cursor_addr, yesno(active));
a23dc658 2285 }
cace841c
DV		 2286
2287 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2288 yesno(!crtc->cpu_fifo_underrun_disabled),
2289 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2290 }
2291
2292 seq_printf(m, "\n");
2293 seq_printf(m, "Connector info\n");
2294 seq_printf(m, "--------------\n");
2295 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2296 intel_connector_info(m, connector);
2297 }
2298 drm_modeset_unlock_all(dev);
b0e5ddf3 2299 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2300
2301 return 0;
2302}
2303
e04934cf
BW		 2304static int i915_semaphore_status(struct seq_file *m, void *unused)
2305{
2306 struct drm_info_node *node = (struct drm_info_node *) m->private;
2307 struct drm_device *dev = node->minor->dev;
2308 struct drm_i915_private *dev_priv = dev->dev_private;
2309 struct intel_engine_cs *ring;
2310 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2311 int i, j, ret;
2312
2313 if (!i915_semaphore_is_enabled(dev)) {
2314 seq_puts(m, "Semaphores are disabled\n");
2315 return 0;
2316 }
2317
2318 ret = mutex_lock_interruptible(&dev->struct_mutex);
2319 if (ret)
2320 return ret;
03872064 2321 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2322
2323 if (IS_BROADWELL(dev)) {
2324 struct page *page;
2325 uint64_t *seqno;
2326
2327 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2328
2329 seqno = (uint64_t *)kmap_atomic(page);
2330 for_each_ring(ring, dev_priv, i) {
2331 uint64_t offset;
2332
2333 seq_printf(m, "%s\n", ring->name);
2334
2335 seq_puts(m, " Last signal:");
2336 for (j = 0; j < num_rings; j++) {
2337 offset = i * I915_NUM_RINGS + j;
2338 seq_printf(m, "0x%08llx (0x%02llx) ",
2339 seqno[offset], offset * 8);
2340 }
2341 seq_putc(m, '\n');
2342
2343 seq_puts(m, " Last wait: ");
2344 for (j = 0; j < num_rings; j++) {
2345 offset = i + (j * I915_NUM_RINGS);
2346 seq_printf(m, "0x%08llx (0x%02llx) ",
2347 seqno[offset], offset * 8);
2348 }
2349 seq_putc(m, '\n');
2350
2351 }
2352 kunmap_atomic(seqno);
2353 } else {
2354 seq_puts(m, " Last signal:");
2355 for_each_ring(ring, dev_priv, i)
2356 for (j = 0; j < num_rings; j++)
2357 seq_printf(m, "0x%08x\n",
2358 I915_READ(ring->semaphore.mbox.signal[j]));
2359 seq_putc(m, '\n');
2360 }
2361
2362 seq_puts(m, "\nSync seqno:\n");
2363 for_each_ring(ring, dev_priv, i) {
2364 for (j = 0; j < num_rings; j++) {
2365 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2366 }
2367 seq_putc(m, '\n');
2368 }
2369 seq_putc(m, '\n');
2370
03872064 2371 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2372 mutex_unlock(&dev->struct_mutex);
2373 return 0;
2374}
2375
728e29d7
DV		 2376static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2377{
2378 struct drm_info_node *node = (struct drm_info_node *) m->private;
2379 struct drm_device *dev = node->minor->dev;
2380 struct drm_i915_private *dev_priv = dev->dev_private;
2381 int i;
2382
2383 drm_modeset_lock_all(dev);
2384 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2385 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2386
2387 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2388 seq_printf(m, " refcount: %i, active: %i, on: %s\n", pll->refcount,
2389 pll->active, yesno(pll->on));
2390 seq_printf(m, " tracked hardware state:\n");
2391 seq_printf(m, " dpll: 0x%08x\n", pll->hw_state.dpll);
2392 seq_printf(m, " dpll_md: 0x%08x\n", pll->hw_state.dpll_md);
2393 seq_printf(m, " fp0: 0x%08x\n", pll->hw_state.fp0);
2394 seq_printf(m, " fp1: 0x%08x\n", pll->hw_state.fp1);
d452c5b6 2395 seq_printf(m, " wrpll: 0x%08x\n", pll->hw_state.wrpll);
728e29d7
DV		 2396 }
2397 drm_modeset_unlock_all(dev);
2398
2399 return 0;
2400}
2401
07144428
DL		 2402struct pipe_crc_info {
2403 const char *name;
2404 struct drm_device *dev;
2405 enum pipe pipe;
2406};
2407
2408static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2409{
be5c7a90
DL		 2410 struct pipe_crc_info *info = inode->i_private;
2411 struct drm_i915_private *dev_priv = info->dev->dev_private;
2412 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2413
7eb1c496
DV		 2414 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2415 return -ENODEV;
2416
d538bbdf
DL		 2417 spin_lock_irq(&pipe_crc->lock);
2418
2419 if (pipe_crc->opened) {
2420 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2421 return -EBUSY; /* already open */
2422 }
2423
d538bbdf 2424 pipe_crc->opened = true;
07144428
DL		 2425 filep->private_data = inode->i_private;
2426
d538bbdf
DL		 2427 spin_unlock_irq(&pipe_crc->lock);
2428
07144428
DL		 2429 return 0;
2430}
2431
2432static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2433{
be5c7a90
DL		 2434 struct pipe_crc_info *info = inode->i_private;
2435 struct drm_i915_private *dev_priv = info->dev->dev_private;
2436 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2437
d538bbdf
DL		 2438 spin_lock_irq(&pipe_crc->lock);
2439 pipe_crc->opened = false;
2440 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2441
07144428
DL		 2442 return 0;
2443}
2444
2445/* (6 fields, 8 chars each, space separated (5) + '\n') */
2446#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2447/* account for \'0' */
2448#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2449
2450static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2451{
d538bbdf
DL		 2452 assert_spin_locked(&pipe_crc->lock);
2453 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2454 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2455}
2456
2457static ssize_t
2458i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2459 loff_t *pos)
2460{
2461 struct pipe_crc_info *info = filep->private_data;
2462 struct drm_device *dev = info->dev;
2463 struct drm_i915_private *dev_priv = dev->dev_private;
2464 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2465 char buf[PIPE_CRC_BUFFER_LEN];
2466 int head, tail, n_entries, n;
2467 ssize_t bytes_read;
2468
2469 /*
2470 * Don't allow user space to provide buffers not big enough to hold
2471 * a line of data.
2472 */
2473 if (count < PIPE_CRC_LINE_LEN)
2474 return -EINVAL;
2475
2476 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2477 return 0;
07144428
DL		 2478
2479 /* nothing to read */
d538bbdf 2480 spin_lock_irq(&pipe_crc->lock);
07144428 2481 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2482 int ret;
2483
2484 if (filep->f_flags & O_NONBLOCK) {
2485 spin_unlock_irq(&pipe_crc->lock);
07144428 2486 return -EAGAIN;
d538bbdf 2487 }
07144428 2488
d538bbdf
DL		 2489 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2490 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2491 if (ret) {
2492 spin_unlock_irq(&pipe_crc->lock);
2493 return ret;
2494 }
8bf1e9f1
SH		 2495 }
2496
07144428 2497 /* We now have one or more entries to read */
d538bbdf
DL		 2498 head = pipe_crc->head;
2499 tail = pipe_crc->tail;
07144428
DL		 2500 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2501 count / PIPE_CRC_LINE_LEN);
d538bbdf
DL		 2502 spin_unlock_irq(&pipe_crc->lock);
2503
07144428
DL		 2504 bytes_read = 0;
2505 n = 0;
2506 do {
b2c88f5b 2507 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
07144428 2508 int ret;
8bf1e9f1 2509
07144428
DL		 2510 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2511 "%8u %8x %8x %8x %8x %8x\n",
2512 entry->frame, entry->crc[0],
2513 entry->crc[1], entry->crc[2],
2514 entry->crc[3], entry->crc[4]);
2515
2516 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2517 buf, PIPE_CRC_LINE_LEN);
2518 if (ret == PIPE_CRC_LINE_LEN)
2519 return -EFAULT;
b2c88f5b
DL		 2520
2521 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2522 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
07144428
DL		 2523 n++;
2524 } while (--n_entries);
8bf1e9f1 2525
d538bbdf
DL		 2526 spin_lock_irq(&pipe_crc->lock);
2527 pipe_crc->tail = tail;
2528 spin_unlock_irq(&pipe_crc->lock);
2529
07144428
DL		 2530 return bytes_read;
2531}
2532
2533static const struct file_operations i915_pipe_crc_fops = {
2534 .owner = THIS_MODULE,
2535 .open = i915_pipe_crc_open,
2536 .read = i915_pipe_crc_read,
2537 .release = i915_pipe_crc_release,
2538};
2539
2540static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2541 {
2542 .name = "i915_pipe_A_crc",
2543 .pipe = PIPE_A,
2544 },
2545 {
2546 .name = "i915_pipe_B_crc",
2547 .pipe = PIPE_B,
2548 },
2549 {
2550 .name = "i915_pipe_C_crc",
2551 .pipe = PIPE_C,
2552 },
2553};
2554
2555static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2556 enum pipe pipe)
2557{
2558 struct drm_device *dev = minor->dev;
2559 struct dentry *ent;
2560 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2561
2562 info->dev = dev;
2563 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2564 &i915_pipe_crc_fops);
f3c5fe97
WY		 2565 if (!ent)
2566 return -ENOMEM;
07144428
DL		 2567
2568 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2569}
2570
e8dfcf78 2571static const char * const pipe_crc_sources[] = {
926321d5
DV		 2572 "none",
2573 "plane1",
2574 "plane2",
2575 "pf",
5b3a856b 2576 "pipe",
3d099a05
DV		 2577 "TV",
2578 "DP-B",
2579 "DP-C",
2580 "DP-D",
46a19188 2581 "auto",
926321d5
DV		 2582};
2583
2584static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2585{
2586 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2587 return pipe_crc_sources[source];
2588}
2589
bd9db02f 2590static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2591{
2592 struct drm_device *dev = m->private;
2593 struct drm_i915_private *dev_priv = dev->dev_private;
2594 int i;
2595
2596 for (i = 0; i < I915_MAX_PIPES; i++)
2597 seq_printf(m, "%c %s\n", pipe_name(i),
2598 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2599
2600 return 0;
2601}
2602
bd9db02f 2603static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 2604{
2605 struct drm_device *dev = inode->i_private;
2606
bd9db02f 2607 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 2608}
2609
46a19188 2610static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 2611 uint32_t *val)
2612{
46a19188
DV		 2613 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2614 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2615
2616 switch (*source) {
52f843f6
DV		 2617 case INTEL_PIPE_CRC_SOURCE_PIPE:
2618 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2619 break;
2620 case INTEL_PIPE_CRC_SOURCE_NONE:
2621 *val = 0;
2622 break;
2623 default:
2624 return -EINVAL;
2625 }
2626
2627 return 0;
2628}
2629
46a19188
DV		 2630static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2631 enum intel_pipe_crc_source *source)
2632{
2633 struct intel_encoder *encoder;
2634 struct intel_crtc *crtc;
26756809 2635 struct intel_digital_port *dig_port;
46a19188
DV		 2636 int ret = 0;
2637
2638 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2639
6e9f798d 2640 drm_modeset_lock_all(dev);
46a19188
DV		 2641 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2642 base.head) {
2643 if (!encoder->base.crtc)
2644 continue;
2645
2646 crtc = to_intel_crtc(encoder->base.crtc);
2647
2648 if (crtc->pipe != pipe)
2649 continue;
2650
2651 switch (encoder->type) {
2652 case INTEL_OUTPUT_TVOUT:
2653 *source = INTEL_PIPE_CRC_SOURCE_TV;
2654 break;
2655 case INTEL_OUTPUT_DISPLAYPORT:
2656 case INTEL_OUTPUT_EDP:
26756809
DV		 2657 dig_port = enc_to_dig_port(&encoder->base);
2658 switch (dig_port->port) {
2659 case PORT_B:
2660 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2661 break;
2662 case PORT_C:
2663 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2664 break;
2665 case PORT_D:
2666 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2667 break;
2668 default:
2669 WARN(1, "nonexisting DP port %c\n",
2670 port_name(dig_port->port));
2671 break;
2672 }
46a19188
DV		 2673 break;
2674 }
2675 }
6e9f798d 2676 drm_modeset_unlock_all(dev);
46a19188
DV		 2677
2678 return ret;
2679}
2680
2681static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2682 enum pipe pipe,
2683 enum intel_pipe_crc_source *source,
7ac0129b
DV		 2684 uint32_t *val)
2685{
8d2f24ca
DV		 2686 struct drm_i915_private *dev_priv = dev->dev_private;
2687 bool need_stable_symbols = false;
2688
46a19188
DV		 2689 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2690 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2691 if (ret)
2692 return ret;
2693 }
2694
2695 switch (*source) {
7ac0129b
DV		 2696 case INTEL_PIPE_CRC_SOURCE_PIPE:
2697 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2698 break;
2699 case INTEL_PIPE_CRC_SOURCE_DP_B:
2700 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 2701 need_stable_symbols = true;
7ac0129b
DV		 2702 break;
2703 case INTEL_PIPE_CRC_SOURCE_DP_C:
2704 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 2705 need_stable_symbols = true;
7ac0129b
DV		 2706 break;
2707 case INTEL_PIPE_CRC_SOURCE_NONE:
2708 *val = 0;
2709 break;
2710 default:
2711 return -EINVAL;
2712 }
2713
8d2f24ca
DV		 2714 /*
2715 * When the pipe CRC tap point is after the transcoders we need
2716 * to tweak symbol-level features to produce a deterministic series of
2717 * symbols for a given frame. We need to reset those features only once
2718 * a frame (instead of every nth symbol):
2719 * - DC-balance: used to ensure a better clock recovery from the data
2720 * link (SDVO)
2721 * - DisplayPort scrambling: used for EMI reduction
2722 */
2723 if (need_stable_symbols) {
2724 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2725
8d2f24ca
DV		 2726 tmp |= DC_BALANCE_RESET_VLV;
2727 if (pipe == PIPE_A)
2728 tmp |= PIPE_A_SCRAMBLE_RESET;
2729 else
2730 tmp |= PIPE_B_SCRAMBLE_RESET;
2731
2732 I915_WRITE(PORT_DFT2_G4X, tmp);
2733 }
2734
7ac0129b
DV		 2735 return 0;
2736}
2737
4b79ebf7 2738static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 2739 enum pipe pipe,
2740 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 2741 uint32_t *val)
2742{
84093603
DV		 2743 struct drm_i915_private *dev_priv = dev->dev_private;
2744 bool need_stable_symbols = false;
2745
46a19188
DV		 2746 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2747 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2748 if (ret)
2749 return ret;
2750 }
2751
2752 switch (*source) {
4b79ebf7
DV		 2753 case INTEL_PIPE_CRC_SOURCE_PIPE:
2754 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2755 break;
2756 case INTEL_PIPE_CRC_SOURCE_TV:
2757 if (!SUPPORTS_TV(dev))
2758 return -EINVAL;
2759 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2760 break;
2761 case INTEL_PIPE_CRC_SOURCE_DP_B:
2762 if (!IS_G4X(dev))
2763 return -EINVAL;
2764 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 2765 need_stable_symbols = true;
4b79ebf7
DV		 2766 break;
2767 case INTEL_PIPE_CRC_SOURCE_DP_C:
2768 if (!IS_G4X(dev))
2769 return -EINVAL;
2770 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 2771 need_stable_symbols = true;
4b79ebf7
DV		 2772 break;
2773 case INTEL_PIPE_CRC_SOURCE_DP_D:
2774 if (!IS_G4X(dev))
2775 return -EINVAL;
2776 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 2777 need_stable_symbols = true;
4b79ebf7
DV		 2778 break;
2779 case INTEL_PIPE_CRC_SOURCE_NONE:
2780 *val = 0;
2781 break;
2782 default:
2783 return -EINVAL;
2784 }
2785
84093603
DV		 2786 /*
2787 * When the pipe CRC tap point is after the transcoders we need
2788 * to tweak symbol-level features to produce a deterministic series of
2789 * symbols for a given frame. We need to reset those features only once
2790 * a frame (instead of every nth symbol):
2791 * - DC-balance: used to ensure a better clock recovery from the data
2792 * link (SDVO)
2793 * - DisplayPort scrambling: used for EMI reduction
2794 */
2795 if (need_stable_symbols) {
2796 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2797
2798 WARN_ON(!IS_G4X(dev));
2799
2800 I915_WRITE(PORT_DFT_I9XX,
2801 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2802
2803 if (pipe == PIPE_A)
2804 tmp |= PIPE_A_SCRAMBLE_RESET;
2805 else
2806 tmp |= PIPE_B_SCRAMBLE_RESET;
2807
2808 I915_WRITE(PORT_DFT2_G4X, tmp);
2809 }
2810
4b79ebf7
DV		 2811 return 0;
2812}
2813
8d2f24ca
DV		 2814static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2815 enum pipe pipe)
2816{
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2819
2820 if (pipe == PIPE_A)
2821 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2822 else
2823 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2824 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2825 tmp &= ~DC_BALANCE_RESET_VLV;
2826 I915_WRITE(PORT_DFT2_G4X, tmp);
2827
2828}
2829
84093603
DV		 2830static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2831 enum pipe pipe)
2832{
2833 struct drm_i915_private *dev_priv = dev->dev_private;
2834 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2835
2836 if (pipe == PIPE_A)
2837 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2838 else
2839 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2840 I915_WRITE(PORT_DFT2_G4X, tmp);
2841
2842 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2843 I915_WRITE(PORT_DFT_I9XX,
2844 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2845 }
2846}
2847
46a19188 2848static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 2849 uint32_t *val)
2850{
46a19188
DV		 2851 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2852 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2853
2854 switch (*source) {
5b3a856b
DV		 2855 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2856 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2857 break;
2858 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2859 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2860 break;
5b3a856b
DV		 2861 case INTEL_PIPE_CRC_SOURCE_PIPE:
2862 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2863 break;
3d099a05 2864 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2865 *val = 0;
2866 break;
3d099a05
DV		 2867 default:
2868 return -EINVAL;
5b3a856b
DV		 2869 }
2870
2871 return 0;
2872}
2873
fabf6e51
DV		 2874static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
2875{
2876 struct drm_i915_private *dev_priv = dev->dev_private;
2877 struct intel_crtc *crtc =
2878 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
2879
2880 drm_modeset_lock_all(dev);
2881 /*
2882 * If we use the eDP transcoder we need to make sure that we don't
2883 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
2884 * relevant on hsw with pipe A when using the always-on power well
2885 * routing.
2886 */
2887 if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
2888 !crtc->config.pch_pfit.enabled) {
2889 crtc->config.pch_pfit.force_thru = true;
2890
2891 intel_display_power_get(dev_priv,
2892 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
2893
2894 dev_priv->display.crtc_disable(&crtc->base);
2895 dev_priv->display.crtc_enable(&crtc->base);
2896 }
2897 drm_modeset_unlock_all(dev);
2898}
2899
2900static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
2901{
2902 struct drm_i915_private *dev_priv = dev->dev_private;
2903 struct intel_crtc *crtc =
2904 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
2905
2906 drm_modeset_lock_all(dev);
2907 /*
2908 * If we use the eDP transcoder we need to make sure that we don't
2909 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
2910 * relevant on hsw with pipe A when using the always-on power well
2911 * routing.
2912 */
2913 if (crtc->config.pch_pfit.force_thru) {
2914 crtc->config.pch_pfit.force_thru = false;
2915
2916 dev_priv->display.crtc_disable(&crtc->base);
2917 dev_priv->display.crtc_enable(&crtc->base);
2918
2919 intel_display_power_put(dev_priv,
2920 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
2921 }
2922 drm_modeset_unlock_all(dev);
2923}
2924
2925static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
2926 enum pipe pipe,
2927 enum intel_pipe_crc_source *source,
5b3a856b
DV		 2928 uint32_t *val)
2929{
46a19188
DV		 2930 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2931 *source = INTEL_PIPE_CRC_SOURCE_PF;
2932
2933 switch (*source) {
5b3a856b
DV		 2934 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2935 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2936 break;
2937 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2938 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2939 break;
2940 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 2941 if (IS_HASWELL(dev) && pipe == PIPE_A)
2942 hsw_trans_edp_pipe_A_crc_wa(dev);
2943
5b3a856b
DV		 2944 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2945 break;
3d099a05 2946 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 2947 *val = 0;
2948 break;
3d099a05
DV		 2949 default:
2950 return -EINVAL;
5b3a856b
DV		 2951 }
2952
2953 return 0;
2954}
2955
926321d5
DV		 2956static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2957 enum intel_pipe_crc_source source)
2958{
2959 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 2960 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
432f3342 2961 u32 val = 0; /* shut up gcc */
5b3a856b 2962 int ret;
926321d5 2963
cc3da175
DL		 2964 if (pipe_crc->source == source)
2965 return 0;
2966
ae676fcd
DL		 2967 /* forbid changing the source without going back to 'none' */
2968 if (pipe_crc->source && source)
2969 return -EINVAL;
2970
52f843f6 2971 if (IS_GEN2(dev))
46a19188 2972 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 2973 else if (INTEL_INFO(dev)->gen < 5)
46a19188 2974 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 2975 else if (IS_VALLEYVIEW(dev))
fabf6e51 2976 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 2977 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 2978 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 2979 else
fabf6e51 2980 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 2981
2982 if (ret != 0)
2983 return ret;
2984
4b584369
DL		 2985 /* none -> real source transition */
2986 if (source) {
7cd6ccff
DL		 2987 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2988 pipe_name(pipe), pipe_crc_source_name(source));
2989
e5f75aca
DL		 2990 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2991 INTEL_PIPE_CRC_ENTRIES_NR,
2992 GFP_KERNEL);
2993 if (!pipe_crc->entries)
2994 return -ENOMEM;
2995
d538bbdf
DL		 2996 spin_lock_irq(&pipe_crc->lock);
2997 pipe_crc->head = 0;
2998 pipe_crc->tail = 0;
2999 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3000 }
3001
cc3da175 3002 pipe_crc->source = source;
926321d5 3003
926321d5
DV		 3004 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3005 POSTING_READ(PIPE_CRC_CTL(pipe));
3006
e5f75aca
DL		 3007 /* real source -> none transition */
3008 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3009 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3010 struct intel_crtc *crtc =
3011 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3012
7cd6ccff
DL		 3013 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3014 pipe_name(pipe));
3015
a33d7105
DV		 3016 drm_modeset_lock(&crtc->base.mutex, NULL);
3017 if (crtc->active)
3018 intel_wait_for_vblank(dev, pipe);
3019 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3020
d538bbdf
DL		 3021 spin_lock_irq(&pipe_crc->lock);
3022 entries = pipe_crc->entries;
e5f75aca 3023 pipe_crc->entries = NULL;
d538bbdf
DL		 3024 spin_unlock_irq(&pipe_crc->lock);
3025
3026 kfree(entries);
84093603
DV		 3027
3028 if (IS_G4X(dev))
3029 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3030 else if (IS_VALLEYVIEW(dev))
3031 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3032 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3033 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
e5f75aca
DL		 3034 }
3035
926321d5
DV		 3036 return 0;
3037}
3038
3039/*
3040 * Parse pipe CRC command strings:
b94dec87
DL		 3041 * command: wsp* object wsp+ name wsp+ source wsp*
3042 * object: 'pipe'
3043 * name: (A | B | C)
926321d5
DV		 3044 * source: (none | plane1 | plane2 | pf)
3045 * wsp: (#0x20 | #0x9 | #0xA)+
3046 *
3047 * eg.:
b94dec87
DL		 3048 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3049 * "pipe A none" -> Stop CRC
926321d5 3050 */
bd9db02f 3051static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3052{
3053 int n_words = 0;
3054
3055 while (*buf) {
3056 char *end;
3057
3058 /* skip leading white space */
3059 buf = skip_spaces(buf);
3060 if (!*buf)
3061 break; /* end of buffer */
3062
3063 /* find end of word */
3064 for (end = buf; *end && !isspace(*end); end++)
3065 ;
3066
3067 if (n_words == max_words) {
3068 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3069 max_words);
3070 return -EINVAL; /* ran out of words[] before bytes */
3071 }
3072
3073 if (*end)
3074 *end++ = '\0';
3075 words[n_words++] = buf;
3076 buf = end;
3077 }
3078
3079 return n_words;
3080}
3081
b94dec87
DL		 3082enum intel_pipe_crc_object {
3083 PIPE_CRC_OBJECT_PIPE,
3084};
3085
e8dfcf78 3086static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3087 "pipe",
3088};
3089
3090static int
bd9db02f 3091display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3092{
3093 int i;
3094
3095 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3096 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3097 *o = i;
b94dec87
DL		 3098 return 0;
3099 }
3100
3101 return -EINVAL;
3102}
3103
bd9db02f 3104static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3105{
3106 const char name = buf[0];
3107
3108 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3109 return -EINVAL;
3110
3111 *pipe = name - 'A';
3112
3113 return 0;
3114}
3115
3116static int
bd9db02f 3117display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3118{
3119 int i;
3120
3121 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3122 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3123 *s = i;
926321d5
DV		 3124 return 0;
3125 }
3126
3127 return -EINVAL;
3128}
3129
bd9db02f 3130static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3131{
b94dec87 3132#define N_WORDS 3
926321d5 3133 int n_words;
b94dec87 3134 char *words[N_WORDS];
926321d5 3135 enum pipe pipe;
b94dec87 3136 enum intel_pipe_crc_object object;
926321d5
DV		 3137 enum intel_pipe_crc_source source;
3138
bd9db02f 3139 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3140 if (n_words != N_WORDS) {
3141 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3142 N_WORDS);
3143 return -EINVAL;
3144 }
3145
bd9db02f 3146 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3147 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3148 return -EINVAL;
3149 }
3150
bd9db02f 3151 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3152 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3153 return -EINVAL;
3154 }
3155
bd9db02f 3156 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3157 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3158 return -EINVAL;
3159 }
3160
3161 return pipe_crc_set_source(dev, pipe, source);
3162}
3163
bd9db02f
DL		 3164static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3165 size_t len, loff_t *offp)
926321d5
DV		 3166{
3167 struct seq_file *m = file->private_data;
3168 struct drm_device *dev = m->private;
3169 char *tmpbuf;
3170 int ret;
3171
3172 if (len == 0)
3173 return 0;
3174
3175 if (len > PAGE_SIZE - 1) {
3176 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3177 PAGE_SIZE);
3178 return -E2BIG;
3179 }
3180
3181 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3182 if (!tmpbuf)
3183 return -ENOMEM;
3184
3185 if (copy_from_user(tmpbuf, ubuf, len)) {
3186 ret = -EFAULT;
3187 goto out;
3188 }
3189 tmpbuf[len] = '\0';
3190
bd9db02f 3191 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3192
3193out:
3194 kfree(tmpbuf);
3195 if (ret < 0)
3196 return ret;
3197
3198 *offp += len;
3199 return len;
3200}
3201
bd9db02f 3202static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3203 .owner = THIS_MODULE,
bd9db02f 3204 .open = display_crc_ctl_open,
926321d5
DV		 3205 .read = seq_read,
3206 .llseek = seq_lseek,
3207 .release = single_release,
bd9db02f 3208 .write = display_crc_ctl_write
926321d5
DV		 3209};
3210
369a1342
VS		 3211static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3212{
3213 struct drm_device *dev = m->private;
546c81fd 3214 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3215 int level;
3216
3217 drm_modeset_lock_all(dev);
3218
3219 for (level = 0; level < num_levels; level++) {
3220 unsigned int latency = wm[level];
3221
3222 /* WM1+ latency values in 0.5us units */
3223 if (level > 0)
3224 latency *= 5;
3225
3226 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3227 level, wm[level],
3228 latency / 10, latency % 10);
3229 }
3230
3231 drm_modeset_unlock_all(dev);
3232}
3233
3234static int pri_wm_latency_show(struct seq_file *m, void *data)
3235{
3236 struct drm_device *dev = m->private;
3237
3238 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3239
3240 return 0;
3241}
3242
3243static int spr_wm_latency_show(struct seq_file *m, void *data)
3244{
3245 struct drm_device *dev = m->private;
3246
3247 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3248
3249 return 0;
3250}
3251
3252static int cur_wm_latency_show(struct seq_file *m, void *data)
3253{
3254 struct drm_device *dev = m->private;
3255
3256 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3257
3258 return 0;
3259}
3260
3261static int pri_wm_latency_open(struct inode *inode, struct file *file)
3262{
3263 struct drm_device *dev = inode->i_private;
3264
3265 if (!HAS_PCH_SPLIT(dev))
3266 return -ENODEV;
3267
3268 return single_open(file, pri_wm_latency_show, dev);
3269}
3270
3271static int spr_wm_latency_open(struct inode *inode, struct file *file)
3272{
3273 struct drm_device *dev = inode->i_private;
3274
3275 if (!HAS_PCH_SPLIT(dev))
3276 return -ENODEV;
3277
3278 return single_open(file, spr_wm_latency_show, dev);
3279}
3280
3281static int cur_wm_latency_open(struct inode *inode, struct file *file)
3282{
3283 struct drm_device *dev = inode->i_private;
3284
3285 if (!HAS_PCH_SPLIT(dev))
3286 return -ENODEV;
3287
3288 return single_open(file, cur_wm_latency_show, dev);
3289}
3290
3291static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3292 size_t len, loff_t *offp, uint16_t wm[5])
3293{
3294 struct seq_file *m = file->private_data;
3295 struct drm_device *dev = m->private;
3296 uint16_t new[5] = { 0 };
546c81fd 3297 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3298 int level;
3299 int ret;
3300 char tmp[32];
3301
3302 if (len >= sizeof(tmp))
3303 return -EINVAL;
3304
3305 if (copy_from_user(tmp, ubuf, len))
3306 return -EFAULT;
3307
3308 tmp[len] = '\0';
3309
3310 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3311 if (ret != num_levels)
3312 return -EINVAL;
3313
3314 drm_modeset_lock_all(dev);
3315
3316 for (level = 0; level < num_levels; level++)
3317 wm[level] = new[level];
3318
3319 drm_modeset_unlock_all(dev);
3320
3321 return len;
3322}
3323
3324
3325static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3326 size_t len, loff_t *offp)
3327{
3328 struct seq_file *m = file->private_data;
3329 struct drm_device *dev = m->private;
3330
3331 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3332}
3333
3334static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3335 size_t len, loff_t *offp)
3336{
3337 struct seq_file *m = file->private_data;
3338 struct drm_device *dev = m->private;
3339
3340 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3341}
3342
3343static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3344 size_t len, loff_t *offp)
3345{
3346 struct seq_file *m = file->private_data;
3347 struct drm_device *dev = m->private;
3348
3349 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3350}
3351
3352static const struct file_operations i915_pri_wm_latency_fops = {
3353 .owner = THIS_MODULE,
3354 .open = pri_wm_latency_open,
3355 .read = seq_read,
3356 .llseek = seq_lseek,
3357 .release = single_release,
3358 .write = pri_wm_latency_write
3359};
3360
3361static const struct file_operations i915_spr_wm_latency_fops = {
3362 .owner = THIS_MODULE,
3363 .open = spr_wm_latency_open,
3364 .read = seq_read,
3365 .llseek = seq_lseek,
3366 .release = single_release,
3367 .write = spr_wm_latency_write
3368};
3369
3370static const struct file_operations i915_cur_wm_latency_fops = {
3371 .owner = THIS_MODULE,
3372 .open = cur_wm_latency_open,
3373 .read = seq_read,
3374 .llseek = seq_lseek,
3375 .release = single_release,
3376 .write = cur_wm_latency_write
3377};
3378
647416f9
KC		 3379static int
3380i915_wedged_get(void *data, u64 *val)
f3cd474b 3381{
647416f9 3382 struct drm_device *dev = data;
e277a1f8 3383 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3384
647416f9 3385 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3386
647416f9 3387 return 0;
f3cd474b
CW		 3388}
3389
647416f9
KC		 3390static int
3391i915_wedged_set(void *data, u64 val)
f3cd474b 3392{
647416f9 3393 struct drm_device *dev = data;
d46c0517
ID		 3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395
3396 intel_runtime_pm_get(dev_priv);
f3cd474b 3397
58174462
MK		 3398 i915_handle_error(dev, val,
3399 "Manually setting wedged to %llu", val);
d46c0517
ID		 3400
3401 intel_runtime_pm_put(dev_priv);
3402
647416f9 3403 return 0;
f3cd474b
CW		 3404}
3405
647416f9
KC		 3406DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3407 i915_wedged_get, i915_wedged_set,
3a3b4f98 3408 "%llu\n");
f3cd474b 3409
647416f9
KC		 3410static int
3411i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3412{
647416f9 3413 struct drm_device *dev = data;
e277a1f8 3414 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 3415
647416f9 3416 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3417
647416f9 3418 return 0;
e5eb3d63
DV		 3419}
3420
647416f9
KC		 3421static int
3422i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3423{
647416f9 3424 struct drm_device *dev = data;
e5eb3d63 3425 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3426 int ret;
e5eb3d63 3427
647416f9 3428 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3429
22bcfc6a
DV		 3430 ret = mutex_lock_interruptible(&dev->struct_mutex);
3431 if (ret)
3432 return ret;
3433
99584db3 3434 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3435 mutex_unlock(&dev->struct_mutex);
3436
647416f9 3437 return 0;
e5eb3d63
DV		 3438}
3439
647416f9
KC		 3440DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3441 i915_ring_stop_get, i915_ring_stop_set,
3442 "0x%08llx\n");
d5442303 3443
094f9a54
CW		 3444static int
3445i915_ring_missed_irq_get(void *data, u64 *val)
3446{
3447 struct drm_device *dev = data;
3448 struct drm_i915_private *dev_priv = dev->dev_private;
3449
3450 *val = dev_priv->gpu_error.missed_irq_rings;
3451 return 0;
3452}
3453
3454static int
3455i915_ring_missed_irq_set(void *data, u64 val)
3456{
3457 struct drm_device *dev = data;
3458 struct drm_i915_private *dev_priv = dev->dev_private;
3459 int ret;
3460
3461 /* Lock against concurrent debugfs callers */
3462 ret = mutex_lock_interruptible(&dev->struct_mutex);
3463 if (ret)
3464 return ret;
3465 dev_priv->gpu_error.missed_irq_rings = val;
3466 mutex_unlock(&dev->struct_mutex);
3467
3468 return 0;
3469}
3470
3471DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3472 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3473 "0x%08llx\n");
3474
3475static int
3476i915_ring_test_irq_get(void *data, u64 *val)
3477{
3478 struct drm_device *dev = data;
3479 struct drm_i915_private *dev_priv = dev->dev_private;
3480
3481 *val = dev_priv->gpu_error.test_irq_rings;
3482
3483 return 0;
3484}
3485
3486static int
3487i915_ring_test_irq_set(void *data, u64 val)
3488{
3489 struct drm_device *dev = data;
3490 struct drm_i915_private *dev_priv = dev->dev_private;
3491 int ret;
3492
3493 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3494
3495 /* Lock against concurrent debugfs callers */
3496 ret = mutex_lock_interruptible(&dev->struct_mutex);
3497 if (ret)
3498 return ret;
3499
3500 dev_priv->gpu_error.test_irq_rings = val;
3501 mutex_unlock(&dev->struct_mutex);
3502
3503 return 0;
3504}
3505
3506DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3507 i915_ring_test_irq_get, i915_ring_test_irq_set,
3508 "0x%08llx\n");
3509
dd624afd
CW		 3510#define DROP_UNBOUND 0x1
3511#define DROP_BOUND 0x2
3512#define DROP_RETIRE 0x4
3513#define DROP_ACTIVE 0x8
3514#define DROP_ALL (DROP_UNBOUND | \
3515 DROP_BOUND | \
3516 DROP_RETIRE | \
3517 DROP_ACTIVE)
647416f9
KC		 3518static int
3519i915_drop_caches_get(void *data, u64 *val)
dd624afd 3520{
647416f9 3521 *val = DROP_ALL;
dd624afd 3522
647416f9 3523 return 0;
dd624afd
CW		 3524}
3525
647416f9
KC		 3526static int
3527i915_drop_caches_set(void *data, u64 val)
dd624afd 3528{
647416f9 3529 struct drm_device *dev = data;
dd624afd
CW		 3530 struct drm_i915_private *dev_priv = dev->dev_private;
3531 struct drm_i915_gem_object *obj, *next;
ca191b13
BW		 3532 struct i915_address_space *vm;
3533 struct i915_vma *vma, *x;
647416f9 3534 int ret;
dd624afd 3535
2f9fe5ff 3536 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 3537
3538 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3539 * on ioctls on -EAGAIN. */
3540 ret = mutex_lock_interruptible(&dev->struct_mutex);
3541 if (ret)
3542 return ret;
3543
3544 if (val & DROP_ACTIVE) {
3545 ret = i915_gpu_idle(dev);
3546 if (ret)
3547 goto unlock;
3548 }
3549
3550 if (val & (DROP_RETIRE | DROP_ACTIVE))
3551 i915_gem_retire_requests(dev);
3552
3553 if (val & DROP_BOUND) {
ca191b13
BW		 3554 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3555 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3556 mm_list) {
d7f46fc4 3557 if (vma->pin_count)
ca191b13
BW		 3558 continue;
3559
3560 ret = i915_vma_unbind(vma);
3561 if (ret)
3562 goto unlock;
3563 }
31a46c9c 3564 }
dd624afd
CW		 3565 }
3566
3567 if (val & DROP_UNBOUND) {
35c20a60
BW		 3568 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3569 global_list)
dd624afd
CW		 3570 if (obj->pages_pin_count == 0) {
3571 ret = i915_gem_object_put_pages(obj);
3572 if (ret)
3573 goto unlock;
3574 }
3575 }
3576
3577unlock:
3578 mutex_unlock(&dev->struct_mutex);
3579
647416f9 3580 return ret;
dd624afd
CW		 3581}
3582
647416f9
KC		 3583DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3584 i915_drop_caches_get, i915_drop_caches_set,
3585 "0x%08llx\n");
dd624afd 3586
647416f9
KC		 3587static int
3588i915_max_freq_get(void *data, u64 *val)
358733e9 3589{
647416f9 3590 struct drm_device *dev = data;
e277a1f8 3591 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3592 int ret;
004777cb 3593
daa3afb2 3594 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 3595 return -ENODEV;
3596
5c9669ce
TR		 3597 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3598
4fc688ce 3599 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3600 if (ret)
3601 return ret;
358733e9 3602
0a073b84 3603 if (IS_VALLEYVIEW(dev))
b39fb297 3604 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
0a073b84 3605 else
b39fb297 3606 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3607 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3608
647416f9 3609 return 0;
358733e9
JB		 3610}
3611
647416f9
KC		 3612static int
3613i915_max_freq_set(void *data, u64 val)
358733e9 3614{
647416f9 3615 struct drm_device *dev = data;
358733e9 3616 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3617 u32 rp_state_cap, hw_max, hw_min;
647416f9 3618 int ret;
004777cb 3619
daa3afb2 3620 if (INTEL_INFO(dev)->gen < 6)
004777cb 3621 return -ENODEV;
358733e9 3622
5c9669ce
TR		 3623 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3624
647416f9 3625 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 3626
4fc688ce 3627 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3628 if (ret)
3629 return ret;
3630
358733e9
JB		 3631 /*
3632 * Turbo will still be enabled, but won't go above the set value.
3633 */
0a073b84 3634 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3635 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 3636
3637 hw_max = valleyview_rps_max_freq(dev_priv);
3638 hw_min = valleyview_rps_min_freq(dev_priv);
0a073b84
JB		 3639 } else {
3640 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3641
3642 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 3643 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 3644 hw_min = (rp_state_cap >> 16) & 0xff;
3645 }
3646
b39fb297 3647 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 3648 mutex_unlock(&dev_priv->rps.hw_lock);
3649 return -EINVAL;
0a073b84
JB		 3650 }
3651
b39fb297 3652 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 3653
3654 if (IS_VALLEYVIEW(dev))
3655 valleyview_set_rps(dev, val);
3656 else
3657 gen6_set_rps(dev, val);
3658
4fc688ce 3659 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 3660
647416f9 3661 return 0;
358733e9
JB		 3662}
3663
647416f9
KC		 3664DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3665 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 3666 "%llu\n");
358733e9 3667
647416f9
KC		 3668static int
3669i915_min_freq_get(void *data, u64 *val)
1523c310 3670{
647416f9 3671 struct drm_device *dev = data;
e277a1f8 3672 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3673 int ret;
004777cb 3674
daa3afb2 3675 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 3676 return -ENODEV;
3677
5c9669ce
TR		 3678 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3679
4fc688ce 3680 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3681 if (ret)
3682 return ret;
1523c310 3683
0a073b84 3684 if (IS_VALLEYVIEW(dev))
b39fb297 3685 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
0a073b84 3686 else
b39fb297 3687 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 3688 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3689
647416f9 3690 return 0;
1523c310
JB		 3691}
3692
647416f9
KC		 3693static int
3694i915_min_freq_set(void *data, u64 val)
1523c310 3695{
647416f9 3696 struct drm_device *dev = data;
1523c310 3697 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 3698 u32 rp_state_cap, hw_max, hw_min;
647416f9 3699 int ret;
004777cb 3700
daa3afb2 3701 if (INTEL_INFO(dev)->gen < 6)
004777cb 3702 return -ENODEV;
1523c310 3703
5c9669ce
TR		 3704 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3705
647416f9 3706 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 3707
4fc688ce 3708 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 3709 if (ret)
3710 return ret;
3711
1523c310
JB		 3712 /*
3713 * Turbo will still be enabled, but won't go below the set value.
3714 */
0a073b84 3715 if (IS_VALLEYVIEW(dev)) {
2ec3815f 3716 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1
JM		 3717
3718 hw_max = valleyview_rps_max_freq(dev_priv);
3719 hw_min = valleyview_rps_min_freq(dev_priv);
0a073b84
JB		 3720 } else {
3721 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 3722
3723 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 3724 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 3725 hw_min = (rp_state_cap >> 16) & 0xff;
3726 }
3727
b39fb297 3728 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 3729 mutex_unlock(&dev_priv->rps.hw_lock);
3730 return -EINVAL;
0a073b84 3731 }
dd0a1aa1 3732
b39fb297 3733 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 3734
3735 if (IS_VALLEYVIEW(dev))
3736 valleyview_set_rps(dev, val);
3737 else
3738 gen6_set_rps(dev, val);
3739
4fc688ce 3740 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 3741
647416f9 3742 return 0;
1523c310
JB		 3743}
3744
647416f9
KC		 3745DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3746 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 3747 "%llu\n");
1523c310 3748
647416f9
KC		 3749static int
3750i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 3751{
647416f9 3752 struct drm_device *dev = data;
e277a1f8 3753 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3754 u32 snpcr;
647416f9 3755 int ret;
07b7ddd9 3756
004777cb
DV		 3757 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3758 return -ENODEV;
3759
22bcfc6a
DV		 3760 ret = mutex_lock_interruptible(&dev->struct_mutex);
3761 if (ret)
3762 return ret;
c8c8fb33 3763 intel_runtime_pm_get(dev_priv);
22bcfc6a 3764
07b7ddd9 3765 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 3766
3767 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 3768 mutex_unlock(&dev_priv->dev->struct_mutex);
3769
647416f9 3770 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 3771
647416f9 3772 return 0;
07b7ddd9
JB		 3773}
3774
647416f9
KC		 3775static int
3776i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 3777{
647416f9 3778 struct drm_device *dev = data;
07b7ddd9 3779 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 3780 u32 snpcr;
07b7ddd9 3781
004777cb
DV		 3782 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3783 return -ENODEV;
3784
647416f9 3785 if (val > 3)
07b7ddd9
JB		 3786 return -EINVAL;
3787
c8c8fb33 3788 intel_runtime_pm_get(dev_priv);
647416f9 3789 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 3790
3791 /* Update the cache sharing policy here as well */
3792 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3793 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3794 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3795 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3796
c8c8fb33 3797 intel_runtime_pm_put(dev_priv);
647416f9 3798 return 0;
07b7ddd9
JB		 3799}
3800
647416f9
KC		 3801DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3802 i915_cache_sharing_get, i915_cache_sharing_set,
3803 "%llu\n");
07b7ddd9 3804
6d794d42
BW		 3805static int i915_forcewake_open(struct inode *inode, struct file *file)
3806{
3807 struct drm_device *dev = inode->i_private;
3808 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 3809
075edca4 3810 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3811 return 0;
3812
c8d9a590 3813 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3814
3815 return 0;
3816}
3817
c43b5634 3818static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 3819{
3820 struct drm_device *dev = inode->i_private;
3821 struct drm_i915_private *dev_priv = dev->dev_private;
3822
075edca4 3823 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 3824 return 0;
3825
c8d9a590 3826 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 3827
3828 return 0;
3829}
3830
3831static const struct file_operations i915_forcewake_fops = {
3832 .owner = THIS_MODULE,
3833 .open = i915_forcewake_open,
3834 .release = i915_forcewake_release,
3835};
3836
3837static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3838{
3839 struct drm_device *dev = minor->dev;
3840 struct dentry *ent;
3841
3842 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 3843 S_IRUSR,
6d794d42
BW		 3844 root, dev,
3845 &i915_forcewake_fops);
f3c5fe97
WY		 3846 if (!ent)
3847 return -ENOMEM;
6d794d42 3848
8eb57294 3849 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 3850}
3851
6a9c308d
DV		 3852static int i915_debugfs_create(struct dentry *root,
3853 struct drm_minor *minor,
3854 const char *name,
3855 const struct file_operations *fops)
07b7ddd9
JB		 3856{
3857 struct drm_device *dev = minor->dev;
3858 struct dentry *ent;
3859
6a9c308d 3860 ent = debugfs_create_file(name,
07b7ddd9
JB		 3861 S_IRUGO | S_IWUSR,
3862 root, dev,
6a9c308d 3863 fops);
f3c5fe97
WY		 3864 if (!ent)
3865 return -ENOMEM;
07b7ddd9 3866
6a9c308d 3867 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 3868}
3869
06c5bf8c 3870static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 3871 {"i915_capabilities", i915_capabilities, 0},
73aa808f 3872 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 3873 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 3874 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 3875 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 3876 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 3877 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 3878 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 3879 {"i915_gem_request", i915_gem_request_info, 0},
3880 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 3881 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 3882 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 3883 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3884 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3885 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 3886 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
adb4bd12 3887 {"i915_frequency_info", i915_frequency_info, 0},
f97108d1 3888 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 3889 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 3890 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 3891 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 3892 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 3893 {"i915_sr_status", i915_sr_status, 0},
44834a67 3894 {"i915_opregion", i915_opregion, 0},
37811fcc 3895 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 3896 {"i915_context_status", i915_context_status, 0},
6d794d42 3897 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 3898 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 3899 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 3900 {"i915_llc", i915_llc, 0},
e91fd8c6 3901 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 3902 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 3903 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 3904 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 3905 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 3906 {"i915_display_info", i915_display_info, 0},
e04934cf 3907 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 3908 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
2017263e 3909};
27c202ad 3910#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 3911
06c5bf8c 3912static const struct i915_debugfs_files {
34b9674c
DV		 3913 const char *name;
3914 const struct file_operations *fops;
3915} i915_debugfs_files[] = {
3916 {"i915_wedged", &i915_wedged_fops},
3917 {"i915_max_freq", &i915_max_freq_fops},
3918 {"i915_min_freq", &i915_min_freq_fops},
3919 {"i915_cache_sharing", &i915_cache_sharing_fops},
3920 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 3921 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3922 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 3923 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3924 {"i915_error_state", &i915_error_state_fops},
3925 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 3926 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 3927 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3928 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3929 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
34b9674c
DV		 3930};
3931
07144428
DL		 3932void intel_display_crc_init(struct drm_device *dev)
3933{
3934 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 3935 enum pipe pipe;
07144428 3936
b378360e
DV		 3937 for_each_pipe(pipe) {
3938 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 3939
d538bbdf
DL		 3940 pipe_crc->opened = false;
3941 spin_lock_init(&pipe_crc->lock);
07144428
DL		 3942 init_waitqueue_head(&pipe_crc->wq);
3943 }
3944}
3945
27c202ad 3946int i915_debugfs_init(struct drm_minor *minor)
2017263e 3947{
34b9674c 3948 int ret, i;
f3cd474b 3949
6d794d42 3950 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 3951 if (ret)
3952 return ret;
6a9c308d 3953
07144428
DL		 3954 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3955 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3956 if (ret)
3957 return ret;
3958 }
3959
34b9674c
DV		 3960 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3961 ret = i915_debugfs_create(minor->debugfs_root, minor,
3962 i915_debugfs_files[i].name,
3963 i915_debugfs_files[i].fops);
3964 if (ret)
3965 return ret;
3966 }
40633219 3967
27c202ad
BG		 3968 return drm_debugfs_create_files(i915_debugfs_list,
3969 I915_DEBUGFS_ENTRIES,
2017263e
BG		 3970 minor->debugfs_root, minor);
3971}
3972
27c202ad 3973void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 3974{
34b9674c
DV		 3975 int i;
3976
27c202ad
BG		 3977 drm_debugfs_remove_files(i915_debugfs_list,
3978 I915_DEBUGFS_ENTRIES, minor);
07144428 3979
6d794d42
BW		 3980 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3981 1, minor);
07144428 3982
e309a997 3983 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 3984 struct drm_info_list *info_list =
3985 (struct drm_info_list *)&i915_pipe_crc_data[i];
3986
3987 drm_debugfs_remove_files(info_list, 1, minor);
3988 }
3989
34b9674c
DV		 3990 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3991 struct drm_info_list *info_list =
3992 (struct drm_info_list *) i915_debugfs_files[i].fops;
3993
3994 drm_debugfs_remove_files(info_list, 1, minor);
3995 }
2017263e 3996}
Michael's Linux tree.