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drm/i915: fix use after free during eDP encoder destroying
[people/ms/linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
CommitLineData
2017263e
BG		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
b2c88f5b 30#include <linux/circ_buf.h>
926321d5 31#include <linux/ctype.h>
f3cd474b 32#include <linux/debugfs.h>
5a0e3ad6 33#include <linux/slab.h>
2d1a8a48 34#include <linux/export.h>
6d2b8885 35#include <linux/list_sort.h>
ec013e7f 36#include <asm/msr-index.h>
760285e7 37#include <drm/drmP.h>
4e5359cd 38#include "intel_drv.h"
e5c65260 39#include "intel_ringbuffer.h"
760285e7 40#include <drm/i915_drm.h>
2017263e
BG		 41#include "i915_drv.h"
42
f13d3f73 43enum {
69dc4987 44 ACTIVE_LIST,
f13d3f73 45 INACTIVE_LIST,
d21d5975 46 PINNED_LIST,
f13d3f73 47};
2017263e 48
70d39fe4
CW		 49static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
497666d8
DL		 54/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
70d39fe4
CW		 80static int i915_capabilities(struct seq_file *m, void *data)
81{
9f25d007 82 struct drm_info_node *node = m->private;
70d39fe4
CW		 83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
03d00ac5 87 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
79fc46df
DL		 88#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
70d39fe4
CW		 93
94 return 0;
95}
2017263e 96
05394f39 97static const char *get_pin_flag(struct drm_i915_gem_object *obj)
a6172a80 98{
4feb7659 99 if (i915_gem_obj_is_pinned(obj))
a6172a80
CW		 100 return "p";
101 else
102 return " ";
103}
104
05394f39 105static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
a6172a80 106{
0206e353
AJ		 107 switch (obj->tiling_mode) {
108 default:
109 case I915_TILING_NONE: return " ";
110 case I915_TILING_X: return "X";
111 case I915_TILING_Y: return "Y";
112 }
a6172a80
CW		 113}
114
1d693bcc
BW		 115static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
116{
aff43766 117 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
1d693bcc
BW		 118}
119
37811fcc
CW		 120static void
121describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
122{
1d693bcc 123 struct i915_vma *vma;
d7f46fc4
BW		 124 int pin_count = 0;
125
fb1ae911 126 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
37811fcc
CW		 127 &obj->base,
128 get_pin_flag(obj),
129 get_tiling_flag(obj),
1d693bcc 130 get_global_flag(obj),
a05a5862 131 obj->base.size / 1024,
37811fcc
CW		 132 obj->base.read_domains,
133 obj->base.write_domain,
97b2a6a1
JH		 134 i915_gem_request_get_seqno(obj->last_read_req),
135 i915_gem_request_get_seqno(obj->last_write_req),
136 i915_gem_request_get_seqno(obj->last_fenced_req),
0a4cd7c8 137 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
37811fcc
CW		 138 obj->dirty ? " dirty" : "",
139 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
140 if (obj->base.name)
141 seq_printf(m, " (name: %d)", obj->base.name);
d7f46fc4
BW		 142 list_for_each_entry(vma, &obj->vma_list, vma_link)
143 if (vma->pin_count > 0)
144 pin_count++;
145 seq_printf(m, " (pinned x %d)", pin_count);
cc98b413
CW		 146 if (obj->pin_display)
147 seq_printf(m, " (display)");
37811fcc
CW		 148 if (obj->fence_reg != I915_FENCE_REG_NONE)
149 seq_printf(m, " (fence: %d)", obj->fence_reg);
1d693bcc
BW		 150 list_for_each_entry(vma, &obj->vma_list, vma_link) {
151 if (!i915_is_ggtt(vma->vm))
152 seq_puts(m, " (pp");
153 else
154 seq_puts(m, " (g");
fe14d5f4
TU		 155 seq_printf(m, "gtt offset: %08lx, size: %08lx, type: %u)",
156 vma->node.start, vma->node.size,
157 vma->ggtt_view.type);
1d693bcc 158 }
c1ad11fc
CW		 159 if (obj->stolen)
160 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
6299f992
CW		 161 if (obj->pin_mappable || obj->fault_mappable) {
162 char s[3], *t = s;
163 if (obj->pin_mappable)
164 *t++ = 'p';
165 if (obj->fault_mappable)
166 *t++ = 'f';
167 *t = '\0';
168 seq_printf(m, " (%s mappable)", s);
169 }
41c52415
JH		 170 if (obj->last_read_req != NULL)
171 seq_printf(m, " (%s)",
172 i915_gem_request_get_ring(obj->last_read_req)->name);
d5a81ef1
DV		 173 if (obj->frontbuffer_bits)
174 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
37811fcc
CW		 175}
176
273497e5 177static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
3ccfd19d 178{
ea0c76f8 179 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
3ccfd19d
BW		 180 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
181 seq_putc(m, ' ');
182}
183
433e12f7 184static int i915_gem_object_list_info(struct seq_file *m, void *data)
2017263e 185{
9f25d007 186 struct drm_info_node *node = m->private;
433e12f7
BG		 187 uintptr_t list = (uintptr_t) node->info_ent->data;
188 struct list_head *head;
2017263e 189 struct drm_device *dev = node->minor->dev;
5cef07e1
BW		 190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct i915_address_space *vm = &dev_priv->gtt.base;
ca191b13 192 struct i915_vma *vma;
8f2480fb
CW		 193 size_t total_obj_size, total_gtt_size;
194 int count, ret;
de227ef0
CW		 195
196 ret = mutex_lock_interruptible(&dev->struct_mutex);
197 if (ret)
198 return ret;
2017263e 199
ca191b13 200 /* FIXME: the user of this interface might want more than just GGTT */
433e12f7
BG		 201 switch (list) {
202 case ACTIVE_LIST:
267f0c90 203 seq_puts(m, "Active:\n");
5cef07e1 204 head = &vm->active_list;
433e12f7
BG		 205 break;
206 case INACTIVE_LIST:
267f0c90 207 seq_puts(m, "Inactive:\n");
5cef07e1 208 head = &vm->inactive_list;
433e12f7 209 break;
433e12f7 210 default:
de227ef0
CW		 211 mutex_unlock(&dev->struct_mutex);
212 return -EINVAL;
2017263e 213 }
2017263e 214
8f2480fb 215 total_obj_size = total_gtt_size = count = 0;
ca191b13
BW		 216 list_for_each_entry(vma, head, mm_list) {
217 seq_printf(m, " ");
218 describe_obj(m, vma->obj);
219 seq_printf(m, "\n");
220 total_obj_size += vma->obj->base.size;
221 total_gtt_size += vma->node.size;
8f2480fb 222 count++;
2017263e 223 }
de227ef0 224 mutex_unlock(&dev->struct_mutex);
5e118f41 225
8f2480fb
CW		 226 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
227 count, total_obj_size, total_gtt_size);
2017263e
BG		 228 return 0;
229}
230
6d2b8885
CW		 231static int obj_rank_by_stolen(void *priv,
232 struct list_head *A, struct list_head *B)
233{
234 struct drm_i915_gem_object *a =
b25cb2f8 235 container_of(A, struct drm_i915_gem_object, obj_exec_link);
6d2b8885 236 struct drm_i915_gem_object *b =
b25cb2f8 237 container_of(B, struct drm_i915_gem_object, obj_exec_link);
6d2b8885
CW		 238
239 return a->stolen->start - b->stolen->start;
240}
241
242static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
243{
9f25d007 244 struct drm_info_node *node = m->private;
6d2b8885
CW		 245 struct drm_device *dev = node->minor->dev;
246 struct drm_i915_private *dev_priv = dev->dev_private;
247 struct drm_i915_gem_object *obj;
248 size_t total_obj_size, total_gtt_size;
249 LIST_HEAD(stolen);
250 int count, ret;
251
252 ret = mutex_lock_interruptible(&dev->struct_mutex);
253 if (ret)
254 return ret;
255
256 total_obj_size = total_gtt_size = count = 0;
257 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
258 if (obj->stolen == NULL)
259 continue;
260
b25cb2f8 261 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 262
263 total_obj_size += obj->base.size;
264 total_gtt_size += i915_gem_obj_ggtt_size(obj);
265 count++;
266 }
267 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
268 if (obj->stolen == NULL)
269 continue;
270
b25cb2f8 271 list_add(&obj->obj_exec_link, &stolen);
6d2b8885
CW		 272
273 total_obj_size += obj->base.size;
274 count++;
275 }
276 list_sort(NULL, &stolen, obj_rank_by_stolen);
277 seq_puts(m, "Stolen:\n");
278 while (!list_empty(&stolen)) {
b25cb2f8 279 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
6d2b8885
CW		 280 seq_puts(m, " ");
281 describe_obj(m, obj);
282 seq_putc(m, '\n');
b25cb2f8 283 list_del_init(&obj->obj_exec_link);
6d2b8885
CW		 284 }
285 mutex_unlock(&dev->struct_mutex);
286
287 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
288 count, total_obj_size, total_gtt_size);
289 return 0;
290}
291
6299f992
CW		 292#define count_objects(list, member) do { \
293 list_for_each_entry(obj, list, member) { \
f343c5f6 294 size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 295 ++count; \
296 if (obj->map_and_fenceable) { \
f343c5f6 297 mappable_size += i915_gem_obj_ggtt_size(obj); \
6299f992
CW		 298 ++mappable_count; \
299 } \
300 } \
0206e353 301} while (0)
6299f992 302
2db8e9d6 303struct file_stats {
6313c204 304 struct drm_i915_file_private *file_priv;
2db8e9d6 305 int count;
c67a17e9
CW		 306 size_t total, unbound;
307 size_t global, shared;
308 size_t active, inactive;
2db8e9d6
CW		 309};
310
311static int per_file_stats(int id, void *ptr, void *data)
312{
313 struct drm_i915_gem_object *obj = ptr;
314 struct file_stats *stats = data;
6313c204 315 struct i915_vma *vma;
2db8e9d6
CW		 316
317 stats->count++;
318 stats->total += obj->base.size;
319
c67a17e9
CW		 320 if (obj->base.name || obj->base.dma_buf)
321 stats->shared += obj->base.size;
322
6313c204
CW		 323 if (USES_FULL_PPGTT(obj->base.dev)) {
324 list_for_each_entry(vma, &obj->vma_list, vma_link) {
325 struct i915_hw_ppgtt *ppgtt;
326
327 if (!drm_mm_node_allocated(&vma->node))
328 continue;
329
330 if (i915_is_ggtt(vma->vm)) {
331 stats->global += obj->base.size;
332 continue;
333 }
334
335 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
4d884705 336 if (ppgtt->file_priv != stats->file_priv)
6313c204
CW		 337 continue;
338
41c52415 339 if (obj->active) /* XXX per-vma statistic */
6313c204
CW		 340 stats->active += obj->base.size;
341 else
342 stats->inactive += obj->base.size;
343
344 return 0;
345 }
2db8e9d6 346 } else {
6313c204
CW		 347 if (i915_gem_obj_ggtt_bound(obj)) {
348 stats->global += obj->base.size;
41c52415 349 if (obj->active)
6313c204
CW		 350 stats->active += obj->base.size;
351 else
352 stats->inactive += obj->base.size;
353 return 0;
354 }
2db8e9d6
CW		 355 }
356
6313c204
CW		 357 if (!list_empty(&obj->global_list))
358 stats->unbound += obj->base.size;
359
2db8e9d6
CW		 360 return 0;
361}
362
ca191b13
BW		 363#define count_vmas(list, member) do { \
364 list_for_each_entry(vma, list, member) { \
365 size += i915_gem_obj_ggtt_size(vma->obj); \
366 ++count; \
367 if (vma->obj->map_and_fenceable) { \
368 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
369 ++mappable_count; \
370 } \
371 } \
372} while (0)
373
374static int i915_gem_object_info(struct seq_file *m, void* data)
73aa808f 375{
9f25d007 376 struct drm_info_node *node = m->private;
73aa808f
CW		 377 struct drm_device *dev = node->minor->dev;
378 struct drm_i915_private *dev_priv = dev->dev_private;
b7abb714
CW		 379 u32 count, mappable_count, purgeable_count;
380 size_t size, mappable_size, purgeable_size;
6299f992 381 struct drm_i915_gem_object *obj;
5cef07e1 382 struct i915_address_space *vm = &dev_priv->gtt.base;
2db8e9d6 383 struct drm_file *file;
ca191b13 384 struct i915_vma *vma;
73aa808f
CW		 385 int ret;
386
387 ret = mutex_lock_interruptible(&dev->struct_mutex);
388 if (ret)
389 return ret;
390
6299f992
CW		 391 seq_printf(m, "%u objects, %zu bytes\n",
392 dev_priv->mm.object_count,
393 dev_priv->mm.object_memory);
394
395 size = count = mappable_size = mappable_count = 0;
35c20a60 396 count_objects(&dev_priv->mm.bound_list, global_list);
6299f992
CW		 397 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
398 count, mappable_count, size, mappable_size);
399
400 size = count = mappable_size = mappable_count = 0;
ca191b13 401 count_vmas(&vm->active_list, mm_list);
6299f992
CW		 402 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
403 count, mappable_count, size, mappable_size);
404
6299f992 405 size = count = mappable_size = mappable_count = 0;
ca191b13 406 count_vmas(&vm->inactive_list, mm_list);
6299f992
CW		 407 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
408 count, mappable_count, size, mappable_size);
409
b7abb714 410 size = count = purgeable_size = purgeable_count = 0;
35c20a60 411 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
6c085a72 412 size += obj->base.size, ++count;
b7abb714
CW		 413 if (obj->madv == I915_MADV_DONTNEED)
414 purgeable_size += obj->base.size, ++purgeable_count;
415 }
6c085a72
CW		 416 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
417
6299f992 418 size = count = mappable_size = mappable_count = 0;
35c20a60 419 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
6299f992 420 if (obj->fault_mappable) {
f343c5f6 421 size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 422 ++count;
423 }
424 if (obj->pin_mappable) {
f343c5f6 425 mappable_size += i915_gem_obj_ggtt_size(obj);
6299f992
CW		 426 ++mappable_count;
427 }
b7abb714
CW		 428 if (obj->madv == I915_MADV_DONTNEED) {
429 purgeable_size += obj->base.size;
430 ++purgeable_count;
431 }
6299f992 432 }
b7abb714
CW		 433 seq_printf(m, "%u purgeable objects, %zu bytes\n",
434 purgeable_count, purgeable_size);
6299f992
CW		 435 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
436 mappable_count, mappable_size);
437 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
438 count, size);
439
93d18799 440 seq_printf(m, "%zu [%lu] gtt total\n",
853ba5d2
BW		 441 dev_priv->gtt.base.total,
442 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
73aa808f 443
267f0c90 444 seq_putc(m, '\n');
2db8e9d6
CW		 445 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
446 struct file_stats stats;
3ec2f427 447 struct task_struct *task;
2db8e9d6
CW		 448
449 memset(&stats, 0, sizeof(stats));
6313c204 450 stats.file_priv = file->driver_priv;
5b5ffff0 451 spin_lock(&file->table_lock);
2db8e9d6 452 idr_for_each(&file->object_idr, per_file_stats, &stats);
5b5ffff0 453 spin_unlock(&file->table_lock);
3ec2f427
TH		 454 /*
455 * Although we have a valid reference on file->pid, that does
456 * not guarantee that the task_struct who called get_pid() is
457 * still alive (e.g. get_pid(current) => fork() => exit()).
458 * Therefore, we need to protect this ->comm access using RCU.
459 */
460 rcu_read_lock();
461 task = pid_task(file->pid, PIDTYPE_PID);
c67a17e9 462 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n",
3ec2f427 463 task ? task->comm : "<unknown>",
2db8e9d6
CW		 464 stats.count,
465 stats.total,
466 stats.active,
467 stats.inactive,
6313c204 468 stats.global,
c67a17e9 469 stats.shared,
2db8e9d6 470 stats.unbound);
3ec2f427 471 rcu_read_unlock();
2db8e9d6
CW		 472 }
473
73aa808f
CW		 474 mutex_unlock(&dev->struct_mutex);
475
476 return 0;
477}
478
aee56cff 479static int i915_gem_gtt_info(struct seq_file *m, void *data)
08c18323 480{
9f25d007 481 struct drm_info_node *node = m->private;
08c18323 482 struct drm_device *dev = node->minor->dev;
1b50247a 483 uintptr_t list = (uintptr_t) node->info_ent->data;
08c18323
CW		 484 struct drm_i915_private *dev_priv = dev->dev_private;
485 struct drm_i915_gem_object *obj;
486 size_t total_obj_size, total_gtt_size;
487 int count, ret;
488
489 ret = mutex_lock_interruptible(&dev->struct_mutex);
490 if (ret)
491 return ret;
492
493 total_obj_size = total_gtt_size = count = 0;
35c20a60 494 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
d7f46fc4 495 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
1b50247a
CW		 496 continue;
497
267f0c90 498 seq_puts(m, " ");
08c18323 499 describe_obj(m, obj);
267f0c90 500 seq_putc(m, '\n');
08c18323 501 total_obj_size += obj->base.size;
f343c5f6 502 total_gtt_size += i915_gem_obj_ggtt_size(obj);
08c18323
CW		 503 count++;
504 }
505
506 mutex_unlock(&dev->struct_mutex);
507
508 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
509 count, total_obj_size, total_gtt_size);
510
511 return 0;
512}
513
4e5359cd
SF		 514static int i915_gem_pageflip_info(struct seq_file *m, void *data)
515{
9f25d007 516 struct drm_info_node *node = m->private;
4e5359cd 517 struct drm_device *dev = node->minor->dev;
d6bbafa1 518 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd 519 struct intel_crtc *crtc;
8a270ebf
DV		 520 int ret;
521
522 ret = mutex_lock_interruptible(&dev->struct_mutex);
523 if (ret)
524 return ret;
4e5359cd 525
d3fcc808 526 for_each_intel_crtc(dev, crtc) {
9db4a9c7
JB		 527 const char pipe = pipe_name(crtc->pipe);
528 const char plane = plane_name(crtc->plane);
4e5359cd
SF		 529 struct intel_unpin_work *work;
530
5e2d7afc 531 spin_lock_irq(&dev->event_lock);
4e5359cd
SF		 532 work = crtc->unpin_work;
533 if (work == NULL) {
9db4a9c7 534 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
4e5359cd
SF		 535 pipe, plane);
536 } else {
d6bbafa1
CW		 537 u32 addr;
538
e7d841ca 539 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9db4a9c7 540 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
4e5359cd
SF		 541 pipe, plane);
542 } else {
9db4a9c7 543 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
4e5359cd
SF		 544 pipe, plane);
545 }
3a8a946e
DV		 546 if (work->flip_queued_req) {
547 struct intel_engine_cs *ring =
548 i915_gem_request_get_ring(work->flip_queued_req);
549
d6bbafa1 550 seq_printf(m, "Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d\n",
3a8a946e 551 ring->name,
f06cc1b9 552 i915_gem_request_get_seqno(work->flip_queued_req),
d6bbafa1 553 dev_priv->next_seqno,
3a8a946e 554 ring->get_seqno(ring, true),
1b5a433a 555 i915_gem_request_completed(work->flip_queued_req, true));
d6bbafa1
CW		 556 } else
557 seq_printf(m, "Flip not associated with any ring\n");
558 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
559 work->flip_queued_vblank,
560 work->flip_ready_vblank,
561 drm_vblank_count(dev, crtc->pipe));
4e5359cd 562 if (work->enable_stall_check)
267f0c90 563 seq_puts(m, "Stall check enabled, ");
4e5359cd 564 else
267f0c90 565 seq_puts(m, "Stall check waiting for page flip ioctl, ");
e7d841ca 566 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
4e5359cd 567
d6bbafa1
CW		 568 if (INTEL_INFO(dev)->gen >= 4)
569 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
570 else
571 addr = I915_READ(DSPADDR(crtc->plane));
572 seq_printf(m, "Current scanout address 0x%08x\n", addr);
573
4e5359cd 574 if (work->pending_flip_obj) {
d6bbafa1
CW		 575 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
576 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
4e5359cd
SF		 577 }
578 }
5e2d7afc 579 spin_unlock_irq(&dev->event_lock);
4e5359cd
SF		 580 }
581
8a270ebf
DV		 582 mutex_unlock(&dev->struct_mutex);
583
4e5359cd
SF		 584 return 0;
585}
586
2017263e
BG		 587static int i915_gem_request_info(struct seq_file *m, void *data)
588{
9f25d007 589 struct drm_info_node *node = m->private;
2017263e 590 struct drm_device *dev = node->minor->dev;
e277a1f8 591 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 592 struct intel_engine_cs *ring;
2017263e 593 struct drm_i915_gem_request *gem_request;
a2c7f6fd 594 int ret, count, i;
de227ef0
CW		 595
596 ret = mutex_lock_interruptible(&dev->struct_mutex);
597 if (ret)
598 return ret;
2017263e 599
c2c347a9 600 count = 0;
a2c7f6fd
CW		 601 for_each_ring(ring, dev_priv, i) {
602 if (list_empty(&ring->request_list))
603 continue;
604
605 seq_printf(m, "%s requests:\n", ring->name);
c2c347a9 606 list_for_each_entry(gem_request,
a2c7f6fd 607 &ring->request_list,
c2c347a9
CW		 608 list) {
609 seq_printf(m, " %d @ %d\n",
610 gem_request->seqno,
611 (int) (jiffies - gem_request->emitted_jiffies));
612 }
613 count++;
2017263e 614 }
de227ef0
CW		 615 mutex_unlock(&dev->struct_mutex);
616
c2c347a9 617 if (count == 0)
267f0c90 618 seq_puts(m, "No requests\n");
c2c347a9 619
2017263e
BG		 620 return 0;
621}
622
b2223497 623static void i915_ring_seqno_info(struct seq_file *m,
a4872ba6 624 struct intel_engine_cs *ring)
b2223497
CW		 625{
626 if (ring->get_seqno) {
43a7b924 627 seq_printf(m, "Current sequence (%s): %u\n",
b2eadbc8 628 ring->name, ring->get_seqno(ring, false));
b2223497
CW		 629 }
630}
631
2017263e
BG		 632static int i915_gem_seqno_info(struct seq_file *m, void *data)
633{
9f25d007 634 struct drm_info_node *node = m->private;
2017263e 635 struct drm_device *dev = node->minor->dev;
e277a1f8 636 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 637 struct intel_engine_cs *ring;
1ec14ad3 638 int ret, i;
de227ef0
CW		 639
640 ret = mutex_lock_interruptible(&dev->struct_mutex);
641 if (ret)
642 return ret;
c8c8fb33 643 intel_runtime_pm_get(dev_priv);
2017263e 644
a2c7f6fd
CW		 645 for_each_ring(ring, dev_priv, i)
646 i915_ring_seqno_info(m, ring);
de227ef0 647
c8c8fb33 648 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 649 mutex_unlock(&dev->struct_mutex);
650
2017263e
BG		 651 return 0;
652}
653
654
655static int i915_interrupt_info(struct seq_file *m, void *data)
656{
9f25d007 657 struct drm_info_node *node = m->private;
2017263e 658 struct drm_device *dev = node->minor->dev;
e277a1f8 659 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 660 struct intel_engine_cs *ring;
9db4a9c7 661 int ret, i, pipe;
de227ef0
CW		 662
663 ret = mutex_lock_interruptible(&dev->struct_mutex);
664 if (ret)
665 return ret;
c8c8fb33 666 intel_runtime_pm_get(dev_priv);
2017263e 667
74e1ca8c 668 if (IS_CHERRYVIEW(dev)) {
74e1ca8c
VS		 669 seq_printf(m, "Master Interrupt Control:\t%08x\n",
670 I915_READ(GEN8_MASTER_IRQ));
671
672 seq_printf(m, "Display IER:\t%08x\n",
673 I915_READ(VLV_IER));
674 seq_printf(m, "Display IIR:\t%08x\n",
675 I915_READ(VLV_IIR));
676 seq_printf(m, "Display IIR_RW:\t%08x\n",
677 I915_READ(VLV_IIR_RW));
678 seq_printf(m, "Display IMR:\t%08x\n",
679 I915_READ(VLV_IMR));
055e393f 680 for_each_pipe(dev_priv, pipe)
74e1ca8c
VS		 681 seq_printf(m, "Pipe %c stat:\t%08x\n",
682 pipe_name(pipe),
683 I915_READ(PIPESTAT(pipe)));
684
685 seq_printf(m, "Port hotplug:\t%08x\n",
686 I915_READ(PORT_HOTPLUG_EN));
687 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
688 I915_READ(VLV_DPFLIPSTAT));
689 seq_printf(m, "DPINVGTT:\t%08x\n",
690 I915_READ(DPINVGTT));
691
692 for (i = 0; i < 4; i++) {
693 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
694 i, I915_READ(GEN8_GT_IMR(i)));
695 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
696 i, I915_READ(GEN8_GT_IIR(i)));
697 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
698 i, I915_READ(GEN8_GT_IER(i)));
699 }
700
701 seq_printf(m, "PCU interrupt mask:\t%08x\n",
702 I915_READ(GEN8_PCU_IMR));
703 seq_printf(m, "PCU interrupt identity:\t%08x\n",
704 I915_READ(GEN8_PCU_IIR));
705 seq_printf(m, "PCU interrupt enable:\t%08x\n",
706 I915_READ(GEN8_PCU_IER));
707 } else if (INTEL_INFO(dev)->gen >= 8) {
a123f157
BW		 708 seq_printf(m, "Master Interrupt Control:\t%08x\n",
709 I915_READ(GEN8_MASTER_IRQ));
710
711 for (i = 0; i < 4; i++) {
712 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
713 i, I915_READ(GEN8_GT_IMR(i)));
714 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
715 i, I915_READ(GEN8_GT_IIR(i)));
716 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
717 i, I915_READ(GEN8_GT_IER(i)));
718 }
719
055e393f 720 for_each_pipe(dev_priv, pipe) {
f458ebbc 721 if (!intel_display_power_is_enabled(dev_priv,
22c59960
PZ		 722 POWER_DOMAIN_PIPE(pipe))) {
723 seq_printf(m, "Pipe %c power disabled\n",
724 pipe_name(pipe));
725 continue;
726 }
a123f157 727 seq_printf(m, "Pipe %c IMR:\t%08x\n",
07d27e20
DL		 728 pipe_name(pipe),
729 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
a123f157 730 seq_printf(m, "Pipe %c IIR:\t%08x\n",
07d27e20
DL		 731 pipe_name(pipe),
732 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
a123f157 733 seq_printf(m, "Pipe %c IER:\t%08x\n",
07d27e20
DL		 734 pipe_name(pipe),
735 I915_READ(GEN8_DE_PIPE_IER(pipe)));
a123f157
BW		 736 }
737
738 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
739 I915_READ(GEN8_DE_PORT_IMR));
740 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
741 I915_READ(GEN8_DE_PORT_IIR));
742 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
743 I915_READ(GEN8_DE_PORT_IER));
744
745 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
746 I915_READ(GEN8_DE_MISC_IMR));
747 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
748 I915_READ(GEN8_DE_MISC_IIR));
749 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
750 I915_READ(GEN8_DE_MISC_IER));
751
752 seq_printf(m, "PCU interrupt mask:\t%08x\n",
753 I915_READ(GEN8_PCU_IMR));
754 seq_printf(m, "PCU interrupt identity:\t%08x\n",
755 I915_READ(GEN8_PCU_IIR));
756 seq_printf(m, "PCU interrupt enable:\t%08x\n",
757 I915_READ(GEN8_PCU_IER));
758 } else if (IS_VALLEYVIEW(dev)) {
7e231dbe
JB		 759 seq_printf(m, "Display IER:\t%08x\n",
760 I915_READ(VLV_IER));
761 seq_printf(m, "Display IIR:\t%08x\n",
762 I915_READ(VLV_IIR));
763 seq_printf(m, "Display IIR_RW:\t%08x\n",
764 I915_READ(VLV_IIR_RW));
765 seq_printf(m, "Display IMR:\t%08x\n",
766 I915_READ(VLV_IMR));
055e393f 767 for_each_pipe(dev_priv, pipe)
7e231dbe
JB		 768 seq_printf(m, "Pipe %c stat:\t%08x\n",
769 pipe_name(pipe),
770 I915_READ(PIPESTAT(pipe)));
771
772 seq_printf(m, "Master IER:\t%08x\n",
773 I915_READ(VLV_MASTER_IER));
774
775 seq_printf(m, "Render IER:\t%08x\n",
776 I915_READ(GTIER));
777 seq_printf(m, "Render IIR:\t%08x\n",
778 I915_READ(GTIIR));
779 seq_printf(m, "Render IMR:\t%08x\n",
780 I915_READ(GTIMR));
781
782 seq_printf(m, "PM IER:\t\t%08x\n",
783 I915_READ(GEN6_PMIER));
784 seq_printf(m, "PM IIR:\t\t%08x\n",
785 I915_READ(GEN6_PMIIR));
786 seq_printf(m, "PM IMR:\t\t%08x\n",
787 I915_READ(GEN6_PMIMR));
788
789 seq_printf(m, "Port hotplug:\t%08x\n",
790 I915_READ(PORT_HOTPLUG_EN));
791 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
792 I915_READ(VLV_DPFLIPSTAT));
793 seq_printf(m, "DPINVGTT:\t%08x\n",
794 I915_READ(DPINVGTT));
795
796 } else if (!HAS_PCH_SPLIT(dev)) {
5f6a1695
ZW		 797 seq_printf(m, "Interrupt enable: %08x\n",
798 I915_READ(IER));
799 seq_printf(m, "Interrupt identity: %08x\n",
800 I915_READ(IIR));
801 seq_printf(m, "Interrupt mask: %08x\n",
802 I915_READ(IMR));
055e393f 803 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 804 seq_printf(m, "Pipe %c stat: %08x\n",
805 pipe_name(pipe),
806 I915_READ(PIPESTAT(pipe)));
5f6a1695
ZW		 807 } else {
808 seq_printf(m, "North Display Interrupt enable: %08x\n",
809 I915_READ(DEIER));
810 seq_printf(m, "North Display Interrupt identity: %08x\n",
811 I915_READ(DEIIR));
812 seq_printf(m, "North Display Interrupt mask: %08x\n",
813 I915_READ(DEIMR));
814 seq_printf(m, "South Display Interrupt enable: %08x\n",
815 I915_READ(SDEIER));
816 seq_printf(m, "South Display Interrupt identity: %08x\n",
817 I915_READ(SDEIIR));
818 seq_printf(m, "South Display Interrupt mask: %08x\n",
819 I915_READ(SDEIMR));
820 seq_printf(m, "Graphics Interrupt enable: %08x\n",
821 I915_READ(GTIER));
822 seq_printf(m, "Graphics Interrupt identity: %08x\n",
823 I915_READ(GTIIR));
824 seq_printf(m, "Graphics Interrupt mask: %08x\n",
825 I915_READ(GTIMR));
826 }
a2c7f6fd 827 for_each_ring(ring, dev_priv, i) {
a123f157 828 if (INTEL_INFO(dev)->gen >= 6) {
a2c7f6fd
CW		 829 seq_printf(m,
830 "Graphics Interrupt mask (%s): %08x\n",
831 ring->name, I915_READ_IMR(ring));
9862e600 832 }
a2c7f6fd 833 i915_ring_seqno_info(m, ring);
9862e600 834 }
c8c8fb33 835 intel_runtime_pm_put(dev_priv);
de227ef0
CW		 836 mutex_unlock(&dev->struct_mutex);
837
2017263e
BG		 838 return 0;
839}
840
a6172a80
CW		 841static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
842{
9f25d007 843 struct drm_info_node *node = m->private;
a6172a80 844 struct drm_device *dev = node->minor->dev;
e277a1f8 845 struct drm_i915_private *dev_priv = dev->dev_private;
de227ef0
CW		 846 int i, ret;
847
848 ret = mutex_lock_interruptible(&dev->struct_mutex);
849 if (ret)
850 return ret;
a6172a80
CW		 851
852 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
853 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
854 for (i = 0; i < dev_priv->num_fence_regs; i++) {
05394f39 855 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
a6172a80 856
6c085a72
CW		 857 seq_printf(m, "Fence %d, pin count = %d, object = ",
858 i, dev_priv->fence_regs[i].pin_count);
c2c347a9 859 if (obj == NULL)
267f0c90 860 seq_puts(m, "unused");
c2c347a9 861 else
05394f39 862 describe_obj(m, obj);
267f0c90 863 seq_putc(m, '\n');
a6172a80
CW		 864 }
865
05394f39 866 mutex_unlock(&dev->struct_mutex);
a6172a80
CW		 867 return 0;
868}
869
2017263e
BG		 870static int i915_hws_info(struct seq_file *m, void *data)
871{
9f25d007 872 struct drm_info_node *node = m->private;
2017263e 873 struct drm_device *dev = node->minor->dev;
e277a1f8 874 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 875 struct intel_engine_cs *ring;
1a240d4d 876 const u32 *hws;
4066c0ae
CW		 877 int i;
878
1ec14ad3 879 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
1a240d4d 880 hws = ring->status_page.page_addr;
2017263e
BG		 881 if (hws == NULL)
882 return 0;
883
884 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
885 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
886 i * 4,
887 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
888 }
889 return 0;
890}
891
d5442303
DV		 892static ssize_t
893i915_error_state_write(struct file *filp,
894 const char __user *ubuf,
895 size_t cnt,
896 loff_t *ppos)
897{
edc3d884 898 struct i915_error_state_file_priv *error_priv = filp->private_data;
d5442303 899 struct drm_device *dev = error_priv->dev;
22bcfc6a 900 int ret;
d5442303
DV		 901
902 DRM_DEBUG_DRIVER("Resetting error state\n");
903
22bcfc6a
DV		 904 ret = mutex_lock_interruptible(&dev->struct_mutex);
905 if (ret)
906 return ret;
907
d5442303
DV		 908 i915_destroy_error_state(dev);
909 mutex_unlock(&dev->struct_mutex);
910
911 return cnt;
912}
913
914static int i915_error_state_open(struct inode *inode, struct file *file)
915{
916 struct drm_device *dev = inode->i_private;
d5442303 917 struct i915_error_state_file_priv *error_priv;
d5442303
DV		 918
919 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
920 if (!error_priv)
921 return -ENOMEM;
922
923 error_priv->dev = dev;
924
95d5bfb3 925 i915_error_state_get(dev, error_priv);
d5442303 926
edc3d884
MK		 927 file->private_data = error_priv;
928
929 return 0;
d5442303
DV		 930}
931
932static int i915_error_state_release(struct inode *inode, struct file *file)
933{
edc3d884 934 struct i915_error_state_file_priv *error_priv = file->private_data;
d5442303 935
95d5bfb3 936 i915_error_state_put(error_priv);
d5442303
DV		 937 kfree(error_priv);
938
edc3d884
MK		 939 return 0;
940}
941
4dc955f7
MK		 942static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
943 size_t count, loff_t *pos)
944{
945 struct i915_error_state_file_priv *error_priv = file->private_data;
946 struct drm_i915_error_state_buf error_str;
947 loff_t tmp_pos = 0;
948 ssize_t ret_count = 0;
949 int ret;
950
0a4cd7c8 951 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
4dc955f7
MK		 952 if (ret)
953 return ret;
edc3d884 954
fc16b48b 955 ret = i915_error_state_to_str(&error_str, error_priv);
edc3d884
MK		 956 if (ret)
957 goto out;
958
edc3d884
MK		 959 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
960 error_str.buf,
961 error_str.bytes);
962
963 if (ret_count < 0)
964 ret = ret_count;
965 else
966 *pos = error_str.start + ret_count;
967out:
4dc955f7 968 i915_error_state_buf_release(&error_str);
edc3d884 969 return ret ?: ret_count;
d5442303
DV		 970}
971
972static const struct file_operations i915_error_state_fops = {
973 .owner = THIS_MODULE,
974 .open = i915_error_state_open,
edc3d884 975 .read = i915_error_state_read,
d5442303
DV		 976 .write = i915_error_state_write,
977 .llseek = default_llseek,
978 .release = i915_error_state_release,
979};
980
647416f9
KC		 981static int
982i915_next_seqno_get(void *data, u64 *val)
40633219 983{
647416f9 984 struct drm_device *dev = data;
e277a1f8 985 struct drm_i915_private *dev_priv = dev->dev_private;
40633219
MK		 986 int ret;
987
988 ret = mutex_lock_interruptible(&dev->struct_mutex);
989 if (ret)
990 return ret;
991
647416f9 992 *val = dev_priv->next_seqno;
40633219
MK		 993 mutex_unlock(&dev->struct_mutex);
994
647416f9 995 return 0;
40633219
MK		 996}
997
647416f9
KC		 998static int
999i915_next_seqno_set(void *data, u64 val)
1000{
1001 struct drm_device *dev = data;
40633219
MK		 1002 int ret;
1003
40633219
MK		 1004 ret = mutex_lock_interruptible(&dev->struct_mutex);
1005 if (ret)
1006 return ret;
1007
e94fbaa8 1008 ret = i915_gem_set_seqno(dev, val);
40633219
MK		 1009 mutex_unlock(&dev->struct_mutex);
1010
647416f9 1011 return ret;
40633219
MK		 1012}
1013
647416f9
KC		 1014DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1015 i915_next_seqno_get, i915_next_seqno_set,
3a3b4f98 1016 "0x%llx\n");
40633219 1017
adb4bd12 1018static int i915_frequency_info(struct seq_file *m, void *unused)
f97108d1 1019{
9f25d007 1020 struct drm_info_node *node = m->private;
f97108d1 1021 struct drm_device *dev = node->minor->dev;
e277a1f8 1022 struct drm_i915_private *dev_priv = dev->dev_private;
c8c8fb33
PZ		 1023 int ret = 0;
1024
1025 intel_runtime_pm_get(dev_priv);
3b8d8d91 1026
5c9669ce
TR		 1027 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1028
3b8d8d91
JB		 1029 if (IS_GEN5(dev)) {
1030 u16 rgvswctl = I915_READ16(MEMSWCTL);
1031 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1032
1033 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1034 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1035 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1036 MEMSTAT_VID_SHIFT);
1037 seq_printf(m, "Current P-state: %d\n",
1038 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
daa3afb2
TR		 1039 } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1040 IS_BROADWELL(dev)) {
3b8d8d91
JB		 1041 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1042 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1043 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
0d8f9491 1044 u32 rpmodectl, rpinclimit, rpdeclimit;
8e8c06cd 1045 u32 rpstat, cagf, reqf;
ccab5c82
JB		 1046 u32 rpupei, rpcurup, rpprevup;
1047 u32 rpdownei, rpcurdown, rpprevdown;
9dd3c605 1048 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
3b8d8d91
JB		 1049 int max_freq;
1050
1051 /* RPSTAT1 is in the GT power well */
d1ebd816
BW		 1052 ret = mutex_lock_interruptible(&dev->struct_mutex);
1053 if (ret)
c8c8fb33 1054 goto out;
d1ebd816 1055
c8d9a590 1056 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3b8d8d91 1057
8e8c06cd
CW		 1058 reqf = I915_READ(GEN6_RPNSWREQ);
1059 reqf &= ~GEN6_TURBO_DISABLE;
daa3afb2 1060 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8e8c06cd
CW		 1061 reqf >>= 24;
1062 else
1063 reqf >>= 25;
1064 reqf *= GT_FREQUENCY_MULTIPLIER;
1065
0d8f9491
CW		 1066 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1067 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1068 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1069
ccab5c82
JB		 1070 rpstat = I915_READ(GEN6_RPSTAT1);
1071 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1072 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1073 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1074 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1075 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1076 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
daa3afb2 1077 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
f82855d3
BW		 1078 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1079 else
1080 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1081 cagf *= GT_FREQUENCY_MULTIPLIER;
ccab5c82 1082
c8d9a590 1083 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
d1ebd816
BW		 1084 mutex_unlock(&dev->struct_mutex);
1085
9dd3c605
PZ		 1086 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1087 pm_ier = I915_READ(GEN6_PMIER);
1088 pm_imr = I915_READ(GEN6_PMIMR);
1089 pm_isr = I915_READ(GEN6_PMISR);
1090 pm_iir = I915_READ(GEN6_PMIIR);
1091 pm_mask = I915_READ(GEN6_PMINTRMSK);
1092 } else {
1093 pm_ier = I915_READ(GEN8_GT_IER(2));
1094 pm_imr = I915_READ(GEN8_GT_IMR(2));
1095 pm_isr = I915_READ(GEN8_GT_ISR(2));
1096 pm_iir = I915_READ(GEN8_GT_IIR(2));
1097 pm_mask = I915_READ(GEN6_PMINTRMSK);
1098 }
0d8f9491 1099 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
9dd3c605 1100 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
3b8d8d91 1101 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
3b8d8d91
JB		 1102 seq_printf(m, "Render p-state ratio: %d\n",
1103 (gt_perf_status & 0xff00) >> 8);
1104 seq_printf(m, "Render p-state VID: %d\n",
1105 gt_perf_status & 0xff);
1106 seq_printf(m, "Render p-state limit: %d\n",
1107 rp_state_limits & 0xff);
0d8f9491
CW		 1108 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1109 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1110 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1111 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
8e8c06cd 1112 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
f82855d3 1113 seq_printf(m, "CAGF: %dMHz\n", cagf);
ccab5c82
JB		 1114 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1115 GEN6_CURICONT_MASK);
1116 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1117 GEN6_CURBSYTAVG_MASK);
1118 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1119 GEN6_CURBSYTAVG_MASK);
1120 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1121 GEN6_CURIAVG_MASK);
1122 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1123 GEN6_CURBSYTAVG_MASK);
1124 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1125 GEN6_CURBSYTAVG_MASK);
3b8d8d91
JB		 1126
1127 max_freq = (rp_state_cap & 0xff0000) >> 16;
1128 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
c8735b0c 1129 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1130
1131 max_freq = (rp_state_cap & 0xff00) >> 8;
1132 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
c8735b0c 1133 max_freq * GT_FREQUENCY_MULTIPLIER);
3b8d8d91
JB		 1134
1135 max_freq = rp_state_cap & 0xff;
1136 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
c8735b0c 1137 max_freq * GT_FREQUENCY_MULTIPLIER);
31c77388
BW		 1138
1139 seq_printf(m, "Max overclocked frequency: %dMHz\n",
b39fb297 1140 dev_priv->rps.max_freq * GT_FREQUENCY_MULTIPLIER);
0a073b84 1141 } else if (IS_VALLEYVIEW(dev)) {
03af2045 1142 u32 freq_sts;
0a073b84 1143
259bd5d4 1144 mutex_lock(&dev_priv->rps.hw_lock);
64936258 1145 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 1146 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1147 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1148
0a073b84 1149 seq_printf(m, "max GPU freq: %d MHz\n",
b2435c94 1150 vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq));
0a073b84 1151
0a073b84 1152 seq_printf(m, "min GPU freq: %d MHz\n",
b2435c94 1153 vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq));
03af2045
VS		 1154
1155 seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
b2435c94 1156 vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
0a073b84
JB		 1157
1158 seq_printf(m, "current GPU freq: %d MHz\n",
2ec3815f 1159 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
259bd5d4 1160 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91 1161 } else {
267f0c90 1162 seq_puts(m, "no P-state info available\n");
3b8d8d91 1163 }
f97108d1 1164
c8c8fb33
PZ		 1165out:
1166 intel_runtime_pm_put(dev_priv);
1167 return ret;
f97108d1
JB		 1168}
1169
4d85529d 1170static int ironlake_drpc_info(struct seq_file *m)
f97108d1 1171{
9f25d007 1172 struct drm_info_node *node = m->private;
f97108d1 1173 struct drm_device *dev = node->minor->dev;
e277a1f8 1174 struct drm_i915_private *dev_priv = dev->dev_private;
616fdb5a
BW		 1175 u32 rgvmodectl, rstdbyctl;
1176 u16 crstandvid;
1177 int ret;
1178
1179 ret = mutex_lock_interruptible(&dev->struct_mutex);
1180 if (ret)
1181 return ret;
c8c8fb33 1182 intel_runtime_pm_get(dev_priv);
616fdb5a
BW		 1183
1184 rgvmodectl = I915_READ(MEMMODECTL);
1185 rstdbyctl = I915_READ(RSTDBYCTL);
1186 crstandvid = I915_READ16(CRSTANDVID);
1187
c8c8fb33 1188 intel_runtime_pm_put(dev_priv);
616fdb5a 1189 mutex_unlock(&dev->struct_mutex);
f97108d1
JB		 1190
1191 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1192 "yes" : "no");
1193 seq_printf(m, "Boost freq: %d\n",
1194 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1195 MEMMODE_BOOST_FREQ_SHIFT);
1196 seq_printf(m, "HW control enabled: %s\n",
1197 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1198 seq_printf(m, "SW control enabled: %s\n",
1199 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1200 seq_printf(m, "Gated voltage change: %s\n",
1201 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1202 seq_printf(m, "Starting frequency: P%d\n",
1203 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
7648fa99 1204 seq_printf(m, "Max P-state: P%d\n",
f97108d1 1205 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
7648fa99
JB		 1206 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1207 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1208 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1209 seq_printf(m, "Render standby enabled: %s\n",
1210 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
267f0c90 1211 seq_puts(m, "Current RS state: ");
88271da3
JB		 1212 switch (rstdbyctl & RSX_STATUS_MASK) {
1213 case RSX_STATUS_ON:
267f0c90 1214 seq_puts(m, "on\n");
88271da3
JB		 1215 break;
1216 case RSX_STATUS_RC1:
267f0c90 1217 seq_puts(m, "RC1\n");
88271da3
JB		 1218 break;
1219 case RSX_STATUS_RC1E:
267f0c90 1220 seq_puts(m, "RC1E\n");
88271da3
JB		 1221 break;
1222 case RSX_STATUS_RS1:
267f0c90 1223 seq_puts(m, "RS1\n");
88271da3
JB		 1224 break;
1225 case RSX_STATUS_RS2:
267f0c90 1226 seq_puts(m, "RS2 (RC6)\n");
88271da3
JB		 1227 break;
1228 case RSX_STATUS_RS3:
267f0c90 1229 seq_puts(m, "RC3 (RC6+)\n");
88271da3
JB		 1230 break;
1231 default:
267f0c90 1232 seq_puts(m, "unknown\n");
88271da3
JB		 1233 break;
1234 }
f97108d1
JB		 1235
1236 return 0;
1237}
1238
669ab5aa
D		 1239static int vlv_drpc_info(struct seq_file *m)
1240{
1241
9f25d007 1242 struct drm_info_node *node = m->private;
669ab5aa
D		 1243 struct drm_device *dev = node->minor->dev;
1244 struct drm_i915_private *dev_priv = dev->dev_private;
6b312cd3 1245 u32 rpmodectl1, rcctl1, pw_status;
669ab5aa
D		 1246 unsigned fw_rendercount = 0, fw_mediacount = 0;
1247
d46c0517
ID		 1248 intel_runtime_pm_get(dev_priv);
1249
6b312cd3 1250 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
669ab5aa
D		 1251 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1252 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1253
d46c0517
ID		 1254 intel_runtime_pm_put(dev_priv);
1255
669ab5aa
D		 1256 seq_printf(m, "Video Turbo Mode: %s\n",
1257 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1258 seq_printf(m, "Turbo enabled: %s\n",
1259 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1260 seq_printf(m, "HW control enabled: %s\n",
1261 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1262 seq_printf(m, "SW control enabled: %s\n",
1263 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1264 GEN6_RP_MEDIA_SW_MODE));
1265 seq_printf(m, "RC6 Enabled: %s\n",
1266 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1267 GEN6_RC_CTL_EI_MODE(1))));
1268 seq_printf(m, "Render Power Well: %s\n",
6b312cd3 1269 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1270 seq_printf(m, "Media Power Well: %s\n",
6b312cd3 1271 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
669ab5aa 1272
9cc19be5
ID		 1273 seq_printf(m, "Render RC6 residency since boot: %u\n",
1274 I915_READ(VLV_GT_RENDER_RC6));
1275 seq_printf(m, "Media RC6 residency since boot: %u\n",
1276 I915_READ(VLV_GT_MEDIA_RC6));
1277
669ab5aa
D		 1278 spin_lock_irq(&dev_priv->uncore.lock);
1279 fw_rendercount = dev_priv->uncore.fw_rendercount;
1280 fw_mediacount = dev_priv->uncore.fw_mediacount;
1281 spin_unlock_irq(&dev_priv->uncore.lock);
1282
1283 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1284 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1285
1286
1287 return 0;
1288}
1289
1290
4d85529d
BW		 1291static int gen6_drpc_info(struct seq_file *m)
1292{
1293
9f25d007 1294 struct drm_info_node *node = m->private;
4d85529d
BW		 1295 struct drm_device *dev = node->minor->dev;
1296 struct drm_i915_private *dev_priv = dev->dev_private;
ecd8faea 1297 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
93b525dc 1298 unsigned forcewake_count;
aee56cff 1299 int count = 0, ret;
4d85529d
BW		 1300
1301 ret = mutex_lock_interruptible(&dev->struct_mutex);
1302 if (ret)
1303 return ret;
c8c8fb33 1304 intel_runtime_pm_get(dev_priv);
4d85529d 1305
907b28c5
CW		 1306 spin_lock_irq(&dev_priv->uncore.lock);
1307 forcewake_count = dev_priv->uncore.forcewake_count;
1308 spin_unlock_irq(&dev_priv->uncore.lock);
93b525dc
DV		 1309
1310 if (forcewake_count) {
267f0c90
DL		 1311 seq_puts(m, "RC information inaccurate because somebody "
1312 "holds a forcewake reference \n");
4d85529d
BW		 1313 } else {
1314 /* NB: we cannot use forcewake, else we read the wrong values */
1315 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1316 udelay(10);
1317 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1318 }
1319
1320 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
ed71f1b4 1321 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
4d85529d
BW		 1322
1323 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1324 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1325 mutex_unlock(&dev->struct_mutex);
44cbd338
BW		 1326 mutex_lock(&dev_priv->rps.hw_lock);
1327 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1328 mutex_unlock(&dev_priv->rps.hw_lock);
4d85529d 1329
c8c8fb33
PZ		 1330 intel_runtime_pm_put(dev_priv);
1331
4d85529d
BW		 1332 seq_printf(m, "Video Turbo Mode: %s\n",
1333 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1334 seq_printf(m, "HW control enabled: %s\n",
1335 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1336 seq_printf(m, "SW control enabled: %s\n",
1337 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1338 GEN6_RP_MEDIA_SW_MODE));
fff24e21 1339 seq_printf(m, "RC1e Enabled: %s\n",
4d85529d
BW		 1340 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1341 seq_printf(m, "RC6 Enabled: %s\n",
1342 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1343 seq_printf(m, "Deep RC6 Enabled: %s\n",
1344 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1345 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1346 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
267f0c90 1347 seq_puts(m, "Current RC state: ");
4d85529d
BW		 1348 switch (gt_core_status & GEN6_RCn_MASK) {
1349 case GEN6_RC0:
1350 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
267f0c90 1351 seq_puts(m, "Core Power Down\n");
4d85529d 1352 else
267f0c90 1353 seq_puts(m, "on\n");
4d85529d
BW		 1354 break;
1355 case GEN6_RC3:
267f0c90 1356 seq_puts(m, "RC3\n");
4d85529d
BW		 1357 break;
1358 case GEN6_RC6:
267f0c90 1359 seq_puts(m, "RC6\n");
4d85529d
BW		 1360 break;
1361 case GEN6_RC7:
267f0c90 1362 seq_puts(m, "RC7\n");
4d85529d
BW		 1363 break;
1364 default:
267f0c90 1365 seq_puts(m, "Unknown\n");
4d85529d
BW		 1366 break;
1367 }
1368
1369 seq_printf(m, "Core Power Down: %s\n",
1370 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
cce66a28
BW		 1371
1372 /* Not exactly sure what this is */
1373 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1374 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1375 seq_printf(m, "RC6 residency since boot: %u\n",
1376 I915_READ(GEN6_GT_GFX_RC6));
1377 seq_printf(m, "RC6+ residency since boot: %u\n",
1378 I915_READ(GEN6_GT_GFX_RC6p));
1379 seq_printf(m, "RC6++ residency since boot: %u\n",
1380 I915_READ(GEN6_GT_GFX_RC6pp));
1381
ecd8faea
BW		 1382 seq_printf(m, "RC6 voltage: %dmV\n",
1383 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1384 seq_printf(m, "RC6+ voltage: %dmV\n",
1385 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1386 seq_printf(m, "RC6++ voltage: %dmV\n",
1387 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
4d85529d
BW		 1388 return 0;
1389}
1390
1391static int i915_drpc_info(struct seq_file *m, void *unused)
1392{
9f25d007 1393 struct drm_info_node *node = m->private;
4d85529d
BW		 1394 struct drm_device *dev = node->minor->dev;
1395
669ab5aa
D		 1396 if (IS_VALLEYVIEW(dev))
1397 return vlv_drpc_info(m);
ac66cf4b 1398 else if (INTEL_INFO(dev)->gen >= 6)
4d85529d
BW		 1399 return gen6_drpc_info(m);
1400 else
1401 return ironlake_drpc_info(m);
1402}
1403
b5e50c3f
JB		 1404static int i915_fbc_status(struct seq_file *m, void *unused)
1405{
9f25d007 1406 struct drm_info_node *node = m->private;
b5e50c3f 1407 struct drm_device *dev = node->minor->dev;
e277a1f8 1408 struct drm_i915_private *dev_priv = dev->dev_private;
b5e50c3f 1409
3a77c4c4 1410 if (!HAS_FBC(dev)) {
267f0c90 1411 seq_puts(m, "FBC unsupported on this chipset\n");
b5e50c3f
JB		 1412 return 0;
1413 }
1414
36623ef8
PZ		 1415 intel_runtime_pm_get(dev_priv);
1416
ee5382ae 1417 if (intel_fbc_enabled(dev)) {
267f0c90 1418 seq_puts(m, "FBC enabled\n");
b5e50c3f 1419 } else {
267f0c90 1420 seq_puts(m, "FBC disabled: ");
5c3fe8b0 1421 switch (dev_priv->fbc.no_fbc_reason) {
29ebf90f
CW		 1422 case FBC_OK:
1423 seq_puts(m, "FBC actived, but currently disabled in hardware");
1424 break;
1425 case FBC_UNSUPPORTED:
1426 seq_puts(m, "unsupported by this chipset");
1427 break;
bed4a673 1428 case FBC_NO_OUTPUT:
267f0c90 1429 seq_puts(m, "no outputs");
bed4a673 1430 break;
b5e50c3f 1431 case FBC_STOLEN_TOO_SMALL:
267f0c90 1432 seq_puts(m, "not enough stolen memory");
b5e50c3f
JB		 1433 break;
1434 case FBC_UNSUPPORTED_MODE:
267f0c90 1435 seq_puts(m, "mode not supported");
b5e50c3f
JB		 1436 break;
1437 case FBC_MODE_TOO_LARGE:
267f0c90 1438 seq_puts(m, "mode too large");
b5e50c3f
JB		 1439 break;
1440 case FBC_BAD_PLANE:
267f0c90 1441 seq_puts(m, "FBC unsupported on plane");
b5e50c3f
JB		 1442 break;
1443 case FBC_NOT_TILED:
267f0c90 1444 seq_puts(m, "scanout buffer not tiled");
b5e50c3f 1445 break;
9c928d16 1446 case FBC_MULTIPLE_PIPES:
267f0c90 1447 seq_puts(m, "multiple pipes are enabled");
9c928d16 1448 break;
c1a9f047 1449 case FBC_MODULE_PARAM:
267f0c90 1450 seq_puts(m, "disabled per module param (default off)");
c1a9f047 1451 break;
8a5729a3 1452 case FBC_CHIP_DEFAULT:
267f0c90 1453 seq_puts(m, "disabled per chip default");
8a5729a3 1454 break;
b5e50c3f 1455 default:
267f0c90 1456 seq_puts(m, "unknown reason");
b5e50c3f 1457 }
267f0c90 1458 seq_putc(m, '\n');
b5e50c3f 1459 }
36623ef8
PZ		 1460
1461 intel_runtime_pm_put(dev_priv);
1462
b5e50c3f
JB		 1463 return 0;
1464}
1465
da46f936
RV		 1466static int i915_fbc_fc_get(void *data, u64 *val)
1467{
1468 struct drm_device *dev = data;
1469 struct drm_i915_private *dev_priv = dev->dev_private;
1470
1471 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1472 return -ENODEV;
1473
1474 drm_modeset_lock_all(dev);
1475 *val = dev_priv->fbc.false_color;
1476 drm_modeset_unlock_all(dev);
1477
1478 return 0;
1479}
1480
1481static int i915_fbc_fc_set(void *data, u64 val)
1482{
1483 struct drm_device *dev = data;
1484 struct drm_i915_private *dev_priv = dev->dev_private;
1485 u32 reg;
1486
1487 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1488 return -ENODEV;
1489
1490 drm_modeset_lock_all(dev);
1491
1492 reg = I915_READ(ILK_DPFC_CONTROL);
1493 dev_priv->fbc.false_color = val;
1494
1495 I915_WRITE(ILK_DPFC_CONTROL, val ?
1496 (reg | FBC_CTL_FALSE_COLOR) :
1497 (reg & ~FBC_CTL_FALSE_COLOR));
1498
1499 drm_modeset_unlock_all(dev);
1500 return 0;
1501}
1502
1503DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1504 i915_fbc_fc_get, i915_fbc_fc_set,
1505 "%llu\n");
1506
92d44621
PZ		 1507static int i915_ips_status(struct seq_file *m, void *unused)
1508{
9f25d007 1509 struct drm_info_node *node = m->private;
92d44621
PZ		 1510 struct drm_device *dev = node->minor->dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512
f5adf94e 1513 if (!HAS_IPS(dev)) {
92d44621
PZ		 1514 seq_puts(m, "not supported\n");
1515 return 0;
1516 }
1517
36623ef8
PZ		 1518 intel_runtime_pm_get(dev_priv);
1519
0eaa53f0
RV		 1520 seq_printf(m, "Enabled by kernel parameter: %s\n",
1521 yesno(i915.enable_ips));
1522
1523 if (INTEL_INFO(dev)->gen >= 8) {
1524 seq_puts(m, "Currently: unknown\n");
1525 } else {
1526 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1527 seq_puts(m, "Currently: enabled\n");
1528 else
1529 seq_puts(m, "Currently: disabled\n");
1530 }
92d44621 1531
36623ef8
PZ		 1532 intel_runtime_pm_put(dev_priv);
1533
92d44621
PZ		 1534 return 0;
1535}
1536
4a9bef37
JB		 1537static int i915_sr_status(struct seq_file *m, void *unused)
1538{
9f25d007 1539 struct drm_info_node *node = m->private;
4a9bef37 1540 struct drm_device *dev = node->minor->dev;
e277a1f8 1541 struct drm_i915_private *dev_priv = dev->dev_private;
4a9bef37
JB		 1542 bool sr_enabled = false;
1543
36623ef8
PZ		 1544 intel_runtime_pm_get(dev_priv);
1545
1398261a 1546 if (HAS_PCH_SPLIT(dev))
5ba2aaaa 1547 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
a6c45cf0 1548 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
4a9bef37
JB		 1549 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1550 else if (IS_I915GM(dev))
1551 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1552 else if (IS_PINEVIEW(dev))
1553 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1554
36623ef8
PZ		 1555 intel_runtime_pm_put(dev_priv);
1556
5ba2aaaa
CW		 1557 seq_printf(m, "self-refresh: %s\n",
1558 sr_enabled ? "enabled" : "disabled");
4a9bef37
JB		 1559
1560 return 0;
1561}
1562
7648fa99
JB		 1563static int i915_emon_status(struct seq_file *m, void *unused)
1564{
9f25d007 1565 struct drm_info_node *node = m->private;
7648fa99 1566 struct drm_device *dev = node->minor->dev;
e277a1f8 1567 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 1568 unsigned long temp, chipset, gfx;
de227ef0
CW		 1569 int ret;
1570
582be6b4
CW		 1571 if (!IS_GEN5(dev))
1572 return -ENODEV;
1573
de227ef0
CW		 1574 ret = mutex_lock_interruptible(&dev->struct_mutex);
1575 if (ret)
1576 return ret;
7648fa99
JB		 1577
1578 temp = i915_mch_val(dev_priv);
1579 chipset = i915_chipset_val(dev_priv);
1580 gfx = i915_gfx_val(dev_priv);
de227ef0 1581 mutex_unlock(&dev->struct_mutex);
7648fa99
JB		 1582
1583 seq_printf(m, "GMCH temp: %ld\n", temp);
1584 seq_printf(m, "Chipset power: %ld\n", chipset);
1585 seq_printf(m, "GFX power: %ld\n", gfx);
1586 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1587
1588 return 0;
1589}
1590
23b2f8bb
JB		 1591static int i915_ring_freq_table(struct seq_file *m, void *unused)
1592{
9f25d007 1593 struct drm_info_node *node = m->private;
23b2f8bb 1594 struct drm_device *dev = node->minor->dev;
e277a1f8 1595 struct drm_i915_private *dev_priv = dev->dev_private;
5bfa0199 1596 int ret = 0;
23b2f8bb
JB		 1597 int gpu_freq, ia_freq;
1598
1c70c0ce 1599 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
267f0c90 1600 seq_puts(m, "unsupported on this chipset\n");
23b2f8bb
JB		 1601 return 0;
1602 }
1603
5bfa0199
PZ		 1604 intel_runtime_pm_get(dev_priv);
1605
5c9669ce
TR		 1606 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1607
4fc688ce 1608 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
23b2f8bb 1609 if (ret)
5bfa0199 1610 goto out;
23b2f8bb 1611
267f0c90 1612 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
23b2f8bb 1613
b39fb297
BW		 1614 for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1615 gpu_freq <= dev_priv->rps.max_freq_softlimit;
23b2f8bb 1616 gpu_freq++) {
42c0526c
BW		 1617 ia_freq = gpu_freq;
1618 sandybridge_pcode_read(dev_priv,
1619 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1620 &ia_freq);
3ebecd07
CW		 1621 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1622 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1623 ((ia_freq >> 0) & 0xff) * 100,
1624 ((ia_freq >> 8) & 0xff) * 100);
23b2f8bb
JB		 1625 }
1626
4fc688ce 1627 mutex_unlock(&dev_priv->rps.hw_lock);
23b2f8bb 1628
5bfa0199
PZ		 1629out:
1630 intel_runtime_pm_put(dev_priv);
1631 return ret;
23b2f8bb
JB		 1632}
1633
44834a67
CW		 1634static int i915_opregion(struct seq_file *m, void *unused)
1635{
9f25d007 1636 struct drm_info_node *node = m->private;
44834a67 1637 struct drm_device *dev = node->minor->dev;
e277a1f8 1638 struct drm_i915_private *dev_priv = dev->dev_private;
44834a67 1639 struct intel_opregion *opregion = &dev_priv->opregion;
0d38f009 1640 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
44834a67
CW		 1641 int ret;
1642
0d38f009
DV		 1643 if (data == NULL)
1644 return -ENOMEM;
1645
44834a67
CW		 1646 ret = mutex_lock_interruptible(&dev->struct_mutex);
1647 if (ret)
0d38f009 1648 goto out;
44834a67 1649
0d38f009
DV		 1650 if (opregion->header) {
1651 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1652 seq_write(m, data, OPREGION_SIZE);
1653 }
44834a67
CW		 1654
1655 mutex_unlock(&dev->struct_mutex);
1656
0d38f009
DV		 1657out:
1658 kfree(data);
44834a67
CW		 1659 return 0;
1660}
1661
37811fcc
CW		 1662static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1663{
9f25d007 1664 struct drm_info_node *node = m->private;
37811fcc 1665 struct drm_device *dev = node->minor->dev;
4520f53a 1666 struct intel_fbdev *ifbdev = NULL;
37811fcc 1667 struct intel_framebuffer *fb;
37811fcc 1668
4520f53a
DV		 1669#ifdef CONFIG_DRM_I915_FBDEV
1670 struct drm_i915_private *dev_priv = dev->dev_private;
37811fcc
CW		 1671
1672 ifbdev = dev_priv->fbdev;
1673 fb = to_intel_framebuffer(ifbdev->helper.fb);
1674
623f9783 1675 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1676 fb->base.width,
1677 fb->base.height,
1678 fb->base.depth,
623f9783
DV		 1679 fb->base.bits_per_pixel,
1680 atomic_read(&fb->base.refcount.refcount));
05394f39 1681 describe_obj(m, fb->obj);
267f0c90 1682 seq_putc(m, '\n');
4520f53a 1683#endif
37811fcc 1684
4b096ac1 1685 mutex_lock(&dev->mode_config.fb_lock);
37811fcc 1686 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
131a56dc 1687 if (ifbdev && &fb->base == ifbdev->helper.fb)
37811fcc
CW		 1688 continue;
1689
623f9783 1690 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
37811fcc
CW		 1691 fb->base.width,
1692 fb->base.height,
1693 fb->base.depth,
623f9783
DV		 1694 fb->base.bits_per_pixel,
1695 atomic_read(&fb->base.refcount.refcount));
05394f39 1696 describe_obj(m, fb->obj);
267f0c90 1697 seq_putc(m, '\n');
37811fcc 1698 }
4b096ac1 1699 mutex_unlock(&dev->mode_config.fb_lock);
37811fcc
CW		 1700
1701 return 0;
1702}
1703
c9fe99bd
OM		 1704static void describe_ctx_ringbuf(struct seq_file *m,
1705 struct intel_ringbuffer *ringbuf)
1706{
1707 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1708 ringbuf->space, ringbuf->head, ringbuf->tail,
1709 ringbuf->last_retired_head);
1710}
1711
e76d3630
BW		 1712static int i915_context_status(struct seq_file *m, void *unused)
1713{
9f25d007 1714 struct drm_info_node *node = m->private;
e76d3630 1715 struct drm_device *dev = node->minor->dev;
e277a1f8 1716 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1717 struct intel_engine_cs *ring;
273497e5 1718 struct intel_context *ctx;
a168c293 1719 int ret, i;
e76d3630 1720
f3d28878 1721 ret = mutex_lock_interruptible(&dev->struct_mutex);
e76d3630
BW		 1722 if (ret)
1723 return ret;
1724
3e373948 1725 if (dev_priv->ips.pwrctx) {
267f0c90 1726 seq_puts(m, "power context ");
3e373948 1727 describe_obj(m, dev_priv->ips.pwrctx);
267f0c90 1728 seq_putc(m, '\n');
dc501fbc 1729 }
e76d3630 1730
3e373948 1731 if (dev_priv->ips.renderctx) {
267f0c90 1732 seq_puts(m, "render context ");
3e373948 1733 describe_obj(m, dev_priv->ips.renderctx);
267f0c90 1734 seq_putc(m, '\n');
dc501fbc 1735 }
e76d3630 1736
a33afea5 1737 list_for_each_entry(ctx, &dev_priv->context_list, link) {
c9fe99bd
OM		 1738 if (!i915.enable_execlists &&
1739 ctx->legacy_hw_ctx.rcs_state == NULL)
b77f6997
CW		 1740 continue;
1741
a33afea5 1742 seq_puts(m, "HW context ");
3ccfd19d 1743 describe_ctx(m, ctx);
c9fe99bd 1744 for_each_ring(ring, dev_priv, i) {
a33afea5 1745 if (ring->default_context == ctx)
c9fe99bd
OM		 1746 seq_printf(m, "(default context %s) ",
1747 ring->name);
1748 }
1749
1750 if (i915.enable_execlists) {
1751 seq_putc(m, '\n');
1752 for_each_ring(ring, dev_priv, i) {
1753 struct drm_i915_gem_object *ctx_obj =
1754 ctx->engine[i].state;
1755 struct intel_ringbuffer *ringbuf =
1756 ctx->engine[i].ringbuf;
1757
1758 seq_printf(m, "%s: ", ring->name);
1759 if (ctx_obj)
1760 describe_obj(m, ctx_obj);
1761 if (ringbuf)
1762 describe_ctx_ringbuf(m, ringbuf);
1763 seq_putc(m, '\n');
1764 }
1765 } else {
1766 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1767 }
a33afea5 1768
a33afea5 1769 seq_putc(m, '\n');
a168c293
BW		 1770 }
1771
f3d28878 1772 mutex_unlock(&dev->struct_mutex);
e76d3630
BW		 1773
1774 return 0;
1775}
1776
064ca1d2
TD		 1777static void i915_dump_lrc_obj(struct seq_file *m,
1778 struct intel_engine_cs *ring,
1779 struct drm_i915_gem_object *ctx_obj)
1780{
1781 struct page *page;
1782 uint32_t *reg_state;
1783 int j;
1784 unsigned long ggtt_offset = 0;
1785
1786 if (ctx_obj == NULL) {
1787 seq_printf(m, "Context on %s with no gem object\n",
1788 ring->name);
1789 return;
1790 }
1791
1792 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1793 intel_execlists_ctx_id(ctx_obj));
1794
1795 if (!i915_gem_obj_ggtt_bound(ctx_obj))
1796 seq_puts(m, "\tNot bound in GGTT\n");
1797 else
1798 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1799
1800 if (i915_gem_object_get_pages(ctx_obj)) {
1801 seq_puts(m, "\tFailed to get pages for context object\n");
1802 return;
1803 }
1804
1805 page = i915_gem_object_get_page(ctx_obj, 1);
1806 if (!WARN_ON(page == NULL)) {
1807 reg_state = kmap_atomic(page);
1808
1809 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1810 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1811 ggtt_offset + 4096 + (j * 4),
1812 reg_state[j], reg_state[j + 1],
1813 reg_state[j + 2], reg_state[j + 3]);
1814 }
1815 kunmap_atomic(reg_state);
1816 }
1817
1818 seq_putc(m, '\n');
1819}
1820
c0ab1ae9
BW		 1821static int i915_dump_lrc(struct seq_file *m, void *unused)
1822{
1823 struct drm_info_node *node = (struct drm_info_node *) m->private;
1824 struct drm_device *dev = node->minor->dev;
1825 struct drm_i915_private *dev_priv = dev->dev_private;
1826 struct intel_engine_cs *ring;
1827 struct intel_context *ctx;
1828 int ret, i;
1829
1830 if (!i915.enable_execlists) {
1831 seq_printf(m, "Logical Ring Contexts are disabled\n");
1832 return 0;
1833 }
1834
1835 ret = mutex_lock_interruptible(&dev->struct_mutex);
1836 if (ret)
1837 return ret;
1838
1839 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1840 for_each_ring(ring, dev_priv, i) {
064ca1d2
TD		 1841 if (ring->default_context != ctx)
1842 i915_dump_lrc_obj(m, ring,
1843 ctx->engine[i].state);
c0ab1ae9
BW		 1844 }
1845 }
1846
1847 mutex_unlock(&dev->struct_mutex);
1848
1849 return 0;
1850}
1851
4ba70e44
OM		 1852static int i915_execlists(struct seq_file *m, void *data)
1853{
1854 struct drm_info_node *node = (struct drm_info_node *)m->private;
1855 struct drm_device *dev = node->minor->dev;
1856 struct drm_i915_private *dev_priv = dev->dev_private;
1857 struct intel_engine_cs *ring;
1858 u32 status_pointer;
1859 u8 read_pointer;
1860 u8 write_pointer;
1861 u32 status;
1862 u32 ctx_id;
1863 struct list_head *cursor;
1864 int ring_id, i;
1865 int ret;
1866
1867 if (!i915.enable_execlists) {
1868 seq_puts(m, "Logical Ring Contexts are disabled\n");
1869 return 0;
1870 }
1871
1872 ret = mutex_lock_interruptible(&dev->struct_mutex);
1873 if (ret)
1874 return ret;
1875
fc0412ec
MT		 1876 intel_runtime_pm_get(dev_priv);
1877
4ba70e44
OM		 1878 for_each_ring(ring, dev_priv, ring_id) {
1879 struct intel_ctx_submit_request *head_req = NULL;
1880 int count = 0;
1881 unsigned long flags;
1882
1883 seq_printf(m, "%s\n", ring->name);
1884
1885 status = I915_READ(RING_EXECLIST_STATUS(ring));
1886 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
1887 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
1888 status, ctx_id);
1889
1890 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
1891 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
1892
1893 read_pointer = ring->next_context_status_buffer;
1894 write_pointer = status_pointer & 0x07;
1895 if (read_pointer > write_pointer)
1896 write_pointer += 6;
1897 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
1898 read_pointer, write_pointer);
1899
1900 for (i = 0; i < 6; i++) {
1901 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
1902 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
1903
1904 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
1905 i, status, ctx_id);
1906 }
1907
1908 spin_lock_irqsave(&ring->execlist_lock, flags);
1909 list_for_each(cursor, &ring->execlist_queue)
1910 count++;
1911 head_req = list_first_entry_or_null(&ring->execlist_queue,
1912 struct intel_ctx_submit_request, execlist_link);
1913 spin_unlock_irqrestore(&ring->execlist_lock, flags);
1914
1915 seq_printf(m, "\t%d requests in queue\n", count);
1916 if (head_req) {
1917 struct drm_i915_gem_object *ctx_obj;
1918
1919 ctx_obj = head_req->ctx->engine[ring_id].state;
1920 seq_printf(m, "\tHead request id: %u\n",
1921 intel_execlists_ctx_id(ctx_obj));
1922 seq_printf(m, "\tHead request tail: %u\n",
1923 head_req->tail);
1924 }
1925
1926 seq_putc(m, '\n');
1927 }
1928
fc0412ec 1929 intel_runtime_pm_put(dev_priv);
4ba70e44
OM		 1930 mutex_unlock(&dev->struct_mutex);
1931
1932 return 0;
1933}
1934
6d794d42
BW		 1935static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1936{
9f25d007 1937 struct drm_info_node *node = m->private;
6d794d42
BW		 1938 struct drm_device *dev = node->minor->dev;
1939 struct drm_i915_private *dev_priv = dev->dev_private;
43709ba0 1940 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
6d794d42 1941
907b28c5 1942 spin_lock_irq(&dev_priv->uncore.lock);
43709ba0
D		 1943 if (IS_VALLEYVIEW(dev)) {
1944 fw_rendercount = dev_priv->uncore.fw_rendercount;
1945 fw_mediacount = dev_priv->uncore.fw_mediacount;
1946 } else
1947 forcewake_count = dev_priv->uncore.forcewake_count;
907b28c5 1948 spin_unlock_irq(&dev_priv->uncore.lock);
6d794d42 1949
43709ba0
D		 1950 if (IS_VALLEYVIEW(dev)) {
1951 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1952 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1953 } else
1954 seq_printf(m, "forcewake count = %u\n", forcewake_count);
6d794d42
BW		 1955
1956 return 0;
1957}
1958
ea16a3cd
DV		 1959static const char *swizzle_string(unsigned swizzle)
1960{
aee56cff 1961 switch (swizzle) {
ea16a3cd
DV		 1962 case I915_BIT_6_SWIZZLE_NONE:
1963 return "none";
1964 case I915_BIT_6_SWIZZLE_9:
1965 return "bit9";
1966 case I915_BIT_6_SWIZZLE_9_10:
1967 return "bit9/bit10";
1968 case I915_BIT_6_SWIZZLE_9_11:
1969 return "bit9/bit11";
1970 case I915_BIT_6_SWIZZLE_9_10_11:
1971 return "bit9/bit10/bit11";
1972 case I915_BIT_6_SWIZZLE_9_17:
1973 return "bit9/bit17";
1974 case I915_BIT_6_SWIZZLE_9_10_17:
1975 return "bit9/bit10/bit17";
1976 case I915_BIT_6_SWIZZLE_UNKNOWN:
8a168ca7 1977 return "unknown";
ea16a3cd
DV		 1978 }
1979
1980 return "bug";
1981}
1982
1983static int i915_swizzle_info(struct seq_file *m, void *data)
1984{
9f25d007 1985 struct drm_info_node *node = m->private;
ea16a3cd
DV		 1986 struct drm_device *dev = node->minor->dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
22bcfc6a
DV		 1988 int ret;
1989
1990 ret = mutex_lock_interruptible(&dev->struct_mutex);
1991 if (ret)
1992 return ret;
c8c8fb33 1993 intel_runtime_pm_get(dev_priv);
ea16a3cd 1994
ea16a3cd
DV		 1995 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1996 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1997 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1998 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1999
2000 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2001 seq_printf(m, "DDC = 0x%08x\n",
2002 I915_READ(DCC));
656bfa3a
DV		 2003 seq_printf(m, "DDC2 = 0x%08x\n",
2004 I915_READ(DCC2));
ea16a3cd
DV		 2005 seq_printf(m, "C0DRB3 = 0x%04x\n",
2006 I915_READ16(C0DRB3));
2007 seq_printf(m, "C1DRB3 = 0x%04x\n",
2008 I915_READ16(C1DRB3));
9d3203e1 2009 } else if (INTEL_INFO(dev)->gen >= 6) {
3fa7d235
DV		 2010 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2011 I915_READ(MAD_DIMM_C0));
2012 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2013 I915_READ(MAD_DIMM_C1));
2014 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2015 I915_READ(MAD_DIMM_C2));
2016 seq_printf(m, "TILECTL = 0x%08x\n",
2017 I915_READ(TILECTL));
5907f5fb 2018 if (INTEL_INFO(dev)->gen >= 8)
9d3203e1
BW		 2019 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2020 I915_READ(GAMTARBMODE));
2021 else
2022 seq_printf(m, "ARB_MODE = 0x%08x\n",
2023 I915_READ(ARB_MODE));
3fa7d235
DV		 2024 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2025 I915_READ(DISP_ARB_CTL));
ea16a3cd 2026 }
656bfa3a
DV		 2027
2028 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2029 seq_puts(m, "L-shaped memory detected\n");
2030
c8c8fb33 2031 intel_runtime_pm_put(dev_priv);
ea16a3cd
DV		 2032 mutex_unlock(&dev->struct_mutex);
2033
2034 return 0;
2035}
2036
1c60fef5
BW		 2037static int per_file_ctx(int id, void *ptr, void *data)
2038{
273497e5 2039 struct intel_context *ctx = ptr;
1c60fef5 2040 struct seq_file *m = data;
ae6c4806
DV		 2041 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2042
2043 if (!ppgtt) {
2044 seq_printf(m, " no ppgtt for context %d\n",
2045 ctx->user_handle);
2046 return 0;
2047 }
1c60fef5 2048
f83d6518
OM		 2049 if (i915_gem_context_is_default(ctx))
2050 seq_puts(m, " default context:\n");
2051 else
821d66dd 2052 seq_printf(m, " context %d:\n", ctx->user_handle);
1c60fef5
BW		 2053 ppgtt->debug_dump(ppgtt, m);
2054
2055 return 0;
2056}
2057
77df6772 2058static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
3cf17fc5 2059{
3cf17fc5 2060 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2061 struct intel_engine_cs *ring;
77df6772
BW		 2062 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2063 int unused, i;
3cf17fc5 2064
77df6772
BW		 2065 if (!ppgtt)
2066 return;
2067
2068 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
5abbcca3 2069 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
77df6772
BW		 2070 for_each_ring(ring, dev_priv, unused) {
2071 seq_printf(m, "%s\n", ring->name);
2072 for (i = 0; i < 4; i++) {
2073 u32 offset = 0x270 + i * 8;
2074 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2075 pdp <<= 32;
2076 pdp |= I915_READ(ring->mmio_base + offset);
a2a5b15c 2077 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
77df6772
BW		 2078 }
2079 }
2080}
2081
2082static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2083{
2084 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 2085 struct intel_engine_cs *ring;
1c60fef5 2086 struct drm_file *file;
77df6772 2087 int i;
3cf17fc5 2088
3cf17fc5
DV		 2089 if (INTEL_INFO(dev)->gen == 6)
2090 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2091
a2c7f6fd 2092 for_each_ring(ring, dev_priv, i) {
3cf17fc5
DV		 2093 seq_printf(m, "%s\n", ring->name);
2094 if (INTEL_INFO(dev)->gen == 7)
2095 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2096 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2097 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2098 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2099 }
2100 if (dev_priv->mm.aliasing_ppgtt) {
2101 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2102
267f0c90 2103 seq_puts(m, "aliasing PPGTT:\n");
3cf17fc5 2104 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1c60fef5 2105
87d60b63 2106 ppgtt->debug_dump(ppgtt, m);
ae6c4806 2107 }
1c60fef5
BW		 2108
2109 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2110 struct drm_i915_file_private *file_priv = file->driver_priv;
1c60fef5 2111
1c60fef5
BW		 2112 seq_printf(m, "proc: %s\n",
2113 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1c60fef5 2114 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
3cf17fc5
DV		 2115 }
2116 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
77df6772
BW		 2117}
2118
2119static int i915_ppgtt_info(struct seq_file *m, void *data)
2120{
9f25d007 2121 struct drm_info_node *node = m->private;
77df6772 2122 struct drm_device *dev = node->minor->dev;
c8c8fb33 2123 struct drm_i915_private *dev_priv = dev->dev_private;
77df6772
BW		 2124
2125 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2126 if (ret)
2127 return ret;
c8c8fb33 2128 intel_runtime_pm_get(dev_priv);
77df6772
BW		 2129
2130 if (INTEL_INFO(dev)->gen >= 8)
2131 gen8_ppgtt_info(m, dev);
2132 else if (INTEL_INFO(dev)->gen >= 6)
2133 gen6_ppgtt_info(m, dev);
2134
c8c8fb33 2135 intel_runtime_pm_put(dev_priv);
3cf17fc5
DV		 2136 mutex_unlock(&dev->struct_mutex);
2137
2138 return 0;
2139}
2140
63573eb7
BW		 2141static int i915_llc(struct seq_file *m, void *data)
2142{
9f25d007 2143 struct drm_info_node *node = m->private;
63573eb7
BW		 2144 struct drm_device *dev = node->minor->dev;
2145 struct drm_i915_private *dev_priv = dev->dev_private;
2146
2147 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2148 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2149 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2150
2151 return 0;
2152}
2153
e91fd8c6
RV		 2154static int i915_edp_psr_status(struct seq_file *m, void *data)
2155{
2156 struct drm_info_node *node = m->private;
2157 struct drm_device *dev = node->minor->dev;
2158 struct drm_i915_private *dev_priv = dev->dev_private;
a031d709 2159 u32 psrperf = 0;
a6cbdb8e
RV		 2160 u32 stat[3];
2161 enum pipe pipe;
a031d709 2162 bool enabled = false;
e91fd8c6 2163
c8c8fb33
PZ		 2164 intel_runtime_pm_get(dev_priv);
2165
fa128fa6 2166 mutex_lock(&dev_priv->psr.lock);
a031d709
RV		 2167 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2168 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2807cf69 2169 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
5755c78f 2170 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
fa128fa6
DV		 2171 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2172 dev_priv->psr.busy_frontbuffer_bits);
2173 seq_printf(m, "Re-enable work scheduled: %s\n",
2174 yesno(work_busy(&dev_priv->psr.work.work)));
e91fd8c6 2175
a6cbdb8e
RV		 2176 if (HAS_PSR(dev)) {
2177 if (HAS_DDI(dev))
2178 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2179 else {
2180 for_each_pipe(dev_priv, pipe) {
2181 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2182 VLV_EDP_PSR_CURR_STATE_MASK;
2183 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2184 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2185 enabled = true;
2186 }
2187 }
2188 }
2189 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2190
2191 if (!HAS_DDI(dev))
2192 for_each_pipe(dev_priv, pipe) {
2193 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2194 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2195 seq_printf(m, " pipe %c", pipe_name(pipe));
2196 }
2197 seq_puts(m, "\n");
e91fd8c6 2198
a6cbdb8e
RV		 2199 /* CHV PSR has no kind of performance counter */
2200 if (HAS_PSR(dev) && HAS_DDI(dev)) {
a031d709
RV		 2201 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2202 EDP_PSR_PERF_CNT_MASK;
a6cbdb8e
RV		 2203
2204 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2205 }
fa128fa6 2206 mutex_unlock(&dev_priv->psr.lock);
e91fd8c6 2207
c8c8fb33 2208 intel_runtime_pm_put(dev_priv);
e91fd8c6
RV		 2209 return 0;
2210}
2211
d2e216d0
RV		 2212static int i915_sink_crc(struct seq_file *m, void *data)
2213{
2214 struct drm_info_node *node = m->private;
2215 struct drm_device *dev = node->minor->dev;
2216 struct intel_encoder *encoder;
2217 struct intel_connector *connector;
2218 struct intel_dp *intel_dp = NULL;
2219 int ret;
2220 u8 crc[6];
2221
2222 drm_modeset_lock_all(dev);
2223 list_for_each_entry(connector, &dev->mode_config.connector_list,
2224 base.head) {
2225
2226 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2227 continue;
2228
b6ae3c7c
PZ		 2229 if (!connector->base.encoder)
2230 continue;
2231
d2e216d0
RV		 2232 encoder = to_intel_encoder(connector->base.encoder);
2233 if (encoder->type != INTEL_OUTPUT_EDP)
2234 continue;
2235
2236 intel_dp = enc_to_intel_dp(&encoder->base);
2237
2238 ret = intel_dp_sink_crc(intel_dp, crc);
2239 if (ret)
2240 goto out;
2241
2242 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2243 crc[0], crc[1], crc[2],
2244 crc[3], crc[4], crc[5]);
2245 goto out;
2246 }
2247 ret = -ENODEV;
2248out:
2249 drm_modeset_unlock_all(dev);
2250 return ret;
2251}
2252
ec013e7f
JB		 2253static int i915_energy_uJ(struct seq_file *m, void *data)
2254{
2255 struct drm_info_node *node = m->private;
2256 struct drm_device *dev = node->minor->dev;
2257 struct drm_i915_private *dev_priv = dev->dev_private;
2258 u64 power;
2259 u32 units;
2260
2261 if (INTEL_INFO(dev)->gen < 6)
2262 return -ENODEV;
2263
36623ef8
PZ		 2264 intel_runtime_pm_get(dev_priv);
2265
ec013e7f
JB		 2266 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2267 power = (power & 0x1f00) >> 8;
2268 units = 1000000 / (1 << power); /* convert to uJ */
2269 power = I915_READ(MCH_SECP_NRG_STTS);
2270 power *= units;
2271
36623ef8
PZ		 2272 intel_runtime_pm_put(dev_priv);
2273
ec013e7f 2274 seq_printf(m, "%llu", (long long unsigned)power);
371db66a
PZ		 2275
2276 return 0;
2277}
2278
2279static int i915_pc8_status(struct seq_file *m, void *unused)
2280{
9f25d007 2281 struct drm_info_node *node = m->private;
371db66a
PZ		 2282 struct drm_device *dev = node->minor->dev;
2283 struct drm_i915_private *dev_priv = dev->dev_private;
2284
85b8d5c2 2285 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
371db66a
PZ		 2286 seq_puts(m, "not supported\n");
2287 return 0;
2288 }
2289
86c4ec0d 2290 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
371db66a 2291 seq_printf(m, "IRQs disabled: %s\n",
9df7575f 2292 yesno(!intel_irqs_enabled(dev_priv)));
371db66a 2293
ec013e7f
JB		 2294 return 0;
2295}
2296
1da51581
ID		 2297static const char *power_domain_str(enum intel_display_power_domain domain)
2298{
2299 switch (domain) {
2300 case POWER_DOMAIN_PIPE_A:
2301 return "PIPE_A";
2302 case POWER_DOMAIN_PIPE_B:
2303 return "PIPE_B";
2304 case POWER_DOMAIN_PIPE_C:
2305 return "PIPE_C";
2306 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2307 return "PIPE_A_PANEL_FITTER";
2308 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2309 return "PIPE_B_PANEL_FITTER";
2310 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2311 return "PIPE_C_PANEL_FITTER";
2312 case POWER_DOMAIN_TRANSCODER_A:
2313 return "TRANSCODER_A";
2314 case POWER_DOMAIN_TRANSCODER_B:
2315 return "TRANSCODER_B";
2316 case POWER_DOMAIN_TRANSCODER_C:
2317 return "TRANSCODER_C";
2318 case POWER_DOMAIN_TRANSCODER_EDP:
2319 return "TRANSCODER_EDP";
319be8ae
ID		 2320 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2321 return "PORT_DDI_A_2_LANES";
2322 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2323 return "PORT_DDI_A_4_LANES";
2324 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2325 return "PORT_DDI_B_2_LANES";
2326 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2327 return "PORT_DDI_B_4_LANES";
2328 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2329 return "PORT_DDI_C_2_LANES";
2330 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2331 return "PORT_DDI_C_4_LANES";
2332 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2333 return "PORT_DDI_D_2_LANES";
2334 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2335 return "PORT_DDI_D_4_LANES";
2336 case POWER_DOMAIN_PORT_DSI:
2337 return "PORT_DSI";
2338 case POWER_DOMAIN_PORT_CRT:
2339 return "PORT_CRT";
2340 case POWER_DOMAIN_PORT_OTHER:
2341 return "PORT_OTHER";
1da51581
ID		 2342 case POWER_DOMAIN_VGA:
2343 return "VGA";
2344 case POWER_DOMAIN_AUDIO:
2345 return "AUDIO";
bd2bb1b9
PZ		 2346 case POWER_DOMAIN_PLLS:
2347 return "PLLS";
1da51581
ID		 2348 case POWER_DOMAIN_INIT:
2349 return "INIT";
2350 default:
5f77eeb0 2351 MISSING_CASE(domain);
1da51581
ID		 2352 return "?";
2353 }
2354}
2355
2356static int i915_power_domain_info(struct seq_file *m, void *unused)
2357{
9f25d007 2358 struct drm_info_node *node = m->private;
1da51581
ID		 2359 struct drm_device *dev = node->minor->dev;
2360 struct drm_i915_private *dev_priv = dev->dev_private;
2361 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2362 int i;
2363
2364 mutex_lock(&power_domains->lock);
2365
2366 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2367 for (i = 0; i < power_domains->power_well_count; i++) {
2368 struct i915_power_well *power_well;
2369 enum intel_display_power_domain power_domain;
2370
2371 power_well = &power_domains->power_wells[i];
2372 seq_printf(m, "%-25s %d\n", power_well->name,
2373 power_well->count);
2374
2375 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2376 power_domain++) {
2377 if (!(BIT(power_domain) & power_well->domains))
2378 continue;
2379
2380 seq_printf(m, " %-23s %d\n",
2381 power_domain_str(power_domain),
2382 power_domains->domain_use_count[power_domain]);
2383 }
2384 }
2385
2386 mutex_unlock(&power_domains->lock);
2387
2388 return 0;
2389}
2390
53f5e3ca
JB		 2391static void intel_seq_print_mode(struct seq_file *m, int tabs,
2392 struct drm_display_mode *mode)
2393{
2394 int i;
2395
2396 for (i = 0; i < tabs; i++)
2397 seq_putc(m, '\t');
2398
2399 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2400 mode->base.id, mode->name,
2401 mode->vrefresh, mode->clock,
2402 mode->hdisplay, mode->hsync_start,
2403 mode->hsync_end, mode->htotal,
2404 mode->vdisplay, mode->vsync_start,
2405 mode->vsync_end, mode->vtotal,
2406 mode->type, mode->flags);
2407}
2408
2409static void intel_encoder_info(struct seq_file *m,
2410 struct intel_crtc *intel_crtc,
2411 struct intel_encoder *intel_encoder)
2412{
9f25d007 2413 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2414 struct drm_device *dev = node->minor->dev;
2415 struct drm_crtc *crtc = &intel_crtc->base;
2416 struct intel_connector *intel_connector;
2417 struct drm_encoder *encoder;
2418
2419 encoder = &intel_encoder->base;
2420 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
8e329a03 2421 encoder->base.id, encoder->name);
53f5e3ca
JB		 2422 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2423 struct drm_connector *connector = &intel_connector->base;
2424 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2425 connector->base.id,
c23cc417 2426 connector->name,
53f5e3ca
JB		 2427 drm_get_connector_status_name(connector->status));
2428 if (connector->status == connector_status_connected) {
2429 struct drm_display_mode *mode = &crtc->mode;
2430 seq_printf(m, ", mode:\n");
2431 intel_seq_print_mode(m, 2, mode);
2432 } else {
2433 seq_putc(m, '\n');
2434 }
2435 }
2436}
2437
2438static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2439{
9f25d007 2440 struct drm_info_node *node = m->private;
53f5e3ca
JB		 2441 struct drm_device *dev = node->minor->dev;
2442 struct drm_crtc *crtc = &intel_crtc->base;
2443 struct intel_encoder *intel_encoder;
2444
5aa8a937
MR		 2445 if (crtc->primary->fb)
2446 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2447 crtc->primary->fb->base.id, crtc->x, crtc->y,
2448 crtc->primary->fb->width, crtc->primary->fb->height);
2449 else
2450 seq_puts(m, "\tprimary plane disabled\n");
53f5e3ca
JB		 2451 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2452 intel_encoder_info(m, intel_crtc, intel_encoder);
2453}
2454
2455static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2456{
2457 struct drm_display_mode *mode = panel->fixed_mode;
2458
2459 seq_printf(m, "\tfixed mode:\n");
2460 intel_seq_print_mode(m, 2, mode);
2461}
2462
2463static void intel_dp_info(struct seq_file *m,
2464 struct intel_connector *intel_connector)
2465{
2466 struct intel_encoder *intel_encoder = intel_connector->encoder;
2467 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2468
2469 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2470 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2471 "no");
2472 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2473 intel_panel_info(m, &intel_connector->panel);
2474}
2475
2476static void intel_hdmi_info(struct seq_file *m,
2477 struct intel_connector *intel_connector)
2478{
2479 struct intel_encoder *intel_encoder = intel_connector->encoder;
2480 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2481
2482 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2483 "no");
2484}
2485
2486static void intel_lvds_info(struct seq_file *m,
2487 struct intel_connector *intel_connector)
2488{
2489 intel_panel_info(m, &intel_connector->panel);
2490}
2491
2492static void intel_connector_info(struct seq_file *m,
2493 struct drm_connector *connector)
2494{
2495 struct intel_connector *intel_connector = to_intel_connector(connector);
2496 struct intel_encoder *intel_encoder = intel_connector->encoder;
f103fc7d 2497 struct drm_display_mode *mode;
53f5e3ca
JB		 2498
2499 seq_printf(m, "connector %d: type %s, status: %s\n",
c23cc417 2500 connector->base.id, connector->name,
53f5e3ca
JB		 2501 drm_get_connector_status_name(connector->status));
2502 if (connector->status == connector_status_connected) {
2503 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2504 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2505 connector->display_info.width_mm,
2506 connector->display_info.height_mm);
2507 seq_printf(m, "\tsubpixel order: %s\n",
2508 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2509 seq_printf(m, "\tCEA rev: %d\n",
2510 connector->display_info.cea_rev);
2511 }
36cd7444
DA		 2512 if (intel_encoder) {
2513 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2514 intel_encoder->type == INTEL_OUTPUT_EDP)
2515 intel_dp_info(m, intel_connector);
2516 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2517 intel_hdmi_info(m, intel_connector);
2518 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2519 intel_lvds_info(m, intel_connector);
2520 }
53f5e3ca 2521
f103fc7d
JB		 2522 seq_printf(m, "\tmodes:\n");
2523 list_for_each_entry(mode, &connector->modes, head)
2524 intel_seq_print_mode(m, 2, mode);
53f5e3ca
JB		 2525}
2526
065f2ec2
CW		 2527static bool cursor_active(struct drm_device *dev, int pipe)
2528{
2529 struct drm_i915_private *dev_priv = dev->dev_private;
2530 u32 state;
2531
2532 if (IS_845G(dev) || IS_I865G(dev))
2533 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
065f2ec2 2534 else
5efb3e28 2535 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
065f2ec2
CW		 2536
2537 return state;
2538}
2539
2540static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2541{
2542 struct drm_i915_private *dev_priv = dev->dev_private;
2543 u32 pos;
2544
5efb3e28 2545 pos = I915_READ(CURPOS(pipe));
065f2ec2
CW		 2546
2547 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2548 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2549 *x = -*x;
2550
2551 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2552 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2553 *y = -*y;
2554
2555 return cursor_active(dev, pipe);
2556}
2557
53f5e3ca
JB		 2558static int i915_display_info(struct seq_file *m, void *unused)
2559{
9f25d007 2560 struct drm_info_node *node = m->private;
53f5e3ca 2561 struct drm_device *dev = node->minor->dev;
b0e5ddf3 2562 struct drm_i915_private *dev_priv = dev->dev_private;
065f2ec2 2563 struct intel_crtc *crtc;
53f5e3ca
JB		 2564 struct drm_connector *connector;
2565
b0e5ddf3 2566 intel_runtime_pm_get(dev_priv);
53f5e3ca
JB		 2567 drm_modeset_lock_all(dev);
2568 seq_printf(m, "CRTC info\n");
2569 seq_printf(m, "---------\n");
d3fcc808 2570 for_each_intel_crtc(dev, crtc) {
065f2ec2
CW		 2571 bool active;
2572 int x, y;
53f5e3ca 2573
57127efa 2574 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
065f2ec2 2575 crtc->base.base.id, pipe_name(crtc->pipe),
57127efa 2576 yesno(crtc->active), crtc->config.pipe_src_w, crtc->config.pipe_src_h);
a23dc658 2577 if (crtc->active) {
065f2ec2
CW		 2578 intel_crtc_info(m, crtc);
2579
a23dc658 2580 active = cursor_position(dev, crtc->pipe, &x, &y);
57127efa 2581 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
4b0e333e 2582 yesno(crtc->cursor_base),
57127efa
CW		 2583 x, y, crtc->cursor_width, crtc->cursor_height,
2584 crtc->cursor_addr, yesno(active));
a23dc658 2585 }
cace841c
DV		 2586
2587 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2588 yesno(!crtc->cpu_fifo_underrun_disabled),
2589 yesno(!crtc->pch_fifo_underrun_disabled));
53f5e3ca
JB		 2590 }
2591
2592 seq_printf(m, "\n");
2593 seq_printf(m, "Connector info\n");
2594 seq_printf(m, "--------------\n");
2595 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2596 intel_connector_info(m, connector);
2597 }
2598 drm_modeset_unlock_all(dev);
b0e5ddf3 2599 intel_runtime_pm_put(dev_priv);
53f5e3ca
JB		 2600
2601 return 0;
2602}
2603
e04934cf
BW		 2604static int i915_semaphore_status(struct seq_file *m, void *unused)
2605{
2606 struct drm_info_node *node = (struct drm_info_node *) m->private;
2607 struct drm_device *dev = node->minor->dev;
2608 struct drm_i915_private *dev_priv = dev->dev_private;
2609 struct intel_engine_cs *ring;
2610 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2611 int i, j, ret;
2612
2613 if (!i915_semaphore_is_enabled(dev)) {
2614 seq_puts(m, "Semaphores are disabled\n");
2615 return 0;
2616 }
2617
2618 ret = mutex_lock_interruptible(&dev->struct_mutex);
2619 if (ret)
2620 return ret;
03872064 2621 intel_runtime_pm_get(dev_priv);
e04934cf
BW		 2622
2623 if (IS_BROADWELL(dev)) {
2624 struct page *page;
2625 uint64_t *seqno;
2626
2627 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2628
2629 seqno = (uint64_t *)kmap_atomic(page);
2630 for_each_ring(ring, dev_priv, i) {
2631 uint64_t offset;
2632
2633 seq_printf(m, "%s\n", ring->name);
2634
2635 seq_puts(m, " Last signal:");
2636 for (j = 0; j < num_rings; j++) {
2637 offset = i * I915_NUM_RINGS + j;
2638 seq_printf(m, "0x%08llx (0x%02llx) ",
2639 seqno[offset], offset * 8);
2640 }
2641 seq_putc(m, '\n');
2642
2643 seq_puts(m, " Last wait: ");
2644 for (j = 0; j < num_rings; j++) {
2645 offset = i + (j * I915_NUM_RINGS);
2646 seq_printf(m, "0x%08llx (0x%02llx) ",
2647 seqno[offset], offset * 8);
2648 }
2649 seq_putc(m, '\n');
2650
2651 }
2652 kunmap_atomic(seqno);
2653 } else {
2654 seq_puts(m, " Last signal:");
2655 for_each_ring(ring, dev_priv, i)
2656 for (j = 0; j < num_rings; j++)
2657 seq_printf(m, "0x%08x\n",
2658 I915_READ(ring->semaphore.mbox.signal[j]));
2659 seq_putc(m, '\n');
2660 }
2661
2662 seq_puts(m, "\nSync seqno:\n");
2663 for_each_ring(ring, dev_priv, i) {
2664 for (j = 0; j < num_rings; j++) {
2665 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
2666 }
2667 seq_putc(m, '\n');
2668 }
2669 seq_putc(m, '\n');
2670
03872064 2671 intel_runtime_pm_put(dev_priv);
e04934cf
BW		 2672 mutex_unlock(&dev->struct_mutex);
2673 return 0;
2674}
2675
728e29d7
DV		 2676static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2677{
2678 struct drm_info_node *node = (struct drm_info_node *) m->private;
2679 struct drm_device *dev = node->minor->dev;
2680 struct drm_i915_private *dev_priv = dev->dev_private;
2681 int i;
2682
2683 drm_modeset_lock_all(dev);
2684 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2685 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2686
2687 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
1e6f2ddc 2688 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3e369b76 2689 pll->config.crtc_mask, pll->active, yesno(pll->on));
728e29d7 2690 seq_printf(m, " tracked hardware state:\n");
3e369b76
ACO		 2691 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
2692 seq_printf(m, " dpll_md: 0x%08x\n",
2693 pll->config.hw_state.dpll_md);
2694 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
2695 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
2696 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
728e29d7
DV		 2697 }
2698 drm_modeset_unlock_all(dev);
2699
2700 return 0;
2701}
2702
1ed1ef9d 2703static int i915_wa_registers(struct seq_file *m, void *unused)
888b5995
AS		 2704{
2705 int i;
2706 int ret;
2707 struct drm_info_node *node = (struct drm_info_node *) m->private;
2708 struct drm_device *dev = node->minor->dev;
2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710
888b5995
AS		 2711 ret = mutex_lock_interruptible(&dev->struct_mutex);
2712 if (ret)
2713 return ret;
2714
2715 intel_runtime_pm_get(dev_priv);
2716
7225342a
MK		 2717 seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2718 for (i = 0; i < dev_priv->workarounds.count; ++i) {
2fa60f6d
MK		 2719 u32 addr, mask, value, read;
2720 bool ok;
888b5995 2721
7225342a
MK		 2722 addr = dev_priv->workarounds.reg[i].addr;
2723 mask = dev_priv->workarounds.reg[i].mask;
2fa60f6d
MK		 2724 value = dev_priv->workarounds.reg[i].value;
2725 read = I915_READ(addr);
2726 ok = (value & mask) == (read & mask);
2727 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2728 addr, value, mask, read, ok ? "OK" : "FAIL");
888b5995
AS		 2729 }
2730
2731 intel_runtime_pm_put(dev_priv);
2732 mutex_unlock(&dev->struct_mutex);
2733
2734 return 0;
2735}
2736
c5511e44
DL		 2737static int i915_ddb_info(struct seq_file *m, void *unused)
2738{
2739 struct drm_info_node *node = m->private;
2740 struct drm_device *dev = node->minor->dev;
2741 struct drm_i915_private *dev_priv = dev->dev_private;
2742 struct skl_ddb_allocation *ddb;
2743 struct skl_ddb_entry *entry;
2744 enum pipe pipe;
2745 int plane;
2746
2fcffe19
DL		 2747 if (INTEL_INFO(dev)->gen < 9)
2748 return 0;
2749
c5511e44
DL		 2750 drm_modeset_lock_all(dev);
2751
2752 ddb = &dev_priv->wm.skl_hw.ddb;
2753
2754 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2755
2756 for_each_pipe(dev_priv, pipe) {
2757 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2758
2759 for_each_plane(pipe, plane) {
2760 entry = &ddb->plane[pipe][plane];
2761 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
2762 entry->start, entry->end,
2763 skl_ddb_entry_size(entry));
2764 }
2765
2766 entry = &ddb->cursor[pipe];
2767 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
2768 entry->end, skl_ddb_entry_size(entry));
2769 }
2770
2771 drm_modeset_unlock_all(dev);
2772
2773 return 0;
2774}
2775
07144428
DL		 2776struct pipe_crc_info {
2777 const char *name;
2778 struct drm_device *dev;
2779 enum pipe pipe;
2780};
2781
11bed958
DA		 2782static int i915_dp_mst_info(struct seq_file *m, void *unused)
2783{
2784 struct drm_info_node *node = (struct drm_info_node *) m->private;
2785 struct drm_device *dev = node->minor->dev;
2786 struct drm_encoder *encoder;
2787 struct intel_encoder *intel_encoder;
2788 struct intel_digital_port *intel_dig_port;
2789 drm_modeset_lock_all(dev);
2790 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2791 intel_encoder = to_intel_encoder(encoder);
2792 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
2793 continue;
2794 intel_dig_port = enc_to_dig_port(encoder);
2795 if (!intel_dig_port->dp.can_mst)
2796 continue;
2797
2798 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
2799 }
2800 drm_modeset_unlock_all(dev);
2801 return 0;
2802}
2803
07144428
DL		 2804static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2805{
be5c7a90
DL		 2806 struct pipe_crc_info *info = inode->i_private;
2807 struct drm_i915_private *dev_priv = info->dev->dev_private;
2808 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2809
7eb1c496
DV		 2810 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2811 return -ENODEV;
2812
d538bbdf
DL		 2813 spin_lock_irq(&pipe_crc->lock);
2814
2815 if (pipe_crc->opened) {
2816 spin_unlock_irq(&pipe_crc->lock);
be5c7a90
DL		 2817 return -EBUSY; /* already open */
2818 }
2819
d538bbdf 2820 pipe_crc->opened = true;
07144428
DL		 2821 filep->private_data = inode->i_private;
2822
d538bbdf
DL		 2823 spin_unlock_irq(&pipe_crc->lock);
2824
07144428
DL		 2825 return 0;
2826}
2827
2828static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2829{
be5c7a90
DL		 2830 struct pipe_crc_info *info = inode->i_private;
2831 struct drm_i915_private *dev_priv = info->dev->dev_private;
2832 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2833
d538bbdf
DL		 2834 spin_lock_irq(&pipe_crc->lock);
2835 pipe_crc->opened = false;
2836 spin_unlock_irq(&pipe_crc->lock);
be5c7a90 2837
07144428
DL		 2838 return 0;
2839}
2840
2841/* (6 fields, 8 chars each, space separated (5) + '\n') */
2842#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2843/* account for \'0' */
2844#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2845
2846static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
8bf1e9f1 2847{
d538bbdf
DL		 2848 assert_spin_locked(&pipe_crc->lock);
2849 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2850 INTEL_PIPE_CRC_ENTRIES_NR);
07144428
DL		 2851}
2852
2853static ssize_t
2854i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2855 loff_t *pos)
2856{
2857 struct pipe_crc_info *info = filep->private_data;
2858 struct drm_device *dev = info->dev;
2859 struct drm_i915_private *dev_priv = dev->dev_private;
2860 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2861 char buf[PIPE_CRC_BUFFER_LEN];
9ad6d99f 2862 int n_entries;
07144428
DL		 2863 ssize_t bytes_read;
2864
2865 /*
2866 * Don't allow user space to provide buffers not big enough to hold
2867 * a line of data.
2868 */
2869 if (count < PIPE_CRC_LINE_LEN)
2870 return -EINVAL;
2871
2872 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
8bf1e9f1 2873 return 0;
07144428
DL		 2874
2875 /* nothing to read */
d538bbdf 2876 spin_lock_irq(&pipe_crc->lock);
07144428 2877 while (pipe_crc_data_count(pipe_crc) == 0) {
d538bbdf
DL		 2878 int ret;
2879
2880 if (filep->f_flags & O_NONBLOCK) {
2881 spin_unlock_irq(&pipe_crc->lock);
07144428 2882 return -EAGAIN;
d538bbdf 2883 }
07144428 2884
d538bbdf
DL		 2885 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2886 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2887 if (ret) {
2888 spin_unlock_irq(&pipe_crc->lock);
2889 return ret;
2890 }
8bf1e9f1
SH		 2891 }
2892
07144428 2893 /* We now have one or more entries to read */
9ad6d99f 2894 n_entries = count / PIPE_CRC_LINE_LEN;
d538bbdf 2895
07144428 2896 bytes_read = 0;
9ad6d99f
VS		 2897 while (n_entries > 0) {
2898 struct intel_pipe_crc_entry *entry =
2899 &pipe_crc->entries[pipe_crc->tail];
07144428 2900 int ret;
8bf1e9f1 2901
9ad6d99f
VS		 2902 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2903 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
2904 break;
2905
2906 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2907 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2908
07144428
DL		 2909 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2910 "%8u %8x %8x %8x %8x %8x\n",
2911 entry->frame, entry->crc[0],
2912 entry->crc[1], entry->crc[2],
2913 entry->crc[3], entry->crc[4]);
2914
9ad6d99f
VS		 2915 spin_unlock_irq(&pipe_crc->lock);
2916
2917 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
07144428
DL		 2918 if (ret == PIPE_CRC_LINE_LEN)
2919 return -EFAULT;
b2c88f5b 2920
9ad6d99f
VS		 2921 user_buf += PIPE_CRC_LINE_LEN;
2922 n_entries--;
2923
2924 spin_lock_irq(&pipe_crc->lock);
2925 }
8bf1e9f1 2926
d538bbdf
DL		 2927 spin_unlock_irq(&pipe_crc->lock);
2928
07144428
DL		 2929 return bytes_read;
2930}
2931
2932static const struct file_operations i915_pipe_crc_fops = {
2933 .owner = THIS_MODULE,
2934 .open = i915_pipe_crc_open,
2935 .read = i915_pipe_crc_read,
2936 .release = i915_pipe_crc_release,
2937};
2938
2939static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2940 {
2941 .name = "i915_pipe_A_crc",
2942 .pipe = PIPE_A,
2943 },
2944 {
2945 .name = "i915_pipe_B_crc",
2946 .pipe = PIPE_B,
2947 },
2948 {
2949 .name = "i915_pipe_C_crc",
2950 .pipe = PIPE_C,
2951 },
2952};
2953
2954static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2955 enum pipe pipe)
2956{
2957 struct drm_device *dev = minor->dev;
2958 struct dentry *ent;
2959 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2960
2961 info->dev = dev;
2962 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2963 &i915_pipe_crc_fops);
f3c5fe97
WY		 2964 if (!ent)
2965 return -ENOMEM;
07144428
DL		 2966
2967 return drm_add_fake_info_node(minor, ent, info);
8bf1e9f1
SH		 2968}
2969
e8dfcf78 2970static const char * const pipe_crc_sources[] = {
926321d5
DV		 2971 "none",
2972 "plane1",
2973 "plane2",
2974 "pf",
5b3a856b 2975 "pipe",
3d099a05
DV		 2976 "TV",
2977 "DP-B",
2978 "DP-C",
2979 "DP-D",
46a19188 2980 "auto",
926321d5
DV		 2981};
2982
2983static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2984{
2985 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2986 return pipe_crc_sources[source];
2987}
2988
bd9db02f 2989static int display_crc_ctl_show(struct seq_file *m, void *data)
926321d5
DV		 2990{
2991 struct drm_device *dev = m->private;
2992 struct drm_i915_private *dev_priv = dev->dev_private;
2993 int i;
2994
2995 for (i = 0; i < I915_MAX_PIPES; i++)
2996 seq_printf(m, "%c %s\n", pipe_name(i),
2997 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2998
2999 return 0;
3000}
3001
bd9db02f 3002static int display_crc_ctl_open(struct inode *inode, struct file *file)
926321d5
DV		 3003{
3004 struct drm_device *dev = inode->i_private;
3005
bd9db02f 3006 return single_open(file, display_crc_ctl_show, dev);
926321d5
DV		 3007}
3008
46a19188 3009static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
52f843f6
DV		 3010 uint32_t *val)
3011{
46a19188
DV		 3012 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3013 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3014
3015 switch (*source) {
52f843f6
DV		 3016 case INTEL_PIPE_CRC_SOURCE_PIPE:
3017 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3018 break;
3019 case INTEL_PIPE_CRC_SOURCE_NONE:
3020 *val = 0;
3021 break;
3022 default:
3023 return -EINVAL;
3024 }
3025
3026 return 0;
3027}
3028
46a19188
DV		 3029static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3030 enum intel_pipe_crc_source *source)
3031{
3032 struct intel_encoder *encoder;
3033 struct intel_crtc *crtc;
26756809 3034 struct intel_digital_port *dig_port;
46a19188
DV		 3035 int ret = 0;
3036
3037 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3038
6e9f798d 3039 drm_modeset_lock_all(dev);
b2784e15 3040 for_each_intel_encoder(dev, encoder) {
46a19188
DV		 3041 if (!encoder->base.crtc)
3042 continue;
3043
3044 crtc = to_intel_crtc(encoder->base.crtc);
3045
3046 if (crtc->pipe != pipe)
3047 continue;
3048
3049 switch (encoder->type) {
3050 case INTEL_OUTPUT_TVOUT:
3051 *source = INTEL_PIPE_CRC_SOURCE_TV;
3052 break;
3053 case INTEL_OUTPUT_DISPLAYPORT:
3054 case INTEL_OUTPUT_EDP:
26756809
DV		 3055 dig_port = enc_to_dig_port(&encoder->base);
3056 switch (dig_port->port) {
3057 case PORT_B:
3058 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3059 break;
3060 case PORT_C:
3061 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3062 break;
3063 case PORT_D:
3064 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3065 break;
3066 default:
3067 WARN(1, "nonexisting DP port %c\n",
3068 port_name(dig_port->port));
3069 break;
3070 }
46a19188 3071 break;
6847d71b
PZ		 3072 default:
3073 break;
46a19188
DV		 3074 }
3075 }
6e9f798d 3076 drm_modeset_unlock_all(dev);
46a19188
DV		 3077
3078 return ret;
3079}
3080
3081static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3082 enum pipe pipe,
3083 enum intel_pipe_crc_source *source,
7ac0129b
DV		 3084 uint32_t *val)
3085{
8d2f24ca
DV		 3086 struct drm_i915_private *dev_priv = dev->dev_private;
3087 bool need_stable_symbols = false;
3088
46a19188
DV		 3089 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3090 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3091 if (ret)
3092 return ret;
3093 }
3094
3095 switch (*source) {
7ac0129b
DV		 3096 case INTEL_PIPE_CRC_SOURCE_PIPE:
3097 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3098 break;
3099 case INTEL_PIPE_CRC_SOURCE_DP_B:
3100 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
8d2f24ca 3101 need_stable_symbols = true;
7ac0129b
DV		 3102 break;
3103 case INTEL_PIPE_CRC_SOURCE_DP_C:
3104 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
8d2f24ca 3105 need_stable_symbols = true;
7ac0129b 3106 break;
2be57922
VS		 3107 case INTEL_PIPE_CRC_SOURCE_DP_D:
3108 if (!IS_CHERRYVIEW(dev))
3109 return -EINVAL;
3110 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3111 need_stable_symbols = true;
3112 break;
7ac0129b
DV		 3113 case INTEL_PIPE_CRC_SOURCE_NONE:
3114 *val = 0;
3115 break;
3116 default:
3117 return -EINVAL;
3118 }
3119
8d2f24ca
DV		 3120 /*
3121 * When the pipe CRC tap point is after the transcoders we need
3122 * to tweak symbol-level features to produce a deterministic series of
3123 * symbols for a given frame. We need to reset those features only once
3124 * a frame (instead of every nth symbol):
3125 * - DC-balance: used to ensure a better clock recovery from the data
3126 * link (SDVO)
3127 * - DisplayPort scrambling: used for EMI reduction
3128 */
3129 if (need_stable_symbols) {
3130 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3131
8d2f24ca 3132 tmp |= DC_BALANCE_RESET_VLV;
eb736679
VS		 3133 switch (pipe) {
3134 case PIPE_A:
8d2f24ca 3135 tmp |= PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3136 break;
3137 case PIPE_B:
8d2f24ca 3138 tmp |= PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3139 break;
3140 case PIPE_C:
3141 tmp |= PIPE_C_SCRAMBLE_RESET;
3142 break;
3143 default:
3144 return -EINVAL;
3145 }
8d2f24ca
DV		 3146 I915_WRITE(PORT_DFT2_G4X, tmp);
3147 }
3148
7ac0129b
DV		 3149 return 0;
3150}
3151
4b79ebf7 3152static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
46a19188
DV		 3153 enum pipe pipe,
3154 enum intel_pipe_crc_source *source,
4b79ebf7
DV		 3155 uint32_t *val)
3156{
84093603
DV		 3157 struct drm_i915_private *dev_priv = dev->dev_private;
3158 bool need_stable_symbols = false;
3159
46a19188
DV		 3160 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3161 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3162 if (ret)
3163 return ret;
3164 }
3165
3166 switch (*source) {
4b79ebf7
DV		 3167 case INTEL_PIPE_CRC_SOURCE_PIPE:
3168 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3169 break;
3170 case INTEL_PIPE_CRC_SOURCE_TV:
3171 if (!SUPPORTS_TV(dev))
3172 return -EINVAL;
3173 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3174 break;
3175 case INTEL_PIPE_CRC_SOURCE_DP_B:
3176 if (!IS_G4X(dev))
3177 return -EINVAL;
3178 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
84093603 3179 need_stable_symbols = true;
4b79ebf7
DV		 3180 break;
3181 case INTEL_PIPE_CRC_SOURCE_DP_C:
3182 if (!IS_G4X(dev))
3183 return -EINVAL;
3184 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
84093603 3185 need_stable_symbols = true;
4b79ebf7
DV		 3186 break;
3187 case INTEL_PIPE_CRC_SOURCE_DP_D:
3188 if (!IS_G4X(dev))
3189 return -EINVAL;
3190 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
84093603 3191 need_stable_symbols = true;
4b79ebf7
DV		 3192 break;
3193 case INTEL_PIPE_CRC_SOURCE_NONE:
3194 *val = 0;
3195 break;
3196 default:
3197 return -EINVAL;
3198 }
3199
84093603
DV		 3200 /*
3201 * When the pipe CRC tap point is after the transcoders we need
3202 * to tweak symbol-level features to produce a deterministic series of
3203 * symbols for a given frame. We need to reset those features only once
3204 * a frame (instead of every nth symbol):
3205 * - DC-balance: used to ensure a better clock recovery from the data
3206 * link (SDVO)
3207 * - DisplayPort scrambling: used for EMI reduction
3208 */
3209 if (need_stable_symbols) {
3210 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3211
3212 WARN_ON(!IS_G4X(dev));
3213
3214 I915_WRITE(PORT_DFT_I9XX,
3215 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3216
3217 if (pipe == PIPE_A)
3218 tmp |= PIPE_A_SCRAMBLE_RESET;
3219 else
3220 tmp |= PIPE_B_SCRAMBLE_RESET;
3221
3222 I915_WRITE(PORT_DFT2_G4X, tmp);
3223 }
3224
4b79ebf7
DV		 3225 return 0;
3226}
3227
8d2f24ca
DV		 3228static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3229 enum pipe pipe)
3230{
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3233
eb736679
VS		 3234 switch (pipe) {
3235 case PIPE_A:
8d2f24ca 3236 tmp &= ~PIPE_A_SCRAMBLE_RESET;
eb736679
VS		 3237 break;
3238 case PIPE_B:
8d2f24ca 3239 tmp &= ~PIPE_B_SCRAMBLE_RESET;
eb736679
VS		 3240 break;
3241 case PIPE_C:
3242 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3243 break;
3244 default:
3245 return;
3246 }
8d2f24ca
DV		 3247 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3248 tmp &= ~DC_BALANCE_RESET_VLV;
3249 I915_WRITE(PORT_DFT2_G4X, tmp);
3250
3251}
3252
84093603
DV		 3253static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3254 enum pipe pipe)
3255{
3256 struct drm_i915_private *dev_priv = dev->dev_private;
3257 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3258
3259 if (pipe == PIPE_A)
3260 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3261 else
3262 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3263 I915_WRITE(PORT_DFT2_G4X, tmp);
3264
3265 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3266 I915_WRITE(PORT_DFT_I9XX,
3267 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3268 }
3269}
3270
46a19188 3271static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
5b3a856b
DV		 3272 uint32_t *val)
3273{
46a19188
DV		 3274 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3275 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3276
3277 switch (*source) {
5b3a856b
DV		 3278 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3279 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3280 break;
3281 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3282 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3283 break;
5b3a856b
DV		 3284 case INTEL_PIPE_CRC_SOURCE_PIPE:
3285 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3286 break;
3d099a05 3287 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3288 *val = 0;
3289 break;
3d099a05
DV		 3290 default:
3291 return -EINVAL;
5b3a856b
DV		 3292 }
3293
3294 return 0;
3295}
3296
fabf6e51
DV		 3297static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3298{
3299 struct drm_i915_private *dev_priv = dev->dev_private;
3300 struct intel_crtc *crtc =
3301 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3302
3303 drm_modeset_lock_all(dev);
3304 /*
3305 * If we use the eDP transcoder we need to make sure that we don't
3306 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3307 * relevant on hsw with pipe A when using the always-on power well
3308 * routing.
3309 */
3310 if (crtc->config.cpu_transcoder == TRANSCODER_EDP &&
3311 !crtc->config.pch_pfit.enabled) {
3312 crtc->config.pch_pfit.force_thru = true;
3313
3314 intel_display_power_get(dev_priv,
3315 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3316
3317 dev_priv->display.crtc_disable(&crtc->base);
3318 dev_priv->display.crtc_enable(&crtc->base);
3319 }
3320 drm_modeset_unlock_all(dev);
3321}
3322
3323static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3324{
3325 struct drm_i915_private *dev_priv = dev->dev_private;
3326 struct intel_crtc *crtc =
3327 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3328
3329 drm_modeset_lock_all(dev);
3330 /*
3331 * If we use the eDP transcoder we need to make sure that we don't
3332 * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3333 * relevant on hsw with pipe A when using the always-on power well
3334 * routing.
3335 */
3336 if (crtc->config.pch_pfit.force_thru) {
3337 crtc->config.pch_pfit.force_thru = false;
3338
3339 dev_priv->display.crtc_disable(&crtc->base);
3340 dev_priv->display.crtc_enable(&crtc->base);
3341
3342 intel_display_power_put(dev_priv,
3343 POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3344 }
3345 drm_modeset_unlock_all(dev);
3346}
3347
3348static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3349 enum pipe pipe,
3350 enum intel_pipe_crc_source *source,
5b3a856b
DV		 3351 uint32_t *val)
3352{
46a19188
DV		 3353 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3354 *source = INTEL_PIPE_CRC_SOURCE_PF;
3355
3356 switch (*source) {
5b3a856b
DV		 3357 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3358 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3359 break;
3360 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3361 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3362 break;
3363 case INTEL_PIPE_CRC_SOURCE_PF:
fabf6e51
DV		 3364 if (IS_HASWELL(dev) && pipe == PIPE_A)
3365 hsw_trans_edp_pipe_A_crc_wa(dev);
3366
5b3a856b
DV		 3367 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3368 break;
3d099a05 3369 case INTEL_PIPE_CRC_SOURCE_NONE:
5b3a856b
DV		 3370 *val = 0;
3371 break;
3d099a05
DV		 3372 default:
3373 return -EINVAL;
5b3a856b
DV		 3374 }
3375
3376 return 0;
3377}
3378
926321d5
DV		 3379static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3380 enum intel_pipe_crc_source source)
3381{
3382 struct drm_i915_private *dev_priv = dev->dev_private;
cc3da175 3383 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
8c740dce
PZ		 3384 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3385 pipe));
432f3342 3386 u32 val = 0; /* shut up gcc */
5b3a856b 3387 int ret;
926321d5 3388
cc3da175
DL		 3389 if (pipe_crc->source == source)
3390 return 0;
3391
ae676fcd
DL		 3392 /* forbid changing the source without going back to 'none' */
3393 if (pipe_crc->source && source)
3394 return -EINVAL;
3395
9d8b0588
DV		 3396 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3397 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3398 return -EIO;
3399 }
3400
52f843f6 3401 if (IS_GEN2(dev))
46a19188 3402 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
52f843f6 3403 else if (INTEL_INFO(dev)->gen < 5)
46a19188 3404 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
7ac0129b 3405 else if (IS_VALLEYVIEW(dev))
fabf6e51 3406 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4b79ebf7 3407 else if (IS_GEN5(dev) || IS_GEN6(dev))
46a19188 3408 ret = ilk_pipe_crc_ctl_reg(&source, &val);
5b3a856b 3409 else
fabf6e51 3410 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
5b3a856b
DV		 3411
3412 if (ret != 0)
3413 return ret;
3414
4b584369
DL		 3415 /* none -> real source transition */
3416 if (source) {
4252fbc3
VS		 3417 struct intel_pipe_crc_entry *entries;
3418
7cd6ccff
DL		 3419 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3420 pipe_name(pipe), pipe_crc_source_name(source));
3421
3cf54b34
VS		 3422 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3423 sizeof(pipe_crc->entries[0]),
4252fbc3
VS		 3424 GFP_KERNEL);
3425 if (!entries)
e5f75aca
DL		 3426 return -ENOMEM;
3427
8c740dce
PZ		 3428 /*
3429 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3430 * enabled and disabled dynamically based on package C states,
3431 * user space can't make reliable use of the CRCs, so let's just
3432 * completely disable it.
3433 */
3434 hsw_disable_ips(crtc);
3435
d538bbdf 3436 spin_lock_irq(&pipe_crc->lock);
64387b61 3437 kfree(pipe_crc->entries);
4252fbc3 3438 pipe_crc->entries = entries;
d538bbdf
DL		 3439 pipe_crc->head = 0;
3440 pipe_crc->tail = 0;
3441 spin_unlock_irq(&pipe_crc->lock);
4b584369
DL		 3442 }
3443
cc3da175 3444 pipe_crc->source = source;
926321d5 3445
926321d5
DV		 3446 I915_WRITE(PIPE_CRC_CTL(pipe), val);
3447 POSTING_READ(PIPE_CRC_CTL(pipe));
3448
e5f75aca
DL		 3449 /* real source -> none transition */
3450 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
d538bbdf 3451 struct intel_pipe_crc_entry *entries;
a33d7105
DV		 3452 struct intel_crtc *crtc =
3453 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
d538bbdf 3454
7cd6ccff
DL		 3455 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3456 pipe_name(pipe));
3457
a33d7105
DV		 3458 drm_modeset_lock(&crtc->base.mutex, NULL);
3459 if (crtc->active)
3460 intel_wait_for_vblank(dev, pipe);
3461 drm_modeset_unlock(&crtc->base.mutex);
bcf17ab2 3462
d538bbdf
DL		 3463 spin_lock_irq(&pipe_crc->lock);
3464 entries = pipe_crc->entries;
e5f75aca 3465 pipe_crc->entries = NULL;
9ad6d99f
VS		 3466 pipe_crc->head = 0;
3467 pipe_crc->tail = 0;
d538bbdf
DL		 3468 spin_unlock_irq(&pipe_crc->lock);
3469
3470 kfree(entries);
84093603
DV		 3471
3472 if (IS_G4X(dev))
3473 g4x_undo_pipe_scramble_reset(dev, pipe);
8d2f24ca
DV		 3474 else if (IS_VALLEYVIEW(dev))
3475 vlv_undo_pipe_scramble_reset(dev, pipe);
fabf6e51
DV		 3476 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3477 hsw_undo_trans_edp_pipe_A_crc_wa(dev);
8c740dce
PZ		 3478
3479 hsw_enable_ips(crtc);
e5f75aca
DL		 3480 }
3481
926321d5
DV		 3482 return 0;
3483}
3484
3485/*
3486 * Parse pipe CRC command strings:
b94dec87
DL		 3487 * command: wsp* object wsp+ name wsp+ source wsp*
3488 * object: 'pipe'
3489 * name: (A | B | C)
926321d5
DV		 3490 * source: (none | plane1 | plane2 | pf)
3491 * wsp: (#0x20 | #0x9 | #0xA)+
3492 *
3493 * eg.:
b94dec87
DL		 3494 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
3495 * "pipe A none" -> Stop CRC
926321d5 3496 */
bd9db02f 3497static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
926321d5
DV		 3498{
3499 int n_words = 0;
3500
3501 while (*buf) {
3502 char *end;
3503
3504 /* skip leading white space */
3505 buf = skip_spaces(buf);
3506 if (!*buf)
3507 break; /* end of buffer */
3508
3509 /* find end of word */
3510 for (end = buf; *end && !isspace(*end); end++)
3511 ;
3512
3513 if (n_words == max_words) {
3514 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3515 max_words);
3516 return -EINVAL; /* ran out of words[] before bytes */
3517 }
3518
3519 if (*end)
3520 *end++ = '\0';
3521 words[n_words++] = buf;
3522 buf = end;
3523 }
3524
3525 return n_words;
3526}
3527
b94dec87
DL		 3528enum intel_pipe_crc_object {
3529 PIPE_CRC_OBJECT_PIPE,
3530};
3531
e8dfcf78 3532static const char * const pipe_crc_objects[] = {
b94dec87
DL		 3533 "pipe",
3534};
3535
3536static int
bd9db02f 3537display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
b94dec87
DL		 3538{
3539 int i;
3540
3541 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3542 if (!strcmp(buf, pipe_crc_objects[i])) {
bd9db02f 3543 *o = i;
b94dec87
DL		 3544 return 0;
3545 }
3546
3547 return -EINVAL;
3548}
3549
bd9db02f 3550static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
926321d5
DV		 3551{
3552 const char name = buf[0];
3553
3554 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3555 return -EINVAL;
3556
3557 *pipe = name - 'A';
3558
3559 return 0;
3560}
3561
3562static int
bd9db02f 3563display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
926321d5
DV		 3564{
3565 int i;
3566
3567 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3568 if (!strcmp(buf, pipe_crc_sources[i])) {
bd9db02f 3569 *s = i;
926321d5
DV		 3570 return 0;
3571 }
3572
3573 return -EINVAL;
3574}
3575
bd9db02f 3576static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
926321d5 3577{
b94dec87 3578#define N_WORDS 3
926321d5 3579 int n_words;
b94dec87 3580 char *words[N_WORDS];
926321d5 3581 enum pipe pipe;
b94dec87 3582 enum intel_pipe_crc_object object;
926321d5
DV		 3583 enum intel_pipe_crc_source source;
3584
bd9db02f 3585 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
b94dec87
DL		 3586 if (n_words != N_WORDS) {
3587 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3588 N_WORDS);
3589 return -EINVAL;
3590 }
3591
bd9db02f 3592 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
b94dec87 3593 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
926321d5
DV		 3594 return -EINVAL;
3595 }
3596
bd9db02f 3597 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
b94dec87 3598 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
926321d5
DV		 3599 return -EINVAL;
3600 }
3601
bd9db02f 3602 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
b94dec87 3603 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
926321d5
DV		 3604 return -EINVAL;
3605 }
3606
3607 return pipe_crc_set_source(dev, pipe, source);
3608}
3609
bd9db02f
DL		 3610static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3611 size_t len, loff_t *offp)
926321d5
DV		 3612{
3613 struct seq_file *m = file->private_data;
3614 struct drm_device *dev = m->private;
3615 char *tmpbuf;
3616 int ret;
3617
3618 if (len == 0)
3619 return 0;
3620
3621 if (len > PAGE_SIZE - 1) {
3622 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3623 PAGE_SIZE);
3624 return -E2BIG;
3625 }
3626
3627 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3628 if (!tmpbuf)
3629 return -ENOMEM;
3630
3631 if (copy_from_user(tmpbuf, ubuf, len)) {
3632 ret = -EFAULT;
3633 goto out;
3634 }
3635 tmpbuf[len] = '\0';
3636
bd9db02f 3637 ret = display_crc_ctl_parse(dev, tmpbuf, len);
926321d5
DV		 3638
3639out:
3640 kfree(tmpbuf);
3641 if (ret < 0)
3642 return ret;
3643
3644 *offp += len;
3645 return len;
3646}
3647
bd9db02f 3648static const struct file_operations i915_display_crc_ctl_fops = {
926321d5 3649 .owner = THIS_MODULE,
bd9db02f 3650 .open = display_crc_ctl_open,
926321d5
DV		 3651 .read = seq_read,
3652 .llseek = seq_lseek,
3653 .release = single_release,
bd9db02f 3654 .write = display_crc_ctl_write
926321d5
DV		 3655};
3656
97e94b22 3657static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
369a1342
VS		 3658{
3659 struct drm_device *dev = m->private;
546c81fd 3660 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3661 int level;
3662
3663 drm_modeset_lock_all(dev);
3664
3665 for (level = 0; level < num_levels; level++) {
3666 unsigned int latency = wm[level];
3667
97e94b22
DL		 3668 /*
3669 * - WM1+ latency values in 0.5us units
3670 * - latencies are in us on gen9
3671 */
3672 if (INTEL_INFO(dev)->gen >= 9)
3673 latency *= 10;
3674 else if (level > 0)
369a1342
VS		 3675 latency *= 5;
3676
3677 seq_printf(m, "WM%d %u (%u.%u usec)\n",
97e94b22 3678 level, wm[level], latency / 10, latency % 10);
369a1342
VS		 3679 }
3680
3681 drm_modeset_unlock_all(dev);
3682}
3683
3684static int pri_wm_latency_show(struct seq_file *m, void *data)
3685{
3686 struct drm_device *dev = m->private;
97e94b22
DL		 3687 struct drm_i915_private *dev_priv = dev->dev_private;
3688 const uint16_t *latencies;
3689
3690 if (INTEL_INFO(dev)->gen >= 9)
3691 latencies = dev_priv->wm.skl_latency;
3692 else
3693 latencies = to_i915(dev)->wm.pri_latency;
369a1342 3694
97e94b22 3695 wm_latency_show(m, latencies);
369a1342
VS		 3696
3697 return 0;
3698}
3699
3700static int spr_wm_latency_show(struct seq_file *m, void *data)
3701{
3702 struct drm_device *dev = m->private;
97e94b22
DL		 3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 const uint16_t *latencies;
3705
3706 if (INTEL_INFO(dev)->gen >= 9)
3707 latencies = dev_priv->wm.skl_latency;
3708 else
3709 latencies = to_i915(dev)->wm.spr_latency;
369a1342 3710
97e94b22 3711 wm_latency_show(m, latencies);
369a1342
VS		 3712
3713 return 0;
3714}
3715
3716static int cur_wm_latency_show(struct seq_file *m, void *data)
3717{
3718 struct drm_device *dev = m->private;
97e94b22
DL		 3719 struct drm_i915_private *dev_priv = dev->dev_private;
3720 const uint16_t *latencies;
3721
3722 if (INTEL_INFO(dev)->gen >= 9)
3723 latencies = dev_priv->wm.skl_latency;
3724 else
3725 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3726
97e94b22 3727 wm_latency_show(m, latencies);
369a1342
VS		 3728
3729 return 0;
3730}
3731
3732static int pri_wm_latency_open(struct inode *inode, struct file *file)
3733{
3734 struct drm_device *dev = inode->i_private;
3735
9ad0257c 3736 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3737 return -ENODEV;
3738
3739 return single_open(file, pri_wm_latency_show, dev);
3740}
3741
3742static int spr_wm_latency_open(struct inode *inode, struct file *file)
3743{
3744 struct drm_device *dev = inode->i_private;
3745
9ad0257c 3746 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3747 return -ENODEV;
3748
3749 return single_open(file, spr_wm_latency_show, dev);
3750}
3751
3752static int cur_wm_latency_open(struct inode *inode, struct file *file)
3753{
3754 struct drm_device *dev = inode->i_private;
3755
9ad0257c 3756 if (HAS_GMCH_DISPLAY(dev))
369a1342
VS		 3757 return -ENODEV;
3758
3759 return single_open(file, cur_wm_latency_show, dev);
3760}
3761
3762static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
97e94b22 3763 size_t len, loff_t *offp, uint16_t wm[8])
369a1342
VS		 3764{
3765 struct seq_file *m = file->private_data;
3766 struct drm_device *dev = m->private;
97e94b22 3767 uint16_t new[8] = { 0 };
546c81fd 3768 int num_levels = ilk_wm_max_level(dev) + 1;
369a1342
VS		 3769 int level;
3770 int ret;
3771 char tmp[32];
3772
3773 if (len >= sizeof(tmp))
3774 return -EINVAL;
3775
3776 if (copy_from_user(tmp, ubuf, len))
3777 return -EFAULT;
3778
3779 tmp[len] = '\0';
3780
97e94b22
DL		 3781 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
3782 &new[0], &new[1], &new[2], &new[3],
3783 &new[4], &new[5], &new[6], &new[7]);
369a1342
VS		 3784 if (ret != num_levels)
3785 return -EINVAL;
3786
3787 drm_modeset_lock_all(dev);
3788
3789 for (level = 0; level < num_levels; level++)
3790 wm[level] = new[level];
3791
3792 drm_modeset_unlock_all(dev);
3793
3794 return len;
3795}
3796
3797
3798static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3799 size_t len, loff_t *offp)
3800{
3801 struct seq_file *m = file->private_data;
3802 struct drm_device *dev = m->private;
97e94b22
DL		 3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 uint16_t *latencies;
369a1342 3805
97e94b22
DL		 3806 if (INTEL_INFO(dev)->gen >= 9)
3807 latencies = dev_priv->wm.skl_latency;
3808 else
3809 latencies = to_i915(dev)->wm.pri_latency;
3810
3811 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3812}
3813
3814static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3815 size_t len, loff_t *offp)
3816{
3817 struct seq_file *m = file->private_data;
3818 struct drm_device *dev = m->private;
97e94b22
DL		 3819 struct drm_i915_private *dev_priv = dev->dev_private;
3820 uint16_t *latencies;
369a1342 3821
97e94b22
DL		 3822 if (INTEL_INFO(dev)->gen >= 9)
3823 latencies = dev_priv->wm.skl_latency;
3824 else
3825 latencies = to_i915(dev)->wm.spr_latency;
3826
3827 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3828}
3829
3830static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3831 size_t len, loff_t *offp)
3832{
3833 struct seq_file *m = file->private_data;
3834 struct drm_device *dev = m->private;
97e94b22
DL		 3835 struct drm_i915_private *dev_priv = dev->dev_private;
3836 uint16_t *latencies;
3837
3838 if (INTEL_INFO(dev)->gen >= 9)
3839 latencies = dev_priv->wm.skl_latency;
3840 else
3841 latencies = to_i915(dev)->wm.cur_latency;
369a1342 3842
97e94b22 3843 return wm_latency_write(file, ubuf, len, offp, latencies);
369a1342
VS		 3844}
3845
3846static const struct file_operations i915_pri_wm_latency_fops = {
3847 .owner = THIS_MODULE,
3848 .open = pri_wm_latency_open,
3849 .read = seq_read,
3850 .llseek = seq_lseek,
3851 .release = single_release,
3852 .write = pri_wm_latency_write
3853};
3854
3855static const struct file_operations i915_spr_wm_latency_fops = {
3856 .owner = THIS_MODULE,
3857 .open = spr_wm_latency_open,
3858 .read = seq_read,
3859 .llseek = seq_lseek,
3860 .release = single_release,
3861 .write = spr_wm_latency_write
3862};
3863
3864static const struct file_operations i915_cur_wm_latency_fops = {
3865 .owner = THIS_MODULE,
3866 .open = cur_wm_latency_open,
3867 .read = seq_read,
3868 .llseek = seq_lseek,
3869 .release = single_release,
3870 .write = cur_wm_latency_write
3871};
3872
647416f9
KC		 3873static int
3874i915_wedged_get(void *data, u64 *val)
f3cd474b 3875{
647416f9 3876 struct drm_device *dev = data;
e277a1f8 3877 struct drm_i915_private *dev_priv = dev->dev_private;
f3cd474b 3878
647416f9 3879 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
f3cd474b 3880
647416f9 3881 return 0;
f3cd474b
CW		 3882}
3883
647416f9
KC		 3884static int
3885i915_wedged_set(void *data, u64 val)
f3cd474b 3886{
647416f9 3887 struct drm_device *dev = data;
d46c0517
ID		 3888 struct drm_i915_private *dev_priv = dev->dev_private;
3889
3890 intel_runtime_pm_get(dev_priv);
f3cd474b 3891
58174462
MK		 3892 i915_handle_error(dev, val,
3893 "Manually setting wedged to %llu", val);
d46c0517
ID		 3894
3895 intel_runtime_pm_put(dev_priv);
3896
647416f9 3897 return 0;
f3cd474b
CW		 3898}
3899
647416f9
KC		 3900DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3901 i915_wedged_get, i915_wedged_set,
3a3b4f98 3902 "%llu\n");
f3cd474b 3903
647416f9
KC		 3904static int
3905i915_ring_stop_get(void *data, u64 *val)
e5eb3d63 3906{
647416f9 3907 struct drm_device *dev = data;
e277a1f8 3908 struct drm_i915_private *dev_priv = dev->dev_private;
e5eb3d63 3909
647416f9 3910 *val = dev_priv->gpu_error.stop_rings;
e5eb3d63 3911
647416f9 3912 return 0;
e5eb3d63
DV		 3913}
3914
647416f9
KC		 3915static int
3916i915_ring_stop_set(void *data, u64 val)
e5eb3d63 3917{
647416f9 3918 struct drm_device *dev = data;
e5eb3d63 3919 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 3920 int ret;
e5eb3d63 3921
647416f9 3922 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
e5eb3d63 3923
22bcfc6a
DV		 3924 ret = mutex_lock_interruptible(&dev->struct_mutex);
3925 if (ret)
3926 return ret;
3927
99584db3 3928 dev_priv->gpu_error.stop_rings = val;
e5eb3d63
DV		 3929 mutex_unlock(&dev->struct_mutex);
3930
647416f9 3931 return 0;
e5eb3d63
DV		 3932}
3933
647416f9
KC		 3934DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3935 i915_ring_stop_get, i915_ring_stop_set,
3936 "0x%08llx\n");
d5442303 3937
094f9a54
CW		 3938static int
3939i915_ring_missed_irq_get(void *data, u64 *val)
3940{
3941 struct drm_device *dev = data;
3942 struct drm_i915_private *dev_priv = dev->dev_private;
3943
3944 *val = dev_priv->gpu_error.missed_irq_rings;
3945 return 0;
3946}
3947
3948static int
3949i915_ring_missed_irq_set(void *data, u64 val)
3950{
3951 struct drm_device *dev = data;
3952 struct drm_i915_private *dev_priv = dev->dev_private;
3953 int ret;
3954
3955 /* Lock against concurrent debugfs callers */
3956 ret = mutex_lock_interruptible(&dev->struct_mutex);
3957 if (ret)
3958 return ret;
3959 dev_priv->gpu_error.missed_irq_rings = val;
3960 mutex_unlock(&dev->struct_mutex);
3961
3962 return 0;
3963}
3964
3965DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3966 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3967 "0x%08llx\n");
3968
3969static int
3970i915_ring_test_irq_get(void *data, u64 *val)
3971{
3972 struct drm_device *dev = data;
3973 struct drm_i915_private *dev_priv = dev->dev_private;
3974
3975 *val = dev_priv->gpu_error.test_irq_rings;
3976
3977 return 0;
3978}
3979
3980static int
3981i915_ring_test_irq_set(void *data, u64 val)
3982{
3983 struct drm_device *dev = data;
3984 struct drm_i915_private *dev_priv = dev->dev_private;
3985 int ret;
3986
3987 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3988
3989 /* Lock against concurrent debugfs callers */
3990 ret = mutex_lock_interruptible(&dev->struct_mutex);
3991 if (ret)
3992 return ret;
3993
3994 dev_priv->gpu_error.test_irq_rings = val;
3995 mutex_unlock(&dev->struct_mutex);
3996
3997 return 0;
3998}
3999
4000DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4001 i915_ring_test_irq_get, i915_ring_test_irq_set,
4002 "0x%08llx\n");
4003
dd624afd
CW		 4004#define DROP_UNBOUND 0x1
4005#define DROP_BOUND 0x2
4006#define DROP_RETIRE 0x4
4007#define DROP_ACTIVE 0x8
4008#define DROP_ALL (DROP_UNBOUND | \
4009 DROP_BOUND | \
4010 DROP_RETIRE | \
4011 DROP_ACTIVE)
647416f9
KC		 4012static int
4013i915_drop_caches_get(void *data, u64 *val)
dd624afd 4014{
647416f9 4015 *val = DROP_ALL;
dd624afd 4016
647416f9 4017 return 0;
dd624afd
CW		 4018}
4019
647416f9
KC		 4020static int
4021i915_drop_caches_set(void *data, u64 val)
dd624afd 4022{
647416f9 4023 struct drm_device *dev = data;
dd624afd 4024 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4025 int ret;
dd624afd 4026
2f9fe5ff 4027 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
dd624afd
CW		 4028
4029 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4030 * on ioctls on -EAGAIN. */
4031 ret = mutex_lock_interruptible(&dev->struct_mutex);
4032 if (ret)
4033 return ret;
4034
4035 if (val & DROP_ACTIVE) {
4036 ret = i915_gpu_idle(dev);
4037 if (ret)
4038 goto unlock;
4039 }
4040
4041 if (val & (DROP_RETIRE | DROP_ACTIVE))
4042 i915_gem_retire_requests(dev);
4043
21ab4e74
CW		 4044 if (val & DROP_BOUND)
4045 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4ad72b7f 4046
21ab4e74
CW		 4047 if (val & DROP_UNBOUND)
4048 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
dd624afd
CW		 4049
4050unlock:
4051 mutex_unlock(&dev->struct_mutex);
4052
647416f9 4053 return ret;
dd624afd
CW		 4054}
4055
647416f9
KC		 4056DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4057 i915_drop_caches_get, i915_drop_caches_set,
4058 "0x%08llx\n");
dd624afd 4059
647416f9
KC		 4060static int
4061i915_max_freq_get(void *data, u64 *val)
358733e9 4062{
647416f9 4063 struct drm_device *dev = data;
e277a1f8 4064 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4065 int ret;
004777cb 4066
daa3afb2 4067 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4068 return -ENODEV;
4069
5c9669ce
TR		 4070 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4071
4fc688ce 4072 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4073 if (ret)
4074 return ret;
358733e9 4075
0a073b84 4076 if (IS_VALLEYVIEW(dev))
b39fb297 4077 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
0a073b84 4078 else
b39fb297 4079 *val = dev_priv->rps.max_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 4080 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4081
647416f9 4082 return 0;
358733e9
JB		 4083}
4084
647416f9
KC		 4085static int
4086i915_max_freq_set(void *data, u64 val)
358733e9 4087{
647416f9 4088 struct drm_device *dev = data;
358733e9 4089 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4090 u32 rp_state_cap, hw_max, hw_min;
647416f9 4091 int ret;
004777cb 4092
daa3afb2 4093 if (INTEL_INFO(dev)->gen < 6)
004777cb 4094 return -ENODEV;
358733e9 4095
5c9669ce
TR		 4096 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4097
647416f9 4098 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
358733e9 4099
4fc688ce 4100 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4101 if (ret)
4102 return ret;
4103
358733e9
JB		 4104 /*
4105 * Turbo will still be enabled, but won't go above the set value.
4106 */
0a073b84 4107 if (IS_VALLEYVIEW(dev)) {
2ec3815f 4108 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 4109
03af2045
VS		 4110 hw_max = dev_priv->rps.max_freq;
4111 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 4112 } else {
4113 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 4114
4115 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4116 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4117 hw_min = (rp_state_cap >> 16) & 0xff;
4118 }
4119
b39fb297 4120 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
dd0a1aa1
JM		 4121 mutex_unlock(&dev_priv->rps.hw_lock);
4122 return -EINVAL;
0a073b84
JB		 4123 }
4124
b39fb297 4125 dev_priv->rps.max_freq_softlimit = val;
dd0a1aa1
JM		 4126
4127 if (IS_VALLEYVIEW(dev))
4128 valleyview_set_rps(dev, val);
4129 else
4130 gen6_set_rps(dev, val);
4131
4fc688ce 4132 mutex_unlock(&dev_priv->rps.hw_lock);
358733e9 4133
647416f9 4134 return 0;
358733e9
JB		 4135}
4136
647416f9
KC		 4137DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4138 i915_max_freq_get, i915_max_freq_set,
3a3b4f98 4139 "%llu\n");
358733e9 4140
647416f9
KC		 4141static int
4142i915_min_freq_get(void *data, u64 *val)
1523c310 4143{
647416f9 4144 struct drm_device *dev = data;
e277a1f8 4145 struct drm_i915_private *dev_priv = dev->dev_private;
647416f9 4146 int ret;
004777cb 4147
daa3afb2 4148 if (INTEL_INFO(dev)->gen < 6)
004777cb
DV		 4149 return -ENODEV;
4150
5c9669ce
TR		 4151 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4152
4fc688ce 4153 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4154 if (ret)
4155 return ret;
1523c310 4156
0a073b84 4157 if (IS_VALLEYVIEW(dev))
b39fb297 4158 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
0a073b84 4159 else
b39fb297 4160 *val = dev_priv->rps.min_freq_softlimit * GT_FREQUENCY_MULTIPLIER;
4fc688ce 4161 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4162
647416f9 4163 return 0;
1523c310
JB		 4164}
4165
647416f9
KC		 4166static int
4167i915_min_freq_set(void *data, u64 val)
1523c310 4168{
647416f9 4169 struct drm_device *dev = data;
1523c310 4170 struct drm_i915_private *dev_priv = dev->dev_private;
dd0a1aa1 4171 u32 rp_state_cap, hw_max, hw_min;
647416f9 4172 int ret;
004777cb 4173
daa3afb2 4174 if (INTEL_INFO(dev)->gen < 6)
004777cb 4175 return -ENODEV;
1523c310 4176
5c9669ce
TR		 4177 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4178
647416f9 4179 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
1523c310 4180
4fc688ce 4181 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
004777cb
DV		 4182 if (ret)
4183 return ret;
4184
1523c310
JB		 4185 /*
4186 * Turbo will still be enabled, but won't go below the set value.
4187 */
0a073b84 4188 if (IS_VALLEYVIEW(dev)) {
2ec3815f 4189 val = vlv_freq_opcode(dev_priv, val);
dd0a1aa1 4190
03af2045
VS		 4191 hw_max = dev_priv->rps.max_freq;
4192 hw_min = dev_priv->rps.min_freq;
0a073b84
JB		 4193 } else {
4194 do_div(val, GT_FREQUENCY_MULTIPLIER);
dd0a1aa1
JM		 4195
4196 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
b39fb297 4197 hw_max = dev_priv->rps.max_freq;
dd0a1aa1
JM		 4198 hw_min = (rp_state_cap >> 16) & 0xff;
4199 }
4200
b39fb297 4201 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
dd0a1aa1
JM		 4202 mutex_unlock(&dev_priv->rps.hw_lock);
4203 return -EINVAL;
0a073b84 4204 }
dd0a1aa1 4205
b39fb297 4206 dev_priv->rps.min_freq_softlimit = val;
dd0a1aa1
JM		 4207
4208 if (IS_VALLEYVIEW(dev))
4209 valleyview_set_rps(dev, val);
4210 else
4211 gen6_set_rps(dev, val);
4212
4fc688ce 4213 mutex_unlock(&dev_priv->rps.hw_lock);
1523c310 4214
647416f9 4215 return 0;
1523c310
JB		 4216}
4217
647416f9
KC		 4218DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4219 i915_min_freq_get, i915_min_freq_set,
3a3b4f98 4220 "%llu\n");
1523c310 4221
647416f9
KC		 4222static int
4223i915_cache_sharing_get(void *data, u64 *val)
07b7ddd9 4224{
647416f9 4225 struct drm_device *dev = data;
e277a1f8 4226 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4227 u32 snpcr;
647416f9 4228 int ret;
07b7ddd9 4229
004777cb
DV		 4230 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4231 return -ENODEV;
4232
22bcfc6a
DV		 4233 ret = mutex_lock_interruptible(&dev->struct_mutex);
4234 if (ret)
4235 return ret;
c8c8fb33 4236 intel_runtime_pm_get(dev_priv);
22bcfc6a 4237
07b7ddd9 4238 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
c8c8fb33
PZ		 4239
4240 intel_runtime_pm_put(dev_priv);
07b7ddd9
JB		 4241 mutex_unlock(&dev_priv->dev->struct_mutex);
4242
647416f9 4243 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
07b7ddd9 4244
647416f9 4245 return 0;
07b7ddd9
JB		 4246}
4247
647416f9
KC		 4248static int
4249i915_cache_sharing_set(void *data, u64 val)
07b7ddd9 4250{
647416f9 4251 struct drm_device *dev = data;
07b7ddd9 4252 struct drm_i915_private *dev_priv = dev->dev_private;
07b7ddd9 4253 u32 snpcr;
07b7ddd9 4254
004777cb
DV		 4255 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4256 return -ENODEV;
4257
647416f9 4258 if (val > 3)
07b7ddd9
JB		 4259 return -EINVAL;
4260
c8c8fb33 4261 intel_runtime_pm_get(dev_priv);
647416f9 4262 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
07b7ddd9
JB		 4263
4264 /* Update the cache sharing policy here as well */
4265 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4266 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4267 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4268 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4269
c8c8fb33 4270 intel_runtime_pm_put(dev_priv);
647416f9 4271 return 0;
07b7ddd9
JB		 4272}
4273
647416f9
KC		 4274DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4275 i915_cache_sharing_get, i915_cache_sharing_set,
4276 "%llu\n");
07b7ddd9 4277
6d794d42
BW		 4278static int i915_forcewake_open(struct inode *inode, struct file *file)
4279{
4280 struct drm_device *dev = inode->i_private;
4281 struct drm_i915_private *dev_priv = dev->dev_private;
6d794d42 4282
075edca4 4283 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4284 return 0;
4285
c8d9a590 4286 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4287
4288 return 0;
4289}
4290
c43b5634 4291static int i915_forcewake_release(struct inode *inode, struct file *file)
6d794d42
BW		 4292{
4293 struct drm_device *dev = inode->i_private;
4294 struct drm_i915_private *dev_priv = dev->dev_private;
4295
075edca4 4296 if (INTEL_INFO(dev)->gen < 6)
6d794d42
BW		 4297 return 0;
4298
c8d9a590 4299 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6d794d42
BW		 4300
4301 return 0;
4302}
4303
4304static const struct file_operations i915_forcewake_fops = {
4305 .owner = THIS_MODULE,
4306 .open = i915_forcewake_open,
4307 .release = i915_forcewake_release,
4308};
4309
4310static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4311{
4312 struct drm_device *dev = minor->dev;
4313 struct dentry *ent;
4314
4315 ent = debugfs_create_file("i915_forcewake_user",
8eb57294 4316 S_IRUSR,
6d794d42
BW		 4317 root, dev,
4318 &i915_forcewake_fops);
f3c5fe97
WY		 4319 if (!ent)
4320 return -ENOMEM;
6d794d42 4321
8eb57294 4322 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
6d794d42
BW		 4323}
4324
6a9c308d
DV		 4325static int i915_debugfs_create(struct dentry *root,
4326 struct drm_minor *minor,
4327 const char *name,
4328 const struct file_operations *fops)
07b7ddd9
JB		 4329{
4330 struct drm_device *dev = minor->dev;
4331 struct dentry *ent;
4332
6a9c308d 4333 ent = debugfs_create_file(name,
07b7ddd9
JB		 4334 S_IRUGO | S_IWUSR,
4335 root, dev,
6a9c308d 4336 fops);
f3c5fe97
WY		 4337 if (!ent)
4338 return -ENOMEM;
07b7ddd9 4339
6a9c308d 4340 return drm_add_fake_info_node(minor, ent, fops);
07b7ddd9
JB		 4341}
4342
06c5bf8c 4343static const struct drm_info_list i915_debugfs_list[] = {
311bd68e 4344 {"i915_capabilities", i915_capabilities, 0},
73aa808f 4345 {"i915_gem_objects", i915_gem_object_info, 0},
08c18323 4346 {"i915_gem_gtt", i915_gem_gtt_info, 0},
1b50247a 4347 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
433e12f7 4348 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
433e12f7 4349 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
6d2b8885 4350 {"i915_gem_stolen", i915_gem_stolen_list_info },
4e5359cd 4351 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
2017263e
BG		 4352 {"i915_gem_request", i915_gem_request_info, 0},
4353 {"i915_gem_seqno", i915_gem_seqno_info, 0},
a6172a80 4354 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
2017263e 4355 {"i915_gem_interrupt", i915_interrupt_info, 0},
1ec14ad3
CW		 4356 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
4357 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
4358 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
9010ebfd 4359 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
adb4bd12 4360 {"i915_frequency_info", i915_frequency_info, 0},
f97108d1 4361 {"i915_drpc_info", i915_drpc_info, 0},
7648fa99 4362 {"i915_emon_status", i915_emon_status, 0},
23b2f8bb 4363 {"i915_ring_freq_table", i915_ring_freq_table, 0},
b5e50c3f 4364 {"i915_fbc_status", i915_fbc_status, 0},
92d44621 4365 {"i915_ips_status", i915_ips_status, 0},
4a9bef37 4366 {"i915_sr_status", i915_sr_status, 0},
44834a67 4367 {"i915_opregion", i915_opregion, 0},
37811fcc 4368 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
e76d3630 4369 {"i915_context_status", i915_context_status, 0},
c0ab1ae9 4370 {"i915_dump_lrc", i915_dump_lrc, 0},
4ba70e44 4371 {"i915_execlists", i915_execlists, 0},
6d794d42 4372 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
ea16a3cd 4373 {"i915_swizzle_info", i915_swizzle_info, 0},
3cf17fc5 4374 {"i915_ppgtt_info", i915_ppgtt_info, 0},
63573eb7 4375 {"i915_llc", i915_llc, 0},
e91fd8c6 4376 {"i915_edp_psr_status", i915_edp_psr_status, 0},
d2e216d0 4377 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
ec013e7f 4378 {"i915_energy_uJ", i915_energy_uJ, 0},
371db66a 4379 {"i915_pc8_status", i915_pc8_status, 0},
1da51581 4380 {"i915_power_domain_info", i915_power_domain_info, 0},
53f5e3ca 4381 {"i915_display_info", i915_display_info, 0},
e04934cf 4382 {"i915_semaphore_status", i915_semaphore_status, 0},
728e29d7 4383 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
11bed958 4384 {"i915_dp_mst_info", i915_dp_mst_info, 0},
1ed1ef9d 4385 {"i915_wa_registers", i915_wa_registers, 0},
c5511e44 4386 {"i915_ddb_info", i915_ddb_info, 0},
2017263e 4387};
27c202ad 4388#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
2017263e 4389
06c5bf8c 4390static const struct i915_debugfs_files {
34b9674c
DV		 4391 const char *name;
4392 const struct file_operations *fops;
4393} i915_debugfs_files[] = {
4394 {"i915_wedged", &i915_wedged_fops},
4395 {"i915_max_freq", &i915_max_freq_fops},
4396 {"i915_min_freq", &i915_min_freq_fops},
4397 {"i915_cache_sharing", &i915_cache_sharing_fops},
4398 {"i915_ring_stop", &i915_ring_stop_fops},
094f9a54
CW		 4399 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
4400 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
34b9674c
DV		 4401 {"i915_gem_drop_caches", &i915_drop_caches_fops},
4402 {"i915_error_state", &i915_error_state_fops},
4403 {"i915_next_seqno", &i915_next_seqno_fops},
bd9db02f 4404 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
369a1342
VS		 4405 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
4406 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
4407 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
da46f936 4408 {"i915_fbc_false_color", &i915_fbc_fc_fops},
34b9674c
DV		 4409};
4410
07144428
DL		 4411void intel_display_crc_init(struct drm_device *dev)
4412{
4413 struct drm_i915_private *dev_priv = dev->dev_private;
b378360e 4414 enum pipe pipe;
07144428 4415
055e393f 4416 for_each_pipe(dev_priv, pipe) {
b378360e 4417 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
07144428 4418
d538bbdf
DL		 4419 pipe_crc->opened = false;
4420 spin_lock_init(&pipe_crc->lock);
07144428
DL		 4421 init_waitqueue_head(&pipe_crc->wq);
4422 }
4423}
4424
27c202ad 4425int i915_debugfs_init(struct drm_minor *minor)
2017263e 4426{
34b9674c 4427 int ret, i;
f3cd474b 4428
6d794d42 4429 ret = i915_forcewake_create(minor->debugfs_root, minor);
358733e9
JB		 4430 if (ret)
4431 return ret;
6a9c308d 4432
07144428
DL		 4433 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
4434 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
4435 if (ret)
4436 return ret;
4437 }
4438
34b9674c
DV		 4439 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4440 ret = i915_debugfs_create(minor->debugfs_root, minor,
4441 i915_debugfs_files[i].name,
4442 i915_debugfs_files[i].fops);
4443 if (ret)
4444 return ret;
4445 }
40633219 4446
27c202ad
BG		 4447 return drm_debugfs_create_files(i915_debugfs_list,
4448 I915_DEBUGFS_ENTRIES,
2017263e
BG		 4449 minor->debugfs_root, minor);
4450}
4451
27c202ad 4452void i915_debugfs_cleanup(struct drm_minor *minor)
2017263e 4453{
34b9674c
DV		 4454 int i;
4455
27c202ad
BG		 4456 drm_debugfs_remove_files(i915_debugfs_list,
4457 I915_DEBUGFS_ENTRIES, minor);
07144428 4458
6d794d42
BW		 4459 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
4460 1, minor);
07144428 4461
e309a997 4462 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
07144428
DL		 4463 struct drm_info_list *info_list =
4464 (struct drm_info_list *)&i915_pipe_crc_data[i];
4465
4466 drm_debugfs_remove_files(info_list, 1, minor);
4467 }
4468
34b9674c
DV		 4469 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
4470 struct drm_info_list *info_list =
4471 (struct drm_info_list *) i915_debugfs_files[i].fops;
4472
4473 drm_debugfs_remove_files(info_list, 1, minor);
4474 }
2017263e 4475}
Michael's Linux tree.