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Merge branch 'drm-next-5.1' of git://people.freedesktop.org/~agd5f/linux into drm...
[thirdparty/kernel/stable.git] / drivers / gpu / drm / i915 / i915_drv.c
CommitLineData
1da177e4
LT		 1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4 29
e5747e3a 30#include <linux/acpi.h>
0673ad47
CW		 31#include <linux/device.h>
32#include <linux/oom.h>
e0cd3608 33#include <linux/module.h>
0673ad47
CW		 34#include <linux/pci.h>
35#include <linux/pm.h>
d6102977 36#include <linux/pm_runtime.h>
0673ad47
CW		 37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vgaarb.h>
704ab614 40#include <linux/vga_switcheroo.h>
0673ad47
CW		 41#include <linux/vt.h>
42#include <acpi/video.h>
43
fcd70cd3 44#include <drm/drm_probe_helper.h>
a667fb40 45#include <drm/drm_atomic_helper.h>
0673ad47
CW		 46#include <drm/i915_drm.h>
47
48#include "i915_drv.h"
49#include "i915_trace.h"
b46a33e2 50#include "i915_pmu.h"
9f58892e 51#include "i915_reset.h"
a446ae2c 52#include "i915_query.h"
0673ad47
CW		 53#include "i915_vgpu.h"
54#include "intel_drv.h"
5464cd65 55#include "intel_uc.h"
094304be 56#include "intel_workarounds.h"
79e53945 57
112b715e
KH		 58static struct drm_driver driver;
59
fae919f0 60#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
0673ad47
CW		 61static unsigned int i915_load_fail_count;
62
63bool __i915_inject_load_failure(const char *func, int line)
64{
4f044a88 65 if (i915_load_fail_count >= i915_modparams.inject_load_failure)
0673ad47
CW		 66 return false;
67
4f044a88 68 if (++i915_load_fail_count == i915_modparams.inject_load_failure) {
0673ad47 69 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
4f044a88 70 i915_modparams.inject_load_failure, func, line);
cf68f0c3 71 i915_modparams.inject_load_failure = 0;
0673ad47
CW		 72 return true;
73 }
74
75 return false;
76}
51c18bf7
CW		 77
78bool i915_error_injected(void)
79{
80 return i915_load_fail_count && !i915_modparams.inject_load_failure;
81}
82
fae919f0 83#endif
0673ad47
CW		 84
85#define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
86#define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
87 "providing the dmesg log by booting with drm.debug=0xf"
88
89void
90__i915_printk(struct drm_i915_private *dev_priv, const char *level,
91 const char *fmt, ...)
92{
93 static bool shown_bug_once;
c49d13ee 94 struct device *kdev = dev_priv->drm.dev;
0673ad47
CW		 95 bool is_error = level[1] <= KERN_ERR[1];
96 bool is_debug = level[1] == KERN_DEBUG[1];
97 struct va_format vaf;
98 va_list args;
99
100 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
101 return;
102
103 va_start(args, fmt);
104
105 vaf.fmt = fmt;
106 vaf.va = &args;
107
8cff1f4a
CW		 108 if (is_error)
109 dev_printk(level, kdev, "%pV", &vaf);
110 else
111 dev_printk(level, kdev, "[" DRM_NAME ":%ps] %pV",
112 __builtin_return_address(0), &vaf);
113
114 va_end(args);
0673ad47
CW		 115
116 if (is_error && !shown_bug_once) {
4e8507ba
CW		 117 /*
118 * Ask the user to file a bug report for the error, except
119 * if they may have caused the bug by fiddling with unsafe
120 * module parameters.
121 */
122 if (!test_taint(TAINT_USER))
123 dev_notice(kdev, "%s", FDO_BUG_MSG);
0673ad47
CW		 124 shown_bug_once = true;
125 }
0673ad47
CW		 126}
127
da6c10c2
JN		 128/* Map PCH device id to PCH type, or PCH_NONE if unknown. */
129static enum intel_pch
130intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
131{
132 switch (id) {
133 case INTEL_PCH_IBX_DEVICE_ID_TYPE:
134 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
cf819eff 135 WARN_ON(!IS_GEN(dev_priv, 5));
da6c10c2
JN		 136 return PCH_IBX;
137 case INTEL_PCH_CPT_DEVICE_ID_TYPE:
138 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
cf819eff 139 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
da6c10c2
JN		 140 return PCH_CPT;
141 case INTEL_PCH_PPT_DEVICE_ID_TYPE:
142 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
cf819eff 143 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
da6c10c2
JN		 144 /* PantherPoint is CPT compatible */
145 return PCH_CPT;
146 case INTEL_PCH_LPT_DEVICE_ID_TYPE:
147 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
148 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
149 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
150 return PCH_LPT;
151 case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
152 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
153 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
154 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
155 return PCH_LPT;
156 case INTEL_PCH_WPT_DEVICE_ID_TYPE:
157 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
158 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
159 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
160 /* WildcatPoint is LPT compatible */
161 return PCH_LPT;
162 case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
163 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
164 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
165 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
166 /* WildcatPoint is LPT compatible */
167 return PCH_LPT;
168 case INTEL_PCH_SPT_DEVICE_ID_TYPE:
169 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
170 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
171 return PCH_SPT;
172 case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
173 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
174 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
175 return PCH_SPT;
176 case INTEL_PCH_KBP_DEVICE_ID_TYPE:
177 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
178 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
179 !IS_COFFEELAKE(dev_priv));
180 return PCH_KBP;
181 case INTEL_PCH_CNP_DEVICE_ID_TYPE:
182 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
183 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
184 return PCH_CNP;
185 case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
186 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
187 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
188 return PCH_CNP;
189 case INTEL_PCH_ICP_DEVICE_ID_TYPE:
190 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
191 WARN_ON(!IS_ICELAKE(dev_priv));
192 return PCH_ICP;
193 default:
194 return PCH_NONE;
195 }
196}
0673ad47 197
435ad2c0
JN		 198static bool intel_is_virt_pch(unsigned short id,
199 unsigned short svendor, unsigned short sdevice)
200{
201 return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
202 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
203 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
204 svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
205 sdevice == PCI_SUBDEVICE_ID_QEMU));
206}
207
40ace64b
JN		 208static unsigned short
209intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
0673ad47 210{
40ace64b 211 unsigned short id = 0;
0673ad47
CW		 212
213 /*
214 * In a virtualized passthrough environment we can be in a
215 * setup where the ISA bridge is not able to be passed through.
216 * In this case, a south bridge can be emulated and we have to
217 * make an educated guess as to which PCH is really there.
218 */
219
cf819eff 220 if (IS_GEN(dev_priv, 5))
40ace64b 221 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
cf819eff 222 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
40ace64b
JN		 223 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
224 else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
225 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
226 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
227 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
228 else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
229 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
230 else if (IS_COFFEELAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
231 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
f17ca501
AS		 232 else if (IS_ICELAKE(dev_priv))
233 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
40ace64b
JN		 234
235 if (id)
236 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
237 else
238 DRM_DEBUG_KMS("Assuming no PCH\n");
239
240 return id;
0673ad47
CW		 241}
242
da5f53bf 243static void intel_detect_pch(struct drm_i915_private *dev_priv)
0673ad47 244{
0673ad47
CW		 245 struct pci_dev *pch = NULL;
246
0673ad47
CW		 247 /*
248 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
249 * make graphics device passthrough work easy for VMM, that only
250 * need to expose ISA bridge to let driver know the real hardware
251 * underneath. This is a requirement from virtualization team.
252 *
253 * In some virtualized environments (e.g. XEN), there is irrelevant
254 * ISA bridge in the system. To work reliably, we should scan trhough
255 * all the ISA bridge devices and check for the first match, instead
256 * of only checking the first one.
257 */
258 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
d67c0ac1 259 unsigned short id;
da6c10c2 260 enum intel_pch pch_type;
d67c0ac1
JN		 261
262 if (pch->vendor != PCI_VENDOR_ID_INTEL)
263 continue;
264
265 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
266
da6c10c2
JN		 267 pch_type = intel_pch_type(dev_priv, id);
268 if (pch_type != PCH_NONE) {
269 dev_priv->pch_type = pch_type;
40ace64b
JN		 270 dev_priv->pch_id = id;
271 break;
435ad2c0 272 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
40ace64b
JN		 273 pch->subsystem_device)) {
274 id = intel_virt_detect_pch(dev_priv);
85b17e6e
JN		 275 pch_type = intel_pch_type(dev_priv, id);
276
277 /* Sanity check virtual PCH id */
278 if (WARN_ON(id && pch_type == PCH_NONE))
279 id = 0;
280
40ace64b
JN		 281 dev_priv->pch_type = pch_type;
282 dev_priv->pch_id = id;
283 break;
0673ad47
CW		 284 }
285 }
07ba0a82
JN		 286
287 /*
288 * Use PCH_NOP (PCH but no South Display) for PCH platforms without
289 * display.
290 */
e1bf094b 291 if (pch && !HAS_DISPLAY(dev_priv)) {
07ba0a82
JN		 292 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
293 dev_priv->pch_type = PCH_NOP;
294 dev_priv->pch_id = 0;
295 }
296
0673ad47
CW		 297 if (!pch)
298 DRM_DEBUG_KMS("No PCH found.\n");
299
300 pci_dev_put(pch);
301}
302
6a20fe7b
VS		 303static int i915_getparam_ioctl(struct drm_device *dev, void *data,
304 struct drm_file *file_priv)
0673ad47 305{
fac5e23e 306 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 307 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 308 drm_i915_getparam_t *param = data;
309 int value;
310
311 switch (param->param) {
312 case I915_PARAM_IRQ_ACTIVE:
313 case I915_PARAM_ALLOW_BATCHBUFFER:
314 case I915_PARAM_LAST_DISPATCH:
ef0f411f 315 case I915_PARAM_HAS_EXEC_CONSTANTS:
0673ad47
CW		 316 /* Reject all old ums/dri params. */
317 return -ENODEV;
318 case I915_PARAM_CHIPSET_ID:
52a05c30 319 value = pdev->device;
0673ad47
CW		 320 break;
321 case I915_PARAM_REVISION:
52a05c30 322 value = pdev->revision;
0673ad47 323 break;
0673ad47
CW		 324 case I915_PARAM_NUM_FENCES_AVAIL:
325 value = dev_priv->num_fence_regs;
326 break;
327 case I915_PARAM_HAS_OVERLAY:
328 value = dev_priv->overlay ? 1 : 0;
329 break;
0673ad47 330 case I915_PARAM_HAS_BSD:
3b3f1650 331 value = !!dev_priv->engine[VCS];
0673ad47
CW		 332 break;
333 case I915_PARAM_HAS_BLT:
3b3f1650 334 value = !!dev_priv->engine[BCS];
0673ad47
CW		 335 break;
336 case I915_PARAM_HAS_VEBOX:
3b3f1650 337 value = !!dev_priv->engine[VECS];
0673ad47
CW		 338 break;
339 case I915_PARAM_HAS_BSD2:
3b3f1650 340 value = !!dev_priv->engine[VCS2];
0673ad47 341 break;
0673ad47 342 case I915_PARAM_HAS_LLC:
16162470 343 value = HAS_LLC(dev_priv);
0673ad47
CW		 344 break;
345 case I915_PARAM_HAS_WT:
16162470 346 value = HAS_WT(dev_priv);
0673ad47
CW		 347 break;
348 case I915_PARAM_HAS_ALIASING_PPGTT:
4bdafb9d 349 value = min_t(int, INTEL_PPGTT(dev_priv), I915_GEM_PPGTT_FULL);
0673ad47
CW		 350 break;
351 case I915_PARAM_HAS_SEMAPHORES:
6faf5916 352 value = 0;
0673ad47 353 break;
0673ad47
CW		 354 case I915_PARAM_HAS_SECURE_BATCHES:
355 value = capable(CAP_SYS_ADMIN);
356 break;
0673ad47
CW		 357 case I915_PARAM_CMD_PARSER_VERSION:
358 value = i915_cmd_parser_get_version(dev_priv);
359 break;
0673ad47 360 case I915_PARAM_SUBSLICE_TOTAL:
0258404f 361 value = sseu_subslice_total(&RUNTIME_INFO(dev_priv)->sseu);
0673ad47
CW		 362 if (!value)
363 return -ENODEV;
364 break;
365 case I915_PARAM_EU_TOTAL:
0258404f 366 value = RUNTIME_INFO(dev_priv)->sseu.eu_total;
0673ad47
CW		 367 if (!value)
368 return -ENODEV;
369 break;
370 case I915_PARAM_HAS_GPU_RESET:
4f044a88
MW		 371 value = i915_modparams.enable_hangcheck &&
372 intel_has_gpu_reset(dev_priv);
142bc7d9
MT		 373 if (value && intel_has_reset_engine(dev_priv))
374 value = 2;
0673ad47
CW		 375 break;
376 case I915_PARAM_HAS_RESOURCE_STREAMER:
08e3e21a 377 value = 0;
0673ad47 378 break;
37f501af 379 case I915_PARAM_HAS_POOLED_EU:
16162470 380 value = HAS_POOLED_EU(dev_priv);
37f501af 381 break;
382 case I915_PARAM_MIN_EU_IN_POOL:
0258404f 383 value = RUNTIME_INFO(dev_priv)->sseu.min_eu_in_pool;
37f501af 384 break;
5464cd65 385 case I915_PARAM_HUC_STATUS:
fa265275
MW		 386 value = intel_huc_check_status(&dev_priv->huc);
387 if (value < 0)
388 return value;
5464cd65 389 break;
4cc69075
CW		 390 case I915_PARAM_MMAP_GTT_VERSION:
391 /* Though we've started our numbering from 1, and so class all
392 * earlier versions as 0, in effect their value is undefined as
393 * the ioctl will report EINVAL for the unknown param!
394 */
395 value = i915_gem_mmap_gtt_version();
396 break;
0de9136d 397 case I915_PARAM_HAS_SCHEDULER:
3fed1808 398 value = dev_priv->caps.scheduler;
0de9136d 399 break;
beecec90 400
16162470
DW		 401 case I915_PARAM_MMAP_VERSION:
402 /* Remember to bump this if the version changes! */
403 case I915_PARAM_HAS_GEM:
404 case I915_PARAM_HAS_PAGEFLIPPING:
405 case I915_PARAM_HAS_EXECBUF2: /* depends on GEM */
406 case I915_PARAM_HAS_RELAXED_FENCING:
407 case I915_PARAM_HAS_COHERENT_RINGS:
408 case I915_PARAM_HAS_RELAXED_DELTA:
409 case I915_PARAM_HAS_GEN7_SOL_RESET:
410 case I915_PARAM_HAS_WAIT_TIMEOUT:
411 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
412 case I915_PARAM_HAS_PINNED_BATCHES:
413 case I915_PARAM_HAS_EXEC_NO_RELOC:
414 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
415 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
416 case I915_PARAM_HAS_EXEC_SOFTPIN:
77ae9957 417 case I915_PARAM_HAS_EXEC_ASYNC:
fec0445c 418 case I915_PARAM_HAS_EXEC_FENCE:
b0fd47ad 419 case I915_PARAM_HAS_EXEC_CAPTURE:
1a71cf2f 420 case I915_PARAM_HAS_EXEC_BATCH_FIRST:
cf6e7bac 421 case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
16162470
DW		 422 /* For the time being all of these are always true;
423 * if some supported hardware does not have one of these
424 * features this value needs to be provided from
425 * INTEL_INFO(), a feature macro, or similar.
426 */
427 value = 1;
428 break;
d2b4b979
CW		 429 case I915_PARAM_HAS_CONTEXT_ISOLATION:
430 value = intel_engines_has_context_isolation(dev_priv);
431 break;
7fed555c 432 case I915_PARAM_SLICE_MASK:
0258404f 433 value = RUNTIME_INFO(dev_priv)->sseu.slice_mask;
7fed555c
RB		 434 if (!value)
435 return -ENODEV;
436 break;
f5320233 437 case I915_PARAM_SUBSLICE_MASK:
0258404f 438 value = RUNTIME_INFO(dev_priv)->sseu.subslice_mask[0];
f5320233
RB		 439 if (!value)
440 return -ENODEV;
441 break;
dab91783 442 case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
0258404f 443 value = 1000 * RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz;
dab91783 444 break;
900ccf30
CW		 445 case I915_PARAM_MMAP_GTT_COHERENT:
446 value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
447 break;
0673ad47
CW		 448 default:
449 DRM_DEBUG("Unknown parameter %d\n", param->param);
450 return -EINVAL;
451 }
452
dda33009 453 if (put_user(value, param->value))
0673ad47 454 return -EFAULT;
0673ad47
CW		 455
456 return 0;
457}
458
da5f53bf 459static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
0673ad47 460{
57b29646
SK		 461 int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
462
463 dev_priv->bridge_dev =
464 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
0673ad47
CW		 465 if (!dev_priv->bridge_dev) {
466 DRM_ERROR("bridge device not found\n");
467 return -1;
468 }
469 return 0;
470}
471
472/* Allocate space for the MCH regs if needed, return nonzero on error */
473static int
da5f53bf 474intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
0673ad47 475{
514e1d64 476 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 477 u32 temp_lo, temp_hi = 0;
478 u64 mchbar_addr;
479 int ret;
480
514e1d64 481 if (INTEL_GEN(dev_priv) >= 4)
0673ad47
CW		 482 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
483 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
484 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
485
486 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
487#ifdef CONFIG_PNP
488 if (mchbar_addr &&
489 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
490 return 0;
491#endif
492
493 /* Get some space for it */
494 dev_priv->mch_res.name = "i915 MCHBAR";
495 dev_priv->mch_res.flags = IORESOURCE_MEM;
496 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
497 &dev_priv->mch_res,
498 MCHBAR_SIZE, MCHBAR_SIZE,
499 PCIBIOS_MIN_MEM,
500 0, pcibios_align_resource,
501 dev_priv->bridge_dev);
502 if (ret) {
503 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
504 dev_priv->mch_res.start = 0;
505 return ret;
506 }
507
514e1d64 508 if (INTEL_GEN(dev_priv) >= 4)
0673ad47
CW		 509 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
510 upper_32_bits(dev_priv->mch_res.start));
511
512 pci_write_config_dword(dev_priv->bridge_dev, reg,
513 lower_32_bits(dev_priv->mch_res.start));
514 return 0;
515}
516
517/* Setup MCHBAR if possible, return true if we should disable it again */
518static void
da5f53bf 519intel_setup_mchbar(struct drm_i915_private *dev_priv)
0673ad47 520{
514e1d64 521 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 522 u32 temp;
523 bool enabled;
524
920a14b2 525 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
0673ad47
CW		 526 return;
527
528 dev_priv->mchbar_need_disable = false;
529
50a0bc90 530 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 531 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
532 enabled = !!(temp & DEVEN_MCHBAR_EN);
533 } else {
534 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
535 enabled = temp & 1;
536 }
537
538 /* If it's already enabled, don't have to do anything */
539 if (enabled)
540 return;
541
da5f53bf 542 if (intel_alloc_mchbar_resource(dev_priv))
0673ad47
CW		 543 return;
544
545 dev_priv->mchbar_need_disable = true;
546
547 /* Space is allocated or reserved, so enable it. */
50a0bc90 548 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 549 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
550 temp | DEVEN_MCHBAR_EN);
551 } else {
552 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
553 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
554 }
555}
556
557static void
da5f53bf 558intel_teardown_mchbar(struct drm_i915_private *dev_priv)
0673ad47 559{
514e1d64 560 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
0673ad47
CW		 561
562 if (dev_priv->mchbar_need_disable) {
50a0bc90 563 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
0673ad47
CW		 564 u32 deven_val;
565
566 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
567 &deven_val);
568 deven_val &= ~DEVEN_MCHBAR_EN;
569 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
570 deven_val);
571 } else {
572 u32 mchbar_val;
573
574 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
575 &mchbar_val);
576 mchbar_val &= ~1;
577 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
578 mchbar_val);
579 }
580 }
581
582 if (dev_priv->mch_res.start)
583 release_resource(&dev_priv->mch_res);
584}
585
586/* true = enable decode, false = disable decoder */
587static unsigned int i915_vga_set_decode(void *cookie, bool state)
588{
da5f53bf 589 struct drm_i915_private *dev_priv = cookie;
0673ad47 590
da5f53bf 591 intel_modeset_vga_set_state(dev_priv, state);
0673ad47
CW		 592 if (state)
593 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
594 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
595 else
596 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
597}
598
7f26cb88
TU		 599static int i915_resume_switcheroo(struct drm_device *dev);
600static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
601
0673ad47
CW		 602static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
603{
604 struct drm_device *dev = pci_get_drvdata(pdev);
605 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
606
607 if (state == VGA_SWITCHEROO_ON) {
608 pr_info("switched on\n");
609 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
610 /* i915 resume handler doesn't set to D0 */
52a05c30 611 pci_set_power_state(pdev, PCI_D0);
0673ad47
CW		 612 i915_resume_switcheroo(dev);
613 dev->switch_power_state = DRM_SWITCH_POWER_ON;
614 } else {
615 pr_info("switched off\n");
616 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
617 i915_suspend_switcheroo(dev, pmm);
618 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
619 }
620}
621
622static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
623{
624 struct drm_device *dev = pci_get_drvdata(pdev);
625
626 /*
627 * FIXME: open_count is protected by drm_global_mutex but that would lead to
628 * locking inversion with the driver load path. And the access here is
629 * completely racy anyway. So don't bother with locking for now.
630 */
631 return dev->open_count == 0;
632}
633
634static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
635 .set_gpu_state = i915_switcheroo_set_state,
636 .reprobe = NULL,
637 .can_switch = i915_switcheroo_can_switch,
638};
639
0673ad47
CW		 640static int i915_load_modeset_init(struct drm_device *dev)
641{
fac5e23e 642 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 643 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 644 int ret;
645
646 if (i915_inject_load_failure())
647 return -ENODEV;
648
e1bf094b 649 if (HAS_DISPLAY(dev_priv)) {
8d3bf1a3
JRS		 650 ret = drm_vblank_init(&dev_priv->drm,
651 INTEL_INFO(dev_priv)->num_pipes);
652 if (ret)
653 goto out;
654 }
655
66578857 656 intel_bios_init(dev_priv);
0673ad47
CW		 657
658 /* If we have > 1 VGA cards, then we need to arbitrate access
659 * to the common VGA resources.
660 *
661 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
662 * then we do not take part in VGA arbitration and the
663 * vga_client_register() fails with -ENODEV.
664 */
da5f53bf 665 ret = vga_client_register(pdev, dev_priv, NULL, i915_vga_set_decode);
0673ad47
CW		 666 if (ret && ret != -ENODEV)
667 goto out;
668
669 intel_register_dsm_handler();
670
52a05c30 671 ret = vga_switcheroo_register_client(pdev, &i915_switcheroo_ops, false);
0673ad47
CW		 672 if (ret)
673 goto cleanup_vga_client;
674
675 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
676 intel_update_rawclk(dev_priv);
677
678 intel_power_domains_init_hw(dev_priv, false);
679
680 intel_csr_ucode_init(dev_priv);
681
682 ret = intel_irq_install(dev_priv);
683 if (ret)
684 goto cleanup_csr;
685
40196446 686 intel_setup_gmbus(dev_priv);
0673ad47
CW		 687
688 /* Important: The output setup functions called by modeset_init need
689 * working irqs for e.g. gmbus and dp aux transfers. */
b079bd17
VS		 690 ret = intel_modeset_init(dev);
691 if (ret)
692 goto cleanup_irq;
0673ad47 693
bf9e8429 694 ret = i915_gem_init(dev_priv);
0673ad47 695 if (ret)
73bad7ca 696 goto cleanup_modeset;
0673ad47 697
58db08a7 698 intel_overlay_setup(dev_priv);
0673ad47 699
e1bf094b 700 if (!HAS_DISPLAY(dev_priv))
0673ad47
CW		 701 return 0;
702
703 ret = intel_fbdev_init(dev);
704 if (ret)
705 goto cleanup_gem;
706
707 /* Only enable hotplug handling once the fbdev is fully set up. */
708 intel_hpd_init(dev_priv);
709
a8147d0c
JRS		 710 intel_init_ipc(dev_priv);
711
0673ad47
CW		 712 return 0;
713
714cleanup_gem:
bf9e8429 715 if (i915_gem_suspend(dev_priv))
1c777c5d 716 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
fbbd37b3 717 i915_gem_fini(dev_priv);
73bad7ca
CW		 718cleanup_modeset:
719 intel_modeset_cleanup(dev);
0673ad47 720cleanup_irq:
0673ad47 721 drm_irq_uninstall(dev);
40196446 722 intel_teardown_gmbus(dev_priv);
0673ad47
CW		 723cleanup_csr:
724 intel_csr_ucode_fini(dev_priv);
48a287ed 725 intel_power_domains_fini_hw(dev_priv);
52a05c30 726 vga_switcheroo_unregister_client(pdev);
0673ad47 727cleanup_vga_client:
52a05c30 728 vga_client_register(pdev, NULL, NULL, NULL);
0673ad47
CW		 729out:
730 return ret;
731}
732
0673ad47
CW		 733static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
734{
735 struct apertures_struct *ap;
91c8a326 736 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 737 struct i915_ggtt *ggtt = &dev_priv->ggtt;
738 bool primary;
739 int ret;
740
741 ap = alloc_apertures(1);
742 if (!ap)
743 return -ENOMEM;
744
73ebd503 745 ap->ranges[0].base = ggtt->gmadr.start;
0673ad47
CW		 746 ap->ranges[0].size = ggtt->mappable_end;
747
748 primary =
749 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
750
44adece5 751 ret = drm_fb_helper_remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
0673ad47
CW		 752
753 kfree(ap);
754
755 return ret;
756}
0673ad47
CW		 757
758#if !defined(CONFIG_VGA_CONSOLE)
759static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
760{
761 return 0;
762}
763#elif !defined(CONFIG_DUMMY_CONSOLE)
764static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
765{
766 return -ENODEV;
767}
768#else
769static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
770{
771 int ret = 0;
772
773 DRM_INFO("Replacing VGA console driver\n");
774
775 console_lock();
776 if (con_is_bound(&vga_con))
777 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
778 if (ret == 0) {
779 ret = do_unregister_con_driver(&vga_con);
780
781 /* Ignore "already unregistered". */
782 if (ret == -ENODEV)
783 ret = 0;
784 }
785 console_unlock();
786
787 return ret;
788}
789#endif
790
0673ad47
CW		 791static void intel_init_dpio(struct drm_i915_private *dev_priv)
792{
793 /*
794 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
795 * CHV x1 PHY (DP/HDMI D)
796 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
797 */
798 if (IS_CHERRYVIEW(dev_priv)) {
799 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
800 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
801 } else if (IS_VALLEYVIEW(dev_priv)) {
802 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
803 }
804}
805
806static int i915_workqueues_init(struct drm_i915_private *dev_priv)
807{
808 /*
809 * The i915 workqueue is primarily used for batched retirement of
810 * requests (and thus managing bo) once the task has been completed
e61e0f51 811 * by the GPU. i915_retire_requests() is called directly when we
0673ad47
CW		 812 * need high-priority retirement, such as waiting for an explicit
813 * bo.
814 *
815 * It is also used for periodic low-priority events, such as
816 * idle-timers and recording error state.
817 *
818 * All tasks on the workqueue are expected to acquire the dev mutex
819 * so there is no point in running more than one instance of the
820 * workqueue at any time. Use an ordered one.
821 */
822 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
823 if (dev_priv->wq == NULL)
824 goto out_err;
825
826 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
827 if (dev_priv->hotplug.dp_wq == NULL)
828 goto out_free_wq;
829
0673ad47
CW		 830 return 0;
831
0673ad47
CW		 832out_free_wq:
833 destroy_workqueue(dev_priv->wq);
834out_err:
835 DRM_ERROR("Failed to allocate workqueues.\n");
836
837 return -ENOMEM;
838}
839
bb8f0f5a
CW		 840static void i915_engines_cleanup(struct drm_i915_private *i915)
841{
842 struct intel_engine_cs *engine;
843 enum intel_engine_id id;
844
845 for_each_engine(engine, i915, id)
846 kfree(engine);
847}
848
0673ad47
CW		 849static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
850{
0673ad47
CW		 851 destroy_workqueue(dev_priv->hotplug.dp_wq);
852 destroy_workqueue(dev_priv->wq);
853}
854
4fc7e845
PZ		 855/*
856 * We don't keep the workarounds for pre-production hardware, so we expect our
857 * driver to fail on these machines in one way or another. A little warning on
858 * dmesg may help both the user and the bug triagers.
6a7a6a98
CW		 859 *
860 * Our policy for removing pre-production workarounds is to keep the
861 * current gen workarounds as a guide to the bring-up of the next gen
862 * (workarounds have a habit of persisting!). Anything older than that
863 * should be removed along with the complications they introduce.
4fc7e845
PZ		 864 */
865static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
866{
248a124d
CW		 867 bool pre = false;
868
869 pre |= IS_HSW_EARLY_SDV(dev_priv);
870 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
0102ba1f 871 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
1aca96cc 872 pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
248a124d 873
7c5ff4a2 874 if (pre) {
4fc7e845
PZ		 875 DRM_ERROR("This is a pre-production stepping. "
876 "It may not be fully functional.\n");
7c5ff4a2
CW		 877 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
878 }
4fc7e845
PZ		 879}
880
0673ad47
CW		 881/**
882 * i915_driver_init_early - setup state not requiring device access
883 * @dev_priv: device private
884 *
885 * Initialize everything that is a "SW-only" state, that is state not
886 * requiring accessing the device or exposing the driver via kernel internal
887 * or userspace interfaces. Example steps belonging here: lock initialization,
888 * system memory allocation, setting up device specific attributes and
889 * function hooks not requiring accessing the device.
890 */
55ac5a16 891static int i915_driver_init_early(struct drm_i915_private *dev_priv)
0673ad47 892{
0673ad47
CW		 893 int ret = 0;
894
895 if (i915_inject_load_failure())
896 return -ENODEV;
897
0673ad47
CW		 898 spin_lock_init(&dev_priv->irq_lock);
899 spin_lock_init(&dev_priv->gpu_error.lock);
900 mutex_init(&dev_priv->backlight_lock);
901 spin_lock_init(&dev_priv->uncore.lock);
317eaa95 902
0673ad47 903 mutex_init(&dev_priv->sb_lock);
0673ad47
CW		 904 mutex_init(&dev_priv->av_mutex);
905 mutex_init(&dev_priv->wm.wm_mutex);
906 mutex_init(&dev_priv->pps_mutex);
907
0b1de5d5 908 i915_memcpy_init_early(dev_priv);
bd780f37 909 intel_runtime_pm_init_early(dev_priv);
0b1de5d5 910
0673ad47
CW		 911 ret = i915_workqueues_init(dev_priv);
912 if (ret < 0)
bb8f0f5a 913 goto err_engines;
0673ad47 914
a0de908d
MW		 915 ret = i915_gem_init_early(dev_priv);
916 if (ret < 0)
917 goto err_workqueues;
918
0673ad47 919 /* This must be called before any calls to HAS_PCH_* */
da5f53bf 920 intel_detect_pch(dev_priv);
0673ad47 921
a0de908d
MW		 922 intel_wopcm_init_early(&dev_priv->wopcm);
923 intel_uc_init_early(dev_priv);
192aa181 924 intel_pm_setup(dev_priv);
0673ad47 925 intel_init_dpio(dev_priv);
f28ec6f4
ID		 926 ret = intel_power_domains_init(dev_priv);
927 if (ret < 0)
928 goto err_uc;
0673ad47 929 intel_irq_init(dev_priv);
3ac168a7 930 intel_hangcheck_init(dev_priv);
0673ad47
CW		 931 intel_init_display_hooks(dev_priv);
932 intel_init_clock_gating_hooks(dev_priv);
933 intel_init_audio_hooks(dev_priv);
36cdd013 934 intel_display_crc_init(dev_priv);
0673ad47 935
4fc7e845 936 intel_detect_preproduction_hw(dev_priv);
0673ad47
CW		 937
938 return 0;
939
f28ec6f4
ID		 940err_uc:
941 intel_uc_cleanup_early(dev_priv);
942 i915_gem_cleanup_early(dev_priv);
a0de908d 943err_workqueues:
0673ad47 944 i915_workqueues_cleanup(dev_priv);
bb8f0f5a
CW		 945err_engines:
946 i915_engines_cleanup(dev_priv);
0673ad47
CW		 947 return ret;
948}
949
950/**
951 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
952 * @dev_priv: device private
953 */
954static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
955{
cefcff8f 956 intel_irq_fini(dev_priv);
f28ec6f4 957 intel_power_domains_cleanup(dev_priv);
8c650aef 958 intel_uc_cleanup_early(dev_priv);
a0de908d 959 i915_gem_cleanup_early(dev_priv);
0673ad47 960 i915_workqueues_cleanup(dev_priv);
bb8f0f5a 961 i915_engines_cleanup(dev_priv);
0673ad47
CW		 962}
963
da5f53bf 964static int i915_mmio_setup(struct drm_i915_private *dev_priv)
0673ad47 965{
52a05c30 966 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 967 int mmio_bar;
968 int mmio_size;
969
cf819eff 970 mmio_bar = IS_GEN(dev_priv, 2) ? 1 : 0;
0673ad47
CW		 971 /*
972 * Before gen4, the registers and the GTT are behind different BARs.
973 * However, from gen4 onwards, the registers and the GTT are shared
974 * in the same BAR, so we want to restrict this ioremap from
975 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
976 * the register BAR remains the same size for all the earlier
977 * generations up to Ironlake.
978 */
514e1d64 979 if (INTEL_GEN(dev_priv) < 5)
0673ad47
CW		 980 mmio_size = 512 * 1024;
981 else
982 mmio_size = 2 * 1024 * 1024;
52a05c30 983 dev_priv->regs = pci_iomap(pdev, mmio_bar, mmio_size);
0673ad47
CW		 984 if (dev_priv->regs == NULL) {
985 DRM_ERROR("failed to map registers\n");
986
987 return -EIO;
988 }
989
990 /* Try to make sure MCHBAR is enabled before poking at it */
da5f53bf 991 intel_setup_mchbar(dev_priv);
0673ad47
CW		 992
993 return 0;
994}
995
da5f53bf 996static void i915_mmio_cleanup(struct drm_i915_private *dev_priv)
0673ad47 997{
52a05c30 998 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47 999
da5f53bf 1000 intel_teardown_mchbar(dev_priv);
52a05c30 1001 pci_iounmap(pdev, dev_priv->regs);
0673ad47
CW		 1002}
1003
1004/**
1005 * i915_driver_init_mmio - setup device MMIO
1006 * @dev_priv: device private
1007 *
1008 * Setup minimal device state necessary for MMIO accesses later in the
1009 * initialization sequence. The setup here should avoid any other device-wide
1010 * side effects or exposing the driver via kernel internal or user space
1011 * interfaces.
1012 */
1013static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1014{
0673ad47
CW		 1015 int ret;
1016
1017 if (i915_inject_load_failure())
1018 return -ENODEV;
1019
da5f53bf 1020 if (i915_get_bridge_dev(dev_priv))
0673ad47
CW		 1021 return -EIO;
1022
da5f53bf 1023 ret = i915_mmio_setup(dev_priv);
0673ad47 1024 if (ret < 0)
63ffbcda 1025 goto err_bridge;
0673ad47
CW		 1026
1027 intel_uncore_init(dev_priv);
63ffbcda 1028
26376a7e
OM		 1029 intel_device_info_init_mmio(dev_priv);
1030
1031 intel_uncore_prune(dev_priv);
1032
1fc556fa
SAK		 1033 intel_uc_init_mmio(dev_priv);
1034
63ffbcda
JL		 1035 ret = intel_engines_init_mmio(dev_priv);
1036 if (ret)
1037 goto err_uncore;
1038
24145517 1039 i915_gem_init_mmio(dev_priv);
0673ad47
CW		 1040
1041 return 0;
1042
63ffbcda
JL		 1043err_uncore:
1044 intel_uncore_fini(dev_priv);
c5b083a1 1045 i915_mmio_cleanup(dev_priv);
63ffbcda 1046err_bridge:
0673ad47
CW		 1047 pci_dev_put(dev_priv->bridge_dev);
1048
1049 return ret;
1050}
1051
1052/**
1053 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1054 * @dev_priv: device private
1055 */
1056static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1057{
0673ad47 1058 intel_uncore_fini(dev_priv);
da5f53bf 1059 i915_mmio_cleanup(dev_priv);
0673ad47
CW		 1060 pci_dev_put(dev_priv->bridge_dev);
1061}
1062
94b4f3ba
CW		 1063static void intel_sanitize_options(struct drm_i915_private *dev_priv)
1064{
67b7f33e 1065 intel_gvt_sanitize_options(dev_priv);
94b4f3ba
CW		 1066}
1067
5771caf8
MK		 1068static enum dram_rank skl_get_dimm_rank(u8 size, u32 rank)
1069{
1070 if (size == 0)
1071 return I915_DRAM_RANK_INVALID;
1072 if (rank == SKL_DRAM_RANK_SINGLE)
1073 return I915_DRAM_RANK_SINGLE;
1074 else if (rank == SKL_DRAM_RANK_DUAL)
1075 return I915_DRAM_RANK_DUAL;
1076
1077 return I915_DRAM_RANK_INVALID;
1078}
1079
86b59287
MK		 1080static bool
1081skl_is_16gb_dimm(enum dram_rank rank, u8 size, u8 width)
1082{
1083 if (rank == I915_DRAM_RANK_SINGLE && width == 8 && size == 16)
1084 return true;
1085 else if (rank == I915_DRAM_RANK_DUAL && width == 8 && size == 32)
1086 return true;
1087 else if (rank == SKL_DRAM_RANK_SINGLE && width == 16 && size == 8)
1088 return true;
1089 else if (rank == SKL_DRAM_RANK_DUAL && width == 16 && size == 16)
1090 return true;
1091
1092 return false;
1093}
1094
5771caf8
MK		 1095static int
1096skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
1097{
1098 u32 tmp_l, tmp_s;
1099 u32 s_val = val >> SKL_DRAM_S_SHIFT;
1100
1101 if (!val)
1102 return -EINVAL;
1103
1104 tmp_l = val & SKL_DRAM_SIZE_MASK;
1105 tmp_s = s_val & SKL_DRAM_SIZE_MASK;
1106
1107 if (tmp_l == 0 && tmp_s == 0)
1108 return -EINVAL;
1109
1110 ch->l_info.size = tmp_l;
1111 ch->s_info.size = tmp_s;
1112
1113 tmp_l = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1114 tmp_s = (s_val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
1115 ch->l_info.width = (1 << tmp_l) * 8;
1116 ch->s_info.width = (1 << tmp_s) * 8;
1117
1118 tmp_l = val & SKL_DRAM_RANK_MASK;
1119 tmp_s = s_val & SKL_DRAM_RANK_MASK;
1120 ch->l_info.rank = skl_get_dimm_rank(ch->l_info.size, tmp_l);
1121 ch->s_info.rank = skl_get_dimm_rank(ch->s_info.size, tmp_s);
1122
1123 if (ch->l_info.rank == I915_DRAM_RANK_DUAL ||
1124 ch->s_info.rank == I915_DRAM_RANK_DUAL)
1125 ch->rank = I915_DRAM_RANK_DUAL;
1126 else if (ch->l_info.rank == I915_DRAM_RANK_SINGLE &&
1127 ch->s_info.rank == I915_DRAM_RANK_SINGLE)
1128 ch->rank = I915_DRAM_RANK_DUAL;
1129 else
1130 ch->rank = I915_DRAM_RANK_SINGLE;
1131
86b59287
MK		 1132 ch->is_16gb_dimm = skl_is_16gb_dimm(ch->l_info.rank, ch->l_info.size,
1133 ch->l_info.width) ||
1134 skl_is_16gb_dimm(ch->s_info.rank, ch->s_info.size,
1135 ch->s_info.width);
1136
5771caf8
MK		 1137 DRM_DEBUG_KMS("(size:width:rank) L(%dGB:X%d:%s) S(%dGB:X%d:%s)\n",
1138 ch->l_info.size, ch->l_info.width,
1139 ch->l_info.rank ? "dual" : "single",
1140 ch->s_info.size, ch->s_info.width,
1141 ch->s_info.rank ? "dual" : "single");
1142
1143 return 0;
1144}
1145
8a6c5447
MK		 1146static bool
1147intel_is_dram_symmetric(u32 val_ch0, u32 val_ch1,
1148 struct dram_channel_info *ch0)
1149{
1150 return (val_ch0 == val_ch1 &&
1151 (ch0->s_info.size == 0 ||
1152 (ch0->l_info.size == ch0->s_info.size &&
1153 ch0->l_info.width == ch0->s_info.width &&
1154 ch0->l_info.rank == ch0->s_info.rank)));
1155}
1156
5771caf8
MK		 1157static int
1158skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
1159{
1160 struct dram_info *dram_info = &dev_priv->dram_info;
1161 struct dram_channel_info ch0, ch1;
8a6c5447 1162 u32 val_ch0, val_ch1;
5771caf8
MK		 1163 int ret;
1164
8a6c5447
MK		 1165 val_ch0 = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
1166 ret = skl_dram_get_channel_info(&ch0, val_ch0);
5771caf8
MK		 1167 if (ret == 0)
1168 dram_info->num_channels++;
1169
8a6c5447
MK		 1170 val_ch1 = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
1171 ret = skl_dram_get_channel_info(&ch1, val_ch1);
5771caf8
MK		 1172 if (ret == 0)
1173 dram_info->num_channels++;
1174
1175 if (dram_info->num_channels == 0) {
1176 DRM_INFO("Number of memory channels is zero\n");
1177 return -EINVAL;
1178 }
1179
1180 /*
1181 * If any of the channel is single rank channel, worst case output
1182 * will be same as if single rank memory, so consider single rank
1183 * memory.
1184 */
1185 if (ch0.rank == I915_DRAM_RANK_SINGLE ||
1186 ch1.rank == I915_DRAM_RANK_SINGLE)
1187 dram_info->rank = I915_DRAM_RANK_SINGLE;
1188 else
1189 dram_info->rank = max(ch0.rank, ch1.rank);
1190
1191 if (dram_info->rank == I915_DRAM_RANK_INVALID) {
1192 DRM_INFO("couldn't get memory rank information\n");
1193 return -EINVAL;
1194 }
86b59287 1195
5d6f36b2 1196 dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
86b59287 1197
8a6c5447
MK		 1198 dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
1199 val_ch1,
1200 &ch0);
1201
1202 DRM_DEBUG_KMS("memory configuration is %sSymmetric memory\n",
1203 dev_priv->dram_info.symmetric_memory ? "" : "not ");
5771caf8
MK		 1204 return 0;
1205}
1206
1207static int
1208skl_get_dram_info(struct drm_i915_private *dev_priv)
1209{
1210 struct dram_info *dram_info = &dev_priv->dram_info;
1211 u32 mem_freq_khz, val;
1212 int ret;
1213
1214 ret = skl_dram_get_channels_info(dev_priv);
1215 if (ret)
1216 return ret;
1217
1218 val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
1219 mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
1220 SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1221
1222 dram_info->bandwidth_kbps = dram_info->num_channels *
1223 mem_freq_khz * 8;
1224
1225 if (dram_info->bandwidth_kbps == 0) {
1226 DRM_INFO("Couldn't get system memory bandwidth\n");
1227 return -EINVAL;
1228 }
1229
1230 dram_info->valid = true;
1231 return 0;
1232}
1233
cbfa59d4
MK		 1234static int
1235bxt_get_dram_info(struct drm_i915_private *dev_priv)
1236{
1237 struct dram_info *dram_info = &dev_priv->dram_info;
1238 u32 dram_channels;
1239 u32 mem_freq_khz, val;
1240 u8 num_active_channels;
1241 int i;
1242
1243 val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1244 mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
1245 BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
1246
1247 dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
1248 num_active_channels = hweight32(dram_channels);
1249
1250 /* Each active bit represents 4-byte channel */
1251 dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
1252
1253 if (dram_info->bandwidth_kbps == 0) {
1254 DRM_INFO("Couldn't get system memory bandwidth\n");
1255 return -EINVAL;
1256 }
1257
1258 /*
1259 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
1260 */
1261 for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
1262 u8 size, width;
1263 enum dram_rank rank;
1264 u32 tmp;
1265
1266 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
1267 if (val == 0xFFFFFFFF)
1268 continue;
1269
1270 dram_info->num_channels++;
1271 tmp = val & BXT_DRAM_RANK_MASK;
1272
1273 if (tmp == BXT_DRAM_RANK_SINGLE)
1274 rank = I915_DRAM_RANK_SINGLE;
1275 else if (tmp == BXT_DRAM_RANK_DUAL)
1276 rank = I915_DRAM_RANK_DUAL;
1277 else
1278 rank = I915_DRAM_RANK_INVALID;
1279
1280 tmp = val & BXT_DRAM_SIZE_MASK;
1281 if (tmp == BXT_DRAM_SIZE_4GB)
1282 size = 4;
1283 else if (tmp == BXT_DRAM_SIZE_6GB)
1284 size = 6;
1285 else if (tmp == BXT_DRAM_SIZE_8GB)
1286 size = 8;
1287 else if (tmp == BXT_DRAM_SIZE_12GB)
1288 size = 12;
1289 else if (tmp == BXT_DRAM_SIZE_16GB)
1290 size = 16;
1291 else
1292 size = 0;
1293
1294 tmp = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
1295 width = (1 << tmp) * 8;
1296 DRM_DEBUG_KMS("dram size:%dGB width:X%d rank:%s\n", size,
1297 width, rank == I915_DRAM_RANK_SINGLE ? "single" :
1298 rank == I915_DRAM_RANK_DUAL ? "dual" : "unknown");
1299
1300 /*
1301 * If any of the channel is single rank channel,
1302 * worst case output will be same as if single rank
1303 * memory, so consider single rank memory.
1304 */
1305 if (dram_info->rank == I915_DRAM_RANK_INVALID)
1306 dram_info->rank = rank;
1307 else if (rank == I915_DRAM_RANK_SINGLE)
1308 dram_info->rank = I915_DRAM_RANK_SINGLE;
1309 }
1310
1311 if (dram_info->rank == I915_DRAM_RANK_INVALID) {
1312 DRM_INFO("couldn't get memory rank information\n");
1313 return -EINVAL;
1314 }
1315
1316 dram_info->valid = true;
1317 return 0;
1318}
1319
1320static void
1321intel_get_dram_info(struct drm_i915_private *dev_priv)
1322{
1323 struct dram_info *dram_info = &dev_priv->dram_info;
5771caf8 1324 char bandwidth_str[32];
cbfa59d4
MK		 1325 int ret;
1326
1327 dram_info->valid = false;
1328 dram_info->rank = I915_DRAM_RANK_INVALID;
1329 dram_info->bandwidth_kbps = 0;
1330 dram_info->num_channels = 0;
1331
5d6f36b2
VS		 1332 /*
1333 * Assume 16Gb DIMMs are present until proven otherwise.
1334 * This is only used for the level 0 watermark latency
1335 * w/a which does not apply to bxt/glk.
1336 */
1337 dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv);
1338
5771caf8 1339 if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
cbfa59d4
MK		 1340 return;
1341
5771caf8
MK		 1342 /* Need to calculate bandwidth only for Gen9 */
1343 if (IS_BROXTON(dev_priv))
1344 ret = bxt_get_dram_info(dev_priv);
cf819eff 1345 else if (IS_GEN(dev_priv, 9))
5771caf8
MK		 1346 ret = skl_get_dram_info(dev_priv);
1347 else
1348 ret = skl_dram_get_channels_info(dev_priv);
cbfa59d4
MK		 1349 if (ret)
1350 return;
1351
5771caf8
MK		 1352 if (dram_info->bandwidth_kbps)
1353 sprintf(bandwidth_str, "%d KBps", dram_info->bandwidth_kbps);
1354 else
1355 sprintf(bandwidth_str, "unknown");
1356 DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n",
1357 bandwidth_str, dram_info->num_channels);
86b59287 1358 DRM_DEBUG_KMS("DRAM rank: %s rank 16GB-dimm:%s\n",
cbfa59d4 1359 (dram_info->rank == I915_DRAM_RANK_DUAL) ?
86b59287 1360 "dual" : "single", yesno(dram_info->is_16gb_dimm));
cbfa59d4
MK		 1361}
1362
0673ad47
CW		 1363/**
1364 * i915_driver_init_hw - setup state requiring device access
1365 * @dev_priv: device private
1366 *
1367 * Setup state that requires accessing the device, but doesn't require
1368 * exposing the driver via kernel internal or userspace interfaces.
1369 */
1370static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1371{
52a05c30 1372 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47
CW		 1373 int ret;
1374
1375 if (i915_inject_load_failure())
1376 return -ENODEV;
1377
1400cc7e 1378 intel_device_info_runtime_init(dev_priv);
94b4f3ba 1379
4bdafb9d
CW		 1380 if (HAS_PPGTT(dev_priv)) {
1381 if (intel_vgpu_active(dev_priv) &&
1382 !intel_vgpu_has_full_48bit_ppgtt(dev_priv)) {
1383 i915_report_error(dev_priv,
1384 "incompatible vGPU found, support for isolated ppGTT required\n");
1385 return -ENXIO;
1386 }
1387 }
1388
46592892
CW		 1389 if (HAS_EXECLISTS(dev_priv)) {
1390 /*
1391 * Older GVT emulation depends upon intercepting CSB mmio,
1392 * which we no longer use, preferring to use the HWSP cache
1393 * instead.
1394 */
1395 if (intel_vgpu_active(dev_priv) &&
1396 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
1397 i915_report_error(dev_priv,
1398 "old vGPU host found, support for HWSP emulation required\n");
1399 return -ENXIO;
1400 }
1401 }
1402
94b4f3ba 1403 intel_sanitize_options(dev_priv);
0673ad47 1404
9f9b2792
LL		 1405 i915_perf_init(dev_priv);
1406
97d6d7ab 1407 ret = i915_ggtt_probe_hw(dev_priv);
0673ad47 1408 if (ret)
9f172f6f 1409 goto err_perf;
0673ad47 1410
9f172f6f
CW		 1411 /*
1412 * WARNING: Apparently we must kick fbdev drivers before vgacon,
1413 * otherwise the vga fbdev driver falls over.
1414 */
0673ad47
CW		 1415 ret = i915_kick_out_firmware_fb(dev_priv);
1416 if (ret) {
1417 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
9f172f6f 1418 goto err_ggtt;
0673ad47
CW		 1419 }
1420
1421 ret = i915_kick_out_vgacon(dev_priv);
1422 if (ret) {
1423 DRM_ERROR("failed to remove conflicting VGA console\n");
9f172f6f 1424 goto err_ggtt;
0673ad47
CW		 1425 }
1426
97d6d7ab 1427 ret = i915_ggtt_init_hw(dev_priv);
0088e522 1428 if (ret)
9f172f6f 1429 goto err_ggtt;
0088e522 1430
97d6d7ab 1431 ret = i915_ggtt_enable_hw(dev_priv);
0088e522
CW		 1432 if (ret) {
1433 DRM_ERROR("failed to enable GGTT\n");
9f172f6f 1434 goto err_ggtt;
0088e522
CW		 1435 }
1436
52a05c30 1437 pci_set_master(pdev);
0673ad47
CW		 1438
1439 /* overlay on gen2 is broken and can't address above 1G */
cf819eff 1440 if (IS_GEN(dev_priv, 2)) {
52a05c30 1441 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
0673ad47
CW		 1442 if (ret) {
1443 DRM_ERROR("failed to set DMA mask\n");
1444
9f172f6f 1445 goto err_ggtt;
0673ad47
CW		 1446 }
1447 }
1448
0673ad47
CW		 1449 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1450 * using 32bit addressing, overwriting memory if HWS is located
1451 * above 4GB.
1452 *
1453 * The documentation also mentions an issue with undefined
1454 * behaviour if any general state is accessed within a page above 4GB,
1455 * which also needs to be handled carefully.
1456 */
c0f86832 1457 if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
52a05c30 1458 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
0673ad47
CW		 1459
1460 if (ret) {
1461 DRM_ERROR("failed to set DMA mask\n");
1462
9f172f6f 1463 goto err_ggtt;
0673ad47
CW		 1464 }
1465 }
1466
0673ad47
CW		 1467 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1468 PM_QOS_DEFAULT_VALUE);
1469
1470 intel_uncore_sanitize(dev_priv);
1471
25d140fa 1472 intel_gt_init_workarounds(dev_priv);
0673ad47
CW		 1473 i915_gem_load_init_fences(dev_priv);
1474
1475 /* On the 945G/GM, the chipset reports the MSI capability on the
1476 * integrated graphics even though the support isn't actually there
1477 * according to the published specs. It doesn't appear to function
1478 * correctly in testing on 945G.
1479 * This may be a side effect of MSI having been made available for PEG
1480 * and the registers being closely associated.
1481 *
1482 * According to chipset errata, on the 965GM, MSI interrupts may
e38c2da0
VS		 1483 * be lost or delayed, and was defeatured. MSI interrupts seem to
1484 * get lost on g4x as well, and interrupt delivery seems to stay
1485 * properly dead afterwards. So we'll just disable them for all
1486 * pre-gen5 chipsets.
8a29c778
LDM		 1487 *
1488 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
1489 * interrupts even when in MSI mode. This results in spurious
1490 * interrupt warnings if the legacy irq no. is shared with another
1491 * device. The kernel then disables that interrupt source and so
1492 * prevents the other device from working properly.
0673ad47 1493 */
e38c2da0 1494 if (INTEL_GEN(dev_priv) >= 5) {
52a05c30 1495 if (pci_enable_msi(pdev) < 0)
0673ad47
CW		 1496 DRM_DEBUG_DRIVER("can't enable MSI");
1497 }
1498
26f837e8
ZW		 1499 ret = intel_gvt_init(dev_priv);
1500 if (ret)
7ab87ede
CW		 1501 goto err_msi;
1502
1503 intel_opregion_setup(dev_priv);
cbfa59d4
MK		 1504 /*
1505 * Fill the dram structure to get the system raw bandwidth and
1506 * dram info. This will be used for memory latency calculation.
1507 */
1508 intel_get_dram_info(dev_priv);
1509
26f837e8 1510
0673ad47
CW		 1511 return 0;
1512
7ab87ede
CW		 1513err_msi:
1514 if (pdev->msi_enabled)
1515 pci_disable_msi(pdev);
1516 pm_qos_remove_request(&dev_priv->pm_qos);
9f172f6f 1517err_ggtt:
97d6d7ab 1518 i915_ggtt_cleanup_hw(dev_priv);
9f172f6f
CW		 1519err_perf:
1520 i915_perf_fini(dev_priv);
0673ad47
CW		 1521 return ret;
1522}
1523
1524/**
1525 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1526 * @dev_priv: device private
1527 */
1528static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1529{
52a05c30 1530 struct pci_dev *pdev = dev_priv->drm.pdev;
0673ad47 1531
9f9b2792
LL		 1532 i915_perf_fini(dev_priv);
1533
52a05c30
DW		 1534 if (pdev->msi_enabled)
1535 pci_disable_msi(pdev);
0673ad47
CW		 1536
1537 pm_qos_remove_request(&dev_priv->pm_qos);
97d6d7ab 1538 i915_ggtt_cleanup_hw(dev_priv);
0673ad47
CW		 1539}
1540
1541/**
1542 * i915_driver_register - register the driver with the rest of the system
1543 * @dev_priv: device private
1544 *
1545 * Perform any steps necessary to make the driver available via kernel
1546 * internal or userspace interfaces.
1547 */
1548static void i915_driver_register(struct drm_i915_private *dev_priv)
1549{
91c8a326 1550 struct drm_device *dev = &dev_priv->drm;
0673ad47 1551
848b365d 1552 i915_gem_shrinker_register(dev_priv);
b46a33e2 1553 i915_pmu_register(dev_priv);
0673ad47
CW		 1554
1555 /*
1556 * Notify a valid surface after modesetting,
1557 * when running inside a VM.
1558 */
1559 if (intel_vgpu_active(dev_priv))
1560 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1561
1562 /* Reveal our presence to userspace */
1563 if (drm_dev_register(dev, 0) == 0) {
1564 i915_debugfs_register(dev_priv);
694c2828 1565 i915_setup_sysfs(dev_priv);
442b8c06
RB		 1566
1567 /* Depends on sysfs having been initialized */
1568 i915_perf_register(dev_priv);
0673ad47
CW		 1569 } else
1570 DRM_ERROR("Failed to register driver for userspace access!\n");
1571
e1bf094b 1572 if (HAS_DISPLAY(dev_priv)) {
0673ad47
CW		 1573 /* Must be done after probing outputs */
1574 intel_opregion_register(dev_priv);
1575 acpi_video_register();
1576 }
1577
cf819eff 1578 if (IS_GEN(dev_priv, 5))
0673ad47
CW		 1579 intel_gpu_ips_init(dev_priv);
1580
eef57324 1581 intel_audio_init(dev_priv);
0673ad47
CW		 1582
1583 /*
1584 * Some ports require correctly set-up hpd registers for detection to
1585 * work properly (leading to ghost connected connector status), e.g. VGA
1586 * on gm45. Hence we can only set up the initial fbdev config after hpd
1587 * irqs are fully enabled. We do it last so that the async config
1588 * cannot run before the connectors are registered.
1589 */
1590 intel_fbdev_initial_config_async(dev);
448aa911
CW		 1591
1592 /*
1593 * We need to coordinate the hotplugs with the asynchronous fbdev
1594 * configuration, for which we use the fbdev->async_cookie.
1595 */
e1bf094b 1596 if (HAS_DISPLAY(dev_priv))
448aa911 1597 drm_kms_helper_poll_init(dev);
07d80572 1598
2cd9a689 1599 intel_power_domains_enable(dev_priv);
07d80572 1600 intel_runtime_pm_enable(dev_priv);
0673ad47
CW		 1601}
1602
1603/**
1604 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1605 * @dev_priv: device private
1606 */
1607static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1608{
07d80572 1609 intel_runtime_pm_disable(dev_priv);
2cd9a689 1610 intel_power_domains_disable(dev_priv);
07d80572 1611
4f256d82 1612 intel_fbdev_unregister(dev_priv);
eef57324 1613 intel_audio_deinit(dev_priv);
0673ad47 1614
448aa911
CW		 1615 /*
1616 * After flushing the fbdev (incl. a late async config which will
1617 * have delayed queuing of a hotplug event), then flush the hotplug
1618 * events.
1619 */
1620 drm_kms_helper_poll_fini(&dev_priv->drm);
1621
0673ad47
CW		 1622 intel_gpu_ips_teardown();
1623 acpi_video_unregister();
1624 intel_opregion_unregister(dev_priv);
1625
442b8c06 1626 i915_perf_unregister(dev_priv);
b46a33e2 1627 i915_pmu_unregister(dev_priv);
442b8c06 1628
694c2828 1629 i915_teardown_sysfs(dev_priv);
91c8a326 1630 drm_dev_unregister(&dev_priv->drm);
0673ad47 1631
848b365d 1632 i915_gem_shrinker_unregister(dev_priv);
0673ad47
CW		 1633}
1634
27d558a1
MW		 1635static void i915_welcome_messages(struct drm_i915_private *dev_priv)
1636{
1637 if (drm_debug & DRM_UT_DRIVER) {
1638 struct drm_printer p = drm_debug_printer("i915 device info:");
1639
1787a984
JN		 1640 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n",
1641 INTEL_DEVID(dev_priv),
1642 INTEL_REVID(dev_priv),
1643 intel_platform_name(INTEL_INFO(dev_priv)->platform),
1644 INTEL_GEN(dev_priv));
1645
1646 intel_device_info_dump_flags(INTEL_INFO(dev_priv), &p);
0258404f 1647 intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
27d558a1
MW		 1648 }
1649
1650 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
1651 DRM_INFO("DRM_I915_DEBUG enabled\n");
1652 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
1653 DRM_INFO("DRM_I915_DEBUG_GEM enabled\n");
6dfc4a8f
ID		 1654 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
1655 DRM_INFO("DRM_I915_DEBUG_RUNTIME_PM enabled\n");
27d558a1
MW		 1656}
1657
55ac5a16
CW		 1658static struct drm_i915_private *
1659i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
1660{
1661 const struct intel_device_info *match_info =
1662 (struct intel_device_info *)ent->driver_data;
1663 struct intel_device_info *device_info;
1664 struct drm_i915_private *i915;
2ddcc982 1665 int err;
55ac5a16
CW		 1666
1667 i915 = kzalloc(sizeof(*i915), GFP_KERNEL);
1668 if (!i915)
2ddcc982 1669 return ERR_PTR(-ENOMEM);
55ac5a16 1670
2ddcc982
AS		 1671 err = drm_dev_init(&i915->drm, &driver, &pdev->dev);
1672 if (err) {
55ac5a16 1673 kfree(i915);
2ddcc982 1674 return ERR_PTR(err);
55ac5a16
CW		 1675 }
1676
1677 i915->drm.pdev = pdev;
1678 i915->drm.dev_private = i915;
1679 pci_set_drvdata(pdev, &i915->drm);
1680
1681 /* Setup the write-once "constant" device info */
1682 device_info = mkwrite_device_info(i915);
1683 memcpy(device_info, match_info, sizeof(*device_info));
0258404f 1684 RUNTIME_INFO(i915)->device_id = pdev->device;
55ac5a16
CW		 1685
1686 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
74f6e183
CW		 1687 BITS_PER_TYPE(device_info->platform_mask));
1688 BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
55ac5a16
CW		 1689
1690 return i915;
1691}
1692
31962ca6
CW		 1693static void i915_driver_destroy(struct drm_i915_private *i915)
1694{
1695 struct pci_dev *pdev = i915->drm.pdev;
1696
1697 drm_dev_fini(&i915->drm);
1698 kfree(i915);
1699
1700 /* And make sure we never chase our dangling pointer from pci_dev */
1701 pci_set_drvdata(pdev, NULL);
1702}
1703
0673ad47
CW		 1704/**
1705 * i915_driver_load - setup chip and create an initial config
d2ad3ae4
JL		 1706 * @pdev: PCI device
1707 * @ent: matching PCI ID entry
0673ad47
CW		 1708 *
1709 * The driver load routine has to do several things:
1710 * - drive output discovery via intel_modeset_init()
1711 * - initialize the memory manager
1712 * - allocate initial config memory
1713 * - setup the DRM framebuffer with the allocated memory
1714 */
42f5551d 1715int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
0673ad47 1716{
8d2b47dd
ML		 1717 const struct intel_device_info *match_info =
1718 (struct intel_device_info *)ent->driver_data;
0673ad47
CW		 1719 struct drm_i915_private *dev_priv;
1720 int ret;
7d87a7f7 1721
55ac5a16 1722 dev_priv = i915_driver_create(pdev, ent);
2ddcc982
AS		 1723 if (IS_ERR(dev_priv))
1724 return PTR_ERR(dev_priv);
719388e1 1725
1feb64c4
VS		 1726 /* Disable nuclear pageflip by default on pre-ILK */
1727 if (!i915_modparams.nuclear_pageflip && match_info->gen < 5)
1728 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
1729
0673ad47
CW		 1730 ret = pci_enable_device(pdev);
1731 if (ret)
cad3688f 1732 goto out_fini;
1347f5b4 1733
55ac5a16 1734 ret = i915_driver_init_early(dev_priv);
0673ad47
CW		 1735 if (ret < 0)
1736 goto out_pci_disable;
ef11bdb3 1737
2cd9a689 1738 disable_rpm_wakeref_asserts(dev_priv);
1da177e4 1739
0673ad47
CW		 1740 ret = i915_driver_init_mmio(dev_priv);
1741 if (ret < 0)
1742 goto out_runtime_pm_put;
79e53945 1743
0673ad47
CW		 1744 ret = i915_driver_init_hw(dev_priv);
1745 if (ret < 0)
1746 goto out_cleanup_mmio;
30c964a6 1747
91c8a326 1748 ret = i915_load_modeset_init(&dev_priv->drm);
0673ad47 1749 if (ret < 0)
baf54385 1750 goto out_cleanup_hw;
0673ad47
CW		 1751
1752 i915_driver_register(dev_priv);
1753
2cd9a689 1754 enable_rpm_wakeref_asserts(dev_priv);
0673ad47 1755
27d558a1
MW		 1756 i915_welcome_messages(dev_priv);
1757
0673ad47
CW		 1758 return 0;
1759
0673ad47
CW		 1760out_cleanup_hw:
1761 i915_driver_cleanup_hw(dev_priv);
1762out_cleanup_mmio:
1763 i915_driver_cleanup_mmio(dev_priv);
1764out_runtime_pm_put:
2cd9a689 1765 enable_rpm_wakeref_asserts(dev_priv);
0673ad47
CW		 1766 i915_driver_cleanup_early(dev_priv);
1767out_pci_disable:
1768 pci_disable_device(pdev);
cad3688f 1769out_fini:
0673ad47 1770 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
31962ca6 1771 i915_driver_destroy(dev_priv);
30c964a6
RB		 1772 return ret;
1773}
1774
42f5551d 1775void i915_driver_unload(struct drm_device *dev)
3bad0781 1776{
fac5e23e 1777 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1778 struct pci_dev *pdev = dev_priv->drm.pdev;
3bad0781 1779
2cd9a689 1780 disable_rpm_wakeref_asserts(dev_priv);
07d80572 1781
99c539be
SV		 1782 i915_driver_unregister(dev_priv);
1783
4a8ab5ea
CW		 1784 /* Flush any external code that still may be under the RCU lock */
1785 synchronize_rcu();
1786
bf9e8429 1787 if (i915_gem_suspend(dev_priv))
42f5551d 1788 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
ce1bb329 1789
18dddadc 1790 drm_atomic_helper_shutdown(dev);
a667fb40 1791
26f837e8
ZW		 1792 intel_gvt_cleanup(dev_priv);
1793
0673ad47
CW		 1794 intel_modeset_cleanup(dev);
1795
785f076b 1796 intel_bios_cleanup(dev_priv);
3bad0781 1797
52a05c30
DW		 1798 vga_switcheroo_unregister_client(pdev);
1799 vga_client_register(pdev, NULL, NULL, NULL);
bcdb72ac 1800
0673ad47 1801 intel_csr_ucode_fini(dev_priv);
bcdb72ac 1802
0673ad47
CW		 1803 /* Free error state after interrupts are fully disabled. */
1804 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
5a4c6f1b 1805 i915_reset_error_state(dev_priv);
0673ad47 1806
fbbd37b3 1807 i915_gem_fini(dev_priv);
0673ad47 1808
48a287ed 1809 intel_power_domains_fini_hw(dev_priv);
0673ad47
CW		 1810
1811 i915_driver_cleanup_hw(dev_priv);
1812 i915_driver_cleanup_mmio(dev_priv);
1813
2cd9a689 1814 enable_rpm_wakeref_asserts(dev_priv);
bd780f37 1815 intel_runtime_pm_cleanup(dev_priv);
cad3688f
CW		 1816}
1817
1818static void i915_driver_release(struct drm_device *dev)
1819{
1820 struct drm_i915_private *dev_priv = to_i915(dev);
0673ad47
CW		 1821
1822 i915_driver_cleanup_early(dev_priv);
31962ca6 1823 i915_driver_destroy(dev_priv);
3bad0781
ZW		 1824}
1825
0673ad47 1826static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2911a35b 1827{
829a0af2 1828 struct drm_i915_private *i915 = to_i915(dev);
0673ad47 1829 int ret;
2911a35b 1830
829a0af2 1831 ret = i915_gem_open(i915, file);
0673ad47
CW		 1832 if (ret)
1833 return ret;
2911a35b 1834
0673ad47
CW		 1835 return 0;
1836}
71386ef9 1837
0673ad47
CW		 1838/**
1839 * i915_driver_lastclose - clean up after all DRM clients have exited
1840 * @dev: DRM device
1841 *
1842 * Take care of cleaning up after all DRM clients have exited. In the
1843 * mode setting case, we want to restore the kernel's initial mode (just
1844 * in case the last client left us in a bad state).
1845 *
1846 * Additionally, in the non-mode setting case, we'll tear down the GTT
1847 * and DMA structures, since the kernel won't be using them, and clea
1848 * up any GEM state.
1849 */
1850static void i915_driver_lastclose(struct drm_device *dev)
1851{
1852 intel_fbdev_restore_mode(dev);
1853 vga_switcheroo_process_delayed_switch();
1854}
2911a35b 1855
7d2ec881 1856static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
0673ad47 1857{
7d2ec881
SV		 1858 struct drm_i915_file_private *file_priv = file->driver_priv;
1859
0673ad47 1860 mutex_lock(&dev->struct_mutex);
829a0af2 1861 i915_gem_context_close(file);
0673ad47
CW		 1862 i915_gem_release(dev, file);
1863 mutex_unlock(&dev->struct_mutex);
0673ad47
CW		 1864
1865 kfree(file_priv);
2911a35b
BW		 1866}
1867
07f9cd0b
ID		 1868static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1869{
91c8a326 1870 struct drm_device *dev = &dev_priv->drm;
19c8054c 1871 struct intel_encoder *encoder;
07f9cd0b
ID		 1872
1873 drm_modeset_lock_all(dev);
19c8054c
JN		 1874 for_each_intel_encoder(dev, encoder)
1875 if (encoder->suspend)
1876 encoder->suspend(encoder);
07f9cd0b
ID		 1877 drm_modeset_unlock_all(dev);
1878}
1879
1a5df187
PZ		 1880static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1881 bool rpm_resume);
507e126e 1882static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
f75a1985 1883
bc87229f
ID		 1884static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1885{
1886#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1887 if (acpi_target_system_state() < ACPI_STATE_S3)
1888 return true;
1889#endif
1890 return false;
1891}
ebc32824 1892
73b66f87
CW		 1893static int i915_drm_prepare(struct drm_device *dev)
1894{
1895 struct drm_i915_private *i915 = to_i915(dev);
1896 int err;
1897
1898 /*
1899 * NB intel_display_suspend() may issue new requests after we've
1900 * ostensibly marked the GPU as ready-to-sleep here. We need to
1901 * split out that work and pull it forward so that after point,
1902 * the GPU is not woken again.
1903 */
1904 err = i915_gem_suspend(i915);
1905 if (err)
1906 dev_err(&i915->drm.pdev->dev,
1907 "GEM idle failed, suspend/resume might fail\n");
1908
1909 return err;
1910}
1911
5e365c39 1912static int i915_drm_suspend(struct drm_device *dev)
ba8bbcf6 1913{
fac5e23e 1914 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1915 struct pci_dev *pdev = dev_priv->drm.pdev;
e5747e3a 1916 pci_power_t opregion_target_state;
61caf87c 1917
1f814dac
ID		 1918 disable_rpm_wakeref_asserts(dev_priv);
1919
c67a470b
PZ		 1920 /* We do a lot of poking in a lot of registers, make sure they work
1921 * properly. */
2cd9a689 1922 intel_power_domains_disable(dev_priv);
cb10799c 1923
5bcf719b
DA		 1924 drm_kms_helper_poll_disable(dev);
1925
52a05c30 1926 pci_save_state(pdev);
ba8bbcf6 1927
6b72d486 1928 intel_display_suspend(dev);
2eb5252e 1929
1a4313d1 1930 intel_dp_mst_suspend(dev_priv);
7d708ee4 1931
d5818938
SV		 1932 intel_runtime_pm_disable_interrupts(dev_priv);
1933 intel_hpd_cancel_work(dev_priv);
09b64267 1934
d5818938 1935 intel_suspend_encoders(dev_priv);
0e32b39c 1936
712bf364 1937 intel_suspend_hw(dev_priv);
5669fcac 1938
275a991c 1939 i915_gem_suspend_gtt_mappings(dev_priv);
828c7908 1940
af6dc742 1941 i915_save_state(dev_priv);
9e06dd39 1942
bc87229f 1943 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
a950adc6 1944 intel_opregion_suspend(dev_priv, opregion_target_state);
8ee1c3db 1945
82e3b8c1 1946 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
3fa016a0 1947
62d5d69b
MK		 1948 dev_priv->suspend_count++;
1949
f74ed08d 1950 intel_csr_ucode_suspend(dev_priv);
f514c2d8 1951
1f814dac
ID		 1952 enable_rpm_wakeref_asserts(dev_priv);
1953
73b66f87 1954 return 0;
84b79f8d
RW		 1955}
1956
2cd9a689
ID		 1957static enum i915_drm_suspend_mode
1958get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1959{
1960 if (hibernate)
1961 return I915_DRM_SUSPEND_HIBERNATE;
1962
1963 if (suspend_to_idle(dev_priv))
1964 return I915_DRM_SUSPEND_IDLE;
1965
1966 return I915_DRM_SUSPEND_MEM;
1967}
1968
c49d13ee 1969static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
c3c09c95 1970{
c49d13ee 1971 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 1972 struct pci_dev *pdev = dev_priv->drm.pdev;
c3c09c95
ID		 1973 int ret;
1974
1f814dac
ID		 1975 disable_rpm_wakeref_asserts(dev_priv);
1976
ec92ad00
CW		 1977 i915_gem_suspend_late(dev_priv);
1978
ec92ad00 1979 intel_uncore_suspend(dev_priv);
4c494a57 1980
2cd9a689
ID		 1981 intel_power_domains_suspend(dev_priv,
1982 get_suspend_mode(dev_priv, hibernation));
73dfc227 1983
507e126e 1984 ret = 0;
3b6ac43b 1985 if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv))
507e126e 1986 bxt_enable_dc9(dev_priv);
b8aea3d1 1987 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
507e126e
ID		 1988 hsw_enable_pc8(dev_priv);
1989 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1990 ret = vlv_suspend_complete(dev_priv);
c3c09c95
ID		 1991
1992 if (ret) {
1993 DRM_ERROR("Suspend complete failed: %d\n", ret);
2cd9a689 1994 intel_power_domains_resume(dev_priv);
c3c09c95 1995
1f814dac 1996 goto out;
c3c09c95
ID		 1997 }
1998
52a05c30 1999 pci_disable_device(pdev);
ab3be73f 2000 /*
54875571 2001 * During hibernation on some platforms the BIOS may try to access
ab3be73f
ID		 2002 * the device even though it's already in D3 and hang the machine. So
2003 * leave the device in D0 on those platforms and hope the BIOS will
54875571
ID		 2004 * power down the device properly. The issue was seen on multiple old
2005 * GENs with different BIOS vendors, so having an explicit blacklist
2006 * is inpractical; apply the workaround on everything pre GEN6. The
2007 * platforms where the issue was seen:
2008 * Lenovo Thinkpad X301, X61s, X60, T60, X41
2009 * Fujitsu FSC S7110
2010 * Acer Aspire 1830T
ab3be73f 2011 */
514e1d64 2012 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
52a05c30 2013 pci_set_power_state(pdev, PCI_D3hot);
c3c09c95 2014
1f814dac
ID		 2015out:
2016 enable_rpm_wakeref_asserts(dev_priv);
bd780f37
CW		 2017 if (!dev_priv->uncore.user_forcewake.count)
2018 intel_runtime_pm_cleanup(dev_priv);
1f814dac
ID		 2019
2020 return ret;
c3c09c95
ID		 2021}
2022
a9a251c2 2023static int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
84b79f8d
RW		 2024{
2025 int error;
2026
ded8b07d 2027 if (!dev) {
84b79f8d
RW		 2028 DRM_ERROR("dev: %p\n", dev);
2029 DRM_ERROR("DRM not initialized, aborting suspend.\n");
2030 return -ENODEV;
2031 }
2032
0b14cbd2
ID		 2033 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
2034 state.event != PM_EVENT_FREEZE))
2035 return -EINVAL;
5bcf719b
DA		 2036
2037 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2038 return 0;
6eecba33 2039
5e365c39 2040 error = i915_drm_suspend(dev);
84b79f8d
RW		 2041 if (error)
2042 return error;
2043
ab3be73f 2044 return i915_drm_suspend_late(dev, false);
ba8bbcf6
JB		 2045}
2046
5e365c39 2047static int i915_drm_resume(struct drm_device *dev)
76c4b250 2048{
fac5e23e 2049 struct drm_i915_private *dev_priv = to_i915(dev);
ac840ae5 2050 int ret;
9d49c0ef 2051
1f814dac 2052 disable_rpm_wakeref_asserts(dev_priv);
abc80abd 2053 intel_sanitize_gt_powersave(dev_priv);
1f814dac 2054
1288786b
CW		 2055 i915_gem_sanitize(dev_priv);
2056
97d6d7ab 2057 ret = i915_ggtt_enable_hw(dev_priv);
ac840ae5
VS		 2058 if (ret)
2059 DRM_ERROR("failed to re-enable GGTT\n");
2060
f74ed08d
ID		 2061 intel_csr_ucode_resume(dev_priv);
2062
af6dc742 2063 i915_restore_state(dev_priv);
8090ba8c 2064 intel_pps_unlock_regs_wa(dev_priv);
61caf87c 2065
c39055b0 2066 intel_init_pch_refclk(dev_priv);
1833b134 2067
364aece0
PA		 2068 /*
2069 * Interrupts have to be enabled before any batches are run. If not the
2070 * GPU will hang. i915_gem_init_hw() will initiate batches to
2071 * update/restore the context.
2072 *
908764f6
ID		 2073 * drm_mode_config_reset() needs AUX interrupts.
2074 *
364aece0
PA		 2075 * Modeset enabling in intel_modeset_init_hw() also needs working
2076 * interrupts.
2077 */
2078 intel_runtime_pm_enable_interrupts(dev_priv);
2079
908764f6
ID		 2080 drm_mode_config_reset(dev);
2081
37cd3300 2082 i915_gem_resume(dev_priv);
226485e9 2083
d5818938 2084 intel_modeset_init_hw(dev);
675f7ff3 2085 intel_init_clock_gating(dev_priv);
24576d23 2086
d5818938
SV		 2087 spin_lock_irq(&dev_priv->irq_lock);
2088 if (dev_priv->display.hpd_irq_setup)
91d14251 2089 dev_priv->display.hpd_irq_setup(dev_priv);
d5818938 2090 spin_unlock_irq(&dev_priv->irq_lock);
0e32b39c 2091
1a4313d1 2092 intel_dp_mst_resume(dev_priv);
e7d6f7d7 2093
a16b7658
L		 2094 intel_display_resume(dev);
2095
e0b70061
L		 2096 drm_kms_helper_poll_enable(dev);
2097
d5818938
SV		 2098 /*
2099 * ... but also need to make sure that hotplug processing
2100 * doesn't cause havoc. Like in the driver load code we don't
c444ad79 2101 * bother with the tiny race here where we might lose hotplug
d5818938
SV		 2102 * notifications.
2103 * */
2104 intel_hpd_init(dev_priv);
1daed3fb 2105
a950adc6 2106 intel_opregion_resume(dev_priv);
44834a67 2107
82e3b8c1 2108 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
073f34d9 2109
2cd9a689
ID		 2110 intel_power_domains_enable(dev_priv);
2111
1f814dac
ID		 2112 enable_rpm_wakeref_asserts(dev_priv);
2113
074c6ada 2114 return 0;
84b79f8d
RW		 2115}
2116
5e365c39 2117static int i915_drm_resume_early(struct drm_device *dev)
84b79f8d 2118{
fac5e23e 2119 struct drm_i915_private *dev_priv = to_i915(dev);
52a05c30 2120 struct pci_dev *pdev = dev_priv->drm.pdev;
44410cd0 2121 int ret;
36d61e67 2122
76c4b250
ID		 2123 /*
2124 * We have a resume ordering issue with the snd-hda driver also
2125 * requiring our device to be power up. Due to the lack of a
2126 * parent/child relationship we currently solve this with an early
2127 * resume hook.
2128 *
2129 * FIXME: This should be solved with a special hdmi sink device or
2130 * similar so that power domains can be employed.
2131 */
44410cd0
ID		 2132
2133 /*
2134 * Note that we need to set the power state explicitly, since we
2135 * powered off the device during freeze and the PCI core won't power
2136 * it back up for us during thaw. Powering off the device during
2137 * freeze is not a hard requirement though, and during the
2138 * suspend/resume phases the PCI core makes sure we get here with the
2139 * device powered on. So in case we change our freeze logic and keep
2140 * the device powered we can also remove the following set power state
2141 * call.
2142 */
52a05c30 2143 ret = pci_set_power_state(pdev, PCI_D0);
44410cd0
ID		 2144 if (ret) {
2145 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2cd9a689 2146 return ret;
44410cd0
ID		 2147 }
2148
2149 /*
2150 * Note that pci_enable_device() first enables any parent bridge
2151 * device and only then sets the power state for this device. The
2152 * bridge enabling is a nop though, since bridge devices are resumed
2153 * first. The order of enabling power and enabling the device is
2154 * imposed by the PCI core as described above, so here we preserve the
2155 * same order for the freeze/thaw phases.
2156 *
2157 * TODO: eventually we should remove pci_disable_device() /
2158 * pci_enable_enable_device() from suspend/resume. Due to how they
2159 * depend on the device enable refcount we can't anyway depend on them
2160 * disabling/enabling the device.
2161 */
2cd9a689
ID		 2162 if (pci_enable_device(pdev))
2163 return -EIO;
84b79f8d 2164
52a05c30 2165 pci_set_master(pdev);
84b79f8d 2166
1f814dac
ID		 2167 disable_rpm_wakeref_asserts(dev_priv);
2168
666a4537 2169 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1a5df187 2170 ret = vlv_resume_prepare(dev_priv, false);
36d61e67 2171 if (ret)
ff0b187f
DL		 2172 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2173 ret);
36d61e67 2174
68f60946 2175 intel_uncore_resume_early(dev_priv);
efee833a 2176
3e68928b 2177 if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) {
0f90603c 2178 gen9_sanitize_dc_state(dev_priv);
507e126e 2179 bxt_disable_dc9(dev_priv);
da2f41d1 2180 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
a9a6b73a 2181 hsw_disable_pc8(dev_priv);
da2f41d1 2182 }
efee833a 2183
dc97997a 2184 intel_uncore_sanitize(dev_priv);
bc87229f 2185
2cd9a689 2186 intel_power_domains_resume(dev_priv);
bc87229f 2187
55277e1f 2188 intel_engines_sanitize(dev_priv, true);
4fdd5b4e 2189
6e35e8ab
ID		 2190 enable_rpm_wakeref_asserts(dev_priv);
2191
36d61e67 2192 return ret;
76c4b250
ID		 2193}
2194
7f26cb88 2195static int i915_resume_switcheroo(struct drm_device *dev)
76c4b250 2196{
50a0072f 2197 int ret;
76c4b250 2198
097dd837
ID		 2199 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2200 return 0;
2201
5e365c39 2202 ret = i915_drm_resume_early(dev);
50a0072f
ID		 2203 if (ret)
2204 return ret;
2205
5a17514e
ID		 2206 return i915_drm_resume(dev);
2207}
2208
73b66f87
CW		 2209static int i915_pm_prepare(struct device *kdev)
2210{
2211 struct pci_dev *pdev = to_pci_dev(kdev);
2212 struct drm_device *dev = pci_get_drvdata(pdev);
2213
2214 if (!dev) {
2215 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
2216 return -ENODEV;
2217 }
2218
2219 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2220 return 0;
2221
2222 return i915_drm_prepare(dev);
2223}
2224
c49d13ee 2225static int i915_pm_suspend(struct device *kdev)
112b715e 2226{
c49d13ee
DW		 2227 struct pci_dev *pdev = to_pci_dev(kdev);
2228 struct drm_device *dev = pci_get_drvdata(pdev);
112b715e 2229
c49d13ee
DW		 2230 if (!dev) {
2231 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
84b79f8d
RW		 2232 return -ENODEV;
2233 }
112b715e 2234
c49d13ee 2235 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
5bcf719b
DA		 2236 return 0;
2237
c49d13ee 2238 return i915_drm_suspend(dev);
76c4b250
ID		 2239}
2240
c49d13ee 2241static int i915_pm_suspend_late(struct device *kdev)
76c4b250 2242{
c49d13ee 2243 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250
ID		 2244
2245 /*
c965d995 2246 * We have a suspend ordering issue with the snd-hda driver also
76c4b250
ID		 2247 * requiring our device to be power up. Due to the lack of a
2248 * parent/child relationship we currently solve this with an late
2249 * suspend hook.
2250 *
2251 * FIXME: This should be solved with a special hdmi sink device or
2252 * similar so that power domains can be employed.
2253 */
c49d13ee 2254 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
76c4b250 2255 return 0;
112b715e 2256
c49d13ee 2257 return i915_drm_suspend_late(dev, false);
ab3be73f
ID		 2258}
2259
c49d13ee 2260static int i915_pm_poweroff_late(struct device *kdev)
ab3be73f 2261{
c49d13ee 2262 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
ab3be73f 2263
c49d13ee 2264 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
ab3be73f
ID		 2265 return 0;
2266
c49d13ee 2267 return i915_drm_suspend_late(dev, true);
cbda12d7
ZW		 2268}
2269
c49d13ee 2270static int i915_pm_resume_early(struct device *kdev)
76c4b250 2271{
c49d13ee 2272 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
76c4b250 2273
c49d13ee 2274 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 2275 return 0;
2276
c49d13ee 2277 return i915_drm_resume_early(dev);
76c4b250
ID		 2278}
2279
c49d13ee 2280static int i915_pm_resume(struct device *kdev)
cbda12d7 2281{
c49d13ee 2282 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
84b79f8d 2283
c49d13ee 2284 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
097dd837
ID		 2285 return 0;
2286
c49d13ee 2287 return i915_drm_resume(dev);
cbda12d7
ZW		 2288}
2289
1f19ac2a 2290/* freeze: before creating the hibernation_image */
c49d13ee 2291static int i915_pm_freeze(struct device *kdev)
1f19ac2a 2292{
dd9f31c7 2293 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
6a800eab
CW		 2294 int ret;
2295
dd9f31c7
ID		 2296 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2297 ret = i915_drm_suspend(dev);
2298 if (ret)
2299 return ret;
2300 }
6a800eab
CW		 2301
2302 ret = i915_gem_freeze(kdev_to_i915(kdev));
2303 if (ret)
2304 return ret;
2305
2306 return 0;
1f19ac2a
CW		 2307}
2308
c49d13ee 2309static int i915_pm_freeze_late(struct device *kdev)
1f19ac2a 2310{
dd9f31c7 2311 struct drm_device *dev = &kdev_to_i915(kdev)->drm;
461fb99c
CW		 2312 int ret;
2313
dd9f31c7
ID		 2314 if (dev->switch_power_state != DRM_SWITCH_POWER_OFF) {
2315 ret = i915_drm_suspend_late(dev, true);
2316 if (ret)
2317 return ret;
2318 }
461fb99c 2319
c49d13ee 2320 ret = i915_gem_freeze_late(kdev_to_i915(kdev));
461fb99c
CW		 2321 if (ret)
2322 return ret;
2323
2324 return 0;
1f19ac2a
CW		 2325}
2326
2327/* thaw: called after creating the hibernation image, but before turning off. */
c49d13ee 2328static int i915_pm_thaw_early(struct device *kdev)
1f19ac2a 2329{
c49d13ee 2330 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 2331}
2332
c49d13ee 2333static int i915_pm_thaw(struct device *kdev)
1f19ac2a 2334{
c49d13ee 2335 return i915_pm_resume(kdev);
1f19ac2a
CW		 2336}
2337
2338/* restore: called after loading the hibernation image. */
c49d13ee 2339static int i915_pm_restore_early(struct device *kdev)
1f19ac2a 2340{
c49d13ee 2341 return i915_pm_resume_early(kdev);
1f19ac2a
CW		 2342}
2343
c49d13ee 2344static int i915_pm_restore(struct device *kdev)
1f19ac2a 2345{
c49d13ee 2346 return i915_pm_resume(kdev);
1f19ac2a
CW		 2347}
2348
ddeea5b0
ID		 2349/*
2350 * Save all Gunit registers that may be lost after a D3 and a subsequent
2351 * S0i[R123] transition. The list of registers needing a save/restore is
2352 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2353 * registers in the following way:
2354 * - Driver: saved/restored by the driver
2355 * - Punit : saved/restored by the Punit firmware
2356 * - No, w/o marking: no need to save/restore, since the register is R/O or
2357 * used internally by the HW in a way that doesn't depend
2358 * keeping the content across a suspend/resume.
2359 * - Debug : used for debugging
2360 *
2361 * We save/restore all registers marked with 'Driver', with the following
2362 * exceptions:
2363 * - Registers out of use, including also registers marked with 'Debug'.
2364 * These have no effect on the driver's operation, so we don't save/restore
2365 * them to reduce the overhead.
2366 * - Registers that are fully setup by an initialization function called from
2367 * the resume path. For example many clock gating and RPS/RC6 registers.
2368 * - Registers that provide the right functionality with their reset defaults.
2369 *
2370 * TODO: Except for registers that based on the above 3 criteria can be safely
2371 * ignored, we save/restore all others, practically treating the HW context as
2372 * a black-box for the driver. Further investigation is needed to reduce the
2373 * saved/restored registers even further, by following the same 3 criteria.
2374 */
2375static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2376{
2377 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2378 int i;
2379
2380 /* GAM 0x4000-0x4770 */
2381 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2382 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2383 s->arb_mode = I915_READ(ARB_MODE);
2384 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
2385 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
2386
2387 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2388 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
ddeea5b0
ID		 2389
2390 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
b5f1c97f 2391 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
ddeea5b0
ID		 2392
2393 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
2394 s->ecochk = I915_READ(GAM_ECOCHK);
2395 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
2396 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
2397
2398 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
2399
2400 /* MBC 0x9024-0x91D0, 0x8500 */
2401 s->g3dctl = I915_READ(VLV_G3DCTL);
2402 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
2403 s->mbctl = I915_READ(GEN6_MBCTL);
2404
2405 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2406 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
2407 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
2408 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
2409 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
2410 s->rstctl = I915_READ(GEN6_RSTCTL);
2411 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
2412
2413 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2414 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
2415 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
2416 s->rpdeuc = I915_READ(GEN6_RPDEUC);
2417 s->ecobus = I915_READ(ECOBUS);
2418 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
2419 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2420 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
2421 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
2422 s->rcedata = I915_READ(VLV_RCEDATA);
2423 s->spare2gh = I915_READ(VLV_SPAREG2H);
2424
2425 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2426 s->gt_imr = I915_READ(GTIMR);
2427 s->gt_ier = I915_READ(GTIER);
2428 s->pm_imr = I915_READ(GEN6_PMIMR);
2429 s->pm_ier = I915_READ(GEN6_PMIER);
2430
2431 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2432 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
ddeea5b0
ID		 2433
2434 /* GT SA CZ domain, 0x100000-0x138124 */
2435 s->tilectl = I915_READ(TILECTL);
2436 s->gt_fifoctl = I915_READ(GTFIFOCTL);
2437 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
2438 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2439 s->pmwgicz = I915_READ(VLV_PMWGICZ);
2440
2441 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2442 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
2443 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
9c25210f 2444 s->pcbr = I915_READ(VLV_PCBR);
ddeea5b0
ID		 2445 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2446
2447 /*
2448 * Not saving any of:
2449 * DFT, 0x9800-0x9EC0
2450 * SARB, 0xB000-0xB1FC
2451 * GAC, 0x5208-0x524C, 0x14000-0x14C000
2452 * PCI CFG
2453 */
2454}
2455
2456static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2457{
2458 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2459 u32 val;
2460 int i;
2461
2462 /* GAM 0x4000-0x4770 */
2463 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
2464 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
2465 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
2466 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
2467 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
2468
2469 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
22dfe79f 2470 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
ddeea5b0
ID		 2471
2472 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
b5f1c97f 2473 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
ddeea5b0
ID		 2474
2475 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2476 I915_WRITE(GAM_ECOCHK, s->ecochk);
2477 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
2478 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
2479
2480 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
2481
2482 /* MBC 0x9024-0x91D0, 0x8500 */
2483 I915_WRITE(VLV_G3DCTL, s->g3dctl);
2484 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
2485 I915_WRITE(GEN6_MBCTL, s->mbctl);
2486
2487 /* GCP 0x9400-0x9424, 0x8100-0x810C */
2488 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
2489 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
2490 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
2491 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
2492 I915_WRITE(GEN6_RSTCTL, s->rstctl);
2493 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
2494
2495 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2496 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
2497 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
2498 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
2499 I915_WRITE(ECOBUS, s->ecobus);
2500 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
2501 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2502 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
2503 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
2504 I915_WRITE(VLV_RCEDATA, s->rcedata);
2505 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
2506
2507 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2508 I915_WRITE(GTIMR, s->gt_imr);
2509 I915_WRITE(GTIER, s->gt_ier);
2510 I915_WRITE(GEN6_PMIMR, s->pm_imr);
2511 I915_WRITE(GEN6_PMIER, s->pm_ier);
2512
2513 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
22dfe79f 2514 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
ddeea5b0
ID		 2515
2516 /* GT SA CZ domain, 0x100000-0x138124 */
2517 I915_WRITE(TILECTL, s->tilectl);
2518 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
2519 /*
2520 * Preserve the GT allow wake and GFX force clock bit, they are not
2521 * be restored, as they are used to control the s0ix suspend/resume
2522 * sequence by the caller.
2523 */
2524 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2525 val &= VLV_GTLC_ALLOWWAKEREQ;
2526 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2527 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2528
2529 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2530 val &= VLV_GFX_CLK_FORCE_ON_BIT;
2531 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2532 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2533
2534 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
2535
2536 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2537 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
2538 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
9c25210f 2539 I915_WRITE(VLV_PCBR, s->pcbr);
ddeea5b0
ID		 2540 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
2541}
2542
3dd14c04
CW		 2543static int vlv_wait_for_pw_status(struct drm_i915_private *dev_priv,
2544 u32 mask, u32 val)
2545{
39806c3f
VS		 2546 i915_reg_t reg = VLV_GTLC_PW_STATUS;
2547 u32 reg_value;
2548 int ret;
2549
3dd14c04
CW		 2550 /* The HW does not like us polling for PW_STATUS frequently, so
2551 * use the sleeping loop rather than risk the busy spin within
2552 * intel_wait_for_register().
2553 *
2554 * Transitioning between RC6 states should be at most 2ms (see
2555 * valleyview_enable_rps) so use a 3ms timeout.
2556 */
39806c3f
VS		 2557 ret = wait_for(((reg_value = I915_READ_NOTRACE(reg)) & mask) == val, 3);
2558
2559 /* just trace the final value */
2560 trace_i915_reg_rw(false, reg, reg_value, sizeof(reg_value), true);
2561
2562 return ret;
3dd14c04
CW		 2563}
2564
650ad970
ID		 2565int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2566{
2567 u32 val;
2568 int err;
2569
650ad970
ID		 2570 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2571 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2572 if (force_on)
2573 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2574 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2575
2576 if (!force_on)
2577 return 0;
2578
c6ddc5f3
CW		 2579 err = intel_wait_for_register(dev_priv,
2580 VLV_GTLC_SURVIVABILITY_REG,
2581 VLV_GFX_CLK_STATUS_BIT,
2582 VLV_GFX_CLK_STATUS_BIT,
2583 20);
650ad970
ID		 2584 if (err)
2585 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2586 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2587
2588 return err;
650ad970
ID		 2589}
2590
ddeea5b0
ID		 2591static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2592{
3dd14c04 2593 u32 mask;
ddeea5b0 2594 u32 val;
3dd14c04 2595 int err;
ddeea5b0
ID		 2596
2597 val = I915_READ(VLV_GTLC_WAKE_CTRL);
2598 val &= ~VLV_GTLC_ALLOWWAKEREQ;
2599 if (allow)
2600 val |= VLV_GTLC_ALLOWWAKEREQ;
2601 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2602 POSTING_READ(VLV_GTLC_WAKE_CTRL);
2603
3dd14c04
CW		 2604 mask = VLV_GTLC_ALLOWWAKEACK;
2605 val = allow ? mask : 0;
2606
2607 err = vlv_wait_for_pw_status(dev_priv, mask, val);
ddeea5b0
ID		 2608 if (err)
2609 DRM_ERROR("timeout disabling GT waking\n");
b2736695 2610
ddeea5b0 2611 return err;
ddeea5b0
ID		 2612}
2613
3dd14c04
CW		 2614static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2615 bool wait_for_on)
ddeea5b0
ID		 2616{
2617 u32 mask;
2618 u32 val;
ddeea5b0
ID		 2619
2620 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2621 val = wait_for_on ? mask : 0;
ddeea5b0
ID		 2622
2623 /*
2624 * RC6 transitioning can be delayed up to 2 msec (see
2625 * valleyview_enable_rps), use 3 msec for safety.
e01569ab
CW		 2626 *
2627 * This can fail to turn off the rc6 if the GPU is stuck after a failed
2628 * reset and we are trying to force the machine to sleep.
ddeea5b0 2629 */
3dd14c04 2630 if (vlv_wait_for_pw_status(dev_priv, mask, val))
e01569ab
CW		 2631 DRM_DEBUG_DRIVER("timeout waiting for GT wells to go %s\n",
2632 onoff(wait_for_on));
ddeea5b0
ID		 2633}
2634
2635static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2636{
2637 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2638 return;
2639
6fa283b0 2640 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
ddeea5b0
ID		 2641 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2642}
2643
ebc32824 2644static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
ddeea5b0
ID		 2645{
2646 u32 mask;
2647 int err;
2648
2649 /*
2650 * Bspec defines the following GT well on flags as debug only, so
2651 * don't treat them as hard failures.
2652 */
3dd14c04 2653 vlv_wait_for_gt_wells(dev_priv, false);
ddeea5b0
ID		 2654
2655 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2656 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2657
2658 vlv_check_no_gt_access(dev_priv);
2659
2660 err = vlv_force_gfx_clock(dev_priv, true);
2661 if (err)
2662 goto err1;
2663
2664 err = vlv_allow_gt_wake(dev_priv, false);
2665 if (err)
2666 goto err2;
98711167 2667
2d1fe073 2668 if (!IS_CHERRYVIEW(dev_priv))
98711167 2669 vlv_save_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2670
2671 err = vlv_force_gfx_clock(dev_priv, false);
2672 if (err)
2673 goto err2;
2674
2675 return 0;
2676
2677err2:
2678 /* For safety always re-enable waking and disable gfx clock forcing */
2679 vlv_allow_gt_wake(dev_priv, true);
2680err1:
2681 vlv_force_gfx_clock(dev_priv, false);
2682
2683 return err;
2684}
2685
016970be
SK		 2686static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2687 bool rpm_resume)
ddeea5b0 2688{
ddeea5b0
ID		 2689 int err;
2690 int ret;
2691
2692 /*
2693 * If any of the steps fail just try to continue, that's the best we
2694 * can do at this point. Return the first error code (which will also
2695 * leave RPM permanently disabled).
2696 */
2697 ret = vlv_force_gfx_clock(dev_priv, true);
2698
2d1fe073 2699 if (!IS_CHERRYVIEW(dev_priv))
98711167 2700 vlv_restore_gunit_s0ix_state(dev_priv);
ddeea5b0
ID		 2701
2702 err = vlv_allow_gt_wake(dev_priv, true);
2703 if (!ret)
2704 ret = err;
2705
2706 err = vlv_force_gfx_clock(dev_priv, false);
2707 if (!ret)
2708 ret = err;
2709
2710 vlv_check_no_gt_access(dev_priv);
2711
7c108fd8 2712 if (rpm_resume)
46f16e63 2713 intel_init_clock_gating(dev_priv);
ddeea5b0
ID		 2714
2715 return ret;
2716}
2717
c49d13ee 2718static int intel_runtime_suspend(struct device *kdev)
8a187455 2719{
c49d13ee 2720 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2721 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2722 struct drm_i915_private *dev_priv = to_i915(dev);
0ab9cfeb 2723 int ret;
8a187455 2724
fb6db0f5 2725 if (WARN_ON_ONCE(!(dev_priv->gt_pm.rc6.enabled && HAS_RC6(dev_priv))))
c6df39b5
ID		 2726 return -ENODEV;
2727
6772ffe0 2728 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7
ID		 2729 return -ENODEV;
2730
8a187455
PZ		 2731 DRM_DEBUG_KMS("Suspending device\n");
2732
1f814dac
ID		 2733 disable_rpm_wakeref_asserts(dev_priv);
2734
d6102977
ID		 2735 /*
2736 * We are safe here against re-faults, since the fault handler takes
2737 * an RPM reference.
2738 */
7c108fd8 2739 i915_gem_runtime_suspend(dev_priv);
d6102977 2740
7cfca4af 2741 intel_uc_suspend(dev_priv);
a1c41994 2742
2eb5252e 2743 intel_runtime_pm_disable_interrupts(dev_priv);
b5478bcd 2744
01c799c9
HG		 2745 intel_uncore_suspend(dev_priv);
2746
507e126e 2747 ret = 0;
3e68928b
AM		 2748 if (INTEL_GEN(dev_priv) >= 11) {
2749 icl_display_core_uninit(dev_priv);
2750 bxt_enable_dc9(dev_priv);
2751 } else if (IS_GEN9_LP(dev_priv)) {
507e126e
ID		 2752 bxt_display_core_uninit(dev_priv);
2753 bxt_enable_dc9(dev_priv);
2754 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2755 hsw_enable_pc8(dev_priv);
2756 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2757 ret = vlv_suspend_complete(dev_priv);
2758 }
2759
0ab9cfeb
ID		 2760 if (ret) {
2761 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
01c799c9
HG		 2762 intel_uncore_runtime_resume(dev_priv);
2763
b963291c 2764 intel_runtime_pm_enable_interrupts(dev_priv);
0ab9cfeb 2765
7cfca4af 2766 intel_uc_resume(dev_priv);
1ed21cb4
SAK		 2767
2768 i915_gem_init_swizzling(dev_priv);
2769 i915_gem_restore_fences(dev_priv);
2770
1f814dac
ID		 2771 enable_rpm_wakeref_asserts(dev_priv);
2772
0ab9cfeb
ID		 2773 return ret;
2774 }
a8a8bd54 2775
1f814dac 2776 enable_rpm_wakeref_asserts(dev_priv);
bd780f37 2777 intel_runtime_pm_cleanup(dev_priv);
55ec45c2 2778
bc3b9346 2779 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
55ec45c2
MK		 2780 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2781
ad1443f0 2782 dev_priv->runtime_pm.suspended = true;
1fb2362b
KCA		 2783
2784 /*
c8a0bd42
PZ		 2785 * FIXME: We really should find a document that references the arguments
2786 * used below!
1fb2362b 2787 */
6f9f4b7a 2788 if (IS_BROADWELL(dev_priv)) {
d37ae19a
PZ		 2789 /*
2790 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2791 * being detected, and the call we do at intel_runtime_resume()
2792 * won't be able to restore them. Since PCI_D3hot matches the
2793 * actual specification and appears to be working, use it.
2794 */
6f9f4b7a 2795 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
d37ae19a 2796 } else {
c8a0bd42
PZ		 2797 /*
2798 * current versions of firmware which depend on this opregion
2799 * notification have repurposed the D1 definition to mean
2800 * "runtime suspended" vs. what you would normally expect (D3)
2801 * to distinguish it from notifications that might be sent via
2802 * the suspend path.
2803 */
6f9f4b7a 2804 intel_opregion_notify_adapter(dev_priv, PCI_D1);
c8a0bd42 2805 }
8a187455 2806
59bad947 2807 assert_forcewakes_inactive(dev_priv);
dc9fb09c 2808
21d6e0bd 2809 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
19625e85
L		 2810 intel_hpd_poll_init(dev_priv);
2811
a8a8bd54 2812 DRM_DEBUG_KMS("Device suspended\n");
8a187455
PZ		 2813 return 0;
2814}
2815
c49d13ee 2816static int intel_runtime_resume(struct device *kdev)
8a187455 2817{
c49d13ee 2818 struct pci_dev *pdev = to_pci_dev(kdev);
8a187455 2819 struct drm_device *dev = pci_get_drvdata(pdev);
fac5e23e 2820 struct drm_i915_private *dev_priv = to_i915(dev);
1a5df187 2821 int ret = 0;
8a187455 2822
6772ffe0 2823 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev_priv)))
604effb7 2824 return -ENODEV;
8a187455
PZ		 2825
2826 DRM_DEBUG_KMS("Resuming device\n");
2827
ad1443f0 2828 WARN_ON_ONCE(atomic_read(&dev_priv->runtime_pm.wakeref_count));
1f814dac
ID		 2829 disable_rpm_wakeref_asserts(dev_priv);
2830
6f9f4b7a 2831 intel_opregion_notify_adapter(dev_priv, PCI_D0);
ad1443f0 2832 dev_priv->runtime_pm.suspended = false;
55ec45c2
MK		 2833 if (intel_uncore_unclaimed_mmio(dev_priv))
2834 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
8a187455 2835
3e68928b
AM		 2836 if (INTEL_GEN(dev_priv) >= 11) {
2837 bxt_disable_dc9(dev_priv);
2838 icl_display_core_init(dev_priv, true);
2839 if (dev_priv->csr.dmc_payload) {
2840 if (dev_priv->csr.allowed_dc_mask &
2841 DC_STATE_EN_UPTO_DC6)
2842 skl_enable_dc6(dev_priv);
2843 else if (dev_priv->csr.allowed_dc_mask &
2844 DC_STATE_EN_UPTO_DC5)
2845 gen9_enable_dc5(dev_priv);
2846 }
2847 } else if (IS_GEN9_LP(dev_priv)) {
507e126e
ID		 2848 bxt_disable_dc9(dev_priv);
2849 bxt_display_core_init(dev_priv, true);
f62c79b3
ID		 2850 if (dev_priv->csr.dmc_payload &&
2851 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2852 gen9_enable_dc5(dev_priv);
507e126e 2853 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1a5df187 2854 hsw_disable_pc8(dev_priv);
507e126e 2855 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1a5df187 2856 ret = vlv_resume_prepare(dev_priv, true);
507e126e 2857 }
1a5df187 2858
bedf4d79
HG		 2859 intel_uncore_runtime_resume(dev_priv);
2860
1ed21cb4
SAK		 2861 intel_runtime_pm_enable_interrupts(dev_priv);
2862
7cfca4af 2863 intel_uc_resume(dev_priv);
1ed21cb4 2864
0ab9cfeb
ID		 2865 /*
2866 * No point of rolling back things in case of an error, as the best
2867 * we can do is to hope that things will still work (and disable RPM).
2868 */
c6be607a 2869 i915_gem_init_swizzling(dev_priv);
83bf6d55 2870 i915_gem_restore_fences(dev_priv);
92b806d3 2871
08d8a232
VS		 2872 /*
2873 * On VLV/CHV display interrupts are part of the display
2874 * power well, so hpd is reinitialized from there. For
2875 * everyone else do it here.
2876 */
666a4537 2877 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
08d8a232
VS		 2878 intel_hpd_init(dev_priv);
2879
2503a0fe
KM		 2880 intel_enable_ipc(dev_priv);
2881
1f814dac
ID		 2882 enable_rpm_wakeref_asserts(dev_priv);
2883
0ab9cfeb
ID		 2884 if (ret)
2885 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2886 else
2887 DRM_DEBUG_KMS("Device resumed\n");
2888
2889 return ret;
8a187455
PZ		 2890}
2891
42f5551d 2892const struct dev_pm_ops i915_pm_ops = {
5545dbbf
ID		 2893 /*
2894 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2895 * PMSG_RESUME]
2896 */
73b66f87 2897 .prepare = i915_pm_prepare,
0206e353 2898 .suspend = i915_pm_suspend,
76c4b250
ID		 2899 .suspend_late = i915_pm_suspend_late,
2900 .resume_early = i915_pm_resume_early,
0206e353 2901 .resume = i915_pm_resume,
5545dbbf
ID		 2902
2903 /*
2904 * S4 event handlers
2905 * @freeze, @freeze_late : called (1) before creating the
2906 * hibernation image [PMSG_FREEZE] and
2907 * (2) after rebooting, before restoring
2908 * the image [PMSG_QUIESCE]
2909 * @thaw, @thaw_early : called (1) after creating the hibernation
2910 * image, before writing it [PMSG_THAW]
2911 * and (2) after failing to create or
2912 * restore the image [PMSG_RECOVER]
2913 * @poweroff, @poweroff_late: called after writing the hibernation
2914 * image, before rebooting [PMSG_HIBERNATE]
2915 * @restore, @restore_early : called after rebooting and restoring the
2916 * hibernation image [PMSG_RESTORE]
2917 */
1f19ac2a
CW		 2918 .freeze = i915_pm_freeze,
2919 .freeze_late = i915_pm_freeze_late,
2920 .thaw_early = i915_pm_thaw_early,
2921 .thaw = i915_pm_thaw,
36d61e67 2922 .poweroff = i915_pm_suspend,
ab3be73f 2923 .poweroff_late = i915_pm_poweroff_late,
1f19ac2a
CW		 2924 .restore_early = i915_pm_restore_early,
2925 .restore = i915_pm_restore,
5545dbbf
ID		 2926
2927 /* S0ix (via runtime suspend) event handlers */
97bea207
PZ		 2928 .runtime_suspend = intel_runtime_suspend,
2929 .runtime_resume = intel_runtime_resume,
cbda12d7
ZW		 2930};
2931
78b68556 2932static const struct vm_operations_struct i915_gem_vm_ops = {
de151cf6 2933 .fault = i915_gem_fault,
ab00b3e5
JB		 2934 .open = drm_gem_vm_open,
2935 .close = drm_gem_vm_close,
de151cf6
JB		 2936};
2937
e08e96de
AV		 2938static const struct file_operations i915_driver_fops = {
2939 .owner = THIS_MODULE,
2940 .open = drm_open,
2941 .release = drm_release,
2942 .unlocked_ioctl = drm_ioctl,
2943 .mmap = drm_gem_mmap,
2944 .poll = drm_poll,
e08e96de 2945 .read = drm_read,
e08e96de 2946 .compat_ioctl = i915_compat_ioctl,
e08e96de
AV		 2947 .llseek = noop_llseek,
2948};
2949
0673ad47
CW		 2950static int
2951i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2952 struct drm_file *file)
2953{
2954 return -ENODEV;
2955}
2956
2957static const struct drm_ioctl_desc i915_ioctls[] = {
2958 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2959 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2960 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2961 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2962 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2963 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
6a20fe7b 2964 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0673ad47
CW		 2965 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2966 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2967 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2968 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2969 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2970 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2971 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2972 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
2973 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2974 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2975 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
6a20fe7b
VS		 2976 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
2977 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
0673ad47
CW		 2978 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2979 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2980 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2981 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2982 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2983 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2984 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2985 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2986 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2987 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2988 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2989 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2990 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2991 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2992 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
111dbcab
CW		 2993 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
2994 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
0673ad47 2995 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
6a20fe7b 2996 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
0673ad47 2997 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
0cd54b03
SV		 2998 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
2999 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
3000 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
3001 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
0673ad47
CW		 3002 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
3003 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
3004 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
3005 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
3006 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
3007 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
3008 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
3009 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
eec688e1 3010 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
f89823c2
LL		 3011 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
3012 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
a446ae2c 3013 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
0673ad47
CW		 3014};
3015
1da177e4 3016static struct drm_driver driver = {
0c54781b
MW		 3017 /* Don't use MTRRs here; the Xserver or userspace app should
3018 * deal with them for Intel hardware.
792d2b9a 3019 */
673a394b 3020 .driver_features =
1ff49481 3021 DRIVER_GEM | DRIVER_PRIME |
cf6e7bac 3022 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
cad3688f 3023 .release = i915_driver_release,
673a394b 3024 .open = i915_driver_open,
22eae947 3025 .lastclose = i915_driver_lastclose,
673a394b 3026 .postclose = i915_driver_postclose,
d8e29209 3027
b1f788c6 3028 .gem_close_object = i915_gem_close_object,
f0cd5182 3029 .gem_free_object_unlocked = i915_gem_free_object,
de151cf6 3030 .gem_vm_ops = &i915_gem_vm_ops,
1286ff73
SV		 3031
3032 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
3033 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
3034 .gem_prime_export = i915_gem_prime_export,
3035 .gem_prime_import = i915_gem_prime_import,
3036
ff72145b 3037 .dumb_create = i915_gem_dumb_create,
da6b51d0 3038 .dumb_map_offset = i915_gem_mmap_gtt,
1da177e4 3039 .ioctls = i915_ioctls,
0673ad47 3040 .num_ioctls = ARRAY_SIZE(i915_ioctls),
e08e96de 3041 .fops = &i915_driver_fops,
22eae947
DA		 3042 .name = DRIVER_NAME,
3043 .desc = DRIVER_DESC,
3044 .date = DRIVER_DATE,
3045 .major = DRIVER_MAJOR,
3046 .minor = DRIVER_MINOR,
3047 .patchlevel = DRIVER_PATCHLEVEL,
1da177e4 3048};
66d9cb5d
CW		 3049
3050#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3051#include "selftests/mock_drm.c"
3052#endif
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git