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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
673a394b | 37 | |
0f8c6d7c CW |
38 | struct change_domains { |
39 | uint32_t invalidate_domains; | |
40 | uint32_t flush_domains; | |
41 | uint32_t flush_rings; | |
42 | }; | |
43 | ||
05394f39 | 44 | static int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj, |
919926ae | 45 | struct intel_ring_buffer *pipelined); |
05394f39 CW |
46 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
47 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
48 | static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, | |
919926ae | 49 | bool write); |
05394f39 | 50 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
51 | uint64_t offset, |
52 | uint64_t size); | |
05394f39 CW |
53 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
54 | static int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
2cf34d7b | 55 | bool interruptible); |
05394f39 | 56 | static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
a00b10c3 | 57 | unsigned alignment, |
75e9e915 | 58 | bool map_and_fenceable); |
05394f39 CW |
59 | static void i915_gem_clear_fence_reg(struct drm_i915_gem_object *obj); |
60 | static int i915_gem_phys_pwrite(struct drm_device *dev, | |
61 | struct drm_i915_gem_object *obj, | |
71acb5eb | 62 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
63 | struct drm_file *file); |
64 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 65 | |
17250b71 CW |
66 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
67 | int nr_to_scan, | |
68 | gfp_t gfp_mask); | |
69 | ||
31169714 | 70 | |
73aa808f CW |
71 | /* some bookkeeping */ |
72 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
73 | size_t size) | |
74 | { | |
75 | dev_priv->mm.object_count++; | |
76 | dev_priv->mm.object_memory += size; | |
77 | } | |
78 | ||
79 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
80 | size_t size) | |
81 | { | |
82 | dev_priv->mm.object_count--; | |
83 | dev_priv->mm.object_memory -= size; | |
84 | } | |
85 | ||
86 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, | |
a00b10c3 | 87 | struct drm_i915_gem_object *obj) |
73aa808f CW |
88 | { |
89 | dev_priv->mm.gtt_count++; | |
a00b10c3 CW |
90 | dev_priv->mm.gtt_memory += obj->gtt_space->size; |
91 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
fb7d516a | 92 | dev_priv->mm.mappable_gtt_used += |
a00b10c3 CW |
93 | min_t(size_t, obj->gtt_space->size, |
94 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); | |
fb7d516a | 95 | } |
93a37f20 | 96 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
73aa808f CW |
97 | } |
98 | ||
99 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, | |
a00b10c3 | 100 | struct drm_i915_gem_object *obj) |
73aa808f CW |
101 | { |
102 | dev_priv->mm.gtt_count--; | |
a00b10c3 CW |
103 | dev_priv->mm.gtt_memory -= obj->gtt_space->size; |
104 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
fb7d516a | 105 | dev_priv->mm.mappable_gtt_used -= |
a00b10c3 CW |
106 | min_t(size_t, obj->gtt_space->size, |
107 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); | |
fb7d516a | 108 | } |
93a37f20 | 109 | list_del_init(&obj->gtt_list); |
fb7d516a DV |
110 | } |
111 | ||
112 | /** | |
113 | * Update the mappable working set counters. Call _only_ when there is a change | |
114 | * in one of (pin|fault)_mappable and update *_mappable _before_ calling. | |
115 | * @mappable: new state the changed mappable flag (either pin_ or fault_). | |
116 | */ | |
117 | static void | |
118 | i915_gem_info_update_mappable(struct drm_i915_private *dev_priv, | |
a00b10c3 | 119 | struct drm_i915_gem_object *obj, |
fb7d516a DV |
120 | bool mappable) |
121 | { | |
fb7d516a | 122 | if (mappable) { |
a00b10c3 | 123 | if (obj->pin_mappable && obj->fault_mappable) |
fb7d516a DV |
124 | /* Combined state was already mappable. */ |
125 | return; | |
126 | dev_priv->mm.gtt_mappable_count++; | |
a00b10c3 | 127 | dev_priv->mm.gtt_mappable_memory += obj->gtt_space->size; |
fb7d516a | 128 | } else { |
a00b10c3 | 129 | if (obj->pin_mappable || obj->fault_mappable) |
fb7d516a DV |
130 | /* Combined state still mappable. */ |
131 | return; | |
132 | dev_priv->mm.gtt_mappable_count--; | |
a00b10c3 | 133 | dev_priv->mm.gtt_mappable_memory -= obj->gtt_space->size; |
fb7d516a | 134 | } |
73aa808f CW |
135 | } |
136 | ||
137 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, | |
a00b10c3 | 138 | struct drm_i915_gem_object *obj, |
fb7d516a | 139 | bool mappable) |
73aa808f CW |
140 | { |
141 | dev_priv->mm.pin_count++; | |
a00b10c3 | 142 | dev_priv->mm.pin_memory += obj->gtt_space->size; |
fb7d516a | 143 | if (mappable) { |
a00b10c3 | 144 | obj->pin_mappable = true; |
fb7d516a DV |
145 | i915_gem_info_update_mappable(dev_priv, obj, true); |
146 | } | |
73aa808f CW |
147 | } |
148 | ||
149 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, | |
a00b10c3 | 150 | struct drm_i915_gem_object *obj) |
73aa808f CW |
151 | { |
152 | dev_priv->mm.pin_count--; | |
a00b10c3 CW |
153 | dev_priv->mm.pin_memory -= obj->gtt_space->size; |
154 | if (obj->pin_mappable) { | |
155 | obj->pin_mappable = false; | |
fb7d516a DV |
156 | i915_gem_info_update_mappable(dev_priv, obj, false); |
157 | } | |
73aa808f CW |
158 | } |
159 | ||
30dbf0c0 CW |
160 | int |
161 | i915_gem_check_is_wedged(struct drm_device *dev) | |
162 | { | |
163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
164 | struct completion *x = &dev_priv->error_completion; | |
165 | unsigned long flags; | |
166 | int ret; | |
167 | ||
168 | if (!atomic_read(&dev_priv->mm.wedged)) | |
169 | return 0; | |
170 | ||
171 | ret = wait_for_completion_interruptible(x); | |
172 | if (ret) | |
173 | return ret; | |
174 | ||
175 | /* Success, we reset the GPU! */ | |
176 | if (!atomic_read(&dev_priv->mm.wedged)) | |
177 | return 0; | |
178 | ||
179 | /* GPU is hung, bump the completion count to account for | |
180 | * the token we just consumed so that we never hit zero and | |
181 | * end up waiting upon a subsequent completion event that | |
182 | * will never happen. | |
183 | */ | |
184 | spin_lock_irqsave(&x->wait.lock, flags); | |
185 | x->done++; | |
186 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
187 | return -EIO; | |
188 | } | |
189 | ||
76c1dec1 CW |
190 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
191 | { | |
192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
193 | int ret; | |
194 | ||
195 | ret = i915_gem_check_is_wedged(dev); | |
196 | if (ret) | |
197 | return ret; | |
198 | ||
199 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
200 | if (ret) | |
201 | return ret; | |
202 | ||
203 | if (atomic_read(&dev_priv->mm.wedged)) { | |
204 | mutex_unlock(&dev->struct_mutex); | |
205 | return -EAGAIN; | |
206 | } | |
207 | ||
23bc5982 | 208 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
209 | return 0; |
210 | } | |
30dbf0c0 | 211 | |
7d1c4804 | 212 | static inline bool |
05394f39 | 213 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 214 | { |
05394f39 | 215 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
216 | } |
217 | ||
2021746e CW |
218 | void i915_gem_do_init(struct drm_device *dev, |
219 | unsigned long start, | |
220 | unsigned long mappable_end, | |
221 | unsigned long end) | |
673a394b EA |
222 | { |
223 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 224 | |
79e53945 JB |
225 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
226 | end - start); | |
673a394b | 227 | |
73aa808f | 228 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 229 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
53984635 | 230 | dev_priv->mm.gtt_mappable_end = mappable_end; |
79e53945 | 231 | } |
673a394b | 232 | |
79e53945 JB |
233 | int |
234 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 235 | struct drm_file *file) |
79e53945 JB |
236 | { |
237 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
238 | |
239 | if (args->gtt_start >= args->gtt_end || | |
240 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
241 | return -EINVAL; | |
79e53945 JB |
242 | |
243 | mutex_lock(&dev->struct_mutex); | |
2021746e | 244 | i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
245 | mutex_unlock(&dev->struct_mutex); |
246 | ||
2021746e | 247 | return 0; |
673a394b EA |
248 | } |
249 | ||
5a125c3c EA |
250 | int |
251 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 252 | struct drm_file *file) |
5a125c3c | 253 | { |
73aa808f | 254 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 255 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
256 | |
257 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
258 | return -ENODEV; | |
259 | ||
73aa808f CW |
260 | mutex_lock(&dev->struct_mutex); |
261 | args->aper_size = dev_priv->mm.gtt_total; | |
262 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; | |
263 | mutex_unlock(&dev->struct_mutex); | |
5a125c3c EA |
264 | |
265 | return 0; | |
266 | } | |
267 | ||
673a394b EA |
268 | |
269 | /** | |
270 | * Creates a new mm object and returns a handle to it. | |
271 | */ | |
272 | int | |
273 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 274 | struct drm_file *file) |
673a394b EA |
275 | { |
276 | struct drm_i915_gem_create *args = data; | |
05394f39 | 277 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
278 | int ret; |
279 | u32 handle; | |
673a394b EA |
280 | |
281 | args->size = roundup(args->size, PAGE_SIZE); | |
282 | ||
283 | /* Allocate the new object */ | |
ac52bc56 | 284 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
285 | if (obj == NULL) |
286 | return -ENOMEM; | |
287 | ||
05394f39 | 288 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 289 | if (ret) { |
05394f39 CW |
290 | drm_gem_object_release(&obj->base); |
291 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 292 | kfree(obj); |
673a394b | 293 | return ret; |
1dfd9754 | 294 | } |
673a394b | 295 | |
202f2fef | 296 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 297 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
298 | trace_i915_gem_object_create(obj); |
299 | ||
1dfd9754 | 300 | args->handle = handle; |
673a394b EA |
301 | return 0; |
302 | } | |
303 | ||
05394f39 | 304 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 305 | { |
05394f39 | 306 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
307 | |
308 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 309 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
310 | } |
311 | ||
99a03df5 | 312 | static inline void |
40123c1f EA |
313 | slow_shmem_copy(struct page *dst_page, |
314 | int dst_offset, | |
315 | struct page *src_page, | |
316 | int src_offset, | |
317 | int length) | |
318 | { | |
319 | char *dst_vaddr, *src_vaddr; | |
320 | ||
99a03df5 CW |
321 | dst_vaddr = kmap(dst_page); |
322 | src_vaddr = kmap(src_page); | |
40123c1f EA |
323 | |
324 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
325 | ||
99a03df5 CW |
326 | kunmap(src_page); |
327 | kunmap(dst_page); | |
40123c1f EA |
328 | } |
329 | ||
99a03df5 | 330 | static inline void |
280b713b EA |
331 | slow_shmem_bit17_copy(struct page *gpu_page, |
332 | int gpu_offset, | |
333 | struct page *cpu_page, | |
334 | int cpu_offset, | |
335 | int length, | |
336 | int is_read) | |
337 | { | |
338 | char *gpu_vaddr, *cpu_vaddr; | |
339 | ||
340 | /* Use the unswizzled path if this page isn't affected. */ | |
341 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
342 | if (is_read) | |
343 | return slow_shmem_copy(cpu_page, cpu_offset, | |
344 | gpu_page, gpu_offset, length); | |
345 | else | |
346 | return slow_shmem_copy(gpu_page, gpu_offset, | |
347 | cpu_page, cpu_offset, length); | |
348 | } | |
349 | ||
99a03df5 CW |
350 | gpu_vaddr = kmap(gpu_page); |
351 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
352 | |
353 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
354 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
355 | */ | |
356 | while (length > 0) { | |
357 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
358 | int this_length = min(cacheline_end - gpu_offset, length); | |
359 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
360 | ||
361 | if (is_read) { | |
362 | memcpy(cpu_vaddr + cpu_offset, | |
363 | gpu_vaddr + swizzled_gpu_offset, | |
364 | this_length); | |
365 | } else { | |
366 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
367 | cpu_vaddr + cpu_offset, | |
368 | this_length); | |
369 | } | |
370 | cpu_offset += this_length; | |
371 | gpu_offset += this_length; | |
372 | length -= this_length; | |
373 | } | |
374 | ||
99a03df5 CW |
375 | kunmap(cpu_page); |
376 | kunmap(gpu_page); | |
280b713b EA |
377 | } |
378 | ||
eb01459f EA |
379 | /** |
380 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
381 | * from the backing pages of the object to the user's address space. On a | |
382 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
383 | */ | |
384 | static int | |
05394f39 CW |
385 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
386 | struct drm_i915_gem_object *obj, | |
eb01459f | 387 | struct drm_i915_gem_pread *args, |
05394f39 | 388 | struct drm_file *file) |
eb01459f | 389 | { |
05394f39 | 390 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 391 | ssize_t remain; |
e5281ccd | 392 | loff_t offset; |
eb01459f EA |
393 | char __user *user_data; |
394 | int page_offset, page_length; | |
eb01459f EA |
395 | |
396 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
397 | remain = args->size; | |
398 | ||
eb01459f EA |
399 | offset = args->offset; |
400 | ||
401 | while (remain > 0) { | |
e5281ccd CW |
402 | struct page *page; |
403 | char *vaddr; | |
404 | int ret; | |
405 | ||
eb01459f EA |
406 | /* Operation in this page |
407 | * | |
eb01459f EA |
408 | * page_offset = offset within page |
409 | * page_length = bytes to copy for this page | |
410 | */ | |
eb01459f EA |
411 | page_offset = offset & (PAGE_SIZE-1); |
412 | page_length = remain; | |
413 | if ((page_offset + remain) > PAGE_SIZE) | |
414 | page_length = PAGE_SIZE - page_offset; | |
415 | ||
e5281ccd CW |
416 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
417 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
418 | if (IS_ERR(page)) | |
419 | return PTR_ERR(page); | |
420 | ||
421 | vaddr = kmap_atomic(page); | |
422 | ret = __copy_to_user_inatomic(user_data, | |
423 | vaddr + page_offset, | |
424 | page_length); | |
425 | kunmap_atomic(vaddr); | |
426 | ||
427 | mark_page_accessed(page); | |
428 | page_cache_release(page); | |
429 | if (ret) | |
4f27b75d | 430 | return -EFAULT; |
eb01459f EA |
431 | |
432 | remain -= page_length; | |
433 | user_data += page_length; | |
434 | offset += page_length; | |
435 | } | |
436 | ||
4f27b75d | 437 | return 0; |
eb01459f EA |
438 | } |
439 | ||
440 | /** | |
441 | * This is the fallback shmem pread path, which allocates temporary storage | |
442 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
443 | * can copy out of the object's backing pages while holding the struct mutex | |
444 | * and not take page faults. | |
445 | */ | |
446 | static int | |
05394f39 CW |
447 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
448 | struct drm_i915_gem_object *obj, | |
eb01459f | 449 | struct drm_i915_gem_pread *args, |
05394f39 | 450 | struct drm_file *file) |
eb01459f | 451 | { |
05394f39 | 452 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f EA |
453 | struct mm_struct *mm = current->mm; |
454 | struct page **user_pages; | |
455 | ssize_t remain; | |
456 | loff_t offset, pinned_pages, i; | |
457 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd CW |
458 | int shmem_page_offset; |
459 | int data_page_index, data_page_offset; | |
eb01459f EA |
460 | int page_length; |
461 | int ret; | |
462 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 463 | int do_bit17_swizzling; |
eb01459f EA |
464 | |
465 | remain = args->size; | |
466 | ||
467 | /* Pin the user pages containing the data. We can't fault while | |
468 | * holding the struct mutex, yet we want to hold it while | |
469 | * dereferencing the user data. | |
470 | */ | |
471 | first_data_page = data_ptr / PAGE_SIZE; | |
472 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
473 | num_pages = last_data_page - first_data_page + 1; | |
474 | ||
4f27b75d | 475 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
476 | if (user_pages == NULL) |
477 | return -ENOMEM; | |
478 | ||
4f27b75d | 479 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
480 | down_read(&mm->mmap_sem); |
481 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 482 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 483 | up_read(&mm->mmap_sem); |
4f27b75d | 484 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
485 | if (pinned_pages < num_pages) { |
486 | ret = -EFAULT; | |
4f27b75d | 487 | goto out; |
eb01459f EA |
488 | } |
489 | ||
4f27b75d CW |
490 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
491 | args->offset, | |
492 | args->size); | |
07f73f69 | 493 | if (ret) |
4f27b75d | 494 | goto out; |
eb01459f | 495 | |
4f27b75d | 496 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 497 | |
eb01459f EA |
498 | offset = args->offset; |
499 | ||
500 | while (remain > 0) { | |
e5281ccd CW |
501 | struct page *page; |
502 | ||
eb01459f EA |
503 | /* Operation in this page |
504 | * | |
eb01459f EA |
505 | * shmem_page_offset = offset within page in shmem file |
506 | * data_page_index = page number in get_user_pages return | |
507 | * data_page_offset = offset with data_page_index page. | |
508 | * page_length = bytes to copy for this page | |
509 | */ | |
eb01459f EA |
510 | shmem_page_offset = offset & ~PAGE_MASK; |
511 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
512 | data_page_offset = data_ptr & ~PAGE_MASK; | |
513 | ||
514 | page_length = remain; | |
515 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
516 | page_length = PAGE_SIZE - shmem_page_offset; | |
517 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
518 | page_length = PAGE_SIZE - data_page_offset; | |
519 | ||
e5281ccd CW |
520 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
521 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
522 | if (IS_ERR(page)) | |
523 | return PTR_ERR(page); | |
524 | ||
280b713b | 525 | if (do_bit17_swizzling) { |
e5281ccd | 526 | slow_shmem_bit17_copy(page, |
280b713b | 527 | shmem_page_offset, |
99a03df5 CW |
528 | user_pages[data_page_index], |
529 | data_page_offset, | |
530 | page_length, | |
531 | 1); | |
532 | } else { | |
533 | slow_shmem_copy(user_pages[data_page_index], | |
534 | data_page_offset, | |
e5281ccd | 535 | page, |
99a03df5 CW |
536 | shmem_page_offset, |
537 | page_length); | |
280b713b | 538 | } |
eb01459f | 539 | |
e5281ccd CW |
540 | mark_page_accessed(page); |
541 | page_cache_release(page); | |
542 | ||
eb01459f EA |
543 | remain -= page_length; |
544 | data_ptr += page_length; | |
545 | offset += page_length; | |
546 | } | |
547 | ||
4f27b75d | 548 | out: |
eb01459f EA |
549 | for (i = 0; i < pinned_pages; i++) { |
550 | SetPageDirty(user_pages[i]); | |
e5281ccd | 551 | mark_page_accessed(user_pages[i]); |
eb01459f EA |
552 | page_cache_release(user_pages[i]); |
553 | } | |
8e7d2b2c | 554 | drm_free_large(user_pages); |
eb01459f EA |
555 | |
556 | return ret; | |
557 | } | |
558 | ||
673a394b EA |
559 | /** |
560 | * Reads data from the object referenced by handle. | |
561 | * | |
562 | * On error, the contents of *data are undefined. | |
563 | */ | |
564 | int | |
565 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 566 | struct drm_file *file) |
673a394b EA |
567 | { |
568 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 569 | struct drm_i915_gem_object *obj; |
35b62a89 | 570 | int ret = 0; |
673a394b | 571 | |
51311d0a CW |
572 | if (args->size == 0) |
573 | return 0; | |
574 | ||
575 | if (!access_ok(VERIFY_WRITE, | |
576 | (char __user *)(uintptr_t)args->data_ptr, | |
577 | args->size)) | |
578 | return -EFAULT; | |
579 | ||
580 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, | |
581 | args->size); | |
582 | if (ret) | |
583 | return -EFAULT; | |
584 | ||
4f27b75d | 585 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 586 | if (ret) |
4f27b75d | 587 | return ret; |
673a394b | 588 | |
05394f39 | 589 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
590 | if (obj == NULL) { |
591 | ret = -ENOENT; | |
592 | goto unlock; | |
4f27b75d | 593 | } |
673a394b | 594 | |
7dcd2499 | 595 | /* Bounds check source. */ |
05394f39 CW |
596 | if (args->offset > obj->base.size || |
597 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 598 | ret = -EINVAL; |
35b62a89 | 599 | goto out; |
ce9d419d CW |
600 | } |
601 | ||
4f27b75d CW |
602 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
603 | args->offset, | |
604 | args->size); | |
605 | if (ret) | |
e5281ccd | 606 | goto out; |
4f27b75d CW |
607 | |
608 | ret = -EFAULT; | |
609 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
05394f39 | 610 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
4f27b75d | 611 | if (ret == -EFAULT) |
05394f39 | 612 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
673a394b | 613 | |
35b62a89 | 614 | out: |
05394f39 | 615 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 616 | unlock: |
4f27b75d | 617 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 618 | return ret; |
673a394b EA |
619 | } |
620 | ||
0839ccb8 KP |
621 | /* This is the fast write path which cannot handle |
622 | * page faults in the source data | |
9b7530cc | 623 | */ |
0839ccb8 KP |
624 | |
625 | static inline int | |
626 | fast_user_write(struct io_mapping *mapping, | |
627 | loff_t page_base, int page_offset, | |
628 | char __user *user_data, | |
629 | int length) | |
9b7530cc | 630 | { |
9b7530cc | 631 | char *vaddr_atomic; |
0839ccb8 | 632 | unsigned long unwritten; |
9b7530cc | 633 | |
3e4d3af5 | 634 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
635 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
636 | user_data, length); | |
3e4d3af5 | 637 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 638 | return unwritten; |
0839ccb8 KP |
639 | } |
640 | ||
641 | /* Here's the write path which can sleep for | |
642 | * page faults | |
643 | */ | |
644 | ||
ab34c226 | 645 | static inline void |
3de09aa3 EA |
646 | slow_kernel_write(struct io_mapping *mapping, |
647 | loff_t gtt_base, int gtt_offset, | |
648 | struct page *user_page, int user_offset, | |
649 | int length) | |
0839ccb8 | 650 | { |
ab34c226 CW |
651 | char __iomem *dst_vaddr; |
652 | char *src_vaddr; | |
0839ccb8 | 653 | |
ab34c226 CW |
654 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
655 | src_vaddr = kmap(user_page); | |
656 | ||
657 | memcpy_toio(dst_vaddr + gtt_offset, | |
658 | src_vaddr + user_offset, | |
659 | length); | |
660 | ||
661 | kunmap(user_page); | |
662 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
663 | } |
664 | ||
3de09aa3 EA |
665 | /** |
666 | * This is the fast pwrite path, where we copy the data directly from the | |
667 | * user into the GTT, uncached. | |
668 | */ | |
673a394b | 669 | static int |
05394f39 CW |
670 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
671 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 672 | struct drm_i915_gem_pwrite *args, |
05394f39 | 673 | struct drm_file *file) |
673a394b | 674 | { |
0839ccb8 | 675 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 676 | ssize_t remain; |
0839ccb8 | 677 | loff_t offset, page_base; |
673a394b | 678 | char __user *user_data; |
0839ccb8 | 679 | int page_offset, page_length; |
673a394b EA |
680 | |
681 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
682 | remain = args->size; | |
673a394b | 683 | |
05394f39 | 684 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
685 | |
686 | while (remain > 0) { | |
687 | /* Operation in this page | |
688 | * | |
0839ccb8 KP |
689 | * page_base = page offset within aperture |
690 | * page_offset = offset within page | |
691 | * page_length = bytes to copy for this page | |
673a394b | 692 | */ |
0839ccb8 KP |
693 | page_base = (offset & ~(PAGE_SIZE-1)); |
694 | page_offset = offset & (PAGE_SIZE-1); | |
695 | page_length = remain; | |
696 | if ((page_offset + remain) > PAGE_SIZE) | |
697 | page_length = PAGE_SIZE - page_offset; | |
698 | ||
0839ccb8 | 699 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
700 | * source page isn't available. Return the error and we'll |
701 | * retry in the slow path. | |
0839ccb8 | 702 | */ |
fbd5a26d CW |
703 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
704 | page_offset, user_data, page_length)) | |
705 | ||
706 | return -EFAULT; | |
673a394b | 707 | |
0839ccb8 KP |
708 | remain -= page_length; |
709 | user_data += page_length; | |
710 | offset += page_length; | |
673a394b | 711 | } |
673a394b | 712 | |
fbd5a26d | 713 | return 0; |
673a394b EA |
714 | } |
715 | ||
3de09aa3 EA |
716 | /** |
717 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
718 | * the memory and maps it using kmap_atomic for copying. | |
719 | * | |
720 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
721 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
722 | */ | |
3043c60c | 723 | static int |
05394f39 CW |
724 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
725 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 726 | struct drm_i915_gem_pwrite *args, |
05394f39 | 727 | struct drm_file *file) |
673a394b | 728 | { |
3de09aa3 EA |
729 | drm_i915_private_t *dev_priv = dev->dev_private; |
730 | ssize_t remain; | |
731 | loff_t gtt_page_base, offset; | |
732 | loff_t first_data_page, last_data_page, num_pages; | |
733 | loff_t pinned_pages, i; | |
734 | struct page **user_pages; | |
735 | struct mm_struct *mm = current->mm; | |
736 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 737 | int ret; |
3de09aa3 EA |
738 | uint64_t data_ptr = args->data_ptr; |
739 | ||
740 | remain = args->size; | |
741 | ||
742 | /* Pin the user pages containing the data. We can't fault while | |
743 | * holding the struct mutex, and all of the pwrite implementations | |
744 | * want to hold it while dereferencing the user data. | |
745 | */ | |
746 | first_data_page = data_ptr / PAGE_SIZE; | |
747 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
748 | num_pages = last_data_page - first_data_page + 1; | |
749 | ||
fbd5a26d | 750 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
751 | if (user_pages == NULL) |
752 | return -ENOMEM; | |
753 | ||
fbd5a26d | 754 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
755 | down_read(&mm->mmap_sem); |
756 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
757 | num_pages, 0, 0, user_pages, NULL); | |
758 | up_read(&mm->mmap_sem); | |
fbd5a26d | 759 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
760 | if (pinned_pages < num_pages) { |
761 | ret = -EFAULT; | |
762 | goto out_unpin_pages; | |
763 | } | |
673a394b | 764 | |
3de09aa3 EA |
765 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
766 | if (ret) | |
fbd5a26d | 767 | goto out_unpin_pages; |
3de09aa3 | 768 | |
05394f39 | 769 | offset = obj->gtt_offset + args->offset; |
3de09aa3 EA |
770 | |
771 | while (remain > 0) { | |
772 | /* Operation in this page | |
773 | * | |
774 | * gtt_page_base = page offset within aperture | |
775 | * gtt_page_offset = offset within page in aperture | |
776 | * data_page_index = page number in get_user_pages return | |
777 | * data_page_offset = offset with data_page_index page. | |
778 | * page_length = bytes to copy for this page | |
779 | */ | |
780 | gtt_page_base = offset & PAGE_MASK; | |
781 | gtt_page_offset = offset & ~PAGE_MASK; | |
782 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
783 | data_page_offset = data_ptr & ~PAGE_MASK; | |
784 | ||
785 | page_length = remain; | |
786 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
787 | page_length = PAGE_SIZE - gtt_page_offset; | |
788 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
789 | page_length = PAGE_SIZE - data_page_offset; | |
790 | ||
ab34c226 CW |
791 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
792 | gtt_page_base, gtt_page_offset, | |
793 | user_pages[data_page_index], | |
794 | data_page_offset, | |
795 | page_length); | |
3de09aa3 EA |
796 | |
797 | remain -= page_length; | |
798 | offset += page_length; | |
799 | data_ptr += page_length; | |
800 | } | |
801 | ||
3de09aa3 EA |
802 | out_unpin_pages: |
803 | for (i = 0; i < pinned_pages; i++) | |
804 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 805 | drm_free_large(user_pages); |
3de09aa3 EA |
806 | |
807 | return ret; | |
808 | } | |
809 | ||
40123c1f EA |
810 | /** |
811 | * This is the fast shmem pwrite path, which attempts to directly | |
812 | * copy_from_user into the kmapped pages backing the object. | |
813 | */ | |
3043c60c | 814 | static int |
05394f39 CW |
815 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
816 | struct drm_i915_gem_object *obj, | |
40123c1f | 817 | struct drm_i915_gem_pwrite *args, |
05394f39 | 818 | struct drm_file *file) |
673a394b | 819 | { |
05394f39 | 820 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 821 | ssize_t remain; |
e5281ccd | 822 | loff_t offset; |
40123c1f EA |
823 | char __user *user_data; |
824 | int page_offset, page_length; | |
40123c1f EA |
825 | |
826 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
827 | remain = args->size; | |
673a394b | 828 | |
40123c1f | 829 | offset = args->offset; |
05394f39 | 830 | obj->dirty = 1; |
40123c1f EA |
831 | |
832 | while (remain > 0) { | |
e5281ccd CW |
833 | struct page *page; |
834 | char *vaddr; | |
835 | int ret; | |
836 | ||
40123c1f EA |
837 | /* Operation in this page |
838 | * | |
40123c1f EA |
839 | * page_offset = offset within page |
840 | * page_length = bytes to copy for this page | |
841 | */ | |
40123c1f EA |
842 | page_offset = offset & (PAGE_SIZE-1); |
843 | page_length = remain; | |
844 | if ((page_offset + remain) > PAGE_SIZE) | |
845 | page_length = PAGE_SIZE - page_offset; | |
846 | ||
e5281ccd CW |
847 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
848 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
849 | if (IS_ERR(page)) | |
850 | return PTR_ERR(page); | |
851 | ||
852 | vaddr = kmap_atomic(page, KM_USER0); | |
853 | ret = __copy_from_user_inatomic(vaddr + page_offset, | |
854 | user_data, | |
855 | page_length); | |
856 | kunmap_atomic(vaddr, KM_USER0); | |
857 | ||
858 | set_page_dirty(page); | |
859 | mark_page_accessed(page); | |
860 | page_cache_release(page); | |
861 | ||
862 | /* If we get a fault while copying data, then (presumably) our | |
863 | * source page isn't available. Return the error and we'll | |
864 | * retry in the slow path. | |
865 | */ | |
866 | if (ret) | |
fbd5a26d | 867 | return -EFAULT; |
40123c1f EA |
868 | |
869 | remain -= page_length; | |
870 | user_data += page_length; | |
871 | offset += page_length; | |
872 | } | |
873 | ||
fbd5a26d | 874 | return 0; |
40123c1f EA |
875 | } |
876 | ||
877 | /** | |
878 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
879 | * the memory and maps it using kmap_atomic for copying. | |
880 | * | |
881 | * This avoids taking mmap_sem for faulting on the user's address while the | |
882 | * struct_mutex is held. | |
883 | */ | |
884 | static int | |
05394f39 CW |
885 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
886 | struct drm_i915_gem_object *obj, | |
40123c1f | 887 | struct drm_i915_gem_pwrite *args, |
05394f39 | 888 | struct drm_file *file) |
40123c1f | 889 | { |
05394f39 | 890 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f EA |
891 | struct mm_struct *mm = current->mm; |
892 | struct page **user_pages; | |
893 | ssize_t remain; | |
894 | loff_t offset, pinned_pages, i; | |
895 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd | 896 | int shmem_page_offset; |
40123c1f EA |
897 | int data_page_index, data_page_offset; |
898 | int page_length; | |
899 | int ret; | |
900 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 901 | int do_bit17_swizzling; |
40123c1f EA |
902 | |
903 | remain = args->size; | |
904 | ||
905 | /* Pin the user pages containing the data. We can't fault while | |
906 | * holding the struct mutex, and all of the pwrite implementations | |
907 | * want to hold it while dereferencing the user data. | |
908 | */ | |
909 | first_data_page = data_ptr / PAGE_SIZE; | |
910 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
911 | num_pages = last_data_page - first_data_page + 1; | |
912 | ||
4f27b75d | 913 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
914 | if (user_pages == NULL) |
915 | return -ENOMEM; | |
916 | ||
fbd5a26d | 917 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
918 | down_read(&mm->mmap_sem); |
919 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
920 | num_pages, 0, 0, user_pages, NULL); | |
921 | up_read(&mm->mmap_sem); | |
fbd5a26d | 922 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
923 | if (pinned_pages < num_pages) { |
924 | ret = -EFAULT; | |
fbd5a26d | 925 | goto out; |
673a394b EA |
926 | } |
927 | ||
fbd5a26d | 928 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 929 | if (ret) |
fbd5a26d | 930 | goto out; |
40123c1f | 931 | |
fbd5a26d | 932 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 933 | |
673a394b | 934 | offset = args->offset; |
05394f39 | 935 | obj->dirty = 1; |
673a394b | 936 | |
40123c1f | 937 | while (remain > 0) { |
e5281ccd CW |
938 | struct page *page; |
939 | ||
40123c1f EA |
940 | /* Operation in this page |
941 | * | |
40123c1f EA |
942 | * shmem_page_offset = offset within page in shmem file |
943 | * data_page_index = page number in get_user_pages return | |
944 | * data_page_offset = offset with data_page_index page. | |
945 | * page_length = bytes to copy for this page | |
946 | */ | |
40123c1f EA |
947 | shmem_page_offset = offset & ~PAGE_MASK; |
948 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
949 | data_page_offset = data_ptr & ~PAGE_MASK; | |
950 | ||
951 | page_length = remain; | |
952 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
953 | page_length = PAGE_SIZE - shmem_page_offset; | |
954 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
955 | page_length = PAGE_SIZE - data_page_offset; | |
956 | ||
e5281ccd CW |
957 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
958 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
959 | if (IS_ERR(page)) { | |
960 | ret = PTR_ERR(page); | |
961 | goto out; | |
962 | } | |
963 | ||
280b713b | 964 | if (do_bit17_swizzling) { |
e5281ccd | 965 | slow_shmem_bit17_copy(page, |
280b713b EA |
966 | shmem_page_offset, |
967 | user_pages[data_page_index], | |
968 | data_page_offset, | |
99a03df5 CW |
969 | page_length, |
970 | 0); | |
971 | } else { | |
e5281ccd | 972 | slow_shmem_copy(page, |
99a03df5 CW |
973 | shmem_page_offset, |
974 | user_pages[data_page_index], | |
975 | data_page_offset, | |
976 | page_length); | |
280b713b | 977 | } |
40123c1f | 978 | |
e5281ccd CW |
979 | set_page_dirty(page); |
980 | mark_page_accessed(page); | |
981 | page_cache_release(page); | |
982 | ||
40123c1f EA |
983 | remain -= page_length; |
984 | data_ptr += page_length; | |
985 | offset += page_length; | |
673a394b EA |
986 | } |
987 | ||
fbd5a26d | 988 | out: |
40123c1f EA |
989 | for (i = 0; i < pinned_pages; i++) |
990 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 991 | drm_free_large(user_pages); |
673a394b | 992 | |
40123c1f | 993 | return ret; |
673a394b EA |
994 | } |
995 | ||
996 | /** | |
997 | * Writes data to the object referenced by handle. | |
998 | * | |
999 | * On error, the contents of the buffer that were to be modified are undefined. | |
1000 | */ | |
1001 | int | |
1002 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1003 | struct drm_file *file) |
673a394b EA |
1004 | { |
1005 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1006 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1007 | int ret; |
1008 | ||
1009 | if (args->size == 0) | |
1010 | return 0; | |
1011 | ||
1012 | if (!access_ok(VERIFY_READ, | |
1013 | (char __user *)(uintptr_t)args->data_ptr, | |
1014 | args->size)) | |
1015 | return -EFAULT; | |
1016 | ||
1017 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, | |
1018 | args->size); | |
1019 | if (ret) | |
1020 | return -EFAULT; | |
673a394b | 1021 | |
fbd5a26d | 1022 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1023 | if (ret) |
fbd5a26d | 1024 | return ret; |
1d7cfea1 | 1025 | |
05394f39 | 1026 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
1027 | if (obj == NULL) { |
1028 | ret = -ENOENT; | |
1029 | goto unlock; | |
fbd5a26d | 1030 | } |
673a394b | 1031 | |
7dcd2499 | 1032 | /* Bounds check destination. */ |
05394f39 CW |
1033 | if (args->offset > obj->base.size || |
1034 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1035 | ret = -EINVAL; |
35b62a89 | 1036 | goto out; |
ce9d419d CW |
1037 | } |
1038 | ||
673a394b EA |
1039 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1040 | * it would end up going through the fenced access, and we'll get | |
1041 | * different detiling behavior between reading and writing. | |
1042 | * pread/pwrite currently are reading and writing from the CPU | |
1043 | * perspective, requiring manual detiling by the client. | |
1044 | */ | |
05394f39 | 1045 | if (obj->phys_obj) |
fbd5a26d | 1046 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
05394f39 CW |
1047 | else if (obj->tiling_mode == I915_TILING_NONE && |
1048 | obj->gtt_space && | |
1049 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
75e9e915 | 1050 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
1051 | if (ret) |
1052 | goto out; | |
1053 | ||
1054 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
1055 | if (ret) | |
1056 | goto out_unpin; | |
1057 | ||
1058 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1059 | if (ret == -EFAULT) | |
1060 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1061 | ||
1062 | out_unpin: | |
1063 | i915_gem_object_unpin(obj); | |
40123c1f | 1064 | } else { |
fbd5a26d CW |
1065 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1066 | if (ret) | |
e5281ccd | 1067 | goto out; |
673a394b | 1068 | |
fbd5a26d CW |
1069 | ret = -EFAULT; |
1070 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1071 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1072 | if (ret == -EFAULT) | |
1073 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
fbd5a26d | 1074 | } |
673a394b | 1075 | |
35b62a89 | 1076 | out: |
05394f39 | 1077 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1078 | unlock: |
fbd5a26d | 1079 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1080 | return ret; |
1081 | } | |
1082 | ||
1083 | /** | |
2ef7eeaa EA |
1084 | * Called when user space prepares to use an object with the CPU, either |
1085 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1086 | */ |
1087 | int | |
1088 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1089 | struct drm_file *file) |
673a394b | 1090 | { |
a09ba7fa | 1091 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 1092 | struct drm_i915_gem_set_domain *args = data; |
05394f39 | 1093 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1094 | uint32_t read_domains = args->read_domains; |
1095 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1096 | int ret; |
1097 | ||
1098 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1099 | return -ENODEV; | |
1100 | ||
2ef7eeaa | 1101 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1102 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1103 | return -EINVAL; |
1104 | ||
21d509e3 | 1105 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1106 | return -EINVAL; |
1107 | ||
1108 | /* Having something in the write domain implies it's in the read | |
1109 | * domain, and only that read domain. Enforce that in the request. | |
1110 | */ | |
1111 | if (write_domain != 0 && read_domains != write_domain) | |
1112 | return -EINVAL; | |
1113 | ||
76c1dec1 | 1114 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1115 | if (ret) |
76c1dec1 | 1116 | return ret; |
1d7cfea1 | 1117 | |
05394f39 | 1118 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
1119 | if (obj == NULL) { |
1120 | ret = -ENOENT; | |
1121 | goto unlock; | |
76c1dec1 | 1122 | } |
673a394b | 1123 | |
652c393a JB |
1124 | intel_mark_busy(dev, obj); |
1125 | ||
2ef7eeaa EA |
1126 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1127 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1128 | |
a09ba7fa EA |
1129 | /* Update the LRU on the fence for the CPU access that's |
1130 | * about to occur. | |
1131 | */ | |
05394f39 | 1132 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
007cc8ac | 1133 | struct drm_i915_fence_reg *reg = |
05394f39 | 1134 | &dev_priv->fence_regs[obj->fence_reg]; |
007cc8ac | 1135 | list_move_tail(®->lru_list, |
a09ba7fa EA |
1136 | &dev_priv->mm.fence_list); |
1137 | } | |
1138 | ||
02354392 EA |
1139 | /* Silently promote "you're not bound, there was nothing to do" |
1140 | * to success, since the client was just asking us to | |
1141 | * make sure everything was done. | |
1142 | */ | |
1143 | if (ret == -EINVAL) | |
1144 | ret = 0; | |
2ef7eeaa | 1145 | } else { |
e47c68e9 | 1146 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1147 | } |
1148 | ||
7d1c4804 | 1149 | /* Maintain LRU order of "inactive" objects */ |
05394f39 CW |
1150 | if (ret == 0 && i915_gem_object_is_inactive(obj)) |
1151 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1152 | |
05394f39 | 1153 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1154 | unlock: |
673a394b EA |
1155 | mutex_unlock(&dev->struct_mutex); |
1156 | return ret; | |
1157 | } | |
1158 | ||
1159 | /** | |
1160 | * Called when user space has done writes to this buffer | |
1161 | */ | |
1162 | int | |
1163 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1164 | struct drm_file *file) |
673a394b EA |
1165 | { |
1166 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1167 | struct drm_i915_gem_object *obj; |
673a394b EA |
1168 | int ret = 0; |
1169 | ||
1170 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1171 | return -ENODEV; | |
1172 | ||
76c1dec1 | 1173 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1174 | if (ret) |
76c1dec1 | 1175 | return ret; |
1d7cfea1 | 1176 | |
05394f39 | 1177 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 1178 | if (obj == NULL) { |
1d7cfea1 CW |
1179 | ret = -ENOENT; |
1180 | goto unlock; | |
673a394b EA |
1181 | } |
1182 | ||
673a394b | 1183 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1184 | if (obj->pin_count) |
e47c68e9 EA |
1185 | i915_gem_object_flush_cpu_write_domain(obj); |
1186 | ||
05394f39 | 1187 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1188 | unlock: |
673a394b EA |
1189 | mutex_unlock(&dev->struct_mutex); |
1190 | return ret; | |
1191 | } | |
1192 | ||
1193 | /** | |
1194 | * Maps the contents of an object, returning the address it is mapped | |
1195 | * into. | |
1196 | * | |
1197 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1198 | * imply a ref on the object itself. | |
1199 | */ | |
1200 | int | |
1201 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1202 | struct drm_file *file) |
673a394b | 1203 | { |
da761a6e | 1204 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1205 | struct drm_i915_gem_mmap *args = data; |
1206 | struct drm_gem_object *obj; | |
1207 | loff_t offset; | |
1208 | unsigned long addr; | |
1209 | ||
1210 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1211 | return -ENODEV; | |
1212 | ||
05394f39 | 1213 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1214 | if (obj == NULL) |
bf79cb91 | 1215 | return -ENOENT; |
673a394b | 1216 | |
da761a6e CW |
1217 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1218 | drm_gem_object_unreference_unlocked(obj); | |
1219 | return -E2BIG; | |
1220 | } | |
1221 | ||
673a394b EA |
1222 | offset = args->offset; |
1223 | ||
1224 | down_write(¤t->mm->mmap_sem); | |
1225 | addr = do_mmap(obj->filp, 0, args->size, | |
1226 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1227 | args->offset); | |
1228 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1229 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1230 | if (IS_ERR((void *)addr)) |
1231 | return addr; | |
1232 | ||
1233 | args->addr_ptr = (uint64_t) addr; | |
1234 | ||
1235 | return 0; | |
1236 | } | |
1237 | ||
de151cf6 JB |
1238 | /** |
1239 | * i915_gem_fault - fault a page into the GTT | |
1240 | * vma: VMA in question | |
1241 | * vmf: fault info | |
1242 | * | |
1243 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1244 | * from userspace. The fault handler takes care of binding the object to | |
1245 | * the GTT (if needed), allocating and programming a fence register (again, | |
1246 | * only if needed based on whether the old reg is still valid or the object | |
1247 | * is tiled) and inserting a new PTE into the faulting process. | |
1248 | * | |
1249 | * Note that the faulting process may involve evicting existing objects | |
1250 | * from the GTT and/or fence registers to make room. So performance may | |
1251 | * suffer if the GTT working set is large or there are few fence registers | |
1252 | * left. | |
1253 | */ | |
1254 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1255 | { | |
05394f39 CW |
1256 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1257 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1258 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1259 | pgoff_t page_offset; |
1260 | unsigned long pfn; | |
1261 | int ret = 0; | |
0f973f27 | 1262 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1263 | |
1264 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1265 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1266 | PAGE_SHIFT; | |
1267 | ||
1268 | /* Now bind it into the GTT if needed */ | |
1269 | mutex_lock(&dev->struct_mutex); | |
05394f39 | 1270 | BUG_ON(obj->pin_count && !obj->pin_mappable); |
a00b10c3 | 1271 | |
919926ae CW |
1272 | if (!obj->map_and_fenceable) { |
1273 | ret = i915_gem_object_unbind(obj); | |
1274 | if (ret) | |
1275 | goto unlock; | |
a00b10c3 | 1276 | } |
16e809ac | 1277 | |
05394f39 | 1278 | if (!obj->gtt_space) { |
75e9e915 | 1279 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1280 | if (ret) |
1281 | goto unlock; | |
de151cf6 JB |
1282 | } |
1283 | ||
4a684a41 CW |
1284 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1285 | if (ret) | |
1286 | goto unlock; | |
1287 | ||
05394f39 CW |
1288 | if (!obj->fault_mappable) { |
1289 | obj->fault_mappable = true; | |
1290 | i915_gem_info_update_mappable(dev_priv, obj, true); | |
fb7d516a DV |
1291 | } |
1292 | ||
de151cf6 | 1293 | /* Need a new fence register? */ |
05394f39 | 1294 | if (obj->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1295 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1296 | if (ret) |
1297 | goto unlock; | |
d9ddcb96 | 1298 | } |
de151cf6 | 1299 | |
05394f39 CW |
1300 | if (i915_gem_object_is_inactive(obj)) |
1301 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1302 | |
05394f39 | 1303 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1304 | page_offset; |
1305 | ||
1306 | /* Finally, remap it using the new GTT offset */ | |
1307 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1308 | unlock: |
de151cf6 JB |
1309 | mutex_unlock(&dev->struct_mutex); |
1310 | ||
1311 | switch (ret) { | |
045e769a CW |
1312 | case -EAGAIN: |
1313 | set_need_resched(); | |
c715089f CW |
1314 | case 0: |
1315 | case -ERESTARTSYS: | |
1316 | return VM_FAULT_NOPAGE; | |
de151cf6 | 1317 | case -ENOMEM: |
de151cf6 | 1318 | return VM_FAULT_OOM; |
de151cf6 | 1319 | default: |
c715089f | 1320 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1321 | } |
1322 | } | |
1323 | ||
1324 | /** | |
1325 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1326 | * @obj: obj in question | |
1327 | * | |
1328 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1329 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1330 | * up the object based on the offset and sets up the various memory mapping | |
1331 | * structures. | |
1332 | * | |
1333 | * This routine allocates and attaches a fake offset for @obj. | |
1334 | */ | |
1335 | static int | |
05394f39 | 1336 | i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj) |
de151cf6 | 1337 | { |
05394f39 | 1338 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 1339 | struct drm_gem_mm *mm = dev->mm_private; |
de151cf6 | 1340 | struct drm_map_list *list; |
f77d390c | 1341 | struct drm_local_map *map; |
de151cf6 JB |
1342 | int ret = 0; |
1343 | ||
1344 | /* Set the object up for mmap'ing */ | |
05394f39 | 1345 | list = &obj->base.map_list; |
9a298b2a | 1346 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1347 | if (!list->map) |
1348 | return -ENOMEM; | |
1349 | ||
1350 | map = list->map; | |
1351 | map->type = _DRM_GEM; | |
05394f39 | 1352 | map->size = obj->base.size; |
de151cf6 JB |
1353 | map->handle = obj; |
1354 | ||
1355 | /* Get a DRM GEM mmap offset allocated... */ | |
1356 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
05394f39 CW |
1357 | obj->base.size / PAGE_SIZE, |
1358 | 0, 0); | |
de151cf6 | 1359 | if (!list->file_offset_node) { |
05394f39 CW |
1360 | DRM_ERROR("failed to allocate offset for bo %d\n", |
1361 | obj->base.name); | |
9e0ae534 | 1362 | ret = -ENOSPC; |
de151cf6 JB |
1363 | goto out_free_list; |
1364 | } | |
1365 | ||
1366 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
05394f39 CW |
1367 | obj->base.size / PAGE_SIZE, |
1368 | 0); | |
de151cf6 JB |
1369 | if (!list->file_offset_node) { |
1370 | ret = -ENOMEM; | |
1371 | goto out_free_list; | |
1372 | } | |
1373 | ||
1374 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1375 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1376 | if (ret) { | |
de151cf6 JB |
1377 | DRM_ERROR("failed to add to map hash\n"); |
1378 | goto out_free_mm; | |
1379 | } | |
1380 | ||
de151cf6 JB |
1381 | return 0; |
1382 | ||
1383 | out_free_mm: | |
1384 | drm_mm_put_block(list->file_offset_node); | |
1385 | out_free_list: | |
9a298b2a | 1386 | kfree(list->map); |
39a01d1f | 1387 | list->map = NULL; |
de151cf6 JB |
1388 | |
1389 | return ret; | |
1390 | } | |
1391 | ||
901782b2 CW |
1392 | /** |
1393 | * i915_gem_release_mmap - remove physical page mappings | |
1394 | * @obj: obj in question | |
1395 | * | |
af901ca1 | 1396 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1397 | * relinquish ownership of the pages back to the system. |
1398 | * | |
1399 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1400 | * object through the GTT and then lose the fence register due to | |
1401 | * resource pressure. Similarly if the object has been moved out of the | |
1402 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1403 | * mapping will then trigger a page fault on the next user access, allowing | |
1404 | * fixup by i915_gem_fault(). | |
1405 | */ | |
d05ca301 | 1406 | void |
05394f39 | 1407 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1408 | { |
05394f39 | 1409 | struct drm_device *dev = obj->base.dev; |
fb7d516a | 1410 | struct drm_i915_private *dev_priv = dev->dev_private; |
901782b2 | 1411 | |
05394f39 | 1412 | if (unlikely(obj->base.map_list.map && dev->dev_mapping)) |
901782b2 | 1413 | unmap_mapping_range(dev->dev_mapping, |
05394f39 CW |
1414 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, |
1415 | obj->base.size, 1); | |
fb7d516a | 1416 | |
05394f39 CW |
1417 | if (obj->fault_mappable) { |
1418 | obj->fault_mappable = false; | |
1419 | i915_gem_info_update_mappable(dev_priv, obj, false); | |
fb7d516a | 1420 | } |
901782b2 CW |
1421 | } |
1422 | ||
ab00b3e5 | 1423 | static void |
05394f39 | 1424 | i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj) |
ab00b3e5 | 1425 | { |
05394f39 | 1426 | struct drm_device *dev = obj->base.dev; |
ab00b3e5 | 1427 | struct drm_gem_mm *mm = dev->mm_private; |
05394f39 | 1428 | struct drm_map_list *list = &obj->base.map_list; |
ab00b3e5 | 1429 | |
ab00b3e5 | 1430 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
39a01d1f CW |
1431 | drm_mm_put_block(list->file_offset_node); |
1432 | kfree(list->map); | |
1433 | list->map = NULL; | |
ab00b3e5 JB |
1434 | } |
1435 | ||
92b88aeb CW |
1436 | static uint32_t |
1437 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj) | |
1438 | { | |
1439 | struct drm_device *dev = obj->base.dev; | |
1440 | uint32_t size; | |
1441 | ||
1442 | if (INTEL_INFO(dev)->gen >= 4 || | |
1443 | obj->tiling_mode == I915_TILING_NONE) | |
1444 | return obj->base.size; | |
1445 | ||
1446 | /* Previous chips need a power-of-two fence region when tiling */ | |
1447 | if (INTEL_INFO(dev)->gen == 3) | |
1448 | size = 1024*1024; | |
1449 | else | |
1450 | size = 512*1024; | |
1451 | ||
1452 | while (size < obj->base.size) | |
1453 | size <<= 1; | |
1454 | ||
1455 | return size; | |
1456 | } | |
1457 | ||
de151cf6 JB |
1458 | /** |
1459 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1460 | * @obj: object to check | |
1461 | * | |
1462 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1463 | * potential fence register mapping. |
de151cf6 JB |
1464 | */ |
1465 | static uint32_t | |
05394f39 | 1466 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) |
de151cf6 | 1467 | { |
05394f39 | 1468 | struct drm_device *dev = obj->base.dev; |
de151cf6 JB |
1469 | |
1470 | /* | |
1471 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1472 | * if a fence register is needed for the object. | |
1473 | */ | |
a00b10c3 | 1474 | if (INTEL_INFO(dev)->gen >= 4 || |
05394f39 | 1475 | obj->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1476 | return 4096; |
1477 | ||
a00b10c3 CW |
1478 | /* |
1479 | * Previous chips need to be aligned to the size of the smallest | |
1480 | * fence register that can contain the object. | |
1481 | */ | |
05394f39 | 1482 | return i915_gem_get_gtt_size(obj); |
a00b10c3 CW |
1483 | } |
1484 | ||
5e783301 DV |
1485 | /** |
1486 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1487 | * unfenced object | |
1488 | * @obj: object to check | |
1489 | * | |
1490 | * Return the required GTT alignment for an object, only taking into account | |
1491 | * unfenced tiled surface requirements. | |
1492 | */ | |
1493 | static uint32_t | |
05394f39 | 1494 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) |
5e783301 | 1495 | { |
05394f39 | 1496 | struct drm_device *dev = obj->base.dev; |
5e783301 DV |
1497 | int tile_height; |
1498 | ||
1499 | /* | |
1500 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1501 | */ | |
1502 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
05394f39 | 1503 | obj->tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1504 | return 4096; |
1505 | ||
1506 | /* | |
1507 | * Older chips need unfenced tiled buffers to be aligned to the left | |
1508 | * edge of an even tile row (where tile rows are counted as if the bo is | |
1509 | * placed in a fenced gtt region). | |
1510 | */ | |
1511 | if (IS_GEN2(dev) || | |
05394f39 | 1512 | (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
5e783301 DV |
1513 | tile_height = 32; |
1514 | else | |
1515 | tile_height = 8; | |
1516 | ||
05394f39 | 1517 | return tile_height * obj->stride * 2; |
5e783301 DV |
1518 | } |
1519 | ||
de151cf6 JB |
1520 | /** |
1521 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1522 | * @dev: DRM device | |
1523 | * @data: GTT mapping ioctl data | |
05394f39 | 1524 | * @file: GEM object info |
de151cf6 JB |
1525 | * |
1526 | * Simply returns the fake offset to userspace so it can mmap it. | |
1527 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1528 | * up so we can get faults in the handler above. | |
1529 | * | |
1530 | * The fault handler will take care of binding the object into the GTT | |
1531 | * (since it may have been evicted to make room for something), allocating | |
1532 | * a fence register, and mapping the appropriate aperture address into | |
1533 | * userspace. | |
1534 | */ | |
1535 | int | |
1536 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1537 | struct drm_file *file) |
de151cf6 | 1538 | { |
da761a6e | 1539 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 1540 | struct drm_i915_gem_mmap_gtt *args = data; |
05394f39 | 1541 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1542 | int ret; |
1543 | ||
1544 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1545 | return -ENODEV; | |
1546 | ||
76c1dec1 | 1547 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1548 | if (ret) |
76c1dec1 | 1549 | return ret; |
de151cf6 | 1550 | |
05394f39 | 1551 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
1552 | if (obj == NULL) { |
1553 | ret = -ENOENT; | |
1554 | goto unlock; | |
1555 | } | |
de151cf6 | 1556 | |
05394f39 | 1557 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e CW |
1558 | ret = -E2BIG; |
1559 | goto unlock; | |
1560 | } | |
1561 | ||
05394f39 | 1562 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1563 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1564 | ret = -EINVAL; |
1565 | goto out; | |
ab18282d CW |
1566 | } |
1567 | ||
05394f39 | 1568 | if (!obj->base.map_list.map) { |
de151cf6 | 1569 | ret = i915_gem_create_mmap_offset(obj); |
1d7cfea1 CW |
1570 | if (ret) |
1571 | goto out; | |
de151cf6 JB |
1572 | } |
1573 | ||
05394f39 | 1574 | args->offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1575 | |
1d7cfea1 | 1576 | out: |
05394f39 | 1577 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1578 | unlock: |
de151cf6 | 1579 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1580 | return ret; |
de151cf6 JB |
1581 | } |
1582 | ||
e5281ccd | 1583 | static int |
05394f39 | 1584 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1585 | gfp_t gfpmask) |
1586 | { | |
e5281ccd CW |
1587 | int page_count, i; |
1588 | struct address_space *mapping; | |
1589 | struct inode *inode; | |
1590 | struct page *page; | |
1591 | ||
1592 | /* Get the list of pages out of our struct file. They'll be pinned | |
1593 | * at this point until we release them. | |
1594 | */ | |
05394f39 CW |
1595 | page_count = obj->base.size / PAGE_SIZE; |
1596 | BUG_ON(obj->pages != NULL); | |
1597 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1598 | if (obj->pages == NULL) | |
e5281ccd CW |
1599 | return -ENOMEM; |
1600 | ||
05394f39 | 1601 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd CW |
1602 | mapping = inode->i_mapping; |
1603 | for (i = 0; i < page_count; i++) { | |
1604 | page = read_cache_page_gfp(mapping, i, | |
1605 | GFP_HIGHUSER | | |
1606 | __GFP_COLD | | |
1607 | __GFP_RECLAIMABLE | | |
1608 | gfpmask); | |
1609 | if (IS_ERR(page)) | |
1610 | goto err_pages; | |
1611 | ||
05394f39 | 1612 | obj->pages[i] = page; |
e5281ccd CW |
1613 | } |
1614 | ||
05394f39 | 1615 | if (obj->tiling_mode != I915_TILING_NONE) |
e5281ccd CW |
1616 | i915_gem_object_do_bit_17_swizzle(obj); |
1617 | ||
1618 | return 0; | |
1619 | ||
1620 | err_pages: | |
1621 | while (i--) | |
05394f39 | 1622 | page_cache_release(obj->pages[i]); |
e5281ccd | 1623 | |
05394f39 CW |
1624 | drm_free_large(obj->pages); |
1625 | obj->pages = NULL; | |
e5281ccd CW |
1626 | return PTR_ERR(page); |
1627 | } | |
1628 | ||
5cdf5881 | 1629 | static void |
05394f39 | 1630 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1631 | { |
05394f39 | 1632 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1633 | int i; |
1634 | ||
05394f39 | 1635 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1636 | |
05394f39 | 1637 | if (obj->tiling_mode != I915_TILING_NONE) |
280b713b EA |
1638 | i915_gem_object_save_bit_17_swizzle(obj); |
1639 | ||
05394f39 CW |
1640 | if (obj->madv == I915_MADV_DONTNEED) |
1641 | obj->dirty = 0; | |
3ef94daa CW |
1642 | |
1643 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1644 | if (obj->dirty) |
1645 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1646 | |
05394f39 CW |
1647 | if (obj->madv == I915_MADV_WILLNEED) |
1648 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1649 | |
05394f39 | 1650 | page_cache_release(obj->pages[i]); |
3ef94daa | 1651 | } |
05394f39 | 1652 | obj->dirty = 0; |
673a394b | 1653 | |
05394f39 CW |
1654 | drm_free_large(obj->pages); |
1655 | obj->pages = NULL; | |
673a394b EA |
1656 | } |
1657 | ||
a56ba56c CW |
1658 | static uint32_t |
1659 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1660 | struct intel_ring_buffer *ring) | |
1661 | { | |
1662 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5d97eb69 | 1663 | return ring->outstanding_lazy_request = dev_priv->next_seqno; |
a56ba56c CW |
1664 | } |
1665 | ||
673a394b | 1666 | static void |
05394f39 | 1667 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
852835f3 | 1668 | struct intel_ring_buffer *ring) |
673a394b | 1669 | { |
05394f39 | 1670 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1671 | struct drm_i915_private *dev_priv = dev->dev_private; |
a56ba56c | 1672 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1673 | |
852835f3 | 1674 | BUG_ON(ring == NULL); |
05394f39 | 1675 | obj->ring = ring; |
673a394b EA |
1676 | |
1677 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1678 | if (!obj->active) { |
1679 | drm_gem_object_reference(&obj->base); | |
1680 | obj->active = 1; | |
673a394b | 1681 | } |
e35a41de | 1682 | |
673a394b | 1683 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1684 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1685 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1686 | |
05394f39 | 1687 | obj->last_rendering_seqno = seqno; |
caea7476 CW |
1688 | if (obj->fenced_gpu_access) { |
1689 | struct drm_i915_fence_reg *reg; | |
1690 | ||
1691 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); | |
1692 | ||
1693 | obj->last_fenced_seqno = seqno; | |
1694 | obj->last_fenced_ring = ring; | |
1695 | ||
1696 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1697 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
1698 | } | |
1699 | } | |
1700 | ||
1701 | static void | |
1702 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1703 | { | |
1704 | list_del_init(&obj->ring_list); | |
1705 | obj->last_rendering_seqno = 0; | |
1706 | obj->last_fenced_seqno = 0; | |
673a394b EA |
1707 | } |
1708 | ||
ce44b0ea | 1709 | static void |
05394f39 | 1710 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1711 | { |
05394f39 | 1712 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1713 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1714 | |
05394f39 CW |
1715 | BUG_ON(!obj->active); |
1716 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1717 | |
1718 | i915_gem_object_move_off_active(obj); | |
1719 | } | |
1720 | ||
1721 | static void | |
1722 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1723 | { | |
1724 | struct drm_device *dev = obj->base.dev; | |
1725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1726 | ||
1727 | if (obj->pin_count != 0) | |
1728 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1729 | else | |
1730 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1731 | ||
1732 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1733 | BUG_ON(!obj->active); | |
1734 | obj->ring = NULL; | |
1735 | ||
1736 | i915_gem_object_move_off_active(obj); | |
1737 | obj->fenced_gpu_access = false; | |
1738 | obj->last_fenced_ring = NULL; | |
1739 | ||
1740 | obj->active = 0; | |
1741 | drm_gem_object_unreference(&obj->base); | |
1742 | ||
1743 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1744 | } |
673a394b | 1745 | |
963b4836 CW |
1746 | /* Immediately discard the backing storage */ |
1747 | static void | |
05394f39 | 1748 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1749 | { |
bb6baf76 | 1750 | struct inode *inode; |
963b4836 | 1751 | |
ae9fed6b CW |
1752 | /* Our goal here is to return as much of the memory as |
1753 | * is possible back to the system as we are called from OOM. | |
1754 | * To do this we must instruct the shmfs to drop all of its | |
1755 | * backing pages, *now*. Here we mirror the actions taken | |
1756 | * when by shmem_delete_inode() to release the backing store. | |
1757 | */ | |
05394f39 | 1758 | inode = obj->base.filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1759 | truncate_inode_pages(inode->i_mapping, 0); |
1760 | if (inode->i_op->truncate_range) | |
1761 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 | 1762 | |
05394f39 | 1763 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1764 | } |
1765 | ||
1766 | static inline int | |
05394f39 | 1767 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1768 | { |
05394f39 | 1769 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1770 | } |
1771 | ||
63560396 DV |
1772 | static void |
1773 | i915_gem_process_flushing_list(struct drm_device *dev, | |
8a1a49f9 | 1774 | uint32_t flush_domains, |
852835f3 | 1775 | struct intel_ring_buffer *ring) |
63560396 | 1776 | { |
05394f39 | 1777 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1778 | |
05394f39 | 1779 | list_for_each_entry_safe(obj, next, |
64193406 | 1780 | &ring->gpu_write_list, |
63560396 | 1781 | gpu_write_list) { |
05394f39 CW |
1782 | if (obj->base.write_domain & flush_domains) { |
1783 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1784 | |
05394f39 CW |
1785 | obj->base.write_domain = 0; |
1786 | list_del_init(&obj->gpu_write_list); | |
617dbe27 | 1787 | i915_gem_object_move_to_active(obj, ring); |
63560396 | 1788 | |
63560396 | 1789 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1790 | obj->base.read_domains, |
63560396 DV |
1791 | old_write_domain); |
1792 | } | |
1793 | } | |
1794 | } | |
8187a2b7 | 1795 | |
3cce469c | 1796 | int |
8a1a49f9 | 1797 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1798 | struct drm_file *file, |
8dc5d147 | 1799 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1800 | struct intel_ring_buffer *ring) |
673a394b EA |
1801 | { |
1802 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1803 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1804 | uint32_t seqno; |
1805 | int was_empty; | |
3cce469c CW |
1806 | int ret; |
1807 | ||
1808 | BUG_ON(request == NULL); | |
673a394b | 1809 | |
f787a5f5 CW |
1810 | if (file != NULL) |
1811 | file_priv = file->driver_priv; | |
b962442e | 1812 | |
3cce469c CW |
1813 | ret = ring->add_request(ring, &seqno); |
1814 | if (ret) | |
1815 | return ret; | |
673a394b | 1816 | |
a56ba56c | 1817 | ring->outstanding_lazy_request = false; |
673a394b EA |
1818 | |
1819 | request->seqno = seqno; | |
852835f3 | 1820 | request->ring = ring; |
673a394b | 1821 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1822 | was_empty = list_empty(&ring->request_list); |
1823 | list_add_tail(&request->list, &ring->request_list); | |
1824 | ||
f787a5f5 | 1825 | if (file_priv) { |
1c25595f | 1826 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1827 | request->file_priv = file_priv; |
b962442e | 1828 | list_add_tail(&request->client_list, |
f787a5f5 | 1829 | &file_priv->mm.request_list); |
1c25595f | 1830 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1831 | } |
673a394b | 1832 | |
f65d9421 | 1833 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1834 | mod_timer(&dev_priv->hangcheck_timer, |
1835 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1836 | if (was_empty) |
b3b079db CW |
1837 | queue_delayed_work(dev_priv->wq, |
1838 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1839 | } |
3cce469c | 1840 | return 0; |
673a394b EA |
1841 | } |
1842 | ||
1843 | /** | |
1844 | * Command execution barrier | |
1845 | * | |
1846 | * Ensures that all commands in the ring are finished | |
1847 | * before signalling the CPU | |
1848 | */ | |
8a1a49f9 | 1849 | static void |
852835f3 | 1850 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1851 | { |
673a394b | 1852 | uint32_t flush_domains = 0; |
673a394b EA |
1853 | |
1854 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1855 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1856 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 | 1857 | |
78501eac | 1858 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
673a394b EA |
1859 | } |
1860 | ||
f787a5f5 CW |
1861 | static inline void |
1862 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1863 | { |
1c25595f | 1864 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1865 | |
1c25595f CW |
1866 | if (!file_priv) |
1867 | return; | |
1c5d22f7 | 1868 | |
1c25595f CW |
1869 | spin_lock(&file_priv->mm.lock); |
1870 | list_del(&request->client_list); | |
1871 | request->file_priv = NULL; | |
1872 | spin_unlock(&file_priv->mm.lock); | |
673a394b | 1873 | } |
673a394b | 1874 | |
dfaae392 CW |
1875 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1876 | struct intel_ring_buffer *ring) | |
9375e446 | 1877 | { |
dfaae392 CW |
1878 | while (!list_empty(&ring->request_list)) { |
1879 | struct drm_i915_gem_request *request; | |
673a394b | 1880 | |
dfaae392 CW |
1881 | request = list_first_entry(&ring->request_list, |
1882 | struct drm_i915_gem_request, | |
1883 | list); | |
de151cf6 | 1884 | |
dfaae392 | 1885 | list_del(&request->list); |
f787a5f5 | 1886 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1887 | kfree(request); |
1888 | } | |
673a394b | 1889 | |
dfaae392 | 1890 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1891 | struct drm_i915_gem_object *obj; |
9375e446 | 1892 | |
05394f39 CW |
1893 | obj = list_first_entry(&ring->active_list, |
1894 | struct drm_i915_gem_object, | |
1895 | ring_list); | |
9375e446 | 1896 | |
05394f39 CW |
1897 | obj->base.write_domain = 0; |
1898 | list_del_init(&obj->gpu_write_list); | |
1899 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1900 | } |
1901 | } | |
1902 | ||
312817a3 CW |
1903 | static void i915_gem_reset_fences(struct drm_device *dev) |
1904 | { | |
1905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1906 | int i; | |
1907 | ||
1908 | for (i = 0; i < 16; i++) { | |
1909 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
1910 | if (reg->obj) | |
1911 | i915_gem_clear_fence_reg(reg->obj); | |
1912 | } | |
1913 | } | |
1914 | ||
069efc1d | 1915 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1916 | { |
77f01230 | 1917 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1918 | struct drm_i915_gem_object *obj; |
673a394b | 1919 | |
dfaae392 | 1920 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
87acb0a5 | 1921 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
549f7365 | 1922 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
dfaae392 CW |
1923 | |
1924 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1925 | * to be lost on reset along with the data, so simply move the | |
1926 | * lost bo to the inactive list. | |
1927 | */ | |
1928 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
05394f39 CW |
1929 | obj= list_first_entry(&dev_priv->mm.flushing_list, |
1930 | struct drm_i915_gem_object, | |
1931 | mm_list); | |
dfaae392 | 1932 | |
05394f39 CW |
1933 | obj->base.write_domain = 0; |
1934 | list_del_init(&obj->gpu_write_list); | |
1935 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1936 | } |
1937 | ||
1938 | /* Move everything out of the GPU domains to ensure we do any | |
1939 | * necessary invalidation upon reuse. | |
1940 | */ | |
05394f39 | 1941 | list_for_each_entry(obj, |
77f01230 | 1942 | &dev_priv->mm.inactive_list, |
69dc4987 | 1943 | mm_list) |
77f01230 | 1944 | { |
05394f39 | 1945 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1946 | } |
069efc1d CW |
1947 | |
1948 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1949 | i915_gem_reset_fences(dev); |
673a394b EA |
1950 | } |
1951 | ||
1952 | /** | |
1953 | * This function clears the request list as sequence numbers are passed. | |
1954 | */ | |
b09a1fec CW |
1955 | static void |
1956 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1957 | struct intel_ring_buffer *ring) | |
673a394b EA |
1958 | { |
1959 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1960 | uint32_t seqno; | |
1961 | ||
b84d5f0c CW |
1962 | if (!ring->status_page.page_addr || |
1963 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1964 | return; |
1965 | ||
23bc5982 | 1966 | WARN_ON(i915_verify_lists(dev)); |
673a394b | 1967 | |
78501eac | 1968 | seqno = ring->get_seqno(ring); |
852835f3 | 1969 | while (!list_empty(&ring->request_list)) { |
673a394b | 1970 | struct drm_i915_gem_request *request; |
673a394b | 1971 | |
852835f3 | 1972 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1973 | struct drm_i915_gem_request, |
1974 | list); | |
673a394b | 1975 | |
dfaae392 | 1976 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1977 | break; |
1978 | ||
1979 | trace_i915_gem_request_retire(dev, request->seqno); | |
1980 | ||
1981 | list_del(&request->list); | |
f787a5f5 | 1982 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1983 | kfree(request); |
1984 | } | |
673a394b | 1985 | |
b84d5f0c CW |
1986 | /* Move any buffers on the active list that are no longer referenced |
1987 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1988 | */ | |
1989 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1990 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1991 | |
05394f39 CW |
1992 | obj= list_first_entry(&ring->active_list, |
1993 | struct drm_i915_gem_object, | |
1994 | ring_list); | |
673a394b | 1995 | |
05394f39 | 1996 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1997 | break; |
b84d5f0c | 1998 | |
05394f39 | 1999 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
2000 | i915_gem_object_move_to_flushing(obj); |
2001 | else | |
2002 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 2003 | } |
9d34e5db CW |
2004 | |
2005 | if (unlikely (dev_priv->trace_irq_seqno && | |
2006 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
78501eac | 2007 | ring->user_irq_put(ring); |
9d34e5db CW |
2008 | dev_priv->trace_irq_seqno = 0; |
2009 | } | |
23bc5982 CW |
2010 | |
2011 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
2012 | } |
2013 | ||
b09a1fec CW |
2014 | void |
2015 | i915_gem_retire_requests(struct drm_device *dev) | |
2016 | { | |
2017 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2018 | ||
be72615b | 2019 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 2020 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
2021 | |
2022 | /* We must be careful that during unbind() we do not | |
2023 | * accidentally infinitely recurse into retire requests. | |
2024 | * Currently: | |
2025 | * retire -> free -> unbind -> wait -> retire_ring | |
2026 | */ | |
05394f39 | 2027 | list_for_each_entry_safe(obj, next, |
be72615b | 2028 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 2029 | mm_list) |
05394f39 | 2030 | i915_gem_free_object_tail(obj); |
be72615b CW |
2031 | } |
2032 | ||
b09a1fec | 2033 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
87acb0a5 | 2034 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
549f7365 | 2035 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
b09a1fec CW |
2036 | } |
2037 | ||
75ef9da2 | 2038 | static void |
673a394b EA |
2039 | i915_gem_retire_work_handler(struct work_struct *work) |
2040 | { | |
2041 | drm_i915_private_t *dev_priv; | |
2042 | struct drm_device *dev; | |
2043 | ||
2044 | dev_priv = container_of(work, drm_i915_private_t, | |
2045 | mm.retire_work.work); | |
2046 | dev = dev_priv->dev; | |
2047 | ||
891b48cf CW |
2048 | /* Come back later if the device is busy... */ |
2049 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2050 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
2051 | return; | |
2052 | } | |
2053 | ||
b09a1fec | 2054 | i915_gem_retire_requests(dev); |
d1b851fc | 2055 | |
6dbe2772 | 2056 | if (!dev_priv->mm.suspended && |
d1b851fc | 2057 | (!list_empty(&dev_priv->render_ring.request_list) || |
549f7365 CW |
2058 | !list_empty(&dev_priv->bsd_ring.request_list) || |
2059 | !list_empty(&dev_priv->blt_ring.request_list))) | |
9c9fe1f8 | 2060 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
2061 | mutex_unlock(&dev->struct_mutex); |
2062 | } | |
2063 | ||
5a5a0c64 | 2064 | int |
852835f3 | 2065 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 2066 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
2067 | { |
2068 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 2069 | u32 ier; |
673a394b EA |
2070 | int ret = 0; |
2071 | ||
2072 | BUG_ON(seqno == 0); | |
2073 | ||
ba1234d1 | 2074 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 CW |
2075 | return -EAGAIN; |
2076 | ||
5d97eb69 | 2077 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
2078 | struct drm_i915_gem_request *request; |
2079 | ||
2080 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
2081 | if (request == NULL) | |
e35a41de | 2082 | return -ENOMEM; |
3cce469c CW |
2083 | |
2084 | ret = i915_add_request(dev, NULL, request, ring); | |
2085 | if (ret) { | |
2086 | kfree(request); | |
2087 | return ret; | |
2088 | } | |
2089 | ||
2090 | seqno = request->seqno; | |
e35a41de | 2091 | } |
ffed1d09 | 2092 | |
78501eac | 2093 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
bad720ff | 2094 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
2095 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2096 | else | |
2097 | ier = I915_READ(IER); | |
802c7eb6 JB |
2098 | if (!ier) { |
2099 | DRM_ERROR("something (likely vbetool) disabled " | |
2100 | "interrupts, re-enabling\n"); | |
2101 | i915_driver_irq_preinstall(dev); | |
2102 | i915_driver_irq_postinstall(dev); | |
2103 | } | |
2104 | ||
1c5d22f7 CW |
2105 | trace_i915_gem_request_wait_begin(dev, seqno); |
2106 | ||
b2223497 | 2107 | ring->waiting_seqno = seqno; |
78501eac | 2108 | ring->user_irq_get(ring); |
48764bf4 | 2109 | if (interruptible) |
852835f3 | 2110 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 2111 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2112 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2113 | else |
852835f3 | 2114 | wait_event(ring->irq_queue, |
78501eac | 2115 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2116 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2117 | |
78501eac | 2118 | ring->user_irq_put(ring); |
b2223497 | 2119 | ring->waiting_seqno = 0; |
1c5d22f7 CW |
2120 | |
2121 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2122 | } |
ba1234d1 | 2123 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2124 | ret = -EAGAIN; |
673a394b EA |
2125 | |
2126 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2127 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2128 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2129 | dev_priv->next_seqno); |
673a394b EA |
2130 | |
2131 | /* Directly dispatch request retiring. While we have the work queue | |
2132 | * to handle this, the waiter on a request often wants an associated | |
2133 | * buffer to have made it to the inactive list, and we would need | |
2134 | * a separate wait queue to handle that. | |
2135 | */ | |
2136 | if (ret == 0) | |
b09a1fec | 2137 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2138 | |
2139 | return ret; | |
2140 | } | |
2141 | ||
48764bf4 DV |
2142 | /** |
2143 | * Waits for a sequence number to be signaled, and cleans up the | |
2144 | * request and object lists appropriately for that event. | |
2145 | */ | |
2146 | static int | |
852835f3 | 2147 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2148 | struct intel_ring_buffer *ring) |
48764bf4 | 2149 | { |
852835f3 | 2150 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2151 | } |
2152 | ||
20f0cd55 | 2153 | static void |
9220434a CW |
2154 | i915_gem_flush_ring(struct drm_device *dev, |
2155 | struct intel_ring_buffer *ring, | |
2156 | uint32_t invalidate_domains, | |
2157 | uint32_t flush_domains) | |
2158 | { | |
78501eac | 2159 | ring->flush(ring, invalidate_domains, flush_domains); |
9220434a CW |
2160 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
2161 | } | |
2162 | ||
8187a2b7 ZN |
2163 | static void |
2164 | i915_gem_flush(struct drm_device *dev, | |
2165 | uint32_t invalidate_domains, | |
9220434a CW |
2166 | uint32_t flush_domains, |
2167 | uint32_t flush_rings) | |
8187a2b7 ZN |
2168 | { |
2169 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2170 | |
8187a2b7 | 2171 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
40ce6575 | 2172 | intel_gtt_chipset_flush(); |
8bff917c | 2173 | |
9220434a CW |
2174 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2175 | if (flush_rings & RING_RENDER) | |
05394f39 | 2176 | i915_gem_flush_ring(dev, &dev_priv->render_ring, |
9220434a CW |
2177 | invalidate_domains, flush_domains); |
2178 | if (flush_rings & RING_BSD) | |
05394f39 | 2179 | i915_gem_flush_ring(dev, &dev_priv->bsd_ring, |
9220434a | 2180 | invalidate_domains, flush_domains); |
549f7365 | 2181 | if (flush_rings & RING_BLT) |
05394f39 | 2182 | i915_gem_flush_ring(dev, &dev_priv->blt_ring, |
549f7365 | 2183 | invalidate_domains, flush_domains); |
9220434a | 2184 | } |
8187a2b7 ZN |
2185 | } |
2186 | ||
673a394b EA |
2187 | /** |
2188 | * Ensures that all rendering to the object has completed and the object is | |
2189 | * safe to unbind from the GTT or access from the CPU. | |
2190 | */ | |
2191 | static int | |
05394f39 | 2192 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
2cf34d7b | 2193 | bool interruptible) |
673a394b | 2194 | { |
05394f39 | 2195 | struct drm_device *dev = obj->base.dev; |
673a394b EA |
2196 | int ret; |
2197 | ||
e47c68e9 EA |
2198 | /* This function only exists to support waiting for existing rendering, |
2199 | * not for emitting required flushes. | |
673a394b | 2200 | */ |
05394f39 | 2201 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2202 | |
2203 | /* If there is rendering queued on the buffer being evicted, wait for | |
2204 | * it. | |
2205 | */ | |
05394f39 | 2206 | if (obj->active) { |
2cf34d7b | 2207 | ret = i915_do_wait_request(dev, |
05394f39 | 2208 | obj->last_rendering_seqno, |
2cf34d7b | 2209 | interruptible, |
05394f39 | 2210 | obj->ring); |
2cf34d7b | 2211 | if (ret) |
673a394b EA |
2212 | return ret; |
2213 | } | |
2214 | ||
2215 | return 0; | |
2216 | } | |
2217 | ||
2218 | /** | |
2219 | * Unbinds an object from the GTT aperture. | |
2220 | */ | |
0f973f27 | 2221 | int |
05394f39 | 2222 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2223 | { |
05394f39 | 2224 | struct drm_device *dev = obj->base.dev; |
73aa808f | 2225 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
2226 | int ret = 0; |
2227 | ||
05394f39 | 2228 | if (obj->gtt_space == NULL) |
673a394b EA |
2229 | return 0; |
2230 | ||
05394f39 | 2231 | if (obj->pin_count != 0) { |
673a394b EA |
2232 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
2233 | return -EINVAL; | |
2234 | } | |
2235 | ||
5323fd04 EA |
2236 | /* blow away mappings if mapped through GTT */ |
2237 | i915_gem_release_mmap(obj); | |
2238 | ||
673a394b EA |
2239 | /* Move the object to the CPU domain to ensure that |
2240 | * any possible CPU writes while it's not in the GTT | |
2241 | * are flushed when we go to remap it. This will | |
2242 | * also ensure that all pending GPU writes are finished | |
2243 | * before we unbind. | |
2244 | */ | |
e47c68e9 | 2245 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2246 | if (ret == -ERESTARTSYS) |
673a394b | 2247 | return ret; |
8dc1775d CW |
2248 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2249 | * should be safe and we need to cleanup or else we might | |
2250 | * cause memory corruption through use-after-free. | |
2251 | */ | |
812ed492 CW |
2252 | if (ret) { |
2253 | i915_gem_clflush_object(obj); | |
05394f39 | 2254 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2255 | } |
673a394b | 2256 | |
96b47b65 | 2257 | /* release the fence reg _after_ flushing */ |
05394f39 | 2258 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
96b47b65 DV |
2259 | i915_gem_clear_fence_reg(obj); |
2260 | ||
7c2e6fdf | 2261 | i915_gem_gtt_unbind_object(obj); |
673a394b | 2262 | |
e5281ccd | 2263 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2264 | |
05394f39 CW |
2265 | i915_gem_info_remove_gtt(dev_priv, obj); |
2266 | list_del_init(&obj->mm_list); | |
75e9e915 | 2267 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2268 | obj->map_and_fenceable = true; |
673a394b | 2269 | |
05394f39 CW |
2270 | drm_mm_put_block(obj->gtt_space); |
2271 | obj->gtt_space = NULL; | |
2272 | obj->gtt_offset = 0; | |
673a394b | 2273 | |
05394f39 | 2274 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2275 | i915_gem_object_truncate(obj); |
2276 | ||
1c5d22f7 CW |
2277 | trace_i915_gem_object_unbind(obj); |
2278 | ||
8dc1775d | 2279 | return ret; |
673a394b EA |
2280 | } |
2281 | ||
a56ba56c CW |
2282 | static int i915_ring_idle(struct drm_device *dev, |
2283 | struct intel_ring_buffer *ring) | |
2284 | { | |
395b70be | 2285 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2286 | return 0; |
2287 | ||
05394f39 | 2288 | i915_gem_flush_ring(dev, ring, |
a56ba56c CW |
2289 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
2290 | return i915_wait_request(dev, | |
2291 | i915_gem_next_request_seqno(dev, ring), | |
2292 | ring); | |
2293 | } | |
2294 | ||
b47eb4a2 | 2295 | int |
4df2faf4 DV |
2296 | i915_gpu_idle(struct drm_device *dev) |
2297 | { | |
2298 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2299 | bool lists_empty; | |
852835f3 | 2300 | int ret; |
4df2faf4 | 2301 | |
d1b851fc | 2302 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
395b70be | 2303 | list_empty(&dev_priv->mm.active_list)); |
4df2faf4 DV |
2304 | if (lists_empty) |
2305 | return 0; | |
2306 | ||
2307 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2308 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2309 | if (ret) |
2310 | return ret; | |
d1b851fc | 2311 | |
87acb0a5 CW |
2312 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
2313 | if (ret) | |
2314 | return ret; | |
d1b851fc | 2315 | |
549f7365 CW |
2316 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
2317 | if (ret) | |
2318 | return ret; | |
4df2faf4 | 2319 | |
8a1a49f9 | 2320 | return 0; |
4df2faf4 DV |
2321 | } |
2322 | ||
c6642782 DV |
2323 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
2324 | struct intel_ring_buffer *pipelined) | |
4e901fdc | 2325 | { |
05394f39 | 2326 | struct drm_device *dev = obj->base.dev; |
4e901fdc | 2327 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2328 | u32 size = obj->gtt_space->size; |
2329 | int regnum = obj->fence_reg; | |
4e901fdc EA |
2330 | uint64_t val; |
2331 | ||
05394f39 | 2332 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
c6642782 | 2333 | 0xfffff000) << 32; |
05394f39 CW |
2334 | val |= obj->gtt_offset & 0xfffff000; |
2335 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
4e901fdc EA |
2336 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2337 | ||
05394f39 | 2338 | if (obj->tiling_mode == I915_TILING_Y) |
4e901fdc EA |
2339 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2340 | val |= I965_FENCE_REG_VALID; | |
2341 | ||
c6642782 DV |
2342 | if (pipelined) { |
2343 | int ret = intel_ring_begin(pipelined, 6); | |
2344 | if (ret) | |
2345 | return ret; | |
2346 | ||
2347 | intel_ring_emit(pipelined, MI_NOOP); | |
2348 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2349 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); | |
2350 | intel_ring_emit(pipelined, (u32)val); | |
2351 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); | |
2352 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2353 | intel_ring_advance(pipelined); | |
2354 | } else | |
2355 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); | |
2356 | ||
2357 | return 0; | |
4e901fdc EA |
2358 | } |
2359 | ||
c6642782 DV |
2360 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
2361 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2362 | { |
05394f39 | 2363 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2364 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2365 | u32 size = obj->gtt_space->size; |
2366 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2367 | uint64_t val; |
2368 | ||
05394f39 | 2369 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
de151cf6 | 2370 | 0xfffff000) << 32; |
05394f39 CW |
2371 | val |= obj->gtt_offset & 0xfffff000; |
2372 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2373 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 JB |
2374 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2375 | val |= I965_FENCE_REG_VALID; | |
2376 | ||
c6642782 DV |
2377 | if (pipelined) { |
2378 | int ret = intel_ring_begin(pipelined, 6); | |
2379 | if (ret) | |
2380 | return ret; | |
2381 | ||
2382 | intel_ring_emit(pipelined, MI_NOOP); | |
2383 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2384 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); | |
2385 | intel_ring_emit(pipelined, (u32)val); | |
2386 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); | |
2387 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2388 | intel_ring_advance(pipelined); | |
2389 | } else | |
2390 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); | |
2391 | ||
2392 | return 0; | |
de151cf6 JB |
2393 | } |
2394 | ||
c6642782 DV |
2395 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
2396 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2397 | { |
05394f39 | 2398 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2399 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2400 | u32 size = obj->gtt_space->size; |
c6642782 | 2401 | u32 fence_reg, val, pitch_val; |
0f973f27 | 2402 | int tile_width; |
de151cf6 | 2403 | |
c6642782 DV |
2404 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2405 | (size & -size) != size || | |
2406 | (obj->gtt_offset & (size - 1)), | |
2407 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2408 | obj->gtt_offset, obj->map_and_fenceable, size)) | |
2409 | return -EINVAL; | |
de151cf6 | 2410 | |
c6642782 | 2411 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
0f973f27 | 2412 | tile_width = 128; |
de151cf6 | 2413 | else |
0f973f27 JB |
2414 | tile_width = 512; |
2415 | ||
2416 | /* Note: pitch better be a power of two tile widths */ | |
05394f39 | 2417 | pitch_val = obj->stride / tile_width; |
0f973f27 | 2418 | pitch_val = ffs(pitch_val) - 1; |
de151cf6 | 2419 | |
05394f39 CW |
2420 | val = obj->gtt_offset; |
2421 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2422 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
a00b10c3 | 2423 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2424 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2425 | val |= I830_FENCE_REG_VALID; | |
2426 | ||
05394f39 | 2427 | fence_reg = obj->fence_reg; |
a00b10c3 CW |
2428 | if (fence_reg < 8) |
2429 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2430 | else |
a00b10c3 | 2431 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
c6642782 DV |
2432 | |
2433 | if (pipelined) { | |
2434 | int ret = intel_ring_begin(pipelined, 4); | |
2435 | if (ret) | |
2436 | return ret; | |
2437 | ||
2438 | intel_ring_emit(pipelined, MI_NOOP); | |
2439 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2440 | intel_ring_emit(pipelined, fence_reg); | |
2441 | intel_ring_emit(pipelined, val); | |
2442 | intel_ring_advance(pipelined); | |
2443 | } else | |
2444 | I915_WRITE(fence_reg, val); | |
2445 | ||
2446 | return 0; | |
de151cf6 JB |
2447 | } |
2448 | ||
c6642782 DV |
2449 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
2450 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2451 | { |
05394f39 | 2452 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2453 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2454 | u32 size = obj->gtt_space->size; |
2455 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2456 | uint32_t val; |
2457 | uint32_t pitch_val; | |
2458 | ||
c6642782 DV |
2459 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2460 | (size & -size) != size || | |
2461 | (obj->gtt_offset & (size - 1)), | |
2462 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2463 | obj->gtt_offset, size)) | |
2464 | return -EINVAL; | |
de151cf6 | 2465 | |
05394f39 | 2466 | pitch_val = obj->stride / 128; |
e76a16de | 2467 | pitch_val = ffs(pitch_val) - 1; |
e76a16de | 2468 | |
05394f39 CW |
2469 | val = obj->gtt_offset; |
2470 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2471 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
c6642782 | 2472 | val |= I830_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2473 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2474 | val |= I830_FENCE_REG_VALID; | |
2475 | ||
c6642782 DV |
2476 | if (pipelined) { |
2477 | int ret = intel_ring_begin(pipelined, 4); | |
2478 | if (ret) | |
2479 | return ret; | |
2480 | ||
2481 | intel_ring_emit(pipelined, MI_NOOP); | |
2482 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2483 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); | |
2484 | intel_ring_emit(pipelined, val); | |
2485 | intel_ring_advance(pipelined); | |
2486 | } else | |
2487 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); | |
2488 | ||
2489 | return 0; | |
de151cf6 JB |
2490 | } |
2491 | ||
2cf34d7b CW |
2492 | static int i915_find_fence_reg(struct drm_device *dev, |
2493 | bool interruptible) | |
ae3db24a | 2494 | { |
ae3db24a | 2495 | struct drm_i915_private *dev_priv = dev->dev_private; |
a00b10c3 | 2496 | struct drm_i915_fence_reg *reg; |
05394f39 | 2497 | struct drm_i915_gem_object *obj = NULL; |
ae3db24a DV |
2498 | int i, avail, ret; |
2499 | ||
2500 | /* First try to find a free reg */ | |
2501 | avail = 0; | |
2502 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2503 | reg = &dev_priv->fence_regs[i]; | |
2504 | if (!reg->obj) | |
2505 | return i; | |
2506 | ||
05394f39 CW |
2507 | if (!reg->obj->pin_count) |
2508 | avail++; | |
ae3db24a DV |
2509 | } |
2510 | ||
2511 | if (avail == 0) | |
2512 | return -ENOSPC; | |
2513 | ||
2514 | /* None available, try to steal one or wait for a user to finish */ | |
a00b10c3 | 2515 | avail = I915_FENCE_REG_NONE; |
007cc8ac DV |
2516 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2517 | lru_list) { | |
05394f39 CW |
2518 | obj = reg->obj; |
2519 | if (obj->pin_count) | |
ae3db24a DV |
2520 | continue; |
2521 | ||
2522 | /* found one! */ | |
05394f39 | 2523 | avail = obj->fence_reg; |
ae3db24a DV |
2524 | break; |
2525 | } | |
2526 | ||
a00b10c3 | 2527 | BUG_ON(avail == I915_FENCE_REG_NONE); |
ae3db24a DV |
2528 | |
2529 | /* We only have a reference on obj from the active list. put_fence_reg | |
2530 | * might drop that one, causing a use-after-free in it. So hold a | |
2531 | * private reference to obj like the other callers of put_fence_reg | |
2532 | * (set_tiling ioctl) do. */ | |
05394f39 CW |
2533 | drm_gem_object_reference(&obj->base); |
2534 | ret = i915_gem_object_put_fence_reg(obj, interruptible); | |
2535 | drm_gem_object_unreference(&obj->base); | |
ae3db24a DV |
2536 | if (ret != 0) |
2537 | return ret; | |
2538 | ||
a00b10c3 | 2539 | return avail; |
ae3db24a DV |
2540 | } |
2541 | ||
de151cf6 JB |
2542 | /** |
2543 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2544 | * @obj: object to map through a fence reg | |
2545 | * | |
2546 | * When mapping objects through the GTT, userspace wants to be able to write | |
2547 | * to them without having to worry about swizzling if the object is tiled. | |
2548 | * | |
2549 | * This function walks the fence regs looking for a free one for @obj, | |
2550 | * stealing one if it can't find any. | |
2551 | * | |
2552 | * It then sets up the reg based on the object's properties: address, pitch | |
2553 | * and tiling format. | |
2554 | */ | |
8c4b8c3f | 2555 | int |
05394f39 | 2556 | i915_gem_object_get_fence_reg(struct drm_i915_gem_object *obj, |
2cf34d7b | 2557 | bool interruptible) |
de151cf6 | 2558 | { |
05394f39 | 2559 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2560 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 2561 | struct drm_i915_fence_reg *reg = NULL; |
c6642782 | 2562 | struct intel_ring_buffer *pipelined = NULL; |
ae3db24a | 2563 | int ret; |
de151cf6 | 2564 | |
a09ba7fa | 2565 | /* Just update our place in the LRU if our fence is getting used. */ |
05394f39 CW |
2566 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2567 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2568 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa EA |
2569 | return 0; |
2570 | } | |
2571 | ||
05394f39 | 2572 | switch (obj->tiling_mode) { |
de151cf6 JB |
2573 | case I915_TILING_NONE: |
2574 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2575 | break; | |
2576 | case I915_TILING_X: | |
05394f39 | 2577 | if (!obj->stride) |
0f973f27 | 2578 | return -EINVAL; |
05394f39 | 2579 | WARN((obj->stride & (512 - 1)), |
0f973f27 | 2580 | "object 0x%08x is X tiled but has non-512B pitch\n", |
05394f39 | 2581 | obj->gtt_offset); |
de151cf6 JB |
2582 | break; |
2583 | case I915_TILING_Y: | |
05394f39 | 2584 | if (!obj->stride) |
0f973f27 | 2585 | return -EINVAL; |
05394f39 | 2586 | WARN((obj->stride & (128 - 1)), |
0f973f27 | 2587 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
05394f39 | 2588 | obj->gtt_offset); |
de151cf6 JB |
2589 | break; |
2590 | } | |
2591 | ||
2cf34d7b | 2592 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2593 | if (ret < 0) |
2594 | return ret; | |
de151cf6 | 2595 | |
05394f39 CW |
2596 | obj->fence_reg = ret; |
2597 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2598 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2599 | |
de151cf6 JB |
2600 | reg->obj = obj; |
2601 | ||
e259befd CW |
2602 | switch (INTEL_INFO(dev)->gen) { |
2603 | case 6: | |
c6642782 | 2604 | ret = sandybridge_write_fence_reg(obj, pipelined); |
e259befd CW |
2605 | break; |
2606 | case 5: | |
2607 | case 4: | |
c6642782 | 2608 | ret = i965_write_fence_reg(obj, pipelined); |
e259befd CW |
2609 | break; |
2610 | case 3: | |
c6642782 | 2611 | ret = i915_write_fence_reg(obj, pipelined); |
e259befd CW |
2612 | break; |
2613 | case 2: | |
c6642782 | 2614 | ret = i830_write_fence_reg(obj, pipelined); |
e259befd CW |
2615 | break; |
2616 | } | |
d9ddcb96 | 2617 | |
a00b10c3 | 2618 | trace_i915_gem_object_get_fence(obj, |
05394f39 CW |
2619 | obj->fence_reg, |
2620 | obj->tiling_mode); | |
c6642782 | 2621 | return ret; |
de151cf6 JB |
2622 | } |
2623 | ||
2624 | /** | |
2625 | * i915_gem_clear_fence_reg - clear out fence register info | |
2626 | * @obj: object to clear | |
2627 | * | |
2628 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2629 | * data structures in dev_priv and obj. |
de151cf6 JB |
2630 | */ |
2631 | static void | |
05394f39 | 2632 | i915_gem_clear_fence_reg(struct drm_i915_gem_object *obj) |
de151cf6 | 2633 | { |
05394f39 | 2634 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2635 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2636 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[obj->fence_reg]; |
e259befd | 2637 | uint32_t fence_reg; |
de151cf6 | 2638 | |
e259befd CW |
2639 | switch (INTEL_INFO(dev)->gen) { |
2640 | case 6: | |
4e901fdc | 2641 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
05394f39 | 2642 | (obj->fence_reg * 8), 0); |
e259befd CW |
2643 | break; |
2644 | case 5: | |
2645 | case 4: | |
05394f39 | 2646 | I915_WRITE64(FENCE_REG_965_0 + (obj->fence_reg * 8), 0); |
e259befd CW |
2647 | break; |
2648 | case 3: | |
05394f39 CW |
2649 | if (obj->fence_reg >= 8) |
2650 | fence_reg = FENCE_REG_945_8 + (obj->fence_reg - 8) * 4; | |
dc529a4f | 2651 | else |
e259befd | 2652 | case 2: |
05394f39 | 2653 | fence_reg = FENCE_REG_830_0 + obj->fence_reg * 4; |
dc529a4f EA |
2654 | |
2655 | I915_WRITE(fence_reg, 0); | |
e259befd | 2656 | break; |
dc529a4f | 2657 | } |
de151cf6 | 2658 | |
007cc8ac | 2659 | reg->obj = NULL; |
05394f39 | 2660 | obj->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2661 | list_del_init(®->lru_list); |
de151cf6 JB |
2662 | } |
2663 | ||
52dc7d32 CW |
2664 | /** |
2665 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2666 | * to the buffer to finish, and then resets the fence register. | |
2667 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2668 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2669 | * |
2670 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2671 | * data structures in dev_priv and obj. |
52dc7d32 CW |
2672 | */ |
2673 | int | |
05394f39 | 2674 | i915_gem_object_put_fence_reg(struct drm_i915_gem_object *obj, |
2cf34d7b | 2675 | bool interruptible) |
52dc7d32 | 2676 | { |
05394f39 | 2677 | struct drm_device *dev = obj->base.dev; |
caea7476 | 2678 | int ret; |
52dc7d32 | 2679 | |
05394f39 | 2680 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
52dc7d32 CW |
2681 | return 0; |
2682 | ||
10ae9bd2 DV |
2683 | /* If we've changed tiling, GTT-mappings of the object |
2684 | * need to re-fault to ensure that the correct fence register | |
2685 | * setup is in place. | |
2686 | */ | |
2687 | i915_gem_release_mmap(obj); | |
2688 | ||
52dc7d32 CW |
2689 | /* On the i915, GPU access to tiled buffers is via a fence, |
2690 | * therefore we must wait for any outstanding access to complete | |
2691 | * before clearing the fence. | |
2692 | */ | |
caea7476 | 2693 | if (obj->fenced_gpu_access) { |
919926ae | 2694 | ret = i915_gem_object_flush_gpu_write_domain(obj, NULL); |
0bc23aad | 2695 | if (ret) |
2dafb1e0 CW |
2696 | return ret; |
2697 | ||
caea7476 CW |
2698 | obj->fenced_gpu_access = false; |
2699 | } | |
2700 | ||
2701 | if (obj->last_fenced_seqno) { | |
2702 | ret = i915_do_wait_request(dev, | |
2703 | obj->last_fenced_seqno, | |
2704 | interruptible, | |
2705 | obj->last_fenced_ring); | |
0bc23aad | 2706 | if (ret) |
52dc7d32 | 2707 | return ret; |
53640e1d | 2708 | |
caea7476 | 2709 | obj->last_fenced_seqno = false; |
52dc7d32 CW |
2710 | } |
2711 | ||
4a726612 | 2712 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2713 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2714 | |
2715 | return 0; | |
2716 | } | |
2717 | ||
673a394b EA |
2718 | /** |
2719 | * Finds free space in the GTT aperture and binds the object there. | |
2720 | */ | |
2721 | static int | |
05394f39 | 2722 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2723 | unsigned alignment, |
75e9e915 | 2724 | bool map_and_fenceable) |
673a394b | 2725 | { |
05394f39 | 2726 | struct drm_device *dev = obj->base.dev; |
673a394b | 2727 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2728 | struct drm_mm_node *free_space; |
a00b10c3 | 2729 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2730 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2731 | bool mappable, fenceable; |
07f73f69 | 2732 | int ret; |
673a394b | 2733 | |
05394f39 | 2734 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2735 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2736 | return -EINVAL; | |
2737 | } | |
2738 | ||
05394f39 CW |
2739 | fence_size = i915_gem_get_gtt_size(obj); |
2740 | fence_alignment = i915_gem_get_gtt_alignment(obj); | |
2741 | unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj); | |
a00b10c3 | 2742 | |
673a394b | 2743 | if (alignment == 0) |
5e783301 DV |
2744 | alignment = map_and_fenceable ? fence_alignment : |
2745 | unfenced_alignment; | |
75e9e915 | 2746 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2747 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2748 | return -EINVAL; | |
2749 | } | |
2750 | ||
05394f39 | 2751 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2752 | |
654fc607 CW |
2753 | /* If the object is bigger than the entire aperture, reject it early |
2754 | * before evicting everything in a vain attempt to find space. | |
2755 | */ | |
05394f39 | 2756 | if (obj->base.size > |
75e9e915 | 2757 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2758 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2759 | return -E2BIG; | |
2760 | } | |
2761 | ||
673a394b | 2762 | search_free: |
75e9e915 | 2763 | if (map_and_fenceable) |
920afa77 DV |
2764 | free_space = |
2765 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2766 | size, alignment, 0, |
920afa77 DV |
2767 | dev_priv->mm.gtt_mappable_end, |
2768 | 0); | |
2769 | else | |
2770 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2771 | size, alignment, 0); |
920afa77 DV |
2772 | |
2773 | if (free_space != NULL) { | |
75e9e915 | 2774 | if (map_and_fenceable) |
05394f39 | 2775 | obj->gtt_space = |
920afa77 | 2776 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2777 | size, alignment, 0, |
920afa77 DV |
2778 | dev_priv->mm.gtt_mappable_end, |
2779 | 0); | |
2780 | else | |
05394f39 | 2781 | obj->gtt_space = |
a00b10c3 | 2782 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2783 | } |
05394f39 | 2784 | if (obj->gtt_space == NULL) { |
673a394b EA |
2785 | /* If the gtt is empty and we're still having trouble |
2786 | * fitting our object in, we're out of memory. | |
2787 | */ | |
75e9e915 DV |
2788 | ret = i915_gem_evict_something(dev, size, alignment, |
2789 | map_and_fenceable); | |
9731129c | 2790 | if (ret) |
673a394b | 2791 | return ret; |
9731129c | 2792 | |
673a394b EA |
2793 | goto search_free; |
2794 | } | |
2795 | ||
e5281ccd | 2796 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2797 | if (ret) { |
05394f39 CW |
2798 | drm_mm_put_block(obj->gtt_space); |
2799 | obj->gtt_space = NULL; | |
07f73f69 CW |
2800 | |
2801 | if (ret == -ENOMEM) { | |
2802 | /* first try to clear up some space from the GTT */ | |
a00b10c3 | 2803 | ret = i915_gem_evict_something(dev, size, |
75e9e915 DV |
2804 | alignment, |
2805 | map_and_fenceable); | |
07f73f69 | 2806 | if (ret) { |
07f73f69 | 2807 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2808 | if (gfpmask) { |
2809 | gfpmask = 0; | |
2810 | goto search_free; | |
07f73f69 CW |
2811 | } |
2812 | ||
2813 | return ret; | |
2814 | } | |
2815 | ||
2816 | goto search_free; | |
2817 | } | |
2818 | ||
673a394b EA |
2819 | return ret; |
2820 | } | |
2821 | ||
7c2e6fdf DV |
2822 | ret = i915_gem_gtt_bind_object(obj); |
2823 | if (ret) { | |
e5281ccd | 2824 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2825 | drm_mm_put_block(obj->gtt_space); |
2826 | obj->gtt_space = NULL; | |
07f73f69 | 2827 | |
a00b10c3 | 2828 | ret = i915_gem_evict_something(dev, size, |
75e9e915 | 2829 | alignment, map_and_fenceable); |
9731129c | 2830 | if (ret) |
07f73f69 | 2831 | return ret; |
07f73f69 CW |
2832 | |
2833 | goto search_free; | |
673a394b | 2834 | } |
673a394b | 2835 | |
05394f39 | 2836 | obj->gtt_offset = obj->gtt_space->start; |
fb7d516a | 2837 | |
bf1a1092 | 2838 | /* keep track of bounds object by adding it to the inactive list */ |
05394f39 CW |
2839 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
2840 | i915_gem_info_add_gtt(dev_priv, obj); | |
bf1a1092 | 2841 | |
673a394b EA |
2842 | /* Assert that the object is not currently in any GPU domain. As it |
2843 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2844 | * a GPU cache | |
2845 | */ | |
05394f39 CW |
2846 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2847 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2848 | |
05394f39 | 2849 | trace_i915_gem_object_bind(obj, obj->gtt_offset, map_and_fenceable); |
1c5d22f7 | 2850 | |
75e9e915 | 2851 | fenceable = |
05394f39 CW |
2852 | obj->gtt_space->size == fence_size && |
2853 | (obj->gtt_space->start & (fence_alignment -1)) == 0; | |
a00b10c3 | 2854 | |
75e9e915 | 2855 | mappable = |
05394f39 | 2856 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2857 | |
05394f39 | 2858 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2859 | |
673a394b EA |
2860 | return 0; |
2861 | } | |
2862 | ||
2863 | void | |
05394f39 | 2864 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2865 | { |
673a394b EA |
2866 | /* If we don't have a page list set up, then we're not pinned |
2867 | * to GPU, and we can ignore the cache flush because it'll happen | |
2868 | * again at bind time. | |
2869 | */ | |
05394f39 | 2870 | if (obj->pages == NULL) |
673a394b EA |
2871 | return; |
2872 | ||
1c5d22f7 | 2873 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2874 | |
05394f39 | 2875 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2876 | } |
2877 | ||
e47c68e9 | 2878 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2879 | static int |
05394f39 | 2880 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj, |
919926ae | 2881 | struct intel_ring_buffer *pipelined) |
e47c68e9 | 2882 | { |
05394f39 | 2883 | struct drm_device *dev = obj->base.dev; |
e47c68e9 | 2884 | |
05394f39 | 2885 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
2dafb1e0 | 2886 | return 0; |
e47c68e9 EA |
2887 | |
2888 | /* Queue the GPU write cache flushing we need. */ | |
05394f39 CW |
2889 | i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain); |
2890 | BUG_ON(obj->base.write_domain); | |
1c5d22f7 | 2891 | |
919926ae | 2892 | if (pipelined && pipelined == obj->ring) |
ba3d8d74 DV |
2893 | return 0; |
2894 | ||
2cf34d7b | 2895 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2896 | } |
2897 | ||
2898 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2899 | static void | |
05394f39 | 2900 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2901 | { |
1c5d22f7 CW |
2902 | uint32_t old_write_domain; |
2903 | ||
05394f39 | 2904 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2905 | return; |
2906 | ||
2907 | /* No actual flushing is required for the GTT write domain. Writes | |
2908 | * to it immediately go to main memory as far as we know, so there's | |
2909 | * no chipset flush. It also doesn't land in render cache. | |
2910 | */ | |
4a684a41 CW |
2911 | i915_gem_release_mmap(obj); |
2912 | ||
05394f39 CW |
2913 | old_write_domain = obj->base.write_domain; |
2914 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2915 | |
2916 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2917 | obj->base.read_domains, |
1c5d22f7 | 2918 | old_write_domain); |
e47c68e9 EA |
2919 | } |
2920 | ||
2921 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2922 | static void | |
05394f39 | 2923 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2924 | { |
1c5d22f7 | 2925 | uint32_t old_write_domain; |
e47c68e9 | 2926 | |
05394f39 | 2927 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2928 | return; |
2929 | ||
2930 | i915_gem_clflush_object(obj); | |
40ce6575 | 2931 | intel_gtt_chipset_flush(); |
05394f39 CW |
2932 | old_write_domain = obj->base.write_domain; |
2933 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2934 | |
2935 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2936 | obj->base.read_domains, |
1c5d22f7 | 2937 | old_write_domain); |
e47c68e9 EA |
2938 | } |
2939 | ||
2ef7eeaa EA |
2940 | /** |
2941 | * Moves a single object to the GTT read, and possibly write domain. | |
2942 | * | |
2943 | * This function returns when the move is complete, including waiting on | |
2944 | * flushes to occur. | |
2945 | */ | |
79e53945 | 2946 | int |
2021746e | 2947 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2948 | { |
1c5d22f7 | 2949 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2950 | int ret; |
2ef7eeaa | 2951 | |
02354392 | 2952 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2953 | if (obj->gtt_space == NULL) |
02354392 EA |
2954 | return -EINVAL; |
2955 | ||
919926ae | 2956 | ret = i915_gem_object_flush_gpu_write_domain(obj, NULL); |
2dafb1e0 CW |
2957 | if (ret != 0) |
2958 | return ret; | |
2959 | ||
7213342d | 2960 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2961 | |
ba3d8d74 | 2962 | if (write) { |
2cf34d7b | 2963 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2964 | if (ret) |
2965 | return ret; | |
ba3d8d74 | 2966 | } |
e47c68e9 | 2967 | |
05394f39 CW |
2968 | old_write_domain = obj->base.write_domain; |
2969 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2970 | |
e47c68e9 EA |
2971 | /* It should now be out of any other write domains, and we can update |
2972 | * the domain values for our changes. | |
2973 | */ | |
05394f39 CW |
2974 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2975 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2976 | if (write) { |
05394f39 CW |
2977 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2978 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2979 | obj->dirty = 1; | |
2ef7eeaa EA |
2980 | } |
2981 | ||
1c5d22f7 CW |
2982 | trace_i915_gem_object_change_domain(obj, |
2983 | old_read_domains, | |
2984 | old_write_domain); | |
2985 | ||
e47c68e9 EA |
2986 | return 0; |
2987 | } | |
2988 | ||
b9241ea3 ZW |
2989 | /* |
2990 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2991 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2992 | */ | |
2993 | int | |
05394f39 | 2994 | i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, |
919926ae | 2995 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 2996 | { |
ba3d8d74 | 2997 | uint32_t old_read_domains; |
b9241ea3 ZW |
2998 | int ret; |
2999 | ||
3000 | /* Not valid to be called on unbound objects. */ | |
05394f39 | 3001 | if (obj->gtt_space == NULL) |
b9241ea3 ZW |
3002 | return -EINVAL; |
3003 | ||
919926ae | 3004 | ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined); |
2dafb1e0 CW |
3005 | if (ret) |
3006 | return ret; | |
b9241ea3 | 3007 | |
ced270fa CW |
3008 | /* Currently, we are always called from an non-interruptible context. */ |
3009 | if (!pipelined) { | |
3010 | ret = i915_gem_object_wait_rendering(obj, false); | |
3011 | if (ret) | |
b9241ea3 ZW |
3012 | return ret; |
3013 | } | |
3014 | ||
b118c1e3 CW |
3015 | i915_gem_object_flush_cpu_write_domain(obj); |
3016 | ||
05394f39 CW |
3017 | old_read_domains = obj->base.read_domains; |
3018 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
b9241ea3 ZW |
3019 | |
3020 | trace_i915_gem_object_change_domain(obj, | |
3021 | old_read_domains, | |
05394f39 | 3022 | obj->base.write_domain); |
b9241ea3 ZW |
3023 | |
3024 | return 0; | |
3025 | } | |
3026 | ||
85345517 CW |
3027 | int |
3028 | i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj, | |
3029 | bool interruptible) | |
3030 | { | |
3031 | if (!obj->active) | |
3032 | return 0; | |
3033 | ||
3034 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) | |
05394f39 | 3035 | i915_gem_flush_ring(obj->base.dev, obj->ring, |
85345517 CW |
3036 | 0, obj->base.write_domain); |
3037 | ||
05394f39 | 3038 | return i915_gem_object_wait_rendering(obj, interruptible); |
85345517 CW |
3039 | } |
3040 | ||
e47c68e9 EA |
3041 | /** |
3042 | * Moves a single object to the CPU read, and possibly write domain. | |
3043 | * | |
3044 | * This function returns when the move is complete, including waiting on | |
3045 | * flushes to occur. | |
3046 | */ | |
3047 | static int | |
919926ae | 3048 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3049 | { |
1c5d22f7 | 3050 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3051 | int ret; |
3052 | ||
ba3d8d74 | 3053 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
3054 | if (ret != 0) |
3055 | return ret; | |
2ef7eeaa | 3056 | |
e47c68e9 | 3057 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3058 | |
e47c68e9 EA |
3059 | /* If we have a partially-valid cache of the object in the CPU, |
3060 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3061 | */ |
e47c68e9 | 3062 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3063 | |
7213342d | 3064 | if (write) { |
2cf34d7b | 3065 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
3066 | if (ret) |
3067 | return ret; | |
3068 | } | |
3069 | ||
05394f39 CW |
3070 | old_write_domain = obj->base.write_domain; |
3071 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3072 | |
e47c68e9 | 3073 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3074 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3075 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3076 | |
05394f39 | 3077 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3078 | } |
3079 | ||
3080 | /* It should now be out of any other write domains, and we can update | |
3081 | * the domain values for our changes. | |
3082 | */ | |
05394f39 | 3083 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3084 | |
3085 | /* If we're writing through the CPU, then the GPU read domains will | |
3086 | * need to be invalidated at next use. | |
3087 | */ | |
3088 | if (write) { | |
05394f39 CW |
3089 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3090 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3091 | } |
2ef7eeaa | 3092 | |
1c5d22f7 CW |
3093 | trace_i915_gem_object_change_domain(obj, |
3094 | old_read_domains, | |
3095 | old_write_domain); | |
3096 | ||
2ef7eeaa EA |
3097 | return 0; |
3098 | } | |
3099 | ||
673a394b EA |
3100 | /* |
3101 | * Set the next domain for the specified object. This | |
3102 | * may not actually perform the necessary flushing/invaliding though, | |
3103 | * as that may want to be batched with other set_domain operations | |
3104 | * | |
3105 | * This is (we hope) the only really tricky part of gem. The goal | |
3106 | * is fairly simple -- track which caches hold bits of the object | |
3107 | * and make sure they remain coherent. A few concrete examples may | |
3108 | * help to explain how it works. For shorthand, we use the notation | |
3109 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
3110 | * a pair of read and write domain masks. | |
3111 | * | |
3112 | * Case 1: the batch buffer | |
3113 | * | |
3114 | * 1. Allocated | |
3115 | * 2. Written by CPU | |
3116 | * 3. Mapped to GTT | |
3117 | * 4. Read by GPU | |
3118 | * 5. Unmapped from GTT | |
3119 | * 6. Freed | |
3120 | * | |
3121 | * Let's take these a step at a time | |
3122 | * | |
3123 | * 1. Allocated | |
3124 | * Pages allocated from the kernel may still have | |
3125 | * cache contents, so we set them to (CPU, CPU) always. | |
3126 | * 2. Written by CPU (using pwrite) | |
3127 | * The pwrite function calls set_domain (CPU, CPU) and | |
3128 | * this function does nothing (as nothing changes) | |
3129 | * 3. Mapped by GTT | |
3130 | * This function asserts that the object is not | |
3131 | * currently in any GPU-based read or write domains | |
3132 | * 4. Read by GPU | |
3133 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
3134 | * As write_domain is zero, this function adds in the | |
3135 | * current read domains (CPU+COMMAND, 0). | |
3136 | * flush_domains is set to CPU. | |
3137 | * invalidate_domains is set to COMMAND | |
3138 | * clflush is run to get data out of the CPU caches | |
3139 | * then i915_dev_set_domain calls i915_gem_flush to | |
3140 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
3141 | * 5. Unmapped from GTT | |
3142 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
3143 | * flush_domains and invalidate_domains end up both zero | |
3144 | * so no flushing/invalidating happens | |
3145 | * 6. Freed | |
3146 | * yay, done | |
3147 | * | |
3148 | * Case 2: The shared render buffer | |
3149 | * | |
3150 | * 1. Allocated | |
3151 | * 2. Mapped to GTT | |
3152 | * 3. Read/written by GPU | |
3153 | * 4. set_domain to (CPU,CPU) | |
3154 | * 5. Read/written by CPU | |
3155 | * 6. Read/written by GPU | |
3156 | * | |
3157 | * 1. Allocated | |
3158 | * Same as last example, (CPU, CPU) | |
3159 | * 2. Mapped to GTT | |
3160 | * Nothing changes (assertions find that it is not in the GPU) | |
3161 | * 3. Read/written by GPU | |
3162 | * execbuffer calls set_domain (RENDER, RENDER) | |
3163 | * flush_domains gets CPU | |
3164 | * invalidate_domains gets GPU | |
3165 | * clflush (obj) | |
3166 | * MI_FLUSH and drm_agp_chipset_flush | |
3167 | * 4. set_domain (CPU, CPU) | |
3168 | * flush_domains gets GPU | |
3169 | * invalidate_domains gets CPU | |
3170 | * wait_rendering (obj) to make sure all drawing is complete. | |
3171 | * This will include an MI_FLUSH to get the data from GPU | |
3172 | * to memory | |
3173 | * clflush (obj) to invalidate the CPU cache | |
3174 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3175 | * 5. Read/written by CPU | |
3176 | * cache lines are loaded and dirtied | |
3177 | * 6. Read written by GPU | |
3178 | * Same as last GPU access | |
3179 | * | |
3180 | * Case 3: The constant buffer | |
3181 | * | |
3182 | * 1. Allocated | |
3183 | * 2. Written by CPU | |
3184 | * 3. Read by GPU | |
3185 | * 4. Updated (written) by CPU again | |
3186 | * 5. Read by GPU | |
3187 | * | |
3188 | * 1. Allocated | |
3189 | * (CPU, CPU) | |
3190 | * 2. Written by CPU | |
3191 | * (CPU, CPU) | |
3192 | * 3. Read by GPU | |
3193 | * (CPU+RENDER, 0) | |
3194 | * flush_domains = CPU | |
3195 | * invalidate_domains = RENDER | |
3196 | * clflush (obj) | |
3197 | * MI_FLUSH | |
3198 | * drm_agp_chipset_flush | |
3199 | * 4. Updated (written) by CPU again | |
3200 | * (CPU, CPU) | |
3201 | * flush_domains = 0 (no previous write domain) | |
3202 | * invalidate_domains = 0 (no new read domains) | |
3203 | * 5. Read by GPU | |
3204 | * (CPU+RENDER, 0) | |
3205 | * flush_domains = CPU | |
3206 | * invalidate_domains = RENDER | |
3207 | * clflush (obj) | |
3208 | * MI_FLUSH | |
3209 | * drm_agp_chipset_flush | |
3210 | */ | |
c0d90829 | 3211 | static void |
05394f39 | 3212 | i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj, |
0f8c6d7c CW |
3213 | struct intel_ring_buffer *ring, |
3214 | struct change_domains *cd) | |
673a394b | 3215 | { |
05394f39 | 3216 | uint32_t invalidate_domains = 0, flush_domains = 0; |
652c393a | 3217 | |
673a394b EA |
3218 | /* |
3219 | * If the object isn't moving to a new write domain, | |
3220 | * let the object stay in multiple read domains | |
3221 | */ | |
05394f39 CW |
3222 | if (obj->base.pending_write_domain == 0) |
3223 | obj->base.pending_read_domains |= obj->base.read_domains; | |
673a394b EA |
3224 | |
3225 | /* | |
3226 | * Flush the current write domain if | |
3227 | * the new read domains don't match. Invalidate | |
3228 | * any read domains which differ from the old | |
3229 | * write domain | |
3230 | */ | |
05394f39 | 3231 | if (obj->base.write_domain && |
caea7476 CW |
3232 | (((obj->base.write_domain != obj->base.pending_read_domains || |
3233 | obj->ring != ring)) || | |
3234 | (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) { | |
05394f39 | 3235 | flush_domains |= obj->base.write_domain; |
8b0e378a | 3236 | invalidate_domains |= |
05394f39 | 3237 | obj->base.pending_read_domains & ~obj->base.write_domain; |
673a394b EA |
3238 | } |
3239 | /* | |
3240 | * Invalidate any read caches which may have | |
3241 | * stale data. That is, any new read domains. | |
3242 | */ | |
05394f39 | 3243 | invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains; |
3d2a812a | 3244 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3245 | i915_gem_clflush_object(obj); |
673a394b | 3246 | |
4a684a41 CW |
3247 | /* blow away mappings if mapped through GTT */ |
3248 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT) | |
3249 | i915_gem_release_mmap(obj); | |
3250 | ||
efbeed96 EA |
3251 | /* The actual obj->write_domain will be updated with |
3252 | * pending_write_domain after we emit the accumulated flush for all | |
3253 | * of our domain changes in execbuffers (which clears objects' | |
3254 | * write_domains). So if we have a current write domain that we | |
3255 | * aren't changing, set pending_write_domain to that. | |
3256 | */ | |
05394f39 CW |
3257 | if (flush_domains == 0 && obj->base.pending_write_domain == 0) |
3258 | obj->base.pending_write_domain = obj->base.write_domain; | |
673a394b | 3259 | |
0f8c6d7c CW |
3260 | cd->invalidate_domains |= invalidate_domains; |
3261 | cd->flush_domains |= flush_domains; | |
b6651458 | 3262 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
05394f39 | 3263 | cd->flush_rings |= obj->ring->id; |
b6651458 | 3264 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
0f8c6d7c | 3265 | cd->flush_rings |= ring->id; |
673a394b EA |
3266 | } |
3267 | ||
3268 | /** | |
e47c68e9 | 3269 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3270 | * |
e47c68e9 EA |
3271 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3272 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3273 | */ |
e47c68e9 | 3274 | static void |
05394f39 | 3275 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
673a394b | 3276 | { |
05394f39 | 3277 | if (!obj->page_cpu_valid) |
e47c68e9 EA |
3278 | return; |
3279 | ||
3280 | /* If we're partially in the CPU read domain, finish moving it in. | |
3281 | */ | |
05394f39 | 3282 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
e47c68e9 EA |
3283 | int i; |
3284 | ||
05394f39 CW |
3285 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
3286 | if (obj->page_cpu_valid[i]) | |
e47c68e9 | 3287 | continue; |
05394f39 | 3288 | drm_clflush_pages(obj->pages + i, 1); |
e47c68e9 | 3289 | } |
e47c68e9 EA |
3290 | } |
3291 | ||
3292 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3293 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3294 | */ | |
05394f39 CW |
3295 | kfree(obj->page_cpu_valid); |
3296 | obj->page_cpu_valid = NULL; | |
e47c68e9 EA |
3297 | } |
3298 | ||
3299 | /** | |
3300 | * Set the CPU read domain on a range of the object. | |
3301 | * | |
3302 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3303 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3304 | * pages have been flushed, and will be respected by | |
3305 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3306 | * of the whole object. | |
3307 | * | |
3308 | * This function returns when the move is complete, including waiting on | |
3309 | * flushes to occur. | |
3310 | */ | |
3311 | static int | |
05394f39 | 3312 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
3313 | uint64_t offset, uint64_t size) |
3314 | { | |
1c5d22f7 | 3315 | uint32_t old_read_domains; |
e47c68e9 | 3316 | int i, ret; |
673a394b | 3317 | |
05394f39 | 3318 | if (offset == 0 && size == obj->base.size) |
e47c68e9 | 3319 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
673a394b | 3320 | |
ba3d8d74 | 3321 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3322 | if (ret != 0) |
6a47baa6 | 3323 | return ret; |
e47c68e9 EA |
3324 | i915_gem_object_flush_gtt_write_domain(obj); |
3325 | ||
3326 | /* If we're already fully in the CPU read domain, we're done. */ | |
05394f39 CW |
3327 | if (obj->page_cpu_valid == NULL && |
3328 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
e47c68e9 | 3329 | return 0; |
673a394b | 3330 | |
e47c68e9 EA |
3331 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3332 | * newly adding I915_GEM_DOMAIN_CPU | |
3333 | */ | |
05394f39 CW |
3334 | if (obj->page_cpu_valid == NULL) { |
3335 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, | |
3336 | GFP_KERNEL); | |
3337 | if (obj->page_cpu_valid == NULL) | |
e47c68e9 | 3338 | return -ENOMEM; |
05394f39 CW |
3339 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
3340 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); | |
673a394b EA |
3341 | |
3342 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3343 | * perspective. | |
3344 | */ | |
e47c68e9 EA |
3345 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3346 | i++) { | |
05394f39 | 3347 | if (obj->page_cpu_valid[i]) |
673a394b EA |
3348 | continue; |
3349 | ||
05394f39 | 3350 | drm_clflush_pages(obj->pages + i, 1); |
673a394b | 3351 | |
05394f39 | 3352 | obj->page_cpu_valid[i] = 1; |
673a394b EA |
3353 | } |
3354 | ||
e47c68e9 EA |
3355 | /* It should now be out of any other write domains, and we can update |
3356 | * the domain values for our changes. | |
3357 | */ | |
05394f39 | 3358 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 | 3359 | |
05394f39 CW |
3360 | old_read_domains = obj->base.read_domains; |
3361 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3362 | |
1c5d22f7 CW |
3363 | trace_i915_gem_object_change_domain(obj, |
3364 | old_read_domains, | |
05394f39 | 3365 | obj->base.write_domain); |
1c5d22f7 | 3366 | |
673a394b EA |
3367 | return 0; |
3368 | } | |
3369 | ||
673a394b | 3370 | static int |
bcf50e27 CW |
3371 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, |
3372 | struct drm_file *file_priv, | |
3373 | struct drm_i915_gem_exec_object2 *entry, | |
3374 | struct drm_i915_gem_relocation_entry *reloc) | |
673a394b | 3375 | { |
9af90d19 | 3376 | struct drm_device *dev = obj->base.dev; |
bcf50e27 CW |
3377 | struct drm_gem_object *target_obj; |
3378 | uint32_t target_offset; | |
3379 | int ret = -EINVAL; | |
673a394b | 3380 | |
bcf50e27 CW |
3381 | target_obj = drm_gem_object_lookup(dev, file_priv, |
3382 | reloc->target_handle); | |
3383 | if (target_obj == NULL) | |
3384 | return -ENOENT; | |
673a394b | 3385 | |
bcf50e27 | 3386 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
76446cac | 3387 | |
bcf50e27 CW |
3388 | #if WATCH_RELOC |
3389 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3390 | "read %08x write %08x gtt %08x " | |
3391 | "presumed %08x delta %08x\n", | |
3392 | __func__, | |
3393 | obj, | |
3394 | (int) reloc->offset, | |
3395 | (int) reloc->target_handle, | |
3396 | (int) reloc->read_domains, | |
3397 | (int) reloc->write_domain, | |
3398 | (int) target_offset, | |
3399 | (int) reloc->presumed_offset, | |
3400 | reloc->delta); | |
3401 | #endif | |
673a394b | 3402 | |
bcf50e27 CW |
3403 | /* The target buffer should have appeared before us in the |
3404 | * exec_object list, so it should have a GTT space bound by now. | |
3405 | */ | |
3406 | if (target_offset == 0) { | |
3407 | DRM_ERROR("No GTT space found for object %d\n", | |
3408 | reloc->target_handle); | |
3409 | goto err; | |
3410 | } | |
9af90d19 | 3411 | |
bcf50e27 CW |
3412 | /* Validate that the target is in a valid r/w GPU domain */ |
3413 | if (reloc->write_domain & (reloc->write_domain - 1)) { | |
3414 | DRM_ERROR("reloc with multiple write domains: " | |
3415 | "obj %p target %d offset %d " | |
3416 | "read %08x write %08x", | |
3417 | obj, reloc->target_handle, | |
3418 | (int) reloc->offset, | |
3419 | reloc->read_domains, | |
3420 | reloc->write_domain); | |
3421 | goto err; | |
3422 | } | |
3423 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || | |
3424 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { | |
3425 | DRM_ERROR("reloc with read/write CPU domains: " | |
3426 | "obj %p target %d offset %d " | |
3427 | "read %08x write %08x", | |
3428 | obj, reloc->target_handle, | |
3429 | (int) reloc->offset, | |
3430 | reloc->read_domains, | |
3431 | reloc->write_domain); | |
3432 | goto err; | |
3433 | } | |
3434 | if (reloc->write_domain && target_obj->pending_write_domain && | |
3435 | reloc->write_domain != target_obj->pending_write_domain) { | |
3436 | DRM_ERROR("Write domain conflict: " | |
3437 | "obj %p target %d offset %d " | |
3438 | "new %08x old %08x\n", | |
3439 | obj, reloc->target_handle, | |
3440 | (int) reloc->offset, | |
3441 | reloc->write_domain, | |
3442 | target_obj->pending_write_domain); | |
3443 | goto err; | |
3444 | } | |
673a394b | 3445 | |
bcf50e27 CW |
3446 | target_obj->pending_read_domains |= reloc->read_domains; |
3447 | target_obj->pending_write_domain |= reloc->write_domain; | |
8542a0bb | 3448 | |
bcf50e27 CW |
3449 | /* If the relocation already has the right value in it, no |
3450 | * more work needs to be done. | |
3451 | */ | |
3452 | if (target_offset == reloc->presumed_offset) | |
3453 | goto out; | |
673a394b | 3454 | |
bcf50e27 CW |
3455 | /* Check that the relocation address is valid... */ |
3456 | if (reloc->offset > obj->base.size - 4) { | |
3457 | DRM_ERROR("Relocation beyond object bounds: " | |
3458 | "obj %p target %d offset %d size %d.\n", | |
3459 | obj, reloc->target_handle, | |
3460 | (int) reloc->offset, | |
3461 | (int) obj->base.size); | |
3462 | goto err; | |
3463 | } | |
3464 | if (reloc->offset & 3) { | |
3465 | DRM_ERROR("Relocation not 4-byte aligned: " | |
3466 | "obj %p target %d offset %d.\n", | |
3467 | obj, reloc->target_handle, | |
3468 | (int) reloc->offset); | |
3469 | goto err; | |
3470 | } | |
673a394b | 3471 | |
bcf50e27 CW |
3472 | /* and points to somewhere within the target object. */ |
3473 | if (reloc->delta >= target_obj->size) { | |
3474 | DRM_ERROR("Relocation beyond target object bounds: " | |
3475 | "obj %p target %d delta %d size %d.\n", | |
3476 | obj, reloc->target_handle, | |
3477 | (int) reloc->delta, | |
3478 | (int) target_obj->size); | |
3479 | goto err; | |
3480 | } | |
673a394b | 3481 | |
bcf50e27 CW |
3482 | reloc->delta += target_offset; |
3483 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { | |
3484 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; | |
3485 | char *vaddr; | |
673a394b | 3486 | |
bcf50e27 CW |
3487 | vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]); |
3488 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; | |
3489 | kunmap_atomic(vaddr); | |
3490 | } else { | |
3491 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3492 | uint32_t __iomem *reloc_entry; | |
3493 | void __iomem *reloc_page; | |
8542a0bb | 3494 | |
05394f39 | 3495 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
bcf50e27 CW |
3496 | if (ret) |
3497 | goto err; | |
673a394b | 3498 | |
bcf50e27 CW |
3499 | /* Map the page containing the relocation we're going to perform. */ |
3500 | reloc->offset += obj->gtt_offset; | |
3501 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
3502 | reloc->offset & PAGE_MASK); | |
3503 | reloc_entry = (uint32_t __iomem *) | |
3504 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
3505 | iowrite32(reloc->delta, reloc_entry); | |
3506 | io_mapping_unmap_atomic(reloc_page); | |
3507 | } | |
673a394b | 3508 | |
bcf50e27 CW |
3509 | /* and update the user's relocation entry */ |
3510 | reloc->presumed_offset = target_offset; | |
b962442e | 3511 | |
bcf50e27 CW |
3512 | out: |
3513 | ret = 0; | |
3514 | err: | |
3515 | drm_gem_object_unreference(target_obj); | |
3516 | return ret; | |
3517 | } | |
b962442e | 3518 | |
bcf50e27 CW |
3519 | static int |
3520 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
3521 | struct drm_file *file_priv, | |
3522 | struct drm_i915_gem_exec_object2 *entry) | |
3523 | { | |
3524 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3525 | int i, ret; | |
3526 | ||
3527 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; | |
3528 | for (i = 0; i < entry->relocation_count; i++) { | |
3529 | struct drm_i915_gem_relocation_entry reloc; | |
3530 | ||
3531 | if (__copy_from_user_inatomic(&reloc, | |
3532 | user_relocs+i, | |
3533 | sizeof(reloc))) | |
3534 | return -EFAULT; | |
3535 | ||
3536 | ret = i915_gem_execbuffer_relocate_entry(obj, file_priv, entry, &reloc); | |
3537 | if (ret) | |
3538 | return ret; | |
b962442e | 3539 | |
b5dc608c | 3540 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, |
bcf50e27 CW |
3541 | &reloc.presumed_offset, |
3542 | sizeof(reloc.presumed_offset))) | |
3543 | return -EFAULT; | |
b962442e | 3544 | } |
b962442e | 3545 | |
bcf50e27 CW |
3546 | return 0; |
3547 | } | |
3548 | ||
3549 | static int | |
3550 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
3551 | struct drm_file *file_priv, | |
3552 | struct drm_i915_gem_exec_object2 *entry, | |
3553 | struct drm_i915_gem_relocation_entry *relocs) | |
3554 | { | |
3555 | int i, ret; | |
3556 | ||
3557 | for (i = 0; i < entry->relocation_count; i++) { | |
3558 | ret = i915_gem_execbuffer_relocate_entry(obj, file_priv, entry, &relocs[i]); | |
3559 | if (ret) | |
3560 | return ret; | |
3561 | } | |
3562 | ||
3563 | return 0; | |
673a394b EA |
3564 | } |
3565 | ||
40a5f0de | 3566 | static int |
bcf50e27 CW |
3567 | i915_gem_execbuffer_relocate(struct drm_device *dev, |
3568 | struct drm_file *file, | |
05394f39 | 3569 | struct drm_i915_gem_object **object_list, |
bcf50e27 CW |
3570 | struct drm_i915_gem_exec_object2 *exec_list, |
3571 | int count) | |
3572 | { | |
3573 | int i, ret; | |
3574 | ||
3575 | for (i = 0; i < count; i++) { | |
05394f39 | 3576 | struct drm_i915_gem_object *obj = object_list[i]; |
bcf50e27 CW |
3577 | obj->base.pending_read_domains = 0; |
3578 | obj->base.pending_write_domain = 0; | |
3579 | ret = i915_gem_execbuffer_relocate_object(obj, file, | |
3580 | &exec_list[i]); | |
3581 | if (ret) | |
3582 | return ret; | |
3583 | } | |
3584 | ||
3585 | return 0; | |
673a394b EA |
3586 | } |
3587 | ||
40a5f0de | 3588 | static int |
bcf50e27 CW |
3589 | i915_gem_execbuffer_reserve(struct drm_device *dev, |
3590 | struct drm_file *file, | |
05394f39 | 3591 | struct drm_i915_gem_object **object_list, |
bcf50e27 CW |
3592 | struct drm_i915_gem_exec_object2 *exec_list, |
3593 | int count) | |
40a5f0de | 3594 | { |
9af90d19 | 3595 | int ret, i, retry; |
40a5f0de | 3596 | |
a7a09aeb CW |
3597 | /* Attempt to pin all of the buffers into the GTT. |
3598 | * This is done in 3 phases: | |
3599 | * | |
3600 | * 1a. Unbind all objects that do not match the GTT constraints for | |
3601 | * the execbuffer (fenceable, mappable, alignment etc). | |
3602 | * 1b. Increment pin count for already bound objects. | |
3603 | * 2. Bind new objects. | |
3604 | * 3. Decrement pin count. | |
3605 | * | |
3606 | * This avoid unnecessary unbinding of later objects in order to makr | |
3607 | * room for the earlier objects *unless* we need to defragment. | |
3608 | */ | |
5eac3ab4 CW |
3609 | retry = 0; |
3610 | do { | |
9af90d19 | 3611 | ret = 0; |
a7a09aeb CW |
3612 | |
3613 | /* Unbind any ill-fitting objects or pin. */ | |
9af90d19 | 3614 | for (i = 0; i < count; i++) { |
05394f39 | 3615 | struct drm_i915_gem_object *obj = object_list[i]; |
a7a09aeb CW |
3616 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; |
3617 | bool need_fence, need_mappable; | |
3618 | ||
3619 | if (!obj->gtt_space) | |
3620 | continue; | |
3621 | ||
3622 | need_fence = | |
9af90d19 CW |
3623 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
3624 | obj->tiling_mode != I915_TILING_NONE; | |
a7a09aeb | 3625 | need_mappable = |
16e809ac DV |
3626 | entry->relocation_count ? true : need_fence; |
3627 | ||
a7a09aeb CW |
3628 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || |
3629 | (need_mappable && !obj->map_and_fenceable)) | |
05394f39 | 3630 | ret = i915_gem_object_unbind(obj); |
a7a09aeb CW |
3631 | else |
3632 | ret = i915_gem_object_pin(obj, | |
3633 | entry->alignment, | |
3634 | need_mappable); | |
3635 | if (ret) { | |
3636 | count = i; | |
3637 | goto err; | |
3638 | } | |
3639 | } | |
3640 | ||
3641 | /* Bind fresh objects */ | |
3642 | for (i = 0; i < count; i++) { | |
3643 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; | |
3644 | struct drm_i915_gem_object *obj = object_list[i]; | |
3645 | bool need_fence; | |
3646 | ||
3647 | need_fence = | |
3648 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3649 | obj->tiling_mode != I915_TILING_NONE; | |
3650 | ||
3651 | if (!obj->gtt_space) { | |
3652 | bool need_mappable = | |
3653 | entry->relocation_count ? true : need_fence; | |
3654 | ||
3655 | ret = i915_gem_object_pin(obj, | |
3656 | entry->alignment, | |
3657 | need_mappable); | |
9af90d19 CW |
3658 | if (ret) |
3659 | break; | |
3660 | } | |
40a5f0de | 3661 | |
9af90d19 | 3662 | if (need_fence) { |
05394f39 | 3663 | ret = i915_gem_object_get_fence_reg(obj, true); |
a7a09aeb | 3664 | if (ret) |
9af90d19 | 3665 | break; |
40a5f0de | 3666 | |
caea7476 | 3667 | obj->pending_fenced_gpu_access = true; |
9af90d19 | 3668 | } |
40a5f0de | 3669 | |
9af90d19 | 3670 | entry->offset = obj->gtt_offset; |
40a5f0de EA |
3671 | } |
3672 | ||
a7a09aeb CW |
3673 | err: /* Decrement pin count for bound objects */ |
3674 | for (i = 0; i < count; i++) { | |
3675 | struct drm_i915_gem_object *obj = object_list[i]; | |
3676 | if (obj->gtt_space) | |
3677 | i915_gem_object_unpin(obj); | |
3678 | } | |
9af90d19 | 3679 | |
5eac3ab4 | 3680 | if (ret != -ENOSPC || retry > 1) |
9af90d19 CW |
3681 | return ret; |
3682 | ||
5eac3ab4 CW |
3683 | /* First attempt, just clear anything that is purgeable. |
3684 | * Second attempt, clear the entire GTT. | |
3685 | */ | |
3686 | ret = i915_gem_evict_everything(dev, retry == 0); | |
9af90d19 CW |
3687 | if (ret) |
3688 | return ret; | |
40a5f0de | 3689 | |
5eac3ab4 CW |
3690 | retry++; |
3691 | } while (1); | |
40a5f0de EA |
3692 | } |
3693 | ||
bcf50e27 CW |
3694 | static int |
3695 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
3696 | struct drm_file *file, | |
05394f39 | 3697 | struct drm_i915_gem_object **object_list, |
bcf50e27 CW |
3698 | struct drm_i915_gem_exec_object2 *exec_list, |
3699 | int count) | |
3700 | { | |
3701 | struct drm_i915_gem_relocation_entry *reloc; | |
3702 | int i, total, ret; | |
3703 | ||
05394f39 CW |
3704 | for (i = 0; i < count; i++) |
3705 | object_list[i]->in_execbuffer = false; | |
bcf50e27 CW |
3706 | |
3707 | mutex_unlock(&dev->struct_mutex); | |
3708 | ||
3709 | total = 0; | |
3710 | for (i = 0; i < count; i++) | |
3711 | total += exec_list[i].relocation_count; | |
3712 | ||
3713 | reloc = drm_malloc_ab(total, sizeof(*reloc)); | |
3714 | if (reloc == NULL) { | |
3715 | mutex_lock(&dev->struct_mutex); | |
3716 | return -ENOMEM; | |
3717 | } | |
3718 | ||
3719 | total = 0; | |
3720 | for (i = 0; i < count; i++) { | |
3721 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3722 | ||
3723 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3724 | ||
3725 | if (copy_from_user(reloc+total, user_relocs, | |
3726 | exec_list[i].relocation_count * | |
3727 | sizeof(*reloc))) { | |
3728 | ret = -EFAULT; | |
3729 | mutex_lock(&dev->struct_mutex); | |
3730 | goto err; | |
3731 | } | |
3732 | ||
3733 | total += exec_list[i].relocation_count; | |
3734 | } | |
3735 | ||
3736 | ret = i915_mutex_lock_interruptible(dev); | |
3737 | if (ret) { | |
3738 | mutex_lock(&dev->struct_mutex); | |
3739 | goto err; | |
3740 | } | |
3741 | ||
3742 | ret = i915_gem_execbuffer_reserve(dev, file, | |
3743 | object_list, exec_list, | |
3744 | count); | |
3745 | if (ret) | |
3746 | goto err; | |
3747 | ||
3748 | total = 0; | |
3749 | for (i = 0; i < count; i++) { | |
05394f39 | 3750 | struct drm_i915_gem_object *obj = object_list[i]; |
bcf50e27 CW |
3751 | obj->base.pending_read_domains = 0; |
3752 | obj->base.pending_write_domain = 0; | |
3753 | ret = i915_gem_execbuffer_relocate_object_slow(obj, file, | |
3754 | &exec_list[i], | |
3755 | reloc + total); | |
3756 | if (ret) | |
3757 | goto err; | |
3758 | ||
3759 | total += exec_list[i].relocation_count; | |
3760 | } | |
3761 | ||
3762 | /* Leave the user relocations as are, this is the painfully slow path, | |
3763 | * and we want to avoid the complication of dropping the lock whilst | |
3764 | * having buffers reserved in the aperture and so causing spurious | |
3765 | * ENOSPC for random operations. | |
3766 | */ | |
3767 | ||
3768 | err: | |
3769 | drm_free_large(reloc); | |
3770 | return ret; | |
3771 | } | |
3772 | ||
13b29289 CW |
3773 | static int |
3774 | i915_gem_execbuffer_move_to_gpu(struct drm_device *dev, | |
3775 | struct drm_file *file, | |
3776 | struct intel_ring_buffer *ring, | |
05394f39 | 3777 | struct drm_i915_gem_object **objects, |
13b29289 CW |
3778 | int count) |
3779 | { | |
0f8c6d7c | 3780 | struct change_domains cd; |
13b29289 CW |
3781 | int ret, i; |
3782 | ||
0f8c6d7c CW |
3783 | cd.invalidate_domains = 0; |
3784 | cd.flush_domains = 0; | |
3785 | cd.flush_rings = 0; | |
13b29289 | 3786 | for (i = 0; i < count; i++) |
0f8c6d7c | 3787 | i915_gem_object_set_to_gpu_domain(objects[i], ring, &cd); |
13b29289 | 3788 | |
0f8c6d7c | 3789 | if (cd.invalidate_domains | cd.flush_domains) { |
13b29289 CW |
3790 | #if WATCH_EXEC |
3791 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3792 | __func__, | |
0f8c6d7c CW |
3793 | cd.invalidate_domains, |
3794 | cd.flush_domains); | |
13b29289 | 3795 | #endif |
05394f39 | 3796 | i915_gem_flush(dev, |
0f8c6d7c CW |
3797 | cd.invalidate_domains, |
3798 | cd.flush_domains, | |
3799 | cd.flush_rings); | |
13b29289 CW |
3800 | } |
3801 | ||
3802 | for (i = 0; i < count; i++) { | |
05394f39 | 3803 | struct drm_i915_gem_object *obj = objects[i]; |
13b29289 CW |
3804 | /* XXX replace with semaphores */ |
3805 | if (obj->ring && ring != obj->ring) { | |
05394f39 | 3806 | ret = i915_gem_object_wait_rendering(obj, true); |
13b29289 CW |
3807 | if (ret) |
3808 | return ret; | |
3809 | } | |
3810 | } | |
3811 | ||
3812 | return 0; | |
3813 | } | |
3814 | ||
673a394b EA |
3815 | /* Throttle our rendering by waiting until the ring has completed our requests |
3816 | * emitted over 20 msec ago. | |
3817 | * | |
b962442e EA |
3818 | * Note that if we were to use the current jiffies each time around the loop, |
3819 | * we wouldn't escape the function with any frames outstanding if the time to | |
3820 | * render a frame was over 20ms. | |
3821 | * | |
673a394b EA |
3822 | * This should get us reasonable parallelism between CPU and GPU but also |
3823 | * relatively low latency when blocking on a particular request to finish. | |
3824 | */ | |
40a5f0de | 3825 | static int |
f787a5f5 | 3826 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3827 | { |
f787a5f5 CW |
3828 | struct drm_i915_private *dev_priv = dev->dev_private; |
3829 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3830 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3831 | struct drm_i915_gem_request *request; |
3832 | struct intel_ring_buffer *ring = NULL; | |
3833 | u32 seqno = 0; | |
3834 | int ret; | |
93533c29 | 3835 | |
1c25595f | 3836 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3837 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3838 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3839 | break; | |
40a5f0de | 3840 | |
f787a5f5 CW |
3841 | ring = request->ring; |
3842 | seqno = request->seqno; | |
b962442e | 3843 | } |
1c25595f | 3844 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3845 | |
f787a5f5 CW |
3846 | if (seqno == 0) |
3847 | return 0; | |
2bc43b5c | 3848 | |
f787a5f5 | 3849 | ret = 0; |
78501eac | 3850 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3851 | /* And wait for the seqno passing without holding any locks and |
3852 | * causing extra latency for others. This is safe as the irq | |
3853 | * generation is designed to be run atomically and so is | |
3854 | * lockless. | |
3855 | */ | |
78501eac | 3856 | ring->user_irq_get(ring); |
f787a5f5 | 3857 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 3858 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
f787a5f5 | 3859 | || atomic_read(&dev_priv->mm.wedged)); |
78501eac | 3860 | ring->user_irq_put(ring); |
40a5f0de | 3861 | |
f787a5f5 CW |
3862 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3863 | ret = -EIO; | |
40a5f0de EA |
3864 | } |
3865 | ||
f787a5f5 CW |
3866 | if (ret == 0) |
3867 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3868 | |
3869 | return ret; | |
3870 | } | |
3871 | ||
83d60795 | 3872 | static int |
2549d6c2 CW |
3873 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
3874 | uint64_t exec_offset) | |
83d60795 CW |
3875 | { |
3876 | uint32_t exec_start, exec_len; | |
3877 | ||
3878 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3879 | exec_len = (uint32_t) exec->batch_len; | |
3880 | ||
3881 | if ((exec_start | exec_len) & 0x7) | |
3882 | return -EINVAL; | |
3883 | ||
3884 | if (!exec_start) | |
3885 | return -EINVAL; | |
3886 | ||
3887 | return 0; | |
3888 | } | |
3889 | ||
6b95a207 | 3890 | static int |
2549d6c2 CW |
3891 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
3892 | int count) | |
6b95a207 | 3893 | { |
2549d6c2 | 3894 | int i; |
6b95a207 | 3895 | |
2549d6c2 CW |
3896 | for (i = 0; i < count; i++) { |
3897 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
d1d78830 | 3898 | int length; /* limited by fault_in_pages_readable() */ |
6b95a207 | 3899 | |
d1d78830 CW |
3900 | /* First check for malicious input causing overflow */ |
3901 | if (exec[i].relocation_count > | |
3902 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) | |
3903 | return -EINVAL; | |
6b95a207 | 3904 | |
d1d78830 CW |
3905 | length = exec[i].relocation_count * |
3906 | sizeof(struct drm_i915_gem_relocation_entry); | |
2549d6c2 CW |
3907 | if (!access_ok(VERIFY_READ, ptr, length)) |
3908 | return -EFAULT; | |
40a5f0de | 3909 | |
b5dc608c CW |
3910 | /* we may also need to update the presumed offsets */ |
3911 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
3912 | return -EFAULT; | |
3913 | ||
2549d6c2 CW |
3914 | if (fault_in_pages_readable(ptr, length)) |
3915 | return -EFAULT; | |
6b95a207 | 3916 | } |
6b95a207 | 3917 | |
83d60795 | 3918 | return 0; |
6b95a207 KH |
3919 | } |
3920 | ||
8dc5d147 | 3921 | static int |
76446cac | 3922 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
9af90d19 | 3923 | struct drm_file *file, |
76446cac JB |
3924 | struct drm_i915_gem_execbuffer2 *args, |
3925 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3926 | { |
3927 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 CW |
3928 | struct drm_i915_gem_object **object_list = NULL; |
3929 | struct drm_i915_gem_object *batch_obj; | |
201361a5 | 3930 | struct drm_clip_rect *cliprects = NULL; |
8dc5d147 | 3931 | struct drm_i915_gem_request *request = NULL; |
9af90d19 | 3932 | int ret, i, flips; |
673a394b | 3933 | uint64_t exec_offset; |
673a394b | 3934 | |
852835f3 ZN |
3935 | struct intel_ring_buffer *ring = NULL; |
3936 | ||
30dbf0c0 CW |
3937 | ret = i915_gem_check_is_wedged(dev); |
3938 | if (ret) | |
3939 | return ret; | |
3940 | ||
2549d6c2 CW |
3941 | ret = validate_exec_list(exec_list, args->buffer_count); |
3942 | if (ret) | |
3943 | return ret; | |
3944 | ||
673a394b EA |
3945 | #if WATCH_EXEC |
3946 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3947 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3948 | #endif | |
549f7365 CW |
3949 | switch (args->flags & I915_EXEC_RING_MASK) { |
3950 | case I915_EXEC_DEFAULT: | |
3951 | case I915_EXEC_RENDER: | |
3952 | ring = &dev_priv->render_ring; | |
3953 | break; | |
3954 | case I915_EXEC_BSD: | |
d1b851fc | 3955 | if (!HAS_BSD(dev)) { |
549f7365 | 3956 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
d1b851fc ZN |
3957 | return -EINVAL; |
3958 | } | |
3959 | ring = &dev_priv->bsd_ring; | |
549f7365 CW |
3960 | break; |
3961 | case I915_EXEC_BLT: | |
3962 | if (!HAS_BLT(dev)) { | |
3963 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); | |
3964 | return -EINVAL; | |
3965 | } | |
3966 | ring = &dev_priv->blt_ring; | |
3967 | break; | |
3968 | default: | |
3969 | DRM_ERROR("execbuf with unknown ring: %d\n", | |
3970 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
3971 | return -EINVAL; | |
d1b851fc ZN |
3972 | } |
3973 | ||
4f481ed2 EA |
3974 | if (args->buffer_count < 1) { |
3975 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3976 | return -EINVAL; | |
3977 | } | |
c8e0f93a | 3978 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3979 | if (object_list == NULL) { |
3980 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3981 | args->buffer_count); |
3982 | ret = -ENOMEM; | |
3983 | goto pre_mutex_err; | |
3984 | } | |
673a394b | 3985 | |
201361a5 | 3986 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3987 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3988 | GFP_KERNEL); | |
a40e8d31 OA |
3989 | if (cliprects == NULL) { |
3990 | ret = -ENOMEM; | |
201361a5 | 3991 | goto pre_mutex_err; |
a40e8d31 | 3992 | } |
201361a5 EA |
3993 | |
3994 | ret = copy_from_user(cliprects, | |
3995 | (struct drm_clip_rect __user *) | |
3996 | (uintptr_t) args->cliprects_ptr, | |
3997 | sizeof(*cliprects) * args->num_cliprects); | |
3998 | if (ret != 0) { | |
3999 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
4000 | args->num_cliprects, ret); | |
c877cdce | 4001 | ret = -EFAULT; |
201361a5 EA |
4002 | goto pre_mutex_err; |
4003 | } | |
4004 | } | |
4005 | ||
8dc5d147 CW |
4006 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
4007 | if (request == NULL) { | |
4008 | ret = -ENOMEM; | |
40a5f0de | 4009 | goto pre_mutex_err; |
8dc5d147 | 4010 | } |
40a5f0de | 4011 | |
76c1dec1 CW |
4012 | ret = i915_mutex_lock_interruptible(dev); |
4013 | if (ret) | |
a198bc80 | 4014 | goto pre_mutex_err; |
673a394b EA |
4015 | |
4016 | if (dev_priv->mm.suspended) { | |
673a394b | 4017 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
4018 | ret = -EBUSY; |
4019 | goto pre_mutex_err; | |
673a394b EA |
4020 | } |
4021 | ||
ac94a962 | 4022 | /* Look up object handles */ |
673a394b | 4023 | for (i = 0; i < args->buffer_count; i++) { |
05394f39 | 4024 | struct drm_i915_gem_object *obj; |
7e318e18 | 4025 | |
05394f39 CW |
4026 | obj = to_intel_bo (drm_gem_object_lookup(dev, file, |
4027 | exec_list[i].handle)); | |
4028 | if (obj == NULL) { | |
673a394b EA |
4029 | DRM_ERROR("Invalid object handle %d at index %d\n", |
4030 | exec_list[i].handle, i); | |
0ce907f8 | 4031 | /* prevent error path from reading uninitialized data */ |
05394f39 | 4032 | args->buffer_count = i; |
bf79cb91 | 4033 | ret = -ENOENT; |
673a394b EA |
4034 | goto err; |
4035 | } | |
05394f39 | 4036 | object_list[i] = obj; |
b70d11da | 4037 | |
05394f39 | 4038 | if (obj->in_execbuffer) { |
b70d11da | 4039 | DRM_ERROR("Object %p appears more than once in object list\n", |
05394f39 | 4040 | obj); |
0ce907f8 CW |
4041 | /* prevent error path from reading uninitialized data */ |
4042 | args->buffer_count = i + 1; | |
bf79cb91 | 4043 | ret = -EINVAL; |
b70d11da KH |
4044 | goto err; |
4045 | } | |
05394f39 | 4046 | obj->in_execbuffer = true; |
caea7476 | 4047 | obj->pending_fenced_gpu_access = false; |
ac94a962 | 4048 | } |
673a394b | 4049 | |
9af90d19 | 4050 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
bcf50e27 CW |
4051 | ret = i915_gem_execbuffer_reserve(dev, file, |
4052 | object_list, exec_list, | |
4053 | args->buffer_count); | |
9af90d19 CW |
4054 | if (ret) |
4055 | goto err; | |
ac94a962 | 4056 | |
9af90d19 | 4057 | /* The objects are in their final locations, apply the relocations. */ |
bcf50e27 CW |
4058 | ret = i915_gem_execbuffer_relocate(dev, file, |
4059 | object_list, exec_list, | |
4060 | args->buffer_count); | |
4061 | if (ret) { | |
4062 | if (ret == -EFAULT) { | |
4063 | ret = i915_gem_execbuffer_relocate_slow(dev, file, | |
4064 | object_list, | |
4065 | exec_list, | |
4066 | args->buffer_count); | |
4067 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
4068 | } | |
9af90d19 | 4069 | if (ret) |
ac94a962 | 4070 | goto err; |
673a394b EA |
4071 | } |
4072 | ||
4073 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
4074 | batch_obj = object_list[args->buffer_count-1]; | |
05394f39 | 4075 | if (batch_obj->base.pending_write_domain) { |
5f26a2c7 CW |
4076 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); |
4077 | ret = -EINVAL; | |
4078 | goto err; | |
4079 | } | |
05394f39 | 4080 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
673a394b | 4081 | |
9af90d19 | 4082 | /* Sanity check the batch buffer */ |
05394f39 | 4083 | exec_offset = batch_obj->gtt_offset; |
9af90d19 | 4084 | ret = i915_gem_check_execbuffer(args, exec_offset); |
83d60795 CW |
4085 | if (ret != 0) { |
4086 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
4087 | goto err; | |
4088 | } | |
4089 | ||
13b29289 CW |
4090 | ret = i915_gem_execbuffer_move_to_gpu(dev, file, ring, |
4091 | object_list, args->buffer_count); | |
4092 | if (ret) | |
4093 | goto err; | |
673a394b | 4094 | |
673a394b EA |
4095 | #if WATCH_COHERENCY |
4096 | for (i = 0; i < args->buffer_count; i++) { | |
4097 | i915_gem_object_check_coherency(object_list[i], | |
4098 | exec_list[i].handle); | |
4099 | } | |
4100 | #endif | |
4101 | ||
673a394b | 4102 | #if WATCH_EXEC |
6911a9b8 | 4103 | i915_gem_dump_object(batch_obj, |
673a394b EA |
4104 | args->batch_len, |
4105 | __func__, | |
4106 | ~0); | |
4107 | #endif | |
4108 | ||
e59f2bac CW |
4109 | /* Check for any pending flips. As we only maintain a flip queue depth |
4110 | * of 1, we can simply insert a WAIT for the next display flip prior | |
4111 | * to executing the batch and avoid stalling the CPU. | |
4112 | */ | |
4113 | flips = 0; | |
4114 | for (i = 0; i < args->buffer_count; i++) { | |
05394f39 CW |
4115 | if (object_list[i]->base.write_domain) |
4116 | flips |= atomic_read(&object_list[i]->pending_flip); | |
e59f2bac CW |
4117 | } |
4118 | if (flips) { | |
4119 | int plane, flip_mask; | |
4120 | ||
4121 | for (plane = 0; flips >> plane; plane++) { | |
4122 | if (((flips >> plane) & 1) == 0) | |
4123 | continue; | |
4124 | ||
4125 | if (plane) | |
4126 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
4127 | else | |
4128 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
4129 | ||
e1f99ce6 CW |
4130 | ret = intel_ring_begin(ring, 2); |
4131 | if (ret) | |
4132 | goto err; | |
4133 | ||
78501eac CW |
4134 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
4135 | intel_ring_emit(ring, MI_NOOP); | |
4136 | intel_ring_advance(ring); | |
e59f2bac CW |
4137 | } |
4138 | } | |
4139 | ||
673a394b | 4140 | /* Exec the batchbuffer */ |
78501eac | 4141 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
673a394b EA |
4142 | if (ret) { |
4143 | DRM_ERROR("dispatch failed %d\n", ret); | |
4144 | goto err; | |
4145 | } | |
4146 | ||
673a394b | 4147 | for (i = 0; i < args->buffer_count; i++) { |
05394f39 | 4148 | struct drm_i915_gem_object *obj = object_list[i]; |
673a394b | 4149 | |
05394f39 CW |
4150 | obj->base.read_domains = obj->base.pending_read_domains; |
4151 | obj->base.write_domain = obj->base.pending_write_domain; | |
caea7476 | 4152 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
7e318e18 | 4153 | |
617dbe27 | 4154 | i915_gem_object_move_to_active(obj, ring); |
05394f39 CW |
4155 | if (obj->base.write_domain) { |
4156 | obj->dirty = 1; | |
4157 | list_move_tail(&obj->gpu_write_list, | |
64193406 | 4158 | &ring->gpu_write_list); |
7e318e18 CW |
4159 | intel_mark_busy(dev, obj); |
4160 | } | |
4161 | ||
4162 | trace_i915_gem_object_change_domain(obj, | |
05394f39 CW |
4163 | obj->base.read_domains, |
4164 | obj->base.write_domain); | |
673a394b | 4165 | } |
673a394b | 4166 | |
7e318e18 CW |
4167 | /* |
4168 | * Ensure that the commands in the batch buffer are | |
4169 | * finished before the interrupt fires | |
4170 | */ | |
4171 | i915_retire_commands(dev, ring); | |
4172 | ||
3cce469c | 4173 | if (i915_add_request(dev, file, request, ring)) |
5d97eb69 | 4174 | i915_gem_next_request_seqno(dev, ring); |
3cce469c CW |
4175 | else |
4176 | request = NULL; | |
673a394b | 4177 | |
673a394b | 4178 | err: |
b70d11da | 4179 | for (i = 0; i < args->buffer_count; i++) { |
05394f39 CW |
4180 | object_list[i]->in_execbuffer = false; |
4181 | drm_gem_object_unreference(&object_list[i]->base); | |
b70d11da | 4182 | } |
673a394b | 4183 | |
673a394b EA |
4184 | mutex_unlock(&dev->struct_mutex); |
4185 | ||
93533c29 | 4186 | pre_mutex_err: |
8e7d2b2c | 4187 | drm_free_large(object_list); |
9a298b2a | 4188 | kfree(cliprects); |
8dc5d147 | 4189 | kfree(request); |
673a394b EA |
4190 | |
4191 | return ret; | |
4192 | } | |
4193 | ||
76446cac JB |
4194 | /* |
4195 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
4196 | * list array and passes it to the real function. | |
4197 | */ | |
4198 | int | |
4199 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
05394f39 | 4200 | struct drm_file *file) |
76446cac JB |
4201 | { |
4202 | struct drm_i915_gem_execbuffer *args = data; | |
4203 | struct drm_i915_gem_execbuffer2 exec2; | |
4204 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
4205 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4206 | int ret, i; | |
4207 | ||
4208 | #if WATCH_EXEC | |
4209 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4210 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4211 | #endif | |
4212 | ||
4213 | if (args->buffer_count < 1) { | |
4214 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
4215 | return -EINVAL; | |
4216 | } | |
4217 | ||
4218 | /* Copy in the exec list from userland */ | |
4219 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
4220 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4221 | if (exec_list == NULL || exec2_list == NULL) { | |
4222 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4223 | args->buffer_count); | |
4224 | drm_free_large(exec_list); | |
4225 | drm_free_large(exec2_list); | |
4226 | return -ENOMEM; | |
4227 | } | |
4228 | ret = copy_from_user(exec_list, | |
4229 | (struct drm_i915_relocation_entry __user *) | |
4230 | (uintptr_t) args->buffers_ptr, | |
4231 | sizeof(*exec_list) * args->buffer_count); | |
4232 | if (ret != 0) { | |
4233 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4234 | args->buffer_count, ret); | |
4235 | drm_free_large(exec_list); | |
4236 | drm_free_large(exec2_list); | |
4237 | return -EFAULT; | |
4238 | } | |
4239 | ||
4240 | for (i = 0; i < args->buffer_count; i++) { | |
4241 | exec2_list[i].handle = exec_list[i].handle; | |
4242 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
4243 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
4244 | exec2_list[i].alignment = exec_list[i].alignment; | |
4245 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 4246 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
4247 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
4248 | else | |
4249 | exec2_list[i].flags = 0; | |
4250 | } | |
4251 | ||
4252 | exec2.buffers_ptr = args->buffers_ptr; | |
4253 | exec2.buffer_count = args->buffer_count; | |
4254 | exec2.batch_start_offset = args->batch_start_offset; | |
4255 | exec2.batch_len = args->batch_len; | |
4256 | exec2.DR1 = args->DR1; | |
4257 | exec2.DR4 = args->DR4; | |
4258 | exec2.num_cliprects = args->num_cliprects; | |
4259 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 4260 | exec2.flags = I915_EXEC_RENDER; |
76446cac | 4261 | |
05394f39 | 4262 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
76446cac JB |
4263 | if (!ret) { |
4264 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4265 | for (i = 0; i < args->buffer_count; i++) | |
4266 | exec_list[i].offset = exec2_list[i].offset; | |
4267 | /* ... and back out to userspace */ | |
4268 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4269 | (uintptr_t) args->buffers_ptr, | |
4270 | exec_list, | |
4271 | sizeof(*exec_list) * args->buffer_count); | |
4272 | if (ret) { | |
4273 | ret = -EFAULT; | |
4274 | DRM_ERROR("failed to copy %d exec entries " | |
4275 | "back to user (%d)\n", | |
4276 | args->buffer_count, ret); | |
4277 | } | |
76446cac JB |
4278 | } |
4279 | ||
4280 | drm_free_large(exec_list); | |
4281 | drm_free_large(exec2_list); | |
4282 | return ret; | |
4283 | } | |
4284 | ||
4285 | int | |
4286 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
05394f39 | 4287 | struct drm_file *file) |
76446cac JB |
4288 | { |
4289 | struct drm_i915_gem_execbuffer2 *args = data; | |
4290 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4291 | int ret; | |
4292 | ||
4293 | #if WATCH_EXEC | |
4294 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4295 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4296 | #endif | |
4297 | ||
4298 | if (args->buffer_count < 1) { | |
4299 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4300 | return -EINVAL; | |
4301 | } | |
4302 | ||
4303 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4304 | if (exec2_list == NULL) { | |
4305 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4306 | args->buffer_count); | |
4307 | return -ENOMEM; | |
4308 | } | |
4309 | ret = copy_from_user(exec2_list, | |
4310 | (struct drm_i915_relocation_entry __user *) | |
4311 | (uintptr_t) args->buffers_ptr, | |
4312 | sizeof(*exec2_list) * args->buffer_count); | |
4313 | if (ret != 0) { | |
4314 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4315 | args->buffer_count, ret); | |
4316 | drm_free_large(exec2_list); | |
4317 | return -EFAULT; | |
4318 | } | |
4319 | ||
05394f39 | 4320 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
76446cac JB |
4321 | if (!ret) { |
4322 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4323 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4324 | (uintptr_t) args->buffers_ptr, | |
4325 | exec2_list, | |
4326 | sizeof(*exec2_list) * args->buffer_count); | |
4327 | if (ret) { | |
4328 | ret = -EFAULT; | |
4329 | DRM_ERROR("failed to copy %d exec entries " | |
4330 | "back to user (%d)\n", | |
4331 | args->buffer_count, ret); | |
4332 | } | |
4333 | } | |
4334 | ||
4335 | drm_free_large(exec2_list); | |
4336 | return ret; | |
4337 | } | |
4338 | ||
673a394b | 4339 | int |
05394f39 CW |
4340 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
4341 | uint32_t alignment, | |
75e9e915 | 4342 | bool map_and_fenceable) |
673a394b | 4343 | { |
05394f39 | 4344 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 4345 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
4346 | int ret; |
4347 | ||
05394f39 | 4348 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 4349 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 4350 | |
05394f39 CW |
4351 | if (obj->gtt_space != NULL) { |
4352 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
4353 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
4354 | WARN(obj->pin_count, | |
ae7d49d8 | 4355 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
4356 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
4357 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 4358 | obj->gtt_offset, alignment, |
75e9e915 | 4359 | map_and_fenceable, |
05394f39 | 4360 | obj->map_and_fenceable); |
ac0c6b5a CW |
4361 | ret = i915_gem_object_unbind(obj); |
4362 | if (ret) | |
4363 | return ret; | |
4364 | } | |
4365 | } | |
4366 | ||
05394f39 | 4367 | if (obj->gtt_space == NULL) { |
a00b10c3 | 4368 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 4369 | map_and_fenceable); |
9731129c | 4370 | if (ret) |
673a394b | 4371 | return ret; |
22c344e9 | 4372 | } |
76446cac | 4373 | |
05394f39 CW |
4374 | if (obj->pin_count++ == 0) { |
4375 | i915_gem_info_add_pin(dev_priv, obj, map_and_fenceable); | |
4376 | if (!obj->active) | |
4377 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 4378 | &dev_priv->mm.pinned_list); |
673a394b | 4379 | } |
05394f39 | 4380 | BUG_ON(!obj->pin_mappable && map_and_fenceable); |
673a394b | 4381 | |
23bc5982 | 4382 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4383 | return 0; |
4384 | } | |
4385 | ||
4386 | void | |
05394f39 | 4387 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 4388 | { |
05394f39 | 4389 | struct drm_device *dev = obj->base.dev; |
673a394b | 4390 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 4391 | |
23bc5982 | 4392 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
4393 | BUG_ON(obj->pin_count == 0); |
4394 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 4395 | |
05394f39 CW |
4396 | if (--obj->pin_count == 0) { |
4397 | if (!obj->active) | |
4398 | list_move_tail(&obj->mm_list, | |
673a394b | 4399 | &dev_priv->mm.inactive_list); |
05394f39 | 4400 | i915_gem_info_remove_pin(dev_priv, obj); |
673a394b | 4401 | } |
23bc5982 | 4402 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4403 | } |
4404 | ||
4405 | int | |
4406 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4407 | struct drm_file *file) |
673a394b EA |
4408 | { |
4409 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4410 | struct drm_i915_gem_object *obj; |
673a394b EA |
4411 | int ret; |
4412 | ||
1d7cfea1 CW |
4413 | ret = i915_mutex_lock_interruptible(dev); |
4414 | if (ret) | |
4415 | return ret; | |
673a394b | 4416 | |
05394f39 | 4417 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 4418 | if (obj == NULL) { |
1d7cfea1 CW |
4419 | ret = -ENOENT; |
4420 | goto unlock; | |
673a394b | 4421 | } |
673a394b | 4422 | |
05394f39 | 4423 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 4424 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
4425 | ret = -EINVAL; |
4426 | goto out; | |
3ef94daa CW |
4427 | } |
4428 | ||
05394f39 | 4429 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
4430 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
4431 | args->handle); | |
1d7cfea1 CW |
4432 | ret = -EINVAL; |
4433 | goto out; | |
79e53945 JB |
4434 | } |
4435 | ||
05394f39 CW |
4436 | obj->user_pin_count++; |
4437 | obj->pin_filp = file; | |
4438 | if (obj->user_pin_count == 1) { | |
75e9e915 | 4439 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
4440 | if (ret) |
4441 | goto out; | |
673a394b EA |
4442 | } |
4443 | ||
4444 | /* XXX - flush the CPU caches for pinned objects | |
4445 | * as the X server doesn't manage domains yet | |
4446 | */ | |
e47c68e9 | 4447 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 4448 | args->offset = obj->gtt_offset; |
1d7cfea1 | 4449 | out: |
05394f39 | 4450 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4451 | unlock: |
673a394b | 4452 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4453 | return ret; |
673a394b EA |
4454 | } |
4455 | ||
4456 | int | |
4457 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4458 | struct drm_file *file) |
673a394b EA |
4459 | { |
4460 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4461 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4462 | int ret; |
673a394b | 4463 | |
1d7cfea1 CW |
4464 | ret = i915_mutex_lock_interruptible(dev); |
4465 | if (ret) | |
4466 | return ret; | |
673a394b | 4467 | |
05394f39 | 4468 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 4469 | if (obj == NULL) { |
1d7cfea1 CW |
4470 | ret = -ENOENT; |
4471 | goto unlock; | |
673a394b | 4472 | } |
76c1dec1 | 4473 | |
05394f39 | 4474 | if (obj->pin_filp != file) { |
79e53945 JB |
4475 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
4476 | args->handle); | |
1d7cfea1 CW |
4477 | ret = -EINVAL; |
4478 | goto out; | |
79e53945 | 4479 | } |
05394f39 CW |
4480 | obj->user_pin_count--; |
4481 | if (obj->user_pin_count == 0) { | |
4482 | obj->pin_filp = NULL; | |
79e53945 JB |
4483 | i915_gem_object_unpin(obj); |
4484 | } | |
673a394b | 4485 | |
1d7cfea1 | 4486 | out: |
05394f39 | 4487 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4488 | unlock: |
673a394b | 4489 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4490 | return ret; |
673a394b EA |
4491 | } |
4492 | ||
4493 | int | |
4494 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4495 | struct drm_file *file) |
673a394b EA |
4496 | { |
4497 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4498 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4499 | int ret; |
4500 | ||
76c1dec1 | 4501 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4502 | if (ret) |
76c1dec1 | 4503 | return ret; |
673a394b | 4504 | |
05394f39 | 4505 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 4506 | if (obj == NULL) { |
1d7cfea1 CW |
4507 | ret = -ENOENT; |
4508 | goto unlock; | |
673a394b | 4509 | } |
d1b851fc | 4510 | |
0be555b6 CW |
4511 | /* Count all active objects as busy, even if they are currently not used |
4512 | * by the gpu. Users of this interface expect objects to eventually | |
4513 | * become non-busy without any further actions, therefore emit any | |
4514 | * necessary flushes here. | |
c4de0a5d | 4515 | */ |
05394f39 | 4516 | args->busy = obj->active; |
0be555b6 CW |
4517 | if (args->busy) { |
4518 | /* Unconditionally flush objects, even when the gpu still uses this | |
4519 | * object. Userspace calling this function indicates that it wants to | |
4520 | * use this buffer rather sooner than later, so issuing the required | |
4521 | * flush earlier is beneficial. | |
4522 | */ | |
05394f39 CW |
4523 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) |
4524 | i915_gem_flush_ring(dev, obj->ring, | |
4525 | 0, obj->base.write_domain); | |
0be555b6 CW |
4526 | |
4527 | /* Update the active list for the hardware's current position. | |
4528 | * Otherwise this only updates on a delayed timer or when irqs | |
4529 | * are actually unmasked, and our working set ends up being | |
4530 | * larger than required. | |
4531 | */ | |
05394f39 | 4532 | i915_gem_retire_requests_ring(dev, obj->ring); |
0be555b6 | 4533 | |
05394f39 | 4534 | args->busy = obj->active; |
0be555b6 | 4535 | } |
673a394b | 4536 | |
05394f39 | 4537 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4538 | unlock: |
673a394b | 4539 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4540 | return ret; |
673a394b EA |
4541 | } |
4542 | ||
4543 | int | |
4544 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4545 | struct drm_file *file_priv) | |
4546 | { | |
4547 | return i915_gem_ring_throttle(dev, file_priv); | |
4548 | } | |
4549 | ||
3ef94daa CW |
4550 | int |
4551 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4552 | struct drm_file *file_priv) | |
4553 | { | |
4554 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 4555 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4556 | int ret; |
3ef94daa CW |
4557 | |
4558 | switch (args->madv) { | |
4559 | case I915_MADV_DONTNEED: | |
4560 | case I915_MADV_WILLNEED: | |
4561 | break; | |
4562 | default: | |
4563 | return -EINVAL; | |
4564 | } | |
4565 | ||
1d7cfea1 CW |
4566 | ret = i915_mutex_lock_interruptible(dev); |
4567 | if (ret) | |
4568 | return ret; | |
4569 | ||
05394f39 | 4570 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
3ef94daa | 4571 | if (obj == NULL) { |
1d7cfea1 CW |
4572 | ret = -ENOENT; |
4573 | goto unlock; | |
3ef94daa | 4574 | } |
3ef94daa | 4575 | |
05394f39 | 4576 | if (obj->pin_count) { |
1d7cfea1 CW |
4577 | ret = -EINVAL; |
4578 | goto out; | |
3ef94daa CW |
4579 | } |
4580 | ||
05394f39 CW |
4581 | if (obj->madv != __I915_MADV_PURGED) |
4582 | obj->madv = args->madv; | |
3ef94daa | 4583 | |
2d7ef395 | 4584 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
4585 | if (i915_gem_object_is_purgeable(obj) && |
4586 | obj->gtt_space == NULL) | |
2d7ef395 CW |
4587 | i915_gem_object_truncate(obj); |
4588 | ||
05394f39 | 4589 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4590 | |
1d7cfea1 | 4591 | out: |
05394f39 | 4592 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4593 | unlock: |
3ef94daa | 4594 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4595 | return ret; |
3ef94daa CW |
4596 | } |
4597 | ||
05394f39 CW |
4598 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4599 | size_t size) | |
ac52bc56 | 4600 | { |
73aa808f | 4601 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 4602 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4603 | |
c397b908 DV |
4604 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4605 | if (obj == NULL) | |
4606 | return NULL; | |
673a394b | 4607 | |
c397b908 DV |
4608 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4609 | kfree(obj); | |
4610 | return NULL; | |
4611 | } | |
673a394b | 4612 | |
73aa808f CW |
4613 | i915_gem_info_add_obj(dev_priv, size); |
4614 | ||
c397b908 DV |
4615 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4616 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4617 | |
c397b908 | 4618 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4619 | obj->base.driver_private = NULL; |
c397b908 | 4620 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 4621 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 4622 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 4623 | INIT_LIST_HEAD(&obj->ring_list); |
c397b908 | 4624 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 4625 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
4626 | /* Avoid an unnecessary call to unbind on the first bind. */ |
4627 | obj->map_and_fenceable = true; | |
de151cf6 | 4628 | |
05394f39 | 4629 | return obj; |
c397b908 DV |
4630 | } |
4631 | ||
4632 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4633 | { | |
4634 | BUG(); | |
de151cf6 | 4635 | |
673a394b EA |
4636 | return 0; |
4637 | } | |
4638 | ||
05394f39 | 4639 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 4640 | { |
05394f39 | 4641 | struct drm_device *dev = obj->base.dev; |
be72615b | 4642 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 4643 | int ret; |
673a394b | 4644 | |
be72615b CW |
4645 | ret = i915_gem_object_unbind(obj); |
4646 | if (ret == -ERESTARTSYS) { | |
05394f39 | 4647 | list_move(&obj->mm_list, |
be72615b CW |
4648 | &dev_priv->mm.deferred_free_list); |
4649 | return; | |
4650 | } | |
673a394b | 4651 | |
05394f39 | 4652 | if (obj->base.map_list.map) |
7e616158 | 4653 | i915_gem_free_mmap_offset(obj); |
de151cf6 | 4654 | |
05394f39 CW |
4655 | drm_gem_object_release(&obj->base); |
4656 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4657 | |
05394f39 CW |
4658 | kfree(obj->page_cpu_valid); |
4659 | kfree(obj->bit_17); | |
4660 | kfree(obj); | |
673a394b EA |
4661 | } |
4662 | ||
05394f39 | 4663 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 4664 | { |
05394f39 CW |
4665 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
4666 | struct drm_device *dev = obj->base.dev; | |
be72615b CW |
4667 | |
4668 | trace_i915_gem_object_destroy(obj); | |
4669 | ||
05394f39 | 4670 | while (obj->pin_count > 0) |
be72615b CW |
4671 | i915_gem_object_unpin(obj); |
4672 | ||
05394f39 | 4673 | if (obj->phys_obj) |
be72615b CW |
4674 | i915_gem_detach_phys_object(dev, obj); |
4675 | ||
4676 | i915_gem_free_object_tail(obj); | |
4677 | } | |
4678 | ||
29105ccc CW |
4679 | int |
4680 | i915_gem_idle(struct drm_device *dev) | |
4681 | { | |
4682 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4683 | int ret; | |
28dfe52a | 4684 | |
29105ccc | 4685 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4686 | |
87acb0a5 | 4687 | if (dev_priv->mm.suspended) { |
29105ccc CW |
4688 | mutex_unlock(&dev->struct_mutex); |
4689 | return 0; | |
28dfe52a EA |
4690 | } |
4691 | ||
29105ccc | 4692 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4693 | if (ret) { |
4694 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4695 | return ret; |
6dbe2772 | 4696 | } |
673a394b | 4697 | |
29105ccc CW |
4698 | /* Under UMS, be paranoid and evict. */ |
4699 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 4700 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
4701 | if (ret) { |
4702 | mutex_unlock(&dev->struct_mutex); | |
4703 | return ret; | |
4704 | } | |
4705 | } | |
4706 | ||
312817a3 CW |
4707 | i915_gem_reset_fences(dev); |
4708 | ||
29105ccc CW |
4709 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4710 | * We need to replace this with a semaphore, or something. | |
4711 | * And not confound mm.suspended! | |
4712 | */ | |
4713 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4714 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4715 | |
4716 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4717 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4718 | |
6dbe2772 KP |
4719 | mutex_unlock(&dev->struct_mutex); |
4720 | ||
29105ccc CW |
4721 | /* Cancel the retire work handler, which should be idle now. */ |
4722 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4723 | ||
673a394b EA |
4724 | return 0; |
4725 | } | |
4726 | ||
8187a2b7 ZN |
4727 | int |
4728 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4729 | { | |
4730 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4731 | int ret; | |
68f95ba9 | 4732 | |
5c1143bb | 4733 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4734 | if (ret) |
b6913e4b | 4735 | return ret; |
68f95ba9 CW |
4736 | |
4737 | if (HAS_BSD(dev)) { | |
5c1143bb | 4738 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4739 | if (ret) |
4740 | goto cleanup_render_ring; | |
d1b851fc | 4741 | } |
68f95ba9 | 4742 | |
549f7365 CW |
4743 | if (HAS_BLT(dev)) { |
4744 | ret = intel_init_blt_ring_buffer(dev); | |
4745 | if (ret) | |
4746 | goto cleanup_bsd_ring; | |
4747 | } | |
4748 | ||
6f392d54 CW |
4749 | dev_priv->next_seqno = 1; |
4750 | ||
68f95ba9 CW |
4751 | return 0; |
4752 | ||
549f7365 | 4753 | cleanup_bsd_ring: |
78501eac | 4754 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
68f95ba9 | 4755 | cleanup_render_ring: |
78501eac | 4756 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
8187a2b7 ZN |
4757 | return ret; |
4758 | } | |
4759 | ||
4760 | void | |
4761 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4762 | { | |
4763 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4764 | ||
78501eac CW |
4765 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
4766 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); | |
4767 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); | |
8187a2b7 ZN |
4768 | } |
4769 | ||
673a394b EA |
4770 | int |
4771 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4772 | struct drm_file *file_priv) | |
4773 | { | |
4774 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4775 | int ret; | |
4776 | ||
79e53945 JB |
4777 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4778 | return 0; | |
4779 | ||
ba1234d1 | 4780 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4781 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4782 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4783 | } |
4784 | ||
673a394b | 4785 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4786 | dev_priv->mm.suspended = 0; |
4787 | ||
4788 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4789 | if (ret != 0) { |
4790 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4791 | return ret; |
d816f6ac | 4792 | } |
9bb2d6f9 | 4793 | |
69dc4987 | 4794 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
852835f3 | 4795 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
87acb0a5 | 4796 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
549f7365 | 4797 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
673a394b EA |
4798 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4799 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4800 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
87acb0a5 | 4801 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
549f7365 | 4802 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
673a394b | 4803 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4804 | |
5f35308b CW |
4805 | ret = drm_irq_install(dev); |
4806 | if (ret) | |
4807 | goto cleanup_ringbuffer; | |
dbb19d30 | 4808 | |
673a394b | 4809 | return 0; |
5f35308b CW |
4810 | |
4811 | cleanup_ringbuffer: | |
4812 | mutex_lock(&dev->struct_mutex); | |
4813 | i915_gem_cleanup_ringbuffer(dev); | |
4814 | dev_priv->mm.suspended = 1; | |
4815 | mutex_unlock(&dev->struct_mutex); | |
4816 | ||
4817 | return ret; | |
673a394b EA |
4818 | } |
4819 | ||
4820 | int | |
4821 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4822 | struct drm_file *file_priv) | |
4823 | { | |
79e53945 JB |
4824 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4825 | return 0; | |
4826 | ||
dbb19d30 | 4827 | drm_irq_uninstall(dev); |
e6890f6f | 4828 | return i915_gem_idle(dev); |
673a394b EA |
4829 | } |
4830 | ||
4831 | void | |
4832 | i915_gem_lastclose(struct drm_device *dev) | |
4833 | { | |
4834 | int ret; | |
673a394b | 4835 | |
e806b495 EA |
4836 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4837 | return; | |
4838 | ||
6dbe2772 KP |
4839 | ret = i915_gem_idle(dev); |
4840 | if (ret) | |
4841 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4842 | } |
4843 | ||
64193406 CW |
4844 | static void |
4845 | init_ring_lists(struct intel_ring_buffer *ring) | |
4846 | { | |
4847 | INIT_LIST_HEAD(&ring->active_list); | |
4848 | INIT_LIST_HEAD(&ring->request_list); | |
4849 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
4850 | } | |
4851 | ||
673a394b EA |
4852 | void |
4853 | i915_gem_load(struct drm_device *dev) | |
4854 | { | |
b5aa8a0f | 4855 | int i; |
673a394b EA |
4856 | drm_i915_private_t *dev_priv = dev->dev_private; |
4857 | ||
69dc4987 | 4858 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
4859 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
4860 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 4861 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4862 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4863 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 4864 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
64193406 CW |
4865 | init_ring_lists(&dev_priv->render_ring); |
4866 | init_ring_lists(&dev_priv->bsd_ring); | |
4867 | init_ring_lists(&dev_priv->blt_ring); | |
007cc8ac DV |
4868 | for (i = 0; i < 16; i++) |
4869 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4870 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4871 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4872 | init_completion(&dev_priv->error_completion); |
31169714 | 4873 | |
94400120 DA |
4874 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4875 | if (IS_GEN3(dev)) { | |
4876 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4877 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4878 | /* arb state is a masked write, so set bit + bit in mask */ | |
4879 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4880 | I915_WRITE(MI_ARB_STATE, tmp); | |
4881 | } | |
4882 | } | |
4883 | ||
de151cf6 | 4884 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4885 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4886 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4887 | |
a6c45cf0 | 4888 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4889 | dev_priv->num_fence_regs = 16; |
4890 | else | |
4891 | dev_priv->num_fence_regs = 8; | |
4892 | ||
b5aa8a0f | 4893 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4894 | switch (INTEL_INFO(dev)->gen) { |
4895 | case 6: | |
4896 | for (i = 0; i < 16; i++) | |
4897 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4898 | break; | |
4899 | case 5: | |
4900 | case 4: | |
b5aa8a0f GH |
4901 | for (i = 0; i < 16; i++) |
4902 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4903 | break; |
4904 | case 3: | |
b5aa8a0f GH |
4905 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4906 | for (i = 0; i < 8; i++) | |
4907 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4908 | case 2: |
4909 | for (i = 0; i < 8; i++) | |
4910 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4911 | break; | |
b5aa8a0f | 4912 | } |
673a394b | 4913 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4914 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 CW |
4915 | |
4916 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; | |
4917 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4918 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4919 | } |
71acb5eb DA |
4920 | |
4921 | /* | |
4922 | * Create a physically contiguous memory object for this object | |
4923 | * e.g. for cursor + overlay regs | |
4924 | */ | |
995b6762 CW |
4925 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4926 | int id, int size, int align) | |
71acb5eb DA |
4927 | { |
4928 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4929 | struct drm_i915_gem_phys_object *phys_obj; | |
4930 | int ret; | |
4931 | ||
4932 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4933 | return 0; | |
4934 | ||
9a298b2a | 4935 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4936 | if (!phys_obj) |
4937 | return -ENOMEM; | |
4938 | ||
4939 | phys_obj->id = id; | |
4940 | ||
6eeefaf3 | 4941 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4942 | if (!phys_obj->handle) { |
4943 | ret = -ENOMEM; | |
4944 | goto kfree_obj; | |
4945 | } | |
4946 | #ifdef CONFIG_X86 | |
4947 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4948 | #endif | |
4949 | ||
4950 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4951 | ||
4952 | return 0; | |
4953 | kfree_obj: | |
9a298b2a | 4954 | kfree(phys_obj); |
71acb5eb DA |
4955 | return ret; |
4956 | } | |
4957 | ||
995b6762 | 4958 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4959 | { |
4960 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4961 | struct drm_i915_gem_phys_object *phys_obj; | |
4962 | ||
4963 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4964 | return; | |
4965 | ||
4966 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4967 | if (phys_obj->cur_obj) { | |
4968 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4969 | } | |
4970 | ||
4971 | #ifdef CONFIG_X86 | |
4972 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4973 | #endif | |
4974 | drm_pci_free(dev, phys_obj->handle); | |
4975 | kfree(phys_obj); | |
4976 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4977 | } | |
4978 | ||
4979 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4980 | { | |
4981 | int i; | |
4982 | ||
260883c8 | 4983 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4984 | i915_gem_free_phys_object(dev, i); |
4985 | } | |
4986 | ||
4987 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4988 | struct drm_i915_gem_object *obj) |
71acb5eb | 4989 | { |
05394f39 | 4990 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4991 | char *vaddr; |
71acb5eb | 4992 | int i; |
71acb5eb DA |
4993 | int page_count; |
4994 | ||
05394f39 | 4995 | if (!obj->phys_obj) |
71acb5eb | 4996 | return; |
05394f39 | 4997 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4998 | |
05394f39 | 4999 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 5000 | for (i = 0; i < page_count; i++) { |
e5281ccd CW |
5001 | struct page *page = read_cache_page_gfp(mapping, i, |
5002 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
5003 | if (!IS_ERR(page)) { | |
5004 | char *dst = kmap_atomic(page); | |
5005 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
5006 | kunmap_atomic(dst); | |
5007 | ||
5008 | drm_clflush_pages(&page, 1); | |
5009 | ||
5010 | set_page_dirty(page); | |
5011 | mark_page_accessed(page); | |
5012 | page_cache_release(page); | |
5013 | } | |
71acb5eb | 5014 | } |
40ce6575 | 5015 | intel_gtt_chipset_flush(); |
d78b47b9 | 5016 | |
05394f39 CW |
5017 | obj->phys_obj->cur_obj = NULL; |
5018 | obj->phys_obj = NULL; | |
71acb5eb DA |
5019 | } |
5020 | ||
5021 | int | |
5022 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 5023 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
5024 | int id, |
5025 | int align) | |
71acb5eb | 5026 | { |
05394f39 | 5027 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 5028 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
5029 | int ret = 0; |
5030 | int page_count; | |
5031 | int i; | |
5032 | ||
5033 | if (id > I915_MAX_PHYS_OBJECT) | |
5034 | return -EINVAL; | |
5035 | ||
05394f39 CW |
5036 | if (obj->phys_obj) { |
5037 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
5038 | return 0; |
5039 | i915_gem_detach_phys_object(dev, obj); | |
5040 | } | |
5041 | ||
71acb5eb DA |
5042 | /* create a new object */ |
5043 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
5044 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 5045 | obj->base.size, align); |
71acb5eb | 5046 | if (ret) { |
05394f39 CW |
5047 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
5048 | id, obj->base.size); | |
e5281ccd | 5049 | return ret; |
71acb5eb DA |
5050 | } |
5051 | } | |
5052 | ||
5053 | /* bind to the object */ | |
05394f39 CW |
5054 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
5055 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 5056 | |
05394f39 | 5057 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
5058 | |
5059 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
5060 | struct page *page; |
5061 | char *dst, *src; | |
5062 | ||
5063 | page = read_cache_page_gfp(mapping, i, | |
5064 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
5065 | if (IS_ERR(page)) | |
5066 | return PTR_ERR(page); | |
71acb5eb | 5067 | |
ff75b9bc | 5068 | src = kmap_atomic(page); |
05394f39 | 5069 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 5070 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 5071 | kunmap_atomic(src); |
71acb5eb | 5072 | |
e5281ccd CW |
5073 | mark_page_accessed(page); |
5074 | page_cache_release(page); | |
5075 | } | |
d78b47b9 | 5076 | |
71acb5eb | 5077 | return 0; |
71acb5eb DA |
5078 | } |
5079 | ||
5080 | static int | |
05394f39 CW |
5081 | i915_gem_phys_pwrite(struct drm_device *dev, |
5082 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
5083 | struct drm_i915_gem_pwrite *args, |
5084 | struct drm_file *file_priv) | |
5085 | { | |
05394f39 | 5086 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 5087 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 5088 | |
b47b30cc CW |
5089 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
5090 | unsigned long unwritten; | |
5091 | ||
5092 | /* The physical object once assigned is fixed for the lifetime | |
5093 | * of the obj, so we can safely drop the lock and continue | |
5094 | * to access vaddr. | |
5095 | */ | |
5096 | mutex_unlock(&dev->struct_mutex); | |
5097 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
5098 | mutex_lock(&dev->struct_mutex); | |
5099 | if (unwritten) | |
5100 | return -EFAULT; | |
5101 | } | |
71acb5eb | 5102 | |
40ce6575 | 5103 | intel_gtt_chipset_flush(); |
71acb5eb DA |
5104 | return 0; |
5105 | } | |
b962442e | 5106 | |
f787a5f5 | 5107 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5108 | { |
f787a5f5 | 5109 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
5110 | |
5111 | /* Clean up our request list when the client is going away, so that | |
5112 | * later retire_requests won't dereference our soon-to-be-gone | |
5113 | * file_priv. | |
5114 | */ | |
1c25595f | 5115 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5116 | while (!list_empty(&file_priv->mm.request_list)) { |
5117 | struct drm_i915_gem_request *request; | |
5118 | ||
5119 | request = list_first_entry(&file_priv->mm.request_list, | |
5120 | struct drm_i915_gem_request, | |
5121 | client_list); | |
5122 | list_del(&request->client_list); | |
5123 | request->file_priv = NULL; | |
5124 | } | |
1c25595f | 5125 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5126 | } |
31169714 | 5127 | |
1637ef41 CW |
5128 | static int |
5129 | i915_gpu_is_active(struct drm_device *dev) | |
5130 | { | |
5131 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5132 | int lists_empty; | |
5133 | ||
1637ef41 | 5134 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 5135 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
5136 | |
5137 | return !lists_empty; | |
5138 | } | |
5139 | ||
31169714 | 5140 | static int |
17250b71 CW |
5141 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
5142 | int nr_to_scan, | |
5143 | gfp_t gfp_mask) | |
31169714 | 5144 | { |
17250b71 CW |
5145 | struct drm_i915_private *dev_priv = |
5146 | container_of(shrinker, | |
5147 | struct drm_i915_private, | |
5148 | mm.inactive_shrinker); | |
5149 | struct drm_device *dev = dev_priv->dev; | |
5150 | struct drm_i915_gem_object *obj, *next; | |
5151 | int cnt; | |
5152 | ||
5153 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 5154 | return 0; |
31169714 CW |
5155 | |
5156 | /* "fast-path" to count number of available objects */ | |
5157 | if (nr_to_scan == 0) { | |
17250b71 CW |
5158 | cnt = 0; |
5159 | list_for_each_entry(obj, | |
5160 | &dev_priv->mm.inactive_list, | |
5161 | mm_list) | |
5162 | cnt++; | |
5163 | mutex_unlock(&dev->struct_mutex); | |
5164 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
5165 | } |
5166 | ||
1637ef41 | 5167 | rescan: |
31169714 | 5168 | /* first scan for clean buffers */ |
17250b71 | 5169 | i915_gem_retire_requests(dev); |
31169714 | 5170 | |
17250b71 CW |
5171 | list_for_each_entry_safe(obj, next, |
5172 | &dev_priv->mm.inactive_list, | |
5173 | mm_list) { | |
5174 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
5175 | if (i915_gem_object_unbind(obj) == 0 && |
5176 | --nr_to_scan == 0) | |
17250b71 | 5177 | break; |
31169714 | 5178 | } |
31169714 CW |
5179 | } |
5180 | ||
5181 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
5182 | cnt = 0; |
5183 | list_for_each_entry_safe(obj, next, | |
5184 | &dev_priv->mm.inactive_list, | |
5185 | mm_list) { | |
2021746e CW |
5186 | if (nr_to_scan && |
5187 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 5188 | nr_to_scan--; |
2021746e | 5189 | else |
17250b71 CW |
5190 | cnt++; |
5191 | } | |
5192 | ||
5193 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
5194 | /* |
5195 | * We are desperate for pages, so as a last resort, wait | |
5196 | * for the GPU to finish and discard whatever we can. | |
5197 | * This has a dramatic impact to reduce the number of | |
5198 | * OOM-killer events whilst running the GPU aggressively. | |
5199 | */ | |
17250b71 | 5200 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
5201 | goto rescan; |
5202 | } | |
17250b71 CW |
5203 | mutex_unlock(&dev->struct_mutex); |
5204 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 5205 | } |