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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
57822dc6 | 32 | #include "i915_gem_clflush.h" |
eb82289a | 33 | #include "i915_vgpu.h" |
1c5d22f7 | 34 | #include "i915_trace.h" |
652c393a | 35 | #include "intel_drv.h" |
5d723d7a | 36 | #include "intel_frontbuffer.h" |
0ccdacf6 | 37 | #include "intel_mocs.h" |
6b5e90f5 | 38 | #include <linux/dma-fence-array.h> |
fe3288b5 | 39 | #include <linux/kthread.h> |
c13d87ea | 40 | #include <linux/reservation.h> |
5949eac4 | 41 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 42 | #include <linux/slab.h> |
20e4933c | 43 | #include <linux/stop_machine.h> |
673a394b | 44 | #include <linux/swap.h> |
79e53945 | 45 | #include <linux/pci.h> |
1286ff73 | 46 | #include <linux/dma-buf.h> |
673a394b | 47 | |
fbbd37b3 | 48 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915); |
61050808 | 49 | |
2c22569b CW |
50 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
51 | { | |
e27ab73d | 52 | if (obj->cache_dirty) |
b50a5371 AS |
53 | return false; |
54 | ||
7fc92e96 | 55 | if (!obj->cache_coherent) |
2c22569b CW |
56 | return true; |
57 | ||
58 | return obj->pin_display; | |
59 | } | |
60 | ||
4f1959ee | 61 | static int |
bb6dc8d9 | 62 | insert_mappable_node(struct i915_ggtt *ggtt, |
4f1959ee AS |
63 | struct drm_mm_node *node, u32 size) |
64 | { | |
65 | memset(node, 0, sizeof(*node)); | |
4e64e553 CW |
66 | return drm_mm_insert_node_in_range(&ggtt->base.mm, node, |
67 | size, 0, I915_COLOR_UNEVICTABLE, | |
68 | 0, ggtt->mappable_end, | |
69 | DRM_MM_INSERT_LOW); | |
4f1959ee AS |
70 | } |
71 | ||
72 | static void | |
73 | remove_mappable_node(struct drm_mm_node *node) | |
74 | { | |
75 | drm_mm_remove_node(node); | |
76 | } | |
77 | ||
73aa808f CW |
78 | /* some bookkeeping */ |
79 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 80 | u64 size) |
73aa808f | 81 | { |
c20e8355 | 82 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
83 | dev_priv->mm.object_count++; |
84 | dev_priv->mm.object_memory += size; | |
c20e8355 | 85 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
86 | } |
87 | ||
88 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 89 | u64 size) |
73aa808f | 90 | { |
c20e8355 | 91 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
92 | dev_priv->mm.object_count--; |
93 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 94 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
95 | } |
96 | ||
21dd3734 | 97 | static int |
33196ded | 98 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 99 | { |
30dbf0c0 CW |
100 | int ret; |
101 | ||
4c7d62c6 CW |
102 | might_sleep(); |
103 | ||
0a6759c6 DV |
104 | /* |
105 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
106 | * userspace. If it takes that long something really bad is going on and | |
107 | * we should simply try to bail out and fail as gracefully as possible. | |
108 | */ | |
1f83fee0 | 109 | ret = wait_event_interruptible_timeout(error->reset_queue, |
8c185eca | 110 | !i915_reset_backoff(error), |
b52992c0 | 111 | I915_RESET_TIMEOUT); |
0a6759c6 DV |
112 | if (ret == 0) { |
113 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
114 | return -EIO; | |
115 | } else if (ret < 0) { | |
30dbf0c0 | 116 | return ret; |
d98c52cf CW |
117 | } else { |
118 | return 0; | |
0a6759c6 | 119 | } |
30dbf0c0 CW |
120 | } |
121 | ||
54cf91dc | 122 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 123 | { |
fac5e23e | 124 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
125 | int ret; |
126 | ||
33196ded | 127 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
128 | if (ret) |
129 | return ret; | |
130 | ||
131 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
132 | if (ret) | |
133 | return ret; | |
134 | ||
76c1dec1 CW |
135 | return 0; |
136 | } | |
30dbf0c0 | 137 | |
5a125c3c EA |
138 | int |
139 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 140 | struct drm_file *file) |
5a125c3c | 141 | { |
72e96d64 | 142 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 143 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 144 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 145 | struct i915_vma *vma; |
ff8f7975 | 146 | u64 pinned; |
5a125c3c | 147 | |
ff8f7975 | 148 | pinned = ggtt->base.reserved; |
73aa808f | 149 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 150 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 151 | if (i915_vma_is_pinned(vma)) |
ca1543be | 152 | pinned += vma->node.size; |
1c7f4bca | 153 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 154 | if (i915_vma_is_pinned(vma)) |
ca1543be | 155 | pinned += vma->node.size; |
73aa808f | 156 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 157 | |
72e96d64 | 158 | args->aper_size = ggtt->base.total; |
0206e353 | 159 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 160 | |
5a125c3c EA |
161 | return 0; |
162 | } | |
163 | ||
03ac84f1 | 164 | static struct sg_table * |
6a2c4232 | 165 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
00731155 | 166 | { |
93c76a3d | 167 | struct address_space *mapping = obj->base.filp->f_mapping; |
dbb4351b | 168 | drm_dma_handle_t *phys; |
6a2c4232 CW |
169 | struct sg_table *st; |
170 | struct scatterlist *sg; | |
dbb4351b | 171 | char *vaddr; |
6a2c4232 | 172 | int i; |
00731155 | 173 | |
6a2c4232 | 174 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
03ac84f1 | 175 | return ERR_PTR(-EINVAL); |
6a2c4232 | 176 | |
dbb4351b CW |
177 | /* Always aligning to the object size, allows a single allocation |
178 | * to handle all possible callers, and given typical object sizes, | |
179 | * the alignment of the buddy allocation will naturally match. | |
180 | */ | |
181 | phys = drm_pci_alloc(obj->base.dev, | |
182 | obj->base.size, | |
183 | roundup_pow_of_two(obj->base.size)); | |
184 | if (!phys) | |
185 | return ERR_PTR(-ENOMEM); | |
186 | ||
187 | vaddr = phys->vaddr; | |
6a2c4232 CW |
188 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
189 | struct page *page; | |
190 | char *src; | |
191 | ||
192 | page = shmem_read_mapping_page(mapping, i); | |
dbb4351b CW |
193 | if (IS_ERR(page)) { |
194 | st = ERR_CAST(page); | |
195 | goto err_phys; | |
196 | } | |
6a2c4232 CW |
197 | |
198 | src = kmap_atomic(page); | |
199 | memcpy(vaddr, src, PAGE_SIZE); | |
200 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
201 | kunmap_atomic(src); | |
202 | ||
09cbfeaf | 203 | put_page(page); |
6a2c4232 CW |
204 | vaddr += PAGE_SIZE; |
205 | } | |
206 | ||
c033666a | 207 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
208 | |
209 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
dbb4351b CW |
210 | if (!st) { |
211 | st = ERR_PTR(-ENOMEM); | |
212 | goto err_phys; | |
213 | } | |
6a2c4232 CW |
214 | |
215 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
216 | kfree(st); | |
dbb4351b CW |
217 | st = ERR_PTR(-ENOMEM); |
218 | goto err_phys; | |
6a2c4232 CW |
219 | } |
220 | ||
221 | sg = st->sgl; | |
222 | sg->offset = 0; | |
223 | sg->length = obj->base.size; | |
00731155 | 224 | |
dbb4351b | 225 | sg_dma_address(sg) = phys->busaddr; |
6a2c4232 CW |
226 | sg_dma_len(sg) = obj->base.size; |
227 | ||
dbb4351b CW |
228 | obj->phys_handle = phys; |
229 | return st; | |
230 | ||
231 | err_phys: | |
232 | drm_pci_free(obj->base.dev, phys); | |
03ac84f1 | 233 | return st; |
6a2c4232 CW |
234 | } |
235 | ||
e27ab73d CW |
236 | static void __start_cpu_write(struct drm_i915_gem_object *obj) |
237 | { | |
238 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
239 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
240 | if (cpu_write_needs_clflush(obj)) | |
241 | obj->cache_dirty = true; | |
242 | } | |
243 | ||
6a2c4232 | 244 | static void |
2b3c8317 | 245 | __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, |
e5facdf9 CW |
246 | struct sg_table *pages, |
247 | bool needs_clflush) | |
6a2c4232 | 248 | { |
a4f5ea64 | 249 | GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED); |
00731155 | 250 | |
a4f5ea64 CW |
251 | if (obj->mm.madv == I915_MADV_DONTNEED) |
252 | obj->mm.dirty = false; | |
6a2c4232 | 253 | |
e5facdf9 CW |
254 | if (needs_clflush && |
255 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 && | |
7fc92e96 | 256 | !obj->cache_coherent) |
2b3c8317 | 257 | drm_clflush_sg(pages); |
03ac84f1 | 258 | |
e27ab73d | 259 | __start_cpu_write(obj); |
03ac84f1 CW |
260 | } |
261 | ||
262 | static void | |
263 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj, | |
264 | struct sg_table *pages) | |
265 | { | |
e5facdf9 | 266 | __i915_gem_object_release_shmem(obj, pages, false); |
03ac84f1 | 267 | |
a4f5ea64 | 268 | if (obj->mm.dirty) { |
93c76a3d | 269 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 | 270 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
271 | int i; |
272 | ||
273 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
274 | struct page *page; |
275 | char *dst; | |
276 | ||
277 | page = shmem_read_mapping_page(mapping, i); | |
278 | if (IS_ERR(page)) | |
279 | continue; | |
280 | ||
281 | dst = kmap_atomic(page); | |
282 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
283 | memcpy(dst, vaddr, PAGE_SIZE); | |
284 | kunmap_atomic(dst); | |
285 | ||
286 | set_page_dirty(page); | |
a4f5ea64 | 287 | if (obj->mm.madv == I915_MADV_WILLNEED) |
00731155 | 288 | mark_page_accessed(page); |
09cbfeaf | 289 | put_page(page); |
00731155 CW |
290 | vaddr += PAGE_SIZE; |
291 | } | |
a4f5ea64 | 292 | obj->mm.dirty = false; |
00731155 CW |
293 | } |
294 | ||
03ac84f1 CW |
295 | sg_free_table(pages); |
296 | kfree(pages); | |
dbb4351b CW |
297 | |
298 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
6a2c4232 CW |
299 | } |
300 | ||
301 | static void | |
302 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
303 | { | |
a4f5ea64 | 304 | i915_gem_object_unpin_pages(obj); |
6a2c4232 CW |
305 | } |
306 | ||
307 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
308 | .get_pages = i915_gem_object_get_pages_phys, | |
309 | .put_pages = i915_gem_object_put_pages_phys, | |
310 | .release = i915_gem_object_release_phys, | |
311 | }; | |
312 | ||
581ab1fe CW |
313 | static const struct drm_i915_gem_object_ops i915_gem_object_ops; |
314 | ||
35a9611c | 315 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
aa653a68 CW |
316 | { |
317 | struct i915_vma *vma; | |
318 | LIST_HEAD(still_in_list); | |
02bef8f9 CW |
319 | int ret; |
320 | ||
321 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
aa653a68 | 322 | |
02bef8f9 CW |
323 | /* Closed vma are removed from the obj->vma_list - but they may |
324 | * still have an active binding on the object. To remove those we | |
325 | * must wait for all rendering to complete to the object (as unbinding | |
326 | * must anyway), and retire the requests. | |
aa653a68 | 327 | */ |
e95433c7 CW |
328 | ret = i915_gem_object_wait(obj, |
329 | I915_WAIT_INTERRUPTIBLE | | |
330 | I915_WAIT_LOCKED | | |
331 | I915_WAIT_ALL, | |
332 | MAX_SCHEDULE_TIMEOUT, | |
333 | NULL); | |
02bef8f9 CW |
334 | if (ret) |
335 | return ret; | |
336 | ||
337 | i915_gem_retire_requests(to_i915(obj->base.dev)); | |
338 | ||
aa653a68 CW |
339 | while ((vma = list_first_entry_or_null(&obj->vma_list, |
340 | struct i915_vma, | |
341 | obj_link))) { | |
342 | list_move_tail(&vma->obj_link, &still_in_list); | |
343 | ret = i915_vma_unbind(vma); | |
344 | if (ret) | |
345 | break; | |
346 | } | |
347 | list_splice(&still_in_list, &obj->vma_list); | |
348 | ||
349 | return ret; | |
350 | } | |
351 | ||
e95433c7 CW |
352 | static long |
353 | i915_gem_object_wait_fence(struct dma_fence *fence, | |
354 | unsigned int flags, | |
355 | long timeout, | |
356 | struct intel_rps_client *rps) | |
00e60f26 | 357 | { |
e95433c7 | 358 | struct drm_i915_gem_request *rq; |
00e60f26 | 359 | |
e95433c7 | 360 | BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1); |
00e60f26 | 361 | |
e95433c7 CW |
362 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
363 | return timeout; | |
364 | ||
365 | if (!dma_fence_is_i915(fence)) | |
366 | return dma_fence_wait_timeout(fence, | |
367 | flags & I915_WAIT_INTERRUPTIBLE, | |
368 | timeout); | |
369 | ||
370 | rq = to_request(fence); | |
371 | if (i915_gem_request_completed(rq)) | |
372 | goto out; | |
373 | ||
374 | /* This client is about to stall waiting for the GPU. In many cases | |
375 | * this is undesirable and limits the throughput of the system, as | |
376 | * many clients cannot continue processing user input/output whilst | |
377 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
378 | * to the GPU load and thus incurs additional latency for the client. | |
379 | * We can circumvent that by promoting the GPU frequency to maximum | |
380 | * before we wait. This makes the GPU throttle up much more quickly | |
381 | * (good for benchmarks and user experience, e.g. window animations), | |
382 | * but at a cost of spending more power processing the workload | |
383 | * (bad for battery). Not all clients even want their results | |
384 | * immediately and for them we should just let the GPU select its own | |
385 | * frequency to maximise efficiency. To prevent a single client from | |
386 | * forcing the clocks too high for the whole system, we only allow | |
387 | * each client to waitboost once in a busy period. | |
388 | */ | |
389 | if (rps) { | |
390 | if (INTEL_GEN(rq->i915) >= 6) | |
7b92c1bd | 391 | gen6_rps_boost(rq, rps); |
e95433c7 CW |
392 | else |
393 | rps = NULL; | |
00e60f26 CW |
394 | } |
395 | ||
e95433c7 CW |
396 | timeout = i915_wait_request(rq, flags, timeout); |
397 | ||
398 | out: | |
399 | if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq)) | |
400 | i915_gem_request_retire_upto(rq); | |
401 | ||
e95433c7 CW |
402 | return timeout; |
403 | } | |
404 | ||
405 | static long | |
406 | i915_gem_object_wait_reservation(struct reservation_object *resv, | |
407 | unsigned int flags, | |
408 | long timeout, | |
409 | struct intel_rps_client *rps) | |
410 | { | |
e54ca977 | 411 | unsigned int seq = __read_seqcount_begin(&resv->seq); |
e95433c7 | 412 | struct dma_fence *excl; |
e54ca977 | 413 | bool prune_fences = false; |
e95433c7 CW |
414 | |
415 | if (flags & I915_WAIT_ALL) { | |
416 | struct dma_fence **shared; | |
417 | unsigned int count, i; | |
00e60f26 CW |
418 | int ret; |
419 | ||
e95433c7 CW |
420 | ret = reservation_object_get_fences_rcu(resv, |
421 | &excl, &count, &shared); | |
00e60f26 CW |
422 | if (ret) |
423 | return ret; | |
00e60f26 | 424 | |
e95433c7 CW |
425 | for (i = 0; i < count; i++) { |
426 | timeout = i915_gem_object_wait_fence(shared[i], | |
427 | flags, timeout, | |
428 | rps); | |
d892e939 | 429 | if (timeout < 0) |
e95433c7 | 430 | break; |
00e60f26 | 431 | |
e95433c7 CW |
432 | dma_fence_put(shared[i]); |
433 | } | |
434 | ||
435 | for (; i < count; i++) | |
436 | dma_fence_put(shared[i]); | |
437 | kfree(shared); | |
e54ca977 CW |
438 | |
439 | prune_fences = count && timeout >= 0; | |
e95433c7 CW |
440 | } else { |
441 | excl = reservation_object_get_excl_rcu(resv); | |
00e60f26 CW |
442 | } |
443 | ||
e54ca977 | 444 | if (excl && timeout >= 0) { |
e95433c7 | 445 | timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps); |
e54ca977 CW |
446 | prune_fences = timeout >= 0; |
447 | } | |
e95433c7 CW |
448 | |
449 | dma_fence_put(excl); | |
450 | ||
03d1cac6 CW |
451 | /* Oportunistically prune the fences iff we know they have *all* been |
452 | * signaled and that the reservation object has not been changed (i.e. | |
453 | * no new fences have been added). | |
454 | */ | |
e54ca977 | 455 | if (prune_fences && !__read_seqcount_retry(&resv->seq, seq)) { |
03d1cac6 CW |
456 | if (reservation_object_trylock(resv)) { |
457 | if (!__read_seqcount_retry(&resv->seq, seq)) | |
458 | reservation_object_add_excl_fence(resv, NULL); | |
459 | reservation_object_unlock(resv); | |
460 | } | |
e54ca977 CW |
461 | } |
462 | ||
e95433c7 | 463 | return timeout; |
00e60f26 CW |
464 | } |
465 | ||
6b5e90f5 CW |
466 | static void __fence_set_priority(struct dma_fence *fence, int prio) |
467 | { | |
468 | struct drm_i915_gem_request *rq; | |
469 | struct intel_engine_cs *engine; | |
470 | ||
471 | if (!dma_fence_is_i915(fence)) | |
472 | return; | |
473 | ||
474 | rq = to_request(fence); | |
475 | engine = rq->engine; | |
476 | if (!engine->schedule) | |
477 | return; | |
478 | ||
479 | engine->schedule(rq, prio); | |
480 | } | |
481 | ||
482 | static void fence_set_priority(struct dma_fence *fence, int prio) | |
483 | { | |
484 | /* Recurse once into a fence-array */ | |
485 | if (dma_fence_is_array(fence)) { | |
486 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
487 | int i; | |
488 | ||
489 | for (i = 0; i < array->num_fences; i++) | |
490 | __fence_set_priority(array->fences[i], prio); | |
491 | } else { | |
492 | __fence_set_priority(fence, prio); | |
493 | } | |
494 | } | |
495 | ||
496 | int | |
497 | i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, | |
498 | unsigned int flags, | |
499 | int prio) | |
500 | { | |
501 | struct dma_fence *excl; | |
502 | ||
503 | if (flags & I915_WAIT_ALL) { | |
504 | struct dma_fence **shared; | |
505 | unsigned int count, i; | |
506 | int ret; | |
507 | ||
508 | ret = reservation_object_get_fences_rcu(obj->resv, | |
509 | &excl, &count, &shared); | |
510 | if (ret) | |
511 | return ret; | |
512 | ||
513 | for (i = 0; i < count; i++) { | |
514 | fence_set_priority(shared[i], prio); | |
515 | dma_fence_put(shared[i]); | |
516 | } | |
517 | ||
518 | kfree(shared); | |
519 | } else { | |
520 | excl = reservation_object_get_excl_rcu(obj->resv); | |
521 | } | |
522 | ||
523 | if (excl) { | |
524 | fence_set_priority(excl, prio); | |
525 | dma_fence_put(excl); | |
526 | } | |
527 | return 0; | |
528 | } | |
529 | ||
e95433c7 CW |
530 | /** |
531 | * Waits for rendering to the object to be completed | |
532 | * @obj: i915 gem object | |
533 | * @flags: how to wait (under a lock, for all rendering or just for writes etc) | |
534 | * @timeout: how long to wait | |
535 | * @rps: client (user process) to charge for any waitboosting | |
00e60f26 | 536 | */ |
e95433c7 CW |
537 | int |
538 | i915_gem_object_wait(struct drm_i915_gem_object *obj, | |
539 | unsigned int flags, | |
540 | long timeout, | |
541 | struct intel_rps_client *rps) | |
00e60f26 | 542 | { |
e95433c7 CW |
543 | might_sleep(); |
544 | #if IS_ENABLED(CONFIG_LOCKDEP) | |
545 | GEM_BUG_ON(debug_locks && | |
546 | !!lockdep_is_held(&obj->base.dev->struct_mutex) != | |
547 | !!(flags & I915_WAIT_LOCKED)); | |
548 | #endif | |
549 | GEM_BUG_ON(timeout < 0); | |
00e60f26 | 550 | |
d07f0e59 CW |
551 | timeout = i915_gem_object_wait_reservation(obj->resv, |
552 | flags, timeout, | |
553 | rps); | |
e95433c7 | 554 | return timeout < 0 ? timeout : 0; |
00e60f26 CW |
555 | } |
556 | ||
557 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
558 | { | |
559 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
560 | ||
561 | return &fpriv->rps; | |
562 | } | |
563 | ||
00731155 CW |
564 | int |
565 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
566 | int align) | |
567 | { | |
6a2c4232 | 568 | int ret; |
00731155 | 569 | |
dbb4351b CW |
570 | if (align > obj->base.size) |
571 | return -EINVAL; | |
00731155 | 572 | |
dbb4351b | 573 | if (obj->ops == &i915_gem_phys_ops) |
00731155 | 574 | return 0; |
00731155 | 575 | |
a4f5ea64 | 576 | if (obj->mm.madv != I915_MADV_WILLNEED) |
00731155 CW |
577 | return -EFAULT; |
578 | ||
579 | if (obj->base.filp == NULL) | |
580 | return -EINVAL; | |
581 | ||
4717ca9e CW |
582 | ret = i915_gem_object_unbind(obj); |
583 | if (ret) | |
584 | return ret; | |
585 | ||
548625ee | 586 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
03ac84f1 CW |
587 | if (obj->mm.pages) |
588 | return -EBUSY; | |
6a2c4232 | 589 | |
581ab1fe | 590 | GEM_BUG_ON(obj->ops != &i915_gem_object_ops); |
6a2c4232 CW |
591 | obj->ops = &i915_gem_phys_ops; |
592 | ||
581ab1fe CW |
593 | ret = i915_gem_object_pin_pages(obj); |
594 | if (ret) | |
595 | goto err_xfer; | |
596 | ||
597 | return 0; | |
598 | ||
599 | err_xfer: | |
600 | obj->ops = &i915_gem_object_ops; | |
601 | return ret; | |
00731155 CW |
602 | } |
603 | ||
604 | static int | |
605 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
606 | struct drm_i915_gem_pwrite *args, | |
03ac84f1 | 607 | struct drm_file *file) |
00731155 | 608 | { |
00731155 | 609 | void *vaddr = obj->phys_handle->vaddr + args->offset; |
3ed605bc | 610 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
6a2c4232 CW |
611 | |
612 | /* We manually control the domain here and pretend that it | |
613 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
614 | */ | |
77a0d1ca | 615 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
10466d2a CW |
616 | if (copy_from_user(vaddr, user_data, args->size)) |
617 | return -EFAULT; | |
00731155 | 618 | |
6a2c4232 | 619 | drm_clflush_virt_range(vaddr, args->size); |
10466d2a | 620 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
063e4e6b | 621 | |
d59b21ec | 622 | intel_fb_obj_flush(obj, ORIGIN_CPU); |
10466d2a | 623 | return 0; |
00731155 CW |
624 | } |
625 | ||
187685cb | 626 | void *i915_gem_object_alloc(struct drm_i915_private *dev_priv) |
42dcedd4 | 627 | { |
efab6d8d | 628 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
629 | } |
630 | ||
631 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
632 | { | |
fac5e23e | 633 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 634 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
635 | } |
636 | ||
ff72145b DA |
637 | static int |
638 | i915_gem_create(struct drm_file *file, | |
12d79d78 | 639 | struct drm_i915_private *dev_priv, |
ff72145b DA |
640 | uint64_t size, |
641 | uint32_t *handle_p) | |
673a394b | 642 | { |
05394f39 | 643 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
644 | int ret; |
645 | u32 handle; | |
673a394b | 646 | |
ff72145b | 647 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
648 | if (size == 0) |
649 | return -EINVAL; | |
673a394b EA |
650 | |
651 | /* Allocate the new object */ | |
12d79d78 | 652 | obj = i915_gem_object_create(dev_priv, size); |
fe3db79b CW |
653 | if (IS_ERR(obj)) |
654 | return PTR_ERR(obj); | |
673a394b | 655 | |
05394f39 | 656 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 657 | /* drop reference from allocate - handle holds it now */ |
f0cd5182 | 658 | i915_gem_object_put(obj); |
d861e338 DV |
659 | if (ret) |
660 | return ret; | |
202f2fef | 661 | |
ff72145b | 662 | *handle_p = handle; |
673a394b EA |
663 | return 0; |
664 | } | |
665 | ||
ff72145b DA |
666 | int |
667 | i915_gem_dumb_create(struct drm_file *file, | |
668 | struct drm_device *dev, | |
669 | struct drm_mode_create_dumb *args) | |
670 | { | |
671 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 672 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b | 673 | args->size = args->pitch * args->height; |
12d79d78 | 674 | return i915_gem_create(file, to_i915(dev), |
da6b51d0 | 675 | args->size, &args->handle); |
ff72145b DA |
676 | } |
677 | ||
e27ab73d CW |
678 | static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
679 | { | |
680 | return !(obj->cache_level == I915_CACHE_NONE || | |
681 | obj->cache_level == I915_CACHE_WT); | |
682 | } | |
683 | ||
ff72145b DA |
684 | /** |
685 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
686 | * @dev: drm device pointer |
687 | * @data: ioctl data blob | |
688 | * @file: drm file pointer | |
ff72145b DA |
689 | */ |
690 | int | |
691 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
692 | struct drm_file *file) | |
693 | { | |
12d79d78 | 694 | struct drm_i915_private *dev_priv = to_i915(dev); |
ff72145b | 695 | struct drm_i915_gem_create *args = data; |
63ed2cb2 | 696 | |
12d79d78 | 697 | i915_gem_flush_free_objects(dev_priv); |
fbbd37b3 | 698 | |
12d79d78 | 699 | return i915_gem_create(file, dev_priv, |
da6b51d0 | 700 | args->size, &args->handle); |
ff72145b DA |
701 | } |
702 | ||
ef74921b CW |
703 | static inline enum fb_op_origin |
704 | fb_write_origin(struct drm_i915_gem_object *obj, unsigned int domain) | |
705 | { | |
706 | return (domain == I915_GEM_DOMAIN_GTT ? | |
707 | obj->frontbuffer_ggtt_origin : ORIGIN_CPU); | |
708 | } | |
709 | ||
710 | static void | |
711 | flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) | |
712 | { | |
713 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); | |
714 | ||
715 | if (!(obj->base.write_domain & flush_domains)) | |
716 | return; | |
717 | ||
718 | /* No actual flushing is required for the GTT write domain. Writes | |
719 | * to it "immediately" go to main memory as far as we know, so there's | |
720 | * no chipset flush. It also doesn't land in render cache. | |
721 | * | |
722 | * However, we do have to enforce the order so that all writes through | |
723 | * the GTT land before any writes to the device, such as updates to | |
724 | * the GATT itself. | |
725 | * | |
726 | * We also have to wait a bit for the writes to land from the GTT. | |
727 | * An uncached read (i.e. mmio) seems to be ideal for the round-trip | |
728 | * timing. This issue has only been observed when switching quickly | |
729 | * between GTT writes and CPU reads from inside the kernel on recent hw, | |
730 | * and it appears to only affect discrete GTT blocks (i.e. on LLC | |
731 | * system agents we cannot reproduce this behaviour). | |
732 | */ | |
733 | wmb(); | |
734 | ||
735 | switch (obj->base.write_domain) { | |
736 | case I915_GEM_DOMAIN_GTT: | |
737 | if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) { | |
738 | if (intel_runtime_pm_get_if_in_use(dev_priv)) { | |
739 | spin_lock_irq(&dev_priv->uncore.lock); | |
740 | POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base)); | |
741 | spin_unlock_irq(&dev_priv->uncore.lock); | |
742 | intel_runtime_pm_put(dev_priv); | |
743 | } | |
744 | } | |
745 | ||
746 | intel_fb_obj_flush(obj, | |
747 | fb_write_origin(obj, I915_GEM_DOMAIN_GTT)); | |
748 | break; | |
749 | ||
750 | case I915_GEM_DOMAIN_CPU: | |
751 | i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC); | |
752 | break; | |
e27ab73d CW |
753 | |
754 | case I915_GEM_DOMAIN_RENDER: | |
755 | if (gpu_write_needs_clflush(obj)) | |
756 | obj->cache_dirty = true; | |
757 | break; | |
ef74921b CW |
758 | } |
759 | ||
760 | obj->base.write_domain = 0; | |
761 | } | |
762 | ||
8461d226 DV |
763 | static inline int |
764 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
765 | const char *gpu_vaddr, int gpu_offset, | |
766 | int length) | |
767 | { | |
768 | int ret, cpu_offset = 0; | |
769 | ||
770 | while (length > 0) { | |
771 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
772 | int this_length = min(cacheline_end - gpu_offset, length); | |
773 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
774 | ||
775 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
776 | gpu_vaddr + swizzled_gpu_offset, | |
777 | this_length); | |
778 | if (ret) | |
779 | return ret + length; | |
780 | ||
781 | cpu_offset += this_length; | |
782 | gpu_offset += this_length; | |
783 | length -= this_length; | |
784 | } | |
785 | ||
786 | return 0; | |
787 | } | |
788 | ||
8c59967c | 789 | static inline int |
4f0c7cfb BW |
790 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
791 | const char __user *cpu_vaddr, | |
8c59967c DV |
792 | int length) |
793 | { | |
794 | int ret, cpu_offset = 0; | |
795 | ||
796 | while (length > 0) { | |
797 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
798 | int this_length = min(cacheline_end - gpu_offset, length); | |
799 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
800 | ||
801 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
802 | cpu_vaddr + cpu_offset, | |
803 | this_length); | |
804 | if (ret) | |
805 | return ret + length; | |
806 | ||
807 | cpu_offset += this_length; | |
808 | gpu_offset += this_length; | |
809 | length -= this_length; | |
810 | } | |
811 | ||
812 | return 0; | |
813 | } | |
814 | ||
4c914c0c BV |
815 | /* |
816 | * Pins the specified object's pages and synchronizes the object with | |
817 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
818 | * flush the object from the CPU cache. | |
819 | */ | |
820 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
43394c7d | 821 | unsigned int *needs_clflush) |
4c914c0c BV |
822 | { |
823 | int ret; | |
824 | ||
e95433c7 | 825 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c914c0c | 826 | |
e95433c7 | 827 | *needs_clflush = 0; |
43394c7d CW |
828 | if (!i915_gem_object_has_struct_page(obj)) |
829 | return -ENODEV; | |
4c914c0c | 830 | |
e95433c7 CW |
831 | ret = i915_gem_object_wait(obj, |
832 | I915_WAIT_INTERRUPTIBLE | | |
833 | I915_WAIT_LOCKED, | |
834 | MAX_SCHEDULE_TIMEOUT, | |
835 | NULL); | |
c13d87ea CW |
836 | if (ret) |
837 | return ret; | |
838 | ||
a4f5ea64 | 839 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
840 | if (ret) |
841 | return ret; | |
842 | ||
7fc92e96 | 843 | if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
7f5f95d8 CW |
844 | ret = i915_gem_object_set_to_cpu_domain(obj, false); |
845 | if (ret) | |
846 | goto err_unpin; | |
847 | else | |
848 | goto out; | |
849 | } | |
850 | ||
ef74921b | 851 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); |
a314d5cb | 852 | |
43394c7d CW |
853 | /* If we're not in the cpu read domain, set ourself into the gtt |
854 | * read domain and manually flush cachelines (if required). This | |
855 | * optimizes for the case when the gpu will dirty the data | |
856 | * anyway again before the next pread happens. | |
857 | */ | |
e27ab73d CW |
858 | if (!obj->cache_dirty && |
859 | !(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
7f5f95d8 | 860 | *needs_clflush = CLFLUSH_BEFORE; |
4c914c0c | 861 | |
7f5f95d8 | 862 | out: |
9764951e | 863 | /* return with the pages pinned */ |
43394c7d | 864 | return 0; |
9764951e CW |
865 | |
866 | err_unpin: | |
867 | i915_gem_object_unpin_pages(obj); | |
868 | return ret; | |
43394c7d CW |
869 | } |
870 | ||
871 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
872 | unsigned int *needs_clflush) | |
873 | { | |
874 | int ret; | |
875 | ||
e95433c7 CW |
876 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
877 | ||
43394c7d CW |
878 | *needs_clflush = 0; |
879 | if (!i915_gem_object_has_struct_page(obj)) | |
880 | return -ENODEV; | |
881 | ||
e95433c7 CW |
882 | ret = i915_gem_object_wait(obj, |
883 | I915_WAIT_INTERRUPTIBLE | | |
884 | I915_WAIT_LOCKED | | |
885 | I915_WAIT_ALL, | |
886 | MAX_SCHEDULE_TIMEOUT, | |
887 | NULL); | |
43394c7d CW |
888 | if (ret) |
889 | return ret; | |
890 | ||
a4f5ea64 | 891 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
892 | if (ret) |
893 | return ret; | |
894 | ||
7fc92e96 | 895 | if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
7f5f95d8 CW |
896 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
897 | if (ret) | |
898 | goto err_unpin; | |
899 | else | |
900 | goto out; | |
901 | } | |
902 | ||
ef74921b | 903 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); |
a314d5cb | 904 | |
43394c7d CW |
905 | /* If we're not in the cpu write domain, set ourself into the |
906 | * gtt write domain and manually flush cachelines (as required). | |
907 | * This optimizes for the case when the gpu will use the data | |
908 | * right away and we therefore have to clflush anyway. | |
909 | */ | |
e27ab73d | 910 | if (!obj->cache_dirty) { |
7f5f95d8 | 911 | *needs_clflush |= CLFLUSH_AFTER; |
43394c7d | 912 | |
e27ab73d CW |
913 | /* |
914 | * Same trick applies to invalidate partially written | |
915 | * cachelines read before writing. | |
916 | */ | |
917 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
918 | *needs_clflush |= CLFLUSH_BEFORE; | |
919 | } | |
43394c7d | 920 | |
7f5f95d8 | 921 | out: |
43394c7d | 922 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
a4f5ea64 | 923 | obj->mm.dirty = true; |
9764951e | 924 | /* return with the pages pinned */ |
43394c7d | 925 | return 0; |
9764951e CW |
926 | |
927 | err_unpin: | |
928 | i915_gem_object_unpin_pages(obj); | |
929 | return ret; | |
4c914c0c BV |
930 | } |
931 | ||
23c18c71 DV |
932 | static void |
933 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
934 | bool swizzled) | |
935 | { | |
e7e58eb5 | 936 | if (unlikely(swizzled)) { |
23c18c71 DV |
937 | unsigned long start = (unsigned long) addr; |
938 | unsigned long end = (unsigned long) addr + length; | |
939 | ||
940 | /* For swizzling simply ensure that we always flush both | |
941 | * channels. Lame, but simple and it works. Swizzled | |
942 | * pwrite/pread is far from a hotpath - current userspace | |
943 | * doesn't use it at all. */ | |
944 | start = round_down(start, 128); | |
945 | end = round_up(end, 128); | |
946 | ||
947 | drm_clflush_virt_range((void *)start, end - start); | |
948 | } else { | |
949 | drm_clflush_virt_range(addr, length); | |
950 | } | |
951 | ||
952 | } | |
953 | ||
d174bd64 DV |
954 | /* Only difference to the fast-path function is that this can handle bit17 |
955 | * and uses non-atomic copy and kmap functions. */ | |
956 | static int | |
bb6dc8d9 | 957 | shmem_pread_slow(struct page *page, int offset, int length, |
d174bd64 DV |
958 | char __user *user_data, |
959 | bool page_do_bit17_swizzling, bool needs_clflush) | |
960 | { | |
961 | char *vaddr; | |
962 | int ret; | |
963 | ||
964 | vaddr = kmap(page); | |
965 | if (needs_clflush) | |
bb6dc8d9 | 966 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 967 | page_do_bit17_swizzling); |
d174bd64 DV |
968 | |
969 | if (page_do_bit17_swizzling) | |
bb6dc8d9 | 970 | ret = __copy_to_user_swizzled(user_data, vaddr, offset, length); |
d174bd64 | 971 | else |
bb6dc8d9 | 972 | ret = __copy_to_user(user_data, vaddr + offset, length); |
d174bd64 DV |
973 | kunmap(page); |
974 | ||
f60d7f0c | 975 | return ret ? - EFAULT : 0; |
d174bd64 DV |
976 | } |
977 | ||
bb6dc8d9 CW |
978 | static int |
979 | shmem_pread(struct page *page, int offset, int length, char __user *user_data, | |
980 | bool page_do_bit17_swizzling, bool needs_clflush) | |
981 | { | |
982 | int ret; | |
983 | ||
984 | ret = -ENODEV; | |
985 | if (!page_do_bit17_swizzling) { | |
986 | char *vaddr = kmap_atomic(page); | |
987 | ||
988 | if (needs_clflush) | |
989 | drm_clflush_virt_range(vaddr + offset, length); | |
990 | ret = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
991 | kunmap_atomic(vaddr); | |
992 | } | |
993 | if (ret == 0) | |
994 | return 0; | |
995 | ||
996 | return shmem_pread_slow(page, offset, length, user_data, | |
997 | page_do_bit17_swizzling, needs_clflush); | |
998 | } | |
999 | ||
1000 | static int | |
1001 | i915_gem_shmem_pread(struct drm_i915_gem_object *obj, | |
1002 | struct drm_i915_gem_pread *args) | |
1003 | { | |
1004 | char __user *user_data; | |
1005 | u64 remain; | |
1006 | unsigned int obj_do_bit17_swizzling; | |
1007 | unsigned int needs_clflush; | |
1008 | unsigned int idx, offset; | |
1009 | int ret; | |
1010 | ||
1011 | obj_do_bit17_swizzling = 0; | |
1012 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
1013 | obj_do_bit17_swizzling = BIT(17); | |
1014 | ||
1015 | ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex); | |
1016 | if (ret) | |
1017 | return ret; | |
1018 | ||
1019 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); | |
1020 | mutex_unlock(&obj->base.dev->struct_mutex); | |
1021 | if (ret) | |
1022 | return ret; | |
1023 | ||
1024 | remain = args->size; | |
1025 | user_data = u64_to_user_ptr(args->data_ptr); | |
1026 | offset = offset_in_page(args->offset); | |
1027 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
1028 | struct page *page = i915_gem_object_get_page(obj, idx); | |
1029 | int length; | |
1030 | ||
1031 | length = remain; | |
1032 | if (offset + length > PAGE_SIZE) | |
1033 | length = PAGE_SIZE - offset; | |
1034 | ||
1035 | ret = shmem_pread(page, offset, length, user_data, | |
1036 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1037 | needs_clflush); | |
1038 | if (ret) | |
1039 | break; | |
1040 | ||
1041 | remain -= length; | |
1042 | user_data += length; | |
1043 | offset = 0; | |
1044 | } | |
1045 | ||
1046 | i915_gem_obj_finish_shmem_access(obj); | |
1047 | return ret; | |
1048 | } | |
1049 | ||
1050 | static inline bool | |
1051 | gtt_user_read(struct io_mapping *mapping, | |
1052 | loff_t base, int offset, | |
1053 | char __user *user_data, int length) | |
b50a5371 | 1054 | { |
b50a5371 | 1055 | void *vaddr; |
bb6dc8d9 | 1056 | unsigned long unwritten; |
b50a5371 | 1057 | |
b50a5371 | 1058 | /* We can use the cpu mem copy function because this is X86. */ |
bb6dc8d9 CW |
1059 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
1060 | unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
1061 | io_mapping_unmap_atomic(vaddr); | |
1062 | if (unwritten) { | |
1063 | vaddr = (void __force *) | |
1064 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
1065 | unwritten = copy_to_user(user_data, vaddr + offset, length); | |
1066 | io_mapping_unmap(vaddr); | |
1067 | } | |
b50a5371 AS |
1068 | return unwritten; |
1069 | } | |
1070 | ||
1071 | static int | |
bb6dc8d9 CW |
1072 | i915_gem_gtt_pread(struct drm_i915_gem_object *obj, |
1073 | const struct drm_i915_gem_pread *args) | |
b50a5371 | 1074 | { |
bb6dc8d9 CW |
1075 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
1076 | struct i915_ggtt *ggtt = &i915->ggtt; | |
b50a5371 | 1077 | struct drm_mm_node node; |
bb6dc8d9 CW |
1078 | struct i915_vma *vma; |
1079 | void __user *user_data; | |
1080 | u64 remain, offset; | |
b50a5371 AS |
1081 | int ret; |
1082 | ||
bb6dc8d9 CW |
1083 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1084 | if (ret) | |
1085 | return ret; | |
1086 | ||
1087 | intel_runtime_pm_get(i915); | |
1088 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, | |
1089 | PIN_MAPPABLE | PIN_NONBLOCK); | |
18034584 CW |
1090 | if (!IS_ERR(vma)) { |
1091 | node.start = i915_ggtt_offset(vma); | |
1092 | node.allocated = false; | |
49ef5294 | 1093 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1094 | if (ret) { |
1095 | i915_vma_unpin(vma); | |
1096 | vma = ERR_PTR(ret); | |
1097 | } | |
1098 | } | |
058d88c4 | 1099 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1100 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
b50a5371 | 1101 | if (ret) |
bb6dc8d9 CW |
1102 | goto out_unlock; |
1103 | GEM_BUG_ON(!node.allocated); | |
b50a5371 AS |
1104 | } |
1105 | ||
1106 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1107 | if (ret) | |
1108 | goto out_unpin; | |
1109 | ||
bb6dc8d9 | 1110 | mutex_unlock(&i915->drm.struct_mutex); |
b50a5371 | 1111 | |
bb6dc8d9 CW |
1112 | user_data = u64_to_user_ptr(args->data_ptr); |
1113 | remain = args->size; | |
1114 | offset = args->offset; | |
b50a5371 AS |
1115 | |
1116 | while (remain > 0) { | |
1117 | /* Operation in this page | |
1118 | * | |
1119 | * page_base = page offset within aperture | |
1120 | * page_offset = offset within page | |
1121 | * page_length = bytes to copy for this page | |
1122 | */ | |
1123 | u32 page_base = node.start; | |
1124 | unsigned page_offset = offset_in_page(offset); | |
1125 | unsigned page_length = PAGE_SIZE - page_offset; | |
1126 | page_length = remain < page_length ? remain : page_length; | |
1127 | if (node.allocated) { | |
1128 | wmb(); | |
1129 | ggtt->base.insert_page(&ggtt->base, | |
1130 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
bb6dc8d9 | 1131 | node.start, I915_CACHE_NONE, 0); |
b50a5371 AS |
1132 | wmb(); |
1133 | } else { | |
1134 | page_base += offset & PAGE_MASK; | |
1135 | } | |
bb6dc8d9 CW |
1136 | |
1137 | if (gtt_user_read(&ggtt->mappable, page_base, page_offset, | |
1138 | user_data, page_length)) { | |
b50a5371 AS |
1139 | ret = -EFAULT; |
1140 | break; | |
1141 | } | |
1142 | ||
1143 | remain -= page_length; | |
1144 | user_data += page_length; | |
1145 | offset += page_length; | |
1146 | } | |
1147 | ||
bb6dc8d9 | 1148 | mutex_lock(&i915->drm.struct_mutex); |
b50a5371 AS |
1149 | out_unpin: |
1150 | if (node.allocated) { | |
1151 | wmb(); | |
1152 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1153 | node.start, node.size); |
b50a5371 AS |
1154 | remove_mappable_node(&node); |
1155 | } else { | |
058d88c4 | 1156 | i915_vma_unpin(vma); |
b50a5371 | 1157 | } |
bb6dc8d9 CW |
1158 | out_unlock: |
1159 | intel_runtime_pm_put(i915); | |
1160 | mutex_unlock(&i915->drm.struct_mutex); | |
f60d7f0c | 1161 | |
eb01459f EA |
1162 | return ret; |
1163 | } | |
1164 | ||
673a394b EA |
1165 | /** |
1166 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
1167 | * @dev: drm device pointer |
1168 | * @data: ioctl data blob | |
1169 | * @file: drm file pointer | |
673a394b EA |
1170 | * |
1171 | * On error, the contents of *data are undefined. | |
1172 | */ | |
1173 | int | |
1174 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1175 | struct drm_file *file) |
673a394b EA |
1176 | { |
1177 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 1178 | struct drm_i915_gem_object *obj; |
bb6dc8d9 | 1179 | int ret; |
673a394b | 1180 | |
51311d0a CW |
1181 | if (args->size == 0) |
1182 | return 0; | |
1183 | ||
1184 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 1185 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1186 | args->size)) |
1187 | return -EFAULT; | |
1188 | ||
03ac0642 | 1189 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1190 | if (!obj) |
1191 | return -ENOENT; | |
673a394b | 1192 | |
7dcd2499 | 1193 | /* Bounds check source. */ |
966d5bf5 | 1194 | if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { |
ce9d419d | 1195 | ret = -EINVAL; |
bb6dc8d9 | 1196 | goto out; |
ce9d419d CW |
1197 | } |
1198 | ||
db53a302 CW |
1199 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
1200 | ||
e95433c7 CW |
1201 | ret = i915_gem_object_wait(obj, |
1202 | I915_WAIT_INTERRUPTIBLE, | |
1203 | MAX_SCHEDULE_TIMEOUT, | |
1204 | to_rps_client(file)); | |
258a5ede | 1205 | if (ret) |
bb6dc8d9 | 1206 | goto out; |
258a5ede | 1207 | |
bb6dc8d9 | 1208 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1209 | if (ret) |
bb6dc8d9 | 1210 | goto out; |
673a394b | 1211 | |
bb6dc8d9 | 1212 | ret = i915_gem_shmem_pread(obj, args); |
9c870d03 | 1213 | if (ret == -EFAULT || ret == -ENODEV) |
bb6dc8d9 | 1214 | ret = i915_gem_gtt_pread(obj, args); |
b50a5371 | 1215 | |
bb6dc8d9 CW |
1216 | i915_gem_object_unpin_pages(obj); |
1217 | out: | |
f0cd5182 | 1218 | i915_gem_object_put(obj); |
eb01459f | 1219 | return ret; |
673a394b EA |
1220 | } |
1221 | ||
0839ccb8 KP |
1222 | /* This is the fast write path which cannot handle |
1223 | * page faults in the source data | |
9b7530cc | 1224 | */ |
0839ccb8 | 1225 | |
fe115628 CW |
1226 | static inline bool |
1227 | ggtt_write(struct io_mapping *mapping, | |
1228 | loff_t base, int offset, | |
1229 | char __user *user_data, int length) | |
9b7530cc | 1230 | { |
4f0c7cfb | 1231 | void *vaddr; |
0839ccb8 | 1232 | unsigned long unwritten; |
9b7530cc | 1233 | |
4f0c7cfb | 1234 | /* We can use the cpu mem copy function because this is X86. */ |
fe115628 CW |
1235 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
1236 | unwritten = __copy_from_user_inatomic_nocache(vaddr + offset, | |
0839ccb8 | 1237 | user_data, length); |
fe115628 CW |
1238 | io_mapping_unmap_atomic(vaddr); |
1239 | if (unwritten) { | |
1240 | vaddr = (void __force *) | |
1241 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
1242 | unwritten = copy_from_user(vaddr + offset, user_data, length); | |
1243 | io_mapping_unmap(vaddr); | |
1244 | } | |
bb6dc8d9 | 1245 | |
bb6dc8d9 CW |
1246 | return unwritten; |
1247 | } | |
1248 | ||
3de09aa3 EA |
1249 | /** |
1250 | * This is the fast pwrite path, where we copy the data directly from the | |
1251 | * user into the GTT, uncached. | |
fe115628 | 1252 | * @obj: i915 GEM object |
14bb2c11 | 1253 | * @args: pwrite arguments structure |
3de09aa3 | 1254 | */ |
673a394b | 1255 | static int |
fe115628 CW |
1256 | i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, |
1257 | const struct drm_i915_gem_pwrite *args) | |
673a394b | 1258 | { |
fe115628 | 1259 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
4f1959ee AS |
1260 | struct i915_ggtt *ggtt = &i915->ggtt; |
1261 | struct drm_mm_node node; | |
fe115628 CW |
1262 | struct i915_vma *vma; |
1263 | u64 remain, offset; | |
1264 | void __user *user_data; | |
4f1959ee | 1265 | int ret; |
b50a5371 | 1266 | |
fe115628 CW |
1267 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1268 | if (ret) | |
1269 | return ret; | |
935aaa69 | 1270 | |
9c870d03 | 1271 | intel_runtime_pm_get(i915); |
058d88c4 | 1272 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
de895082 | 1273 | PIN_MAPPABLE | PIN_NONBLOCK); |
18034584 CW |
1274 | if (!IS_ERR(vma)) { |
1275 | node.start = i915_ggtt_offset(vma); | |
1276 | node.allocated = false; | |
49ef5294 | 1277 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1278 | if (ret) { |
1279 | i915_vma_unpin(vma); | |
1280 | vma = ERR_PTR(ret); | |
1281 | } | |
1282 | } | |
058d88c4 | 1283 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1284 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
4f1959ee | 1285 | if (ret) |
fe115628 CW |
1286 | goto out_unlock; |
1287 | GEM_BUG_ON(!node.allocated); | |
4f1959ee | 1288 | } |
935aaa69 DV |
1289 | |
1290 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1291 | if (ret) | |
1292 | goto out_unpin; | |
1293 | ||
fe115628 CW |
1294 | mutex_unlock(&i915->drm.struct_mutex); |
1295 | ||
b19482d7 | 1296 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1297 | |
4f1959ee AS |
1298 | user_data = u64_to_user_ptr(args->data_ptr); |
1299 | offset = args->offset; | |
1300 | remain = args->size; | |
1301 | while (remain) { | |
673a394b EA |
1302 | /* Operation in this page |
1303 | * | |
0839ccb8 KP |
1304 | * page_base = page offset within aperture |
1305 | * page_offset = offset within page | |
1306 | * page_length = bytes to copy for this page | |
673a394b | 1307 | */ |
4f1959ee | 1308 | u32 page_base = node.start; |
bb6dc8d9 CW |
1309 | unsigned int page_offset = offset_in_page(offset); |
1310 | unsigned int page_length = PAGE_SIZE - page_offset; | |
4f1959ee AS |
1311 | page_length = remain < page_length ? remain : page_length; |
1312 | if (node.allocated) { | |
1313 | wmb(); /* flush the write before we modify the GGTT */ | |
1314 | ggtt->base.insert_page(&ggtt->base, | |
1315 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1316 | node.start, I915_CACHE_NONE, 0); | |
1317 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1318 | } else { | |
1319 | page_base += offset & PAGE_MASK; | |
1320 | } | |
0839ccb8 | 1321 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1322 | * source page isn't available. Return the error and we'll |
1323 | * retry in the slow path. | |
b50a5371 AS |
1324 | * If the object is non-shmem backed, we retry again with the |
1325 | * path that handles page fault. | |
0839ccb8 | 1326 | */ |
fe115628 CW |
1327 | if (ggtt_write(&ggtt->mappable, page_base, page_offset, |
1328 | user_data, page_length)) { | |
1329 | ret = -EFAULT; | |
1330 | break; | |
935aaa69 | 1331 | } |
673a394b | 1332 | |
0839ccb8 KP |
1333 | remain -= page_length; |
1334 | user_data += page_length; | |
1335 | offset += page_length; | |
673a394b | 1336 | } |
d59b21ec | 1337 | intel_fb_obj_flush(obj, ORIGIN_CPU); |
fe115628 CW |
1338 | |
1339 | mutex_lock(&i915->drm.struct_mutex); | |
935aaa69 | 1340 | out_unpin: |
4f1959ee AS |
1341 | if (node.allocated) { |
1342 | wmb(); | |
1343 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1344 | node.start, node.size); |
4f1959ee AS |
1345 | remove_mappable_node(&node); |
1346 | } else { | |
058d88c4 | 1347 | i915_vma_unpin(vma); |
4f1959ee | 1348 | } |
fe115628 | 1349 | out_unlock: |
9c870d03 | 1350 | intel_runtime_pm_put(i915); |
fe115628 | 1351 | mutex_unlock(&i915->drm.struct_mutex); |
3de09aa3 | 1352 | return ret; |
673a394b EA |
1353 | } |
1354 | ||
3043c60c | 1355 | static int |
fe115628 | 1356 | shmem_pwrite_slow(struct page *page, int offset, int length, |
d174bd64 DV |
1357 | char __user *user_data, |
1358 | bool page_do_bit17_swizzling, | |
1359 | bool needs_clflush_before, | |
1360 | bool needs_clflush_after) | |
673a394b | 1361 | { |
d174bd64 DV |
1362 | char *vaddr; |
1363 | int ret; | |
e5281ccd | 1364 | |
d174bd64 | 1365 | vaddr = kmap(page); |
e7e58eb5 | 1366 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
fe115628 | 1367 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1368 | page_do_bit17_swizzling); |
d174bd64 | 1369 | if (page_do_bit17_swizzling) |
fe115628 CW |
1370 | ret = __copy_from_user_swizzled(vaddr, offset, user_data, |
1371 | length); | |
d174bd64 | 1372 | else |
fe115628 | 1373 | ret = __copy_from_user(vaddr + offset, user_data, length); |
d174bd64 | 1374 | if (needs_clflush_after) |
fe115628 | 1375 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1376 | page_do_bit17_swizzling); |
d174bd64 | 1377 | kunmap(page); |
40123c1f | 1378 | |
755d2218 | 1379 | return ret ? -EFAULT : 0; |
40123c1f EA |
1380 | } |
1381 | ||
fe115628 CW |
1382 | /* Per-page copy function for the shmem pwrite fastpath. |
1383 | * Flushes invalid cachelines before writing to the target if | |
1384 | * needs_clflush_before is set and flushes out any written cachelines after | |
1385 | * writing if needs_clflush is set. | |
1386 | */ | |
40123c1f | 1387 | static int |
fe115628 CW |
1388 | shmem_pwrite(struct page *page, int offset, int len, char __user *user_data, |
1389 | bool page_do_bit17_swizzling, | |
1390 | bool needs_clflush_before, | |
1391 | bool needs_clflush_after) | |
40123c1f | 1392 | { |
fe115628 CW |
1393 | int ret; |
1394 | ||
1395 | ret = -ENODEV; | |
1396 | if (!page_do_bit17_swizzling) { | |
1397 | char *vaddr = kmap_atomic(page); | |
1398 | ||
1399 | if (needs_clflush_before) | |
1400 | drm_clflush_virt_range(vaddr + offset, len); | |
1401 | ret = __copy_from_user_inatomic(vaddr + offset, user_data, len); | |
1402 | if (needs_clflush_after) | |
1403 | drm_clflush_virt_range(vaddr + offset, len); | |
1404 | ||
1405 | kunmap_atomic(vaddr); | |
1406 | } | |
1407 | if (ret == 0) | |
1408 | return ret; | |
1409 | ||
1410 | return shmem_pwrite_slow(page, offset, len, user_data, | |
1411 | page_do_bit17_swizzling, | |
1412 | needs_clflush_before, | |
1413 | needs_clflush_after); | |
1414 | } | |
1415 | ||
1416 | static int | |
1417 | i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, | |
1418 | const struct drm_i915_gem_pwrite *args) | |
1419 | { | |
1420 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
1421 | void __user *user_data; | |
1422 | u64 remain; | |
1423 | unsigned int obj_do_bit17_swizzling; | |
1424 | unsigned int partial_cacheline_write; | |
43394c7d | 1425 | unsigned int needs_clflush; |
fe115628 CW |
1426 | unsigned int offset, idx; |
1427 | int ret; | |
40123c1f | 1428 | |
fe115628 | 1429 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
755d2218 CW |
1430 | if (ret) |
1431 | return ret; | |
1432 | ||
fe115628 CW |
1433 | ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); |
1434 | mutex_unlock(&i915->drm.struct_mutex); | |
1435 | if (ret) | |
1436 | return ret; | |
673a394b | 1437 | |
fe115628 CW |
1438 | obj_do_bit17_swizzling = 0; |
1439 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
1440 | obj_do_bit17_swizzling = BIT(17); | |
e5281ccd | 1441 | |
fe115628 CW |
1442 | /* If we don't overwrite a cacheline completely we need to be |
1443 | * careful to have up-to-date data by first clflushing. Don't | |
1444 | * overcomplicate things and flush the entire patch. | |
1445 | */ | |
1446 | partial_cacheline_write = 0; | |
1447 | if (needs_clflush & CLFLUSH_BEFORE) | |
1448 | partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1; | |
9da3da66 | 1449 | |
fe115628 CW |
1450 | user_data = u64_to_user_ptr(args->data_ptr); |
1451 | remain = args->size; | |
1452 | offset = offset_in_page(args->offset); | |
1453 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
1454 | struct page *page = i915_gem_object_get_page(obj, idx); | |
1455 | int length; | |
40123c1f | 1456 | |
fe115628 CW |
1457 | length = remain; |
1458 | if (offset + length > PAGE_SIZE) | |
1459 | length = PAGE_SIZE - offset; | |
755d2218 | 1460 | |
fe115628 CW |
1461 | ret = shmem_pwrite(page, offset, length, user_data, |
1462 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1463 | (offset | length) & partial_cacheline_write, | |
1464 | needs_clflush & CLFLUSH_AFTER); | |
755d2218 | 1465 | if (ret) |
fe115628 | 1466 | break; |
755d2218 | 1467 | |
fe115628 CW |
1468 | remain -= length; |
1469 | user_data += length; | |
1470 | offset = 0; | |
8c59967c | 1471 | } |
673a394b | 1472 | |
d59b21ec | 1473 | intel_fb_obj_flush(obj, ORIGIN_CPU); |
fe115628 | 1474 | i915_gem_obj_finish_shmem_access(obj); |
40123c1f | 1475 | return ret; |
673a394b EA |
1476 | } |
1477 | ||
1478 | /** | |
1479 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1480 | * @dev: drm device |
1481 | * @data: ioctl data blob | |
1482 | * @file: drm file | |
673a394b EA |
1483 | * |
1484 | * On error, the contents of the buffer that were to be modified are undefined. | |
1485 | */ | |
1486 | int | |
1487 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1488 | struct drm_file *file) |
673a394b EA |
1489 | { |
1490 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1491 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1492 | int ret; |
1493 | ||
1494 | if (args->size == 0) | |
1495 | return 0; | |
1496 | ||
1497 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1498 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1499 | args->size)) |
1500 | return -EFAULT; | |
1501 | ||
03ac0642 | 1502 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1503 | if (!obj) |
1504 | return -ENOENT; | |
673a394b | 1505 | |
7dcd2499 | 1506 | /* Bounds check destination. */ |
966d5bf5 | 1507 | if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { |
ce9d419d | 1508 | ret = -EINVAL; |
258a5ede | 1509 | goto err; |
ce9d419d CW |
1510 | } |
1511 | ||
db53a302 CW |
1512 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1513 | ||
7c55e2c5 CW |
1514 | ret = -ENODEV; |
1515 | if (obj->ops->pwrite) | |
1516 | ret = obj->ops->pwrite(obj, args); | |
1517 | if (ret != -ENODEV) | |
1518 | goto err; | |
1519 | ||
e95433c7 CW |
1520 | ret = i915_gem_object_wait(obj, |
1521 | I915_WAIT_INTERRUPTIBLE | | |
1522 | I915_WAIT_ALL, | |
1523 | MAX_SCHEDULE_TIMEOUT, | |
1524 | to_rps_client(file)); | |
258a5ede CW |
1525 | if (ret) |
1526 | goto err; | |
1527 | ||
fe115628 | 1528 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1529 | if (ret) |
fe115628 | 1530 | goto err; |
258a5ede | 1531 | |
935aaa69 | 1532 | ret = -EFAULT; |
673a394b EA |
1533 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1534 | * it would end up going through the fenced access, and we'll get | |
1535 | * different detiling behavior between reading and writing. | |
1536 | * pread/pwrite currently are reading and writing from the CPU | |
1537 | * perspective, requiring manual detiling by the client. | |
1538 | */ | |
6eae0059 | 1539 | if (!i915_gem_object_has_struct_page(obj) || |
9c870d03 | 1540 | cpu_write_needs_clflush(obj)) |
935aaa69 DV |
1541 | /* Note that the gtt paths might fail with non-page-backed user |
1542 | * pointers (e.g. gtt mappings when moving data between | |
9c870d03 CW |
1543 | * textures). Fallback to the shmem path in that case. |
1544 | */ | |
fe115628 | 1545 | ret = i915_gem_gtt_pwrite_fast(obj, args); |
673a394b | 1546 | |
d1054ee4 | 1547 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1548 | if (obj->phys_handle) |
1549 | ret = i915_gem_phys_pwrite(obj, args, file); | |
b50a5371 | 1550 | else |
fe115628 | 1551 | ret = i915_gem_shmem_pwrite(obj, args); |
6a2c4232 | 1552 | } |
5c0480f2 | 1553 | |
fe115628 | 1554 | i915_gem_object_unpin_pages(obj); |
258a5ede | 1555 | err: |
f0cd5182 | 1556 | i915_gem_object_put(obj); |
258a5ede | 1557 | return ret; |
673a394b EA |
1558 | } |
1559 | ||
40e62d5d CW |
1560 | static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj) |
1561 | { | |
1562 | struct drm_i915_private *i915; | |
1563 | struct list_head *list; | |
1564 | struct i915_vma *vma; | |
1565 | ||
1566 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
1567 | if (!i915_vma_is_ggtt(vma)) | |
28f412e0 | 1568 | break; |
40e62d5d CW |
1569 | |
1570 | if (i915_vma_is_active(vma)) | |
1571 | continue; | |
1572 | ||
1573 | if (!drm_mm_node_allocated(&vma->node)) | |
1574 | continue; | |
1575 | ||
1576 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
1577 | } | |
1578 | ||
1579 | i915 = to_i915(obj->base.dev); | |
1580 | list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list; | |
56cea323 | 1581 | list_move_tail(&obj->global_link, list); |
40e62d5d CW |
1582 | } |
1583 | ||
673a394b | 1584 | /** |
2ef7eeaa EA |
1585 | * Called when user space prepares to use an object with the CPU, either |
1586 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1587 | * @dev: drm device |
1588 | * @data: ioctl data blob | |
1589 | * @file: drm file | |
673a394b EA |
1590 | */ |
1591 | int | |
1592 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1593 | struct drm_file *file) |
673a394b EA |
1594 | { |
1595 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1596 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1597 | uint32_t read_domains = args->read_domains; |
1598 | uint32_t write_domain = args->write_domain; | |
40e62d5d | 1599 | int err; |
673a394b | 1600 | |
2ef7eeaa | 1601 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1602 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1603 | return -EINVAL; |
1604 | ||
1605 | /* Having something in the write domain implies it's in the read | |
1606 | * domain, and only that read domain. Enforce that in the request. | |
1607 | */ | |
1608 | if (write_domain != 0 && read_domains != write_domain) | |
1609 | return -EINVAL; | |
1610 | ||
03ac0642 | 1611 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1612 | if (!obj) |
1613 | return -ENOENT; | |
673a394b | 1614 | |
3236f57a CW |
1615 | /* Try to flush the object off the GPU without holding the lock. |
1616 | * We will repeat the flush holding the lock in the normal manner | |
1617 | * to catch cases where we are gazumped. | |
1618 | */ | |
40e62d5d | 1619 | err = i915_gem_object_wait(obj, |
e95433c7 CW |
1620 | I915_WAIT_INTERRUPTIBLE | |
1621 | (write_domain ? I915_WAIT_ALL : 0), | |
1622 | MAX_SCHEDULE_TIMEOUT, | |
1623 | to_rps_client(file)); | |
40e62d5d | 1624 | if (err) |
f0cd5182 | 1625 | goto out; |
b8f9096d | 1626 | |
40e62d5d CW |
1627 | /* Flush and acquire obj->pages so that we are coherent through |
1628 | * direct access in memory with previous cached writes through | |
1629 | * shmemfs and that our cache domain tracking remains valid. | |
1630 | * For example, if the obj->filp was moved to swap without us | |
1631 | * being notified and releasing the pages, we would mistakenly | |
1632 | * continue to assume that the obj remained out of the CPU cached | |
1633 | * domain. | |
1634 | */ | |
1635 | err = i915_gem_object_pin_pages(obj); | |
1636 | if (err) | |
f0cd5182 | 1637 | goto out; |
40e62d5d CW |
1638 | |
1639 | err = i915_mutex_lock_interruptible(dev); | |
1640 | if (err) | |
f0cd5182 | 1641 | goto out_unpin; |
3236f57a | 1642 | |
e22d8e3c CW |
1643 | if (read_domains & I915_GEM_DOMAIN_WC) |
1644 | err = i915_gem_object_set_to_wc_domain(obj, write_domain); | |
1645 | else if (read_domains & I915_GEM_DOMAIN_GTT) | |
1646 | err = i915_gem_object_set_to_gtt_domain(obj, write_domain); | |
43566ded | 1647 | else |
e22d8e3c | 1648 | err = i915_gem_object_set_to_cpu_domain(obj, write_domain); |
2ef7eeaa | 1649 | |
40e62d5d CW |
1650 | /* And bump the LRU for this access */ |
1651 | i915_gem_object_bump_inactive_ggtt(obj); | |
031b698a | 1652 | |
673a394b | 1653 | mutex_unlock(&dev->struct_mutex); |
b8f9096d | 1654 | |
40e62d5d | 1655 | if (write_domain != 0) |
ef74921b CW |
1656 | intel_fb_obj_invalidate(obj, |
1657 | fb_write_origin(obj, write_domain)); | |
40e62d5d | 1658 | |
f0cd5182 | 1659 | out_unpin: |
40e62d5d | 1660 | i915_gem_object_unpin_pages(obj); |
f0cd5182 CW |
1661 | out: |
1662 | i915_gem_object_put(obj); | |
40e62d5d | 1663 | return err; |
673a394b EA |
1664 | } |
1665 | ||
1666 | /** | |
1667 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1668 | * @dev: drm device |
1669 | * @data: ioctl data blob | |
1670 | * @file: drm file | |
673a394b EA |
1671 | */ |
1672 | int | |
1673 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1674 | struct drm_file *file) |
673a394b EA |
1675 | { |
1676 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1677 | struct drm_i915_gem_object *obj; |
1d7cfea1 | 1678 | |
03ac0642 | 1679 | obj = i915_gem_object_lookup(file, args->handle); |
c21724cc CW |
1680 | if (!obj) |
1681 | return -ENOENT; | |
673a394b | 1682 | |
673a394b | 1683 | /* Pinned buffers may be scanout, so flush the cache */ |
5a97bcc6 | 1684 | i915_gem_object_flush_if_display(obj); |
f0cd5182 | 1685 | i915_gem_object_put(obj); |
5a97bcc6 CW |
1686 | |
1687 | return 0; | |
673a394b EA |
1688 | } |
1689 | ||
1690 | /** | |
14bb2c11 TU |
1691 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1692 | * it is mapped to. | |
1693 | * @dev: drm device | |
1694 | * @data: ioctl data blob | |
1695 | * @file: drm file | |
673a394b EA |
1696 | * |
1697 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1698 | * imply a ref on the object itself. | |
34367381 DV |
1699 | * |
1700 | * IMPORTANT: | |
1701 | * | |
1702 | * DRM driver writers who look a this function as an example for how to do GEM | |
1703 | * mmap support, please don't implement mmap support like here. The modern way | |
1704 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1705 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1706 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1707 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1708 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1709 | */ |
1710 | int | |
1711 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1712 | struct drm_file *file) |
673a394b EA |
1713 | { |
1714 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1715 | struct drm_i915_gem_object *obj; |
673a394b EA |
1716 | unsigned long addr; |
1717 | ||
1816f923 AG |
1718 | if (args->flags & ~(I915_MMAP_WC)) |
1719 | return -EINVAL; | |
1720 | ||
568a58e5 | 1721 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1722 | return -ENODEV; |
1723 | ||
03ac0642 CW |
1724 | obj = i915_gem_object_lookup(file, args->handle); |
1725 | if (!obj) | |
bf79cb91 | 1726 | return -ENOENT; |
673a394b | 1727 | |
1286ff73 DV |
1728 | /* prime objects have no backing filp to GEM mmap |
1729 | * pages from. | |
1730 | */ | |
03ac0642 | 1731 | if (!obj->base.filp) { |
f0cd5182 | 1732 | i915_gem_object_put(obj); |
1286ff73 DV |
1733 | return -EINVAL; |
1734 | } | |
1735 | ||
03ac0642 | 1736 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1737 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1738 | args->offset); | |
1816f923 AG |
1739 | if (args->flags & I915_MMAP_WC) { |
1740 | struct mm_struct *mm = current->mm; | |
1741 | struct vm_area_struct *vma; | |
1742 | ||
80a89a5e | 1743 | if (down_write_killable(&mm->mmap_sem)) { |
f0cd5182 | 1744 | i915_gem_object_put(obj); |
80a89a5e MH |
1745 | return -EINTR; |
1746 | } | |
1816f923 AG |
1747 | vma = find_vma(mm, addr); |
1748 | if (vma) | |
1749 | vma->vm_page_prot = | |
1750 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1751 | else | |
1752 | addr = -ENOMEM; | |
1753 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1754 | |
1755 | /* This may race, but that's ok, it only gets set */ | |
50349247 | 1756 | WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU); |
1816f923 | 1757 | } |
f0cd5182 | 1758 | i915_gem_object_put(obj); |
673a394b EA |
1759 | if (IS_ERR((void *)addr)) |
1760 | return addr; | |
1761 | ||
1762 | args->addr_ptr = (uint64_t) addr; | |
1763 | ||
1764 | return 0; | |
1765 | } | |
1766 | ||
03af84fe CW |
1767 | static unsigned int tile_row_pages(struct drm_i915_gem_object *obj) |
1768 | { | |
6649a0b6 | 1769 | return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT; |
03af84fe CW |
1770 | } |
1771 | ||
4cc69075 CW |
1772 | /** |
1773 | * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps | |
1774 | * | |
1775 | * A history of the GTT mmap interface: | |
1776 | * | |
1777 | * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to | |
1778 | * aligned and suitable for fencing, and still fit into the available | |
1779 | * mappable space left by the pinned display objects. A classic problem | |
1780 | * we called the page-fault-of-doom where we would ping-pong between | |
1781 | * two objects that could not fit inside the GTT and so the memcpy | |
1782 | * would page one object in at the expense of the other between every | |
1783 | * single byte. | |
1784 | * | |
1785 | * 1 - Objects can be any size, and have any compatible fencing (X Y, or none | |
1786 | * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the | |
1787 | * object is too large for the available space (or simply too large | |
1788 | * for the mappable aperture!), a view is created instead and faulted | |
1789 | * into userspace. (This view is aligned and sized appropriately for | |
1790 | * fenced access.) | |
1791 | * | |
e22d8e3c CW |
1792 | * 2 - Recognise WC as a separate cache domain so that we can flush the |
1793 | * delayed writes via GTT before performing direct access via WC. | |
1794 | * | |
4cc69075 CW |
1795 | * Restrictions: |
1796 | * | |
1797 | * * snoopable objects cannot be accessed via the GTT. It can cause machine | |
1798 | * hangs on some architectures, corruption on others. An attempt to service | |
1799 | * a GTT page fault from a snoopable object will generate a SIGBUS. | |
1800 | * | |
1801 | * * the object must be able to fit into RAM (physical memory, though no | |
1802 | * limited to the mappable aperture). | |
1803 | * | |
1804 | * | |
1805 | * Caveats: | |
1806 | * | |
1807 | * * a new GTT page fault will synchronize rendering from the GPU and flush | |
1808 | * all data to system memory. Subsequent access will not be synchronized. | |
1809 | * | |
1810 | * * all mappings are revoked on runtime device suspend. | |
1811 | * | |
1812 | * * there are only 8, 16 or 32 fence registers to share between all users | |
1813 | * (older machines require fence register for display and blitter access | |
1814 | * as well). Contention of the fence registers will cause the previous users | |
1815 | * to be unmapped and any new access will generate new page faults. | |
1816 | * | |
1817 | * * running out of memory while servicing a fault may generate a SIGBUS, | |
1818 | * rather than the expected SIGSEGV. | |
1819 | */ | |
1820 | int i915_gem_mmap_gtt_version(void) | |
1821 | { | |
e22d8e3c | 1822 | return 2; |
4cc69075 CW |
1823 | } |
1824 | ||
2d4281bb CW |
1825 | static inline struct i915_ggtt_view |
1826 | compute_partial_view(struct drm_i915_gem_object *obj, | |
2d4281bb CW |
1827 | pgoff_t page_offset, |
1828 | unsigned int chunk) | |
1829 | { | |
1830 | struct i915_ggtt_view view; | |
1831 | ||
1832 | if (i915_gem_object_is_tiled(obj)) | |
1833 | chunk = roundup(chunk, tile_row_pages(obj)); | |
1834 | ||
2d4281bb | 1835 | view.type = I915_GGTT_VIEW_PARTIAL; |
8bab1193 CW |
1836 | view.partial.offset = rounddown(page_offset, chunk); |
1837 | view.partial.size = | |
2d4281bb | 1838 | min_t(unsigned int, chunk, |
8bab1193 | 1839 | (obj->base.size >> PAGE_SHIFT) - view.partial.offset); |
2d4281bb CW |
1840 | |
1841 | /* If the partial covers the entire object, just create a normal VMA. */ | |
1842 | if (chunk >= obj->base.size >> PAGE_SHIFT) | |
1843 | view.type = I915_GGTT_VIEW_NORMAL; | |
1844 | ||
1845 | return view; | |
1846 | } | |
1847 | ||
de151cf6 JB |
1848 | /** |
1849 | * i915_gem_fault - fault a page into the GTT | |
d9072a3e | 1850 | * @vmf: fault info |
de151cf6 JB |
1851 | * |
1852 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1853 | * from userspace. The fault handler takes care of binding the object to | |
1854 | * the GTT (if needed), allocating and programming a fence register (again, | |
1855 | * only if needed based on whether the old reg is still valid or the object | |
1856 | * is tiled) and inserting a new PTE into the faulting process. | |
1857 | * | |
1858 | * Note that the faulting process may involve evicting existing objects | |
1859 | * from the GTT and/or fence registers to make room. So performance may | |
1860 | * suffer if the GTT working set is large or there are few fence registers | |
1861 | * left. | |
4cc69075 CW |
1862 | * |
1863 | * The current feature set supported by i915_gem_fault() and thus GTT mmaps | |
1864 | * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version). | |
de151cf6 | 1865 | */ |
11bac800 | 1866 | int i915_gem_fault(struct vm_fault *vmf) |
de151cf6 | 1867 | { |
03af84fe | 1868 | #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */ |
11bac800 | 1869 | struct vm_area_struct *area = vmf->vma; |
058d88c4 | 1870 | struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data); |
05394f39 | 1871 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
1872 | struct drm_i915_private *dev_priv = to_i915(dev); |
1873 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b8f9096d | 1874 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
058d88c4 | 1875 | struct i915_vma *vma; |
de151cf6 | 1876 | pgoff_t page_offset; |
82118877 | 1877 | unsigned int flags; |
b8f9096d | 1878 | int ret; |
f65c9168 | 1879 | |
de151cf6 | 1880 | /* We don't use vmf->pgoff since that has the fake offset */ |
1a29d85e | 1881 | page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT; |
de151cf6 | 1882 | |
db53a302 CW |
1883 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1884 | ||
6e4930f6 | 1885 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 1886 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
1887 | * repeat the flush holding the lock in the normal manner to catch cases |
1888 | * where we are gazumped. | |
1889 | */ | |
e95433c7 CW |
1890 | ret = i915_gem_object_wait(obj, |
1891 | I915_WAIT_INTERRUPTIBLE, | |
1892 | MAX_SCHEDULE_TIMEOUT, | |
1893 | NULL); | |
6e4930f6 | 1894 | if (ret) |
b8f9096d CW |
1895 | goto err; |
1896 | ||
40e62d5d CW |
1897 | ret = i915_gem_object_pin_pages(obj); |
1898 | if (ret) | |
1899 | goto err; | |
1900 | ||
b8f9096d CW |
1901 | intel_runtime_pm_get(dev_priv); |
1902 | ||
1903 | ret = i915_mutex_lock_interruptible(dev); | |
1904 | if (ret) | |
1905 | goto err_rpm; | |
6e4930f6 | 1906 | |
eb119bd6 | 1907 | /* Access to snoopable pages through the GTT is incoherent. */ |
0031fb96 | 1908 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) { |
ddeff6ee | 1909 | ret = -EFAULT; |
b8f9096d | 1910 | goto err_unlock; |
eb119bd6 CW |
1911 | } |
1912 | ||
82118877 CW |
1913 | /* If the object is smaller than a couple of partial vma, it is |
1914 | * not worth only creating a single partial vma - we may as well | |
1915 | * clear enough space for the full object. | |
1916 | */ | |
1917 | flags = PIN_MAPPABLE; | |
1918 | if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT) | |
1919 | flags |= PIN_NONBLOCK | PIN_NONFAULT; | |
1920 | ||
a61007a8 | 1921 | /* Now pin it into the GTT as needed */ |
82118877 | 1922 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags); |
a61007a8 | 1923 | if (IS_ERR(vma)) { |
a61007a8 | 1924 | /* Use a partial view if it is bigger than available space */ |
2d4281bb | 1925 | struct i915_ggtt_view view = |
8201c1fa | 1926 | compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES); |
aa136d9d | 1927 | |
50349247 CW |
1928 | /* Userspace is now writing through an untracked VMA, abandon |
1929 | * all hope that the hardware is able to track future writes. | |
1930 | */ | |
1931 | obj->frontbuffer_ggtt_origin = ORIGIN_CPU; | |
1932 | ||
a61007a8 CW |
1933 | vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
1934 | } | |
058d88c4 CW |
1935 | if (IS_ERR(vma)) { |
1936 | ret = PTR_ERR(vma); | |
b8f9096d | 1937 | goto err_unlock; |
058d88c4 | 1938 | } |
4a684a41 | 1939 | |
c9839303 CW |
1940 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1941 | if (ret) | |
b8f9096d | 1942 | goto err_unpin; |
74898d7e | 1943 | |
49ef5294 | 1944 | ret = i915_vma_get_fence(vma); |
d9e86c0e | 1945 | if (ret) |
b8f9096d | 1946 | goto err_unpin; |
7d1c4804 | 1947 | |
275f039d | 1948 | /* Mark as being mmapped into userspace for later revocation */ |
9c870d03 | 1949 | assert_rpm_wakelock_held(dev_priv); |
275f039d CW |
1950 | if (list_empty(&obj->userfault_link)) |
1951 | list_add(&obj->userfault_link, &dev_priv->mm.userfault_list); | |
275f039d | 1952 | |
b90b91d8 | 1953 | /* Finally, remap it using the new GTT offset */ |
c58305af | 1954 | ret = remap_io_mapping(area, |
8bab1193 | 1955 | area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT), |
c58305af CW |
1956 | (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT, |
1957 | min_t(u64, vma->size, area->vm_end - area->vm_start), | |
1958 | &ggtt->mappable); | |
a61007a8 | 1959 | |
b8f9096d | 1960 | err_unpin: |
058d88c4 | 1961 | __i915_vma_unpin(vma); |
b8f9096d | 1962 | err_unlock: |
de151cf6 | 1963 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
1964 | err_rpm: |
1965 | intel_runtime_pm_put(dev_priv); | |
40e62d5d | 1966 | i915_gem_object_unpin_pages(obj); |
b8f9096d | 1967 | err: |
de151cf6 | 1968 | switch (ret) { |
d9bc7e9f | 1969 | case -EIO: |
2232f031 DV |
1970 | /* |
1971 | * We eat errors when the gpu is terminally wedged to avoid | |
1972 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1973 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1974 | * and so needs to be reported. | |
1975 | */ | |
1976 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1977 | ret = VM_FAULT_SIGBUS; |
1978 | break; | |
1979 | } | |
045e769a | 1980 | case -EAGAIN: |
571c608d DV |
1981 | /* |
1982 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1983 | * handler to reset everything when re-faulting in | |
1984 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1985 | */ |
c715089f CW |
1986 | case 0: |
1987 | case -ERESTARTSYS: | |
bed636ab | 1988 | case -EINTR: |
e79e0fe3 DR |
1989 | case -EBUSY: |
1990 | /* | |
1991 | * EBUSY is ok: this just means that another thread | |
1992 | * already did the job. | |
1993 | */ | |
f65c9168 PZ |
1994 | ret = VM_FAULT_NOPAGE; |
1995 | break; | |
de151cf6 | 1996 | case -ENOMEM: |
f65c9168 PZ |
1997 | ret = VM_FAULT_OOM; |
1998 | break; | |
a7c2e1aa | 1999 | case -ENOSPC: |
45d67817 | 2000 | case -EFAULT: |
f65c9168 PZ |
2001 | ret = VM_FAULT_SIGBUS; |
2002 | break; | |
de151cf6 | 2003 | default: |
a7c2e1aa | 2004 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
2005 | ret = VM_FAULT_SIGBUS; |
2006 | break; | |
de151cf6 | 2007 | } |
f65c9168 | 2008 | return ret; |
de151cf6 JB |
2009 | } |
2010 | ||
901782b2 CW |
2011 | /** |
2012 | * i915_gem_release_mmap - remove physical page mappings | |
2013 | * @obj: obj in question | |
2014 | * | |
af901ca1 | 2015 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
2016 | * relinquish ownership of the pages back to the system. |
2017 | * | |
2018 | * It is vital that we remove the page mapping if we have mapped a tiled | |
2019 | * object through the GTT and then lose the fence register due to | |
2020 | * resource pressure. Similarly if the object has been moved out of the | |
2021 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
2022 | * mapping will then trigger a page fault on the next user access, allowing | |
2023 | * fixup by i915_gem_fault(). | |
2024 | */ | |
d05ca301 | 2025 | void |
05394f39 | 2026 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 2027 | { |
275f039d | 2028 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
275f039d | 2029 | |
349f2ccf CW |
2030 | /* Serialisation between user GTT access and our code depends upon |
2031 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
2032 | * pagefault then has to wait until we release the mutex. | |
9c870d03 CW |
2033 | * |
2034 | * Note that RPM complicates somewhat by adding an additional | |
2035 | * requirement that operations to the GGTT be made holding the RPM | |
2036 | * wakeref. | |
349f2ccf | 2037 | */ |
275f039d | 2038 | lockdep_assert_held(&i915->drm.struct_mutex); |
9c870d03 | 2039 | intel_runtime_pm_get(i915); |
349f2ccf | 2040 | |
3594a3e2 | 2041 | if (list_empty(&obj->userfault_link)) |
9c870d03 | 2042 | goto out; |
901782b2 | 2043 | |
3594a3e2 | 2044 | list_del_init(&obj->userfault_link); |
6796cb16 DR |
2045 | drm_vma_node_unmap(&obj->base.vma_node, |
2046 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
2047 | |
2048 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
2049 | * memory transactions from userspace before we return. The TLB | |
2050 | * flushing implied above by changing the PTE above *should* be | |
2051 | * sufficient, an extra barrier here just provides us with a bit | |
2052 | * of paranoid documentation about our requirement to serialise | |
2053 | * memory writes before touching registers / GSM. | |
2054 | */ | |
2055 | wmb(); | |
9c870d03 CW |
2056 | |
2057 | out: | |
2058 | intel_runtime_pm_put(i915); | |
901782b2 CW |
2059 | } |
2060 | ||
7c108fd8 | 2061 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) |
eedd10f4 | 2062 | { |
3594a3e2 | 2063 | struct drm_i915_gem_object *obj, *on; |
7c108fd8 | 2064 | int i; |
eedd10f4 | 2065 | |
3594a3e2 CW |
2066 | /* |
2067 | * Only called during RPM suspend. All users of the userfault_list | |
2068 | * must be holding an RPM wakeref to ensure that this can not | |
2069 | * run concurrently with themselves (and use the struct_mutex for | |
2070 | * protection between themselves). | |
2071 | */ | |
275f039d | 2072 | |
3594a3e2 CW |
2073 | list_for_each_entry_safe(obj, on, |
2074 | &dev_priv->mm.userfault_list, userfault_link) { | |
2075 | list_del_init(&obj->userfault_link); | |
275f039d CW |
2076 | drm_vma_node_unmap(&obj->base.vma_node, |
2077 | obj->base.dev->anon_inode->i_mapping); | |
275f039d | 2078 | } |
7c108fd8 CW |
2079 | |
2080 | /* The fence will be lost when the device powers down. If any were | |
2081 | * in use by hardware (i.e. they are pinned), we should not be powering | |
2082 | * down! All other fences will be reacquired by the user upon waking. | |
2083 | */ | |
2084 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
2085 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
2086 | ||
e0ec3ec6 CW |
2087 | /* Ideally we want to assert that the fence register is not |
2088 | * live at this point (i.e. that no piece of code will be | |
2089 | * trying to write through fence + GTT, as that both violates | |
2090 | * our tracking of activity and associated locking/barriers, | |
2091 | * but also is illegal given that the hw is powered down). | |
2092 | * | |
2093 | * Previously we used reg->pin_count as a "liveness" indicator. | |
2094 | * That is not sufficient, and we need a more fine-grained | |
2095 | * tool if we want to have a sanity check here. | |
2096 | */ | |
7c108fd8 CW |
2097 | |
2098 | if (!reg->vma) | |
2099 | continue; | |
2100 | ||
2101 | GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link)); | |
2102 | reg->dirty = true; | |
2103 | } | |
eedd10f4 CW |
2104 | } |
2105 | ||
d8cb5086 CW |
2106 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2107 | { | |
fac5e23e | 2108 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 2109 | int err; |
da494d7c | 2110 | |
f3f6184c | 2111 | err = drm_gem_create_mmap_offset(&obj->base); |
b42a13d9 | 2112 | if (likely(!err)) |
f3f6184c | 2113 | return 0; |
d8cb5086 | 2114 | |
b42a13d9 CW |
2115 | /* Attempt to reap some mmap space from dead objects */ |
2116 | do { | |
2117 | err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE); | |
2118 | if (err) | |
2119 | break; | |
f3f6184c | 2120 | |
b42a13d9 | 2121 | i915_gem_drain_freed_objects(dev_priv); |
f3f6184c | 2122 | err = drm_gem_create_mmap_offset(&obj->base); |
b42a13d9 CW |
2123 | if (!err) |
2124 | break; | |
2125 | ||
2126 | } while (flush_delayed_work(&dev_priv->gt.retire_work)); | |
da494d7c | 2127 | |
f3f6184c | 2128 | return err; |
d8cb5086 CW |
2129 | } |
2130 | ||
2131 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2132 | { | |
d8cb5086 CW |
2133 | drm_gem_free_mmap_offset(&obj->base); |
2134 | } | |
2135 | ||
da6b51d0 | 2136 | int |
ff72145b DA |
2137 | i915_gem_mmap_gtt(struct drm_file *file, |
2138 | struct drm_device *dev, | |
da6b51d0 | 2139 | uint32_t handle, |
ff72145b | 2140 | uint64_t *offset) |
de151cf6 | 2141 | { |
05394f39 | 2142 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2143 | int ret; |
2144 | ||
03ac0642 | 2145 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
2146 | if (!obj) |
2147 | return -ENOENT; | |
ab18282d | 2148 | |
d8cb5086 | 2149 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
2150 | if (ret == 0) |
2151 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 2152 | |
f0cd5182 | 2153 | i915_gem_object_put(obj); |
1d7cfea1 | 2154 | return ret; |
de151cf6 JB |
2155 | } |
2156 | ||
ff72145b DA |
2157 | /** |
2158 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2159 | * @dev: DRM device | |
2160 | * @data: GTT mapping ioctl data | |
2161 | * @file: GEM object info | |
2162 | * | |
2163 | * Simply returns the fake offset to userspace so it can mmap it. | |
2164 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2165 | * up so we can get faults in the handler above. | |
2166 | * | |
2167 | * The fault handler will take care of binding the object into the GTT | |
2168 | * (since it may have been evicted to make room for something), allocating | |
2169 | * a fence register, and mapping the appropriate aperture address into | |
2170 | * userspace. | |
2171 | */ | |
2172 | int | |
2173 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2174 | struct drm_file *file) | |
2175 | { | |
2176 | struct drm_i915_gem_mmap_gtt *args = data; | |
2177 | ||
da6b51d0 | 2178 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2179 | } |
2180 | ||
225067ee DV |
2181 | /* Immediately discard the backing storage */ |
2182 | static void | |
2183 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2184 | { |
4d6294bf | 2185 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2186 | |
4d6294bf CW |
2187 | if (obj->base.filp == NULL) |
2188 | return; | |
e5281ccd | 2189 | |
225067ee DV |
2190 | /* Our goal here is to return as much of the memory as |
2191 | * is possible back to the system as we are called from OOM. | |
2192 | * To do this we must instruct the shmfs to drop all of its | |
2193 | * backing pages, *now*. | |
2194 | */ | |
5537252b | 2195 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
a4f5ea64 | 2196 | obj->mm.madv = __I915_MADV_PURGED; |
4e5462ee | 2197 | obj->mm.pages = ERR_PTR(-EFAULT); |
225067ee | 2198 | } |
e5281ccd | 2199 | |
5537252b | 2200 | /* Try to discard unwanted pages */ |
03ac84f1 | 2201 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
225067ee | 2202 | { |
5537252b CW |
2203 | struct address_space *mapping; |
2204 | ||
1233e2db CW |
2205 | lockdep_assert_held(&obj->mm.lock); |
2206 | GEM_BUG_ON(obj->mm.pages); | |
2207 | ||
a4f5ea64 | 2208 | switch (obj->mm.madv) { |
5537252b CW |
2209 | case I915_MADV_DONTNEED: |
2210 | i915_gem_object_truncate(obj); | |
2211 | case __I915_MADV_PURGED: | |
2212 | return; | |
2213 | } | |
2214 | ||
2215 | if (obj->base.filp == NULL) | |
2216 | return; | |
2217 | ||
93c76a3d | 2218 | mapping = obj->base.filp->f_mapping, |
5537252b | 2219 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
e5281ccd CW |
2220 | } |
2221 | ||
5cdf5881 | 2222 | static void |
03ac84f1 CW |
2223 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj, |
2224 | struct sg_table *pages) | |
673a394b | 2225 | { |
85d1225e DG |
2226 | struct sgt_iter sgt_iter; |
2227 | struct page *page; | |
1286ff73 | 2228 | |
e5facdf9 | 2229 | __i915_gem_object_release_shmem(obj, pages, true); |
673a394b | 2230 | |
03ac84f1 | 2231 | i915_gem_gtt_finish_pages(obj, pages); |
e2273302 | 2232 | |
6dacfd2f | 2233 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2234 | i915_gem_object_save_bit_17_swizzle(obj, pages); |
280b713b | 2235 | |
03ac84f1 | 2236 | for_each_sgt_page(page, sgt_iter, pages) { |
a4f5ea64 | 2237 | if (obj->mm.dirty) |
9da3da66 | 2238 | set_page_dirty(page); |
3ef94daa | 2239 | |
a4f5ea64 | 2240 | if (obj->mm.madv == I915_MADV_WILLNEED) |
9da3da66 | 2241 | mark_page_accessed(page); |
3ef94daa | 2242 | |
09cbfeaf | 2243 | put_page(page); |
3ef94daa | 2244 | } |
a4f5ea64 | 2245 | obj->mm.dirty = false; |
673a394b | 2246 | |
03ac84f1 CW |
2247 | sg_free_table(pages); |
2248 | kfree(pages); | |
37e680a1 | 2249 | } |
6c085a72 | 2250 | |
96d77634 CW |
2251 | static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj) |
2252 | { | |
2253 | struct radix_tree_iter iter; | |
2254 | void **slot; | |
2255 | ||
a4f5ea64 CW |
2256 | radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0) |
2257 | radix_tree_delete(&obj->mm.get_page.radix, iter.index); | |
96d77634 CW |
2258 | } |
2259 | ||
548625ee CW |
2260 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, |
2261 | enum i915_mm_subclass subclass) | |
37e680a1 | 2262 | { |
03ac84f1 | 2263 | struct sg_table *pages; |
37e680a1 | 2264 | |
a4f5ea64 | 2265 | if (i915_gem_object_has_pinned_pages(obj)) |
03ac84f1 | 2266 | return; |
a5570178 | 2267 | |
15717de2 | 2268 | GEM_BUG_ON(obj->bind_count); |
1233e2db CW |
2269 | if (!READ_ONCE(obj->mm.pages)) |
2270 | return; | |
2271 | ||
2272 | /* May be called by shrinker from within get_pages() (on another bo) */ | |
548625ee | 2273 | mutex_lock_nested(&obj->mm.lock, subclass); |
1233e2db CW |
2274 | if (unlikely(atomic_read(&obj->mm.pages_pin_count))) |
2275 | goto unlock; | |
3e123027 | 2276 | |
a2165e31 CW |
2277 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2278 | * array, hence protect them from being reaped by removing them from gtt | |
2279 | * lists early. */ | |
03ac84f1 CW |
2280 | pages = fetch_and_zero(&obj->mm.pages); |
2281 | GEM_BUG_ON(!pages); | |
a2165e31 | 2282 | |
a4f5ea64 | 2283 | if (obj->mm.mapping) { |
4b30cb23 CW |
2284 | void *ptr; |
2285 | ||
0ce81788 | 2286 | ptr = page_mask_bits(obj->mm.mapping); |
4b30cb23 CW |
2287 | if (is_vmalloc_addr(ptr)) |
2288 | vunmap(ptr); | |
fb8621d3 | 2289 | else |
4b30cb23 CW |
2290 | kunmap(kmap_to_page(ptr)); |
2291 | ||
a4f5ea64 | 2292 | obj->mm.mapping = NULL; |
0a798eb9 CW |
2293 | } |
2294 | ||
96d77634 CW |
2295 | __i915_gem_object_reset_page_iter(obj); |
2296 | ||
4e5462ee CW |
2297 | if (!IS_ERR(pages)) |
2298 | obj->ops->put_pages(obj, pages); | |
2299 | ||
1233e2db CW |
2300 | unlock: |
2301 | mutex_unlock(&obj->mm.lock); | |
6c085a72 CW |
2302 | } |
2303 | ||
935a2f77 | 2304 | static bool i915_sg_trim(struct sg_table *orig_st) |
0c40ce13 TU |
2305 | { |
2306 | struct sg_table new_st; | |
2307 | struct scatterlist *sg, *new_sg; | |
2308 | unsigned int i; | |
2309 | ||
2310 | if (orig_st->nents == orig_st->orig_nents) | |
935a2f77 | 2311 | return false; |
0c40ce13 | 2312 | |
8bfc478f | 2313 | if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN)) |
935a2f77 | 2314 | return false; |
0c40ce13 TU |
2315 | |
2316 | new_sg = new_st.sgl; | |
2317 | for_each_sg(orig_st->sgl, sg, orig_st->nents, i) { | |
2318 | sg_set_page(new_sg, sg_page(sg), sg->length, 0); | |
2319 | /* called before being DMA mapped, no need to copy sg->dma_* */ | |
2320 | new_sg = sg_next(new_sg); | |
2321 | } | |
c2dc6cc9 | 2322 | GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */ |
0c40ce13 TU |
2323 | |
2324 | sg_free_table(orig_st); | |
2325 | ||
2326 | *orig_st = new_st; | |
935a2f77 | 2327 | return true; |
0c40ce13 TU |
2328 | } |
2329 | ||
03ac84f1 | 2330 | static struct sg_table * |
6c085a72 | 2331 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2332 | { |
fac5e23e | 2333 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d766ef53 CW |
2334 | const unsigned long page_count = obj->base.size / PAGE_SIZE; |
2335 | unsigned long i; | |
e5281ccd | 2336 | struct address_space *mapping; |
9da3da66 CW |
2337 | struct sg_table *st; |
2338 | struct scatterlist *sg; | |
85d1225e | 2339 | struct sgt_iter sgt_iter; |
e5281ccd | 2340 | struct page *page; |
90797e6d | 2341 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
4ff340f0 | 2342 | unsigned int max_segment; |
4846bf0c | 2343 | gfp_t noreclaim; |
e2273302 | 2344 | int ret; |
e5281ccd | 2345 | |
6c085a72 CW |
2346 | /* Assert that the object is not currently in any GPU domain. As it |
2347 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2348 | * a GPU cache | |
2349 | */ | |
03ac84f1 CW |
2350 | GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2351 | GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
6c085a72 | 2352 | |
7453c549 | 2353 | max_segment = swiotlb_max_segment(); |
871dfbd6 | 2354 | if (!max_segment) |
4ff340f0 | 2355 | max_segment = rounddown(UINT_MAX, PAGE_SIZE); |
871dfbd6 | 2356 | |
9da3da66 CW |
2357 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2358 | if (st == NULL) | |
03ac84f1 | 2359 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2360 | |
d766ef53 | 2361 | rebuild_st: |
9da3da66 | 2362 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2363 | kfree(st); |
03ac84f1 | 2364 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2365 | } |
e5281ccd | 2366 | |
9da3da66 CW |
2367 | /* Get the list of pages out of our struct file. They'll be pinned |
2368 | * at this point until we release them. | |
2369 | * | |
2370 | * Fail silently without starting the shrinker | |
2371 | */ | |
93c76a3d | 2372 | mapping = obj->base.filp->f_mapping; |
0f6ab55d | 2373 | noreclaim = mapping_gfp_constraint(mapping, ~__GFP_RECLAIM); |
4846bf0c CW |
2374 | noreclaim |= __GFP_NORETRY | __GFP_NOWARN; |
2375 | ||
90797e6d ID |
2376 | sg = st->sgl; |
2377 | st->nents = 0; | |
2378 | for (i = 0; i < page_count; i++) { | |
4846bf0c CW |
2379 | const unsigned int shrink[] = { |
2380 | I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_PURGEABLE, | |
2381 | 0, | |
2382 | }, *s = shrink; | |
2383 | gfp_t gfp = noreclaim; | |
2384 | ||
2385 | do { | |
6c085a72 | 2386 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
4846bf0c CW |
2387 | if (likely(!IS_ERR(page))) |
2388 | break; | |
2389 | ||
2390 | if (!*s) { | |
2391 | ret = PTR_ERR(page); | |
2392 | goto err_sg; | |
2393 | } | |
2394 | ||
2395 | i915_gem_shrink(dev_priv, 2 * page_count, *s++); | |
2396 | cond_resched(); | |
24f8e00a | 2397 | |
6c085a72 CW |
2398 | /* We've tried hard to allocate the memory by reaping |
2399 | * our own buffer, now let the real VM do its job and | |
2400 | * go down in flames if truly OOM. | |
24f8e00a CW |
2401 | * |
2402 | * However, since graphics tend to be disposable, | |
2403 | * defer the oom here by reporting the ENOMEM back | |
2404 | * to userspace. | |
6c085a72 | 2405 | */ |
4846bf0c CW |
2406 | if (!*s) { |
2407 | /* reclaim and warn, but no oom */ | |
2408 | gfp = mapping_gfp_mask(mapping); | |
eaf41801 CW |
2409 | |
2410 | /* Our bo are always dirty and so we require | |
2411 | * kswapd to reclaim our pages (direct reclaim | |
2412 | * does not effectively begin pageout of our | |
2413 | * buffers on its own). However, direct reclaim | |
2414 | * only waits for kswapd when under allocation | |
2415 | * congestion. So as a result __GFP_RECLAIM is | |
2416 | * unreliable and fails to actually reclaim our | |
2417 | * dirty pages -- unless you try over and over | |
2418 | * again with !__GFP_NORETRY. However, we still | |
2419 | * want to fail this allocation rather than | |
2420 | * trigger the out-of-memory killer and for | |
dbb32956 | 2421 | * this we want __GFP_RETRY_MAYFAIL. |
eaf41801 | 2422 | */ |
dbb32956 | 2423 | gfp |= __GFP_RETRY_MAYFAIL; |
e2273302 | 2424 | } |
4846bf0c CW |
2425 | } while (1); |
2426 | ||
871dfbd6 CW |
2427 | if (!i || |
2428 | sg->length >= max_segment || | |
2429 | page_to_pfn(page) != last_pfn + 1) { | |
90797e6d ID |
2430 | if (i) |
2431 | sg = sg_next(sg); | |
2432 | st->nents++; | |
2433 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2434 | } else { | |
2435 | sg->length += PAGE_SIZE; | |
2436 | } | |
2437 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2438 | |
2439 | /* Check that the i965g/gm workaround works. */ | |
2440 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2441 | } |
871dfbd6 | 2442 | if (sg) /* loop terminated early; short sg table */ |
426729dc | 2443 | sg_mark_end(sg); |
74ce6b6c | 2444 | |
0c40ce13 TU |
2445 | /* Trim unused sg entries to avoid wasting memory. */ |
2446 | i915_sg_trim(st); | |
2447 | ||
03ac84f1 | 2448 | ret = i915_gem_gtt_prepare_pages(obj, st); |
d766ef53 CW |
2449 | if (ret) { |
2450 | /* DMA remapping failed? One possible cause is that | |
2451 | * it could not reserve enough large entries, asking | |
2452 | * for PAGE_SIZE chunks instead may be helpful. | |
2453 | */ | |
2454 | if (max_segment > PAGE_SIZE) { | |
2455 | for_each_sgt_page(page, sgt_iter, st) | |
2456 | put_page(page); | |
2457 | sg_free_table(st); | |
2458 | ||
2459 | max_segment = PAGE_SIZE; | |
2460 | goto rebuild_st; | |
2461 | } else { | |
2462 | dev_warn(&dev_priv->drm.pdev->dev, | |
2463 | "Failed to DMA remap %lu pages\n", | |
2464 | page_count); | |
2465 | goto err_pages; | |
2466 | } | |
2467 | } | |
e2273302 | 2468 | |
6dacfd2f | 2469 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2470 | i915_gem_object_do_bit_17_swizzle(obj, st); |
e5281ccd | 2471 | |
03ac84f1 | 2472 | return st; |
e5281ccd | 2473 | |
b17993b7 | 2474 | err_sg: |
90797e6d | 2475 | sg_mark_end(sg); |
b17993b7 | 2476 | err_pages: |
85d1225e DG |
2477 | for_each_sgt_page(page, sgt_iter, st) |
2478 | put_page(page); | |
9da3da66 CW |
2479 | sg_free_table(st); |
2480 | kfree(st); | |
0820baf3 CW |
2481 | |
2482 | /* shmemfs first checks if there is enough memory to allocate the page | |
2483 | * and reports ENOSPC should there be insufficient, along with the usual | |
2484 | * ENOMEM for a genuine allocation failure. | |
2485 | * | |
2486 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2487 | * space and so want to translate the error from shmemfs back to our | |
2488 | * usual understanding of ENOMEM. | |
2489 | */ | |
e2273302 ID |
2490 | if (ret == -ENOSPC) |
2491 | ret = -ENOMEM; | |
2492 | ||
03ac84f1 CW |
2493 | return ERR_PTR(ret); |
2494 | } | |
2495 | ||
2496 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, | |
2497 | struct sg_table *pages) | |
2498 | { | |
1233e2db | 2499 | lockdep_assert_held(&obj->mm.lock); |
03ac84f1 CW |
2500 | |
2501 | obj->mm.get_page.sg_pos = pages->sgl; | |
2502 | obj->mm.get_page.sg_idx = 0; | |
2503 | ||
2504 | obj->mm.pages = pages; | |
2c3a3f44 CW |
2505 | |
2506 | if (i915_gem_object_is_tiled(obj) && | |
2507 | to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
2508 | GEM_BUG_ON(obj->mm.quirked); | |
2509 | __i915_gem_object_pin_pages(obj); | |
2510 | obj->mm.quirked = true; | |
2511 | } | |
03ac84f1 CW |
2512 | } |
2513 | ||
2514 | static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2515 | { | |
2516 | struct sg_table *pages; | |
2517 | ||
2c3a3f44 CW |
2518 | GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); |
2519 | ||
03ac84f1 CW |
2520 | if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { |
2521 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); | |
2522 | return -EFAULT; | |
2523 | } | |
2524 | ||
2525 | pages = obj->ops->get_pages(obj); | |
2526 | if (unlikely(IS_ERR(pages))) | |
2527 | return PTR_ERR(pages); | |
2528 | ||
2529 | __i915_gem_object_set_pages(obj, pages); | |
2530 | return 0; | |
673a394b EA |
2531 | } |
2532 | ||
37e680a1 | 2533 | /* Ensure that the associated pages are gathered from the backing storage |
1233e2db | 2534 | * and pinned into our object. i915_gem_object_pin_pages() may be called |
37e680a1 | 2535 | * multiple times before they are released by a single call to |
1233e2db | 2536 | * i915_gem_object_unpin_pages() - once the pages are no longer referenced |
37e680a1 CW |
2537 | * either as a result of memory pressure (reaping pages under the shrinker) |
2538 | * or as the object is itself released. | |
2539 | */ | |
a4f5ea64 | 2540 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
37e680a1 | 2541 | { |
03ac84f1 | 2542 | int err; |
37e680a1 | 2543 | |
1233e2db CW |
2544 | err = mutex_lock_interruptible(&obj->mm.lock); |
2545 | if (err) | |
2546 | return err; | |
4c7d62c6 | 2547 | |
4e5462ee | 2548 | if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) { |
2c3a3f44 CW |
2549 | err = ____i915_gem_object_get_pages(obj); |
2550 | if (err) | |
2551 | goto unlock; | |
37e680a1 | 2552 | |
2c3a3f44 CW |
2553 | smp_mb__before_atomic(); |
2554 | } | |
2555 | atomic_inc(&obj->mm.pages_pin_count); | |
ee286370 | 2556 | |
1233e2db CW |
2557 | unlock: |
2558 | mutex_unlock(&obj->mm.lock); | |
03ac84f1 | 2559 | return err; |
673a394b EA |
2560 | } |
2561 | ||
dd6034c6 | 2562 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
d31d7cb1 CW |
2563 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, |
2564 | enum i915_map_type type) | |
dd6034c6 DG |
2565 | { |
2566 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
a4f5ea64 | 2567 | struct sg_table *sgt = obj->mm.pages; |
85d1225e DG |
2568 | struct sgt_iter sgt_iter; |
2569 | struct page *page; | |
b338fa47 DG |
2570 | struct page *stack_pages[32]; |
2571 | struct page **pages = stack_pages; | |
dd6034c6 | 2572 | unsigned long i = 0; |
d31d7cb1 | 2573 | pgprot_t pgprot; |
dd6034c6 DG |
2574 | void *addr; |
2575 | ||
2576 | /* A single page can always be kmapped */ | |
d31d7cb1 | 2577 | if (n_pages == 1 && type == I915_MAP_WB) |
dd6034c6 DG |
2578 | return kmap(sg_page(sgt->sgl)); |
2579 | ||
b338fa47 DG |
2580 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2581 | /* Too big for stack -- allocate temporary array instead */ | |
2098105e | 2582 | pages = kvmalloc_array(n_pages, sizeof(*pages), GFP_TEMPORARY); |
b338fa47 DG |
2583 | if (!pages) |
2584 | return NULL; | |
2585 | } | |
dd6034c6 | 2586 | |
85d1225e DG |
2587 | for_each_sgt_page(page, sgt_iter, sgt) |
2588 | pages[i++] = page; | |
dd6034c6 DG |
2589 | |
2590 | /* Check that we have the expected number of pages */ | |
2591 | GEM_BUG_ON(i != n_pages); | |
2592 | ||
d31d7cb1 CW |
2593 | switch (type) { |
2594 | case I915_MAP_WB: | |
2595 | pgprot = PAGE_KERNEL; | |
2596 | break; | |
2597 | case I915_MAP_WC: | |
2598 | pgprot = pgprot_writecombine(PAGE_KERNEL_IO); | |
2599 | break; | |
2600 | } | |
2601 | addr = vmap(pages, n_pages, 0, pgprot); | |
dd6034c6 | 2602 | |
b338fa47 | 2603 | if (pages != stack_pages) |
2098105e | 2604 | kvfree(pages); |
dd6034c6 DG |
2605 | |
2606 | return addr; | |
2607 | } | |
2608 | ||
2609 | /* get, pin, and map the pages of the object into kernel space */ | |
d31d7cb1 CW |
2610 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
2611 | enum i915_map_type type) | |
0a798eb9 | 2612 | { |
d31d7cb1 CW |
2613 | enum i915_map_type has_type; |
2614 | bool pinned; | |
2615 | void *ptr; | |
0a798eb9 CW |
2616 | int ret; |
2617 | ||
d31d7cb1 | 2618 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); |
0a798eb9 | 2619 | |
1233e2db | 2620 | ret = mutex_lock_interruptible(&obj->mm.lock); |
0a798eb9 CW |
2621 | if (ret) |
2622 | return ERR_PTR(ret); | |
2623 | ||
1233e2db CW |
2624 | pinned = true; |
2625 | if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) { | |
4e5462ee | 2626 | if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) { |
2c3a3f44 CW |
2627 | ret = ____i915_gem_object_get_pages(obj); |
2628 | if (ret) | |
2629 | goto err_unlock; | |
1233e2db | 2630 | |
2c3a3f44 CW |
2631 | smp_mb__before_atomic(); |
2632 | } | |
2633 | atomic_inc(&obj->mm.pages_pin_count); | |
1233e2db CW |
2634 | pinned = false; |
2635 | } | |
2636 | GEM_BUG_ON(!obj->mm.pages); | |
0a798eb9 | 2637 | |
0ce81788 | 2638 | ptr = page_unpack_bits(obj->mm.mapping, &has_type); |
d31d7cb1 CW |
2639 | if (ptr && has_type != type) { |
2640 | if (pinned) { | |
2641 | ret = -EBUSY; | |
1233e2db | 2642 | goto err_unpin; |
0a798eb9 | 2643 | } |
d31d7cb1 CW |
2644 | |
2645 | if (is_vmalloc_addr(ptr)) | |
2646 | vunmap(ptr); | |
2647 | else | |
2648 | kunmap(kmap_to_page(ptr)); | |
2649 | ||
a4f5ea64 | 2650 | ptr = obj->mm.mapping = NULL; |
0a798eb9 CW |
2651 | } |
2652 | ||
d31d7cb1 CW |
2653 | if (!ptr) { |
2654 | ptr = i915_gem_object_map(obj, type); | |
2655 | if (!ptr) { | |
2656 | ret = -ENOMEM; | |
1233e2db | 2657 | goto err_unpin; |
d31d7cb1 CW |
2658 | } |
2659 | ||
0ce81788 | 2660 | obj->mm.mapping = page_pack_bits(ptr, type); |
d31d7cb1 CW |
2661 | } |
2662 | ||
1233e2db CW |
2663 | out_unlock: |
2664 | mutex_unlock(&obj->mm.lock); | |
d31d7cb1 CW |
2665 | return ptr; |
2666 | ||
1233e2db CW |
2667 | err_unpin: |
2668 | atomic_dec(&obj->mm.pages_pin_count); | |
2669 | err_unlock: | |
2670 | ptr = ERR_PTR(ret); | |
2671 | goto out_unlock; | |
0a798eb9 CW |
2672 | } |
2673 | ||
7c55e2c5 CW |
2674 | static int |
2675 | i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj, | |
2676 | const struct drm_i915_gem_pwrite *arg) | |
2677 | { | |
2678 | struct address_space *mapping = obj->base.filp->f_mapping; | |
2679 | char __user *user_data = u64_to_user_ptr(arg->data_ptr); | |
2680 | u64 remain, offset; | |
2681 | unsigned int pg; | |
2682 | ||
2683 | /* Before we instantiate/pin the backing store for our use, we | |
2684 | * can prepopulate the shmemfs filp efficiently using a write into | |
2685 | * the pagecache. We avoid the penalty of instantiating all the | |
2686 | * pages, important if the user is just writing to a few and never | |
2687 | * uses the object on the GPU, and using a direct write into shmemfs | |
2688 | * allows it to avoid the cost of retrieving a page (either swapin | |
2689 | * or clearing-before-use) before it is overwritten. | |
2690 | */ | |
2691 | if (READ_ONCE(obj->mm.pages)) | |
2692 | return -ENODEV; | |
2693 | ||
2694 | /* Before the pages are instantiated the object is treated as being | |
2695 | * in the CPU domain. The pages will be clflushed as required before | |
2696 | * use, and we can freely write into the pages directly. If userspace | |
2697 | * races pwrite with any other operation; corruption will ensue - | |
2698 | * that is userspace's prerogative! | |
2699 | */ | |
2700 | ||
2701 | remain = arg->size; | |
2702 | offset = arg->offset; | |
2703 | pg = offset_in_page(offset); | |
2704 | ||
2705 | do { | |
2706 | unsigned int len, unwritten; | |
2707 | struct page *page; | |
2708 | void *data, *vaddr; | |
2709 | int err; | |
2710 | ||
2711 | len = PAGE_SIZE - pg; | |
2712 | if (len > remain) | |
2713 | len = remain; | |
2714 | ||
2715 | err = pagecache_write_begin(obj->base.filp, mapping, | |
2716 | offset, len, 0, | |
2717 | &page, &data); | |
2718 | if (err < 0) | |
2719 | return err; | |
2720 | ||
2721 | vaddr = kmap(page); | |
2722 | unwritten = copy_from_user(vaddr + pg, user_data, len); | |
2723 | kunmap(page); | |
2724 | ||
2725 | err = pagecache_write_end(obj->base.filp, mapping, | |
2726 | offset, len, len - unwritten, | |
2727 | page, data); | |
2728 | if (err < 0) | |
2729 | return err; | |
2730 | ||
2731 | if (unwritten) | |
2732 | return -EFAULT; | |
2733 | ||
2734 | remain -= len; | |
2735 | user_data += len; | |
2736 | offset += len; | |
2737 | pg = 0; | |
2738 | } while (remain); | |
2739 | ||
2740 | return 0; | |
2741 | } | |
2742 | ||
6095868a | 2743 | static bool ban_context(const struct i915_gem_context *ctx) |
be62acb4 | 2744 | { |
6095868a CW |
2745 | return (i915_gem_context_is_bannable(ctx) && |
2746 | ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD); | |
be62acb4 MK |
2747 | } |
2748 | ||
e5e1fc47 | 2749 | static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx) |
aa60c664 | 2750 | { |
bc1d53c6 | 2751 | ctx->guilty_count++; |
6095868a CW |
2752 | ctx->ban_score += CONTEXT_SCORE_GUILTY; |
2753 | if (ban_context(ctx)) | |
2754 | i915_gem_context_set_banned(ctx); | |
b083a087 MK |
2755 | |
2756 | DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n", | |
bc1d53c6 | 2757 | ctx->name, ctx->ban_score, |
6095868a | 2758 | yesno(i915_gem_context_is_banned(ctx))); |
b083a087 | 2759 | |
6095868a | 2760 | if (!i915_gem_context_is_banned(ctx) || IS_ERR_OR_NULL(ctx->file_priv)) |
b083a087 MK |
2761 | return; |
2762 | ||
d9e9da64 CW |
2763 | ctx->file_priv->context_bans++; |
2764 | DRM_DEBUG_DRIVER("client %s has had %d context banned\n", | |
2765 | ctx->name, ctx->file_priv->context_bans); | |
e5e1fc47 MK |
2766 | } |
2767 | ||
2768 | static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx) | |
2769 | { | |
bc1d53c6 | 2770 | ctx->active_count++; |
aa60c664 MK |
2771 | } |
2772 | ||
8d9fc7fd | 2773 | struct drm_i915_gem_request * |
0bc40be8 | 2774 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2775 | { |
754c9fd5 CW |
2776 | struct drm_i915_gem_request *request, *active = NULL; |
2777 | unsigned long flags; | |
4db080f9 | 2778 | |
f69a02c9 CW |
2779 | /* We are called by the error capture and reset at a random |
2780 | * point in time. In particular, note that neither is crucially | |
2781 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2782 | * assume that no more writes can happen (we waited long enough for | |
2783 | * all writes that were in transaction to be flushed) - adding an | |
2784 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2785 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2786 | */ | |
754c9fd5 | 2787 | spin_lock_irqsave(&engine->timeline->lock, flags); |
73cb9701 | 2788 | list_for_each_entry(request, &engine->timeline->requests, link) { |
754c9fd5 CW |
2789 | if (__i915_gem_request_completed(request, |
2790 | request->global_seqno)) | |
4db080f9 | 2791 | continue; |
aa60c664 | 2792 | |
36193acd | 2793 | GEM_BUG_ON(request->engine != engine); |
c00122f3 CW |
2794 | GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, |
2795 | &request->fence.flags)); | |
754c9fd5 CW |
2796 | |
2797 | active = request; | |
2798 | break; | |
4db080f9 | 2799 | } |
754c9fd5 | 2800 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
b6b0fac0 | 2801 | |
754c9fd5 | 2802 | return active; |
b6b0fac0 MK |
2803 | } |
2804 | ||
bf2f0436 MK |
2805 | static bool engine_stalled(struct intel_engine_cs *engine) |
2806 | { | |
2807 | if (!engine->hangcheck.stalled) | |
2808 | return false; | |
2809 | ||
2810 | /* Check for possible seqno movement after hang declaration */ | |
2811 | if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) { | |
2812 | DRM_DEBUG_DRIVER("%s pardoned\n", engine->name); | |
2813 | return false; | |
2814 | } | |
2815 | ||
2816 | return true; | |
2817 | } | |
2818 | ||
a1ef70e1 MT |
2819 | /* |
2820 | * Ensure irq handler finishes, and not run again. | |
2821 | * Also return the active request so that we only search for it once. | |
2822 | */ | |
2823 | struct drm_i915_gem_request * | |
2824 | i915_gem_reset_prepare_engine(struct intel_engine_cs *engine) | |
2825 | { | |
2826 | struct drm_i915_gem_request *request = NULL; | |
2827 | ||
2828 | /* Prevent the signaler thread from updating the request | |
2829 | * state (by calling dma_fence_signal) as we are processing | |
2830 | * the reset. The write from the GPU of the seqno is | |
2831 | * asynchronous and the signaler thread may see a different | |
2832 | * value to us and declare the request complete, even though | |
2833 | * the reset routine have picked that request as the active | |
2834 | * (incomplete) request. This conflict is not handled | |
2835 | * gracefully! | |
2836 | */ | |
2837 | kthread_park(engine->breadcrumbs.signaler); | |
2838 | ||
2839 | /* Prevent request submission to the hardware until we have | |
2840 | * completed the reset in i915_gem_reset_finish(). If a request | |
2841 | * is completed by one engine, it may then queue a request | |
2842 | * to a second via its engine->irq_tasklet *just* as we are | |
2843 | * calling engine->init_hw() and also writing the ELSP. | |
2844 | * Turning off the engine->irq_tasklet until the reset is over | |
2845 | * prevents the race. | |
2846 | */ | |
2847 | tasklet_kill(&engine->irq_tasklet); | |
2848 | tasklet_disable(&engine->irq_tasklet); | |
2849 | ||
2850 | if (engine->irq_seqno_barrier) | |
2851 | engine->irq_seqno_barrier(engine); | |
2852 | ||
2853 | if (engine_stalled(engine)) { | |
2854 | request = i915_gem_find_active_request(engine); | |
2855 | if (request && request->fence.error == -EIO) | |
2856 | request = ERR_PTR(-EIO); /* Previous reset failed! */ | |
2857 | } | |
2858 | ||
2859 | return request; | |
2860 | } | |
2861 | ||
0e178aef | 2862 | int i915_gem_reset_prepare(struct drm_i915_private *dev_priv) |
4c965543 CW |
2863 | { |
2864 | struct intel_engine_cs *engine; | |
a1ef70e1 | 2865 | struct drm_i915_gem_request *request; |
4c965543 | 2866 | enum intel_engine_id id; |
0e178aef | 2867 | int err = 0; |
4c965543 | 2868 | |
0e178aef | 2869 | for_each_engine(engine, dev_priv, id) { |
a1ef70e1 MT |
2870 | request = i915_gem_reset_prepare_engine(engine); |
2871 | if (IS_ERR(request)) { | |
2872 | err = PTR_ERR(request); | |
2873 | continue; | |
0e178aef | 2874 | } |
c64992e0 MT |
2875 | |
2876 | engine->hangcheck.active_request = request; | |
0e178aef CW |
2877 | } |
2878 | ||
4c965543 | 2879 | i915_gem_revoke_fences(dev_priv); |
0e178aef CW |
2880 | |
2881 | return err; | |
4c965543 CW |
2882 | } |
2883 | ||
36193acd | 2884 | static void skip_request(struct drm_i915_gem_request *request) |
821ed7df CW |
2885 | { |
2886 | void *vaddr = request->ring->vaddr; | |
2887 | u32 head; | |
2888 | ||
2889 | /* As this request likely depends on state from the lost | |
2890 | * context, clear out all the user operations leaving the | |
2891 | * breadcrumb at the end (so we get the fence notifications). | |
2892 | */ | |
2893 | head = request->head; | |
2894 | if (request->postfix < head) { | |
2895 | memset(vaddr + head, 0, request->ring->size - head); | |
2896 | head = 0; | |
2897 | } | |
2898 | memset(vaddr + head, 0, request->postfix - head); | |
c0d5f32c CW |
2899 | |
2900 | dma_fence_set_error(&request->fence, -EIO); | |
821ed7df CW |
2901 | } |
2902 | ||
36193acd MK |
2903 | static void engine_skip_context(struct drm_i915_gem_request *request) |
2904 | { | |
2905 | struct intel_engine_cs *engine = request->engine; | |
2906 | struct i915_gem_context *hung_ctx = request->ctx; | |
2907 | struct intel_timeline *timeline; | |
2908 | unsigned long flags; | |
2909 | ||
2910 | timeline = i915_gem_context_lookup_timeline(hung_ctx, engine); | |
2911 | ||
2912 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
2913 | spin_lock(&timeline->lock); | |
2914 | ||
2915 | list_for_each_entry_continue(request, &engine->timeline->requests, link) | |
2916 | if (request->ctx == hung_ctx) | |
2917 | skip_request(request); | |
2918 | ||
2919 | list_for_each_entry(request, &timeline->requests, link) | |
2920 | skip_request(request); | |
2921 | ||
2922 | spin_unlock(&timeline->lock); | |
2923 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
2924 | } | |
2925 | ||
61da5362 MK |
2926 | /* Returns true if the request was guilty of hang */ |
2927 | static bool i915_gem_reset_request(struct drm_i915_gem_request *request) | |
2928 | { | |
2929 | /* Read once and return the resolution */ | |
c64992e0 | 2930 | const bool guilty = !i915_gem_request_completed(request); |
61da5362 | 2931 | |
71895a08 MK |
2932 | /* The guilty request will get skipped on a hung engine. |
2933 | * | |
2934 | * Users of client default contexts do not rely on logical | |
2935 | * state preserved between batches so it is safe to execute | |
2936 | * queued requests following the hang. Non default contexts | |
2937 | * rely on preserved state, so skipping a batch loses the | |
2938 | * evolution of the state and it needs to be considered corrupted. | |
2939 | * Executing more queued batches on top of corrupted state is | |
2940 | * risky. But we take the risk by trying to advance through | |
2941 | * the queued requests in order to make the client behaviour | |
2942 | * more predictable around resets, by not throwing away random | |
2943 | * amount of batches it has prepared for execution. Sophisticated | |
2944 | * clients can use gem_reset_stats_ioctl and dma fence status | |
2945 | * (exported via sync_file info ioctl on explicit fences) to observe | |
2946 | * when it loses the context state and should rebuild accordingly. | |
2947 | * | |
2948 | * The context ban, and ultimately the client ban, mechanism are safety | |
2949 | * valves if client submission ends up resulting in nothing more than | |
2950 | * subsequent hangs. | |
2951 | */ | |
2952 | ||
61da5362 MK |
2953 | if (guilty) { |
2954 | i915_gem_context_mark_guilty(request->ctx); | |
2955 | skip_request(request); | |
2956 | } else { | |
2957 | i915_gem_context_mark_innocent(request->ctx); | |
2958 | dma_fence_set_error(&request->fence, -EAGAIN); | |
2959 | } | |
2960 | ||
2961 | return guilty; | |
2962 | } | |
2963 | ||
a1ef70e1 MT |
2964 | void i915_gem_reset_engine(struct intel_engine_cs *engine, |
2965 | struct drm_i915_gem_request *request) | |
b6b0fac0 | 2966 | { |
c0dcb203 CW |
2967 | if (request && i915_gem_reset_request(request)) { |
2968 | DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", | |
2969 | engine->name, request->global_seqno); | |
821ed7df | 2970 | |
c0dcb203 CW |
2971 | /* If this context is now banned, skip all pending requests. */ |
2972 | if (i915_gem_context_is_banned(request->ctx)) | |
2973 | engine_skip_context(request); | |
2974 | } | |
821ed7df CW |
2975 | |
2976 | /* Setup the CS to resume from the breadcrumb of the hung request */ | |
2977 | engine->reset_hw(engine, request); | |
4db080f9 | 2978 | } |
aa60c664 | 2979 | |
d8027093 | 2980 | void i915_gem_reset(struct drm_i915_private *dev_priv) |
4db080f9 | 2981 | { |
821ed7df | 2982 | struct intel_engine_cs *engine; |
3b3f1650 | 2983 | enum intel_engine_id id; |
608c1a52 | 2984 | |
4c7d62c6 CW |
2985 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2986 | ||
821ed7df CW |
2987 | i915_gem_retire_requests(dev_priv); |
2988 | ||
2ae55738 CW |
2989 | for_each_engine(engine, dev_priv, id) { |
2990 | struct i915_gem_context *ctx; | |
2991 | ||
c64992e0 | 2992 | i915_gem_reset_engine(engine, engine->hangcheck.active_request); |
2ae55738 CW |
2993 | ctx = fetch_and_zero(&engine->last_retired_context); |
2994 | if (ctx) | |
2995 | engine->context_unpin(engine, ctx); | |
2996 | } | |
821ed7df | 2997 | |
4362f4f6 | 2998 | i915_gem_restore_fences(dev_priv); |
f2a91d1a CW |
2999 | |
3000 | if (dev_priv->gt.awake) { | |
3001 | intel_sanitize_gt_powersave(dev_priv); | |
3002 | intel_enable_gt_powersave(dev_priv); | |
3003 | if (INTEL_GEN(dev_priv) >= 6) | |
3004 | gen6_rps_busy(dev_priv); | |
3005 | } | |
821ed7df CW |
3006 | } |
3007 | ||
a1ef70e1 MT |
3008 | void i915_gem_reset_finish_engine(struct intel_engine_cs *engine) |
3009 | { | |
3010 | tasklet_enable(&engine->irq_tasklet); | |
3011 | kthread_unpark(engine->breadcrumbs.signaler); | |
3012 | } | |
3013 | ||
d8027093 CW |
3014 | void i915_gem_reset_finish(struct drm_i915_private *dev_priv) |
3015 | { | |
1f7b847d CW |
3016 | struct intel_engine_cs *engine; |
3017 | enum intel_engine_id id; | |
3018 | ||
d8027093 | 3019 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
1f7b847d | 3020 | |
fe3288b5 | 3021 | for_each_engine(engine, dev_priv, id) { |
c64992e0 | 3022 | engine->hangcheck.active_request = NULL; |
a1ef70e1 | 3023 | i915_gem_reset_finish_engine(engine); |
fe3288b5 | 3024 | } |
d8027093 CW |
3025 | } |
3026 | ||
821ed7df CW |
3027 | static void nop_submit_request(struct drm_i915_gem_request *request) |
3028 | { | |
3cd9442f | 3029 | dma_fence_set_error(&request->fence, -EIO); |
3dcf93f7 CW |
3030 | i915_gem_request_submit(request); |
3031 | intel_engine_init_global_seqno(request->engine, request->global_seqno); | |
821ed7df CW |
3032 | } |
3033 | ||
2a20d6f8 | 3034 | static void engine_set_wedged(struct intel_engine_cs *engine) |
821ed7df | 3035 | { |
3cd9442f CW |
3036 | struct drm_i915_gem_request *request; |
3037 | unsigned long flags; | |
3038 | ||
20e4933c CW |
3039 | /* We need to be sure that no thread is running the old callback as |
3040 | * we install the nop handler (otherwise we would submit a request | |
3041 | * to hardware that will never complete). In order to prevent this | |
3042 | * race, we wait until the machine is idle before making the swap | |
3043 | * (using stop_machine()). | |
3044 | */ | |
821ed7df | 3045 | engine->submit_request = nop_submit_request; |
70c2a24d | 3046 | |
3cd9442f CW |
3047 | /* Mark all executing requests as skipped */ |
3048 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
3049 | list_for_each_entry(request, &engine->timeline->requests, link) | |
36703e79 CW |
3050 | if (!i915_gem_request_completed(request)) |
3051 | dma_fence_set_error(&request->fence, -EIO); | |
3cd9442f CW |
3052 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
3053 | ||
dcb4c12a OM |
3054 | /* |
3055 | * Clear the execlists queue up before freeing the requests, as those | |
3056 | * are the ones that keep the context and ringbuffer backing objects | |
3057 | * pinned in place. | |
3058 | */ | |
dcb4c12a | 3059 | |
7de1691a | 3060 | if (i915.enable_execlists) { |
77f0d0e9 | 3061 | struct execlist_port *port = engine->execlist_port; |
663f71e7 | 3062 | unsigned long flags; |
77f0d0e9 | 3063 | unsigned int n; |
663f71e7 CW |
3064 | |
3065 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
3066 | ||
77f0d0e9 CW |
3067 | for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) |
3068 | i915_gem_request_put(port_request(&port[n])); | |
70c2a24d | 3069 | memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); |
20311bd3 CW |
3070 | engine->execlist_queue = RB_ROOT; |
3071 | engine->execlist_first = NULL; | |
663f71e7 CW |
3072 | |
3073 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
4ee056f4 CW |
3074 | |
3075 | /* The port is checked prior to scheduling a tasklet, but | |
3076 | * just in case we have suspended the tasklet to do the | |
3077 | * wedging make sure that when it wakes, it decides there | |
3078 | * is no work to do by clearing the irq_posted bit. | |
3079 | */ | |
3080 | clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); | |
dcb4c12a | 3081 | } |
5e32d748 CW |
3082 | |
3083 | /* Mark all pending requests as complete so that any concurrent | |
3084 | * (lockless) lookup doesn't try and wait upon the request as we | |
3085 | * reset it. | |
3086 | */ | |
3087 | intel_engine_init_global_seqno(engine, | |
3088 | intel_engine_last_submit(engine)); | |
673a394b EA |
3089 | } |
3090 | ||
20e4933c | 3091 | static int __i915_gem_set_wedged_BKL(void *data) |
673a394b | 3092 | { |
20e4933c | 3093 | struct drm_i915_private *i915 = data; |
e2f80391 | 3094 | struct intel_engine_cs *engine; |
3b3f1650 | 3095 | enum intel_engine_id id; |
673a394b | 3096 | |
36703e79 | 3097 | set_bit(I915_WEDGED, &i915->gpu_error.flags); |
20e4933c | 3098 | for_each_engine(engine, i915, id) |
2a20d6f8 | 3099 | engine_set_wedged(engine); |
20e4933c CW |
3100 | |
3101 | return 0; | |
3102 | } | |
3103 | ||
3104 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv) | |
3105 | { | |
20e4933c | 3106 | stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL); |
673a394b EA |
3107 | } |
3108 | ||
2e8f9d32 CW |
3109 | bool i915_gem_unset_wedged(struct drm_i915_private *i915) |
3110 | { | |
3111 | struct i915_gem_timeline *tl; | |
3112 | int i; | |
3113 | ||
3114 | lockdep_assert_held(&i915->drm.struct_mutex); | |
3115 | if (!test_bit(I915_WEDGED, &i915->gpu_error.flags)) | |
3116 | return true; | |
3117 | ||
3118 | /* Before unwedging, make sure that all pending operations | |
3119 | * are flushed and errored out - we may have requests waiting upon | |
3120 | * third party fences. We marked all inflight requests as EIO, and | |
3121 | * every execbuf since returned EIO, for consistency we want all | |
3122 | * the currently pending requests to also be marked as EIO, which | |
3123 | * is done inside our nop_submit_request - and so we must wait. | |
3124 | * | |
3125 | * No more can be submitted until we reset the wedged bit. | |
3126 | */ | |
3127 | list_for_each_entry(tl, &i915->gt.timelines, link) { | |
3128 | for (i = 0; i < ARRAY_SIZE(tl->engine); i++) { | |
3129 | struct drm_i915_gem_request *rq; | |
3130 | ||
3131 | rq = i915_gem_active_peek(&tl->engine[i].last_request, | |
3132 | &i915->drm.struct_mutex); | |
3133 | if (!rq) | |
3134 | continue; | |
3135 | ||
3136 | /* We can't use our normal waiter as we want to | |
3137 | * avoid recursively trying to handle the current | |
3138 | * reset. The basic dma_fence_default_wait() installs | |
3139 | * a callback for dma_fence_signal(), which is | |
3140 | * triggered by our nop handler (indirectly, the | |
3141 | * callback enables the signaler thread which is | |
3142 | * woken by the nop_submit_request() advancing the seqno | |
3143 | * and when the seqno passes the fence, the signaler | |
3144 | * then signals the fence waking us up). | |
3145 | */ | |
3146 | if (dma_fence_default_wait(&rq->fence, true, | |
3147 | MAX_SCHEDULE_TIMEOUT) < 0) | |
3148 | return false; | |
3149 | } | |
3150 | } | |
3151 | ||
3152 | /* Undo nop_submit_request. We prevent all new i915 requests from | |
3153 | * being queued (by disallowing execbuf whilst wedged) so having | |
3154 | * waited for all active requests above, we know the system is idle | |
3155 | * and do not have to worry about a thread being inside | |
3156 | * engine->submit_request() as we swap over. So unlike installing | |
3157 | * the nop_submit_request on reset, we can do this from normal | |
3158 | * context and do not require stop_machine(). | |
3159 | */ | |
3160 | intel_engines_reset_default_submission(i915); | |
36703e79 | 3161 | i915_gem_contexts_lost(i915); |
2e8f9d32 CW |
3162 | |
3163 | smp_mb__before_atomic(); /* complete takeover before enabling execbuf */ | |
3164 | clear_bit(I915_WEDGED, &i915->gpu_error.flags); | |
3165 | ||
3166 | return true; | |
3167 | } | |
3168 | ||
75ef9da2 | 3169 | static void |
673a394b EA |
3170 | i915_gem_retire_work_handler(struct work_struct *work) |
3171 | { | |
b29c19b6 | 3172 | struct drm_i915_private *dev_priv = |
67d97da3 | 3173 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 3174 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 3175 | |
891b48cf | 3176 | /* Come back later if the device is busy... */ |
b29c19b6 | 3177 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 3178 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 3179 | mutex_unlock(&dev->struct_mutex); |
673a394b | 3180 | } |
67d97da3 CW |
3181 | |
3182 | /* Keep the retire handler running until we are finally idle. | |
3183 | * We do not need to do this test under locking as in the worst-case | |
3184 | * we queue the retire worker once too often. | |
3185 | */ | |
c9615613 CW |
3186 | if (READ_ONCE(dev_priv->gt.awake)) { |
3187 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
3188 | queue_delayed_work(dev_priv->wq, |
3189 | &dev_priv->gt.retire_work, | |
bcb45086 | 3190 | round_jiffies_up_relative(HZ)); |
c9615613 | 3191 | } |
b29c19b6 | 3192 | } |
0a58705b | 3193 | |
b29c19b6 CW |
3194 | static void |
3195 | i915_gem_idle_work_handler(struct work_struct *work) | |
3196 | { | |
3197 | struct drm_i915_private *dev_priv = | |
67d97da3 | 3198 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 3199 | struct drm_device *dev = &dev_priv->drm; |
67d97da3 CW |
3200 | bool rearm_hangcheck; |
3201 | ||
3202 | if (!READ_ONCE(dev_priv->gt.awake)) | |
3203 | return; | |
3204 | ||
0cb5670b ID |
3205 | /* |
3206 | * Wait for last execlists context complete, but bail out in case a | |
3207 | * new request is submitted. | |
3208 | */ | |
8490ae20 | 3209 | wait_for(intel_engines_are_idle(dev_priv), 10); |
28176ef4 | 3210 | if (READ_ONCE(dev_priv->gt.active_requests)) |
67d97da3 CW |
3211 | return; |
3212 | ||
3213 | rearm_hangcheck = | |
3214 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
3215 | ||
3216 | if (!mutex_trylock(&dev->struct_mutex)) { | |
3217 | /* Currently busy, come back later */ | |
3218 | mod_delayed_work(dev_priv->wq, | |
3219 | &dev_priv->gt.idle_work, | |
3220 | msecs_to_jiffies(50)); | |
3221 | goto out_rearm; | |
3222 | } | |
3223 | ||
93c97dc1 ID |
3224 | /* |
3225 | * New request retired after this work handler started, extend active | |
3226 | * period until next instance of the work. | |
3227 | */ | |
3228 | if (work_pending(work)) | |
3229 | goto out_unlock; | |
3230 | ||
28176ef4 | 3231 | if (dev_priv->gt.active_requests) |
67d97da3 | 3232 | goto out_unlock; |
b29c19b6 | 3233 | |
05425249 | 3234 | if (wait_for(intel_engines_are_idle(dev_priv), 10)) |
0cb5670b ID |
3235 | DRM_ERROR("Timeout waiting for engines to idle\n"); |
3236 | ||
6c067579 | 3237 | intel_engines_mark_idle(dev_priv); |
47979480 | 3238 | i915_gem_timelines_mark_idle(dev_priv); |
35c94185 | 3239 | |
67d97da3 CW |
3240 | GEM_BUG_ON(!dev_priv->gt.awake); |
3241 | dev_priv->gt.awake = false; | |
3242 | rearm_hangcheck = false; | |
30ecad77 | 3243 | |
67d97da3 CW |
3244 | if (INTEL_GEN(dev_priv) >= 6) |
3245 | gen6_rps_idle(dev_priv); | |
3246 | intel_runtime_pm_put(dev_priv); | |
3247 | out_unlock: | |
3248 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 3249 | |
67d97da3 CW |
3250 | out_rearm: |
3251 | if (rearm_hangcheck) { | |
3252 | GEM_BUG_ON(!dev_priv->gt.awake); | |
3253 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 3254 | } |
673a394b EA |
3255 | } |
3256 | ||
b1f788c6 CW |
3257 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
3258 | { | |
3259 | struct drm_i915_gem_object *obj = to_intel_bo(gem); | |
3260 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
3261 | struct i915_vma *vma, *vn; | |
3262 | ||
3263 | mutex_lock(&obj->base.dev->struct_mutex); | |
3264 | list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) | |
3265 | if (vma->vm->file == fpriv) | |
3266 | i915_vma_close(vma); | |
f8a7fde4 | 3267 | |
4ff4b44c CW |
3268 | vma = obj->vma_hashed; |
3269 | if (vma && vma->ctx->file_priv == fpriv) | |
3270 | i915_vma_unlink_ctx(vma); | |
3271 | ||
f8a7fde4 CW |
3272 | if (i915_gem_object_is_active(obj) && |
3273 | !i915_gem_object_has_active_reference(obj)) { | |
3274 | i915_gem_object_set_active_reference(obj); | |
3275 | i915_gem_object_get(obj); | |
3276 | } | |
b1f788c6 CW |
3277 | mutex_unlock(&obj->base.dev->struct_mutex); |
3278 | } | |
3279 | ||
e95433c7 CW |
3280 | static unsigned long to_wait_timeout(s64 timeout_ns) |
3281 | { | |
3282 | if (timeout_ns < 0) | |
3283 | return MAX_SCHEDULE_TIMEOUT; | |
3284 | ||
3285 | if (timeout_ns == 0) | |
3286 | return 0; | |
3287 | ||
3288 | return nsecs_to_jiffies_timeout(timeout_ns); | |
3289 | } | |
3290 | ||
23ba4fd0 BW |
3291 | /** |
3292 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
3293 | * @dev: drm device pointer |
3294 | * @data: ioctl data blob | |
3295 | * @file: drm file pointer | |
23ba4fd0 BW |
3296 | * |
3297 | * Returns 0 if successful, else an error is returned with the remaining time in | |
3298 | * the timeout parameter. | |
3299 | * -ETIME: object is still busy after timeout | |
3300 | * -ERESTARTSYS: signal interrupted the wait | |
3301 | * -ENONENT: object doesn't exist | |
3302 | * Also possible, but rare: | |
3303 | * -EAGAIN: GPU wedged | |
3304 | * -ENOMEM: damn | |
3305 | * -ENODEV: Internal IRQ fail | |
3306 | * -E?: The add request failed | |
3307 | * | |
3308 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
3309 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
3310 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
3311 | * without holding struct_mutex the object may become re-busied before this | |
3312 | * function completes. A similar but shorter * race condition exists in the busy | |
3313 | * ioctl | |
3314 | */ | |
3315 | int | |
3316 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
3317 | { | |
3318 | struct drm_i915_gem_wait *args = data; | |
3319 | struct drm_i915_gem_object *obj; | |
e95433c7 CW |
3320 | ktime_t start; |
3321 | long ret; | |
23ba4fd0 | 3322 | |
11b5d511 DV |
3323 | if (args->flags != 0) |
3324 | return -EINVAL; | |
3325 | ||
03ac0642 | 3326 | obj = i915_gem_object_lookup(file, args->bo_handle); |
033d549b | 3327 | if (!obj) |
23ba4fd0 | 3328 | return -ENOENT; |
23ba4fd0 | 3329 | |
e95433c7 CW |
3330 | start = ktime_get(); |
3331 | ||
3332 | ret = i915_gem_object_wait(obj, | |
3333 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL, | |
3334 | to_wait_timeout(args->timeout_ns), | |
3335 | to_rps_client(file)); | |
3336 | ||
3337 | if (args->timeout_ns > 0) { | |
3338 | args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start)); | |
3339 | if (args->timeout_ns < 0) | |
3340 | args->timeout_ns = 0; | |
c1d2061b CW |
3341 | |
3342 | /* | |
3343 | * Apparently ktime isn't accurate enough and occasionally has a | |
3344 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
3345 | * things up to make the test happy. We allow up to 1 jiffy. | |
3346 | * | |
3347 | * This is a regression from the timespec->ktime conversion. | |
3348 | */ | |
3349 | if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns)) | |
3350 | args->timeout_ns = 0; | |
b4716185 CW |
3351 | } |
3352 | ||
f0cd5182 | 3353 | i915_gem_object_put(obj); |
ff865885 | 3354 | return ret; |
23ba4fd0 BW |
3355 | } |
3356 | ||
73cb9701 | 3357 | static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) |
4df2faf4 | 3358 | { |
73cb9701 | 3359 | int ret, i; |
4df2faf4 | 3360 | |
73cb9701 CW |
3361 | for (i = 0; i < ARRAY_SIZE(tl->engine); i++) { |
3362 | ret = i915_gem_active_wait(&tl->engine[i].last_request, flags); | |
3363 | if (ret) | |
3364 | return ret; | |
3365 | } | |
62e63007 | 3366 | |
73cb9701 CW |
3367 | return 0; |
3368 | } | |
3369 | ||
25112b64 CW |
3370 | static int wait_for_engine(struct intel_engine_cs *engine, int timeout_ms) |
3371 | { | |
3372 | return wait_for(intel_engine_is_idle(engine), timeout_ms); | |
3373 | } | |
3374 | ||
3375 | static int wait_for_engines(struct drm_i915_private *i915) | |
3376 | { | |
3377 | struct intel_engine_cs *engine; | |
3378 | enum intel_engine_id id; | |
3379 | ||
3380 | for_each_engine(engine, i915, id) { | |
3381 | if (GEM_WARN_ON(wait_for_engine(engine, 50))) { | |
3382 | i915_gem_set_wedged(i915); | |
3383 | return -EIO; | |
3384 | } | |
3385 | ||
3386 | GEM_BUG_ON(intel_engine_get_seqno(engine) != | |
3387 | intel_engine_last_submit(engine)); | |
3388 | } | |
3389 | ||
3390 | return 0; | |
3391 | } | |
3392 | ||
73cb9701 CW |
3393 | int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags) |
3394 | { | |
73cb9701 CW |
3395 | int ret; |
3396 | ||
863e9fde CW |
3397 | /* If the device is asleep, we have no requests outstanding */ |
3398 | if (!READ_ONCE(i915->gt.awake)) | |
3399 | return 0; | |
3400 | ||
9caa34aa CW |
3401 | if (flags & I915_WAIT_LOCKED) { |
3402 | struct i915_gem_timeline *tl; | |
3403 | ||
3404 | lockdep_assert_held(&i915->drm.struct_mutex); | |
3405 | ||
3406 | list_for_each_entry(tl, &i915->gt.timelines, link) { | |
3407 | ret = wait_for_timeline(tl, flags); | |
3408 | if (ret) | |
3409 | return ret; | |
3410 | } | |
72022a70 CW |
3411 | |
3412 | i915_gem_retire_requests(i915); | |
3413 | GEM_BUG_ON(i915->gt.active_requests); | |
25112b64 CW |
3414 | |
3415 | ret = wait_for_engines(i915); | |
9caa34aa CW |
3416 | } else { |
3417 | ret = wait_for_timeline(&i915->gt.global_timeline, flags); | |
1ec14ad3 | 3418 | } |
4df2faf4 | 3419 | |
25112b64 | 3420 | return ret; |
4df2faf4 DV |
3421 | } |
3422 | ||
5a97bcc6 CW |
3423 | static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj) |
3424 | { | |
e27ab73d CW |
3425 | /* |
3426 | * We manually flush the CPU domain so that we can override and | |
3427 | * force the flush for the display, and perform it asyncrhonously. | |
3428 | */ | |
3429 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); | |
3430 | if (obj->cache_dirty) | |
3431 | i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE); | |
5a97bcc6 CW |
3432 | obj->base.write_domain = 0; |
3433 | } | |
3434 | ||
3435 | void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj) | |
3436 | { | |
3437 | if (!READ_ONCE(obj->pin_display)) | |
3438 | return; | |
3439 | ||
3440 | mutex_lock(&obj->base.dev->struct_mutex); | |
3441 | __i915_gem_object_flush_for_display(obj); | |
3442 | mutex_unlock(&obj->base.dev->struct_mutex); | |
3443 | } | |
3444 | ||
e22d8e3c CW |
3445 | /** |
3446 | * Moves a single object to the WC read, and possibly write domain. | |
3447 | * @obj: object to act on | |
3448 | * @write: ask for write access or read only | |
3449 | * | |
3450 | * This function returns when the move is complete, including waiting on | |
3451 | * flushes to occur. | |
3452 | */ | |
3453 | int | |
3454 | i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write) | |
3455 | { | |
3456 | int ret; | |
3457 | ||
3458 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
3459 | ||
3460 | ret = i915_gem_object_wait(obj, | |
3461 | I915_WAIT_INTERRUPTIBLE | | |
3462 | I915_WAIT_LOCKED | | |
3463 | (write ? I915_WAIT_ALL : 0), | |
3464 | MAX_SCHEDULE_TIMEOUT, | |
3465 | NULL); | |
3466 | if (ret) | |
3467 | return ret; | |
3468 | ||
3469 | if (obj->base.write_domain == I915_GEM_DOMAIN_WC) | |
3470 | return 0; | |
3471 | ||
3472 | /* Flush and acquire obj->pages so that we are coherent through | |
3473 | * direct access in memory with previous cached writes through | |
3474 | * shmemfs and that our cache domain tracking remains valid. | |
3475 | * For example, if the obj->filp was moved to swap without us | |
3476 | * being notified and releasing the pages, we would mistakenly | |
3477 | * continue to assume that the obj remained out of the CPU cached | |
3478 | * domain. | |
3479 | */ | |
3480 | ret = i915_gem_object_pin_pages(obj); | |
3481 | if (ret) | |
3482 | return ret; | |
3483 | ||
3484 | flush_write_domain(obj, ~I915_GEM_DOMAIN_WC); | |
3485 | ||
3486 | /* Serialise direct access to this object with the barriers for | |
3487 | * coherent writes from the GPU, by effectively invalidating the | |
3488 | * WC domain upon first access. | |
3489 | */ | |
3490 | if ((obj->base.read_domains & I915_GEM_DOMAIN_WC) == 0) | |
3491 | mb(); | |
3492 | ||
3493 | /* It should now be out of any other write domains, and we can update | |
3494 | * the domain values for our changes. | |
3495 | */ | |
3496 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_WC) != 0); | |
3497 | obj->base.read_domains |= I915_GEM_DOMAIN_WC; | |
3498 | if (write) { | |
3499 | obj->base.read_domains = I915_GEM_DOMAIN_WC; | |
3500 | obj->base.write_domain = I915_GEM_DOMAIN_WC; | |
3501 | obj->mm.dirty = true; | |
3502 | } | |
3503 | ||
3504 | i915_gem_object_unpin_pages(obj); | |
3505 | return 0; | |
3506 | } | |
3507 | ||
2ef7eeaa EA |
3508 | /** |
3509 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3510 | * @obj: object to act on |
3511 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3512 | * |
3513 | * This function returns when the move is complete, including waiting on | |
3514 | * flushes to occur. | |
3515 | */ | |
79e53945 | 3516 | int |
2021746e | 3517 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3518 | { |
e47c68e9 | 3519 | int ret; |
2ef7eeaa | 3520 | |
e95433c7 | 3521 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3522 | |
e95433c7 CW |
3523 | ret = i915_gem_object_wait(obj, |
3524 | I915_WAIT_INTERRUPTIBLE | | |
3525 | I915_WAIT_LOCKED | | |
3526 | (write ? I915_WAIT_ALL : 0), | |
3527 | MAX_SCHEDULE_TIMEOUT, | |
3528 | NULL); | |
88241785 CW |
3529 | if (ret) |
3530 | return ret; | |
3531 | ||
c13d87ea CW |
3532 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3533 | return 0; | |
3534 | ||
43566ded CW |
3535 | /* Flush and acquire obj->pages so that we are coherent through |
3536 | * direct access in memory with previous cached writes through | |
3537 | * shmemfs and that our cache domain tracking remains valid. | |
3538 | * For example, if the obj->filp was moved to swap without us | |
3539 | * being notified and releasing the pages, we would mistakenly | |
3540 | * continue to assume that the obj remained out of the CPU cached | |
3541 | * domain. | |
3542 | */ | |
a4f5ea64 | 3543 | ret = i915_gem_object_pin_pages(obj); |
43566ded CW |
3544 | if (ret) |
3545 | return ret; | |
3546 | ||
ef74921b | 3547 | flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT); |
1c5d22f7 | 3548 | |
d0a57789 CW |
3549 | /* Serialise direct access to this object with the barriers for |
3550 | * coherent writes from the GPU, by effectively invalidating the | |
3551 | * GTT domain upon first access. | |
3552 | */ | |
3553 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3554 | mb(); | |
3555 | ||
e47c68e9 EA |
3556 | /* It should now be out of any other write domains, and we can update |
3557 | * the domain values for our changes. | |
3558 | */ | |
40e62d5d | 3559 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
05394f39 | 3560 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
e47c68e9 | 3561 | if (write) { |
05394f39 CW |
3562 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3563 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
a4f5ea64 | 3564 | obj->mm.dirty = true; |
2ef7eeaa EA |
3565 | } |
3566 | ||
a4f5ea64 | 3567 | i915_gem_object_unpin_pages(obj); |
e47c68e9 EA |
3568 | return 0; |
3569 | } | |
3570 | ||
ef55f92a CW |
3571 | /** |
3572 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3573 | * @obj: object to act on |
3574 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3575 | * |
3576 | * After this function returns, the object will be in the new cache-level | |
3577 | * across all GTT and the contents of the backing storage will be coherent, | |
3578 | * with respect to the new cache-level. In order to keep the backing storage | |
3579 | * coherent for all users, we only allow a single cache level to be set | |
3580 | * globally on the object and prevent it from being changed whilst the | |
3581 | * hardware is reading from the object. That is if the object is currently | |
3582 | * on the scanout it will be set to uncached (or equivalent display | |
3583 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3584 | * that all direct access to the scanout remains coherent. | |
3585 | */ | |
e4ffd173 CW |
3586 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3587 | enum i915_cache_level cache_level) | |
3588 | { | |
aa653a68 | 3589 | struct i915_vma *vma; |
a6a7cc4b | 3590 | int ret; |
e4ffd173 | 3591 | |
4c7d62c6 CW |
3592 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3593 | ||
e4ffd173 | 3594 | if (obj->cache_level == cache_level) |
a6a7cc4b | 3595 | return 0; |
e4ffd173 | 3596 | |
ef55f92a CW |
3597 | /* Inspect the list of currently bound VMA and unbind any that would |
3598 | * be invalid given the new cache-level. This is principally to | |
3599 | * catch the issue of the CS prefetch crossing page boundaries and | |
3600 | * reading an invalid PTE on older architectures. | |
3601 | */ | |
aa653a68 CW |
3602 | restart: |
3603 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3604 | if (!drm_mm_node_allocated(&vma->node)) |
3605 | continue; | |
3606 | ||
20dfbde4 | 3607 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3608 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3609 | return -EBUSY; | |
3610 | } | |
3611 | ||
aa653a68 CW |
3612 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3613 | continue; | |
3614 | ||
3615 | ret = i915_vma_unbind(vma); | |
3616 | if (ret) | |
3617 | return ret; | |
3618 | ||
3619 | /* As unbinding may affect other elements in the | |
3620 | * obj->vma_list (due to side-effects from retiring | |
3621 | * an active vma), play safe and restart the iterator. | |
3622 | */ | |
3623 | goto restart; | |
42d6ab48 CW |
3624 | } |
3625 | ||
ef55f92a CW |
3626 | /* We can reuse the existing drm_mm nodes but need to change the |
3627 | * cache-level on the PTE. We could simply unbind them all and | |
3628 | * rebind with the correct cache-level on next use. However since | |
3629 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3630 | * rewrite the PTE in the belief that doing so tramples upon less | |
3631 | * state and so involves less work. | |
3632 | */ | |
15717de2 | 3633 | if (obj->bind_count) { |
ef55f92a CW |
3634 | /* Before we change the PTE, the GPU must not be accessing it. |
3635 | * If we wait upon the object, we know that all the bound | |
3636 | * VMA are no longer active. | |
3637 | */ | |
e95433c7 CW |
3638 | ret = i915_gem_object_wait(obj, |
3639 | I915_WAIT_INTERRUPTIBLE | | |
3640 | I915_WAIT_LOCKED | | |
3641 | I915_WAIT_ALL, | |
3642 | MAX_SCHEDULE_TIMEOUT, | |
3643 | NULL); | |
e4ffd173 CW |
3644 | if (ret) |
3645 | return ret; | |
3646 | ||
0031fb96 TU |
3647 | if (!HAS_LLC(to_i915(obj->base.dev)) && |
3648 | cache_level != I915_CACHE_NONE) { | |
ef55f92a CW |
3649 | /* Access to snoopable pages through the GTT is |
3650 | * incoherent and on some machines causes a hard | |
3651 | * lockup. Relinquish the CPU mmaping to force | |
3652 | * userspace to refault in the pages and we can | |
3653 | * then double check if the GTT mapping is still | |
3654 | * valid for that pointer access. | |
3655 | */ | |
3656 | i915_gem_release_mmap(obj); | |
3657 | ||
3658 | /* As we no longer need a fence for GTT access, | |
3659 | * we can relinquish it now (and so prevent having | |
3660 | * to steal a fence from someone else on the next | |
3661 | * fence request). Note GPU activity would have | |
3662 | * dropped the fence as all snoopable access is | |
3663 | * supposed to be linear. | |
3664 | */ | |
49ef5294 CW |
3665 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3666 | ret = i915_vma_put_fence(vma); | |
3667 | if (ret) | |
3668 | return ret; | |
3669 | } | |
ef55f92a CW |
3670 | } else { |
3671 | /* We either have incoherent backing store and | |
3672 | * so no GTT access or the architecture is fully | |
3673 | * coherent. In such cases, existing GTT mmaps | |
3674 | * ignore the cache bit in the PTE and we can | |
3675 | * rewrite it without confusing the GPU or having | |
3676 | * to force userspace to fault back in its mmaps. | |
3677 | */ | |
e4ffd173 CW |
3678 | } |
3679 | ||
1c7f4bca | 3680 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3681 | if (!drm_mm_node_allocated(&vma->node)) |
3682 | continue; | |
3683 | ||
3684 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3685 | if (ret) | |
3686 | return ret; | |
3687 | } | |
e4ffd173 CW |
3688 | } |
3689 | ||
1c7f4bca | 3690 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3691 | vma->node.color = cache_level; |
3692 | obj->cache_level = cache_level; | |
7fc92e96 | 3693 | obj->cache_coherent = i915_gem_object_is_coherent(obj); |
e27ab73d | 3694 | obj->cache_dirty = true; /* Always invalidate stale cachelines */ |
2c22569b | 3695 | |
e4ffd173 CW |
3696 | return 0; |
3697 | } | |
3698 | ||
199adf40 BW |
3699 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3700 | struct drm_file *file) | |
e6994aee | 3701 | { |
199adf40 | 3702 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3703 | struct drm_i915_gem_object *obj; |
fbbd37b3 | 3704 | int err = 0; |
e6994aee | 3705 | |
fbbd37b3 CW |
3706 | rcu_read_lock(); |
3707 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
3708 | if (!obj) { | |
3709 | err = -ENOENT; | |
3710 | goto out; | |
3711 | } | |
e6994aee | 3712 | |
651d794f CW |
3713 | switch (obj->cache_level) { |
3714 | case I915_CACHE_LLC: | |
3715 | case I915_CACHE_L3_LLC: | |
3716 | args->caching = I915_CACHING_CACHED; | |
3717 | break; | |
3718 | ||
4257d3ba CW |
3719 | case I915_CACHE_WT: |
3720 | args->caching = I915_CACHING_DISPLAY; | |
3721 | break; | |
3722 | ||
651d794f CW |
3723 | default: |
3724 | args->caching = I915_CACHING_NONE; | |
3725 | break; | |
3726 | } | |
fbbd37b3 CW |
3727 | out: |
3728 | rcu_read_unlock(); | |
3729 | return err; | |
e6994aee CW |
3730 | } |
3731 | ||
199adf40 BW |
3732 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3733 | struct drm_file *file) | |
e6994aee | 3734 | { |
9c870d03 | 3735 | struct drm_i915_private *i915 = to_i915(dev); |
199adf40 | 3736 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3737 | struct drm_i915_gem_object *obj; |
3738 | enum i915_cache_level level; | |
d65415df | 3739 | int ret = 0; |
e6994aee | 3740 | |
199adf40 BW |
3741 | switch (args->caching) { |
3742 | case I915_CACHING_NONE: | |
e6994aee CW |
3743 | level = I915_CACHE_NONE; |
3744 | break; | |
199adf40 | 3745 | case I915_CACHING_CACHED: |
e5756c10 ID |
3746 | /* |
3747 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3748 | * snooped mapping may leave stale data in a corresponding CPU | |
3749 | * cacheline, whereas normally such cachelines would get | |
3750 | * invalidated. | |
3751 | */ | |
9c870d03 | 3752 | if (!HAS_LLC(i915) && !HAS_SNOOP(i915)) |
e5756c10 ID |
3753 | return -ENODEV; |
3754 | ||
e6994aee CW |
3755 | level = I915_CACHE_LLC; |
3756 | break; | |
4257d3ba | 3757 | case I915_CACHING_DISPLAY: |
9c870d03 | 3758 | level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE; |
4257d3ba | 3759 | break; |
e6994aee CW |
3760 | default: |
3761 | return -EINVAL; | |
3762 | } | |
3763 | ||
d65415df CW |
3764 | obj = i915_gem_object_lookup(file, args->handle); |
3765 | if (!obj) | |
3766 | return -ENOENT; | |
3767 | ||
3768 | if (obj->cache_level == level) | |
3769 | goto out; | |
3770 | ||
3771 | ret = i915_gem_object_wait(obj, | |
3772 | I915_WAIT_INTERRUPTIBLE, | |
3773 | MAX_SCHEDULE_TIMEOUT, | |
3774 | to_rps_client(file)); | |
3bc2913e | 3775 | if (ret) |
d65415df | 3776 | goto out; |
3bc2913e | 3777 | |
d65415df CW |
3778 | ret = i915_mutex_lock_interruptible(dev); |
3779 | if (ret) | |
3780 | goto out; | |
e6994aee CW |
3781 | |
3782 | ret = i915_gem_object_set_cache_level(obj, level); | |
e6994aee | 3783 | mutex_unlock(&dev->struct_mutex); |
d65415df CW |
3784 | |
3785 | out: | |
3786 | i915_gem_object_put(obj); | |
e6994aee CW |
3787 | return ret; |
3788 | } | |
3789 | ||
b9241ea3 | 3790 | /* |
2da3b9b9 CW |
3791 | * Prepare buffer for display plane (scanout, cursors, etc). |
3792 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3793 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 | 3794 | */ |
058d88c4 | 3795 | struct i915_vma * |
2da3b9b9 CW |
3796 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3797 | u32 alignment, | |
e6617330 | 3798 | const struct i915_ggtt_view *view) |
b9241ea3 | 3799 | { |
058d88c4 | 3800 | struct i915_vma *vma; |
b9241ea3 ZW |
3801 | int ret; |
3802 | ||
4c7d62c6 CW |
3803 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3804 | ||
cc98b413 CW |
3805 | /* Mark the pin_display early so that we account for the |
3806 | * display coherency whilst setting up the cache domains. | |
3807 | */ | |
8a0c39b1 | 3808 | obj->pin_display++; |
cc98b413 | 3809 | |
a7ef0640 EA |
3810 | /* The display engine is not coherent with the LLC cache on gen6. As |
3811 | * a result, we make sure that the pinning that is about to occur is | |
3812 | * done with uncached PTEs. This is lowest common denominator for all | |
3813 | * chipsets. | |
3814 | * | |
3815 | * However for gen6+, we could do better by using the GFDT bit instead | |
3816 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3817 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3818 | */ | |
651d794f | 3819 | ret = i915_gem_object_set_cache_level(obj, |
8652744b TU |
3820 | HAS_WT(to_i915(obj->base.dev)) ? |
3821 | I915_CACHE_WT : I915_CACHE_NONE); | |
058d88c4 CW |
3822 | if (ret) { |
3823 | vma = ERR_PTR(ret); | |
cc98b413 | 3824 | goto err_unpin_display; |
058d88c4 | 3825 | } |
a7ef0640 | 3826 | |
2da3b9b9 CW |
3827 | /* As the user may map the buffer once pinned in the display plane |
3828 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2efb813d CW |
3829 | * always use map_and_fenceable for all scanout buffers. However, |
3830 | * it may simply be too big to fit into mappable, in which case | |
3831 | * put it anyway and hope that userspace can cope (but always first | |
3832 | * try to preserve the existing ABI). | |
2da3b9b9 | 3833 | */ |
2efb813d | 3834 | vma = ERR_PTR(-ENOSPC); |
47a8e3f6 | 3835 | if (!view || view->type == I915_GGTT_VIEW_NORMAL) |
2efb813d CW |
3836 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, |
3837 | PIN_MAPPABLE | PIN_NONBLOCK); | |
767a222e CW |
3838 | if (IS_ERR(vma)) { |
3839 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
3840 | unsigned int flags; | |
3841 | ||
3842 | /* Valleyview is definitely limited to scanning out the first | |
3843 | * 512MiB. Lets presume this behaviour was inherited from the | |
3844 | * g4x display engine and that all earlier gen are similarly | |
3845 | * limited. Testing suggests that it is a little more | |
3846 | * complicated than this. For example, Cherryview appears quite | |
3847 | * happy to scanout from anywhere within its global aperture. | |
3848 | */ | |
3849 | flags = 0; | |
3850 | if (HAS_GMCH_DISPLAY(i915)) | |
3851 | flags = PIN_MAPPABLE; | |
3852 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags); | |
3853 | } | |
058d88c4 | 3854 | if (IS_ERR(vma)) |
cc98b413 | 3855 | goto err_unpin_display; |
2da3b9b9 | 3856 | |
d8923dcf CW |
3857 | vma->display_alignment = max_t(u64, vma->display_alignment, alignment); |
3858 | ||
a6a7cc4b | 3859 | /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ |
5a97bcc6 | 3860 | __i915_gem_object_flush_for_display(obj); |
d59b21ec | 3861 | intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); |
b118c1e3 | 3862 | |
2da3b9b9 CW |
3863 | /* It should now be out of any other write domains, and we can update |
3864 | * the domain values for our changes. | |
3865 | */ | |
05394f39 | 3866 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 | 3867 | |
058d88c4 | 3868 | return vma; |
cc98b413 CW |
3869 | |
3870 | err_unpin_display: | |
8a0c39b1 | 3871 | obj->pin_display--; |
058d88c4 | 3872 | return vma; |
cc98b413 CW |
3873 | } |
3874 | ||
3875 | void | |
058d88c4 | 3876 | i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) |
cc98b413 | 3877 | { |
49d73912 | 3878 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
4c7d62c6 | 3879 | |
058d88c4 | 3880 | if (WARN_ON(vma->obj->pin_display == 0)) |
8a0c39b1 TU |
3881 | return; |
3882 | ||
d8923dcf | 3883 | if (--vma->obj->pin_display == 0) |
f51455d4 | 3884 | vma->display_alignment = I915_GTT_MIN_ALIGNMENT; |
e6617330 | 3885 | |
383d5823 | 3886 | /* Bump the LRU to try and avoid premature eviction whilst flipping */ |
befedbb7 | 3887 | i915_gem_object_bump_inactive_ggtt(vma->obj); |
383d5823 | 3888 | |
058d88c4 | 3889 | i915_vma_unpin(vma); |
b9241ea3 ZW |
3890 | } |
3891 | ||
e47c68e9 EA |
3892 | /** |
3893 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3894 | * @obj: object to act on |
3895 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3896 | * |
3897 | * This function returns when the move is complete, including waiting on | |
3898 | * flushes to occur. | |
3899 | */ | |
dabdfe02 | 3900 | int |
919926ae | 3901 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3902 | { |
e47c68e9 EA |
3903 | int ret; |
3904 | ||
e95433c7 | 3905 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3906 | |
e95433c7 CW |
3907 | ret = i915_gem_object_wait(obj, |
3908 | I915_WAIT_INTERRUPTIBLE | | |
3909 | I915_WAIT_LOCKED | | |
3910 | (write ? I915_WAIT_ALL : 0), | |
3911 | MAX_SCHEDULE_TIMEOUT, | |
3912 | NULL); | |
88241785 CW |
3913 | if (ret) |
3914 | return ret; | |
3915 | ||
ef74921b | 3916 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); |
2ef7eeaa | 3917 | |
e47c68e9 | 3918 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3919 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
57822dc6 | 3920 | i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC); |
05394f39 | 3921 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3922 | } |
3923 | ||
3924 | /* It should now be out of any other write domains, and we can update | |
3925 | * the domain values for our changes. | |
3926 | */ | |
e27ab73d | 3927 | GEM_BUG_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
e47c68e9 EA |
3928 | |
3929 | /* If we're writing through the CPU, then the GPU read domains will | |
3930 | * need to be invalidated at next use. | |
3931 | */ | |
e27ab73d CW |
3932 | if (write) |
3933 | __start_cpu_write(obj); | |
2ef7eeaa EA |
3934 | |
3935 | return 0; | |
3936 | } | |
3937 | ||
673a394b EA |
3938 | /* Throttle our rendering by waiting until the ring has completed our requests |
3939 | * emitted over 20 msec ago. | |
3940 | * | |
b962442e EA |
3941 | * Note that if we were to use the current jiffies each time around the loop, |
3942 | * we wouldn't escape the function with any frames outstanding if the time to | |
3943 | * render a frame was over 20ms. | |
3944 | * | |
673a394b EA |
3945 | * This should get us reasonable parallelism between CPU and GPU but also |
3946 | * relatively low latency when blocking on a particular request to finish. | |
3947 | */ | |
40a5f0de | 3948 | static int |
f787a5f5 | 3949 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3950 | { |
fac5e23e | 3951 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3952 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3953 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3954 | struct drm_i915_gem_request *request, *target = NULL; |
e95433c7 | 3955 | long ret; |
93533c29 | 3956 | |
f4457ae7 CW |
3957 | /* ABI: return -EIO if already wedged */ |
3958 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3959 | return -EIO; | |
e110e8d6 | 3960 | |
1c25595f | 3961 | spin_lock(&file_priv->mm.lock); |
c8659efa | 3962 | list_for_each_entry(request, &file_priv->mm.request_list, client_link) { |
b962442e EA |
3963 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3964 | break; | |
40a5f0de | 3965 | |
c8659efa CW |
3966 | if (target) { |
3967 | list_del(&target->client_link); | |
3968 | target->file_priv = NULL; | |
3969 | } | |
fcfa423c | 3970 | |
54fb2411 | 3971 | target = request; |
b962442e | 3972 | } |
ff865885 | 3973 | if (target) |
e8a261ea | 3974 | i915_gem_request_get(target); |
1c25595f | 3975 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3976 | |
54fb2411 | 3977 | if (target == NULL) |
f787a5f5 | 3978 | return 0; |
2bc43b5c | 3979 | |
e95433c7 CW |
3980 | ret = i915_wait_request(target, |
3981 | I915_WAIT_INTERRUPTIBLE, | |
3982 | MAX_SCHEDULE_TIMEOUT); | |
e8a261ea | 3983 | i915_gem_request_put(target); |
ff865885 | 3984 | |
e95433c7 | 3985 | return ret < 0 ? ret : 0; |
40a5f0de EA |
3986 | } |
3987 | ||
058d88c4 | 3988 | struct i915_vma * |
ec7adb6e JL |
3989 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3990 | const struct i915_ggtt_view *view, | |
91b2db6f | 3991 | u64 size, |
2ffffd0f CW |
3992 | u64 alignment, |
3993 | u64 flags) | |
ec7adb6e | 3994 | { |
ad16d2ed CW |
3995 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
3996 | struct i915_address_space *vm = &dev_priv->ggtt.base; | |
59bfa124 CW |
3997 | struct i915_vma *vma; |
3998 | int ret; | |
72e96d64 | 3999 | |
4c7d62c6 CW |
4000 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4001 | ||
718659a6 | 4002 | vma = i915_vma_instance(obj, vm, view); |
e0216b76 | 4003 | if (unlikely(IS_ERR(vma))) |
058d88c4 | 4004 | return vma; |
59bfa124 CW |
4005 | |
4006 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
4007 | if (flags & PIN_NONBLOCK && | |
4008 | (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))) | |
058d88c4 | 4009 | return ERR_PTR(-ENOSPC); |
59bfa124 | 4010 | |
ad16d2ed | 4011 | if (flags & PIN_MAPPABLE) { |
ad16d2ed CW |
4012 | /* If the required space is larger than the available |
4013 | * aperture, we will not able to find a slot for the | |
4014 | * object and unbinding the object now will be in | |
4015 | * vain. Worse, doing so may cause us to ping-pong | |
4016 | * the object in and out of the Global GTT and | |
4017 | * waste a lot of cycles under the mutex. | |
4018 | */ | |
944397f0 | 4019 | if (vma->fence_size > dev_priv->ggtt.mappable_end) |
ad16d2ed CW |
4020 | return ERR_PTR(-E2BIG); |
4021 | ||
4022 | /* If NONBLOCK is set the caller is optimistically | |
4023 | * trying to cache the full object within the mappable | |
4024 | * aperture, and *must* have a fallback in place for | |
4025 | * situations where we cannot bind the object. We | |
4026 | * can be a little more lax here and use the fallback | |
4027 | * more often to avoid costly migrations of ourselves | |
4028 | * and other objects within the aperture. | |
4029 | * | |
4030 | * Half-the-aperture is used as a simple heuristic. | |
4031 | * More interesting would to do search for a free | |
4032 | * block prior to making the commitment to unbind. | |
4033 | * That caters for the self-harm case, and with a | |
4034 | * little more heuristics (e.g. NOFAULT, NOEVICT) | |
4035 | * we could try to minimise harm to others. | |
4036 | */ | |
4037 | if (flags & PIN_NONBLOCK && | |
944397f0 | 4038 | vma->fence_size > dev_priv->ggtt.mappable_end / 2) |
ad16d2ed CW |
4039 | return ERR_PTR(-ENOSPC); |
4040 | } | |
4041 | ||
59bfa124 CW |
4042 | WARN(i915_vma_is_pinned(vma), |
4043 | "bo is already pinned in ggtt with incorrect alignment:" | |
05a20d09 CW |
4044 | " offset=%08x, req.alignment=%llx," |
4045 | " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n", | |
4046 | i915_ggtt_offset(vma), alignment, | |
59bfa124 | 4047 | !!(flags & PIN_MAPPABLE), |
05a20d09 | 4048 | i915_vma_is_map_and_fenceable(vma)); |
59bfa124 CW |
4049 | ret = i915_vma_unbind(vma); |
4050 | if (ret) | |
058d88c4 | 4051 | return ERR_PTR(ret); |
59bfa124 CW |
4052 | } |
4053 | ||
058d88c4 CW |
4054 | ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); |
4055 | if (ret) | |
4056 | return ERR_PTR(ret); | |
ec7adb6e | 4057 | |
058d88c4 | 4058 | return vma; |
673a394b EA |
4059 | } |
4060 | ||
edf6b76f | 4061 | static __always_inline unsigned int __busy_read_flag(unsigned int id) |
3fdc13c7 CW |
4062 | { |
4063 | /* Note that we could alias engines in the execbuf API, but | |
4064 | * that would be very unwise as it prevents userspace from | |
4065 | * fine control over engine selection. Ahem. | |
4066 | * | |
4067 | * This should be something like EXEC_MAX_ENGINE instead of | |
4068 | * I915_NUM_ENGINES. | |
4069 | */ | |
4070 | BUILD_BUG_ON(I915_NUM_ENGINES > 16); | |
4071 | return 0x10000 << id; | |
4072 | } | |
4073 | ||
4074 | static __always_inline unsigned int __busy_write_id(unsigned int id) | |
4075 | { | |
70cb472c CW |
4076 | /* The uABI guarantees an active writer is also amongst the read |
4077 | * engines. This would be true if we accessed the activity tracking | |
4078 | * under the lock, but as we perform the lookup of the object and | |
4079 | * its activity locklessly we can not guarantee that the last_write | |
4080 | * being active implies that we have set the same engine flag from | |
4081 | * last_read - hence we always set both read and write busy for | |
4082 | * last_write. | |
4083 | */ | |
4084 | return id | __busy_read_flag(id); | |
3fdc13c7 CW |
4085 | } |
4086 | ||
edf6b76f | 4087 | static __always_inline unsigned int |
d07f0e59 | 4088 | __busy_set_if_active(const struct dma_fence *fence, |
3fdc13c7 CW |
4089 | unsigned int (*flag)(unsigned int id)) |
4090 | { | |
d07f0e59 | 4091 | struct drm_i915_gem_request *rq; |
3fdc13c7 | 4092 | |
d07f0e59 CW |
4093 | /* We have to check the current hw status of the fence as the uABI |
4094 | * guarantees forward progress. We could rely on the idle worker | |
4095 | * to eventually flush us, but to minimise latency just ask the | |
4096 | * hardware. | |
1255501d | 4097 | * |
d07f0e59 | 4098 | * Note we only report on the status of native fences. |
1255501d | 4099 | */ |
d07f0e59 CW |
4100 | if (!dma_fence_is_i915(fence)) |
4101 | return 0; | |
4102 | ||
4103 | /* opencode to_request() in order to avoid const warnings */ | |
4104 | rq = container_of(fence, struct drm_i915_gem_request, fence); | |
4105 | if (i915_gem_request_completed(rq)) | |
4106 | return 0; | |
4107 | ||
1d39f281 | 4108 | return flag(rq->engine->uabi_id); |
3fdc13c7 CW |
4109 | } |
4110 | ||
edf6b76f | 4111 | static __always_inline unsigned int |
d07f0e59 | 4112 | busy_check_reader(const struct dma_fence *fence) |
3fdc13c7 | 4113 | { |
d07f0e59 | 4114 | return __busy_set_if_active(fence, __busy_read_flag); |
3fdc13c7 CW |
4115 | } |
4116 | ||
edf6b76f | 4117 | static __always_inline unsigned int |
d07f0e59 | 4118 | busy_check_writer(const struct dma_fence *fence) |
3fdc13c7 | 4119 | { |
d07f0e59 CW |
4120 | if (!fence) |
4121 | return 0; | |
4122 | ||
4123 | return __busy_set_if_active(fence, __busy_write_id); | |
3fdc13c7 CW |
4124 | } |
4125 | ||
673a394b EA |
4126 | int |
4127 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4128 | struct drm_file *file) |
673a394b EA |
4129 | { |
4130 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4131 | struct drm_i915_gem_object *obj; |
d07f0e59 CW |
4132 | struct reservation_object_list *list; |
4133 | unsigned int seq; | |
fbbd37b3 | 4134 | int err; |
673a394b | 4135 | |
d07f0e59 | 4136 | err = -ENOENT; |
fbbd37b3 CW |
4137 | rcu_read_lock(); |
4138 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
d07f0e59 | 4139 | if (!obj) |
fbbd37b3 | 4140 | goto out; |
d1b851fc | 4141 | |
d07f0e59 CW |
4142 | /* A discrepancy here is that we do not report the status of |
4143 | * non-i915 fences, i.e. even though we may report the object as idle, | |
4144 | * a call to set-domain may still stall waiting for foreign rendering. | |
4145 | * This also means that wait-ioctl may report an object as busy, | |
4146 | * where busy-ioctl considers it idle. | |
4147 | * | |
4148 | * We trade the ability to warn of foreign fences to report on which | |
4149 | * i915 engines are active for the object. | |
4150 | * | |
4151 | * Alternatively, we can trade that extra information on read/write | |
4152 | * activity with | |
4153 | * args->busy = | |
4154 | * !reservation_object_test_signaled_rcu(obj->resv, true); | |
4155 | * to report the overall busyness. This is what the wait-ioctl does. | |
4156 | * | |
4157 | */ | |
4158 | retry: | |
4159 | seq = raw_read_seqcount(&obj->resv->seq); | |
426960be | 4160 | |
d07f0e59 CW |
4161 | /* Translate the exclusive fence to the READ *and* WRITE engine */ |
4162 | args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl)); | |
3fdc13c7 | 4163 | |
d07f0e59 CW |
4164 | /* Translate shared fences to READ set of engines */ |
4165 | list = rcu_dereference(obj->resv->fence); | |
4166 | if (list) { | |
4167 | unsigned int shared_count = list->shared_count, i; | |
3fdc13c7 | 4168 | |
d07f0e59 CW |
4169 | for (i = 0; i < shared_count; ++i) { |
4170 | struct dma_fence *fence = | |
4171 | rcu_dereference(list->shared[i]); | |
4172 | ||
4173 | args->busy |= busy_check_reader(fence); | |
4174 | } | |
426960be | 4175 | } |
673a394b | 4176 | |
d07f0e59 CW |
4177 | if (args->busy && read_seqcount_retry(&obj->resv->seq, seq)) |
4178 | goto retry; | |
4179 | ||
4180 | err = 0; | |
fbbd37b3 CW |
4181 | out: |
4182 | rcu_read_unlock(); | |
4183 | return err; | |
673a394b EA |
4184 | } |
4185 | ||
4186 | int | |
4187 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4188 | struct drm_file *file_priv) | |
4189 | { | |
0206e353 | 4190 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4191 | } |
4192 | ||
3ef94daa CW |
4193 | int |
4194 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4195 | struct drm_file *file_priv) | |
4196 | { | |
fac5e23e | 4197 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 4198 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4199 | struct drm_i915_gem_object *obj; |
1233e2db | 4200 | int err; |
3ef94daa CW |
4201 | |
4202 | switch (args->madv) { | |
4203 | case I915_MADV_DONTNEED: | |
4204 | case I915_MADV_WILLNEED: | |
4205 | break; | |
4206 | default: | |
4207 | return -EINVAL; | |
4208 | } | |
4209 | ||
03ac0642 | 4210 | obj = i915_gem_object_lookup(file_priv, args->handle); |
1233e2db CW |
4211 | if (!obj) |
4212 | return -ENOENT; | |
4213 | ||
4214 | err = mutex_lock_interruptible(&obj->mm.lock); | |
4215 | if (err) | |
4216 | goto out; | |
3ef94daa | 4217 | |
a4f5ea64 | 4218 | if (obj->mm.pages && |
3e510a8e | 4219 | i915_gem_object_is_tiled(obj) && |
656bfa3a | 4220 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
bc0629a7 CW |
4221 | if (obj->mm.madv == I915_MADV_WILLNEED) { |
4222 | GEM_BUG_ON(!obj->mm.quirked); | |
a4f5ea64 | 4223 | __i915_gem_object_unpin_pages(obj); |
bc0629a7 CW |
4224 | obj->mm.quirked = false; |
4225 | } | |
4226 | if (args->madv == I915_MADV_WILLNEED) { | |
2c3a3f44 | 4227 | GEM_BUG_ON(obj->mm.quirked); |
a4f5ea64 | 4228 | __i915_gem_object_pin_pages(obj); |
bc0629a7 CW |
4229 | obj->mm.quirked = true; |
4230 | } | |
656bfa3a DV |
4231 | } |
4232 | ||
a4f5ea64 CW |
4233 | if (obj->mm.madv != __I915_MADV_PURGED) |
4234 | obj->mm.madv = args->madv; | |
3ef94daa | 4235 | |
6c085a72 | 4236 | /* if the object is no longer attached, discard its backing storage */ |
a4f5ea64 | 4237 | if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages) |
2d7ef395 CW |
4238 | i915_gem_object_truncate(obj); |
4239 | ||
a4f5ea64 | 4240 | args->retained = obj->mm.madv != __I915_MADV_PURGED; |
1233e2db | 4241 | mutex_unlock(&obj->mm.lock); |
bb6baf76 | 4242 | |
1233e2db | 4243 | out: |
f8c417cd | 4244 | i915_gem_object_put(obj); |
1233e2db | 4245 | return err; |
3ef94daa CW |
4246 | } |
4247 | ||
5b8c8aec CW |
4248 | static void |
4249 | frontbuffer_retire(struct i915_gem_active *active, | |
4250 | struct drm_i915_gem_request *request) | |
4251 | { | |
4252 | struct drm_i915_gem_object *obj = | |
4253 | container_of(active, typeof(*obj), frontbuffer_write); | |
4254 | ||
d59b21ec | 4255 | intel_fb_obj_flush(obj, ORIGIN_CS); |
5b8c8aec CW |
4256 | } |
4257 | ||
37e680a1 CW |
4258 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4259 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4260 | { |
1233e2db CW |
4261 | mutex_init(&obj->mm.lock); |
4262 | ||
56cea323 | 4263 | INIT_LIST_HEAD(&obj->global_link); |
275f039d | 4264 | INIT_LIST_HEAD(&obj->userfault_link); |
2f633156 | 4265 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4266 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4267 | |
37e680a1 CW |
4268 | obj->ops = ops; |
4269 | ||
d07f0e59 CW |
4270 | reservation_object_init(&obj->__builtin_resv); |
4271 | obj->resv = &obj->__builtin_resv; | |
4272 | ||
50349247 | 4273 | obj->frontbuffer_ggtt_origin = ORIGIN_GTT; |
5b8c8aec | 4274 | init_request_active(&obj->frontbuffer_write, frontbuffer_retire); |
a4f5ea64 CW |
4275 | |
4276 | obj->mm.madv = I915_MADV_WILLNEED; | |
4277 | INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN); | |
4278 | mutex_init(&obj->mm.get_page.lock); | |
0327d6ba | 4279 | |
f19ec8cb | 4280 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
4281 | } |
4282 | ||
37e680a1 | 4283 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3599a91c TU |
4284 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE | |
4285 | I915_GEM_OBJECT_IS_SHRINKABLE, | |
7c55e2c5 | 4286 | |
37e680a1 CW |
4287 | .get_pages = i915_gem_object_get_pages_gtt, |
4288 | .put_pages = i915_gem_object_put_pages_gtt, | |
7c55e2c5 CW |
4289 | |
4290 | .pwrite = i915_gem_object_pwrite_gtt, | |
37e680a1 CW |
4291 | }; |
4292 | ||
b4bcbe2a | 4293 | struct drm_i915_gem_object * |
12d79d78 | 4294 | i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) |
ac52bc56 | 4295 | { |
c397b908 | 4296 | struct drm_i915_gem_object *obj; |
5949eac4 | 4297 | struct address_space *mapping; |
1a240d4d | 4298 | gfp_t mask; |
fe3db79b | 4299 | int ret; |
ac52bc56 | 4300 | |
b4bcbe2a CW |
4301 | /* There is a prevalence of the assumption that we fit the object's |
4302 | * page count inside a 32bit _signed_ variable. Let's document this and | |
4303 | * catch if we ever need to fix it. In the meantime, if you do spot | |
4304 | * such a local variable, please consider fixing! | |
4305 | */ | |
7a3ee5de | 4306 | if (size >> PAGE_SHIFT > INT_MAX) |
b4bcbe2a CW |
4307 | return ERR_PTR(-E2BIG); |
4308 | ||
4309 | if (overflows_type(size, obj->base.size)) | |
4310 | return ERR_PTR(-E2BIG); | |
4311 | ||
187685cb | 4312 | obj = i915_gem_object_alloc(dev_priv); |
c397b908 | 4313 | if (obj == NULL) |
fe3db79b | 4314 | return ERR_PTR(-ENOMEM); |
673a394b | 4315 | |
12d79d78 | 4316 | ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size); |
fe3db79b CW |
4317 | if (ret) |
4318 | goto fail; | |
673a394b | 4319 | |
bed1ea95 | 4320 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
c0f86832 | 4321 | if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) { |
bed1ea95 CW |
4322 | /* 965gm cannot relocate objects above 4GiB. */ |
4323 | mask &= ~__GFP_HIGHMEM; | |
4324 | mask |= __GFP_DMA32; | |
4325 | } | |
4326 | ||
93c76a3d | 4327 | mapping = obj->base.filp->f_mapping; |
bed1ea95 | 4328 | mapping_set_gfp_mask(mapping, mask); |
4846bf0c | 4329 | GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM)); |
5949eac4 | 4330 | |
37e680a1 | 4331 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4332 | |
c397b908 DV |
4333 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4334 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4335 | |
0031fb96 | 4336 | if (HAS_LLC(dev_priv)) { |
3d29b842 | 4337 | /* On some devices, we can have the GPU use the LLC (the CPU |
a1871112 EA |
4338 | * cache) for about a 10% performance improvement |
4339 | * compared to uncached. Graphics requests other than | |
4340 | * display scanout are coherent with the CPU in | |
4341 | * accessing this cache. This means in this mode we | |
4342 | * don't need to clflush on the CPU side, and on the | |
4343 | * GPU side we only need to flush internal caches to | |
4344 | * get data visible to the CPU. | |
4345 | * | |
4346 | * However, we maintain the display planes as UC, and so | |
4347 | * need to rebind when first used as such. | |
4348 | */ | |
4349 | obj->cache_level = I915_CACHE_LLC; | |
4350 | } else | |
4351 | obj->cache_level = I915_CACHE_NONE; | |
4352 | ||
7fc92e96 CW |
4353 | obj->cache_coherent = i915_gem_object_is_coherent(obj); |
4354 | obj->cache_dirty = !obj->cache_coherent; | |
e27ab73d | 4355 | |
d861e338 DV |
4356 | trace_i915_gem_object_create(obj); |
4357 | ||
05394f39 | 4358 | return obj; |
fe3db79b CW |
4359 | |
4360 | fail: | |
4361 | i915_gem_object_free(obj); | |
fe3db79b | 4362 | return ERR_PTR(ret); |
c397b908 DV |
4363 | } |
4364 | ||
340fbd8c CW |
4365 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4366 | { | |
4367 | /* If we are the last user of the backing storage (be it shmemfs | |
4368 | * pages or stolen etc), we know that the pages are going to be | |
4369 | * immediately released. In this case, we can then skip copying | |
4370 | * back the contents from the GPU. | |
4371 | */ | |
4372 | ||
a4f5ea64 | 4373 | if (obj->mm.madv != I915_MADV_WILLNEED) |
340fbd8c CW |
4374 | return false; |
4375 | ||
4376 | if (obj->base.filp == NULL) | |
4377 | return true; | |
4378 | ||
4379 | /* At first glance, this looks racy, but then again so would be | |
4380 | * userspace racing mmap against close. However, the first external | |
4381 | * reference to the filp can only be obtained through the | |
4382 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4383 | * acquiring such a reference whilst we are in the middle of | |
4384 | * freeing the object. | |
4385 | */ | |
4386 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4387 | } | |
4388 | ||
fbbd37b3 CW |
4389 | static void __i915_gem_free_objects(struct drm_i915_private *i915, |
4390 | struct llist_node *freed) | |
673a394b | 4391 | { |
fbbd37b3 | 4392 | struct drm_i915_gem_object *obj, *on; |
673a394b | 4393 | |
fbbd37b3 CW |
4394 | mutex_lock(&i915->drm.struct_mutex); |
4395 | intel_runtime_pm_get(i915); | |
4396 | llist_for_each_entry(obj, freed, freed) { | |
4397 | struct i915_vma *vma, *vn; | |
4398 | ||
4399 | trace_i915_gem_object_destroy(obj); | |
4400 | ||
4401 | GEM_BUG_ON(i915_gem_object_is_active(obj)); | |
4402 | list_for_each_entry_safe(vma, vn, | |
4403 | &obj->vma_list, obj_link) { | |
fbbd37b3 CW |
4404 | GEM_BUG_ON(i915_vma_is_active(vma)); |
4405 | vma->flags &= ~I915_VMA_PIN_MASK; | |
4406 | i915_vma_close(vma); | |
4407 | } | |
db6c2b41 CW |
4408 | GEM_BUG_ON(!list_empty(&obj->vma_list)); |
4409 | GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree)); | |
fbbd37b3 | 4410 | |
56cea323 | 4411 | list_del(&obj->global_link); |
fbbd37b3 CW |
4412 | } |
4413 | intel_runtime_pm_put(i915); | |
4414 | mutex_unlock(&i915->drm.struct_mutex); | |
4415 | ||
f2be9d68 CW |
4416 | cond_resched(); |
4417 | ||
fbbd37b3 CW |
4418 | llist_for_each_entry_safe(obj, on, freed, freed) { |
4419 | GEM_BUG_ON(obj->bind_count); | |
4420 | GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits)); | |
4421 | ||
4422 | if (obj->ops->release) | |
4423 | obj->ops->release(obj); | |
f65c9168 | 4424 | |
fbbd37b3 CW |
4425 | if (WARN_ON(i915_gem_object_has_pinned_pages(obj))) |
4426 | atomic_set(&obj->mm.pages_pin_count, 0); | |
548625ee | 4427 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
fbbd37b3 CW |
4428 | GEM_BUG_ON(obj->mm.pages); |
4429 | ||
4430 | if (obj->base.import_attach) | |
4431 | drm_prime_gem_destroy(&obj->base, NULL); | |
4432 | ||
d07f0e59 | 4433 | reservation_object_fini(&obj->__builtin_resv); |
fbbd37b3 CW |
4434 | drm_gem_object_release(&obj->base); |
4435 | i915_gem_info_remove_obj(i915, obj->base.size); | |
4436 | ||
4437 | kfree(obj->bit_17); | |
4438 | i915_gem_object_free(obj); | |
4439 | } | |
4440 | } | |
4441 | ||
4442 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915) | |
4443 | { | |
4444 | struct llist_node *freed; | |
4445 | ||
4446 | freed = llist_del_all(&i915->mm.free_list); | |
4447 | if (unlikely(freed)) | |
4448 | __i915_gem_free_objects(i915, freed); | |
4449 | } | |
4450 | ||
4451 | static void __i915_gem_free_work(struct work_struct *work) | |
4452 | { | |
4453 | struct drm_i915_private *i915 = | |
4454 | container_of(work, struct drm_i915_private, mm.free_work); | |
4455 | struct llist_node *freed; | |
26e12f89 | 4456 | |
b1f788c6 CW |
4457 | /* All file-owned VMA should have been released by this point through |
4458 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
4459 | * However, the object may also be bound into the global GTT (e.g. | |
4460 | * older GPUs without per-process support, or for direct access through | |
4461 | * the GTT either for the user or for scanout). Those VMA still need to | |
4462 | * unbound now. | |
4463 | */ | |
1488fc08 | 4464 | |
5ad08be7 | 4465 | while ((freed = llist_del_all(&i915->mm.free_list))) { |
fbbd37b3 | 4466 | __i915_gem_free_objects(i915, freed); |
5ad08be7 CW |
4467 | if (need_resched()) |
4468 | break; | |
4469 | } | |
fbbd37b3 | 4470 | } |
a071fa00 | 4471 | |
fbbd37b3 CW |
4472 | static void __i915_gem_free_object_rcu(struct rcu_head *head) |
4473 | { | |
4474 | struct drm_i915_gem_object *obj = | |
4475 | container_of(head, typeof(*obj), rcu); | |
4476 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
4477 | ||
4478 | /* We can't simply use call_rcu() from i915_gem_free_object() | |
4479 | * as we need to block whilst unbinding, and the call_rcu | |
4480 | * task may be called from softirq context. So we take a | |
4481 | * detour through a worker. | |
4482 | */ | |
4483 | if (llist_add(&obj->freed, &i915->mm.free_list)) | |
4484 | schedule_work(&i915->mm.free_work); | |
4485 | } | |
656bfa3a | 4486 | |
fbbd37b3 CW |
4487 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
4488 | { | |
4489 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); | |
a4f5ea64 | 4490 | |
bc0629a7 CW |
4491 | if (obj->mm.quirked) |
4492 | __i915_gem_object_unpin_pages(obj); | |
4493 | ||
340fbd8c | 4494 | if (discard_backing_storage(obj)) |
a4f5ea64 | 4495 | obj->mm.madv = I915_MADV_DONTNEED; |
de151cf6 | 4496 | |
fbbd37b3 CW |
4497 | /* Before we free the object, make sure any pure RCU-only |
4498 | * read-side critical sections are complete, e.g. | |
4499 | * i915_gem_busy_ioctl(). For the corresponding synchronized | |
4500 | * lookup see i915_gem_object_lookup_rcu(). | |
4501 | */ | |
4502 | call_rcu(&obj->rcu, __i915_gem_free_object_rcu); | |
673a394b EA |
4503 | } |
4504 | ||
f8a7fde4 CW |
4505 | void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj) |
4506 | { | |
4507 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
4508 | ||
4509 | GEM_BUG_ON(i915_gem_object_has_active_reference(obj)); | |
4510 | if (i915_gem_object_is_active(obj)) | |
4511 | i915_gem_object_set_active_reference(obj); | |
4512 | else | |
4513 | i915_gem_object_put(obj); | |
4514 | } | |
4515 | ||
3033acab CW |
4516 | static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv) |
4517 | { | |
4518 | struct intel_engine_cs *engine; | |
4519 | enum intel_engine_id id; | |
4520 | ||
4521 | for_each_engine(engine, dev_priv, id) | |
f131e356 CW |
4522 | GEM_BUG_ON(engine->last_retired_context && |
4523 | !i915_gem_context_is_kernel(engine->last_retired_context)); | |
3033acab CW |
4524 | } |
4525 | ||
24145517 CW |
4526 | void i915_gem_sanitize(struct drm_i915_private *i915) |
4527 | { | |
4528 | /* | |
4529 | * If we inherit context state from the BIOS or earlier occupants | |
4530 | * of the GPU, the GPU may be in an inconsistent state when we | |
4531 | * try to take over. The only way to remove the earlier state | |
4532 | * is by resetting. However, resetting on earlier gen is tricky as | |
4533 | * it may impact the display and we are uncertain about the stability | |
ea117b8d | 4534 | * of the reset, so this could be applied to even earlier gen. |
24145517 | 4535 | */ |
ea117b8d | 4536 | if (INTEL_GEN(i915) >= 5) { |
24145517 CW |
4537 | int reset = intel_gpu_reset(i915, ALL_ENGINES); |
4538 | WARN_ON(reset && reset != -ENODEV); | |
4539 | } | |
4540 | } | |
4541 | ||
bf9e8429 | 4542 | int i915_gem_suspend(struct drm_i915_private *dev_priv) |
29105ccc | 4543 | { |
bf9e8429 | 4544 | struct drm_device *dev = &dev_priv->drm; |
dcff85c8 | 4545 | int ret; |
28dfe52a | 4546 | |
c998e8a0 | 4547 | intel_runtime_pm_get(dev_priv); |
54b4f68f CW |
4548 | intel_suspend_gt_powersave(dev_priv); |
4549 | ||
45c5f202 | 4550 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4551 | |
4552 | /* We have to flush all the executing contexts to main memory so | |
4553 | * that they can saved in the hibernation image. To ensure the last | |
4554 | * context image is coherent, we have to switch away from it. That | |
4555 | * leaves the dev_priv->kernel_context still active when | |
4556 | * we actually suspend, and its image in memory may not match the GPU | |
4557 | * state. Fortunately, the kernel_context is disposable and we do | |
4558 | * not rely on its state. | |
4559 | */ | |
4560 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4561 | if (ret) | |
c998e8a0 | 4562 | goto err_unlock; |
5ab57c70 | 4563 | |
22dd3bb9 CW |
4564 | ret = i915_gem_wait_for_idle(dev_priv, |
4565 | I915_WAIT_INTERRUPTIBLE | | |
4566 | I915_WAIT_LOCKED); | |
f7403347 | 4567 | if (ret) |
c998e8a0 | 4568 | goto err_unlock; |
f7403347 | 4569 | |
3033acab | 4570 | assert_kernel_context_is_current(dev_priv); |
829a0af2 | 4571 | i915_gem_contexts_lost(dev_priv); |
45c5f202 CW |
4572 | mutex_unlock(&dev->struct_mutex); |
4573 | ||
63987bfe SAK |
4574 | intel_guc_suspend(dev_priv); |
4575 | ||
737b1506 | 4576 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 | 4577 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
bdeb9785 CW |
4578 | |
4579 | /* As the idle_work is rearming if it detects a race, play safe and | |
4580 | * repeat the flush until it is definitely idle. | |
4581 | */ | |
4582 | while (flush_delayed_work(&dev_priv->gt.idle_work)) | |
4583 | ; | |
4584 | ||
bdcf120b CW |
4585 | /* Assert that we sucessfully flushed all the work and |
4586 | * reset the GPU back to its idle, low power state. | |
4587 | */ | |
67d97da3 | 4588 | WARN_ON(dev_priv->gt.awake); |
05425249 | 4589 | WARN_ON(!intel_engines_are_idle(dev_priv)); |
bdcf120b | 4590 | |
1c777c5d ID |
4591 | /* |
4592 | * Neither the BIOS, ourselves or any other kernel | |
4593 | * expects the system to be in execlists mode on startup, | |
4594 | * so we need to reset the GPU back to legacy mode. And the only | |
4595 | * known way to disable logical contexts is through a GPU reset. | |
4596 | * | |
4597 | * So in order to leave the system in a known default configuration, | |
4598 | * always reset the GPU upon unload and suspend. Afterwards we then | |
4599 | * clean up the GEM state tracking, flushing off the requests and | |
4600 | * leaving the system in a known idle state. | |
4601 | * | |
4602 | * Note that is of the upmost importance that the GPU is idle and | |
4603 | * all stray writes are flushed *before* we dismantle the backing | |
4604 | * storage for the pinned objects. | |
4605 | * | |
4606 | * However, since we are uncertain that resetting the GPU on older | |
4607 | * machines is a good idea, we don't - just in case it leaves the | |
4608 | * machine in an unusable condition. | |
4609 | */ | |
24145517 | 4610 | i915_gem_sanitize(dev_priv); |
c998e8a0 | 4611 | goto out_rpm_put; |
1c777c5d | 4612 | |
c998e8a0 | 4613 | err_unlock: |
45c5f202 | 4614 | mutex_unlock(&dev->struct_mutex); |
c998e8a0 CW |
4615 | out_rpm_put: |
4616 | intel_runtime_pm_put(dev_priv); | |
45c5f202 | 4617 | return ret; |
673a394b EA |
4618 | } |
4619 | ||
bf9e8429 | 4620 | void i915_gem_resume(struct drm_i915_private *dev_priv) |
5ab57c70 | 4621 | { |
bf9e8429 | 4622 | struct drm_device *dev = &dev_priv->drm; |
5ab57c70 | 4623 | |
31ab49ab ID |
4624 | WARN_ON(dev_priv->gt.awake); |
4625 | ||
5ab57c70 | 4626 | mutex_lock(&dev->struct_mutex); |
275a991c | 4627 | i915_gem_restore_gtt_mappings(dev_priv); |
5ab57c70 CW |
4628 | |
4629 | /* As we didn't flush the kernel context before suspend, we cannot | |
4630 | * guarantee that the context image is complete. So let's just reset | |
4631 | * it and start again. | |
4632 | */ | |
821ed7df | 4633 | dev_priv->gt.resume(dev_priv); |
5ab57c70 CW |
4634 | |
4635 | mutex_unlock(&dev->struct_mutex); | |
4636 | } | |
4637 | ||
c6be607a | 4638 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) |
f691e2f4 | 4639 | { |
c6be607a | 4640 | if (INTEL_GEN(dev_priv) < 5 || |
f691e2f4 DV |
4641 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4642 | return; | |
4643 | ||
4644 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4645 | DISP_TILE_SURFACE_SWIZZLING); | |
4646 | ||
5db94019 | 4647 | if (IS_GEN5(dev_priv)) |
11782b02 DV |
4648 | return; |
4649 | ||
f691e2f4 | 4650 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
5db94019 | 4651 | if (IS_GEN6(dev_priv)) |
6b26c86d | 4652 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
5db94019 | 4653 | else if (IS_GEN7(dev_priv)) |
6b26c86d | 4654 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
5db94019 | 4655 | else if (IS_GEN8(dev_priv)) |
31a5336e | 4656 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
8782e26c BW |
4657 | else |
4658 | BUG(); | |
f691e2f4 | 4659 | } |
e21af88d | 4660 | |
50a0bc90 | 4661 | static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base) |
81e7f200 | 4662 | { |
81e7f200 VS |
4663 | I915_WRITE(RING_CTL(base), 0); |
4664 | I915_WRITE(RING_HEAD(base), 0); | |
4665 | I915_WRITE(RING_TAIL(base), 0); | |
4666 | I915_WRITE(RING_START(base), 0); | |
4667 | } | |
4668 | ||
50a0bc90 | 4669 | static void init_unused_rings(struct drm_i915_private *dev_priv) |
81e7f200 | 4670 | { |
50a0bc90 TU |
4671 | if (IS_I830(dev_priv)) { |
4672 | init_unused_ring(dev_priv, PRB1_BASE); | |
4673 | init_unused_ring(dev_priv, SRB0_BASE); | |
4674 | init_unused_ring(dev_priv, SRB1_BASE); | |
4675 | init_unused_ring(dev_priv, SRB2_BASE); | |
4676 | init_unused_ring(dev_priv, SRB3_BASE); | |
4677 | } else if (IS_GEN2(dev_priv)) { | |
4678 | init_unused_ring(dev_priv, SRB0_BASE); | |
4679 | init_unused_ring(dev_priv, SRB1_BASE); | |
4680 | } else if (IS_GEN3(dev_priv)) { | |
4681 | init_unused_ring(dev_priv, PRB1_BASE); | |
4682 | init_unused_ring(dev_priv, PRB2_BASE); | |
81e7f200 VS |
4683 | } |
4684 | } | |
4685 | ||
20a8a74a | 4686 | static int __i915_gem_restart_engines(void *data) |
4fc7c971 | 4687 | { |
20a8a74a | 4688 | struct drm_i915_private *i915 = data; |
e2f80391 | 4689 | struct intel_engine_cs *engine; |
3b3f1650 | 4690 | enum intel_engine_id id; |
20a8a74a CW |
4691 | int err; |
4692 | ||
4693 | for_each_engine(engine, i915, id) { | |
4694 | err = engine->init_hw(engine); | |
4695 | if (err) | |
4696 | return err; | |
4697 | } | |
4698 | ||
4699 | return 0; | |
4700 | } | |
4701 | ||
4702 | int i915_gem_init_hw(struct drm_i915_private *dev_priv) | |
4703 | { | |
d200cda6 | 4704 | int ret; |
4fc7c971 | 4705 | |
de867c20 CW |
4706 | dev_priv->gt.last_init_time = ktime_get(); |
4707 | ||
5e4f5189 CW |
4708 | /* Double layer security blanket, see i915_gem_init() */ |
4709 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4710 | ||
0031fb96 | 4711 | if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4712 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4713 | |
772c2a51 | 4714 | if (IS_HASWELL(dev_priv)) |
50a0bc90 | 4715 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ? |
0bf21347 | 4716 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
9435373e | 4717 | |
6e266956 | 4718 | if (HAS_PCH_NOP(dev_priv)) { |
fd6b8f43 | 4719 | if (IS_IVYBRIDGE(dev_priv)) { |
6ba844b0 DV |
4720 | u32 temp = I915_READ(GEN7_MSG_CTL); |
4721 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4722 | I915_WRITE(GEN7_MSG_CTL, temp); | |
c6be607a | 4723 | } else if (INTEL_GEN(dev_priv) >= 7) { |
6ba844b0 DV |
4724 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
4725 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4726 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4727 | } | |
88a2b2a3 BW |
4728 | } |
4729 | ||
c6be607a | 4730 | i915_gem_init_swizzling(dev_priv); |
4fc7c971 | 4731 | |
d5abdfda DV |
4732 | /* |
4733 | * At least 830 can leave some of the unused rings | |
4734 | * "active" (ie. head != tail) after resume which | |
4735 | * will prevent c3 entry. Makes sure all unused rings | |
4736 | * are totally idle. | |
4737 | */ | |
50a0bc90 | 4738 | init_unused_rings(dev_priv); |
d5abdfda | 4739 | |
ed54c1a1 | 4740 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4741 | |
c6be607a | 4742 | ret = i915_ppgtt_init_hw(dev_priv); |
4ad2fd88 JH |
4743 | if (ret) { |
4744 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4745 | goto out; | |
4746 | } | |
4747 | ||
4748 | /* Need to do basic initialisation of all rings first: */ | |
20a8a74a CW |
4749 | ret = __i915_gem_restart_engines(dev_priv); |
4750 | if (ret) | |
4751 | goto out; | |
99433931 | 4752 | |
bf9e8429 | 4753 | intel_mocs_init_l3cc_table(dev_priv); |
0ccdacf6 | 4754 | |
b8991403 OM |
4755 | /* We can't enable contexts until all firmware is loaded */ |
4756 | ret = intel_uc_init_hw(dev_priv); | |
4757 | if (ret) | |
4758 | goto out; | |
33a732f4 | 4759 | |
5e4f5189 CW |
4760 | out: |
4761 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4762 | return ret; |
8187a2b7 ZN |
4763 | } |
4764 | ||
39df9190 CW |
4765 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4766 | { | |
4767 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4768 | return false; | |
4769 | ||
4770 | /* TODO: make semaphores and Execlists play nicely together */ | |
4771 | if (i915.enable_execlists) | |
4772 | return false; | |
4773 | ||
4774 | if (value >= 0) | |
4775 | return value; | |
4776 | ||
39df9190 | 4777 | /* Enable semaphores on SNB when IO remapping is off */ |
80debff8 | 4778 | if (IS_GEN6(dev_priv) && intel_vtd_active()) |
39df9190 | 4779 | return false; |
39df9190 CW |
4780 | |
4781 | return true; | |
4782 | } | |
4783 | ||
bf9e8429 | 4784 | int i915_gem_init(struct drm_i915_private *dev_priv) |
1070a42b | 4785 | { |
1070a42b CW |
4786 | int ret; |
4787 | ||
bf9e8429 | 4788 | mutex_lock(&dev_priv->drm.struct_mutex); |
d62b4892 | 4789 | |
94312828 | 4790 | dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1); |
57822dc6 | 4791 | |
a83014d3 | 4792 | if (!i915.enable_execlists) { |
821ed7df | 4793 | dev_priv->gt.resume = intel_legacy_submission_resume; |
7e37f889 | 4794 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
454afebd | 4795 | } else { |
821ed7df | 4796 | dev_priv->gt.resume = intel_lr_context_resume; |
117897f4 | 4797 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
a83014d3 OM |
4798 | } |
4799 | ||
5e4f5189 CW |
4800 | /* This is just a security blanket to placate dragons. |
4801 | * On some systems, we very sporadically observe that the first TLBs | |
4802 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4803 | * we hold the forcewake during initialisation these problems | |
4804 | * just magically go away. | |
4805 | */ | |
4806 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4807 | ||
8a2421bd CW |
4808 | ret = i915_gem_init_userptr(dev_priv); |
4809 | if (ret) | |
4810 | goto out_unlock; | |
f6b9d5ca CW |
4811 | |
4812 | ret = i915_gem_init_ggtt(dev_priv); | |
4813 | if (ret) | |
4814 | goto out_unlock; | |
d62b4892 | 4815 | |
829a0af2 | 4816 | ret = i915_gem_contexts_init(dev_priv); |
7bcc3777 JN |
4817 | if (ret) |
4818 | goto out_unlock; | |
2fa48d8d | 4819 | |
bf9e8429 | 4820 | ret = intel_engines_init(dev_priv); |
35a57ffb | 4821 | if (ret) |
7bcc3777 | 4822 | goto out_unlock; |
2fa48d8d | 4823 | |
bf9e8429 | 4824 | ret = i915_gem_init_hw(dev_priv); |
60990320 | 4825 | if (ret == -EIO) { |
7e21d648 | 4826 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4827 | * wedged. But we only want to do this where the GPU is angry, |
4828 | * for all other failure, such as an allocation failure, bail. | |
4829 | */ | |
4830 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
821ed7df | 4831 | i915_gem_set_wedged(dev_priv); |
60990320 | 4832 | ret = 0; |
1070a42b | 4833 | } |
7bcc3777 JN |
4834 | |
4835 | out_unlock: | |
5e4f5189 | 4836 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
bf9e8429 | 4837 | mutex_unlock(&dev_priv->drm.struct_mutex); |
1070a42b | 4838 | |
60990320 | 4839 | return ret; |
1070a42b CW |
4840 | } |
4841 | ||
24145517 CW |
4842 | void i915_gem_init_mmio(struct drm_i915_private *i915) |
4843 | { | |
4844 | i915_gem_sanitize(i915); | |
4845 | } | |
4846 | ||
8187a2b7 | 4847 | void |
cb15d9f8 | 4848 | i915_gem_cleanup_engines(struct drm_i915_private *dev_priv) |
8187a2b7 | 4849 | { |
e2f80391 | 4850 | struct intel_engine_cs *engine; |
3b3f1650 | 4851 | enum intel_engine_id id; |
8187a2b7 | 4852 | |
3b3f1650 | 4853 | for_each_engine(engine, dev_priv, id) |
117897f4 | 4854 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4855 | } |
4856 | ||
40ae4e16 ID |
4857 | void |
4858 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4859 | { | |
49ef5294 | 4860 | int i; |
40ae4e16 ID |
4861 | |
4862 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4863 | !IS_CHERRYVIEW(dev_priv)) | |
4864 | dev_priv->num_fence_regs = 32; | |
73f67aa8 JN |
4865 | else if (INTEL_INFO(dev_priv)->gen >= 4 || |
4866 | IS_I945G(dev_priv) || IS_I945GM(dev_priv) || | |
4867 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) | |
40ae4e16 ID |
4868 | dev_priv->num_fence_regs = 16; |
4869 | else | |
4870 | dev_priv->num_fence_regs = 8; | |
4871 | ||
c033666a | 4872 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4873 | dev_priv->num_fence_regs = |
4874 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4875 | ||
4876 | /* Initialize fence registers to zero */ | |
49ef5294 CW |
4877 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
4878 | struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i]; | |
4879 | ||
4880 | fence->i915 = dev_priv; | |
4881 | fence->id = i; | |
4882 | list_add_tail(&fence->link, &dev_priv->mm.fence_list); | |
4883 | } | |
4362f4f6 | 4884 | i915_gem_restore_fences(dev_priv); |
40ae4e16 | 4885 | |
4362f4f6 | 4886 | i915_gem_detect_bit_6_swizzle(dev_priv); |
40ae4e16 ID |
4887 | } |
4888 | ||
73cb9701 | 4889 | int |
cb15d9f8 | 4890 | i915_gem_load_init(struct drm_i915_private *dev_priv) |
673a394b | 4891 | { |
a933568e | 4892 | int err = -ENOMEM; |
42dcedd4 | 4893 | |
a933568e TU |
4894 | dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN); |
4895 | if (!dev_priv->objects) | |
73cb9701 | 4896 | goto err_out; |
73cb9701 | 4897 | |
a933568e TU |
4898 | dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN); |
4899 | if (!dev_priv->vmas) | |
73cb9701 | 4900 | goto err_objects; |
73cb9701 | 4901 | |
a933568e TU |
4902 | dev_priv->requests = KMEM_CACHE(drm_i915_gem_request, |
4903 | SLAB_HWCACHE_ALIGN | | |
4904 | SLAB_RECLAIM_ACCOUNT | | |
5f0d5a3a | 4905 | SLAB_TYPESAFE_BY_RCU); |
a933568e | 4906 | if (!dev_priv->requests) |
73cb9701 | 4907 | goto err_vmas; |
73cb9701 | 4908 | |
52e54209 CW |
4909 | dev_priv->dependencies = KMEM_CACHE(i915_dependency, |
4910 | SLAB_HWCACHE_ALIGN | | |
4911 | SLAB_RECLAIM_ACCOUNT); | |
4912 | if (!dev_priv->dependencies) | |
4913 | goto err_requests; | |
4914 | ||
c5cf9a91 CW |
4915 | dev_priv->priorities = KMEM_CACHE(i915_priolist, SLAB_HWCACHE_ALIGN); |
4916 | if (!dev_priv->priorities) | |
4917 | goto err_dependencies; | |
4918 | ||
73cb9701 CW |
4919 | mutex_lock(&dev_priv->drm.struct_mutex); |
4920 | INIT_LIST_HEAD(&dev_priv->gt.timelines); | |
bb89485e | 4921 | err = i915_gem_timeline_init__global(dev_priv); |
73cb9701 CW |
4922 | mutex_unlock(&dev_priv->drm.struct_mutex); |
4923 | if (err) | |
c5cf9a91 | 4924 | goto err_priorities; |
673a394b | 4925 | |
fbbd37b3 CW |
4926 | INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work); |
4927 | init_llist_head(&dev_priv->mm.free_list); | |
6c085a72 CW |
4928 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4929 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4930 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
275f039d | 4931 | INIT_LIST_HEAD(&dev_priv->mm.userfault_list); |
67d97da3 | 4932 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4933 | i915_gem_retire_work_handler); |
67d97da3 | 4934 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4935 | i915_gem_idle_work_handler); |
1f15b76f | 4936 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4937 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4938 | |
6f633402 JL |
4939 | atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); |
4940 | ||
b5add959 | 4941 | spin_lock_init(&dev_priv->fb_tracking.lock); |
73cb9701 CW |
4942 | |
4943 | return 0; | |
4944 | ||
c5cf9a91 CW |
4945 | err_priorities: |
4946 | kmem_cache_destroy(dev_priv->priorities); | |
52e54209 CW |
4947 | err_dependencies: |
4948 | kmem_cache_destroy(dev_priv->dependencies); | |
73cb9701 CW |
4949 | err_requests: |
4950 | kmem_cache_destroy(dev_priv->requests); | |
4951 | err_vmas: | |
4952 | kmem_cache_destroy(dev_priv->vmas); | |
4953 | err_objects: | |
4954 | kmem_cache_destroy(dev_priv->objects); | |
4955 | err_out: | |
4956 | return err; | |
673a394b | 4957 | } |
71acb5eb | 4958 | |
cb15d9f8 | 4959 | void i915_gem_load_cleanup(struct drm_i915_private *dev_priv) |
d64aa096 | 4960 | { |
c4d4c1c6 | 4961 | i915_gem_drain_freed_objects(dev_priv); |
7d5d59e5 | 4962 | WARN_ON(!llist_empty(&dev_priv->mm.free_list)); |
c4d4c1c6 | 4963 | WARN_ON(dev_priv->mm.object_count); |
7d5d59e5 | 4964 | |
ea84aa77 MA |
4965 | mutex_lock(&dev_priv->drm.struct_mutex); |
4966 | i915_gem_timeline_fini(&dev_priv->gt.global_timeline); | |
4967 | WARN_ON(!list_empty(&dev_priv->gt.timelines)); | |
4968 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4969 | ||
c5cf9a91 | 4970 | kmem_cache_destroy(dev_priv->priorities); |
52e54209 | 4971 | kmem_cache_destroy(dev_priv->dependencies); |
d64aa096 ID |
4972 | kmem_cache_destroy(dev_priv->requests); |
4973 | kmem_cache_destroy(dev_priv->vmas); | |
4974 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
4975 | |
4976 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
4977 | rcu_barrier(); | |
d64aa096 ID |
4978 | } |
4979 | ||
6a800eab CW |
4980 | int i915_gem_freeze(struct drm_i915_private *dev_priv) |
4981 | { | |
d0aa301a CW |
4982 | /* Discard all purgeable objects, let userspace recover those as |
4983 | * required after resuming. | |
4984 | */ | |
6a800eab | 4985 | i915_gem_shrink_all(dev_priv); |
6a800eab | 4986 | |
6a800eab CW |
4987 | return 0; |
4988 | } | |
4989 | ||
461fb99c CW |
4990 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4991 | { | |
4992 | struct drm_i915_gem_object *obj; | |
7aab2d53 CW |
4993 | struct list_head *phases[] = { |
4994 | &dev_priv->mm.unbound_list, | |
4995 | &dev_priv->mm.bound_list, | |
4996 | NULL | |
4997 | }, **p; | |
461fb99c CW |
4998 | |
4999 | /* Called just before we write the hibernation image. | |
5000 | * | |
5001 | * We need to update the domain tracking to reflect that the CPU | |
5002 | * will be accessing all the pages to create and restore from the | |
5003 | * hibernation, and so upon restoration those pages will be in the | |
5004 | * CPU domain. | |
5005 | * | |
5006 | * To make sure the hibernation image contains the latest state, | |
5007 | * we update that state just before writing out the image. | |
7aab2d53 CW |
5008 | * |
5009 | * To try and reduce the hibernation image, we manually shrink | |
d0aa301a | 5010 | * the objects as well, see i915_gem_freeze() |
461fb99c CW |
5011 | */ |
5012 | ||
6a800eab | 5013 | i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND); |
17b93c40 | 5014 | i915_gem_drain_freed_objects(dev_priv); |
461fb99c | 5015 | |
d0aa301a | 5016 | mutex_lock(&dev_priv->drm.struct_mutex); |
7aab2d53 | 5017 | for (p = phases; *p; p++) { |
e27ab73d CW |
5018 | list_for_each_entry(obj, *p, global_link) |
5019 | __start_cpu_write(obj); | |
461fb99c | 5020 | } |
6a800eab | 5021 | mutex_unlock(&dev_priv->drm.struct_mutex); |
461fb99c CW |
5022 | |
5023 | return 0; | |
5024 | } | |
5025 | ||
f787a5f5 | 5026 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5027 | { |
f787a5f5 | 5028 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 5029 | struct drm_i915_gem_request *request; |
b962442e EA |
5030 | |
5031 | /* Clean up our request list when the client is going away, so that | |
5032 | * later retire_requests won't dereference our soon-to-be-gone | |
5033 | * file_priv. | |
5034 | */ | |
1c25595f | 5035 | spin_lock(&file_priv->mm.lock); |
c8659efa | 5036 | list_for_each_entry(request, &file_priv->mm.request_list, client_link) |
f787a5f5 | 5037 | request->file_priv = NULL; |
1c25595f | 5038 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 CW |
5039 | } |
5040 | ||
829a0af2 | 5041 | int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file) |
b29c19b6 CW |
5042 | { |
5043 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5044 | int ret; |
b29c19b6 | 5045 | |
c4c29d7b | 5046 | DRM_DEBUG("\n"); |
b29c19b6 CW |
5047 | |
5048 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5049 | if (!file_priv) | |
5050 | return -ENOMEM; | |
5051 | ||
5052 | file->driver_priv = file_priv; | |
829a0af2 | 5053 | file_priv->dev_priv = i915; |
ab0e7ff9 | 5054 | file_priv->file = file; |
b29c19b6 CW |
5055 | |
5056 | spin_lock_init(&file_priv->mm.lock); | |
5057 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 5058 | |
c80ff16e | 5059 | file_priv->bsd_engine = -1; |
de1add36 | 5060 | |
829a0af2 | 5061 | ret = i915_gem_context_open(i915, file); |
e422b888 BW |
5062 | if (ret) |
5063 | kfree(file_priv); | |
b29c19b6 | 5064 | |
e422b888 | 5065 | return ret; |
b29c19b6 CW |
5066 | } |
5067 | ||
b680c37a DV |
5068 | /** |
5069 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
5070 | * @old: current GEM buffer for the frontbuffer slots |
5071 | * @new: new GEM buffer for the frontbuffer slots | |
5072 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
5073 | * |
5074 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5075 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5076 | */ | |
a071fa00 DV |
5077 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5078 | struct drm_i915_gem_object *new, | |
5079 | unsigned frontbuffer_bits) | |
5080 | { | |
faf5bf0a CW |
5081 | /* Control of individual bits within the mask are guarded by |
5082 | * the owning plane->mutex, i.e. we can never see concurrent | |
5083 | * manipulation of individual bits. But since the bitfield as a whole | |
5084 | * is updated using RMW, we need to use atomics in order to update | |
5085 | * the bits. | |
5086 | */ | |
5087 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
5088 | sizeof(atomic_t) * BITS_PER_BYTE); | |
5089 | ||
a071fa00 | 5090 | if (old) { |
faf5bf0a CW |
5091 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
5092 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
5093 | } |
5094 | ||
5095 | if (new) { | |
faf5bf0a CW |
5096 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
5097 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
5098 | } |
5099 | } | |
5100 | ||
ea70299d DG |
5101 | /* Allocate a new GEM object and fill it with the supplied data */ |
5102 | struct drm_i915_gem_object * | |
12d79d78 | 5103 | i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, |
ea70299d DG |
5104 | const void *data, size_t size) |
5105 | { | |
5106 | struct drm_i915_gem_object *obj; | |
be062fa4 CW |
5107 | struct file *file; |
5108 | size_t offset; | |
5109 | int err; | |
ea70299d | 5110 | |
12d79d78 | 5111 | obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE)); |
fe3db79b | 5112 | if (IS_ERR(obj)) |
ea70299d DG |
5113 | return obj; |
5114 | ||
ce8ff099 | 5115 | GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU); |
ea70299d | 5116 | |
be062fa4 CW |
5117 | file = obj->base.filp; |
5118 | offset = 0; | |
5119 | do { | |
5120 | unsigned int len = min_t(typeof(size), size, PAGE_SIZE); | |
5121 | struct page *page; | |
5122 | void *pgdata, *vaddr; | |
ea70299d | 5123 | |
be062fa4 CW |
5124 | err = pagecache_write_begin(file, file->f_mapping, |
5125 | offset, len, 0, | |
5126 | &page, &pgdata); | |
5127 | if (err < 0) | |
5128 | goto fail; | |
ea70299d | 5129 | |
be062fa4 CW |
5130 | vaddr = kmap(page); |
5131 | memcpy(vaddr, data, len); | |
5132 | kunmap(page); | |
5133 | ||
5134 | err = pagecache_write_end(file, file->f_mapping, | |
5135 | offset, len, len, | |
5136 | page, pgdata); | |
5137 | if (err < 0) | |
5138 | goto fail; | |
5139 | ||
5140 | size -= len; | |
5141 | data += len; | |
5142 | offset += len; | |
5143 | } while (size); | |
ea70299d DG |
5144 | |
5145 | return obj; | |
5146 | ||
5147 | fail: | |
f8c417cd | 5148 | i915_gem_object_put(obj); |
be062fa4 | 5149 | return ERR_PTR(err); |
ea70299d | 5150 | } |
96d77634 CW |
5151 | |
5152 | struct scatterlist * | |
5153 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
5154 | unsigned int n, | |
5155 | unsigned int *offset) | |
5156 | { | |
a4f5ea64 | 5157 | struct i915_gem_object_page_iter *iter = &obj->mm.get_page; |
96d77634 CW |
5158 | struct scatterlist *sg; |
5159 | unsigned int idx, count; | |
5160 | ||
5161 | might_sleep(); | |
5162 | GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT); | |
a4f5ea64 | 5163 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
96d77634 CW |
5164 | |
5165 | /* As we iterate forward through the sg, we record each entry in a | |
5166 | * radixtree for quick repeated (backwards) lookups. If we have seen | |
5167 | * this index previously, we will have an entry for it. | |
5168 | * | |
5169 | * Initial lookup is O(N), but this is amortized to O(1) for | |
5170 | * sequential page access (where each new request is consecutive | |
5171 | * to the previous one). Repeated lookups are O(lg(obj->base.size)), | |
5172 | * i.e. O(1) with a large constant! | |
5173 | */ | |
5174 | if (n < READ_ONCE(iter->sg_idx)) | |
5175 | goto lookup; | |
5176 | ||
5177 | mutex_lock(&iter->lock); | |
5178 | ||
5179 | /* We prefer to reuse the last sg so that repeated lookup of this | |
5180 | * (or the subsequent) sg are fast - comparing against the last | |
5181 | * sg is faster than going through the radixtree. | |
5182 | */ | |
5183 | ||
5184 | sg = iter->sg_pos; | |
5185 | idx = iter->sg_idx; | |
5186 | count = __sg_page_count(sg); | |
5187 | ||
5188 | while (idx + count <= n) { | |
5189 | unsigned long exception, i; | |
5190 | int ret; | |
5191 | ||
5192 | /* If we cannot allocate and insert this entry, or the | |
5193 | * individual pages from this range, cancel updating the | |
5194 | * sg_idx so that on this lookup we are forced to linearly | |
5195 | * scan onwards, but on future lookups we will try the | |
5196 | * insertion again (in which case we need to be careful of | |
5197 | * the error return reporting that we have already inserted | |
5198 | * this index). | |
5199 | */ | |
5200 | ret = radix_tree_insert(&iter->radix, idx, sg); | |
5201 | if (ret && ret != -EEXIST) | |
5202 | goto scan; | |
5203 | ||
5204 | exception = | |
5205 | RADIX_TREE_EXCEPTIONAL_ENTRY | | |
5206 | idx << RADIX_TREE_EXCEPTIONAL_SHIFT; | |
5207 | for (i = 1; i < count; i++) { | |
5208 | ret = radix_tree_insert(&iter->radix, idx + i, | |
5209 | (void *)exception); | |
5210 | if (ret && ret != -EEXIST) | |
5211 | goto scan; | |
5212 | } | |
5213 | ||
5214 | idx += count; | |
5215 | sg = ____sg_next(sg); | |
5216 | count = __sg_page_count(sg); | |
5217 | } | |
5218 | ||
5219 | scan: | |
5220 | iter->sg_pos = sg; | |
5221 | iter->sg_idx = idx; | |
5222 | ||
5223 | mutex_unlock(&iter->lock); | |
5224 | ||
5225 | if (unlikely(n < idx)) /* insertion completed by another thread */ | |
5226 | goto lookup; | |
5227 | ||
5228 | /* In case we failed to insert the entry into the radixtree, we need | |
5229 | * to look beyond the current sg. | |
5230 | */ | |
5231 | while (idx + count <= n) { | |
5232 | idx += count; | |
5233 | sg = ____sg_next(sg); | |
5234 | count = __sg_page_count(sg); | |
5235 | } | |
5236 | ||
5237 | *offset = n - idx; | |
5238 | return sg; | |
5239 | ||
5240 | lookup: | |
5241 | rcu_read_lock(); | |
5242 | ||
5243 | sg = radix_tree_lookup(&iter->radix, n); | |
5244 | GEM_BUG_ON(!sg); | |
5245 | ||
5246 | /* If this index is in the middle of multi-page sg entry, | |
5247 | * the radixtree will contain an exceptional entry that points | |
5248 | * to the start of that range. We will return the pointer to | |
5249 | * the base page and the offset of this page within the | |
5250 | * sg entry's range. | |
5251 | */ | |
5252 | *offset = 0; | |
5253 | if (unlikely(radix_tree_exception(sg))) { | |
5254 | unsigned long base = | |
5255 | (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT; | |
5256 | ||
5257 | sg = radix_tree_lookup(&iter->radix, base); | |
5258 | GEM_BUG_ON(!sg); | |
5259 | ||
5260 | *offset = n - base; | |
5261 | } | |
5262 | ||
5263 | rcu_read_unlock(); | |
5264 | ||
5265 | return sg; | |
5266 | } | |
5267 | ||
5268 | struct page * | |
5269 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n) | |
5270 | { | |
5271 | struct scatterlist *sg; | |
5272 | unsigned int offset; | |
5273 | ||
5274 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); | |
5275 | ||
5276 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
5277 | return nth_page(sg_page(sg), offset); | |
5278 | } | |
5279 | ||
5280 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ | |
5281 | struct page * | |
5282 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
5283 | unsigned int n) | |
5284 | { | |
5285 | struct page *page; | |
5286 | ||
5287 | page = i915_gem_object_get_page(obj, n); | |
a4f5ea64 | 5288 | if (!obj->mm.dirty) |
96d77634 CW |
5289 | set_page_dirty(page); |
5290 | ||
5291 | return page; | |
5292 | } | |
5293 | ||
5294 | dma_addr_t | |
5295 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
5296 | unsigned long n) | |
5297 | { | |
5298 | struct scatterlist *sg; | |
5299 | unsigned int offset; | |
5300 | ||
5301 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
5302 | return sg_dma_address(sg) + (offset << PAGE_SHIFT); | |
5303 | } | |
935a2f77 CW |
5304 | |
5305 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
5306 | #include "selftests/scatterlist.c" | |
66d9cb5d | 5307 | #include "selftests/mock_gem_device.c" |
44653988 | 5308 | #include "selftests/huge_gem_object.c" |
8335fd65 | 5309 | #include "selftests/i915_gem_object.c" |
17059450 | 5310 | #include "selftests/i915_gem_coherency.c" |
935a2f77 | 5311 | #endif |