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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
57822dc6 | 32 | #include "i915_gem_clflush.h" |
eb82289a | 33 | #include "i915_vgpu.h" |
1c5d22f7 | 34 | #include "i915_trace.h" |
652c393a | 35 | #include "intel_drv.h" |
5d723d7a | 36 | #include "intel_frontbuffer.h" |
0ccdacf6 | 37 | #include "intel_mocs.h" |
6b5e90f5 | 38 | #include <linux/dma-fence-array.h> |
fe3288b5 | 39 | #include <linux/kthread.h> |
c13d87ea | 40 | #include <linux/reservation.h> |
5949eac4 | 41 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 42 | #include <linux/slab.h> |
20e4933c | 43 | #include <linux/stop_machine.h> |
673a394b | 44 | #include <linux/swap.h> |
79e53945 | 45 | #include <linux/pci.h> |
1286ff73 | 46 | #include <linux/dma-buf.h> |
673a394b | 47 | |
fbbd37b3 | 48 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915); |
61050808 | 49 | |
2c22569b CW |
50 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
51 | { | |
e27ab73d | 52 | if (obj->cache_dirty) |
b50a5371 AS |
53 | return false; |
54 | ||
7fc92e96 | 55 | if (!obj->cache_coherent) |
2c22569b CW |
56 | return true; |
57 | ||
58 | return obj->pin_display; | |
59 | } | |
60 | ||
4f1959ee | 61 | static int |
bb6dc8d9 | 62 | insert_mappable_node(struct i915_ggtt *ggtt, |
4f1959ee AS |
63 | struct drm_mm_node *node, u32 size) |
64 | { | |
65 | memset(node, 0, sizeof(*node)); | |
4e64e553 CW |
66 | return drm_mm_insert_node_in_range(&ggtt->base.mm, node, |
67 | size, 0, I915_COLOR_UNEVICTABLE, | |
68 | 0, ggtt->mappable_end, | |
69 | DRM_MM_INSERT_LOW); | |
4f1959ee AS |
70 | } |
71 | ||
72 | static void | |
73 | remove_mappable_node(struct drm_mm_node *node) | |
74 | { | |
75 | drm_mm_remove_node(node); | |
76 | } | |
77 | ||
73aa808f CW |
78 | /* some bookkeeping */ |
79 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 80 | u64 size) |
73aa808f | 81 | { |
c20e8355 | 82 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
83 | dev_priv->mm.object_count++; |
84 | dev_priv->mm.object_memory += size; | |
c20e8355 | 85 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
86 | } |
87 | ||
88 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 89 | u64 size) |
73aa808f | 90 | { |
c20e8355 | 91 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
92 | dev_priv->mm.object_count--; |
93 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 94 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
95 | } |
96 | ||
21dd3734 | 97 | static int |
33196ded | 98 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 99 | { |
30dbf0c0 CW |
100 | int ret; |
101 | ||
4c7d62c6 CW |
102 | might_sleep(); |
103 | ||
0a6759c6 DV |
104 | /* |
105 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
106 | * userspace. If it takes that long something really bad is going on and | |
107 | * we should simply try to bail out and fail as gracefully as possible. | |
108 | */ | |
1f83fee0 | 109 | ret = wait_event_interruptible_timeout(error->reset_queue, |
8c185eca | 110 | !i915_reset_backoff(error), |
b52992c0 | 111 | I915_RESET_TIMEOUT); |
0a6759c6 DV |
112 | if (ret == 0) { |
113 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
114 | return -EIO; | |
115 | } else if (ret < 0) { | |
30dbf0c0 | 116 | return ret; |
d98c52cf CW |
117 | } else { |
118 | return 0; | |
0a6759c6 | 119 | } |
30dbf0c0 CW |
120 | } |
121 | ||
54cf91dc | 122 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 123 | { |
fac5e23e | 124 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
125 | int ret; |
126 | ||
33196ded | 127 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
128 | if (ret) |
129 | return ret; | |
130 | ||
131 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
132 | if (ret) | |
133 | return ret; | |
134 | ||
76c1dec1 CW |
135 | return 0; |
136 | } | |
30dbf0c0 | 137 | |
5a125c3c EA |
138 | int |
139 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 140 | struct drm_file *file) |
5a125c3c | 141 | { |
72e96d64 | 142 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 143 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 144 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 145 | struct i915_vma *vma; |
ff8f7975 | 146 | u64 pinned; |
5a125c3c | 147 | |
ff8f7975 | 148 | pinned = ggtt->base.reserved; |
73aa808f | 149 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 150 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 151 | if (i915_vma_is_pinned(vma)) |
ca1543be | 152 | pinned += vma->node.size; |
1c7f4bca | 153 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 154 | if (i915_vma_is_pinned(vma)) |
ca1543be | 155 | pinned += vma->node.size; |
73aa808f | 156 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 157 | |
72e96d64 | 158 | args->aper_size = ggtt->base.total; |
0206e353 | 159 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 160 | |
5a125c3c EA |
161 | return 0; |
162 | } | |
163 | ||
03ac84f1 | 164 | static struct sg_table * |
6a2c4232 | 165 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
00731155 | 166 | { |
93c76a3d | 167 | struct address_space *mapping = obj->base.filp->f_mapping; |
dbb4351b | 168 | drm_dma_handle_t *phys; |
6a2c4232 CW |
169 | struct sg_table *st; |
170 | struct scatterlist *sg; | |
dbb4351b | 171 | char *vaddr; |
6a2c4232 | 172 | int i; |
00731155 | 173 | |
6a2c4232 | 174 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
03ac84f1 | 175 | return ERR_PTR(-EINVAL); |
6a2c4232 | 176 | |
dbb4351b CW |
177 | /* Always aligning to the object size, allows a single allocation |
178 | * to handle all possible callers, and given typical object sizes, | |
179 | * the alignment of the buddy allocation will naturally match. | |
180 | */ | |
181 | phys = drm_pci_alloc(obj->base.dev, | |
182 | obj->base.size, | |
183 | roundup_pow_of_two(obj->base.size)); | |
184 | if (!phys) | |
185 | return ERR_PTR(-ENOMEM); | |
186 | ||
187 | vaddr = phys->vaddr; | |
6a2c4232 CW |
188 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
189 | struct page *page; | |
190 | char *src; | |
191 | ||
192 | page = shmem_read_mapping_page(mapping, i); | |
dbb4351b CW |
193 | if (IS_ERR(page)) { |
194 | st = ERR_CAST(page); | |
195 | goto err_phys; | |
196 | } | |
6a2c4232 CW |
197 | |
198 | src = kmap_atomic(page); | |
199 | memcpy(vaddr, src, PAGE_SIZE); | |
200 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
201 | kunmap_atomic(src); | |
202 | ||
09cbfeaf | 203 | put_page(page); |
6a2c4232 CW |
204 | vaddr += PAGE_SIZE; |
205 | } | |
206 | ||
c033666a | 207 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
208 | |
209 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
dbb4351b CW |
210 | if (!st) { |
211 | st = ERR_PTR(-ENOMEM); | |
212 | goto err_phys; | |
213 | } | |
6a2c4232 CW |
214 | |
215 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
216 | kfree(st); | |
dbb4351b CW |
217 | st = ERR_PTR(-ENOMEM); |
218 | goto err_phys; | |
6a2c4232 CW |
219 | } |
220 | ||
221 | sg = st->sgl; | |
222 | sg->offset = 0; | |
223 | sg->length = obj->base.size; | |
00731155 | 224 | |
dbb4351b | 225 | sg_dma_address(sg) = phys->busaddr; |
6a2c4232 CW |
226 | sg_dma_len(sg) = obj->base.size; |
227 | ||
dbb4351b CW |
228 | obj->phys_handle = phys; |
229 | return st; | |
230 | ||
231 | err_phys: | |
232 | drm_pci_free(obj->base.dev, phys); | |
03ac84f1 | 233 | return st; |
6a2c4232 CW |
234 | } |
235 | ||
e27ab73d CW |
236 | static void __start_cpu_write(struct drm_i915_gem_object *obj) |
237 | { | |
238 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
239 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
240 | if (cpu_write_needs_clflush(obj)) | |
241 | obj->cache_dirty = true; | |
242 | } | |
243 | ||
6a2c4232 | 244 | static void |
2b3c8317 | 245 | __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, |
e5facdf9 CW |
246 | struct sg_table *pages, |
247 | bool needs_clflush) | |
6a2c4232 | 248 | { |
a4f5ea64 | 249 | GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED); |
00731155 | 250 | |
a4f5ea64 CW |
251 | if (obj->mm.madv == I915_MADV_DONTNEED) |
252 | obj->mm.dirty = false; | |
6a2c4232 | 253 | |
e5facdf9 CW |
254 | if (needs_clflush && |
255 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 && | |
7fc92e96 | 256 | !obj->cache_coherent) |
2b3c8317 | 257 | drm_clflush_sg(pages); |
03ac84f1 | 258 | |
e27ab73d | 259 | __start_cpu_write(obj); |
03ac84f1 CW |
260 | } |
261 | ||
262 | static void | |
263 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj, | |
264 | struct sg_table *pages) | |
265 | { | |
e5facdf9 | 266 | __i915_gem_object_release_shmem(obj, pages, false); |
03ac84f1 | 267 | |
a4f5ea64 | 268 | if (obj->mm.dirty) { |
93c76a3d | 269 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 | 270 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
271 | int i; |
272 | ||
273 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
274 | struct page *page; |
275 | char *dst; | |
276 | ||
277 | page = shmem_read_mapping_page(mapping, i); | |
278 | if (IS_ERR(page)) | |
279 | continue; | |
280 | ||
281 | dst = kmap_atomic(page); | |
282 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
283 | memcpy(dst, vaddr, PAGE_SIZE); | |
284 | kunmap_atomic(dst); | |
285 | ||
286 | set_page_dirty(page); | |
a4f5ea64 | 287 | if (obj->mm.madv == I915_MADV_WILLNEED) |
00731155 | 288 | mark_page_accessed(page); |
09cbfeaf | 289 | put_page(page); |
00731155 CW |
290 | vaddr += PAGE_SIZE; |
291 | } | |
a4f5ea64 | 292 | obj->mm.dirty = false; |
00731155 CW |
293 | } |
294 | ||
03ac84f1 CW |
295 | sg_free_table(pages); |
296 | kfree(pages); | |
dbb4351b CW |
297 | |
298 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
6a2c4232 CW |
299 | } |
300 | ||
301 | static void | |
302 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
303 | { | |
a4f5ea64 | 304 | i915_gem_object_unpin_pages(obj); |
6a2c4232 CW |
305 | } |
306 | ||
307 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
308 | .get_pages = i915_gem_object_get_pages_phys, | |
309 | .put_pages = i915_gem_object_put_pages_phys, | |
310 | .release = i915_gem_object_release_phys, | |
311 | }; | |
312 | ||
581ab1fe CW |
313 | static const struct drm_i915_gem_object_ops i915_gem_object_ops; |
314 | ||
35a9611c | 315 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
aa653a68 CW |
316 | { |
317 | struct i915_vma *vma; | |
318 | LIST_HEAD(still_in_list); | |
02bef8f9 CW |
319 | int ret; |
320 | ||
321 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
aa653a68 | 322 | |
02bef8f9 CW |
323 | /* Closed vma are removed from the obj->vma_list - but they may |
324 | * still have an active binding on the object. To remove those we | |
325 | * must wait for all rendering to complete to the object (as unbinding | |
326 | * must anyway), and retire the requests. | |
aa653a68 | 327 | */ |
e95433c7 CW |
328 | ret = i915_gem_object_wait(obj, |
329 | I915_WAIT_INTERRUPTIBLE | | |
330 | I915_WAIT_LOCKED | | |
331 | I915_WAIT_ALL, | |
332 | MAX_SCHEDULE_TIMEOUT, | |
333 | NULL); | |
02bef8f9 CW |
334 | if (ret) |
335 | return ret; | |
336 | ||
337 | i915_gem_retire_requests(to_i915(obj->base.dev)); | |
338 | ||
aa653a68 CW |
339 | while ((vma = list_first_entry_or_null(&obj->vma_list, |
340 | struct i915_vma, | |
341 | obj_link))) { | |
342 | list_move_tail(&vma->obj_link, &still_in_list); | |
343 | ret = i915_vma_unbind(vma); | |
344 | if (ret) | |
345 | break; | |
346 | } | |
347 | list_splice(&still_in_list, &obj->vma_list); | |
348 | ||
349 | return ret; | |
350 | } | |
351 | ||
e95433c7 CW |
352 | static long |
353 | i915_gem_object_wait_fence(struct dma_fence *fence, | |
354 | unsigned int flags, | |
355 | long timeout, | |
356 | struct intel_rps_client *rps) | |
00e60f26 | 357 | { |
e95433c7 | 358 | struct drm_i915_gem_request *rq; |
00e60f26 | 359 | |
e95433c7 | 360 | BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1); |
00e60f26 | 361 | |
e95433c7 CW |
362 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
363 | return timeout; | |
364 | ||
365 | if (!dma_fence_is_i915(fence)) | |
366 | return dma_fence_wait_timeout(fence, | |
367 | flags & I915_WAIT_INTERRUPTIBLE, | |
368 | timeout); | |
369 | ||
370 | rq = to_request(fence); | |
371 | if (i915_gem_request_completed(rq)) | |
372 | goto out; | |
373 | ||
374 | /* This client is about to stall waiting for the GPU. In many cases | |
375 | * this is undesirable and limits the throughput of the system, as | |
376 | * many clients cannot continue processing user input/output whilst | |
377 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
378 | * to the GPU load and thus incurs additional latency for the client. | |
379 | * We can circumvent that by promoting the GPU frequency to maximum | |
380 | * before we wait. This makes the GPU throttle up much more quickly | |
381 | * (good for benchmarks and user experience, e.g. window animations), | |
382 | * but at a cost of spending more power processing the workload | |
383 | * (bad for battery). Not all clients even want their results | |
384 | * immediately and for them we should just let the GPU select its own | |
385 | * frequency to maximise efficiency. To prevent a single client from | |
386 | * forcing the clocks too high for the whole system, we only allow | |
387 | * each client to waitboost once in a busy period. | |
388 | */ | |
389 | if (rps) { | |
390 | if (INTEL_GEN(rq->i915) >= 6) | |
391 | gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies); | |
392 | else | |
393 | rps = NULL; | |
00e60f26 CW |
394 | } |
395 | ||
e95433c7 CW |
396 | timeout = i915_wait_request(rq, flags, timeout); |
397 | ||
398 | out: | |
399 | if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq)) | |
400 | i915_gem_request_retire_upto(rq); | |
401 | ||
754c9fd5 | 402 | if (rps && i915_gem_request_global_seqno(rq) == intel_engine_last_submit(rq->engine)) { |
e95433c7 CW |
403 | /* The GPU is now idle and this client has stalled. |
404 | * Since no other client has submitted a request in the | |
405 | * meantime, assume that this client is the only one | |
406 | * supplying work to the GPU but is unable to keep that | |
407 | * work supplied because it is waiting. Since the GPU is | |
408 | * then never kept fully busy, RPS autoclocking will | |
409 | * keep the clocks relatively low, causing further delays. | |
410 | * Compensate by giving the synchronous client credit for | |
411 | * a waitboost next time. | |
412 | */ | |
413 | spin_lock(&rq->i915->rps.client_lock); | |
414 | list_del_init(&rps->link); | |
415 | spin_unlock(&rq->i915->rps.client_lock); | |
416 | } | |
417 | ||
418 | return timeout; | |
419 | } | |
420 | ||
421 | static long | |
422 | i915_gem_object_wait_reservation(struct reservation_object *resv, | |
423 | unsigned int flags, | |
424 | long timeout, | |
425 | struct intel_rps_client *rps) | |
426 | { | |
e54ca977 | 427 | unsigned int seq = __read_seqcount_begin(&resv->seq); |
e95433c7 | 428 | struct dma_fence *excl; |
e54ca977 | 429 | bool prune_fences = false; |
e95433c7 CW |
430 | |
431 | if (flags & I915_WAIT_ALL) { | |
432 | struct dma_fence **shared; | |
433 | unsigned int count, i; | |
00e60f26 CW |
434 | int ret; |
435 | ||
e95433c7 CW |
436 | ret = reservation_object_get_fences_rcu(resv, |
437 | &excl, &count, &shared); | |
00e60f26 CW |
438 | if (ret) |
439 | return ret; | |
00e60f26 | 440 | |
e95433c7 CW |
441 | for (i = 0; i < count; i++) { |
442 | timeout = i915_gem_object_wait_fence(shared[i], | |
443 | flags, timeout, | |
444 | rps); | |
d892e939 | 445 | if (timeout < 0) |
e95433c7 | 446 | break; |
00e60f26 | 447 | |
e95433c7 CW |
448 | dma_fence_put(shared[i]); |
449 | } | |
450 | ||
451 | for (; i < count; i++) | |
452 | dma_fence_put(shared[i]); | |
453 | kfree(shared); | |
e54ca977 CW |
454 | |
455 | prune_fences = count && timeout >= 0; | |
e95433c7 CW |
456 | } else { |
457 | excl = reservation_object_get_excl_rcu(resv); | |
00e60f26 CW |
458 | } |
459 | ||
e54ca977 | 460 | if (excl && timeout >= 0) { |
e95433c7 | 461 | timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps); |
e54ca977 CW |
462 | prune_fences = timeout >= 0; |
463 | } | |
e95433c7 CW |
464 | |
465 | dma_fence_put(excl); | |
466 | ||
03d1cac6 CW |
467 | /* Oportunistically prune the fences iff we know they have *all* been |
468 | * signaled and that the reservation object has not been changed (i.e. | |
469 | * no new fences have been added). | |
470 | */ | |
e54ca977 | 471 | if (prune_fences && !__read_seqcount_retry(&resv->seq, seq)) { |
03d1cac6 CW |
472 | if (reservation_object_trylock(resv)) { |
473 | if (!__read_seqcount_retry(&resv->seq, seq)) | |
474 | reservation_object_add_excl_fence(resv, NULL); | |
475 | reservation_object_unlock(resv); | |
476 | } | |
e54ca977 CW |
477 | } |
478 | ||
e95433c7 | 479 | return timeout; |
00e60f26 CW |
480 | } |
481 | ||
6b5e90f5 CW |
482 | static void __fence_set_priority(struct dma_fence *fence, int prio) |
483 | { | |
484 | struct drm_i915_gem_request *rq; | |
485 | struct intel_engine_cs *engine; | |
486 | ||
487 | if (!dma_fence_is_i915(fence)) | |
488 | return; | |
489 | ||
490 | rq = to_request(fence); | |
491 | engine = rq->engine; | |
492 | if (!engine->schedule) | |
493 | return; | |
494 | ||
495 | engine->schedule(rq, prio); | |
496 | } | |
497 | ||
498 | static void fence_set_priority(struct dma_fence *fence, int prio) | |
499 | { | |
500 | /* Recurse once into a fence-array */ | |
501 | if (dma_fence_is_array(fence)) { | |
502 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
503 | int i; | |
504 | ||
505 | for (i = 0; i < array->num_fences; i++) | |
506 | __fence_set_priority(array->fences[i], prio); | |
507 | } else { | |
508 | __fence_set_priority(fence, prio); | |
509 | } | |
510 | } | |
511 | ||
512 | int | |
513 | i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, | |
514 | unsigned int flags, | |
515 | int prio) | |
516 | { | |
517 | struct dma_fence *excl; | |
518 | ||
519 | if (flags & I915_WAIT_ALL) { | |
520 | struct dma_fence **shared; | |
521 | unsigned int count, i; | |
522 | int ret; | |
523 | ||
524 | ret = reservation_object_get_fences_rcu(obj->resv, | |
525 | &excl, &count, &shared); | |
526 | if (ret) | |
527 | return ret; | |
528 | ||
529 | for (i = 0; i < count; i++) { | |
530 | fence_set_priority(shared[i], prio); | |
531 | dma_fence_put(shared[i]); | |
532 | } | |
533 | ||
534 | kfree(shared); | |
535 | } else { | |
536 | excl = reservation_object_get_excl_rcu(obj->resv); | |
537 | } | |
538 | ||
539 | if (excl) { | |
540 | fence_set_priority(excl, prio); | |
541 | dma_fence_put(excl); | |
542 | } | |
543 | return 0; | |
544 | } | |
545 | ||
e95433c7 CW |
546 | /** |
547 | * Waits for rendering to the object to be completed | |
548 | * @obj: i915 gem object | |
549 | * @flags: how to wait (under a lock, for all rendering or just for writes etc) | |
550 | * @timeout: how long to wait | |
551 | * @rps: client (user process) to charge for any waitboosting | |
00e60f26 | 552 | */ |
e95433c7 CW |
553 | int |
554 | i915_gem_object_wait(struct drm_i915_gem_object *obj, | |
555 | unsigned int flags, | |
556 | long timeout, | |
557 | struct intel_rps_client *rps) | |
00e60f26 | 558 | { |
e95433c7 CW |
559 | might_sleep(); |
560 | #if IS_ENABLED(CONFIG_LOCKDEP) | |
561 | GEM_BUG_ON(debug_locks && | |
562 | !!lockdep_is_held(&obj->base.dev->struct_mutex) != | |
563 | !!(flags & I915_WAIT_LOCKED)); | |
564 | #endif | |
565 | GEM_BUG_ON(timeout < 0); | |
00e60f26 | 566 | |
d07f0e59 CW |
567 | timeout = i915_gem_object_wait_reservation(obj->resv, |
568 | flags, timeout, | |
569 | rps); | |
e95433c7 | 570 | return timeout < 0 ? timeout : 0; |
00e60f26 CW |
571 | } |
572 | ||
573 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
574 | { | |
575 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
576 | ||
577 | return &fpriv->rps; | |
578 | } | |
579 | ||
00731155 CW |
580 | int |
581 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
582 | int align) | |
583 | { | |
6a2c4232 | 584 | int ret; |
00731155 | 585 | |
dbb4351b CW |
586 | if (align > obj->base.size) |
587 | return -EINVAL; | |
00731155 | 588 | |
dbb4351b | 589 | if (obj->ops == &i915_gem_phys_ops) |
00731155 | 590 | return 0; |
00731155 | 591 | |
a4f5ea64 | 592 | if (obj->mm.madv != I915_MADV_WILLNEED) |
00731155 CW |
593 | return -EFAULT; |
594 | ||
595 | if (obj->base.filp == NULL) | |
596 | return -EINVAL; | |
597 | ||
4717ca9e CW |
598 | ret = i915_gem_object_unbind(obj); |
599 | if (ret) | |
600 | return ret; | |
601 | ||
548625ee | 602 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
03ac84f1 CW |
603 | if (obj->mm.pages) |
604 | return -EBUSY; | |
6a2c4232 | 605 | |
581ab1fe | 606 | GEM_BUG_ON(obj->ops != &i915_gem_object_ops); |
6a2c4232 CW |
607 | obj->ops = &i915_gem_phys_ops; |
608 | ||
581ab1fe CW |
609 | ret = i915_gem_object_pin_pages(obj); |
610 | if (ret) | |
611 | goto err_xfer; | |
612 | ||
613 | return 0; | |
614 | ||
615 | err_xfer: | |
616 | obj->ops = &i915_gem_object_ops; | |
617 | return ret; | |
00731155 CW |
618 | } |
619 | ||
620 | static int | |
621 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
622 | struct drm_i915_gem_pwrite *args, | |
03ac84f1 | 623 | struct drm_file *file) |
00731155 | 624 | { |
00731155 | 625 | void *vaddr = obj->phys_handle->vaddr + args->offset; |
3ed605bc | 626 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
6a2c4232 CW |
627 | |
628 | /* We manually control the domain here and pretend that it | |
629 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
630 | */ | |
77a0d1ca | 631 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
10466d2a CW |
632 | if (copy_from_user(vaddr, user_data, args->size)) |
633 | return -EFAULT; | |
00731155 | 634 | |
6a2c4232 | 635 | drm_clflush_virt_range(vaddr, args->size); |
10466d2a | 636 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
063e4e6b | 637 | |
d59b21ec | 638 | intel_fb_obj_flush(obj, ORIGIN_CPU); |
10466d2a | 639 | return 0; |
00731155 CW |
640 | } |
641 | ||
187685cb | 642 | void *i915_gem_object_alloc(struct drm_i915_private *dev_priv) |
42dcedd4 | 643 | { |
efab6d8d | 644 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
645 | } |
646 | ||
647 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
648 | { | |
fac5e23e | 649 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 650 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
651 | } |
652 | ||
ff72145b DA |
653 | static int |
654 | i915_gem_create(struct drm_file *file, | |
12d79d78 | 655 | struct drm_i915_private *dev_priv, |
ff72145b DA |
656 | uint64_t size, |
657 | uint32_t *handle_p) | |
673a394b | 658 | { |
05394f39 | 659 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
660 | int ret; |
661 | u32 handle; | |
673a394b | 662 | |
ff72145b | 663 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
664 | if (size == 0) |
665 | return -EINVAL; | |
673a394b EA |
666 | |
667 | /* Allocate the new object */ | |
12d79d78 | 668 | obj = i915_gem_object_create(dev_priv, size); |
fe3db79b CW |
669 | if (IS_ERR(obj)) |
670 | return PTR_ERR(obj); | |
673a394b | 671 | |
05394f39 | 672 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 673 | /* drop reference from allocate - handle holds it now */ |
f0cd5182 | 674 | i915_gem_object_put(obj); |
d861e338 DV |
675 | if (ret) |
676 | return ret; | |
202f2fef | 677 | |
ff72145b | 678 | *handle_p = handle; |
673a394b EA |
679 | return 0; |
680 | } | |
681 | ||
ff72145b DA |
682 | int |
683 | i915_gem_dumb_create(struct drm_file *file, | |
684 | struct drm_device *dev, | |
685 | struct drm_mode_create_dumb *args) | |
686 | { | |
687 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 688 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b | 689 | args->size = args->pitch * args->height; |
12d79d78 | 690 | return i915_gem_create(file, to_i915(dev), |
da6b51d0 | 691 | args->size, &args->handle); |
ff72145b DA |
692 | } |
693 | ||
e27ab73d CW |
694 | static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
695 | { | |
696 | return !(obj->cache_level == I915_CACHE_NONE || | |
697 | obj->cache_level == I915_CACHE_WT); | |
698 | } | |
699 | ||
ff72145b DA |
700 | /** |
701 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
702 | * @dev: drm device pointer |
703 | * @data: ioctl data blob | |
704 | * @file: drm file pointer | |
ff72145b DA |
705 | */ |
706 | int | |
707 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
708 | struct drm_file *file) | |
709 | { | |
12d79d78 | 710 | struct drm_i915_private *dev_priv = to_i915(dev); |
ff72145b | 711 | struct drm_i915_gem_create *args = data; |
63ed2cb2 | 712 | |
12d79d78 | 713 | i915_gem_flush_free_objects(dev_priv); |
fbbd37b3 | 714 | |
12d79d78 | 715 | return i915_gem_create(file, dev_priv, |
da6b51d0 | 716 | args->size, &args->handle); |
ff72145b DA |
717 | } |
718 | ||
ef74921b CW |
719 | static inline enum fb_op_origin |
720 | fb_write_origin(struct drm_i915_gem_object *obj, unsigned int domain) | |
721 | { | |
722 | return (domain == I915_GEM_DOMAIN_GTT ? | |
723 | obj->frontbuffer_ggtt_origin : ORIGIN_CPU); | |
724 | } | |
725 | ||
726 | static void | |
727 | flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) | |
728 | { | |
729 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); | |
730 | ||
731 | if (!(obj->base.write_domain & flush_domains)) | |
732 | return; | |
733 | ||
734 | /* No actual flushing is required for the GTT write domain. Writes | |
735 | * to it "immediately" go to main memory as far as we know, so there's | |
736 | * no chipset flush. It also doesn't land in render cache. | |
737 | * | |
738 | * However, we do have to enforce the order so that all writes through | |
739 | * the GTT land before any writes to the device, such as updates to | |
740 | * the GATT itself. | |
741 | * | |
742 | * We also have to wait a bit for the writes to land from the GTT. | |
743 | * An uncached read (i.e. mmio) seems to be ideal for the round-trip | |
744 | * timing. This issue has only been observed when switching quickly | |
745 | * between GTT writes and CPU reads from inside the kernel on recent hw, | |
746 | * and it appears to only affect discrete GTT blocks (i.e. on LLC | |
747 | * system agents we cannot reproduce this behaviour). | |
748 | */ | |
749 | wmb(); | |
750 | ||
751 | switch (obj->base.write_domain) { | |
752 | case I915_GEM_DOMAIN_GTT: | |
753 | if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) { | |
754 | if (intel_runtime_pm_get_if_in_use(dev_priv)) { | |
755 | spin_lock_irq(&dev_priv->uncore.lock); | |
756 | POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base)); | |
757 | spin_unlock_irq(&dev_priv->uncore.lock); | |
758 | intel_runtime_pm_put(dev_priv); | |
759 | } | |
760 | } | |
761 | ||
762 | intel_fb_obj_flush(obj, | |
763 | fb_write_origin(obj, I915_GEM_DOMAIN_GTT)); | |
764 | break; | |
765 | ||
766 | case I915_GEM_DOMAIN_CPU: | |
767 | i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC); | |
768 | break; | |
e27ab73d CW |
769 | |
770 | case I915_GEM_DOMAIN_RENDER: | |
771 | if (gpu_write_needs_clflush(obj)) | |
772 | obj->cache_dirty = true; | |
773 | break; | |
ef74921b CW |
774 | } |
775 | ||
776 | obj->base.write_domain = 0; | |
777 | } | |
778 | ||
8461d226 DV |
779 | static inline int |
780 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
781 | const char *gpu_vaddr, int gpu_offset, | |
782 | int length) | |
783 | { | |
784 | int ret, cpu_offset = 0; | |
785 | ||
786 | while (length > 0) { | |
787 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
788 | int this_length = min(cacheline_end - gpu_offset, length); | |
789 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
790 | ||
791 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
792 | gpu_vaddr + swizzled_gpu_offset, | |
793 | this_length); | |
794 | if (ret) | |
795 | return ret + length; | |
796 | ||
797 | cpu_offset += this_length; | |
798 | gpu_offset += this_length; | |
799 | length -= this_length; | |
800 | } | |
801 | ||
802 | return 0; | |
803 | } | |
804 | ||
8c59967c | 805 | static inline int |
4f0c7cfb BW |
806 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
807 | const char __user *cpu_vaddr, | |
8c59967c DV |
808 | int length) |
809 | { | |
810 | int ret, cpu_offset = 0; | |
811 | ||
812 | while (length > 0) { | |
813 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
814 | int this_length = min(cacheline_end - gpu_offset, length); | |
815 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
816 | ||
817 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
818 | cpu_vaddr + cpu_offset, | |
819 | this_length); | |
820 | if (ret) | |
821 | return ret + length; | |
822 | ||
823 | cpu_offset += this_length; | |
824 | gpu_offset += this_length; | |
825 | length -= this_length; | |
826 | } | |
827 | ||
828 | return 0; | |
829 | } | |
830 | ||
4c914c0c BV |
831 | /* |
832 | * Pins the specified object's pages and synchronizes the object with | |
833 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
834 | * flush the object from the CPU cache. | |
835 | */ | |
836 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
43394c7d | 837 | unsigned int *needs_clflush) |
4c914c0c BV |
838 | { |
839 | int ret; | |
840 | ||
e95433c7 | 841 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c914c0c | 842 | |
e95433c7 | 843 | *needs_clflush = 0; |
43394c7d CW |
844 | if (!i915_gem_object_has_struct_page(obj)) |
845 | return -ENODEV; | |
4c914c0c | 846 | |
e95433c7 CW |
847 | ret = i915_gem_object_wait(obj, |
848 | I915_WAIT_INTERRUPTIBLE | | |
849 | I915_WAIT_LOCKED, | |
850 | MAX_SCHEDULE_TIMEOUT, | |
851 | NULL); | |
c13d87ea CW |
852 | if (ret) |
853 | return ret; | |
854 | ||
a4f5ea64 | 855 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
856 | if (ret) |
857 | return ret; | |
858 | ||
7fc92e96 | 859 | if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
7f5f95d8 CW |
860 | ret = i915_gem_object_set_to_cpu_domain(obj, false); |
861 | if (ret) | |
862 | goto err_unpin; | |
863 | else | |
864 | goto out; | |
865 | } | |
866 | ||
ef74921b | 867 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); |
a314d5cb | 868 | |
43394c7d CW |
869 | /* If we're not in the cpu read domain, set ourself into the gtt |
870 | * read domain and manually flush cachelines (if required). This | |
871 | * optimizes for the case when the gpu will dirty the data | |
872 | * anyway again before the next pread happens. | |
873 | */ | |
e27ab73d CW |
874 | if (!obj->cache_dirty && |
875 | !(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
7f5f95d8 | 876 | *needs_clflush = CLFLUSH_BEFORE; |
4c914c0c | 877 | |
7f5f95d8 | 878 | out: |
9764951e | 879 | /* return with the pages pinned */ |
43394c7d | 880 | return 0; |
9764951e CW |
881 | |
882 | err_unpin: | |
883 | i915_gem_object_unpin_pages(obj); | |
884 | return ret; | |
43394c7d CW |
885 | } |
886 | ||
887 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
888 | unsigned int *needs_clflush) | |
889 | { | |
890 | int ret; | |
891 | ||
e95433c7 CW |
892 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
893 | ||
43394c7d CW |
894 | *needs_clflush = 0; |
895 | if (!i915_gem_object_has_struct_page(obj)) | |
896 | return -ENODEV; | |
897 | ||
e95433c7 CW |
898 | ret = i915_gem_object_wait(obj, |
899 | I915_WAIT_INTERRUPTIBLE | | |
900 | I915_WAIT_LOCKED | | |
901 | I915_WAIT_ALL, | |
902 | MAX_SCHEDULE_TIMEOUT, | |
903 | NULL); | |
43394c7d CW |
904 | if (ret) |
905 | return ret; | |
906 | ||
a4f5ea64 | 907 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
908 | if (ret) |
909 | return ret; | |
910 | ||
7fc92e96 | 911 | if (obj->cache_coherent || !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
7f5f95d8 CW |
912 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
913 | if (ret) | |
914 | goto err_unpin; | |
915 | else | |
916 | goto out; | |
917 | } | |
918 | ||
ef74921b | 919 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); |
a314d5cb | 920 | |
43394c7d CW |
921 | /* If we're not in the cpu write domain, set ourself into the |
922 | * gtt write domain and manually flush cachelines (as required). | |
923 | * This optimizes for the case when the gpu will use the data | |
924 | * right away and we therefore have to clflush anyway. | |
925 | */ | |
e27ab73d | 926 | if (!obj->cache_dirty) { |
7f5f95d8 | 927 | *needs_clflush |= CLFLUSH_AFTER; |
43394c7d | 928 | |
e27ab73d CW |
929 | /* |
930 | * Same trick applies to invalidate partially written | |
931 | * cachelines read before writing. | |
932 | */ | |
933 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
934 | *needs_clflush |= CLFLUSH_BEFORE; | |
935 | } | |
43394c7d | 936 | |
7f5f95d8 | 937 | out: |
43394c7d | 938 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
a4f5ea64 | 939 | obj->mm.dirty = true; |
9764951e | 940 | /* return with the pages pinned */ |
43394c7d | 941 | return 0; |
9764951e CW |
942 | |
943 | err_unpin: | |
944 | i915_gem_object_unpin_pages(obj); | |
945 | return ret; | |
4c914c0c BV |
946 | } |
947 | ||
23c18c71 DV |
948 | static void |
949 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
950 | bool swizzled) | |
951 | { | |
e7e58eb5 | 952 | if (unlikely(swizzled)) { |
23c18c71 DV |
953 | unsigned long start = (unsigned long) addr; |
954 | unsigned long end = (unsigned long) addr + length; | |
955 | ||
956 | /* For swizzling simply ensure that we always flush both | |
957 | * channels. Lame, but simple and it works. Swizzled | |
958 | * pwrite/pread is far from a hotpath - current userspace | |
959 | * doesn't use it at all. */ | |
960 | start = round_down(start, 128); | |
961 | end = round_up(end, 128); | |
962 | ||
963 | drm_clflush_virt_range((void *)start, end - start); | |
964 | } else { | |
965 | drm_clflush_virt_range(addr, length); | |
966 | } | |
967 | ||
968 | } | |
969 | ||
d174bd64 DV |
970 | /* Only difference to the fast-path function is that this can handle bit17 |
971 | * and uses non-atomic copy and kmap functions. */ | |
972 | static int | |
bb6dc8d9 | 973 | shmem_pread_slow(struct page *page, int offset, int length, |
d174bd64 DV |
974 | char __user *user_data, |
975 | bool page_do_bit17_swizzling, bool needs_clflush) | |
976 | { | |
977 | char *vaddr; | |
978 | int ret; | |
979 | ||
980 | vaddr = kmap(page); | |
981 | if (needs_clflush) | |
bb6dc8d9 | 982 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 983 | page_do_bit17_swizzling); |
d174bd64 DV |
984 | |
985 | if (page_do_bit17_swizzling) | |
bb6dc8d9 | 986 | ret = __copy_to_user_swizzled(user_data, vaddr, offset, length); |
d174bd64 | 987 | else |
bb6dc8d9 | 988 | ret = __copy_to_user(user_data, vaddr + offset, length); |
d174bd64 DV |
989 | kunmap(page); |
990 | ||
f60d7f0c | 991 | return ret ? - EFAULT : 0; |
d174bd64 DV |
992 | } |
993 | ||
bb6dc8d9 CW |
994 | static int |
995 | shmem_pread(struct page *page, int offset, int length, char __user *user_data, | |
996 | bool page_do_bit17_swizzling, bool needs_clflush) | |
997 | { | |
998 | int ret; | |
999 | ||
1000 | ret = -ENODEV; | |
1001 | if (!page_do_bit17_swizzling) { | |
1002 | char *vaddr = kmap_atomic(page); | |
1003 | ||
1004 | if (needs_clflush) | |
1005 | drm_clflush_virt_range(vaddr + offset, length); | |
1006 | ret = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
1007 | kunmap_atomic(vaddr); | |
1008 | } | |
1009 | if (ret == 0) | |
1010 | return 0; | |
1011 | ||
1012 | return shmem_pread_slow(page, offset, length, user_data, | |
1013 | page_do_bit17_swizzling, needs_clflush); | |
1014 | } | |
1015 | ||
1016 | static int | |
1017 | i915_gem_shmem_pread(struct drm_i915_gem_object *obj, | |
1018 | struct drm_i915_gem_pread *args) | |
1019 | { | |
1020 | char __user *user_data; | |
1021 | u64 remain; | |
1022 | unsigned int obj_do_bit17_swizzling; | |
1023 | unsigned int needs_clflush; | |
1024 | unsigned int idx, offset; | |
1025 | int ret; | |
1026 | ||
1027 | obj_do_bit17_swizzling = 0; | |
1028 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
1029 | obj_do_bit17_swizzling = BIT(17); | |
1030 | ||
1031 | ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex); | |
1032 | if (ret) | |
1033 | return ret; | |
1034 | ||
1035 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); | |
1036 | mutex_unlock(&obj->base.dev->struct_mutex); | |
1037 | if (ret) | |
1038 | return ret; | |
1039 | ||
1040 | remain = args->size; | |
1041 | user_data = u64_to_user_ptr(args->data_ptr); | |
1042 | offset = offset_in_page(args->offset); | |
1043 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
1044 | struct page *page = i915_gem_object_get_page(obj, idx); | |
1045 | int length; | |
1046 | ||
1047 | length = remain; | |
1048 | if (offset + length > PAGE_SIZE) | |
1049 | length = PAGE_SIZE - offset; | |
1050 | ||
1051 | ret = shmem_pread(page, offset, length, user_data, | |
1052 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1053 | needs_clflush); | |
1054 | if (ret) | |
1055 | break; | |
1056 | ||
1057 | remain -= length; | |
1058 | user_data += length; | |
1059 | offset = 0; | |
1060 | } | |
1061 | ||
1062 | i915_gem_obj_finish_shmem_access(obj); | |
1063 | return ret; | |
1064 | } | |
1065 | ||
1066 | static inline bool | |
1067 | gtt_user_read(struct io_mapping *mapping, | |
1068 | loff_t base, int offset, | |
1069 | char __user *user_data, int length) | |
b50a5371 | 1070 | { |
b50a5371 | 1071 | void *vaddr; |
bb6dc8d9 | 1072 | unsigned long unwritten; |
b50a5371 | 1073 | |
b50a5371 | 1074 | /* We can use the cpu mem copy function because this is X86. */ |
bb6dc8d9 CW |
1075 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
1076 | unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
1077 | io_mapping_unmap_atomic(vaddr); | |
1078 | if (unwritten) { | |
1079 | vaddr = (void __force *) | |
1080 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
1081 | unwritten = copy_to_user(user_data, vaddr + offset, length); | |
1082 | io_mapping_unmap(vaddr); | |
1083 | } | |
b50a5371 AS |
1084 | return unwritten; |
1085 | } | |
1086 | ||
1087 | static int | |
bb6dc8d9 CW |
1088 | i915_gem_gtt_pread(struct drm_i915_gem_object *obj, |
1089 | const struct drm_i915_gem_pread *args) | |
b50a5371 | 1090 | { |
bb6dc8d9 CW |
1091 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
1092 | struct i915_ggtt *ggtt = &i915->ggtt; | |
b50a5371 | 1093 | struct drm_mm_node node; |
bb6dc8d9 CW |
1094 | struct i915_vma *vma; |
1095 | void __user *user_data; | |
1096 | u64 remain, offset; | |
b50a5371 AS |
1097 | int ret; |
1098 | ||
bb6dc8d9 CW |
1099 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1100 | if (ret) | |
1101 | return ret; | |
1102 | ||
1103 | intel_runtime_pm_get(i915); | |
1104 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, | |
1105 | PIN_MAPPABLE | PIN_NONBLOCK); | |
18034584 CW |
1106 | if (!IS_ERR(vma)) { |
1107 | node.start = i915_ggtt_offset(vma); | |
1108 | node.allocated = false; | |
49ef5294 | 1109 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1110 | if (ret) { |
1111 | i915_vma_unpin(vma); | |
1112 | vma = ERR_PTR(ret); | |
1113 | } | |
1114 | } | |
058d88c4 | 1115 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1116 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
b50a5371 | 1117 | if (ret) |
bb6dc8d9 CW |
1118 | goto out_unlock; |
1119 | GEM_BUG_ON(!node.allocated); | |
b50a5371 AS |
1120 | } |
1121 | ||
1122 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1123 | if (ret) | |
1124 | goto out_unpin; | |
1125 | ||
bb6dc8d9 | 1126 | mutex_unlock(&i915->drm.struct_mutex); |
b50a5371 | 1127 | |
bb6dc8d9 CW |
1128 | user_data = u64_to_user_ptr(args->data_ptr); |
1129 | remain = args->size; | |
1130 | offset = args->offset; | |
b50a5371 AS |
1131 | |
1132 | while (remain > 0) { | |
1133 | /* Operation in this page | |
1134 | * | |
1135 | * page_base = page offset within aperture | |
1136 | * page_offset = offset within page | |
1137 | * page_length = bytes to copy for this page | |
1138 | */ | |
1139 | u32 page_base = node.start; | |
1140 | unsigned page_offset = offset_in_page(offset); | |
1141 | unsigned page_length = PAGE_SIZE - page_offset; | |
1142 | page_length = remain < page_length ? remain : page_length; | |
1143 | if (node.allocated) { | |
1144 | wmb(); | |
1145 | ggtt->base.insert_page(&ggtt->base, | |
1146 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
bb6dc8d9 | 1147 | node.start, I915_CACHE_NONE, 0); |
b50a5371 AS |
1148 | wmb(); |
1149 | } else { | |
1150 | page_base += offset & PAGE_MASK; | |
1151 | } | |
bb6dc8d9 CW |
1152 | |
1153 | if (gtt_user_read(&ggtt->mappable, page_base, page_offset, | |
1154 | user_data, page_length)) { | |
b50a5371 AS |
1155 | ret = -EFAULT; |
1156 | break; | |
1157 | } | |
1158 | ||
1159 | remain -= page_length; | |
1160 | user_data += page_length; | |
1161 | offset += page_length; | |
1162 | } | |
1163 | ||
bb6dc8d9 | 1164 | mutex_lock(&i915->drm.struct_mutex); |
b50a5371 AS |
1165 | out_unpin: |
1166 | if (node.allocated) { | |
1167 | wmb(); | |
1168 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1169 | node.start, node.size); |
b50a5371 AS |
1170 | remove_mappable_node(&node); |
1171 | } else { | |
058d88c4 | 1172 | i915_vma_unpin(vma); |
b50a5371 | 1173 | } |
bb6dc8d9 CW |
1174 | out_unlock: |
1175 | intel_runtime_pm_put(i915); | |
1176 | mutex_unlock(&i915->drm.struct_mutex); | |
f60d7f0c | 1177 | |
eb01459f EA |
1178 | return ret; |
1179 | } | |
1180 | ||
673a394b EA |
1181 | /** |
1182 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
1183 | * @dev: drm device pointer |
1184 | * @data: ioctl data blob | |
1185 | * @file: drm file pointer | |
673a394b EA |
1186 | * |
1187 | * On error, the contents of *data are undefined. | |
1188 | */ | |
1189 | int | |
1190 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1191 | struct drm_file *file) |
673a394b EA |
1192 | { |
1193 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 1194 | struct drm_i915_gem_object *obj; |
bb6dc8d9 | 1195 | int ret; |
673a394b | 1196 | |
51311d0a CW |
1197 | if (args->size == 0) |
1198 | return 0; | |
1199 | ||
1200 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 1201 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1202 | args->size)) |
1203 | return -EFAULT; | |
1204 | ||
03ac0642 | 1205 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1206 | if (!obj) |
1207 | return -ENOENT; | |
673a394b | 1208 | |
7dcd2499 | 1209 | /* Bounds check source. */ |
966d5bf5 | 1210 | if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { |
ce9d419d | 1211 | ret = -EINVAL; |
bb6dc8d9 | 1212 | goto out; |
ce9d419d CW |
1213 | } |
1214 | ||
db53a302 CW |
1215 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
1216 | ||
e95433c7 CW |
1217 | ret = i915_gem_object_wait(obj, |
1218 | I915_WAIT_INTERRUPTIBLE, | |
1219 | MAX_SCHEDULE_TIMEOUT, | |
1220 | to_rps_client(file)); | |
258a5ede | 1221 | if (ret) |
bb6dc8d9 | 1222 | goto out; |
258a5ede | 1223 | |
bb6dc8d9 | 1224 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1225 | if (ret) |
bb6dc8d9 | 1226 | goto out; |
673a394b | 1227 | |
bb6dc8d9 | 1228 | ret = i915_gem_shmem_pread(obj, args); |
9c870d03 | 1229 | if (ret == -EFAULT || ret == -ENODEV) |
bb6dc8d9 | 1230 | ret = i915_gem_gtt_pread(obj, args); |
b50a5371 | 1231 | |
bb6dc8d9 CW |
1232 | i915_gem_object_unpin_pages(obj); |
1233 | out: | |
f0cd5182 | 1234 | i915_gem_object_put(obj); |
eb01459f | 1235 | return ret; |
673a394b EA |
1236 | } |
1237 | ||
0839ccb8 KP |
1238 | /* This is the fast write path which cannot handle |
1239 | * page faults in the source data | |
9b7530cc | 1240 | */ |
0839ccb8 | 1241 | |
fe115628 CW |
1242 | static inline bool |
1243 | ggtt_write(struct io_mapping *mapping, | |
1244 | loff_t base, int offset, | |
1245 | char __user *user_data, int length) | |
9b7530cc | 1246 | { |
4f0c7cfb | 1247 | void *vaddr; |
0839ccb8 | 1248 | unsigned long unwritten; |
9b7530cc | 1249 | |
4f0c7cfb | 1250 | /* We can use the cpu mem copy function because this is X86. */ |
fe115628 CW |
1251 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
1252 | unwritten = __copy_from_user_inatomic_nocache(vaddr + offset, | |
0839ccb8 | 1253 | user_data, length); |
fe115628 CW |
1254 | io_mapping_unmap_atomic(vaddr); |
1255 | if (unwritten) { | |
1256 | vaddr = (void __force *) | |
1257 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
1258 | unwritten = copy_from_user(vaddr + offset, user_data, length); | |
1259 | io_mapping_unmap(vaddr); | |
1260 | } | |
bb6dc8d9 | 1261 | |
bb6dc8d9 CW |
1262 | return unwritten; |
1263 | } | |
1264 | ||
3de09aa3 EA |
1265 | /** |
1266 | * This is the fast pwrite path, where we copy the data directly from the | |
1267 | * user into the GTT, uncached. | |
fe115628 | 1268 | * @obj: i915 GEM object |
14bb2c11 | 1269 | * @args: pwrite arguments structure |
3de09aa3 | 1270 | */ |
673a394b | 1271 | static int |
fe115628 CW |
1272 | i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, |
1273 | const struct drm_i915_gem_pwrite *args) | |
673a394b | 1274 | { |
fe115628 | 1275 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
4f1959ee AS |
1276 | struct i915_ggtt *ggtt = &i915->ggtt; |
1277 | struct drm_mm_node node; | |
fe115628 CW |
1278 | struct i915_vma *vma; |
1279 | u64 remain, offset; | |
1280 | void __user *user_data; | |
4f1959ee | 1281 | int ret; |
b50a5371 | 1282 | |
fe115628 CW |
1283 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1284 | if (ret) | |
1285 | return ret; | |
935aaa69 | 1286 | |
9c870d03 | 1287 | intel_runtime_pm_get(i915); |
058d88c4 | 1288 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
de895082 | 1289 | PIN_MAPPABLE | PIN_NONBLOCK); |
18034584 CW |
1290 | if (!IS_ERR(vma)) { |
1291 | node.start = i915_ggtt_offset(vma); | |
1292 | node.allocated = false; | |
49ef5294 | 1293 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1294 | if (ret) { |
1295 | i915_vma_unpin(vma); | |
1296 | vma = ERR_PTR(ret); | |
1297 | } | |
1298 | } | |
058d88c4 | 1299 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1300 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
4f1959ee | 1301 | if (ret) |
fe115628 CW |
1302 | goto out_unlock; |
1303 | GEM_BUG_ON(!node.allocated); | |
4f1959ee | 1304 | } |
935aaa69 DV |
1305 | |
1306 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1307 | if (ret) | |
1308 | goto out_unpin; | |
1309 | ||
fe115628 CW |
1310 | mutex_unlock(&i915->drm.struct_mutex); |
1311 | ||
b19482d7 | 1312 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1313 | |
4f1959ee AS |
1314 | user_data = u64_to_user_ptr(args->data_ptr); |
1315 | offset = args->offset; | |
1316 | remain = args->size; | |
1317 | while (remain) { | |
673a394b EA |
1318 | /* Operation in this page |
1319 | * | |
0839ccb8 KP |
1320 | * page_base = page offset within aperture |
1321 | * page_offset = offset within page | |
1322 | * page_length = bytes to copy for this page | |
673a394b | 1323 | */ |
4f1959ee | 1324 | u32 page_base = node.start; |
bb6dc8d9 CW |
1325 | unsigned int page_offset = offset_in_page(offset); |
1326 | unsigned int page_length = PAGE_SIZE - page_offset; | |
4f1959ee AS |
1327 | page_length = remain < page_length ? remain : page_length; |
1328 | if (node.allocated) { | |
1329 | wmb(); /* flush the write before we modify the GGTT */ | |
1330 | ggtt->base.insert_page(&ggtt->base, | |
1331 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1332 | node.start, I915_CACHE_NONE, 0); | |
1333 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1334 | } else { | |
1335 | page_base += offset & PAGE_MASK; | |
1336 | } | |
0839ccb8 | 1337 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1338 | * source page isn't available. Return the error and we'll |
1339 | * retry in the slow path. | |
b50a5371 AS |
1340 | * If the object is non-shmem backed, we retry again with the |
1341 | * path that handles page fault. | |
0839ccb8 | 1342 | */ |
fe115628 CW |
1343 | if (ggtt_write(&ggtt->mappable, page_base, page_offset, |
1344 | user_data, page_length)) { | |
1345 | ret = -EFAULT; | |
1346 | break; | |
935aaa69 | 1347 | } |
673a394b | 1348 | |
0839ccb8 KP |
1349 | remain -= page_length; |
1350 | user_data += page_length; | |
1351 | offset += page_length; | |
673a394b | 1352 | } |
d59b21ec | 1353 | intel_fb_obj_flush(obj, ORIGIN_CPU); |
fe115628 CW |
1354 | |
1355 | mutex_lock(&i915->drm.struct_mutex); | |
935aaa69 | 1356 | out_unpin: |
4f1959ee AS |
1357 | if (node.allocated) { |
1358 | wmb(); | |
1359 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1360 | node.start, node.size); |
4f1959ee AS |
1361 | remove_mappable_node(&node); |
1362 | } else { | |
058d88c4 | 1363 | i915_vma_unpin(vma); |
4f1959ee | 1364 | } |
fe115628 | 1365 | out_unlock: |
9c870d03 | 1366 | intel_runtime_pm_put(i915); |
fe115628 | 1367 | mutex_unlock(&i915->drm.struct_mutex); |
3de09aa3 | 1368 | return ret; |
673a394b EA |
1369 | } |
1370 | ||
3043c60c | 1371 | static int |
fe115628 | 1372 | shmem_pwrite_slow(struct page *page, int offset, int length, |
d174bd64 DV |
1373 | char __user *user_data, |
1374 | bool page_do_bit17_swizzling, | |
1375 | bool needs_clflush_before, | |
1376 | bool needs_clflush_after) | |
673a394b | 1377 | { |
d174bd64 DV |
1378 | char *vaddr; |
1379 | int ret; | |
e5281ccd | 1380 | |
d174bd64 | 1381 | vaddr = kmap(page); |
e7e58eb5 | 1382 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
fe115628 | 1383 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1384 | page_do_bit17_swizzling); |
d174bd64 | 1385 | if (page_do_bit17_swizzling) |
fe115628 CW |
1386 | ret = __copy_from_user_swizzled(vaddr, offset, user_data, |
1387 | length); | |
d174bd64 | 1388 | else |
fe115628 | 1389 | ret = __copy_from_user(vaddr + offset, user_data, length); |
d174bd64 | 1390 | if (needs_clflush_after) |
fe115628 | 1391 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1392 | page_do_bit17_swizzling); |
d174bd64 | 1393 | kunmap(page); |
40123c1f | 1394 | |
755d2218 | 1395 | return ret ? -EFAULT : 0; |
40123c1f EA |
1396 | } |
1397 | ||
fe115628 CW |
1398 | /* Per-page copy function for the shmem pwrite fastpath. |
1399 | * Flushes invalid cachelines before writing to the target if | |
1400 | * needs_clflush_before is set and flushes out any written cachelines after | |
1401 | * writing if needs_clflush is set. | |
1402 | */ | |
40123c1f | 1403 | static int |
fe115628 CW |
1404 | shmem_pwrite(struct page *page, int offset, int len, char __user *user_data, |
1405 | bool page_do_bit17_swizzling, | |
1406 | bool needs_clflush_before, | |
1407 | bool needs_clflush_after) | |
40123c1f | 1408 | { |
fe115628 CW |
1409 | int ret; |
1410 | ||
1411 | ret = -ENODEV; | |
1412 | if (!page_do_bit17_swizzling) { | |
1413 | char *vaddr = kmap_atomic(page); | |
1414 | ||
1415 | if (needs_clflush_before) | |
1416 | drm_clflush_virt_range(vaddr + offset, len); | |
1417 | ret = __copy_from_user_inatomic(vaddr + offset, user_data, len); | |
1418 | if (needs_clflush_after) | |
1419 | drm_clflush_virt_range(vaddr + offset, len); | |
1420 | ||
1421 | kunmap_atomic(vaddr); | |
1422 | } | |
1423 | if (ret == 0) | |
1424 | return ret; | |
1425 | ||
1426 | return shmem_pwrite_slow(page, offset, len, user_data, | |
1427 | page_do_bit17_swizzling, | |
1428 | needs_clflush_before, | |
1429 | needs_clflush_after); | |
1430 | } | |
1431 | ||
1432 | static int | |
1433 | i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, | |
1434 | const struct drm_i915_gem_pwrite *args) | |
1435 | { | |
1436 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
1437 | void __user *user_data; | |
1438 | u64 remain; | |
1439 | unsigned int obj_do_bit17_swizzling; | |
1440 | unsigned int partial_cacheline_write; | |
43394c7d | 1441 | unsigned int needs_clflush; |
fe115628 CW |
1442 | unsigned int offset, idx; |
1443 | int ret; | |
40123c1f | 1444 | |
fe115628 | 1445 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
755d2218 CW |
1446 | if (ret) |
1447 | return ret; | |
1448 | ||
fe115628 CW |
1449 | ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); |
1450 | mutex_unlock(&i915->drm.struct_mutex); | |
1451 | if (ret) | |
1452 | return ret; | |
673a394b | 1453 | |
fe115628 CW |
1454 | obj_do_bit17_swizzling = 0; |
1455 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
1456 | obj_do_bit17_swizzling = BIT(17); | |
e5281ccd | 1457 | |
fe115628 CW |
1458 | /* If we don't overwrite a cacheline completely we need to be |
1459 | * careful to have up-to-date data by first clflushing. Don't | |
1460 | * overcomplicate things and flush the entire patch. | |
1461 | */ | |
1462 | partial_cacheline_write = 0; | |
1463 | if (needs_clflush & CLFLUSH_BEFORE) | |
1464 | partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1; | |
9da3da66 | 1465 | |
fe115628 CW |
1466 | user_data = u64_to_user_ptr(args->data_ptr); |
1467 | remain = args->size; | |
1468 | offset = offset_in_page(args->offset); | |
1469 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
1470 | struct page *page = i915_gem_object_get_page(obj, idx); | |
1471 | int length; | |
40123c1f | 1472 | |
fe115628 CW |
1473 | length = remain; |
1474 | if (offset + length > PAGE_SIZE) | |
1475 | length = PAGE_SIZE - offset; | |
755d2218 | 1476 | |
fe115628 CW |
1477 | ret = shmem_pwrite(page, offset, length, user_data, |
1478 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1479 | (offset | length) & partial_cacheline_write, | |
1480 | needs_clflush & CLFLUSH_AFTER); | |
755d2218 | 1481 | if (ret) |
fe115628 | 1482 | break; |
755d2218 | 1483 | |
fe115628 CW |
1484 | remain -= length; |
1485 | user_data += length; | |
1486 | offset = 0; | |
8c59967c | 1487 | } |
673a394b | 1488 | |
d59b21ec | 1489 | intel_fb_obj_flush(obj, ORIGIN_CPU); |
fe115628 | 1490 | i915_gem_obj_finish_shmem_access(obj); |
40123c1f | 1491 | return ret; |
673a394b EA |
1492 | } |
1493 | ||
1494 | /** | |
1495 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1496 | * @dev: drm device |
1497 | * @data: ioctl data blob | |
1498 | * @file: drm file | |
673a394b EA |
1499 | * |
1500 | * On error, the contents of the buffer that were to be modified are undefined. | |
1501 | */ | |
1502 | int | |
1503 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1504 | struct drm_file *file) |
673a394b EA |
1505 | { |
1506 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1507 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1508 | int ret; |
1509 | ||
1510 | if (args->size == 0) | |
1511 | return 0; | |
1512 | ||
1513 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1514 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1515 | args->size)) |
1516 | return -EFAULT; | |
1517 | ||
03ac0642 | 1518 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1519 | if (!obj) |
1520 | return -ENOENT; | |
673a394b | 1521 | |
7dcd2499 | 1522 | /* Bounds check destination. */ |
966d5bf5 | 1523 | if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { |
ce9d419d | 1524 | ret = -EINVAL; |
258a5ede | 1525 | goto err; |
ce9d419d CW |
1526 | } |
1527 | ||
db53a302 CW |
1528 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1529 | ||
7c55e2c5 CW |
1530 | ret = -ENODEV; |
1531 | if (obj->ops->pwrite) | |
1532 | ret = obj->ops->pwrite(obj, args); | |
1533 | if (ret != -ENODEV) | |
1534 | goto err; | |
1535 | ||
e95433c7 CW |
1536 | ret = i915_gem_object_wait(obj, |
1537 | I915_WAIT_INTERRUPTIBLE | | |
1538 | I915_WAIT_ALL, | |
1539 | MAX_SCHEDULE_TIMEOUT, | |
1540 | to_rps_client(file)); | |
258a5ede CW |
1541 | if (ret) |
1542 | goto err; | |
1543 | ||
fe115628 | 1544 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1545 | if (ret) |
fe115628 | 1546 | goto err; |
258a5ede | 1547 | |
935aaa69 | 1548 | ret = -EFAULT; |
673a394b EA |
1549 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1550 | * it would end up going through the fenced access, and we'll get | |
1551 | * different detiling behavior between reading and writing. | |
1552 | * pread/pwrite currently are reading and writing from the CPU | |
1553 | * perspective, requiring manual detiling by the client. | |
1554 | */ | |
6eae0059 | 1555 | if (!i915_gem_object_has_struct_page(obj) || |
9c870d03 | 1556 | cpu_write_needs_clflush(obj)) |
935aaa69 DV |
1557 | /* Note that the gtt paths might fail with non-page-backed user |
1558 | * pointers (e.g. gtt mappings when moving data between | |
9c870d03 CW |
1559 | * textures). Fallback to the shmem path in that case. |
1560 | */ | |
fe115628 | 1561 | ret = i915_gem_gtt_pwrite_fast(obj, args); |
673a394b | 1562 | |
d1054ee4 | 1563 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1564 | if (obj->phys_handle) |
1565 | ret = i915_gem_phys_pwrite(obj, args, file); | |
b50a5371 | 1566 | else |
fe115628 | 1567 | ret = i915_gem_shmem_pwrite(obj, args); |
6a2c4232 | 1568 | } |
5c0480f2 | 1569 | |
fe115628 | 1570 | i915_gem_object_unpin_pages(obj); |
258a5ede | 1571 | err: |
f0cd5182 | 1572 | i915_gem_object_put(obj); |
258a5ede | 1573 | return ret; |
673a394b EA |
1574 | } |
1575 | ||
40e62d5d CW |
1576 | static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj) |
1577 | { | |
1578 | struct drm_i915_private *i915; | |
1579 | struct list_head *list; | |
1580 | struct i915_vma *vma; | |
1581 | ||
1582 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
1583 | if (!i915_vma_is_ggtt(vma)) | |
28f412e0 | 1584 | break; |
40e62d5d CW |
1585 | |
1586 | if (i915_vma_is_active(vma)) | |
1587 | continue; | |
1588 | ||
1589 | if (!drm_mm_node_allocated(&vma->node)) | |
1590 | continue; | |
1591 | ||
1592 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
1593 | } | |
1594 | ||
1595 | i915 = to_i915(obj->base.dev); | |
1596 | list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list; | |
56cea323 | 1597 | list_move_tail(&obj->global_link, list); |
40e62d5d CW |
1598 | } |
1599 | ||
673a394b | 1600 | /** |
2ef7eeaa EA |
1601 | * Called when user space prepares to use an object with the CPU, either |
1602 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1603 | * @dev: drm device |
1604 | * @data: ioctl data blob | |
1605 | * @file: drm file | |
673a394b EA |
1606 | */ |
1607 | int | |
1608 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1609 | struct drm_file *file) |
673a394b EA |
1610 | { |
1611 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1612 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1613 | uint32_t read_domains = args->read_domains; |
1614 | uint32_t write_domain = args->write_domain; | |
40e62d5d | 1615 | int err; |
673a394b | 1616 | |
2ef7eeaa | 1617 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1618 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1619 | return -EINVAL; |
1620 | ||
1621 | /* Having something in the write domain implies it's in the read | |
1622 | * domain, and only that read domain. Enforce that in the request. | |
1623 | */ | |
1624 | if (write_domain != 0 && read_domains != write_domain) | |
1625 | return -EINVAL; | |
1626 | ||
03ac0642 | 1627 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1628 | if (!obj) |
1629 | return -ENOENT; | |
673a394b | 1630 | |
3236f57a CW |
1631 | /* Try to flush the object off the GPU without holding the lock. |
1632 | * We will repeat the flush holding the lock in the normal manner | |
1633 | * to catch cases where we are gazumped. | |
1634 | */ | |
40e62d5d | 1635 | err = i915_gem_object_wait(obj, |
e95433c7 CW |
1636 | I915_WAIT_INTERRUPTIBLE | |
1637 | (write_domain ? I915_WAIT_ALL : 0), | |
1638 | MAX_SCHEDULE_TIMEOUT, | |
1639 | to_rps_client(file)); | |
40e62d5d | 1640 | if (err) |
f0cd5182 | 1641 | goto out; |
b8f9096d | 1642 | |
40e62d5d CW |
1643 | /* Flush and acquire obj->pages so that we are coherent through |
1644 | * direct access in memory with previous cached writes through | |
1645 | * shmemfs and that our cache domain tracking remains valid. | |
1646 | * For example, if the obj->filp was moved to swap without us | |
1647 | * being notified and releasing the pages, we would mistakenly | |
1648 | * continue to assume that the obj remained out of the CPU cached | |
1649 | * domain. | |
1650 | */ | |
1651 | err = i915_gem_object_pin_pages(obj); | |
1652 | if (err) | |
f0cd5182 | 1653 | goto out; |
40e62d5d CW |
1654 | |
1655 | err = i915_mutex_lock_interruptible(dev); | |
1656 | if (err) | |
f0cd5182 | 1657 | goto out_unpin; |
3236f57a | 1658 | |
e22d8e3c CW |
1659 | if (read_domains & I915_GEM_DOMAIN_WC) |
1660 | err = i915_gem_object_set_to_wc_domain(obj, write_domain); | |
1661 | else if (read_domains & I915_GEM_DOMAIN_GTT) | |
1662 | err = i915_gem_object_set_to_gtt_domain(obj, write_domain); | |
43566ded | 1663 | else |
e22d8e3c | 1664 | err = i915_gem_object_set_to_cpu_domain(obj, write_domain); |
2ef7eeaa | 1665 | |
40e62d5d CW |
1666 | /* And bump the LRU for this access */ |
1667 | i915_gem_object_bump_inactive_ggtt(obj); | |
031b698a | 1668 | |
673a394b | 1669 | mutex_unlock(&dev->struct_mutex); |
b8f9096d | 1670 | |
40e62d5d | 1671 | if (write_domain != 0) |
ef74921b CW |
1672 | intel_fb_obj_invalidate(obj, |
1673 | fb_write_origin(obj, write_domain)); | |
40e62d5d | 1674 | |
f0cd5182 | 1675 | out_unpin: |
40e62d5d | 1676 | i915_gem_object_unpin_pages(obj); |
f0cd5182 CW |
1677 | out: |
1678 | i915_gem_object_put(obj); | |
40e62d5d | 1679 | return err; |
673a394b EA |
1680 | } |
1681 | ||
1682 | /** | |
1683 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1684 | * @dev: drm device |
1685 | * @data: ioctl data blob | |
1686 | * @file: drm file | |
673a394b EA |
1687 | */ |
1688 | int | |
1689 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1690 | struct drm_file *file) |
673a394b EA |
1691 | { |
1692 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1693 | struct drm_i915_gem_object *obj; |
1d7cfea1 | 1694 | |
03ac0642 | 1695 | obj = i915_gem_object_lookup(file, args->handle); |
c21724cc CW |
1696 | if (!obj) |
1697 | return -ENOENT; | |
673a394b | 1698 | |
673a394b | 1699 | /* Pinned buffers may be scanout, so flush the cache */ |
5a97bcc6 | 1700 | i915_gem_object_flush_if_display(obj); |
f0cd5182 | 1701 | i915_gem_object_put(obj); |
5a97bcc6 CW |
1702 | |
1703 | return 0; | |
673a394b EA |
1704 | } |
1705 | ||
1706 | /** | |
14bb2c11 TU |
1707 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1708 | * it is mapped to. | |
1709 | * @dev: drm device | |
1710 | * @data: ioctl data blob | |
1711 | * @file: drm file | |
673a394b EA |
1712 | * |
1713 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1714 | * imply a ref on the object itself. | |
34367381 DV |
1715 | * |
1716 | * IMPORTANT: | |
1717 | * | |
1718 | * DRM driver writers who look a this function as an example for how to do GEM | |
1719 | * mmap support, please don't implement mmap support like here. The modern way | |
1720 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1721 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1722 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1723 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1724 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1725 | */ |
1726 | int | |
1727 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1728 | struct drm_file *file) |
673a394b EA |
1729 | { |
1730 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1731 | struct drm_i915_gem_object *obj; |
673a394b EA |
1732 | unsigned long addr; |
1733 | ||
1816f923 AG |
1734 | if (args->flags & ~(I915_MMAP_WC)) |
1735 | return -EINVAL; | |
1736 | ||
568a58e5 | 1737 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1738 | return -ENODEV; |
1739 | ||
03ac0642 CW |
1740 | obj = i915_gem_object_lookup(file, args->handle); |
1741 | if (!obj) | |
bf79cb91 | 1742 | return -ENOENT; |
673a394b | 1743 | |
1286ff73 DV |
1744 | /* prime objects have no backing filp to GEM mmap |
1745 | * pages from. | |
1746 | */ | |
03ac0642 | 1747 | if (!obj->base.filp) { |
f0cd5182 | 1748 | i915_gem_object_put(obj); |
1286ff73 DV |
1749 | return -EINVAL; |
1750 | } | |
1751 | ||
03ac0642 | 1752 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1753 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1754 | args->offset); | |
1816f923 AG |
1755 | if (args->flags & I915_MMAP_WC) { |
1756 | struct mm_struct *mm = current->mm; | |
1757 | struct vm_area_struct *vma; | |
1758 | ||
80a89a5e | 1759 | if (down_write_killable(&mm->mmap_sem)) { |
f0cd5182 | 1760 | i915_gem_object_put(obj); |
80a89a5e MH |
1761 | return -EINTR; |
1762 | } | |
1816f923 AG |
1763 | vma = find_vma(mm, addr); |
1764 | if (vma) | |
1765 | vma->vm_page_prot = | |
1766 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1767 | else | |
1768 | addr = -ENOMEM; | |
1769 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1770 | |
1771 | /* This may race, but that's ok, it only gets set */ | |
50349247 | 1772 | WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU); |
1816f923 | 1773 | } |
f0cd5182 | 1774 | i915_gem_object_put(obj); |
673a394b EA |
1775 | if (IS_ERR((void *)addr)) |
1776 | return addr; | |
1777 | ||
1778 | args->addr_ptr = (uint64_t) addr; | |
1779 | ||
1780 | return 0; | |
1781 | } | |
1782 | ||
03af84fe CW |
1783 | static unsigned int tile_row_pages(struct drm_i915_gem_object *obj) |
1784 | { | |
6649a0b6 | 1785 | return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT; |
03af84fe CW |
1786 | } |
1787 | ||
4cc69075 CW |
1788 | /** |
1789 | * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps | |
1790 | * | |
1791 | * A history of the GTT mmap interface: | |
1792 | * | |
1793 | * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to | |
1794 | * aligned and suitable for fencing, and still fit into the available | |
1795 | * mappable space left by the pinned display objects. A classic problem | |
1796 | * we called the page-fault-of-doom where we would ping-pong between | |
1797 | * two objects that could not fit inside the GTT and so the memcpy | |
1798 | * would page one object in at the expense of the other between every | |
1799 | * single byte. | |
1800 | * | |
1801 | * 1 - Objects can be any size, and have any compatible fencing (X Y, or none | |
1802 | * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the | |
1803 | * object is too large for the available space (or simply too large | |
1804 | * for the mappable aperture!), a view is created instead and faulted | |
1805 | * into userspace. (This view is aligned and sized appropriately for | |
1806 | * fenced access.) | |
1807 | * | |
e22d8e3c CW |
1808 | * 2 - Recognise WC as a separate cache domain so that we can flush the |
1809 | * delayed writes via GTT before performing direct access via WC. | |
1810 | * | |
4cc69075 CW |
1811 | * Restrictions: |
1812 | * | |
1813 | * * snoopable objects cannot be accessed via the GTT. It can cause machine | |
1814 | * hangs on some architectures, corruption on others. An attempt to service | |
1815 | * a GTT page fault from a snoopable object will generate a SIGBUS. | |
1816 | * | |
1817 | * * the object must be able to fit into RAM (physical memory, though no | |
1818 | * limited to the mappable aperture). | |
1819 | * | |
1820 | * | |
1821 | * Caveats: | |
1822 | * | |
1823 | * * a new GTT page fault will synchronize rendering from the GPU and flush | |
1824 | * all data to system memory. Subsequent access will not be synchronized. | |
1825 | * | |
1826 | * * all mappings are revoked on runtime device suspend. | |
1827 | * | |
1828 | * * there are only 8, 16 or 32 fence registers to share between all users | |
1829 | * (older machines require fence register for display and blitter access | |
1830 | * as well). Contention of the fence registers will cause the previous users | |
1831 | * to be unmapped and any new access will generate new page faults. | |
1832 | * | |
1833 | * * running out of memory while servicing a fault may generate a SIGBUS, | |
1834 | * rather than the expected SIGSEGV. | |
1835 | */ | |
1836 | int i915_gem_mmap_gtt_version(void) | |
1837 | { | |
e22d8e3c | 1838 | return 2; |
4cc69075 CW |
1839 | } |
1840 | ||
2d4281bb CW |
1841 | static inline struct i915_ggtt_view |
1842 | compute_partial_view(struct drm_i915_gem_object *obj, | |
2d4281bb CW |
1843 | pgoff_t page_offset, |
1844 | unsigned int chunk) | |
1845 | { | |
1846 | struct i915_ggtt_view view; | |
1847 | ||
1848 | if (i915_gem_object_is_tiled(obj)) | |
1849 | chunk = roundup(chunk, tile_row_pages(obj)); | |
1850 | ||
2d4281bb | 1851 | view.type = I915_GGTT_VIEW_PARTIAL; |
8bab1193 CW |
1852 | view.partial.offset = rounddown(page_offset, chunk); |
1853 | view.partial.size = | |
2d4281bb | 1854 | min_t(unsigned int, chunk, |
8bab1193 | 1855 | (obj->base.size >> PAGE_SHIFT) - view.partial.offset); |
2d4281bb CW |
1856 | |
1857 | /* If the partial covers the entire object, just create a normal VMA. */ | |
1858 | if (chunk >= obj->base.size >> PAGE_SHIFT) | |
1859 | view.type = I915_GGTT_VIEW_NORMAL; | |
1860 | ||
1861 | return view; | |
1862 | } | |
1863 | ||
de151cf6 JB |
1864 | /** |
1865 | * i915_gem_fault - fault a page into the GTT | |
d9072a3e | 1866 | * @vmf: fault info |
de151cf6 JB |
1867 | * |
1868 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1869 | * from userspace. The fault handler takes care of binding the object to | |
1870 | * the GTT (if needed), allocating and programming a fence register (again, | |
1871 | * only if needed based on whether the old reg is still valid or the object | |
1872 | * is tiled) and inserting a new PTE into the faulting process. | |
1873 | * | |
1874 | * Note that the faulting process may involve evicting existing objects | |
1875 | * from the GTT and/or fence registers to make room. So performance may | |
1876 | * suffer if the GTT working set is large or there are few fence registers | |
1877 | * left. | |
4cc69075 CW |
1878 | * |
1879 | * The current feature set supported by i915_gem_fault() and thus GTT mmaps | |
1880 | * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version). | |
de151cf6 | 1881 | */ |
11bac800 | 1882 | int i915_gem_fault(struct vm_fault *vmf) |
de151cf6 | 1883 | { |
03af84fe | 1884 | #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */ |
11bac800 | 1885 | struct vm_area_struct *area = vmf->vma; |
058d88c4 | 1886 | struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data); |
05394f39 | 1887 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
1888 | struct drm_i915_private *dev_priv = to_i915(dev); |
1889 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b8f9096d | 1890 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
058d88c4 | 1891 | struct i915_vma *vma; |
de151cf6 | 1892 | pgoff_t page_offset; |
82118877 | 1893 | unsigned int flags; |
b8f9096d | 1894 | int ret; |
f65c9168 | 1895 | |
de151cf6 | 1896 | /* We don't use vmf->pgoff since that has the fake offset */ |
1a29d85e | 1897 | page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT; |
de151cf6 | 1898 | |
db53a302 CW |
1899 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1900 | ||
6e4930f6 | 1901 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 1902 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
1903 | * repeat the flush holding the lock in the normal manner to catch cases |
1904 | * where we are gazumped. | |
1905 | */ | |
e95433c7 CW |
1906 | ret = i915_gem_object_wait(obj, |
1907 | I915_WAIT_INTERRUPTIBLE, | |
1908 | MAX_SCHEDULE_TIMEOUT, | |
1909 | NULL); | |
6e4930f6 | 1910 | if (ret) |
b8f9096d CW |
1911 | goto err; |
1912 | ||
40e62d5d CW |
1913 | ret = i915_gem_object_pin_pages(obj); |
1914 | if (ret) | |
1915 | goto err; | |
1916 | ||
b8f9096d CW |
1917 | intel_runtime_pm_get(dev_priv); |
1918 | ||
1919 | ret = i915_mutex_lock_interruptible(dev); | |
1920 | if (ret) | |
1921 | goto err_rpm; | |
6e4930f6 | 1922 | |
eb119bd6 | 1923 | /* Access to snoopable pages through the GTT is incoherent. */ |
0031fb96 | 1924 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) { |
ddeff6ee | 1925 | ret = -EFAULT; |
b8f9096d | 1926 | goto err_unlock; |
eb119bd6 CW |
1927 | } |
1928 | ||
82118877 CW |
1929 | /* If the object is smaller than a couple of partial vma, it is |
1930 | * not worth only creating a single partial vma - we may as well | |
1931 | * clear enough space for the full object. | |
1932 | */ | |
1933 | flags = PIN_MAPPABLE; | |
1934 | if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT) | |
1935 | flags |= PIN_NONBLOCK | PIN_NONFAULT; | |
1936 | ||
a61007a8 | 1937 | /* Now pin it into the GTT as needed */ |
82118877 | 1938 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags); |
a61007a8 | 1939 | if (IS_ERR(vma)) { |
a61007a8 | 1940 | /* Use a partial view if it is bigger than available space */ |
2d4281bb | 1941 | struct i915_ggtt_view view = |
8201c1fa | 1942 | compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES); |
aa136d9d | 1943 | |
50349247 CW |
1944 | /* Userspace is now writing through an untracked VMA, abandon |
1945 | * all hope that the hardware is able to track future writes. | |
1946 | */ | |
1947 | obj->frontbuffer_ggtt_origin = ORIGIN_CPU; | |
1948 | ||
a61007a8 CW |
1949 | vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
1950 | } | |
058d88c4 CW |
1951 | if (IS_ERR(vma)) { |
1952 | ret = PTR_ERR(vma); | |
b8f9096d | 1953 | goto err_unlock; |
058d88c4 | 1954 | } |
4a684a41 | 1955 | |
c9839303 CW |
1956 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1957 | if (ret) | |
b8f9096d | 1958 | goto err_unpin; |
74898d7e | 1959 | |
49ef5294 | 1960 | ret = i915_vma_get_fence(vma); |
d9e86c0e | 1961 | if (ret) |
b8f9096d | 1962 | goto err_unpin; |
7d1c4804 | 1963 | |
275f039d | 1964 | /* Mark as being mmapped into userspace for later revocation */ |
9c870d03 | 1965 | assert_rpm_wakelock_held(dev_priv); |
275f039d CW |
1966 | if (list_empty(&obj->userfault_link)) |
1967 | list_add(&obj->userfault_link, &dev_priv->mm.userfault_list); | |
275f039d | 1968 | |
b90b91d8 | 1969 | /* Finally, remap it using the new GTT offset */ |
c58305af | 1970 | ret = remap_io_mapping(area, |
8bab1193 | 1971 | area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT), |
c58305af CW |
1972 | (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT, |
1973 | min_t(u64, vma->size, area->vm_end - area->vm_start), | |
1974 | &ggtt->mappable); | |
a61007a8 | 1975 | |
b8f9096d | 1976 | err_unpin: |
058d88c4 | 1977 | __i915_vma_unpin(vma); |
b8f9096d | 1978 | err_unlock: |
de151cf6 | 1979 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
1980 | err_rpm: |
1981 | intel_runtime_pm_put(dev_priv); | |
40e62d5d | 1982 | i915_gem_object_unpin_pages(obj); |
b8f9096d | 1983 | err: |
de151cf6 | 1984 | switch (ret) { |
d9bc7e9f | 1985 | case -EIO: |
2232f031 DV |
1986 | /* |
1987 | * We eat errors when the gpu is terminally wedged to avoid | |
1988 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1989 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1990 | * and so needs to be reported. | |
1991 | */ | |
1992 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1993 | ret = VM_FAULT_SIGBUS; |
1994 | break; | |
1995 | } | |
045e769a | 1996 | case -EAGAIN: |
571c608d DV |
1997 | /* |
1998 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1999 | * handler to reset everything when re-faulting in | |
2000 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 2001 | */ |
c715089f CW |
2002 | case 0: |
2003 | case -ERESTARTSYS: | |
bed636ab | 2004 | case -EINTR: |
e79e0fe3 DR |
2005 | case -EBUSY: |
2006 | /* | |
2007 | * EBUSY is ok: this just means that another thread | |
2008 | * already did the job. | |
2009 | */ | |
f65c9168 PZ |
2010 | ret = VM_FAULT_NOPAGE; |
2011 | break; | |
de151cf6 | 2012 | case -ENOMEM: |
f65c9168 PZ |
2013 | ret = VM_FAULT_OOM; |
2014 | break; | |
a7c2e1aa | 2015 | case -ENOSPC: |
45d67817 | 2016 | case -EFAULT: |
f65c9168 PZ |
2017 | ret = VM_FAULT_SIGBUS; |
2018 | break; | |
de151cf6 | 2019 | default: |
a7c2e1aa | 2020 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
2021 | ret = VM_FAULT_SIGBUS; |
2022 | break; | |
de151cf6 | 2023 | } |
f65c9168 | 2024 | return ret; |
de151cf6 JB |
2025 | } |
2026 | ||
901782b2 CW |
2027 | /** |
2028 | * i915_gem_release_mmap - remove physical page mappings | |
2029 | * @obj: obj in question | |
2030 | * | |
af901ca1 | 2031 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
2032 | * relinquish ownership of the pages back to the system. |
2033 | * | |
2034 | * It is vital that we remove the page mapping if we have mapped a tiled | |
2035 | * object through the GTT and then lose the fence register due to | |
2036 | * resource pressure. Similarly if the object has been moved out of the | |
2037 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
2038 | * mapping will then trigger a page fault on the next user access, allowing | |
2039 | * fixup by i915_gem_fault(). | |
2040 | */ | |
d05ca301 | 2041 | void |
05394f39 | 2042 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 2043 | { |
275f039d | 2044 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
275f039d | 2045 | |
349f2ccf CW |
2046 | /* Serialisation between user GTT access and our code depends upon |
2047 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
2048 | * pagefault then has to wait until we release the mutex. | |
9c870d03 CW |
2049 | * |
2050 | * Note that RPM complicates somewhat by adding an additional | |
2051 | * requirement that operations to the GGTT be made holding the RPM | |
2052 | * wakeref. | |
349f2ccf | 2053 | */ |
275f039d | 2054 | lockdep_assert_held(&i915->drm.struct_mutex); |
9c870d03 | 2055 | intel_runtime_pm_get(i915); |
349f2ccf | 2056 | |
3594a3e2 | 2057 | if (list_empty(&obj->userfault_link)) |
9c870d03 | 2058 | goto out; |
901782b2 | 2059 | |
3594a3e2 | 2060 | list_del_init(&obj->userfault_link); |
6796cb16 DR |
2061 | drm_vma_node_unmap(&obj->base.vma_node, |
2062 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
2063 | |
2064 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
2065 | * memory transactions from userspace before we return. The TLB | |
2066 | * flushing implied above by changing the PTE above *should* be | |
2067 | * sufficient, an extra barrier here just provides us with a bit | |
2068 | * of paranoid documentation about our requirement to serialise | |
2069 | * memory writes before touching registers / GSM. | |
2070 | */ | |
2071 | wmb(); | |
9c870d03 CW |
2072 | |
2073 | out: | |
2074 | intel_runtime_pm_put(i915); | |
901782b2 CW |
2075 | } |
2076 | ||
7c108fd8 | 2077 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) |
eedd10f4 | 2078 | { |
3594a3e2 | 2079 | struct drm_i915_gem_object *obj, *on; |
7c108fd8 | 2080 | int i; |
eedd10f4 | 2081 | |
3594a3e2 CW |
2082 | /* |
2083 | * Only called during RPM suspend. All users of the userfault_list | |
2084 | * must be holding an RPM wakeref to ensure that this can not | |
2085 | * run concurrently with themselves (and use the struct_mutex for | |
2086 | * protection between themselves). | |
2087 | */ | |
275f039d | 2088 | |
3594a3e2 CW |
2089 | list_for_each_entry_safe(obj, on, |
2090 | &dev_priv->mm.userfault_list, userfault_link) { | |
2091 | list_del_init(&obj->userfault_link); | |
275f039d CW |
2092 | drm_vma_node_unmap(&obj->base.vma_node, |
2093 | obj->base.dev->anon_inode->i_mapping); | |
275f039d | 2094 | } |
7c108fd8 CW |
2095 | |
2096 | /* The fence will be lost when the device powers down. If any were | |
2097 | * in use by hardware (i.e. they are pinned), we should not be powering | |
2098 | * down! All other fences will be reacquired by the user upon waking. | |
2099 | */ | |
2100 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
2101 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
2102 | ||
e0ec3ec6 CW |
2103 | /* Ideally we want to assert that the fence register is not |
2104 | * live at this point (i.e. that no piece of code will be | |
2105 | * trying to write through fence + GTT, as that both violates | |
2106 | * our tracking of activity and associated locking/barriers, | |
2107 | * but also is illegal given that the hw is powered down). | |
2108 | * | |
2109 | * Previously we used reg->pin_count as a "liveness" indicator. | |
2110 | * That is not sufficient, and we need a more fine-grained | |
2111 | * tool if we want to have a sanity check here. | |
2112 | */ | |
7c108fd8 CW |
2113 | |
2114 | if (!reg->vma) | |
2115 | continue; | |
2116 | ||
2117 | GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link)); | |
2118 | reg->dirty = true; | |
2119 | } | |
eedd10f4 CW |
2120 | } |
2121 | ||
d8cb5086 CW |
2122 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2123 | { | |
fac5e23e | 2124 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 2125 | int err; |
da494d7c | 2126 | |
f3f6184c | 2127 | err = drm_gem_create_mmap_offset(&obj->base); |
b42a13d9 | 2128 | if (likely(!err)) |
f3f6184c | 2129 | return 0; |
d8cb5086 | 2130 | |
b42a13d9 CW |
2131 | /* Attempt to reap some mmap space from dead objects */ |
2132 | do { | |
2133 | err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE); | |
2134 | if (err) | |
2135 | break; | |
f3f6184c | 2136 | |
b42a13d9 | 2137 | i915_gem_drain_freed_objects(dev_priv); |
f3f6184c | 2138 | err = drm_gem_create_mmap_offset(&obj->base); |
b42a13d9 CW |
2139 | if (!err) |
2140 | break; | |
2141 | ||
2142 | } while (flush_delayed_work(&dev_priv->gt.retire_work)); | |
da494d7c | 2143 | |
f3f6184c | 2144 | return err; |
d8cb5086 CW |
2145 | } |
2146 | ||
2147 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2148 | { | |
d8cb5086 CW |
2149 | drm_gem_free_mmap_offset(&obj->base); |
2150 | } | |
2151 | ||
da6b51d0 | 2152 | int |
ff72145b DA |
2153 | i915_gem_mmap_gtt(struct drm_file *file, |
2154 | struct drm_device *dev, | |
da6b51d0 | 2155 | uint32_t handle, |
ff72145b | 2156 | uint64_t *offset) |
de151cf6 | 2157 | { |
05394f39 | 2158 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2159 | int ret; |
2160 | ||
03ac0642 | 2161 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
2162 | if (!obj) |
2163 | return -ENOENT; | |
ab18282d | 2164 | |
d8cb5086 | 2165 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
2166 | if (ret == 0) |
2167 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 2168 | |
f0cd5182 | 2169 | i915_gem_object_put(obj); |
1d7cfea1 | 2170 | return ret; |
de151cf6 JB |
2171 | } |
2172 | ||
ff72145b DA |
2173 | /** |
2174 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2175 | * @dev: DRM device | |
2176 | * @data: GTT mapping ioctl data | |
2177 | * @file: GEM object info | |
2178 | * | |
2179 | * Simply returns the fake offset to userspace so it can mmap it. | |
2180 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2181 | * up so we can get faults in the handler above. | |
2182 | * | |
2183 | * The fault handler will take care of binding the object into the GTT | |
2184 | * (since it may have been evicted to make room for something), allocating | |
2185 | * a fence register, and mapping the appropriate aperture address into | |
2186 | * userspace. | |
2187 | */ | |
2188 | int | |
2189 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2190 | struct drm_file *file) | |
2191 | { | |
2192 | struct drm_i915_gem_mmap_gtt *args = data; | |
2193 | ||
da6b51d0 | 2194 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2195 | } |
2196 | ||
225067ee DV |
2197 | /* Immediately discard the backing storage */ |
2198 | static void | |
2199 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2200 | { |
4d6294bf | 2201 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2202 | |
4d6294bf CW |
2203 | if (obj->base.filp == NULL) |
2204 | return; | |
e5281ccd | 2205 | |
225067ee DV |
2206 | /* Our goal here is to return as much of the memory as |
2207 | * is possible back to the system as we are called from OOM. | |
2208 | * To do this we must instruct the shmfs to drop all of its | |
2209 | * backing pages, *now*. | |
2210 | */ | |
5537252b | 2211 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
a4f5ea64 | 2212 | obj->mm.madv = __I915_MADV_PURGED; |
4e5462ee | 2213 | obj->mm.pages = ERR_PTR(-EFAULT); |
225067ee | 2214 | } |
e5281ccd | 2215 | |
5537252b | 2216 | /* Try to discard unwanted pages */ |
03ac84f1 | 2217 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
225067ee | 2218 | { |
5537252b CW |
2219 | struct address_space *mapping; |
2220 | ||
1233e2db CW |
2221 | lockdep_assert_held(&obj->mm.lock); |
2222 | GEM_BUG_ON(obj->mm.pages); | |
2223 | ||
a4f5ea64 | 2224 | switch (obj->mm.madv) { |
5537252b CW |
2225 | case I915_MADV_DONTNEED: |
2226 | i915_gem_object_truncate(obj); | |
2227 | case __I915_MADV_PURGED: | |
2228 | return; | |
2229 | } | |
2230 | ||
2231 | if (obj->base.filp == NULL) | |
2232 | return; | |
2233 | ||
93c76a3d | 2234 | mapping = obj->base.filp->f_mapping, |
5537252b | 2235 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
e5281ccd CW |
2236 | } |
2237 | ||
5cdf5881 | 2238 | static void |
03ac84f1 CW |
2239 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj, |
2240 | struct sg_table *pages) | |
673a394b | 2241 | { |
85d1225e DG |
2242 | struct sgt_iter sgt_iter; |
2243 | struct page *page; | |
1286ff73 | 2244 | |
e5facdf9 | 2245 | __i915_gem_object_release_shmem(obj, pages, true); |
673a394b | 2246 | |
03ac84f1 | 2247 | i915_gem_gtt_finish_pages(obj, pages); |
e2273302 | 2248 | |
6dacfd2f | 2249 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2250 | i915_gem_object_save_bit_17_swizzle(obj, pages); |
280b713b | 2251 | |
03ac84f1 | 2252 | for_each_sgt_page(page, sgt_iter, pages) { |
a4f5ea64 | 2253 | if (obj->mm.dirty) |
9da3da66 | 2254 | set_page_dirty(page); |
3ef94daa | 2255 | |
a4f5ea64 | 2256 | if (obj->mm.madv == I915_MADV_WILLNEED) |
9da3da66 | 2257 | mark_page_accessed(page); |
3ef94daa | 2258 | |
09cbfeaf | 2259 | put_page(page); |
3ef94daa | 2260 | } |
a4f5ea64 | 2261 | obj->mm.dirty = false; |
673a394b | 2262 | |
03ac84f1 CW |
2263 | sg_free_table(pages); |
2264 | kfree(pages); | |
37e680a1 | 2265 | } |
6c085a72 | 2266 | |
96d77634 CW |
2267 | static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj) |
2268 | { | |
2269 | struct radix_tree_iter iter; | |
2270 | void **slot; | |
2271 | ||
a4f5ea64 CW |
2272 | radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0) |
2273 | radix_tree_delete(&obj->mm.get_page.radix, iter.index); | |
96d77634 CW |
2274 | } |
2275 | ||
548625ee CW |
2276 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, |
2277 | enum i915_mm_subclass subclass) | |
37e680a1 | 2278 | { |
03ac84f1 | 2279 | struct sg_table *pages; |
37e680a1 | 2280 | |
a4f5ea64 | 2281 | if (i915_gem_object_has_pinned_pages(obj)) |
03ac84f1 | 2282 | return; |
a5570178 | 2283 | |
15717de2 | 2284 | GEM_BUG_ON(obj->bind_count); |
1233e2db CW |
2285 | if (!READ_ONCE(obj->mm.pages)) |
2286 | return; | |
2287 | ||
2288 | /* May be called by shrinker from within get_pages() (on another bo) */ | |
548625ee | 2289 | mutex_lock_nested(&obj->mm.lock, subclass); |
1233e2db CW |
2290 | if (unlikely(atomic_read(&obj->mm.pages_pin_count))) |
2291 | goto unlock; | |
3e123027 | 2292 | |
a2165e31 CW |
2293 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2294 | * array, hence protect them from being reaped by removing them from gtt | |
2295 | * lists early. */ | |
03ac84f1 CW |
2296 | pages = fetch_and_zero(&obj->mm.pages); |
2297 | GEM_BUG_ON(!pages); | |
a2165e31 | 2298 | |
a4f5ea64 | 2299 | if (obj->mm.mapping) { |
4b30cb23 CW |
2300 | void *ptr; |
2301 | ||
0ce81788 | 2302 | ptr = page_mask_bits(obj->mm.mapping); |
4b30cb23 CW |
2303 | if (is_vmalloc_addr(ptr)) |
2304 | vunmap(ptr); | |
fb8621d3 | 2305 | else |
4b30cb23 CW |
2306 | kunmap(kmap_to_page(ptr)); |
2307 | ||
a4f5ea64 | 2308 | obj->mm.mapping = NULL; |
0a798eb9 CW |
2309 | } |
2310 | ||
96d77634 CW |
2311 | __i915_gem_object_reset_page_iter(obj); |
2312 | ||
4e5462ee CW |
2313 | if (!IS_ERR(pages)) |
2314 | obj->ops->put_pages(obj, pages); | |
2315 | ||
1233e2db CW |
2316 | unlock: |
2317 | mutex_unlock(&obj->mm.lock); | |
6c085a72 CW |
2318 | } |
2319 | ||
935a2f77 | 2320 | static bool i915_sg_trim(struct sg_table *orig_st) |
0c40ce13 TU |
2321 | { |
2322 | struct sg_table new_st; | |
2323 | struct scatterlist *sg, *new_sg; | |
2324 | unsigned int i; | |
2325 | ||
2326 | if (orig_st->nents == orig_st->orig_nents) | |
935a2f77 | 2327 | return false; |
0c40ce13 | 2328 | |
8bfc478f | 2329 | if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN)) |
935a2f77 | 2330 | return false; |
0c40ce13 TU |
2331 | |
2332 | new_sg = new_st.sgl; | |
2333 | for_each_sg(orig_st->sgl, sg, orig_st->nents, i) { | |
2334 | sg_set_page(new_sg, sg_page(sg), sg->length, 0); | |
2335 | /* called before being DMA mapped, no need to copy sg->dma_* */ | |
2336 | new_sg = sg_next(new_sg); | |
2337 | } | |
c2dc6cc9 | 2338 | GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */ |
0c40ce13 TU |
2339 | |
2340 | sg_free_table(orig_st); | |
2341 | ||
2342 | *orig_st = new_st; | |
935a2f77 | 2343 | return true; |
0c40ce13 TU |
2344 | } |
2345 | ||
03ac84f1 | 2346 | static struct sg_table * |
6c085a72 | 2347 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2348 | { |
fac5e23e | 2349 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d766ef53 CW |
2350 | const unsigned long page_count = obj->base.size / PAGE_SIZE; |
2351 | unsigned long i; | |
e5281ccd | 2352 | struct address_space *mapping; |
9da3da66 CW |
2353 | struct sg_table *st; |
2354 | struct scatterlist *sg; | |
85d1225e | 2355 | struct sgt_iter sgt_iter; |
e5281ccd | 2356 | struct page *page; |
90797e6d | 2357 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
4ff340f0 | 2358 | unsigned int max_segment; |
4846bf0c | 2359 | gfp_t noreclaim; |
e2273302 | 2360 | int ret; |
e5281ccd | 2361 | |
6c085a72 CW |
2362 | /* Assert that the object is not currently in any GPU domain. As it |
2363 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2364 | * a GPU cache | |
2365 | */ | |
03ac84f1 CW |
2366 | GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2367 | GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
6c085a72 | 2368 | |
7453c549 | 2369 | max_segment = swiotlb_max_segment(); |
871dfbd6 | 2370 | if (!max_segment) |
4ff340f0 | 2371 | max_segment = rounddown(UINT_MAX, PAGE_SIZE); |
871dfbd6 | 2372 | |
9da3da66 CW |
2373 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2374 | if (st == NULL) | |
03ac84f1 | 2375 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2376 | |
d766ef53 | 2377 | rebuild_st: |
9da3da66 | 2378 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2379 | kfree(st); |
03ac84f1 | 2380 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2381 | } |
e5281ccd | 2382 | |
9da3da66 CW |
2383 | /* Get the list of pages out of our struct file. They'll be pinned |
2384 | * at this point until we release them. | |
2385 | * | |
2386 | * Fail silently without starting the shrinker | |
2387 | */ | |
93c76a3d | 2388 | mapping = obj->base.filp->f_mapping; |
0f6ab55d | 2389 | noreclaim = mapping_gfp_constraint(mapping, ~__GFP_RECLAIM); |
4846bf0c CW |
2390 | noreclaim |= __GFP_NORETRY | __GFP_NOWARN; |
2391 | ||
90797e6d ID |
2392 | sg = st->sgl; |
2393 | st->nents = 0; | |
2394 | for (i = 0; i < page_count; i++) { | |
4846bf0c CW |
2395 | const unsigned int shrink[] = { |
2396 | I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_PURGEABLE, | |
2397 | 0, | |
2398 | }, *s = shrink; | |
2399 | gfp_t gfp = noreclaim; | |
2400 | ||
2401 | do { | |
6c085a72 | 2402 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
4846bf0c CW |
2403 | if (likely(!IS_ERR(page))) |
2404 | break; | |
2405 | ||
2406 | if (!*s) { | |
2407 | ret = PTR_ERR(page); | |
2408 | goto err_sg; | |
2409 | } | |
2410 | ||
2411 | i915_gem_shrink(dev_priv, 2 * page_count, *s++); | |
2412 | cond_resched(); | |
24f8e00a | 2413 | |
6c085a72 CW |
2414 | /* We've tried hard to allocate the memory by reaping |
2415 | * our own buffer, now let the real VM do its job and | |
2416 | * go down in flames if truly OOM. | |
24f8e00a CW |
2417 | * |
2418 | * However, since graphics tend to be disposable, | |
2419 | * defer the oom here by reporting the ENOMEM back | |
2420 | * to userspace. | |
6c085a72 | 2421 | */ |
4846bf0c CW |
2422 | if (!*s) { |
2423 | /* reclaim and warn, but no oom */ | |
2424 | gfp = mapping_gfp_mask(mapping); | |
eaf41801 CW |
2425 | |
2426 | /* Our bo are always dirty and so we require | |
2427 | * kswapd to reclaim our pages (direct reclaim | |
2428 | * does not effectively begin pageout of our | |
2429 | * buffers on its own). However, direct reclaim | |
2430 | * only waits for kswapd when under allocation | |
2431 | * congestion. So as a result __GFP_RECLAIM is | |
2432 | * unreliable and fails to actually reclaim our | |
2433 | * dirty pages -- unless you try over and over | |
2434 | * again with !__GFP_NORETRY. However, we still | |
2435 | * want to fail this allocation rather than | |
2436 | * trigger the out-of-memory killer and for | |
2437 | * this we want the future __GFP_MAYFAIL. | |
2438 | */ | |
e2273302 | 2439 | } |
4846bf0c CW |
2440 | } while (1); |
2441 | ||
871dfbd6 CW |
2442 | if (!i || |
2443 | sg->length >= max_segment || | |
2444 | page_to_pfn(page) != last_pfn + 1) { | |
90797e6d ID |
2445 | if (i) |
2446 | sg = sg_next(sg); | |
2447 | st->nents++; | |
2448 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2449 | } else { | |
2450 | sg->length += PAGE_SIZE; | |
2451 | } | |
2452 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2453 | |
2454 | /* Check that the i965g/gm workaround works. */ | |
2455 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2456 | } |
871dfbd6 | 2457 | if (sg) /* loop terminated early; short sg table */ |
426729dc | 2458 | sg_mark_end(sg); |
74ce6b6c | 2459 | |
0c40ce13 TU |
2460 | /* Trim unused sg entries to avoid wasting memory. */ |
2461 | i915_sg_trim(st); | |
2462 | ||
03ac84f1 | 2463 | ret = i915_gem_gtt_prepare_pages(obj, st); |
d766ef53 CW |
2464 | if (ret) { |
2465 | /* DMA remapping failed? One possible cause is that | |
2466 | * it could not reserve enough large entries, asking | |
2467 | * for PAGE_SIZE chunks instead may be helpful. | |
2468 | */ | |
2469 | if (max_segment > PAGE_SIZE) { | |
2470 | for_each_sgt_page(page, sgt_iter, st) | |
2471 | put_page(page); | |
2472 | sg_free_table(st); | |
2473 | ||
2474 | max_segment = PAGE_SIZE; | |
2475 | goto rebuild_st; | |
2476 | } else { | |
2477 | dev_warn(&dev_priv->drm.pdev->dev, | |
2478 | "Failed to DMA remap %lu pages\n", | |
2479 | page_count); | |
2480 | goto err_pages; | |
2481 | } | |
2482 | } | |
e2273302 | 2483 | |
6dacfd2f | 2484 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2485 | i915_gem_object_do_bit_17_swizzle(obj, st); |
e5281ccd | 2486 | |
03ac84f1 | 2487 | return st; |
e5281ccd | 2488 | |
b17993b7 | 2489 | err_sg: |
90797e6d | 2490 | sg_mark_end(sg); |
b17993b7 | 2491 | err_pages: |
85d1225e DG |
2492 | for_each_sgt_page(page, sgt_iter, st) |
2493 | put_page(page); | |
9da3da66 CW |
2494 | sg_free_table(st); |
2495 | kfree(st); | |
0820baf3 CW |
2496 | |
2497 | /* shmemfs first checks if there is enough memory to allocate the page | |
2498 | * and reports ENOSPC should there be insufficient, along with the usual | |
2499 | * ENOMEM for a genuine allocation failure. | |
2500 | * | |
2501 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2502 | * space and so want to translate the error from shmemfs back to our | |
2503 | * usual understanding of ENOMEM. | |
2504 | */ | |
e2273302 ID |
2505 | if (ret == -ENOSPC) |
2506 | ret = -ENOMEM; | |
2507 | ||
03ac84f1 CW |
2508 | return ERR_PTR(ret); |
2509 | } | |
2510 | ||
2511 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, | |
2512 | struct sg_table *pages) | |
2513 | { | |
1233e2db | 2514 | lockdep_assert_held(&obj->mm.lock); |
03ac84f1 CW |
2515 | |
2516 | obj->mm.get_page.sg_pos = pages->sgl; | |
2517 | obj->mm.get_page.sg_idx = 0; | |
2518 | ||
2519 | obj->mm.pages = pages; | |
2c3a3f44 CW |
2520 | |
2521 | if (i915_gem_object_is_tiled(obj) && | |
2522 | to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
2523 | GEM_BUG_ON(obj->mm.quirked); | |
2524 | __i915_gem_object_pin_pages(obj); | |
2525 | obj->mm.quirked = true; | |
2526 | } | |
03ac84f1 CW |
2527 | } |
2528 | ||
2529 | static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2530 | { | |
2531 | struct sg_table *pages; | |
2532 | ||
2c3a3f44 CW |
2533 | GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); |
2534 | ||
03ac84f1 CW |
2535 | if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { |
2536 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); | |
2537 | return -EFAULT; | |
2538 | } | |
2539 | ||
2540 | pages = obj->ops->get_pages(obj); | |
2541 | if (unlikely(IS_ERR(pages))) | |
2542 | return PTR_ERR(pages); | |
2543 | ||
2544 | __i915_gem_object_set_pages(obj, pages); | |
2545 | return 0; | |
673a394b EA |
2546 | } |
2547 | ||
37e680a1 | 2548 | /* Ensure that the associated pages are gathered from the backing storage |
1233e2db | 2549 | * and pinned into our object. i915_gem_object_pin_pages() may be called |
37e680a1 | 2550 | * multiple times before they are released by a single call to |
1233e2db | 2551 | * i915_gem_object_unpin_pages() - once the pages are no longer referenced |
37e680a1 CW |
2552 | * either as a result of memory pressure (reaping pages under the shrinker) |
2553 | * or as the object is itself released. | |
2554 | */ | |
a4f5ea64 | 2555 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
37e680a1 | 2556 | { |
03ac84f1 | 2557 | int err; |
37e680a1 | 2558 | |
1233e2db CW |
2559 | err = mutex_lock_interruptible(&obj->mm.lock); |
2560 | if (err) | |
2561 | return err; | |
4c7d62c6 | 2562 | |
4e5462ee | 2563 | if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) { |
2c3a3f44 CW |
2564 | err = ____i915_gem_object_get_pages(obj); |
2565 | if (err) | |
2566 | goto unlock; | |
37e680a1 | 2567 | |
2c3a3f44 CW |
2568 | smp_mb__before_atomic(); |
2569 | } | |
2570 | atomic_inc(&obj->mm.pages_pin_count); | |
ee286370 | 2571 | |
1233e2db CW |
2572 | unlock: |
2573 | mutex_unlock(&obj->mm.lock); | |
03ac84f1 | 2574 | return err; |
673a394b EA |
2575 | } |
2576 | ||
dd6034c6 | 2577 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
d31d7cb1 CW |
2578 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, |
2579 | enum i915_map_type type) | |
dd6034c6 DG |
2580 | { |
2581 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
a4f5ea64 | 2582 | struct sg_table *sgt = obj->mm.pages; |
85d1225e DG |
2583 | struct sgt_iter sgt_iter; |
2584 | struct page *page; | |
b338fa47 DG |
2585 | struct page *stack_pages[32]; |
2586 | struct page **pages = stack_pages; | |
dd6034c6 | 2587 | unsigned long i = 0; |
d31d7cb1 | 2588 | pgprot_t pgprot; |
dd6034c6 DG |
2589 | void *addr; |
2590 | ||
2591 | /* A single page can always be kmapped */ | |
d31d7cb1 | 2592 | if (n_pages == 1 && type == I915_MAP_WB) |
dd6034c6 DG |
2593 | return kmap(sg_page(sgt->sgl)); |
2594 | ||
b338fa47 DG |
2595 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2596 | /* Too big for stack -- allocate temporary array instead */ | |
2098105e | 2597 | pages = kvmalloc_array(n_pages, sizeof(*pages), GFP_TEMPORARY); |
b338fa47 DG |
2598 | if (!pages) |
2599 | return NULL; | |
2600 | } | |
dd6034c6 | 2601 | |
85d1225e DG |
2602 | for_each_sgt_page(page, sgt_iter, sgt) |
2603 | pages[i++] = page; | |
dd6034c6 DG |
2604 | |
2605 | /* Check that we have the expected number of pages */ | |
2606 | GEM_BUG_ON(i != n_pages); | |
2607 | ||
d31d7cb1 CW |
2608 | switch (type) { |
2609 | case I915_MAP_WB: | |
2610 | pgprot = PAGE_KERNEL; | |
2611 | break; | |
2612 | case I915_MAP_WC: | |
2613 | pgprot = pgprot_writecombine(PAGE_KERNEL_IO); | |
2614 | break; | |
2615 | } | |
2616 | addr = vmap(pages, n_pages, 0, pgprot); | |
dd6034c6 | 2617 | |
b338fa47 | 2618 | if (pages != stack_pages) |
2098105e | 2619 | kvfree(pages); |
dd6034c6 DG |
2620 | |
2621 | return addr; | |
2622 | } | |
2623 | ||
2624 | /* get, pin, and map the pages of the object into kernel space */ | |
d31d7cb1 CW |
2625 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
2626 | enum i915_map_type type) | |
0a798eb9 | 2627 | { |
d31d7cb1 CW |
2628 | enum i915_map_type has_type; |
2629 | bool pinned; | |
2630 | void *ptr; | |
0a798eb9 CW |
2631 | int ret; |
2632 | ||
d31d7cb1 | 2633 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); |
0a798eb9 | 2634 | |
1233e2db | 2635 | ret = mutex_lock_interruptible(&obj->mm.lock); |
0a798eb9 CW |
2636 | if (ret) |
2637 | return ERR_PTR(ret); | |
2638 | ||
1233e2db CW |
2639 | pinned = true; |
2640 | if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) { | |
4e5462ee | 2641 | if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) { |
2c3a3f44 CW |
2642 | ret = ____i915_gem_object_get_pages(obj); |
2643 | if (ret) | |
2644 | goto err_unlock; | |
1233e2db | 2645 | |
2c3a3f44 CW |
2646 | smp_mb__before_atomic(); |
2647 | } | |
2648 | atomic_inc(&obj->mm.pages_pin_count); | |
1233e2db CW |
2649 | pinned = false; |
2650 | } | |
2651 | GEM_BUG_ON(!obj->mm.pages); | |
0a798eb9 | 2652 | |
0ce81788 | 2653 | ptr = page_unpack_bits(obj->mm.mapping, &has_type); |
d31d7cb1 CW |
2654 | if (ptr && has_type != type) { |
2655 | if (pinned) { | |
2656 | ret = -EBUSY; | |
1233e2db | 2657 | goto err_unpin; |
0a798eb9 | 2658 | } |
d31d7cb1 CW |
2659 | |
2660 | if (is_vmalloc_addr(ptr)) | |
2661 | vunmap(ptr); | |
2662 | else | |
2663 | kunmap(kmap_to_page(ptr)); | |
2664 | ||
a4f5ea64 | 2665 | ptr = obj->mm.mapping = NULL; |
0a798eb9 CW |
2666 | } |
2667 | ||
d31d7cb1 CW |
2668 | if (!ptr) { |
2669 | ptr = i915_gem_object_map(obj, type); | |
2670 | if (!ptr) { | |
2671 | ret = -ENOMEM; | |
1233e2db | 2672 | goto err_unpin; |
d31d7cb1 CW |
2673 | } |
2674 | ||
0ce81788 | 2675 | obj->mm.mapping = page_pack_bits(ptr, type); |
d31d7cb1 CW |
2676 | } |
2677 | ||
1233e2db CW |
2678 | out_unlock: |
2679 | mutex_unlock(&obj->mm.lock); | |
d31d7cb1 CW |
2680 | return ptr; |
2681 | ||
1233e2db CW |
2682 | err_unpin: |
2683 | atomic_dec(&obj->mm.pages_pin_count); | |
2684 | err_unlock: | |
2685 | ptr = ERR_PTR(ret); | |
2686 | goto out_unlock; | |
0a798eb9 CW |
2687 | } |
2688 | ||
7c55e2c5 CW |
2689 | static int |
2690 | i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj, | |
2691 | const struct drm_i915_gem_pwrite *arg) | |
2692 | { | |
2693 | struct address_space *mapping = obj->base.filp->f_mapping; | |
2694 | char __user *user_data = u64_to_user_ptr(arg->data_ptr); | |
2695 | u64 remain, offset; | |
2696 | unsigned int pg; | |
2697 | ||
2698 | /* Before we instantiate/pin the backing store for our use, we | |
2699 | * can prepopulate the shmemfs filp efficiently using a write into | |
2700 | * the pagecache. We avoid the penalty of instantiating all the | |
2701 | * pages, important if the user is just writing to a few and never | |
2702 | * uses the object on the GPU, and using a direct write into shmemfs | |
2703 | * allows it to avoid the cost of retrieving a page (either swapin | |
2704 | * or clearing-before-use) before it is overwritten. | |
2705 | */ | |
2706 | if (READ_ONCE(obj->mm.pages)) | |
2707 | return -ENODEV; | |
2708 | ||
2709 | /* Before the pages are instantiated the object is treated as being | |
2710 | * in the CPU domain. The pages will be clflushed as required before | |
2711 | * use, and we can freely write into the pages directly. If userspace | |
2712 | * races pwrite with any other operation; corruption will ensue - | |
2713 | * that is userspace's prerogative! | |
2714 | */ | |
2715 | ||
2716 | remain = arg->size; | |
2717 | offset = arg->offset; | |
2718 | pg = offset_in_page(offset); | |
2719 | ||
2720 | do { | |
2721 | unsigned int len, unwritten; | |
2722 | struct page *page; | |
2723 | void *data, *vaddr; | |
2724 | int err; | |
2725 | ||
2726 | len = PAGE_SIZE - pg; | |
2727 | if (len > remain) | |
2728 | len = remain; | |
2729 | ||
2730 | err = pagecache_write_begin(obj->base.filp, mapping, | |
2731 | offset, len, 0, | |
2732 | &page, &data); | |
2733 | if (err < 0) | |
2734 | return err; | |
2735 | ||
2736 | vaddr = kmap(page); | |
2737 | unwritten = copy_from_user(vaddr + pg, user_data, len); | |
2738 | kunmap(page); | |
2739 | ||
2740 | err = pagecache_write_end(obj->base.filp, mapping, | |
2741 | offset, len, len - unwritten, | |
2742 | page, data); | |
2743 | if (err < 0) | |
2744 | return err; | |
2745 | ||
2746 | if (unwritten) | |
2747 | return -EFAULT; | |
2748 | ||
2749 | remain -= len; | |
2750 | user_data += len; | |
2751 | offset += len; | |
2752 | pg = 0; | |
2753 | } while (remain); | |
2754 | ||
2755 | return 0; | |
2756 | } | |
2757 | ||
6095868a | 2758 | static bool ban_context(const struct i915_gem_context *ctx) |
be62acb4 | 2759 | { |
6095868a CW |
2760 | return (i915_gem_context_is_bannable(ctx) && |
2761 | ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD); | |
be62acb4 MK |
2762 | } |
2763 | ||
e5e1fc47 | 2764 | static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx) |
aa60c664 | 2765 | { |
bc1d53c6 | 2766 | ctx->guilty_count++; |
6095868a CW |
2767 | ctx->ban_score += CONTEXT_SCORE_GUILTY; |
2768 | if (ban_context(ctx)) | |
2769 | i915_gem_context_set_banned(ctx); | |
b083a087 MK |
2770 | |
2771 | DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n", | |
bc1d53c6 | 2772 | ctx->name, ctx->ban_score, |
6095868a | 2773 | yesno(i915_gem_context_is_banned(ctx))); |
b083a087 | 2774 | |
6095868a | 2775 | if (!i915_gem_context_is_banned(ctx) || IS_ERR_OR_NULL(ctx->file_priv)) |
b083a087 MK |
2776 | return; |
2777 | ||
d9e9da64 CW |
2778 | ctx->file_priv->context_bans++; |
2779 | DRM_DEBUG_DRIVER("client %s has had %d context banned\n", | |
2780 | ctx->name, ctx->file_priv->context_bans); | |
e5e1fc47 MK |
2781 | } |
2782 | ||
2783 | static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx) | |
2784 | { | |
bc1d53c6 | 2785 | ctx->active_count++; |
aa60c664 MK |
2786 | } |
2787 | ||
8d9fc7fd | 2788 | struct drm_i915_gem_request * |
0bc40be8 | 2789 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2790 | { |
754c9fd5 CW |
2791 | struct drm_i915_gem_request *request, *active = NULL; |
2792 | unsigned long flags; | |
4db080f9 | 2793 | |
f69a02c9 CW |
2794 | /* We are called by the error capture and reset at a random |
2795 | * point in time. In particular, note that neither is crucially | |
2796 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2797 | * assume that no more writes can happen (we waited long enough for | |
2798 | * all writes that were in transaction to be flushed) - adding an | |
2799 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2800 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2801 | */ | |
754c9fd5 | 2802 | spin_lock_irqsave(&engine->timeline->lock, flags); |
73cb9701 | 2803 | list_for_each_entry(request, &engine->timeline->requests, link) { |
754c9fd5 CW |
2804 | if (__i915_gem_request_completed(request, |
2805 | request->global_seqno)) | |
4db080f9 | 2806 | continue; |
aa60c664 | 2807 | |
36193acd | 2808 | GEM_BUG_ON(request->engine != engine); |
c00122f3 CW |
2809 | GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, |
2810 | &request->fence.flags)); | |
754c9fd5 CW |
2811 | |
2812 | active = request; | |
2813 | break; | |
4db080f9 | 2814 | } |
754c9fd5 | 2815 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
b6b0fac0 | 2816 | |
754c9fd5 | 2817 | return active; |
b6b0fac0 MK |
2818 | } |
2819 | ||
bf2f0436 MK |
2820 | static bool engine_stalled(struct intel_engine_cs *engine) |
2821 | { | |
2822 | if (!engine->hangcheck.stalled) | |
2823 | return false; | |
2824 | ||
2825 | /* Check for possible seqno movement after hang declaration */ | |
2826 | if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) { | |
2827 | DRM_DEBUG_DRIVER("%s pardoned\n", engine->name); | |
2828 | return false; | |
2829 | } | |
2830 | ||
2831 | return true; | |
2832 | } | |
2833 | ||
0e178aef | 2834 | int i915_gem_reset_prepare(struct drm_i915_private *dev_priv) |
4c965543 CW |
2835 | { |
2836 | struct intel_engine_cs *engine; | |
2837 | enum intel_engine_id id; | |
0e178aef | 2838 | int err = 0; |
4c965543 CW |
2839 | |
2840 | /* Ensure irq handler finishes, and not run again. */ | |
0e178aef CW |
2841 | for_each_engine(engine, dev_priv, id) { |
2842 | struct drm_i915_gem_request *request; | |
2843 | ||
fe3288b5 CW |
2844 | /* Prevent the signaler thread from updating the request |
2845 | * state (by calling dma_fence_signal) as we are processing | |
2846 | * the reset. The write from the GPU of the seqno is | |
2847 | * asynchronous and the signaler thread may see a different | |
2848 | * value to us and declare the request complete, even though | |
2849 | * the reset routine have picked that request as the active | |
2850 | * (incomplete) request. This conflict is not handled | |
2851 | * gracefully! | |
2852 | */ | |
2853 | kthread_park(engine->breadcrumbs.signaler); | |
2854 | ||
1f7b847d CW |
2855 | /* Prevent request submission to the hardware until we have |
2856 | * completed the reset in i915_gem_reset_finish(). If a request | |
2857 | * is completed by one engine, it may then queue a request | |
2858 | * to a second via its engine->irq_tasklet *just* as we are | |
2859 | * calling engine->init_hw() and also writing the ELSP. | |
2860 | * Turning off the engine->irq_tasklet until the reset is over | |
2861 | * prevents the race. | |
2862 | */ | |
4c965543 | 2863 | tasklet_kill(&engine->irq_tasklet); |
1d309634 | 2864 | tasklet_disable(&engine->irq_tasklet); |
4c965543 | 2865 | |
8c12d121 CW |
2866 | if (engine->irq_seqno_barrier) |
2867 | engine->irq_seqno_barrier(engine); | |
2868 | ||
0e178aef CW |
2869 | if (engine_stalled(engine)) { |
2870 | request = i915_gem_find_active_request(engine); | |
2871 | if (request && request->fence.error == -EIO) | |
2872 | err = -EIO; /* Previous reset failed! */ | |
2873 | } | |
2874 | } | |
2875 | ||
4c965543 | 2876 | i915_gem_revoke_fences(dev_priv); |
0e178aef CW |
2877 | |
2878 | return err; | |
4c965543 CW |
2879 | } |
2880 | ||
36193acd | 2881 | static void skip_request(struct drm_i915_gem_request *request) |
821ed7df CW |
2882 | { |
2883 | void *vaddr = request->ring->vaddr; | |
2884 | u32 head; | |
2885 | ||
2886 | /* As this request likely depends on state from the lost | |
2887 | * context, clear out all the user operations leaving the | |
2888 | * breadcrumb at the end (so we get the fence notifications). | |
2889 | */ | |
2890 | head = request->head; | |
2891 | if (request->postfix < head) { | |
2892 | memset(vaddr + head, 0, request->ring->size - head); | |
2893 | head = 0; | |
2894 | } | |
2895 | memset(vaddr + head, 0, request->postfix - head); | |
c0d5f32c CW |
2896 | |
2897 | dma_fence_set_error(&request->fence, -EIO); | |
821ed7df CW |
2898 | } |
2899 | ||
36193acd MK |
2900 | static void engine_skip_context(struct drm_i915_gem_request *request) |
2901 | { | |
2902 | struct intel_engine_cs *engine = request->engine; | |
2903 | struct i915_gem_context *hung_ctx = request->ctx; | |
2904 | struct intel_timeline *timeline; | |
2905 | unsigned long flags; | |
2906 | ||
2907 | timeline = i915_gem_context_lookup_timeline(hung_ctx, engine); | |
2908 | ||
2909 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
2910 | spin_lock(&timeline->lock); | |
2911 | ||
2912 | list_for_each_entry_continue(request, &engine->timeline->requests, link) | |
2913 | if (request->ctx == hung_ctx) | |
2914 | skip_request(request); | |
2915 | ||
2916 | list_for_each_entry(request, &timeline->requests, link) | |
2917 | skip_request(request); | |
2918 | ||
2919 | spin_unlock(&timeline->lock); | |
2920 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
2921 | } | |
2922 | ||
61da5362 MK |
2923 | /* Returns true if the request was guilty of hang */ |
2924 | static bool i915_gem_reset_request(struct drm_i915_gem_request *request) | |
2925 | { | |
2926 | /* Read once and return the resolution */ | |
2927 | const bool guilty = engine_stalled(request->engine); | |
2928 | ||
71895a08 MK |
2929 | /* The guilty request will get skipped on a hung engine. |
2930 | * | |
2931 | * Users of client default contexts do not rely on logical | |
2932 | * state preserved between batches so it is safe to execute | |
2933 | * queued requests following the hang. Non default contexts | |
2934 | * rely on preserved state, so skipping a batch loses the | |
2935 | * evolution of the state and it needs to be considered corrupted. | |
2936 | * Executing more queued batches on top of corrupted state is | |
2937 | * risky. But we take the risk by trying to advance through | |
2938 | * the queued requests in order to make the client behaviour | |
2939 | * more predictable around resets, by not throwing away random | |
2940 | * amount of batches it has prepared for execution. Sophisticated | |
2941 | * clients can use gem_reset_stats_ioctl and dma fence status | |
2942 | * (exported via sync_file info ioctl on explicit fences) to observe | |
2943 | * when it loses the context state and should rebuild accordingly. | |
2944 | * | |
2945 | * The context ban, and ultimately the client ban, mechanism are safety | |
2946 | * valves if client submission ends up resulting in nothing more than | |
2947 | * subsequent hangs. | |
2948 | */ | |
2949 | ||
61da5362 MK |
2950 | if (guilty) { |
2951 | i915_gem_context_mark_guilty(request->ctx); | |
2952 | skip_request(request); | |
2953 | } else { | |
2954 | i915_gem_context_mark_innocent(request->ctx); | |
2955 | dma_fence_set_error(&request->fence, -EAGAIN); | |
2956 | } | |
2957 | ||
2958 | return guilty; | |
2959 | } | |
2960 | ||
821ed7df | 2961 | static void i915_gem_reset_engine(struct intel_engine_cs *engine) |
b6b0fac0 MK |
2962 | { |
2963 | struct drm_i915_gem_request *request; | |
b6b0fac0 | 2964 | |
0bc40be8 | 2965 | request = i915_gem_find_active_request(engine); |
c0dcb203 CW |
2966 | if (request && i915_gem_reset_request(request)) { |
2967 | DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", | |
2968 | engine->name, request->global_seqno); | |
821ed7df | 2969 | |
c0dcb203 CW |
2970 | /* If this context is now banned, skip all pending requests. */ |
2971 | if (i915_gem_context_is_banned(request->ctx)) | |
2972 | engine_skip_context(request); | |
2973 | } | |
821ed7df CW |
2974 | |
2975 | /* Setup the CS to resume from the breadcrumb of the hung request */ | |
2976 | engine->reset_hw(engine, request); | |
4db080f9 | 2977 | } |
aa60c664 | 2978 | |
d8027093 | 2979 | void i915_gem_reset(struct drm_i915_private *dev_priv) |
4db080f9 | 2980 | { |
821ed7df | 2981 | struct intel_engine_cs *engine; |
3b3f1650 | 2982 | enum intel_engine_id id; |
608c1a52 | 2983 | |
4c7d62c6 CW |
2984 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2985 | ||
821ed7df CW |
2986 | i915_gem_retire_requests(dev_priv); |
2987 | ||
2ae55738 CW |
2988 | for_each_engine(engine, dev_priv, id) { |
2989 | struct i915_gem_context *ctx; | |
2990 | ||
821ed7df | 2991 | i915_gem_reset_engine(engine); |
2ae55738 CW |
2992 | ctx = fetch_and_zero(&engine->last_retired_context); |
2993 | if (ctx) | |
2994 | engine->context_unpin(engine, ctx); | |
2995 | } | |
821ed7df | 2996 | |
4362f4f6 | 2997 | i915_gem_restore_fences(dev_priv); |
f2a91d1a CW |
2998 | |
2999 | if (dev_priv->gt.awake) { | |
3000 | intel_sanitize_gt_powersave(dev_priv); | |
3001 | intel_enable_gt_powersave(dev_priv); | |
3002 | if (INTEL_GEN(dev_priv) >= 6) | |
3003 | gen6_rps_busy(dev_priv); | |
3004 | } | |
821ed7df CW |
3005 | } |
3006 | ||
d8027093 CW |
3007 | void i915_gem_reset_finish(struct drm_i915_private *dev_priv) |
3008 | { | |
1f7b847d CW |
3009 | struct intel_engine_cs *engine; |
3010 | enum intel_engine_id id; | |
3011 | ||
d8027093 | 3012 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
1f7b847d | 3013 | |
fe3288b5 | 3014 | for_each_engine(engine, dev_priv, id) { |
1f7b847d | 3015 | tasklet_enable(&engine->irq_tasklet); |
fe3288b5 CW |
3016 | kthread_unpark(engine->breadcrumbs.signaler); |
3017 | } | |
d8027093 CW |
3018 | } |
3019 | ||
821ed7df CW |
3020 | static void nop_submit_request(struct drm_i915_gem_request *request) |
3021 | { | |
3cd9442f | 3022 | dma_fence_set_error(&request->fence, -EIO); |
3dcf93f7 CW |
3023 | i915_gem_request_submit(request); |
3024 | intel_engine_init_global_seqno(request->engine, request->global_seqno); | |
821ed7df CW |
3025 | } |
3026 | ||
2a20d6f8 | 3027 | static void engine_set_wedged(struct intel_engine_cs *engine) |
821ed7df | 3028 | { |
3cd9442f CW |
3029 | struct drm_i915_gem_request *request; |
3030 | unsigned long flags; | |
3031 | ||
20e4933c CW |
3032 | /* We need to be sure that no thread is running the old callback as |
3033 | * we install the nop handler (otherwise we would submit a request | |
3034 | * to hardware that will never complete). In order to prevent this | |
3035 | * race, we wait until the machine is idle before making the swap | |
3036 | * (using stop_machine()). | |
3037 | */ | |
821ed7df | 3038 | engine->submit_request = nop_submit_request; |
70c2a24d | 3039 | |
3cd9442f CW |
3040 | /* Mark all executing requests as skipped */ |
3041 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
3042 | list_for_each_entry(request, &engine->timeline->requests, link) | |
3043 | dma_fence_set_error(&request->fence, -EIO); | |
3044 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
3045 | ||
c4b0930b CW |
3046 | /* Mark all pending requests as complete so that any concurrent |
3047 | * (lockless) lookup doesn't try and wait upon the request as we | |
3048 | * reset it. | |
3049 | */ | |
73cb9701 | 3050 | intel_engine_init_global_seqno(engine, |
cb399eab | 3051 | intel_engine_last_submit(engine)); |
c4b0930b | 3052 | |
dcb4c12a OM |
3053 | /* |
3054 | * Clear the execlists queue up before freeing the requests, as those | |
3055 | * are the ones that keep the context and ringbuffer backing objects | |
3056 | * pinned in place. | |
3057 | */ | |
dcb4c12a | 3058 | |
7de1691a | 3059 | if (i915.enable_execlists) { |
77f0d0e9 | 3060 | struct execlist_port *port = engine->execlist_port; |
663f71e7 | 3061 | unsigned long flags; |
77f0d0e9 | 3062 | unsigned int n; |
663f71e7 CW |
3063 | |
3064 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
3065 | ||
77f0d0e9 CW |
3066 | for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) |
3067 | i915_gem_request_put(port_request(&port[n])); | |
70c2a24d | 3068 | memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); |
20311bd3 CW |
3069 | engine->execlist_queue = RB_ROOT; |
3070 | engine->execlist_first = NULL; | |
663f71e7 CW |
3071 | |
3072 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
dcb4c12a | 3073 | } |
673a394b EA |
3074 | } |
3075 | ||
20e4933c | 3076 | static int __i915_gem_set_wedged_BKL(void *data) |
673a394b | 3077 | { |
20e4933c | 3078 | struct drm_i915_private *i915 = data; |
e2f80391 | 3079 | struct intel_engine_cs *engine; |
3b3f1650 | 3080 | enum intel_engine_id id; |
673a394b | 3081 | |
20e4933c | 3082 | for_each_engine(engine, i915, id) |
2a20d6f8 | 3083 | engine_set_wedged(engine); |
20e4933c CW |
3084 | |
3085 | return 0; | |
3086 | } | |
3087 | ||
3088 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv) | |
3089 | { | |
821ed7df CW |
3090 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
3091 | set_bit(I915_WEDGED, &dev_priv->gpu_error.flags); | |
4db080f9 | 3092 | |
2c170af7 CW |
3093 | /* Retire completed requests first so the list of inflight/incomplete |
3094 | * requests is accurate and we don't try and mark successful requests | |
3095 | * as in error during __i915_gem_set_wedged_BKL(). | |
3096 | */ | |
3097 | i915_gem_retire_requests(dev_priv); | |
3098 | ||
20e4933c | 3099 | stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL); |
dfaae392 | 3100 | |
20e4933c | 3101 | i915_gem_context_lost(dev_priv); |
20e4933c CW |
3102 | |
3103 | mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); | |
673a394b EA |
3104 | } |
3105 | ||
2e8f9d32 CW |
3106 | bool i915_gem_unset_wedged(struct drm_i915_private *i915) |
3107 | { | |
3108 | struct i915_gem_timeline *tl; | |
3109 | int i; | |
3110 | ||
3111 | lockdep_assert_held(&i915->drm.struct_mutex); | |
3112 | if (!test_bit(I915_WEDGED, &i915->gpu_error.flags)) | |
3113 | return true; | |
3114 | ||
3115 | /* Before unwedging, make sure that all pending operations | |
3116 | * are flushed and errored out - we may have requests waiting upon | |
3117 | * third party fences. We marked all inflight requests as EIO, and | |
3118 | * every execbuf since returned EIO, for consistency we want all | |
3119 | * the currently pending requests to also be marked as EIO, which | |
3120 | * is done inside our nop_submit_request - and so we must wait. | |
3121 | * | |
3122 | * No more can be submitted until we reset the wedged bit. | |
3123 | */ | |
3124 | list_for_each_entry(tl, &i915->gt.timelines, link) { | |
3125 | for (i = 0; i < ARRAY_SIZE(tl->engine); i++) { | |
3126 | struct drm_i915_gem_request *rq; | |
3127 | ||
3128 | rq = i915_gem_active_peek(&tl->engine[i].last_request, | |
3129 | &i915->drm.struct_mutex); | |
3130 | if (!rq) | |
3131 | continue; | |
3132 | ||
3133 | /* We can't use our normal waiter as we want to | |
3134 | * avoid recursively trying to handle the current | |
3135 | * reset. The basic dma_fence_default_wait() installs | |
3136 | * a callback for dma_fence_signal(), which is | |
3137 | * triggered by our nop handler (indirectly, the | |
3138 | * callback enables the signaler thread which is | |
3139 | * woken by the nop_submit_request() advancing the seqno | |
3140 | * and when the seqno passes the fence, the signaler | |
3141 | * then signals the fence waking us up). | |
3142 | */ | |
3143 | if (dma_fence_default_wait(&rq->fence, true, | |
3144 | MAX_SCHEDULE_TIMEOUT) < 0) | |
3145 | return false; | |
3146 | } | |
3147 | } | |
3148 | ||
3149 | /* Undo nop_submit_request. We prevent all new i915 requests from | |
3150 | * being queued (by disallowing execbuf whilst wedged) so having | |
3151 | * waited for all active requests above, we know the system is idle | |
3152 | * and do not have to worry about a thread being inside | |
3153 | * engine->submit_request() as we swap over. So unlike installing | |
3154 | * the nop_submit_request on reset, we can do this from normal | |
3155 | * context and do not require stop_machine(). | |
3156 | */ | |
3157 | intel_engines_reset_default_submission(i915); | |
3158 | ||
3159 | smp_mb__before_atomic(); /* complete takeover before enabling execbuf */ | |
3160 | clear_bit(I915_WEDGED, &i915->gpu_error.flags); | |
3161 | ||
3162 | return true; | |
3163 | } | |
3164 | ||
75ef9da2 | 3165 | static void |
673a394b EA |
3166 | i915_gem_retire_work_handler(struct work_struct *work) |
3167 | { | |
b29c19b6 | 3168 | struct drm_i915_private *dev_priv = |
67d97da3 | 3169 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 3170 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 3171 | |
891b48cf | 3172 | /* Come back later if the device is busy... */ |
b29c19b6 | 3173 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 3174 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 3175 | mutex_unlock(&dev->struct_mutex); |
673a394b | 3176 | } |
67d97da3 CW |
3177 | |
3178 | /* Keep the retire handler running until we are finally idle. | |
3179 | * We do not need to do this test under locking as in the worst-case | |
3180 | * we queue the retire worker once too often. | |
3181 | */ | |
c9615613 CW |
3182 | if (READ_ONCE(dev_priv->gt.awake)) { |
3183 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
3184 | queue_delayed_work(dev_priv->wq, |
3185 | &dev_priv->gt.retire_work, | |
bcb45086 | 3186 | round_jiffies_up_relative(HZ)); |
c9615613 | 3187 | } |
b29c19b6 | 3188 | } |
0a58705b | 3189 | |
b29c19b6 CW |
3190 | static void |
3191 | i915_gem_idle_work_handler(struct work_struct *work) | |
3192 | { | |
3193 | struct drm_i915_private *dev_priv = | |
67d97da3 | 3194 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 3195 | struct drm_device *dev = &dev_priv->drm; |
67d97da3 CW |
3196 | bool rearm_hangcheck; |
3197 | ||
3198 | if (!READ_ONCE(dev_priv->gt.awake)) | |
3199 | return; | |
3200 | ||
0cb5670b ID |
3201 | /* |
3202 | * Wait for last execlists context complete, but bail out in case a | |
3203 | * new request is submitted. | |
3204 | */ | |
8490ae20 | 3205 | wait_for(intel_engines_are_idle(dev_priv), 10); |
28176ef4 | 3206 | if (READ_ONCE(dev_priv->gt.active_requests)) |
67d97da3 CW |
3207 | return; |
3208 | ||
3209 | rearm_hangcheck = | |
3210 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
3211 | ||
3212 | if (!mutex_trylock(&dev->struct_mutex)) { | |
3213 | /* Currently busy, come back later */ | |
3214 | mod_delayed_work(dev_priv->wq, | |
3215 | &dev_priv->gt.idle_work, | |
3216 | msecs_to_jiffies(50)); | |
3217 | goto out_rearm; | |
3218 | } | |
3219 | ||
93c97dc1 ID |
3220 | /* |
3221 | * New request retired after this work handler started, extend active | |
3222 | * period until next instance of the work. | |
3223 | */ | |
3224 | if (work_pending(work)) | |
3225 | goto out_unlock; | |
3226 | ||
28176ef4 | 3227 | if (dev_priv->gt.active_requests) |
67d97da3 | 3228 | goto out_unlock; |
b29c19b6 | 3229 | |
05425249 | 3230 | if (wait_for(intel_engines_are_idle(dev_priv), 10)) |
0cb5670b ID |
3231 | DRM_ERROR("Timeout waiting for engines to idle\n"); |
3232 | ||
6c067579 | 3233 | intel_engines_mark_idle(dev_priv); |
47979480 | 3234 | i915_gem_timelines_mark_idle(dev_priv); |
35c94185 | 3235 | |
67d97da3 CW |
3236 | GEM_BUG_ON(!dev_priv->gt.awake); |
3237 | dev_priv->gt.awake = false; | |
3238 | rearm_hangcheck = false; | |
30ecad77 | 3239 | |
67d97da3 CW |
3240 | if (INTEL_GEN(dev_priv) >= 6) |
3241 | gen6_rps_idle(dev_priv); | |
3242 | intel_runtime_pm_put(dev_priv); | |
3243 | out_unlock: | |
3244 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 3245 | |
67d97da3 CW |
3246 | out_rearm: |
3247 | if (rearm_hangcheck) { | |
3248 | GEM_BUG_ON(!dev_priv->gt.awake); | |
3249 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 3250 | } |
673a394b EA |
3251 | } |
3252 | ||
b1f788c6 CW |
3253 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
3254 | { | |
3255 | struct drm_i915_gem_object *obj = to_intel_bo(gem); | |
3256 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
3257 | struct i915_vma *vma, *vn; | |
3258 | ||
3259 | mutex_lock(&obj->base.dev->struct_mutex); | |
3260 | list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) | |
3261 | if (vma->vm->file == fpriv) | |
3262 | i915_vma_close(vma); | |
f8a7fde4 | 3263 | |
4ff4b44c CW |
3264 | vma = obj->vma_hashed; |
3265 | if (vma && vma->ctx->file_priv == fpriv) | |
3266 | i915_vma_unlink_ctx(vma); | |
3267 | ||
f8a7fde4 CW |
3268 | if (i915_gem_object_is_active(obj) && |
3269 | !i915_gem_object_has_active_reference(obj)) { | |
3270 | i915_gem_object_set_active_reference(obj); | |
3271 | i915_gem_object_get(obj); | |
3272 | } | |
b1f788c6 CW |
3273 | mutex_unlock(&obj->base.dev->struct_mutex); |
3274 | } | |
3275 | ||
e95433c7 CW |
3276 | static unsigned long to_wait_timeout(s64 timeout_ns) |
3277 | { | |
3278 | if (timeout_ns < 0) | |
3279 | return MAX_SCHEDULE_TIMEOUT; | |
3280 | ||
3281 | if (timeout_ns == 0) | |
3282 | return 0; | |
3283 | ||
3284 | return nsecs_to_jiffies_timeout(timeout_ns); | |
3285 | } | |
3286 | ||
23ba4fd0 BW |
3287 | /** |
3288 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
3289 | * @dev: drm device pointer |
3290 | * @data: ioctl data blob | |
3291 | * @file: drm file pointer | |
23ba4fd0 BW |
3292 | * |
3293 | * Returns 0 if successful, else an error is returned with the remaining time in | |
3294 | * the timeout parameter. | |
3295 | * -ETIME: object is still busy after timeout | |
3296 | * -ERESTARTSYS: signal interrupted the wait | |
3297 | * -ENONENT: object doesn't exist | |
3298 | * Also possible, but rare: | |
3299 | * -EAGAIN: GPU wedged | |
3300 | * -ENOMEM: damn | |
3301 | * -ENODEV: Internal IRQ fail | |
3302 | * -E?: The add request failed | |
3303 | * | |
3304 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
3305 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
3306 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
3307 | * without holding struct_mutex the object may become re-busied before this | |
3308 | * function completes. A similar but shorter * race condition exists in the busy | |
3309 | * ioctl | |
3310 | */ | |
3311 | int | |
3312 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
3313 | { | |
3314 | struct drm_i915_gem_wait *args = data; | |
3315 | struct drm_i915_gem_object *obj; | |
e95433c7 CW |
3316 | ktime_t start; |
3317 | long ret; | |
23ba4fd0 | 3318 | |
11b5d511 DV |
3319 | if (args->flags != 0) |
3320 | return -EINVAL; | |
3321 | ||
03ac0642 | 3322 | obj = i915_gem_object_lookup(file, args->bo_handle); |
033d549b | 3323 | if (!obj) |
23ba4fd0 | 3324 | return -ENOENT; |
23ba4fd0 | 3325 | |
e95433c7 CW |
3326 | start = ktime_get(); |
3327 | ||
3328 | ret = i915_gem_object_wait(obj, | |
3329 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL, | |
3330 | to_wait_timeout(args->timeout_ns), | |
3331 | to_rps_client(file)); | |
3332 | ||
3333 | if (args->timeout_ns > 0) { | |
3334 | args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start)); | |
3335 | if (args->timeout_ns < 0) | |
3336 | args->timeout_ns = 0; | |
c1d2061b CW |
3337 | |
3338 | /* | |
3339 | * Apparently ktime isn't accurate enough and occasionally has a | |
3340 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
3341 | * things up to make the test happy. We allow up to 1 jiffy. | |
3342 | * | |
3343 | * This is a regression from the timespec->ktime conversion. | |
3344 | */ | |
3345 | if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns)) | |
3346 | args->timeout_ns = 0; | |
b4716185 CW |
3347 | } |
3348 | ||
f0cd5182 | 3349 | i915_gem_object_put(obj); |
ff865885 | 3350 | return ret; |
23ba4fd0 BW |
3351 | } |
3352 | ||
73cb9701 | 3353 | static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) |
4df2faf4 | 3354 | { |
73cb9701 | 3355 | int ret, i; |
4df2faf4 | 3356 | |
73cb9701 CW |
3357 | for (i = 0; i < ARRAY_SIZE(tl->engine); i++) { |
3358 | ret = i915_gem_active_wait(&tl->engine[i].last_request, flags); | |
3359 | if (ret) | |
3360 | return ret; | |
3361 | } | |
62e63007 | 3362 | |
73cb9701 CW |
3363 | return 0; |
3364 | } | |
3365 | ||
25112b64 CW |
3366 | static int wait_for_engine(struct intel_engine_cs *engine, int timeout_ms) |
3367 | { | |
3368 | return wait_for(intel_engine_is_idle(engine), timeout_ms); | |
3369 | } | |
3370 | ||
3371 | static int wait_for_engines(struct drm_i915_private *i915) | |
3372 | { | |
3373 | struct intel_engine_cs *engine; | |
3374 | enum intel_engine_id id; | |
3375 | ||
3376 | for_each_engine(engine, i915, id) { | |
3377 | if (GEM_WARN_ON(wait_for_engine(engine, 50))) { | |
3378 | i915_gem_set_wedged(i915); | |
3379 | return -EIO; | |
3380 | } | |
3381 | ||
3382 | GEM_BUG_ON(intel_engine_get_seqno(engine) != | |
3383 | intel_engine_last_submit(engine)); | |
3384 | } | |
3385 | ||
3386 | return 0; | |
3387 | } | |
3388 | ||
73cb9701 CW |
3389 | int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags) |
3390 | { | |
73cb9701 CW |
3391 | int ret; |
3392 | ||
863e9fde CW |
3393 | /* If the device is asleep, we have no requests outstanding */ |
3394 | if (!READ_ONCE(i915->gt.awake)) | |
3395 | return 0; | |
3396 | ||
9caa34aa CW |
3397 | if (flags & I915_WAIT_LOCKED) { |
3398 | struct i915_gem_timeline *tl; | |
3399 | ||
3400 | lockdep_assert_held(&i915->drm.struct_mutex); | |
3401 | ||
3402 | list_for_each_entry(tl, &i915->gt.timelines, link) { | |
3403 | ret = wait_for_timeline(tl, flags); | |
3404 | if (ret) | |
3405 | return ret; | |
3406 | } | |
72022a70 CW |
3407 | |
3408 | i915_gem_retire_requests(i915); | |
3409 | GEM_BUG_ON(i915->gt.active_requests); | |
25112b64 CW |
3410 | |
3411 | ret = wait_for_engines(i915); | |
9caa34aa CW |
3412 | } else { |
3413 | ret = wait_for_timeline(&i915->gt.global_timeline, flags); | |
1ec14ad3 | 3414 | } |
4df2faf4 | 3415 | |
25112b64 | 3416 | return ret; |
4df2faf4 DV |
3417 | } |
3418 | ||
5a97bcc6 CW |
3419 | static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj) |
3420 | { | |
e27ab73d CW |
3421 | /* |
3422 | * We manually flush the CPU domain so that we can override and | |
3423 | * force the flush for the display, and perform it asyncrhonously. | |
3424 | */ | |
3425 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); | |
3426 | if (obj->cache_dirty) | |
3427 | i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE); | |
5a97bcc6 CW |
3428 | obj->base.write_domain = 0; |
3429 | } | |
3430 | ||
3431 | void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj) | |
3432 | { | |
3433 | if (!READ_ONCE(obj->pin_display)) | |
3434 | return; | |
3435 | ||
3436 | mutex_lock(&obj->base.dev->struct_mutex); | |
3437 | __i915_gem_object_flush_for_display(obj); | |
3438 | mutex_unlock(&obj->base.dev->struct_mutex); | |
3439 | } | |
3440 | ||
e22d8e3c CW |
3441 | /** |
3442 | * Moves a single object to the WC read, and possibly write domain. | |
3443 | * @obj: object to act on | |
3444 | * @write: ask for write access or read only | |
3445 | * | |
3446 | * This function returns when the move is complete, including waiting on | |
3447 | * flushes to occur. | |
3448 | */ | |
3449 | int | |
3450 | i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write) | |
3451 | { | |
3452 | int ret; | |
3453 | ||
3454 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
3455 | ||
3456 | ret = i915_gem_object_wait(obj, | |
3457 | I915_WAIT_INTERRUPTIBLE | | |
3458 | I915_WAIT_LOCKED | | |
3459 | (write ? I915_WAIT_ALL : 0), | |
3460 | MAX_SCHEDULE_TIMEOUT, | |
3461 | NULL); | |
3462 | if (ret) | |
3463 | return ret; | |
3464 | ||
3465 | if (obj->base.write_domain == I915_GEM_DOMAIN_WC) | |
3466 | return 0; | |
3467 | ||
3468 | /* Flush and acquire obj->pages so that we are coherent through | |
3469 | * direct access in memory with previous cached writes through | |
3470 | * shmemfs and that our cache domain tracking remains valid. | |
3471 | * For example, if the obj->filp was moved to swap without us | |
3472 | * being notified and releasing the pages, we would mistakenly | |
3473 | * continue to assume that the obj remained out of the CPU cached | |
3474 | * domain. | |
3475 | */ | |
3476 | ret = i915_gem_object_pin_pages(obj); | |
3477 | if (ret) | |
3478 | return ret; | |
3479 | ||
3480 | flush_write_domain(obj, ~I915_GEM_DOMAIN_WC); | |
3481 | ||
3482 | /* Serialise direct access to this object with the barriers for | |
3483 | * coherent writes from the GPU, by effectively invalidating the | |
3484 | * WC domain upon first access. | |
3485 | */ | |
3486 | if ((obj->base.read_domains & I915_GEM_DOMAIN_WC) == 0) | |
3487 | mb(); | |
3488 | ||
3489 | /* It should now be out of any other write domains, and we can update | |
3490 | * the domain values for our changes. | |
3491 | */ | |
3492 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_WC) != 0); | |
3493 | obj->base.read_domains |= I915_GEM_DOMAIN_WC; | |
3494 | if (write) { | |
3495 | obj->base.read_domains = I915_GEM_DOMAIN_WC; | |
3496 | obj->base.write_domain = I915_GEM_DOMAIN_WC; | |
3497 | obj->mm.dirty = true; | |
3498 | } | |
3499 | ||
3500 | i915_gem_object_unpin_pages(obj); | |
3501 | return 0; | |
3502 | } | |
3503 | ||
2ef7eeaa EA |
3504 | /** |
3505 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3506 | * @obj: object to act on |
3507 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3508 | * |
3509 | * This function returns when the move is complete, including waiting on | |
3510 | * flushes to occur. | |
3511 | */ | |
79e53945 | 3512 | int |
2021746e | 3513 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3514 | { |
e47c68e9 | 3515 | int ret; |
2ef7eeaa | 3516 | |
e95433c7 | 3517 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3518 | |
e95433c7 CW |
3519 | ret = i915_gem_object_wait(obj, |
3520 | I915_WAIT_INTERRUPTIBLE | | |
3521 | I915_WAIT_LOCKED | | |
3522 | (write ? I915_WAIT_ALL : 0), | |
3523 | MAX_SCHEDULE_TIMEOUT, | |
3524 | NULL); | |
88241785 CW |
3525 | if (ret) |
3526 | return ret; | |
3527 | ||
c13d87ea CW |
3528 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3529 | return 0; | |
3530 | ||
43566ded CW |
3531 | /* Flush and acquire obj->pages so that we are coherent through |
3532 | * direct access in memory with previous cached writes through | |
3533 | * shmemfs and that our cache domain tracking remains valid. | |
3534 | * For example, if the obj->filp was moved to swap without us | |
3535 | * being notified and releasing the pages, we would mistakenly | |
3536 | * continue to assume that the obj remained out of the CPU cached | |
3537 | * domain. | |
3538 | */ | |
a4f5ea64 | 3539 | ret = i915_gem_object_pin_pages(obj); |
43566ded CW |
3540 | if (ret) |
3541 | return ret; | |
3542 | ||
ef74921b | 3543 | flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT); |
1c5d22f7 | 3544 | |
d0a57789 CW |
3545 | /* Serialise direct access to this object with the barriers for |
3546 | * coherent writes from the GPU, by effectively invalidating the | |
3547 | * GTT domain upon first access. | |
3548 | */ | |
3549 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3550 | mb(); | |
3551 | ||
e47c68e9 EA |
3552 | /* It should now be out of any other write domains, and we can update |
3553 | * the domain values for our changes. | |
3554 | */ | |
40e62d5d | 3555 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
05394f39 | 3556 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
e47c68e9 | 3557 | if (write) { |
05394f39 CW |
3558 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3559 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
a4f5ea64 | 3560 | obj->mm.dirty = true; |
2ef7eeaa EA |
3561 | } |
3562 | ||
a4f5ea64 | 3563 | i915_gem_object_unpin_pages(obj); |
e47c68e9 EA |
3564 | return 0; |
3565 | } | |
3566 | ||
ef55f92a CW |
3567 | /** |
3568 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3569 | * @obj: object to act on |
3570 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3571 | * |
3572 | * After this function returns, the object will be in the new cache-level | |
3573 | * across all GTT and the contents of the backing storage will be coherent, | |
3574 | * with respect to the new cache-level. In order to keep the backing storage | |
3575 | * coherent for all users, we only allow a single cache level to be set | |
3576 | * globally on the object and prevent it from being changed whilst the | |
3577 | * hardware is reading from the object. That is if the object is currently | |
3578 | * on the scanout it will be set to uncached (or equivalent display | |
3579 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3580 | * that all direct access to the scanout remains coherent. | |
3581 | */ | |
e4ffd173 CW |
3582 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3583 | enum i915_cache_level cache_level) | |
3584 | { | |
aa653a68 | 3585 | struct i915_vma *vma; |
a6a7cc4b | 3586 | int ret; |
e4ffd173 | 3587 | |
4c7d62c6 CW |
3588 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3589 | ||
e4ffd173 | 3590 | if (obj->cache_level == cache_level) |
a6a7cc4b | 3591 | return 0; |
e4ffd173 | 3592 | |
ef55f92a CW |
3593 | /* Inspect the list of currently bound VMA and unbind any that would |
3594 | * be invalid given the new cache-level. This is principally to | |
3595 | * catch the issue of the CS prefetch crossing page boundaries and | |
3596 | * reading an invalid PTE on older architectures. | |
3597 | */ | |
aa653a68 CW |
3598 | restart: |
3599 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3600 | if (!drm_mm_node_allocated(&vma->node)) |
3601 | continue; | |
3602 | ||
20dfbde4 | 3603 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3604 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3605 | return -EBUSY; | |
3606 | } | |
3607 | ||
aa653a68 CW |
3608 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3609 | continue; | |
3610 | ||
3611 | ret = i915_vma_unbind(vma); | |
3612 | if (ret) | |
3613 | return ret; | |
3614 | ||
3615 | /* As unbinding may affect other elements in the | |
3616 | * obj->vma_list (due to side-effects from retiring | |
3617 | * an active vma), play safe and restart the iterator. | |
3618 | */ | |
3619 | goto restart; | |
42d6ab48 CW |
3620 | } |
3621 | ||
ef55f92a CW |
3622 | /* We can reuse the existing drm_mm nodes but need to change the |
3623 | * cache-level on the PTE. We could simply unbind them all and | |
3624 | * rebind with the correct cache-level on next use. However since | |
3625 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3626 | * rewrite the PTE in the belief that doing so tramples upon less | |
3627 | * state and so involves less work. | |
3628 | */ | |
15717de2 | 3629 | if (obj->bind_count) { |
ef55f92a CW |
3630 | /* Before we change the PTE, the GPU must not be accessing it. |
3631 | * If we wait upon the object, we know that all the bound | |
3632 | * VMA are no longer active. | |
3633 | */ | |
e95433c7 CW |
3634 | ret = i915_gem_object_wait(obj, |
3635 | I915_WAIT_INTERRUPTIBLE | | |
3636 | I915_WAIT_LOCKED | | |
3637 | I915_WAIT_ALL, | |
3638 | MAX_SCHEDULE_TIMEOUT, | |
3639 | NULL); | |
e4ffd173 CW |
3640 | if (ret) |
3641 | return ret; | |
3642 | ||
0031fb96 TU |
3643 | if (!HAS_LLC(to_i915(obj->base.dev)) && |
3644 | cache_level != I915_CACHE_NONE) { | |
ef55f92a CW |
3645 | /* Access to snoopable pages through the GTT is |
3646 | * incoherent and on some machines causes a hard | |
3647 | * lockup. Relinquish the CPU mmaping to force | |
3648 | * userspace to refault in the pages and we can | |
3649 | * then double check if the GTT mapping is still | |
3650 | * valid for that pointer access. | |
3651 | */ | |
3652 | i915_gem_release_mmap(obj); | |
3653 | ||
3654 | /* As we no longer need a fence for GTT access, | |
3655 | * we can relinquish it now (and so prevent having | |
3656 | * to steal a fence from someone else on the next | |
3657 | * fence request). Note GPU activity would have | |
3658 | * dropped the fence as all snoopable access is | |
3659 | * supposed to be linear. | |
3660 | */ | |
49ef5294 CW |
3661 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3662 | ret = i915_vma_put_fence(vma); | |
3663 | if (ret) | |
3664 | return ret; | |
3665 | } | |
ef55f92a CW |
3666 | } else { |
3667 | /* We either have incoherent backing store and | |
3668 | * so no GTT access or the architecture is fully | |
3669 | * coherent. In such cases, existing GTT mmaps | |
3670 | * ignore the cache bit in the PTE and we can | |
3671 | * rewrite it without confusing the GPU or having | |
3672 | * to force userspace to fault back in its mmaps. | |
3673 | */ | |
e4ffd173 CW |
3674 | } |
3675 | ||
1c7f4bca | 3676 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3677 | if (!drm_mm_node_allocated(&vma->node)) |
3678 | continue; | |
3679 | ||
3680 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3681 | if (ret) | |
3682 | return ret; | |
3683 | } | |
e4ffd173 CW |
3684 | } |
3685 | ||
1c7f4bca | 3686 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3687 | vma->node.color = cache_level; |
3688 | obj->cache_level = cache_level; | |
7fc92e96 | 3689 | obj->cache_coherent = i915_gem_object_is_coherent(obj); |
e27ab73d | 3690 | obj->cache_dirty = true; /* Always invalidate stale cachelines */ |
2c22569b | 3691 | |
e4ffd173 CW |
3692 | return 0; |
3693 | } | |
3694 | ||
199adf40 BW |
3695 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3696 | struct drm_file *file) | |
e6994aee | 3697 | { |
199adf40 | 3698 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3699 | struct drm_i915_gem_object *obj; |
fbbd37b3 | 3700 | int err = 0; |
e6994aee | 3701 | |
fbbd37b3 CW |
3702 | rcu_read_lock(); |
3703 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
3704 | if (!obj) { | |
3705 | err = -ENOENT; | |
3706 | goto out; | |
3707 | } | |
e6994aee | 3708 | |
651d794f CW |
3709 | switch (obj->cache_level) { |
3710 | case I915_CACHE_LLC: | |
3711 | case I915_CACHE_L3_LLC: | |
3712 | args->caching = I915_CACHING_CACHED; | |
3713 | break; | |
3714 | ||
4257d3ba CW |
3715 | case I915_CACHE_WT: |
3716 | args->caching = I915_CACHING_DISPLAY; | |
3717 | break; | |
3718 | ||
651d794f CW |
3719 | default: |
3720 | args->caching = I915_CACHING_NONE; | |
3721 | break; | |
3722 | } | |
fbbd37b3 CW |
3723 | out: |
3724 | rcu_read_unlock(); | |
3725 | return err; | |
e6994aee CW |
3726 | } |
3727 | ||
199adf40 BW |
3728 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3729 | struct drm_file *file) | |
e6994aee | 3730 | { |
9c870d03 | 3731 | struct drm_i915_private *i915 = to_i915(dev); |
199adf40 | 3732 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3733 | struct drm_i915_gem_object *obj; |
3734 | enum i915_cache_level level; | |
d65415df | 3735 | int ret = 0; |
e6994aee | 3736 | |
199adf40 BW |
3737 | switch (args->caching) { |
3738 | case I915_CACHING_NONE: | |
e6994aee CW |
3739 | level = I915_CACHE_NONE; |
3740 | break; | |
199adf40 | 3741 | case I915_CACHING_CACHED: |
e5756c10 ID |
3742 | /* |
3743 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3744 | * snooped mapping may leave stale data in a corresponding CPU | |
3745 | * cacheline, whereas normally such cachelines would get | |
3746 | * invalidated. | |
3747 | */ | |
9c870d03 | 3748 | if (!HAS_LLC(i915) && !HAS_SNOOP(i915)) |
e5756c10 ID |
3749 | return -ENODEV; |
3750 | ||
e6994aee CW |
3751 | level = I915_CACHE_LLC; |
3752 | break; | |
4257d3ba | 3753 | case I915_CACHING_DISPLAY: |
9c870d03 | 3754 | level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE; |
4257d3ba | 3755 | break; |
e6994aee CW |
3756 | default: |
3757 | return -EINVAL; | |
3758 | } | |
3759 | ||
d65415df CW |
3760 | obj = i915_gem_object_lookup(file, args->handle); |
3761 | if (!obj) | |
3762 | return -ENOENT; | |
3763 | ||
3764 | if (obj->cache_level == level) | |
3765 | goto out; | |
3766 | ||
3767 | ret = i915_gem_object_wait(obj, | |
3768 | I915_WAIT_INTERRUPTIBLE, | |
3769 | MAX_SCHEDULE_TIMEOUT, | |
3770 | to_rps_client(file)); | |
3bc2913e | 3771 | if (ret) |
d65415df | 3772 | goto out; |
3bc2913e | 3773 | |
d65415df CW |
3774 | ret = i915_mutex_lock_interruptible(dev); |
3775 | if (ret) | |
3776 | goto out; | |
e6994aee CW |
3777 | |
3778 | ret = i915_gem_object_set_cache_level(obj, level); | |
e6994aee | 3779 | mutex_unlock(&dev->struct_mutex); |
d65415df CW |
3780 | |
3781 | out: | |
3782 | i915_gem_object_put(obj); | |
e6994aee CW |
3783 | return ret; |
3784 | } | |
3785 | ||
b9241ea3 | 3786 | /* |
2da3b9b9 CW |
3787 | * Prepare buffer for display plane (scanout, cursors, etc). |
3788 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3789 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 | 3790 | */ |
058d88c4 | 3791 | struct i915_vma * |
2da3b9b9 CW |
3792 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3793 | u32 alignment, | |
e6617330 | 3794 | const struct i915_ggtt_view *view) |
b9241ea3 | 3795 | { |
058d88c4 | 3796 | struct i915_vma *vma; |
b9241ea3 ZW |
3797 | int ret; |
3798 | ||
4c7d62c6 CW |
3799 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3800 | ||
cc98b413 CW |
3801 | /* Mark the pin_display early so that we account for the |
3802 | * display coherency whilst setting up the cache domains. | |
3803 | */ | |
8a0c39b1 | 3804 | obj->pin_display++; |
cc98b413 | 3805 | |
a7ef0640 EA |
3806 | /* The display engine is not coherent with the LLC cache on gen6. As |
3807 | * a result, we make sure that the pinning that is about to occur is | |
3808 | * done with uncached PTEs. This is lowest common denominator for all | |
3809 | * chipsets. | |
3810 | * | |
3811 | * However for gen6+, we could do better by using the GFDT bit instead | |
3812 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3813 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3814 | */ | |
651d794f | 3815 | ret = i915_gem_object_set_cache_level(obj, |
8652744b TU |
3816 | HAS_WT(to_i915(obj->base.dev)) ? |
3817 | I915_CACHE_WT : I915_CACHE_NONE); | |
058d88c4 CW |
3818 | if (ret) { |
3819 | vma = ERR_PTR(ret); | |
cc98b413 | 3820 | goto err_unpin_display; |
058d88c4 | 3821 | } |
a7ef0640 | 3822 | |
2da3b9b9 CW |
3823 | /* As the user may map the buffer once pinned in the display plane |
3824 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2efb813d CW |
3825 | * always use map_and_fenceable for all scanout buffers. However, |
3826 | * it may simply be too big to fit into mappable, in which case | |
3827 | * put it anyway and hope that userspace can cope (but always first | |
3828 | * try to preserve the existing ABI). | |
2da3b9b9 | 3829 | */ |
2efb813d | 3830 | vma = ERR_PTR(-ENOSPC); |
47a8e3f6 | 3831 | if (!view || view->type == I915_GGTT_VIEW_NORMAL) |
2efb813d CW |
3832 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, |
3833 | PIN_MAPPABLE | PIN_NONBLOCK); | |
767a222e CW |
3834 | if (IS_ERR(vma)) { |
3835 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
3836 | unsigned int flags; | |
3837 | ||
3838 | /* Valleyview is definitely limited to scanning out the first | |
3839 | * 512MiB. Lets presume this behaviour was inherited from the | |
3840 | * g4x display engine and that all earlier gen are similarly | |
3841 | * limited. Testing suggests that it is a little more | |
3842 | * complicated than this. For example, Cherryview appears quite | |
3843 | * happy to scanout from anywhere within its global aperture. | |
3844 | */ | |
3845 | flags = 0; | |
3846 | if (HAS_GMCH_DISPLAY(i915)) | |
3847 | flags = PIN_MAPPABLE; | |
3848 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags); | |
3849 | } | |
058d88c4 | 3850 | if (IS_ERR(vma)) |
cc98b413 | 3851 | goto err_unpin_display; |
2da3b9b9 | 3852 | |
d8923dcf CW |
3853 | vma->display_alignment = max_t(u64, vma->display_alignment, alignment); |
3854 | ||
a6a7cc4b | 3855 | /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ |
5a97bcc6 | 3856 | __i915_gem_object_flush_for_display(obj); |
d59b21ec | 3857 | intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); |
b118c1e3 | 3858 | |
2da3b9b9 CW |
3859 | /* It should now be out of any other write domains, and we can update |
3860 | * the domain values for our changes. | |
3861 | */ | |
05394f39 | 3862 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 | 3863 | |
058d88c4 | 3864 | return vma; |
cc98b413 CW |
3865 | |
3866 | err_unpin_display: | |
8a0c39b1 | 3867 | obj->pin_display--; |
058d88c4 | 3868 | return vma; |
cc98b413 CW |
3869 | } |
3870 | ||
3871 | void | |
058d88c4 | 3872 | i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) |
cc98b413 | 3873 | { |
49d73912 | 3874 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
4c7d62c6 | 3875 | |
058d88c4 | 3876 | if (WARN_ON(vma->obj->pin_display == 0)) |
8a0c39b1 TU |
3877 | return; |
3878 | ||
d8923dcf | 3879 | if (--vma->obj->pin_display == 0) |
f51455d4 | 3880 | vma->display_alignment = I915_GTT_MIN_ALIGNMENT; |
e6617330 | 3881 | |
383d5823 | 3882 | /* Bump the LRU to try and avoid premature eviction whilst flipping */ |
befedbb7 | 3883 | i915_gem_object_bump_inactive_ggtt(vma->obj); |
383d5823 | 3884 | |
058d88c4 | 3885 | i915_vma_unpin(vma); |
b9241ea3 ZW |
3886 | } |
3887 | ||
e47c68e9 EA |
3888 | /** |
3889 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3890 | * @obj: object to act on |
3891 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3892 | * |
3893 | * This function returns when the move is complete, including waiting on | |
3894 | * flushes to occur. | |
3895 | */ | |
dabdfe02 | 3896 | int |
919926ae | 3897 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3898 | { |
e47c68e9 EA |
3899 | int ret; |
3900 | ||
e95433c7 | 3901 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3902 | |
e95433c7 CW |
3903 | ret = i915_gem_object_wait(obj, |
3904 | I915_WAIT_INTERRUPTIBLE | | |
3905 | I915_WAIT_LOCKED | | |
3906 | (write ? I915_WAIT_ALL : 0), | |
3907 | MAX_SCHEDULE_TIMEOUT, | |
3908 | NULL); | |
88241785 CW |
3909 | if (ret) |
3910 | return ret; | |
3911 | ||
ef74921b | 3912 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); |
2ef7eeaa | 3913 | |
e47c68e9 | 3914 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3915 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
57822dc6 | 3916 | i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC); |
05394f39 | 3917 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3918 | } |
3919 | ||
3920 | /* It should now be out of any other write domains, and we can update | |
3921 | * the domain values for our changes. | |
3922 | */ | |
e27ab73d | 3923 | GEM_BUG_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
e47c68e9 EA |
3924 | |
3925 | /* If we're writing through the CPU, then the GPU read domains will | |
3926 | * need to be invalidated at next use. | |
3927 | */ | |
e27ab73d CW |
3928 | if (write) |
3929 | __start_cpu_write(obj); | |
2ef7eeaa EA |
3930 | |
3931 | return 0; | |
3932 | } | |
3933 | ||
673a394b EA |
3934 | /* Throttle our rendering by waiting until the ring has completed our requests |
3935 | * emitted over 20 msec ago. | |
3936 | * | |
b962442e EA |
3937 | * Note that if we were to use the current jiffies each time around the loop, |
3938 | * we wouldn't escape the function with any frames outstanding if the time to | |
3939 | * render a frame was over 20ms. | |
3940 | * | |
673a394b EA |
3941 | * This should get us reasonable parallelism between CPU and GPU but also |
3942 | * relatively low latency when blocking on a particular request to finish. | |
3943 | */ | |
40a5f0de | 3944 | static int |
f787a5f5 | 3945 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3946 | { |
fac5e23e | 3947 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3948 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3949 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3950 | struct drm_i915_gem_request *request, *target = NULL; |
e95433c7 | 3951 | long ret; |
93533c29 | 3952 | |
f4457ae7 CW |
3953 | /* ABI: return -EIO if already wedged */ |
3954 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3955 | return -EIO; | |
e110e8d6 | 3956 | |
1c25595f | 3957 | spin_lock(&file_priv->mm.lock); |
c8659efa | 3958 | list_for_each_entry(request, &file_priv->mm.request_list, client_link) { |
b962442e EA |
3959 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3960 | break; | |
40a5f0de | 3961 | |
c8659efa CW |
3962 | if (target) { |
3963 | list_del(&target->client_link); | |
3964 | target->file_priv = NULL; | |
3965 | } | |
fcfa423c | 3966 | |
54fb2411 | 3967 | target = request; |
b962442e | 3968 | } |
ff865885 | 3969 | if (target) |
e8a261ea | 3970 | i915_gem_request_get(target); |
1c25595f | 3971 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3972 | |
54fb2411 | 3973 | if (target == NULL) |
f787a5f5 | 3974 | return 0; |
2bc43b5c | 3975 | |
e95433c7 CW |
3976 | ret = i915_wait_request(target, |
3977 | I915_WAIT_INTERRUPTIBLE, | |
3978 | MAX_SCHEDULE_TIMEOUT); | |
e8a261ea | 3979 | i915_gem_request_put(target); |
ff865885 | 3980 | |
e95433c7 | 3981 | return ret < 0 ? ret : 0; |
40a5f0de EA |
3982 | } |
3983 | ||
058d88c4 | 3984 | struct i915_vma * |
ec7adb6e JL |
3985 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3986 | const struct i915_ggtt_view *view, | |
91b2db6f | 3987 | u64 size, |
2ffffd0f CW |
3988 | u64 alignment, |
3989 | u64 flags) | |
ec7adb6e | 3990 | { |
ad16d2ed CW |
3991 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
3992 | struct i915_address_space *vm = &dev_priv->ggtt.base; | |
59bfa124 CW |
3993 | struct i915_vma *vma; |
3994 | int ret; | |
72e96d64 | 3995 | |
4c7d62c6 CW |
3996 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3997 | ||
718659a6 | 3998 | vma = i915_vma_instance(obj, vm, view); |
e0216b76 | 3999 | if (unlikely(IS_ERR(vma))) |
058d88c4 | 4000 | return vma; |
59bfa124 CW |
4001 | |
4002 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
4003 | if (flags & PIN_NONBLOCK && | |
4004 | (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))) | |
058d88c4 | 4005 | return ERR_PTR(-ENOSPC); |
59bfa124 | 4006 | |
ad16d2ed | 4007 | if (flags & PIN_MAPPABLE) { |
ad16d2ed CW |
4008 | /* If the required space is larger than the available |
4009 | * aperture, we will not able to find a slot for the | |
4010 | * object and unbinding the object now will be in | |
4011 | * vain. Worse, doing so may cause us to ping-pong | |
4012 | * the object in and out of the Global GTT and | |
4013 | * waste a lot of cycles under the mutex. | |
4014 | */ | |
944397f0 | 4015 | if (vma->fence_size > dev_priv->ggtt.mappable_end) |
ad16d2ed CW |
4016 | return ERR_PTR(-E2BIG); |
4017 | ||
4018 | /* If NONBLOCK is set the caller is optimistically | |
4019 | * trying to cache the full object within the mappable | |
4020 | * aperture, and *must* have a fallback in place for | |
4021 | * situations where we cannot bind the object. We | |
4022 | * can be a little more lax here and use the fallback | |
4023 | * more often to avoid costly migrations of ourselves | |
4024 | * and other objects within the aperture. | |
4025 | * | |
4026 | * Half-the-aperture is used as a simple heuristic. | |
4027 | * More interesting would to do search for a free | |
4028 | * block prior to making the commitment to unbind. | |
4029 | * That caters for the self-harm case, and with a | |
4030 | * little more heuristics (e.g. NOFAULT, NOEVICT) | |
4031 | * we could try to minimise harm to others. | |
4032 | */ | |
4033 | if (flags & PIN_NONBLOCK && | |
944397f0 | 4034 | vma->fence_size > dev_priv->ggtt.mappable_end / 2) |
ad16d2ed CW |
4035 | return ERR_PTR(-ENOSPC); |
4036 | } | |
4037 | ||
59bfa124 CW |
4038 | WARN(i915_vma_is_pinned(vma), |
4039 | "bo is already pinned in ggtt with incorrect alignment:" | |
05a20d09 CW |
4040 | " offset=%08x, req.alignment=%llx," |
4041 | " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n", | |
4042 | i915_ggtt_offset(vma), alignment, | |
59bfa124 | 4043 | !!(flags & PIN_MAPPABLE), |
05a20d09 | 4044 | i915_vma_is_map_and_fenceable(vma)); |
59bfa124 CW |
4045 | ret = i915_vma_unbind(vma); |
4046 | if (ret) | |
058d88c4 | 4047 | return ERR_PTR(ret); |
59bfa124 CW |
4048 | } |
4049 | ||
058d88c4 CW |
4050 | ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); |
4051 | if (ret) | |
4052 | return ERR_PTR(ret); | |
ec7adb6e | 4053 | |
058d88c4 | 4054 | return vma; |
673a394b EA |
4055 | } |
4056 | ||
edf6b76f | 4057 | static __always_inline unsigned int __busy_read_flag(unsigned int id) |
3fdc13c7 CW |
4058 | { |
4059 | /* Note that we could alias engines in the execbuf API, but | |
4060 | * that would be very unwise as it prevents userspace from | |
4061 | * fine control over engine selection. Ahem. | |
4062 | * | |
4063 | * This should be something like EXEC_MAX_ENGINE instead of | |
4064 | * I915_NUM_ENGINES. | |
4065 | */ | |
4066 | BUILD_BUG_ON(I915_NUM_ENGINES > 16); | |
4067 | return 0x10000 << id; | |
4068 | } | |
4069 | ||
4070 | static __always_inline unsigned int __busy_write_id(unsigned int id) | |
4071 | { | |
70cb472c CW |
4072 | /* The uABI guarantees an active writer is also amongst the read |
4073 | * engines. This would be true if we accessed the activity tracking | |
4074 | * under the lock, but as we perform the lookup of the object and | |
4075 | * its activity locklessly we can not guarantee that the last_write | |
4076 | * being active implies that we have set the same engine flag from | |
4077 | * last_read - hence we always set both read and write busy for | |
4078 | * last_write. | |
4079 | */ | |
4080 | return id | __busy_read_flag(id); | |
3fdc13c7 CW |
4081 | } |
4082 | ||
edf6b76f | 4083 | static __always_inline unsigned int |
d07f0e59 | 4084 | __busy_set_if_active(const struct dma_fence *fence, |
3fdc13c7 CW |
4085 | unsigned int (*flag)(unsigned int id)) |
4086 | { | |
d07f0e59 | 4087 | struct drm_i915_gem_request *rq; |
3fdc13c7 | 4088 | |
d07f0e59 CW |
4089 | /* We have to check the current hw status of the fence as the uABI |
4090 | * guarantees forward progress. We could rely on the idle worker | |
4091 | * to eventually flush us, but to minimise latency just ask the | |
4092 | * hardware. | |
1255501d | 4093 | * |
d07f0e59 | 4094 | * Note we only report on the status of native fences. |
1255501d | 4095 | */ |
d07f0e59 CW |
4096 | if (!dma_fence_is_i915(fence)) |
4097 | return 0; | |
4098 | ||
4099 | /* opencode to_request() in order to avoid const warnings */ | |
4100 | rq = container_of(fence, struct drm_i915_gem_request, fence); | |
4101 | if (i915_gem_request_completed(rq)) | |
4102 | return 0; | |
4103 | ||
1d39f281 | 4104 | return flag(rq->engine->uabi_id); |
3fdc13c7 CW |
4105 | } |
4106 | ||
edf6b76f | 4107 | static __always_inline unsigned int |
d07f0e59 | 4108 | busy_check_reader(const struct dma_fence *fence) |
3fdc13c7 | 4109 | { |
d07f0e59 | 4110 | return __busy_set_if_active(fence, __busy_read_flag); |
3fdc13c7 CW |
4111 | } |
4112 | ||
edf6b76f | 4113 | static __always_inline unsigned int |
d07f0e59 | 4114 | busy_check_writer(const struct dma_fence *fence) |
3fdc13c7 | 4115 | { |
d07f0e59 CW |
4116 | if (!fence) |
4117 | return 0; | |
4118 | ||
4119 | return __busy_set_if_active(fence, __busy_write_id); | |
3fdc13c7 CW |
4120 | } |
4121 | ||
673a394b EA |
4122 | int |
4123 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4124 | struct drm_file *file) |
673a394b EA |
4125 | { |
4126 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4127 | struct drm_i915_gem_object *obj; |
d07f0e59 CW |
4128 | struct reservation_object_list *list; |
4129 | unsigned int seq; | |
fbbd37b3 | 4130 | int err; |
673a394b | 4131 | |
d07f0e59 | 4132 | err = -ENOENT; |
fbbd37b3 CW |
4133 | rcu_read_lock(); |
4134 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
d07f0e59 | 4135 | if (!obj) |
fbbd37b3 | 4136 | goto out; |
d1b851fc | 4137 | |
d07f0e59 CW |
4138 | /* A discrepancy here is that we do not report the status of |
4139 | * non-i915 fences, i.e. even though we may report the object as idle, | |
4140 | * a call to set-domain may still stall waiting for foreign rendering. | |
4141 | * This also means that wait-ioctl may report an object as busy, | |
4142 | * where busy-ioctl considers it idle. | |
4143 | * | |
4144 | * We trade the ability to warn of foreign fences to report on which | |
4145 | * i915 engines are active for the object. | |
4146 | * | |
4147 | * Alternatively, we can trade that extra information on read/write | |
4148 | * activity with | |
4149 | * args->busy = | |
4150 | * !reservation_object_test_signaled_rcu(obj->resv, true); | |
4151 | * to report the overall busyness. This is what the wait-ioctl does. | |
4152 | * | |
4153 | */ | |
4154 | retry: | |
4155 | seq = raw_read_seqcount(&obj->resv->seq); | |
426960be | 4156 | |
d07f0e59 CW |
4157 | /* Translate the exclusive fence to the READ *and* WRITE engine */ |
4158 | args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl)); | |
3fdc13c7 | 4159 | |
d07f0e59 CW |
4160 | /* Translate shared fences to READ set of engines */ |
4161 | list = rcu_dereference(obj->resv->fence); | |
4162 | if (list) { | |
4163 | unsigned int shared_count = list->shared_count, i; | |
3fdc13c7 | 4164 | |
d07f0e59 CW |
4165 | for (i = 0; i < shared_count; ++i) { |
4166 | struct dma_fence *fence = | |
4167 | rcu_dereference(list->shared[i]); | |
4168 | ||
4169 | args->busy |= busy_check_reader(fence); | |
4170 | } | |
426960be | 4171 | } |
673a394b | 4172 | |
d07f0e59 CW |
4173 | if (args->busy && read_seqcount_retry(&obj->resv->seq, seq)) |
4174 | goto retry; | |
4175 | ||
4176 | err = 0; | |
fbbd37b3 CW |
4177 | out: |
4178 | rcu_read_unlock(); | |
4179 | return err; | |
673a394b EA |
4180 | } |
4181 | ||
4182 | int | |
4183 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4184 | struct drm_file *file_priv) | |
4185 | { | |
0206e353 | 4186 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4187 | } |
4188 | ||
3ef94daa CW |
4189 | int |
4190 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4191 | struct drm_file *file_priv) | |
4192 | { | |
fac5e23e | 4193 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 4194 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4195 | struct drm_i915_gem_object *obj; |
1233e2db | 4196 | int err; |
3ef94daa CW |
4197 | |
4198 | switch (args->madv) { | |
4199 | case I915_MADV_DONTNEED: | |
4200 | case I915_MADV_WILLNEED: | |
4201 | break; | |
4202 | default: | |
4203 | return -EINVAL; | |
4204 | } | |
4205 | ||
03ac0642 | 4206 | obj = i915_gem_object_lookup(file_priv, args->handle); |
1233e2db CW |
4207 | if (!obj) |
4208 | return -ENOENT; | |
4209 | ||
4210 | err = mutex_lock_interruptible(&obj->mm.lock); | |
4211 | if (err) | |
4212 | goto out; | |
3ef94daa | 4213 | |
a4f5ea64 | 4214 | if (obj->mm.pages && |
3e510a8e | 4215 | i915_gem_object_is_tiled(obj) && |
656bfa3a | 4216 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
bc0629a7 CW |
4217 | if (obj->mm.madv == I915_MADV_WILLNEED) { |
4218 | GEM_BUG_ON(!obj->mm.quirked); | |
a4f5ea64 | 4219 | __i915_gem_object_unpin_pages(obj); |
bc0629a7 CW |
4220 | obj->mm.quirked = false; |
4221 | } | |
4222 | if (args->madv == I915_MADV_WILLNEED) { | |
2c3a3f44 | 4223 | GEM_BUG_ON(obj->mm.quirked); |
a4f5ea64 | 4224 | __i915_gem_object_pin_pages(obj); |
bc0629a7 CW |
4225 | obj->mm.quirked = true; |
4226 | } | |
656bfa3a DV |
4227 | } |
4228 | ||
a4f5ea64 CW |
4229 | if (obj->mm.madv != __I915_MADV_PURGED) |
4230 | obj->mm.madv = args->madv; | |
3ef94daa | 4231 | |
6c085a72 | 4232 | /* if the object is no longer attached, discard its backing storage */ |
a4f5ea64 | 4233 | if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages) |
2d7ef395 CW |
4234 | i915_gem_object_truncate(obj); |
4235 | ||
a4f5ea64 | 4236 | args->retained = obj->mm.madv != __I915_MADV_PURGED; |
1233e2db | 4237 | mutex_unlock(&obj->mm.lock); |
bb6baf76 | 4238 | |
1233e2db | 4239 | out: |
f8c417cd | 4240 | i915_gem_object_put(obj); |
1233e2db | 4241 | return err; |
3ef94daa CW |
4242 | } |
4243 | ||
5b8c8aec CW |
4244 | static void |
4245 | frontbuffer_retire(struct i915_gem_active *active, | |
4246 | struct drm_i915_gem_request *request) | |
4247 | { | |
4248 | struct drm_i915_gem_object *obj = | |
4249 | container_of(active, typeof(*obj), frontbuffer_write); | |
4250 | ||
d59b21ec | 4251 | intel_fb_obj_flush(obj, ORIGIN_CS); |
5b8c8aec CW |
4252 | } |
4253 | ||
37e680a1 CW |
4254 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4255 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4256 | { |
1233e2db CW |
4257 | mutex_init(&obj->mm.lock); |
4258 | ||
56cea323 | 4259 | INIT_LIST_HEAD(&obj->global_link); |
275f039d | 4260 | INIT_LIST_HEAD(&obj->userfault_link); |
2f633156 | 4261 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4262 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4263 | |
37e680a1 CW |
4264 | obj->ops = ops; |
4265 | ||
d07f0e59 CW |
4266 | reservation_object_init(&obj->__builtin_resv); |
4267 | obj->resv = &obj->__builtin_resv; | |
4268 | ||
50349247 | 4269 | obj->frontbuffer_ggtt_origin = ORIGIN_GTT; |
5b8c8aec | 4270 | init_request_active(&obj->frontbuffer_write, frontbuffer_retire); |
a4f5ea64 CW |
4271 | |
4272 | obj->mm.madv = I915_MADV_WILLNEED; | |
4273 | INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN); | |
4274 | mutex_init(&obj->mm.get_page.lock); | |
0327d6ba | 4275 | |
f19ec8cb | 4276 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
4277 | } |
4278 | ||
37e680a1 | 4279 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3599a91c TU |
4280 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE | |
4281 | I915_GEM_OBJECT_IS_SHRINKABLE, | |
7c55e2c5 | 4282 | |
37e680a1 CW |
4283 | .get_pages = i915_gem_object_get_pages_gtt, |
4284 | .put_pages = i915_gem_object_put_pages_gtt, | |
7c55e2c5 CW |
4285 | |
4286 | .pwrite = i915_gem_object_pwrite_gtt, | |
37e680a1 CW |
4287 | }; |
4288 | ||
b4bcbe2a | 4289 | struct drm_i915_gem_object * |
12d79d78 | 4290 | i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) |
ac52bc56 | 4291 | { |
c397b908 | 4292 | struct drm_i915_gem_object *obj; |
5949eac4 | 4293 | struct address_space *mapping; |
1a240d4d | 4294 | gfp_t mask; |
fe3db79b | 4295 | int ret; |
ac52bc56 | 4296 | |
b4bcbe2a CW |
4297 | /* There is a prevalence of the assumption that we fit the object's |
4298 | * page count inside a 32bit _signed_ variable. Let's document this and | |
4299 | * catch if we ever need to fix it. In the meantime, if you do spot | |
4300 | * such a local variable, please consider fixing! | |
4301 | */ | |
7a3ee5de | 4302 | if (size >> PAGE_SHIFT > INT_MAX) |
b4bcbe2a CW |
4303 | return ERR_PTR(-E2BIG); |
4304 | ||
4305 | if (overflows_type(size, obj->base.size)) | |
4306 | return ERR_PTR(-E2BIG); | |
4307 | ||
187685cb | 4308 | obj = i915_gem_object_alloc(dev_priv); |
c397b908 | 4309 | if (obj == NULL) |
fe3db79b | 4310 | return ERR_PTR(-ENOMEM); |
673a394b | 4311 | |
12d79d78 | 4312 | ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size); |
fe3db79b CW |
4313 | if (ret) |
4314 | goto fail; | |
673a394b | 4315 | |
bed1ea95 | 4316 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
c0f86832 | 4317 | if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) { |
bed1ea95 CW |
4318 | /* 965gm cannot relocate objects above 4GiB. */ |
4319 | mask &= ~__GFP_HIGHMEM; | |
4320 | mask |= __GFP_DMA32; | |
4321 | } | |
4322 | ||
93c76a3d | 4323 | mapping = obj->base.filp->f_mapping; |
bed1ea95 | 4324 | mapping_set_gfp_mask(mapping, mask); |
4846bf0c | 4325 | GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM)); |
5949eac4 | 4326 | |
37e680a1 | 4327 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4328 | |
c397b908 DV |
4329 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4330 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4331 | |
0031fb96 | 4332 | if (HAS_LLC(dev_priv)) { |
3d29b842 | 4333 | /* On some devices, we can have the GPU use the LLC (the CPU |
a1871112 EA |
4334 | * cache) for about a 10% performance improvement |
4335 | * compared to uncached. Graphics requests other than | |
4336 | * display scanout are coherent with the CPU in | |
4337 | * accessing this cache. This means in this mode we | |
4338 | * don't need to clflush on the CPU side, and on the | |
4339 | * GPU side we only need to flush internal caches to | |
4340 | * get data visible to the CPU. | |
4341 | * | |
4342 | * However, we maintain the display planes as UC, and so | |
4343 | * need to rebind when first used as such. | |
4344 | */ | |
4345 | obj->cache_level = I915_CACHE_LLC; | |
4346 | } else | |
4347 | obj->cache_level = I915_CACHE_NONE; | |
4348 | ||
7fc92e96 CW |
4349 | obj->cache_coherent = i915_gem_object_is_coherent(obj); |
4350 | obj->cache_dirty = !obj->cache_coherent; | |
e27ab73d | 4351 | |
d861e338 DV |
4352 | trace_i915_gem_object_create(obj); |
4353 | ||
05394f39 | 4354 | return obj; |
fe3db79b CW |
4355 | |
4356 | fail: | |
4357 | i915_gem_object_free(obj); | |
fe3db79b | 4358 | return ERR_PTR(ret); |
c397b908 DV |
4359 | } |
4360 | ||
340fbd8c CW |
4361 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4362 | { | |
4363 | /* If we are the last user of the backing storage (be it shmemfs | |
4364 | * pages or stolen etc), we know that the pages are going to be | |
4365 | * immediately released. In this case, we can then skip copying | |
4366 | * back the contents from the GPU. | |
4367 | */ | |
4368 | ||
a4f5ea64 | 4369 | if (obj->mm.madv != I915_MADV_WILLNEED) |
340fbd8c CW |
4370 | return false; |
4371 | ||
4372 | if (obj->base.filp == NULL) | |
4373 | return true; | |
4374 | ||
4375 | /* At first glance, this looks racy, but then again so would be | |
4376 | * userspace racing mmap against close. However, the first external | |
4377 | * reference to the filp can only be obtained through the | |
4378 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4379 | * acquiring such a reference whilst we are in the middle of | |
4380 | * freeing the object. | |
4381 | */ | |
4382 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4383 | } | |
4384 | ||
fbbd37b3 CW |
4385 | static void __i915_gem_free_objects(struct drm_i915_private *i915, |
4386 | struct llist_node *freed) | |
673a394b | 4387 | { |
fbbd37b3 | 4388 | struct drm_i915_gem_object *obj, *on; |
673a394b | 4389 | |
fbbd37b3 CW |
4390 | mutex_lock(&i915->drm.struct_mutex); |
4391 | intel_runtime_pm_get(i915); | |
4392 | llist_for_each_entry(obj, freed, freed) { | |
4393 | struct i915_vma *vma, *vn; | |
4394 | ||
4395 | trace_i915_gem_object_destroy(obj); | |
4396 | ||
4397 | GEM_BUG_ON(i915_gem_object_is_active(obj)); | |
4398 | list_for_each_entry_safe(vma, vn, | |
4399 | &obj->vma_list, obj_link) { | |
fbbd37b3 CW |
4400 | GEM_BUG_ON(i915_vma_is_active(vma)); |
4401 | vma->flags &= ~I915_VMA_PIN_MASK; | |
4402 | i915_vma_close(vma); | |
4403 | } | |
db6c2b41 CW |
4404 | GEM_BUG_ON(!list_empty(&obj->vma_list)); |
4405 | GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree)); | |
fbbd37b3 | 4406 | |
56cea323 | 4407 | list_del(&obj->global_link); |
fbbd37b3 CW |
4408 | } |
4409 | intel_runtime_pm_put(i915); | |
4410 | mutex_unlock(&i915->drm.struct_mutex); | |
4411 | ||
f2be9d68 CW |
4412 | cond_resched(); |
4413 | ||
fbbd37b3 CW |
4414 | llist_for_each_entry_safe(obj, on, freed, freed) { |
4415 | GEM_BUG_ON(obj->bind_count); | |
4416 | GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits)); | |
4417 | ||
4418 | if (obj->ops->release) | |
4419 | obj->ops->release(obj); | |
f65c9168 | 4420 | |
fbbd37b3 CW |
4421 | if (WARN_ON(i915_gem_object_has_pinned_pages(obj))) |
4422 | atomic_set(&obj->mm.pages_pin_count, 0); | |
548625ee | 4423 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
fbbd37b3 CW |
4424 | GEM_BUG_ON(obj->mm.pages); |
4425 | ||
4426 | if (obj->base.import_attach) | |
4427 | drm_prime_gem_destroy(&obj->base, NULL); | |
4428 | ||
d07f0e59 | 4429 | reservation_object_fini(&obj->__builtin_resv); |
fbbd37b3 CW |
4430 | drm_gem_object_release(&obj->base); |
4431 | i915_gem_info_remove_obj(i915, obj->base.size); | |
4432 | ||
4433 | kfree(obj->bit_17); | |
4434 | i915_gem_object_free(obj); | |
4435 | } | |
4436 | } | |
4437 | ||
4438 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915) | |
4439 | { | |
4440 | struct llist_node *freed; | |
4441 | ||
4442 | freed = llist_del_all(&i915->mm.free_list); | |
4443 | if (unlikely(freed)) | |
4444 | __i915_gem_free_objects(i915, freed); | |
4445 | } | |
4446 | ||
4447 | static void __i915_gem_free_work(struct work_struct *work) | |
4448 | { | |
4449 | struct drm_i915_private *i915 = | |
4450 | container_of(work, struct drm_i915_private, mm.free_work); | |
4451 | struct llist_node *freed; | |
26e12f89 | 4452 | |
b1f788c6 CW |
4453 | /* All file-owned VMA should have been released by this point through |
4454 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
4455 | * However, the object may also be bound into the global GTT (e.g. | |
4456 | * older GPUs without per-process support, or for direct access through | |
4457 | * the GTT either for the user or for scanout). Those VMA still need to | |
4458 | * unbound now. | |
4459 | */ | |
1488fc08 | 4460 | |
5ad08be7 | 4461 | while ((freed = llist_del_all(&i915->mm.free_list))) { |
fbbd37b3 | 4462 | __i915_gem_free_objects(i915, freed); |
5ad08be7 CW |
4463 | if (need_resched()) |
4464 | break; | |
4465 | } | |
fbbd37b3 | 4466 | } |
a071fa00 | 4467 | |
fbbd37b3 CW |
4468 | static void __i915_gem_free_object_rcu(struct rcu_head *head) |
4469 | { | |
4470 | struct drm_i915_gem_object *obj = | |
4471 | container_of(head, typeof(*obj), rcu); | |
4472 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
4473 | ||
4474 | /* We can't simply use call_rcu() from i915_gem_free_object() | |
4475 | * as we need to block whilst unbinding, and the call_rcu | |
4476 | * task may be called from softirq context. So we take a | |
4477 | * detour through a worker. | |
4478 | */ | |
4479 | if (llist_add(&obj->freed, &i915->mm.free_list)) | |
4480 | schedule_work(&i915->mm.free_work); | |
4481 | } | |
656bfa3a | 4482 | |
fbbd37b3 CW |
4483 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
4484 | { | |
4485 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); | |
a4f5ea64 | 4486 | |
bc0629a7 CW |
4487 | if (obj->mm.quirked) |
4488 | __i915_gem_object_unpin_pages(obj); | |
4489 | ||
340fbd8c | 4490 | if (discard_backing_storage(obj)) |
a4f5ea64 | 4491 | obj->mm.madv = I915_MADV_DONTNEED; |
de151cf6 | 4492 | |
fbbd37b3 CW |
4493 | /* Before we free the object, make sure any pure RCU-only |
4494 | * read-side critical sections are complete, e.g. | |
4495 | * i915_gem_busy_ioctl(). For the corresponding synchronized | |
4496 | * lookup see i915_gem_object_lookup_rcu(). | |
4497 | */ | |
4498 | call_rcu(&obj->rcu, __i915_gem_free_object_rcu); | |
673a394b EA |
4499 | } |
4500 | ||
f8a7fde4 CW |
4501 | void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj) |
4502 | { | |
4503 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
4504 | ||
4505 | GEM_BUG_ON(i915_gem_object_has_active_reference(obj)); | |
4506 | if (i915_gem_object_is_active(obj)) | |
4507 | i915_gem_object_set_active_reference(obj); | |
4508 | else | |
4509 | i915_gem_object_put(obj); | |
4510 | } | |
4511 | ||
3033acab CW |
4512 | static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv) |
4513 | { | |
4514 | struct intel_engine_cs *engine; | |
4515 | enum intel_engine_id id; | |
4516 | ||
4517 | for_each_engine(engine, dev_priv, id) | |
f131e356 CW |
4518 | GEM_BUG_ON(engine->last_retired_context && |
4519 | !i915_gem_context_is_kernel(engine->last_retired_context)); | |
3033acab CW |
4520 | } |
4521 | ||
24145517 CW |
4522 | void i915_gem_sanitize(struct drm_i915_private *i915) |
4523 | { | |
4524 | /* | |
4525 | * If we inherit context state from the BIOS or earlier occupants | |
4526 | * of the GPU, the GPU may be in an inconsistent state when we | |
4527 | * try to take over. The only way to remove the earlier state | |
4528 | * is by resetting. However, resetting on earlier gen is tricky as | |
4529 | * it may impact the display and we are uncertain about the stability | |
ea117b8d | 4530 | * of the reset, so this could be applied to even earlier gen. |
24145517 | 4531 | */ |
ea117b8d | 4532 | if (INTEL_GEN(i915) >= 5) { |
24145517 CW |
4533 | int reset = intel_gpu_reset(i915, ALL_ENGINES); |
4534 | WARN_ON(reset && reset != -ENODEV); | |
4535 | } | |
4536 | } | |
4537 | ||
bf9e8429 | 4538 | int i915_gem_suspend(struct drm_i915_private *dev_priv) |
29105ccc | 4539 | { |
bf9e8429 | 4540 | struct drm_device *dev = &dev_priv->drm; |
dcff85c8 | 4541 | int ret; |
28dfe52a | 4542 | |
c998e8a0 | 4543 | intel_runtime_pm_get(dev_priv); |
54b4f68f CW |
4544 | intel_suspend_gt_powersave(dev_priv); |
4545 | ||
45c5f202 | 4546 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4547 | |
4548 | /* We have to flush all the executing contexts to main memory so | |
4549 | * that they can saved in the hibernation image. To ensure the last | |
4550 | * context image is coherent, we have to switch away from it. That | |
4551 | * leaves the dev_priv->kernel_context still active when | |
4552 | * we actually suspend, and its image in memory may not match the GPU | |
4553 | * state. Fortunately, the kernel_context is disposable and we do | |
4554 | * not rely on its state. | |
4555 | */ | |
4556 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4557 | if (ret) | |
c998e8a0 | 4558 | goto err_unlock; |
5ab57c70 | 4559 | |
22dd3bb9 CW |
4560 | ret = i915_gem_wait_for_idle(dev_priv, |
4561 | I915_WAIT_INTERRUPTIBLE | | |
4562 | I915_WAIT_LOCKED); | |
f7403347 | 4563 | if (ret) |
c998e8a0 | 4564 | goto err_unlock; |
f7403347 | 4565 | |
3033acab | 4566 | assert_kernel_context_is_current(dev_priv); |
b2e862d0 | 4567 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4568 | mutex_unlock(&dev->struct_mutex); |
4569 | ||
63987bfe SAK |
4570 | intel_guc_suspend(dev_priv); |
4571 | ||
737b1506 | 4572 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 | 4573 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
bdeb9785 CW |
4574 | |
4575 | /* As the idle_work is rearming if it detects a race, play safe and | |
4576 | * repeat the flush until it is definitely idle. | |
4577 | */ | |
4578 | while (flush_delayed_work(&dev_priv->gt.idle_work)) | |
4579 | ; | |
4580 | ||
4581 | i915_gem_drain_freed_objects(dev_priv); | |
29105ccc | 4582 | |
bdcf120b CW |
4583 | /* Assert that we sucessfully flushed all the work and |
4584 | * reset the GPU back to its idle, low power state. | |
4585 | */ | |
67d97da3 | 4586 | WARN_ON(dev_priv->gt.awake); |
05425249 | 4587 | WARN_ON(!intel_engines_are_idle(dev_priv)); |
bdcf120b | 4588 | |
1c777c5d ID |
4589 | /* |
4590 | * Neither the BIOS, ourselves or any other kernel | |
4591 | * expects the system to be in execlists mode on startup, | |
4592 | * so we need to reset the GPU back to legacy mode. And the only | |
4593 | * known way to disable logical contexts is through a GPU reset. | |
4594 | * | |
4595 | * So in order to leave the system in a known default configuration, | |
4596 | * always reset the GPU upon unload and suspend. Afterwards we then | |
4597 | * clean up the GEM state tracking, flushing off the requests and | |
4598 | * leaving the system in a known idle state. | |
4599 | * | |
4600 | * Note that is of the upmost importance that the GPU is idle and | |
4601 | * all stray writes are flushed *before* we dismantle the backing | |
4602 | * storage for the pinned objects. | |
4603 | * | |
4604 | * However, since we are uncertain that resetting the GPU on older | |
4605 | * machines is a good idea, we don't - just in case it leaves the | |
4606 | * machine in an unusable condition. | |
4607 | */ | |
24145517 | 4608 | i915_gem_sanitize(dev_priv); |
c998e8a0 | 4609 | goto out_rpm_put; |
1c777c5d | 4610 | |
c998e8a0 | 4611 | err_unlock: |
45c5f202 | 4612 | mutex_unlock(&dev->struct_mutex); |
c998e8a0 CW |
4613 | out_rpm_put: |
4614 | intel_runtime_pm_put(dev_priv); | |
45c5f202 | 4615 | return ret; |
673a394b EA |
4616 | } |
4617 | ||
bf9e8429 | 4618 | void i915_gem_resume(struct drm_i915_private *dev_priv) |
5ab57c70 | 4619 | { |
bf9e8429 | 4620 | struct drm_device *dev = &dev_priv->drm; |
5ab57c70 | 4621 | |
31ab49ab ID |
4622 | WARN_ON(dev_priv->gt.awake); |
4623 | ||
5ab57c70 | 4624 | mutex_lock(&dev->struct_mutex); |
275a991c | 4625 | i915_gem_restore_gtt_mappings(dev_priv); |
5ab57c70 CW |
4626 | |
4627 | /* As we didn't flush the kernel context before suspend, we cannot | |
4628 | * guarantee that the context image is complete. So let's just reset | |
4629 | * it and start again. | |
4630 | */ | |
821ed7df | 4631 | dev_priv->gt.resume(dev_priv); |
5ab57c70 CW |
4632 | |
4633 | mutex_unlock(&dev->struct_mutex); | |
4634 | } | |
4635 | ||
c6be607a | 4636 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) |
f691e2f4 | 4637 | { |
c6be607a | 4638 | if (INTEL_GEN(dev_priv) < 5 || |
f691e2f4 DV |
4639 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4640 | return; | |
4641 | ||
4642 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4643 | DISP_TILE_SURFACE_SWIZZLING); | |
4644 | ||
5db94019 | 4645 | if (IS_GEN5(dev_priv)) |
11782b02 DV |
4646 | return; |
4647 | ||
f691e2f4 | 4648 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
5db94019 | 4649 | if (IS_GEN6(dev_priv)) |
6b26c86d | 4650 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
5db94019 | 4651 | else if (IS_GEN7(dev_priv)) |
6b26c86d | 4652 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
5db94019 | 4653 | else if (IS_GEN8(dev_priv)) |
31a5336e | 4654 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
8782e26c BW |
4655 | else |
4656 | BUG(); | |
f691e2f4 | 4657 | } |
e21af88d | 4658 | |
50a0bc90 | 4659 | static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base) |
81e7f200 | 4660 | { |
81e7f200 VS |
4661 | I915_WRITE(RING_CTL(base), 0); |
4662 | I915_WRITE(RING_HEAD(base), 0); | |
4663 | I915_WRITE(RING_TAIL(base), 0); | |
4664 | I915_WRITE(RING_START(base), 0); | |
4665 | } | |
4666 | ||
50a0bc90 | 4667 | static void init_unused_rings(struct drm_i915_private *dev_priv) |
81e7f200 | 4668 | { |
50a0bc90 TU |
4669 | if (IS_I830(dev_priv)) { |
4670 | init_unused_ring(dev_priv, PRB1_BASE); | |
4671 | init_unused_ring(dev_priv, SRB0_BASE); | |
4672 | init_unused_ring(dev_priv, SRB1_BASE); | |
4673 | init_unused_ring(dev_priv, SRB2_BASE); | |
4674 | init_unused_ring(dev_priv, SRB3_BASE); | |
4675 | } else if (IS_GEN2(dev_priv)) { | |
4676 | init_unused_ring(dev_priv, SRB0_BASE); | |
4677 | init_unused_ring(dev_priv, SRB1_BASE); | |
4678 | } else if (IS_GEN3(dev_priv)) { | |
4679 | init_unused_ring(dev_priv, PRB1_BASE); | |
4680 | init_unused_ring(dev_priv, PRB2_BASE); | |
81e7f200 VS |
4681 | } |
4682 | } | |
4683 | ||
20a8a74a | 4684 | static int __i915_gem_restart_engines(void *data) |
4fc7c971 | 4685 | { |
20a8a74a | 4686 | struct drm_i915_private *i915 = data; |
e2f80391 | 4687 | struct intel_engine_cs *engine; |
3b3f1650 | 4688 | enum intel_engine_id id; |
20a8a74a CW |
4689 | int err; |
4690 | ||
4691 | for_each_engine(engine, i915, id) { | |
4692 | err = engine->init_hw(engine); | |
4693 | if (err) | |
4694 | return err; | |
4695 | } | |
4696 | ||
4697 | return 0; | |
4698 | } | |
4699 | ||
4700 | int i915_gem_init_hw(struct drm_i915_private *dev_priv) | |
4701 | { | |
d200cda6 | 4702 | int ret; |
4fc7c971 | 4703 | |
de867c20 CW |
4704 | dev_priv->gt.last_init_time = ktime_get(); |
4705 | ||
5e4f5189 CW |
4706 | /* Double layer security blanket, see i915_gem_init() */ |
4707 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4708 | ||
0031fb96 | 4709 | if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4710 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4711 | |
772c2a51 | 4712 | if (IS_HASWELL(dev_priv)) |
50a0bc90 | 4713 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ? |
0bf21347 | 4714 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
9435373e | 4715 | |
6e266956 | 4716 | if (HAS_PCH_NOP(dev_priv)) { |
fd6b8f43 | 4717 | if (IS_IVYBRIDGE(dev_priv)) { |
6ba844b0 DV |
4718 | u32 temp = I915_READ(GEN7_MSG_CTL); |
4719 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4720 | I915_WRITE(GEN7_MSG_CTL, temp); | |
c6be607a | 4721 | } else if (INTEL_GEN(dev_priv) >= 7) { |
6ba844b0 DV |
4722 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
4723 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4724 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4725 | } | |
88a2b2a3 BW |
4726 | } |
4727 | ||
c6be607a | 4728 | i915_gem_init_swizzling(dev_priv); |
4fc7c971 | 4729 | |
d5abdfda DV |
4730 | /* |
4731 | * At least 830 can leave some of the unused rings | |
4732 | * "active" (ie. head != tail) after resume which | |
4733 | * will prevent c3 entry. Makes sure all unused rings | |
4734 | * are totally idle. | |
4735 | */ | |
50a0bc90 | 4736 | init_unused_rings(dev_priv); |
d5abdfda | 4737 | |
ed54c1a1 | 4738 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4739 | |
c6be607a | 4740 | ret = i915_ppgtt_init_hw(dev_priv); |
4ad2fd88 JH |
4741 | if (ret) { |
4742 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4743 | goto out; | |
4744 | } | |
4745 | ||
4746 | /* Need to do basic initialisation of all rings first: */ | |
20a8a74a CW |
4747 | ret = __i915_gem_restart_engines(dev_priv); |
4748 | if (ret) | |
4749 | goto out; | |
99433931 | 4750 | |
bf9e8429 | 4751 | intel_mocs_init_l3cc_table(dev_priv); |
0ccdacf6 | 4752 | |
b8991403 OM |
4753 | /* We can't enable contexts until all firmware is loaded */ |
4754 | ret = intel_uc_init_hw(dev_priv); | |
4755 | if (ret) | |
4756 | goto out; | |
33a732f4 | 4757 | |
5e4f5189 CW |
4758 | out: |
4759 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4760 | return ret; |
8187a2b7 ZN |
4761 | } |
4762 | ||
39df9190 CW |
4763 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4764 | { | |
4765 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4766 | return false; | |
4767 | ||
4768 | /* TODO: make semaphores and Execlists play nicely together */ | |
4769 | if (i915.enable_execlists) | |
4770 | return false; | |
4771 | ||
4772 | if (value >= 0) | |
4773 | return value; | |
4774 | ||
39df9190 | 4775 | /* Enable semaphores on SNB when IO remapping is off */ |
80debff8 | 4776 | if (IS_GEN6(dev_priv) && intel_vtd_active()) |
39df9190 | 4777 | return false; |
39df9190 CW |
4778 | |
4779 | return true; | |
4780 | } | |
4781 | ||
bf9e8429 | 4782 | int i915_gem_init(struct drm_i915_private *dev_priv) |
1070a42b | 4783 | { |
1070a42b CW |
4784 | int ret; |
4785 | ||
bf9e8429 | 4786 | mutex_lock(&dev_priv->drm.struct_mutex); |
d62b4892 | 4787 | |
94312828 | 4788 | dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1); |
57822dc6 | 4789 | |
a83014d3 | 4790 | if (!i915.enable_execlists) { |
821ed7df | 4791 | dev_priv->gt.resume = intel_legacy_submission_resume; |
7e37f889 | 4792 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
454afebd | 4793 | } else { |
821ed7df | 4794 | dev_priv->gt.resume = intel_lr_context_resume; |
117897f4 | 4795 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
a83014d3 OM |
4796 | } |
4797 | ||
5e4f5189 CW |
4798 | /* This is just a security blanket to placate dragons. |
4799 | * On some systems, we very sporadically observe that the first TLBs | |
4800 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4801 | * we hold the forcewake during initialisation these problems | |
4802 | * just magically go away. | |
4803 | */ | |
4804 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4805 | ||
8a2421bd CW |
4806 | ret = i915_gem_init_userptr(dev_priv); |
4807 | if (ret) | |
4808 | goto out_unlock; | |
f6b9d5ca CW |
4809 | |
4810 | ret = i915_gem_init_ggtt(dev_priv); | |
4811 | if (ret) | |
4812 | goto out_unlock; | |
d62b4892 | 4813 | |
bf9e8429 | 4814 | ret = i915_gem_context_init(dev_priv); |
7bcc3777 JN |
4815 | if (ret) |
4816 | goto out_unlock; | |
2fa48d8d | 4817 | |
bf9e8429 | 4818 | ret = intel_engines_init(dev_priv); |
35a57ffb | 4819 | if (ret) |
7bcc3777 | 4820 | goto out_unlock; |
2fa48d8d | 4821 | |
bf9e8429 | 4822 | ret = i915_gem_init_hw(dev_priv); |
60990320 | 4823 | if (ret == -EIO) { |
7e21d648 | 4824 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4825 | * wedged. But we only want to do this where the GPU is angry, |
4826 | * for all other failure, such as an allocation failure, bail. | |
4827 | */ | |
4828 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
821ed7df | 4829 | i915_gem_set_wedged(dev_priv); |
60990320 | 4830 | ret = 0; |
1070a42b | 4831 | } |
7bcc3777 JN |
4832 | |
4833 | out_unlock: | |
5e4f5189 | 4834 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
bf9e8429 | 4835 | mutex_unlock(&dev_priv->drm.struct_mutex); |
1070a42b | 4836 | |
60990320 | 4837 | return ret; |
1070a42b CW |
4838 | } |
4839 | ||
24145517 CW |
4840 | void i915_gem_init_mmio(struct drm_i915_private *i915) |
4841 | { | |
4842 | i915_gem_sanitize(i915); | |
4843 | } | |
4844 | ||
8187a2b7 | 4845 | void |
cb15d9f8 | 4846 | i915_gem_cleanup_engines(struct drm_i915_private *dev_priv) |
8187a2b7 | 4847 | { |
e2f80391 | 4848 | struct intel_engine_cs *engine; |
3b3f1650 | 4849 | enum intel_engine_id id; |
8187a2b7 | 4850 | |
3b3f1650 | 4851 | for_each_engine(engine, dev_priv, id) |
117897f4 | 4852 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4853 | } |
4854 | ||
40ae4e16 ID |
4855 | void |
4856 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4857 | { | |
49ef5294 | 4858 | int i; |
40ae4e16 ID |
4859 | |
4860 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4861 | !IS_CHERRYVIEW(dev_priv)) | |
4862 | dev_priv->num_fence_regs = 32; | |
73f67aa8 JN |
4863 | else if (INTEL_INFO(dev_priv)->gen >= 4 || |
4864 | IS_I945G(dev_priv) || IS_I945GM(dev_priv) || | |
4865 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) | |
40ae4e16 ID |
4866 | dev_priv->num_fence_regs = 16; |
4867 | else | |
4868 | dev_priv->num_fence_regs = 8; | |
4869 | ||
c033666a | 4870 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4871 | dev_priv->num_fence_regs = |
4872 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4873 | ||
4874 | /* Initialize fence registers to zero */ | |
49ef5294 CW |
4875 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
4876 | struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i]; | |
4877 | ||
4878 | fence->i915 = dev_priv; | |
4879 | fence->id = i; | |
4880 | list_add_tail(&fence->link, &dev_priv->mm.fence_list); | |
4881 | } | |
4362f4f6 | 4882 | i915_gem_restore_fences(dev_priv); |
40ae4e16 | 4883 | |
4362f4f6 | 4884 | i915_gem_detect_bit_6_swizzle(dev_priv); |
40ae4e16 ID |
4885 | } |
4886 | ||
73cb9701 | 4887 | int |
cb15d9f8 | 4888 | i915_gem_load_init(struct drm_i915_private *dev_priv) |
673a394b | 4889 | { |
a933568e | 4890 | int err = -ENOMEM; |
42dcedd4 | 4891 | |
a933568e TU |
4892 | dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN); |
4893 | if (!dev_priv->objects) | |
73cb9701 | 4894 | goto err_out; |
73cb9701 | 4895 | |
a933568e TU |
4896 | dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN); |
4897 | if (!dev_priv->vmas) | |
73cb9701 | 4898 | goto err_objects; |
73cb9701 | 4899 | |
a933568e TU |
4900 | dev_priv->requests = KMEM_CACHE(drm_i915_gem_request, |
4901 | SLAB_HWCACHE_ALIGN | | |
4902 | SLAB_RECLAIM_ACCOUNT | | |
5f0d5a3a | 4903 | SLAB_TYPESAFE_BY_RCU); |
a933568e | 4904 | if (!dev_priv->requests) |
73cb9701 | 4905 | goto err_vmas; |
73cb9701 | 4906 | |
52e54209 CW |
4907 | dev_priv->dependencies = KMEM_CACHE(i915_dependency, |
4908 | SLAB_HWCACHE_ALIGN | | |
4909 | SLAB_RECLAIM_ACCOUNT); | |
4910 | if (!dev_priv->dependencies) | |
4911 | goto err_requests; | |
4912 | ||
c5cf9a91 CW |
4913 | dev_priv->priorities = KMEM_CACHE(i915_priolist, SLAB_HWCACHE_ALIGN); |
4914 | if (!dev_priv->priorities) | |
4915 | goto err_dependencies; | |
4916 | ||
73cb9701 CW |
4917 | mutex_lock(&dev_priv->drm.struct_mutex); |
4918 | INIT_LIST_HEAD(&dev_priv->gt.timelines); | |
bb89485e | 4919 | err = i915_gem_timeline_init__global(dev_priv); |
73cb9701 CW |
4920 | mutex_unlock(&dev_priv->drm.struct_mutex); |
4921 | if (err) | |
c5cf9a91 | 4922 | goto err_priorities; |
673a394b | 4923 | |
a33afea5 | 4924 | INIT_LIST_HEAD(&dev_priv->context_list); |
fbbd37b3 CW |
4925 | INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work); |
4926 | init_llist_head(&dev_priv->mm.free_list); | |
6c085a72 CW |
4927 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4928 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4929 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
275f039d | 4930 | INIT_LIST_HEAD(&dev_priv->mm.userfault_list); |
67d97da3 | 4931 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4932 | i915_gem_retire_work_handler); |
67d97da3 | 4933 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4934 | i915_gem_idle_work_handler); |
1f15b76f | 4935 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4936 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4937 | |
6b95a207 | 4938 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4939 | |
6f633402 JL |
4940 | atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); |
4941 | ||
b5add959 | 4942 | spin_lock_init(&dev_priv->fb_tracking.lock); |
73cb9701 CW |
4943 | |
4944 | return 0; | |
4945 | ||
c5cf9a91 CW |
4946 | err_priorities: |
4947 | kmem_cache_destroy(dev_priv->priorities); | |
52e54209 CW |
4948 | err_dependencies: |
4949 | kmem_cache_destroy(dev_priv->dependencies); | |
73cb9701 CW |
4950 | err_requests: |
4951 | kmem_cache_destroy(dev_priv->requests); | |
4952 | err_vmas: | |
4953 | kmem_cache_destroy(dev_priv->vmas); | |
4954 | err_objects: | |
4955 | kmem_cache_destroy(dev_priv->objects); | |
4956 | err_out: | |
4957 | return err; | |
673a394b | 4958 | } |
71acb5eb | 4959 | |
cb15d9f8 | 4960 | void i915_gem_load_cleanup(struct drm_i915_private *dev_priv) |
d64aa096 | 4961 | { |
c4d4c1c6 | 4962 | i915_gem_drain_freed_objects(dev_priv); |
7d5d59e5 | 4963 | WARN_ON(!llist_empty(&dev_priv->mm.free_list)); |
c4d4c1c6 | 4964 | WARN_ON(dev_priv->mm.object_count); |
7d5d59e5 | 4965 | |
ea84aa77 MA |
4966 | mutex_lock(&dev_priv->drm.struct_mutex); |
4967 | i915_gem_timeline_fini(&dev_priv->gt.global_timeline); | |
4968 | WARN_ON(!list_empty(&dev_priv->gt.timelines)); | |
4969 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4970 | ||
c5cf9a91 | 4971 | kmem_cache_destroy(dev_priv->priorities); |
52e54209 | 4972 | kmem_cache_destroy(dev_priv->dependencies); |
d64aa096 ID |
4973 | kmem_cache_destroy(dev_priv->requests); |
4974 | kmem_cache_destroy(dev_priv->vmas); | |
4975 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
4976 | |
4977 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
4978 | rcu_barrier(); | |
d64aa096 ID |
4979 | } |
4980 | ||
6a800eab CW |
4981 | int i915_gem_freeze(struct drm_i915_private *dev_priv) |
4982 | { | |
d0aa301a CW |
4983 | /* Discard all purgeable objects, let userspace recover those as |
4984 | * required after resuming. | |
4985 | */ | |
6a800eab | 4986 | i915_gem_shrink_all(dev_priv); |
6a800eab | 4987 | |
6a800eab CW |
4988 | return 0; |
4989 | } | |
4990 | ||
461fb99c CW |
4991 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4992 | { | |
4993 | struct drm_i915_gem_object *obj; | |
7aab2d53 CW |
4994 | struct list_head *phases[] = { |
4995 | &dev_priv->mm.unbound_list, | |
4996 | &dev_priv->mm.bound_list, | |
4997 | NULL | |
4998 | }, **p; | |
461fb99c CW |
4999 | |
5000 | /* Called just before we write the hibernation image. | |
5001 | * | |
5002 | * We need to update the domain tracking to reflect that the CPU | |
5003 | * will be accessing all the pages to create and restore from the | |
5004 | * hibernation, and so upon restoration those pages will be in the | |
5005 | * CPU domain. | |
5006 | * | |
5007 | * To make sure the hibernation image contains the latest state, | |
5008 | * we update that state just before writing out the image. | |
7aab2d53 CW |
5009 | * |
5010 | * To try and reduce the hibernation image, we manually shrink | |
d0aa301a | 5011 | * the objects as well, see i915_gem_freeze() |
461fb99c CW |
5012 | */ |
5013 | ||
6a800eab | 5014 | i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND); |
17b93c40 | 5015 | i915_gem_drain_freed_objects(dev_priv); |
461fb99c | 5016 | |
d0aa301a | 5017 | mutex_lock(&dev_priv->drm.struct_mutex); |
7aab2d53 | 5018 | for (p = phases; *p; p++) { |
e27ab73d CW |
5019 | list_for_each_entry(obj, *p, global_link) |
5020 | __start_cpu_write(obj); | |
461fb99c | 5021 | } |
6a800eab | 5022 | mutex_unlock(&dev_priv->drm.struct_mutex); |
461fb99c CW |
5023 | |
5024 | return 0; | |
5025 | } | |
5026 | ||
f787a5f5 | 5027 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5028 | { |
f787a5f5 | 5029 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 5030 | struct drm_i915_gem_request *request; |
b962442e EA |
5031 | |
5032 | /* Clean up our request list when the client is going away, so that | |
5033 | * later retire_requests won't dereference our soon-to-be-gone | |
5034 | * file_priv. | |
5035 | */ | |
1c25595f | 5036 | spin_lock(&file_priv->mm.lock); |
c8659efa | 5037 | list_for_each_entry(request, &file_priv->mm.request_list, client_link) |
f787a5f5 | 5038 | request->file_priv = NULL; |
1c25595f | 5039 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 5040 | |
2e1b8730 | 5041 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 5042 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 5043 | list_del(&file_priv->rps.link); |
8d3afd7d | 5044 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 5045 | } |
b29c19b6 CW |
5046 | } |
5047 | ||
5048 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5049 | { | |
5050 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5051 | int ret; |
b29c19b6 | 5052 | |
c4c29d7b | 5053 | DRM_DEBUG("\n"); |
b29c19b6 CW |
5054 | |
5055 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5056 | if (!file_priv) | |
5057 | return -ENOMEM; | |
5058 | ||
5059 | file->driver_priv = file_priv; | |
f19ec8cb | 5060 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 5061 | file_priv->file = file; |
2e1b8730 | 5062 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
5063 | |
5064 | spin_lock_init(&file_priv->mm.lock); | |
5065 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 5066 | |
c80ff16e | 5067 | file_priv->bsd_engine = -1; |
de1add36 | 5068 | |
e422b888 BW |
5069 | ret = i915_gem_context_open(dev, file); |
5070 | if (ret) | |
5071 | kfree(file_priv); | |
b29c19b6 | 5072 | |
e422b888 | 5073 | return ret; |
b29c19b6 CW |
5074 | } |
5075 | ||
b680c37a DV |
5076 | /** |
5077 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
5078 | * @old: current GEM buffer for the frontbuffer slots |
5079 | * @new: new GEM buffer for the frontbuffer slots | |
5080 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
5081 | * |
5082 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5083 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5084 | */ | |
a071fa00 DV |
5085 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5086 | struct drm_i915_gem_object *new, | |
5087 | unsigned frontbuffer_bits) | |
5088 | { | |
faf5bf0a CW |
5089 | /* Control of individual bits within the mask are guarded by |
5090 | * the owning plane->mutex, i.e. we can never see concurrent | |
5091 | * manipulation of individual bits. But since the bitfield as a whole | |
5092 | * is updated using RMW, we need to use atomics in order to update | |
5093 | * the bits. | |
5094 | */ | |
5095 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
5096 | sizeof(atomic_t) * BITS_PER_BYTE); | |
5097 | ||
a071fa00 | 5098 | if (old) { |
faf5bf0a CW |
5099 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
5100 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
5101 | } |
5102 | ||
5103 | if (new) { | |
faf5bf0a CW |
5104 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
5105 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
5106 | } |
5107 | } | |
5108 | ||
ea70299d DG |
5109 | /* Allocate a new GEM object and fill it with the supplied data */ |
5110 | struct drm_i915_gem_object * | |
12d79d78 | 5111 | i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, |
ea70299d DG |
5112 | const void *data, size_t size) |
5113 | { | |
5114 | struct drm_i915_gem_object *obj; | |
be062fa4 CW |
5115 | struct file *file; |
5116 | size_t offset; | |
5117 | int err; | |
ea70299d | 5118 | |
12d79d78 | 5119 | obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE)); |
fe3db79b | 5120 | if (IS_ERR(obj)) |
ea70299d DG |
5121 | return obj; |
5122 | ||
ce8ff099 | 5123 | GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU); |
ea70299d | 5124 | |
be062fa4 CW |
5125 | file = obj->base.filp; |
5126 | offset = 0; | |
5127 | do { | |
5128 | unsigned int len = min_t(typeof(size), size, PAGE_SIZE); | |
5129 | struct page *page; | |
5130 | void *pgdata, *vaddr; | |
ea70299d | 5131 | |
be062fa4 CW |
5132 | err = pagecache_write_begin(file, file->f_mapping, |
5133 | offset, len, 0, | |
5134 | &page, &pgdata); | |
5135 | if (err < 0) | |
5136 | goto fail; | |
ea70299d | 5137 | |
be062fa4 CW |
5138 | vaddr = kmap(page); |
5139 | memcpy(vaddr, data, len); | |
5140 | kunmap(page); | |
5141 | ||
5142 | err = pagecache_write_end(file, file->f_mapping, | |
5143 | offset, len, len, | |
5144 | page, pgdata); | |
5145 | if (err < 0) | |
5146 | goto fail; | |
5147 | ||
5148 | size -= len; | |
5149 | data += len; | |
5150 | offset += len; | |
5151 | } while (size); | |
ea70299d DG |
5152 | |
5153 | return obj; | |
5154 | ||
5155 | fail: | |
f8c417cd | 5156 | i915_gem_object_put(obj); |
be062fa4 | 5157 | return ERR_PTR(err); |
ea70299d | 5158 | } |
96d77634 CW |
5159 | |
5160 | struct scatterlist * | |
5161 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
5162 | unsigned int n, | |
5163 | unsigned int *offset) | |
5164 | { | |
a4f5ea64 | 5165 | struct i915_gem_object_page_iter *iter = &obj->mm.get_page; |
96d77634 CW |
5166 | struct scatterlist *sg; |
5167 | unsigned int idx, count; | |
5168 | ||
5169 | might_sleep(); | |
5170 | GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT); | |
a4f5ea64 | 5171 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
96d77634 CW |
5172 | |
5173 | /* As we iterate forward through the sg, we record each entry in a | |
5174 | * radixtree for quick repeated (backwards) lookups. If we have seen | |
5175 | * this index previously, we will have an entry for it. | |
5176 | * | |
5177 | * Initial lookup is O(N), but this is amortized to O(1) for | |
5178 | * sequential page access (where each new request is consecutive | |
5179 | * to the previous one). Repeated lookups are O(lg(obj->base.size)), | |
5180 | * i.e. O(1) with a large constant! | |
5181 | */ | |
5182 | if (n < READ_ONCE(iter->sg_idx)) | |
5183 | goto lookup; | |
5184 | ||
5185 | mutex_lock(&iter->lock); | |
5186 | ||
5187 | /* We prefer to reuse the last sg so that repeated lookup of this | |
5188 | * (or the subsequent) sg are fast - comparing against the last | |
5189 | * sg is faster than going through the radixtree. | |
5190 | */ | |
5191 | ||
5192 | sg = iter->sg_pos; | |
5193 | idx = iter->sg_idx; | |
5194 | count = __sg_page_count(sg); | |
5195 | ||
5196 | while (idx + count <= n) { | |
5197 | unsigned long exception, i; | |
5198 | int ret; | |
5199 | ||
5200 | /* If we cannot allocate and insert this entry, or the | |
5201 | * individual pages from this range, cancel updating the | |
5202 | * sg_idx so that on this lookup we are forced to linearly | |
5203 | * scan onwards, but on future lookups we will try the | |
5204 | * insertion again (in which case we need to be careful of | |
5205 | * the error return reporting that we have already inserted | |
5206 | * this index). | |
5207 | */ | |
5208 | ret = radix_tree_insert(&iter->radix, idx, sg); | |
5209 | if (ret && ret != -EEXIST) | |
5210 | goto scan; | |
5211 | ||
5212 | exception = | |
5213 | RADIX_TREE_EXCEPTIONAL_ENTRY | | |
5214 | idx << RADIX_TREE_EXCEPTIONAL_SHIFT; | |
5215 | for (i = 1; i < count; i++) { | |
5216 | ret = radix_tree_insert(&iter->radix, idx + i, | |
5217 | (void *)exception); | |
5218 | if (ret && ret != -EEXIST) | |
5219 | goto scan; | |
5220 | } | |
5221 | ||
5222 | idx += count; | |
5223 | sg = ____sg_next(sg); | |
5224 | count = __sg_page_count(sg); | |
5225 | } | |
5226 | ||
5227 | scan: | |
5228 | iter->sg_pos = sg; | |
5229 | iter->sg_idx = idx; | |
5230 | ||
5231 | mutex_unlock(&iter->lock); | |
5232 | ||
5233 | if (unlikely(n < idx)) /* insertion completed by another thread */ | |
5234 | goto lookup; | |
5235 | ||
5236 | /* In case we failed to insert the entry into the radixtree, we need | |
5237 | * to look beyond the current sg. | |
5238 | */ | |
5239 | while (idx + count <= n) { | |
5240 | idx += count; | |
5241 | sg = ____sg_next(sg); | |
5242 | count = __sg_page_count(sg); | |
5243 | } | |
5244 | ||
5245 | *offset = n - idx; | |
5246 | return sg; | |
5247 | ||
5248 | lookup: | |
5249 | rcu_read_lock(); | |
5250 | ||
5251 | sg = radix_tree_lookup(&iter->radix, n); | |
5252 | GEM_BUG_ON(!sg); | |
5253 | ||
5254 | /* If this index is in the middle of multi-page sg entry, | |
5255 | * the radixtree will contain an exceptional entry that points | |
5256 | * to the start of that range. We will return the pointer to | |
5257 | * the base page and the offset of this page within the | |
5258 | * sg entry's range. | |
5259 | */ | |
5260 | *offset = 0; | |
5261 | if (unlikely(radix_tree_exception(sg))) { | |
5262 | unsigned long base = | |
5263 | (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT; | |
5264 | ||
5265 | sg = radix_tree_lookup(&iter->radix, base); | |
5266 | GEM_BUG_ON(!sg); | |
5267 | ||
5268 | *offset = n - base; | |
5269 | } | |
5270 | ||
5271 | rcu_read_unlock(); | |
5272 | ||
5273 | return sg; | |
5274 | } | |
5275 | ||
5276 | struct page * | |
5277 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n) | |
5278 | { | |
5279 | struct scatterlist *sg; | |
5280 | unsigned int offset; | |
5281 | ||
5282 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); | |
5283 | ||
5284 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
5285 | return nth_page(sg_page(sg), offset); | |
5286 | } | |
5287 | ||
5288 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ | |
5289 | struct page * | |
5290 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
5291 | unsigned int n) | |
5292 | { | |
5293 | struct page *page; | |
5294 | ||
5295 | page = i915_gem_object_get_page(obj, n); | |
a4f5ea64 | 5296 | if (!obj->mm.dirty) |
96d77634 CW |
5297 | set_page_dirty(page); |
5298 | ||
5299 | return page; | |
5300 | } | |
5301 | ||
5302 | dma_addr_t | |
5303 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
5304 | unsigned long n) | |
5305 | { | |
5306 | struct scatterlist *sg; | |
5307 | unsigned int offset; | |
5308 | ||
5309 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
5310 | return sg_dma_address(sg) + (offset << PAGE_SHIFT); | |
5311 | } | |
935a2f77 CW |
5312 | |
5313 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
5314 | #include "selftests/scatterlist.c" | |
66d9cb5d | 5315 | #include "selftests/mock_gem_device.c" |
44653988 | 5316 | #include "selftests/huge_gem_object.c" |
8335fd65 | 5317 | #include "selftests/i915_gem_object.c" |
17059450 | 5318 | #include "selftests/i915_gem_coherency.c" |
935a2f77 | 5319 | #endif |