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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
eb82289a | 32 | #include "i915_vgpu.h" |
1c5d22f7 | 33 | #include "i915_trace.h" |
652c393a | 34 | #include "intel_drv.h" |
5d723d7a | 35 | #include "intel_frontbuffer.h" |
0ccdacf6 | 36 | #include "intel_mocs.h" |
6b5e90f5 | 37 | #include <linux/dma-fence-array.h> |
c13d87ea | 38 | #include <linux/reservation.h> |
5949eac4 | 39 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
20e4933c | 41 | #include <linux/stop_machine.h> |
673a394b | 42 | #include <linux/swap.h> |
79e53945 | 43 | #include <linux/pci.h> |
1286ff73 | 44 | #include <linux/dma-buf.h> |
673a394b | 45 | |
fbbd37b3 | 46 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915); |
05394f39 | 47 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 48 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
61050808 | 49 | |
c76ce038 CW |
50 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
51 | enum i915_cache_level level) | |
52 | { | |
0031fb96 | 53 | return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE; |
c76ce038 CW |
54 | } |
55 | ||
2c22569b CW |
56 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
57 | { | |
b50a5371 AS |
58 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
59 | return false; | |
60 | ||
2c22569b CW |
61 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
62 | return true; | |
63 | ||
64 | return obj->pin_display; | |
65 | } | |
66 | ||
4f1959ee | 67 | static int |
bb6dc8d9 | 68 | insert_mappable_node(struct i915_ggtt *ggtt, |
4f1959ee AS |
69 | struct drm_mm_node *node, u32 size) |
70 | { | |
71 | memset(node, 0, sizeof(*node)); | |
bb6dc8d9 | 72 | return drm_mm_insert_node_in_range_generic(&ggtt->base.mm, node, |
85fd4f58 CW |
73 | size, 0, |
74 | I915_COLOR_UNEVICTABLE, | |
bb6dc8d9 | 75 | 0, ggtt->mappable_end, |
4f1959ee AS |
76 | DRM_MM_SEARCH_DEFAULT, |
77 | DRM_MM_CREATE_DEFAULT); | |
78 | } | |
79 | ||
80 | static void | |
81 | remove_mappable_node(struct drm_mm_node *node) | |
82 | { | |
83 | drm_mm_remove_node(node); | |
84 | } | |
85 | ||
73aa808f CW |
86 | /* some bookkeeping */ |
87 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 88 | u64 size) |
73aa808f | 89 | { |
c20e8355 | 90 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
91 | dev_priv->mm.object_count++; |
92 | dev_priv->mm.object_memory += size; | |
c20e8355 | 93 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
94 | } |
95 | ||
96 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 97 | u64 size) |
73aa808f | 98 | { |
c20e8355 | 99 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
100 | dev_priv->mm.object_count--; |
101 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 102 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
103 | } |
104 | ||
21dd3734 | 105 | static int |
33196ded | 106 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 107 | { |
30dbf0c0 CW |
108 | int ret; |
109 | ||
4c7d62c6 CW |
110 | might_sleep(); |
111 | ||
d98c52cf | 112 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
113 | return 0; |
114 | ||
0a6759c6 DV |
115 | /* |
116 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
117 | * userspace. If it takes that long something really bad is going on and | |
118 | * we should simply try to bail out and fail as gracefully as possible. | |
119 | */ | |
1f83fee0 | 120 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 121 | !i915_reset_in_progress(error), |
b52992c0 | 122 | I915_RESET_TIMEOUT); |
0a6759c6 DV |
123 | if (ret == 0) { |
124 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
125 | return -EIO; | |
126 | } else if (ret < 0) { | |
30dbf0c0 | 127 | return ret; |
d98c52cf CW |
128 | } else { |
129 | return 0; | |
0a6759c6 | 130 | } |
30dbf0c0 CW |
131 | } |
132 | ||
54cf91dc | 133 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 134 | { |
fac5e23e | 135 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
136 | int ret; |
137 | ||
33196ded | 138 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
139 | if (ret) |
140 | return ret; | |
141 | ||
142 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
143 | if (ret) | |
144 | return ret; | |
145 | ||
76c1dec1 CW |
146 | return 0; |
147 | } | |
30dbf0c0 | 148 | |
5a125c3c EA |
149 | int |
150 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 151 | struct drm_file *file) |
5a125c3c | 152 | { |
72e96d64 | 153 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 154 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 155 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 156 | struct i915_vma *vma; |
6299f992 | 157 | size_t pinned; |
5a125c3c | 158 | |
6299f992 | 159 | pinned = 0; |
73aa808f | 160 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 161 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 162 | if (i915_vma_is_pinned(vma)) |
ca1543be | 163 | pinned += vma->node.size; |
1c7f4bca | 164 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 165 | if (i915_vma_is_pinned(vma)) |
ca1543be | 166 | pinned += vma->node.size; |
73aa808f | 167 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 168 | |
72e96d64 | 169 | args->aper_size = ggtt->base.total; |
0206e353 | 170 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 171 | |
5a125c3c EA |
172 | return 0; |
173 | } | |
174 | ||
03ac84f1 | 175 | static struct sg_table * |
6a2c4232 | 176 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
00731155 | 177 | { |
93c76a3d | 178 | struct address_space *mapping = obj->base.filp->f_mapping; |
dbb4351b | 179 | drm_dma_handle_t *phys; |
6a2c4232 CW |
180 | struct sg_table *st; |
181 | struct scatterlist *sg; | |
dbb4351b | 182 | char *vaddr; |
6a2c4232 | 183 | int i; |
00731155 | 184 | |
6a2c4232 | 185 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
03ac84f1 | 186 | return ERR_PTR(-EINVAL); |
6a2c4232 | 187 | |
dbb4351b CW |
188 | /* Always aligning to the object size, allows a single allocation |
189 | * to handle all possible callers, and given typical object sizes, | |
190 | * the alignment of the buddy allocation will naturally match. | |
191 | */ | |
192 | phys = drm_pci_alloc(obj->base.dev, | |
193 | obj->base.size, | |
194 | roundup_pow_of_two(obj->base.size)); | |
195 | if (!phys) | |
196 | return ERR_PTR(-ENOMEM); | |
197 | ||
198 | vaddr = phys->vaddr; | |
6a2c4232 CW |
199 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
200 | struct page *page; | |
201 | char *src; | |
202 | ||
203 | page = shmem_read_mapping_page(mapping, i); | |
dbb4351b CW |
204 | if (IS_ERR(page)) { |
205 | st = ERR_CAST(page); | |
206 | goto err_phys; | |
207 | } | |
6a2c4232 CW |
208 | |
209 | src = kmap_atomic(page); | |
210 | memcpy(vaddr, src, PAGE_SIZE); | |
211 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
212 | kunmap_atomic(src); | |
213 | ||
09cbfeaf | 214 | put_page(page); |
6a2c4232 CW |
215 | vaddr += PAGE_SIZE; |
216 | } | |
217 | ||
c033666a | 218 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
219 | |
220 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
dbb4351b CW |
221 | if (!st) { |
222 | st = ERR_PTR(-ENOMEM); | |
223 | goto err_phys; | |
224 | } | |
6a2c4232 CW |
225 | |
226 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
227 | kfree(st); | |
dbb4351b CW |
228 | st = ERR_PTR(-ENOMEM); |
229 | goto err_phys; | |
6a2c4232 CW |
230 | } |
231 | ||
232 | sg = st->sgl; | |
233 | sg->offset = 0; | |
234 | sg->length = obj->base.size; | |
00731155 | 235 | |
dbb4351b | 236 | sg_dma_address(sg) = phys->busaddr; |
6a2c4232 CW |
237 | sg_dma_len(sg) = obj->base.size; |
238 | ||
dbb4351b CW |
239 | obj->phys_handle = phys; |
240 | return st; | |
241 | ||
242 | err_phys: | |
243 | drm_pci_free(obj->base.dev, phys); | |
03ac84f1 | 244 | return st; |
6a2c4232 CW |
245 | } |
246 | ||
247 | static void | |
2b3c8317 CW |
248 | __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, |
249 | struct sg_table *pages) | |
6a2c4232 | 250 | { |
a4f5ea64 | 251 | GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED); |
00731155 | 252 | |
a4f5ea64 CW |
253 | if (obj->mm.madv == I915_MADV_DONTNEED) |
254 | obj->mm.dirty = false; | |
6a2c4232 | 255 | |
05c34837 CW |
256 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 && |
257 | !cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
2b3c8317 | 258 | drm_clflush_sg(pages); |
03ac84f1 CW |
259 | |
260 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
261 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
262 | } | |
263 | ||
264 | static void | |
265 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj, | |
266 | struct sg_table *pages) | |
267 | { | |
2b3c8317 | 268 | __i915_gem_object_release_shmem(obj, pages); |
03ac84f1 | 269 | |
a4f5ea64 | 270 | if (obj->mm.dirty) { |
93c76a3d | 271 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 | 272 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
273 | int i; |
274 | ||
275 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
276 | struct page *page; |
277 | char *dst; | |
278 | ||
279 | page = shmem_read_mapping_page(mapping, i); | |
280 | if (IS_ERR(page)) | |
281 | continue; | |
282 | ||
283 | dst = kmap_atomic(page); | |
284 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
285 | memcpy(dst, vaddr, PAGE_SIZE); | |
286 | kunmap_atomic(dst); | |
287 | ||
288 | set_page_dirty(page); | |
a4f5ea64 | 289 | if (obj->mm.madv == I915_MADV_WILLNEED) |
00731155 | 290 | mark_page_accessed(page); |
09cbfeaf | 291 | put_page(page); |
00731155 CW |
292 | vaddr += PAGE_SIZE; |
293 | } | |
a4f5ea64 | 294 | obj->mm.dirty = false; |
00731155 CW |
295 | } |
296 | ||
03ac84f1 CW |
297 | sg_free_table(pages); |
298 | kfree(pages); | |
dbb4351b CW |
299 | |
300 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
6a2c4232 CW |
301 | } |
302 | ||
303 | static void | |
304 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
305 | { | |
a4f5ea64 | 306 | i915_gem_object_unpin_pages(obj); |
6a2c4232 CW |
307 | } |
308 | ||
309 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
310 | .get_pages = i915_gem_object_get_pages_phys, | |
311 | .put_pages = i915_gem_object_put_pages_phys, | |
312 | .release = i915_gem_object_release_phys, | |
313 | }; | |
314 | ||
35a9611c | 315 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
aa653a68 CW |
316 | { |
317 | struct i915_vma *vma; | |
318 | LIST_HEAD(still_in_list); | |
02bef8f9 CW |
319 | int ret; |
320 | ||
321 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
aa653a68 | 322 | |
02bef8f9 CW |
323 | /* Closed vma are removed from the obj->vma_list - but they may |
324 | * still have an active binding on the object. To remove those we | |
325 | * must wait for all rendering to complete to the object (as unbinding | |
326 | * must anyway), and retire the requests. | |
aa653a68 | 327 | */ |
e95433c7 CW |
328 | ret = i915_gem_object_wait(obj, |
329 | I915_WAIT_INTERRUPTIBLE | | |
330 | I915_WAIT_LOCKED | | |
331 | I915_WAIT_ALL, | |
332 | MAX_SCHEDULE_TIMEOUT, | |
333 | NULL); | |
02bef8f9 CW |
334 | if (ret) |
335 | return ret; | |
336 | ||
337 | i915_gem_retire_requests(to_i915(obj->base.dev)); | |
338 | ||
aa653a68 CW |
339 | while ((vma = list_first_entry_or_null(&obj->vma_list, |
340 | struct i915_vma, | |
341 | obj_link))) { | |
342 | list_move_tail(&vma->obj_link, &still_in_list); | |
343 | ret = i915_vma_unbind(vma); | |
344 | if (ret) | |
345 | break; | |
346 | } | |
347 | list_splice(&still_in_list, &obj->vma_list); | |
348 | ||
349 | return ret; | |
350 | } | |
351 | ||
e95433c7 CW |
352 | static long |
353 | i915_gem_object_wait_fence(struct dma_fence *fence, | |
354 | unsigned int flags, | |
355 | long timeout, | |
356 | struct intel_rps_client *rps) | |
00e60f26 | 357 | { |
e95433c7 | 358 | struct drm_i915_gem_request *rq; |
00e60f26 | 359 | |
e95433c7 | 360 | BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1); |
00e60f26 | 361 | |
e95433c7 CW |
362 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
363 | return timeout; | |
364 | ||
365 | if (!dma_fence_is_i915(fence)) | |
366 | return dma_fence_wait_timeout(fence, | |
367 | flags & I915_WAIT_INTERRUPTIBLE, | |
368 | timeout); | |
369 | ||
370 | rq = to_request(fence); | |
371 | if (i915_gem_request_completed(rq)) | |
372 | goto out; | |
373 | ||
374 | /* This client is about to stall waiting for the GPU. In many cases | |
375 | * this is undesirable and limits the throughput of the system, as | |
376 | * many clients cannot continue processing user input/output whilst | |
377 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
378 | * to the GPU load and thus incurs additional latency for the client. | |
379 | * We can circumvent that by promoting the GPU frequency to maximum | |
380 | * before we wait. This makes the GPU throttle up much more quickly | |
381 | * (good for benchmarks and user experience, e.g. window animations), | |
382 | * but at a cost of spending more power processing the workload | |
383 | * (bad for battery). Not all clients even want their results | |
384 | * immediately and for them we should just let the GPU select its own | |
385 | * frequency to maximise efficiency. To prevent a single client from | |
386 | * forcing the clocks too high for the whole system, we only allow | |
387 | * each client to waitboost once in a busy period. | |
388 | */ | |
389 | if (rps) { | |
390 | if (INTEL_GEN(rq->i915) >= 6) | |
391 | gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies); | |
392 | else | |
393 | rps = NULL; | |
00e60f26 CW |
394 | } |
395 | ||
e95433c7 CW |
396 | timeout = i915_wait_request(rq, flags, timeout); |
397 | ||
398 | out: | |
399 | if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq)) | |
400 | i915_gem_request_retire_upto(rq); | |
401 | ||
cb399eab | 402 | if (rps && rq->global_seqno == intel_engine_last_submit(rq->engine)) { |
e95433c7 CW |
403 | /* The GPU is now idle and this client has stalled. |
404 | * Since no other client has submitted a request in the | |
405 | * meantime, assume that this client is the only one | |
406 | * supplying work to the GPU but is unable to keep that | |
407 | * work supplied because it is waiting. Since the GPU is | |
408 | * then never kept fully busy, RPS autoclocking will | |
409 | * keep the clocks relatively low, causing further delays. | |
410 | * Compensate by giving the synchronous client credit for | |
411 | * a waitboost next time. | |
412 | */ | |
413 | spin_lock(&rq->i915->rps.client_lock); | |
414 | list_del_init(&rps->link); | |
415 | spin_unlock(&rq->i915->rps.client_lock); | |
416 | } | |
417 | ||
418 | return timeout; | |
419 | } | |
420 | ||
421 | static long | |
422 | i915_gem_object_wait_reservation(struct reservation_object *resv, | |
423 | unsigned int flags, | |
424 | long timeout, | |
425 | struct intel_rps_client *rps) | |
426 | { | |
427 | struct dma_fence *excl; | |
428 | ||
429 | if (flags & I915_WAIT_ALL) { | |
430 | struct dma_fence **shared; | |
431 | unsigned int count, i; | |
00e60f26 CW |
432 | int ret; |
433 | ||
e95433c7 CW |
434 | ret = reservation_object_get_fences_rcu(resv, |
435 | &excl, &count, &shared); | |
00e60f26 CW |
436 | if (ret) |
437 | return ret; | |
00e60f26 | 438 | |
e95433c7 CW |
439 | for (i = 0; i < count; i++) { |
440 | timeout = i915_gem_object_wait_fence(shared[i], | |
441 | flags, timeout, | |
442 | rps); | |
443 | if (timeout <= 0) | |
444 | break; | |
00e60f26 | 445 | |
e95433c7 CW |
446 | dma_fence_put(shared[i]); |
447 | } | |
448 | ||
449 | for (; i < count; i++) | |
450 | dma_fence_put(shared[i]); | |
451 | kfree(shared); | |
452 | } else { | |
453 | excl = reservation_object_get_excl_rcu(resv); | |
00e60f26 CW |
454 | } |
455 | ||
e95433c7 CW |
456 | if (excl && timeout > 0) |
457 | timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps); | |
458 | ||
459 | dma_fence_put(excl); | |
460 | ||
461 | return timeout; | |
00e60f26 CW |
462 | } |
463 | ||
6b5e90f5 CW |
464 | static void __fence_set_priority(struct dma_fence *fence, int prio) |
465 | { | |
466 | struct drm_i915_gem_request *rq; | |
467 | struct intel_engine_cs *engine; | |
468 | ||
469 | if (!dma_fence_is_i915(fence)) | |
470 | return; | |
471 | ||
472 | rq = to_request(fence); | |
473 | engine = rq->engine; | |
474 | if (!engine->schedule) | |
475 | return; | |
476 | ||
477 | engine->schedule(rq, prio); | |
478 | } | |
479 | ||
480 | static void fence_set_priority(struct dma_fence *fence, int prio) | |
481 | { | |
482 | /* Recurse once into a fence-array */ | |
483 | if (dma_fence_is_array(fence)) { | |
484 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
485 | int i; | |
486 | ||
487 | for (i = 0; i < array->num_fences; i++) | |
488 | __fence_set_priority(array->fences[i], prio); | |
489 | } else { | |
490 | __fence_set_priority(fence, prio); | |
491 | } | |
492 | } | |
493 | ||
494 | int | |
495 | i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, | |
496 | unsigned int flags, | |
497 | int prio) | |
498 | { | |
499 | struct dma_fence *excl; | |
500 | ||
501 | if (flags & I915_WAIT_ALL) { | |
502 | struct dma_fence **shared; | |
503 | unsigned int count, i; | |
504 | int ret; | |
505 | ||
506 | ret = reservation_object_get_fences_rcu(obj->resv, | |
507 | &excl, &count, &shared); | |
508 | if (ret) | |
509 | return ret; | |
510 | ||
511 | for (i = 0; i < count; i++) { | |
512 | fence_set_priority(shared[i], prio); | |
513 | dma_fence_put(shared[i]); | |
514 | } | |
515 | ||
516 | kfree(shared); | |
517 | } else { | |
518 | excl = reservation_object_get_excl_rcu(obj->resv); | |
519 | } | |
520 | ||
521 | if (excl) { | |
522 | fence_set_priority(excl, prio); | |
523 | dma_fence_put(excl); | |
524 | } | |
525 | return 0; | |
526 | } | |
527 | ||
e95433c7 CW |
528 | /** |
529 | * Waits for rendering to the object to be completed | |
530 | * @obj: i915 gem object | |
531 | * @flags: how to wait (under a lock, for all rendering or just for writes etc) | |
532 | * @timeout: how long to wait | |
533 | * @rps: client (user process) to charge for any waitboosting | |
00e60f26 | 534 | */ |
e95433c7 CW |
535 | int |
536 | i915_gem_object_wait(struct drm_i915_gem_object *obj, | |
537 | unsigned int flags, | |
538 | long timeout, | |
539 | struct intel_rps_client *rps) | |
00e60f26 | 540 | { |
e95433c7 CW |
541 | might_sleep(); |
542 | #if IS_ENABLED(CONFIG_LOCKDEP) | |
543 | GEM_BUG_ON(debug_locks && | |
544 | !!lockdep_is_held(&obj->base.dev->struct_mutex) != | |
545 | !!(flags & I915_WAIT_LOCKED)); | |
546 | #endif | |
547 | GEM_BUG_ON(timeout < 0); | |
00e60f26 | 548 | |
d07f0e59 CW |
549 | timeout = i915_gem_object_wait_reservation(obj->resv, |
550 | flags, timeout, | |
551 | rps); | |
e95433c7 | 552 | return timeout < 0 ? timeout : 0; |
00e60f26 CW |
553 | } |
554 | ||
555 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
556 | { | |
557 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
558 | ||
559 | return &fpriv->rps; | |
560 | } | |
561 | ||
00731155 CW |
562 | int |
563 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
564 | int align) | |
565 | { | |
6a2c4232 | 566 | int ret; |
00731155 | 567 | |
dbb4351b CW |
568 | if (align > obj->base.size) |
569 | return -EINVAL; | |
00731155 | 570 | |
dbb4351b | 571 | if (obj->ops == &i915_gem_phys_ops) |
00731155 | 572 | return 0; |
00731155 | 573 | |
a4f5ea64 | 574 | if (obj->mm.madv != I915_MADV_WILLNEED) |
00731155 CW |
575 | return -EFAULT; |
576 | ||
577 | if (obj->base.filp == NULL) | |
578 | return -EINVAL; | |
579 | ||
4717ca9e CW |
580 | ret = i915_gem_object_unbind(obj); |
581 | if (ret) | |
582 | return ret; | |
583 | ||
548625ee | 584 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
03ac84f1 CW |
585 | if (obj->mm.pages) |
586 | return -EBUSY; | |
6a2c4232 | 587 | |
6a2c4232 CW |
588 | obj->ops = &i915_gem_phys_ops; |
589 | ||
a4f5ea64 | 590 | return i915_gem_object_pin_pages(obj); |
00731155 CW |
591 | } |
592 | ||
593 | static int | |
594 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
595 | struct drm_i915_gem_pwrite *args, | |
03ac84f1 | 596 | struct drm_file *file) |
00731155 CW |
597 | { |
598 | struct drm_device *dev = obj->base.dev; | |
599 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
3ed605bc | 600 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
e95433c7 | 601 | int ret; |
6a2c4232 CW |
602 | |
603 | /* We manually control the domain here and pretend that it | |
604 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
605 | */ | |
e95433c7 CW |
606 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
607 | ret = i915_gem_object_wait(obj, | |
608 | I915_WAIT_INTERRUPTIBLE | | |
609 | I915_WAIT_LOCKED | | |
610 | I915_WAIT_ALL, | |
611 | MAX_SCHEDULE_TIMEOUT, | |
03ac84f1 | 612 | to_rps_client(file)); |
6a2c4232 CW |
613 | if (ret) |
614 | return ret; | |
00731155 | 615 | |
77a0d1ca | 616 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
617 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
618 | unsigned long unwritten; | |
619 | ||
620 | /* The physical object once assigned is fixed for the lifetime | |
621 | * of the obj, so we can safely drop the lock and continue | |
622 | * to access vaddr. | |
623 | */ | |
624 | mutex_unlock(&dev->struct_mutex); | |
625 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
626 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
627 | if (unwritten) { |
628 | ret = -EFAULT; | |
629 | goto out; | |
630 | } | |
00731155 CW |
631 | } |
632 | ||
6a2c4232 | 633 | drm_clflush_virt_range(vaddr, args->size); |
c033666a | 634 | i915_gem_chipset_flush(to_i915(dev)); |
063e4e6b PZ |
635 | |
636 | out: | |
de152b62 | 637 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 638 | return ret; |
00731155 CW |
639 | } |
640 | ||
187685cb | 641 | void *i915_gem_object_alloc(struct drm_i915_private *dev_priv) |
42dcedd4 | 642 | { |
efab6d8d | 643 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
644 | } |
645 | ||
646 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
647 | { | |
fac5e23e | 648 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 649 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
650 | } |
651 | ||
ff72145b DA |
652 | static int |
653 | i915_gem_create(struct drm_file *file, | |
12d79d78 | 654 | struct drm_i915_private *dev_priv, |
ff72145b DA |
655 | uint64_t size, |
656 | uint32_t *handle_p) | |
673a394b | 657 | { |
05394f39 | 658 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
659 | int ret; |
660 | u32 handle; | |
673a394b | 661 | |
ff72145b | 662 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
663 | if (size == 0) |
664 | return -EINVAL; | |
673a394b EA |
665 | |
666 | /* Allocate the new object */ | |
12d79d78 | 667 | obj = i915_gem_object_create(dev_priv, size); |
fe3db79b CW |
668 | if (IS_ERR(obj)) |
669 | return PTR_ERR(obj); | |
673a394b | 670 | |
05394f39 | 671 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 672 | /* drop reference from allocate - handle holds it now */ |
f0cd5182 | 673 | i915_gem_object_put(obj); |
d861e338 DV |
674 | if (ret) |
675 | return ret; | |
202f2fef | 676 | |
ff72145b | 677 | *handle_p = handle; |
673a394b EA |
678 | return 0; |
679 | } | |
680 | ||
ff72145b DA |
681 | int |
682 | i915_gem_dumb_create(struct drm_file *file, | |
683 | struct drm_device *dev, | |
684 | struct drm_mode_create_dumb *args) | |
685 | { | |
686 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 687 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b | 688 | args->size = args->pitch * args->height; |
12d79d78 | 689 | return i915_gem_create(file, to_i915(dev), |
da6b51d0 | 690 | args->size, &args->handle); |
ff72145b DA |
691 | } |
692 | ||
ff72145b DA |
693 | /** |
694 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
695 | * @dev: drm device pointer |
696 | * @data: ioctl data blob | |
697 | * @file: drm file pointer | |
ff72145b DA |
698 | */ |
699 | int | |
700 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
701 | struct drm_file *file) | |
702 | { | |
12d79d78 | 703 | struct drm_i915_private *dev_priv = to_i915(dev); |
ff72145b | 704 | struct drm_i915_gem_create *args = data; |
63ed2cb2 | 705 | |
12d79d78 | 706 | i915_gem_flush_free_objects(dev_priv); |
fbbd37b3 | 707 | |
12d79d78 | 708 | return i915_gem_create(file, dev_priv, |
da6b51d0 | 709 | args->size, &args->handle); |
ff72145b DA |
710 | } |
711 | ||
8461d226 DV |
712 | static inline int |
713 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
714 | const char *gpu_vaddr, int gpu_offset, | |
715 | int length) | |
716 | { | |
717 | int ret, cpu_offset = 0; | |
718 | ||
719 | while (length > 0) { | |
720 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
721 | int this_length = min(cacheline_end - gpu_offset, length); | |
722 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
723 | ||
724 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
725 | gpu_vaddr + swizzled_gpu_offset, | |
726 | this_length); | |
727 | if (ret) | |
728 | return ret + length; | |
729 | ||
730 | cpu_offset += this_length; | |
731 | gpu_offset += this_length; | |
732 | length -= this_length; | |
733 | } | |
734 | ||
735 | return 0; | |
736 | } | |
737 | ||
8c59967c | 738 | static inline int |
4f0c7cfb BW |
739 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
740 | const char __user *cpu_vaddr, | |
8c59967c DV |
741 | int length) |
742 | { | |
743 | int ret, cpu_offset = 0; | |
744 | ||
745 | while (length > 0) { | |
746 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
747 | int this_length = min(cacheline_end - gpu_offset, length); | |
748 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
749 | ||
750 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
751 | cpu_vaddr + cpu_offset, | |
752 | this_length); | |
753 | if (ret) | |
754 | return ret + length; | |
755 | ||
756 | cpu_offset += this_length; | |
757 | gpu_offset += this_length; | |
758 | length -= this_length; | |
759 | } | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
4c914c0c BV |
764 | /* |
765 | * Pins the specified object's pages and synchronizes the object with | |
766 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
767 | * flush the object from the CPU cache. | |
768 | */ | |
769 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
43394c7d | 770 | unsigned int *needs_clflush) |
4c914c0c BV |
771 | { |
772 | int ret; | |
773 | ||
e95433c7 | 774 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c914c0c | 775 | |
e95433c7 | 776 | *needs_clflush = 0; |
43394c7d CW |
777 | if (!i915_gem_object_has_struct_page(obj)) |
778 | return -ENODEV; | |
4c914c0c | 779 | |
e95433c7 CW |
780 | ret = i915_gem_object_wait(obj, |
781 | I915_WAIT_INTERRUPTIBLE | | |
782 | I915_WAIT_LOCKED, | |
783 | MAX_SCHEDULE_TIMEOUT, | |
784 | NULL); | |
c13d87ea CW |
785 | if (ret) |
786 | return ret; | |
787 | ||
a4f5ea64 | 788 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
789 | if (ret) |
790 | return ret; | |
791 | ||
a314d5cb CW |
792 | i915_gem_object_flush_gtt_write_domain(obj); |
793 | ||
43394c7d CW |
794 | /* If we're not in the cpu read domain, set ourself into the gtt |
795 | * read domain and manually flush cachelines (if required). This | |
796 | * optimizes for the case when the gpu will dirty the data | |
797 | * anyway again before the next pread happens. | |
798 | */ | |
799 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
4c914c0c BV |
800 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
801 | obj->cache_level); | |
43394c7d | 802 | |
43394c7d CW |
803 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
804 | ret = i915_gem_object_set_to_cpu_domain(obj, false); | |
9764951e CW |
805 | if (ret) |
806 | goto err_unpin; | |
807 | ||
43394c7d | 808 | *needs_clflush = 0; |
4c914c0c BV |
809 | } |
810 | ||
9764951e | 811 | /* return with the pages pinned */ |
43394c7d | 812 | return 0; |
9764951e CW |
813 | |
814 | err_unpin: | |
815 | i915_gem_object_unpin_pages(obj); | |
816 | return ret; | |
43394c7d CW |
817 | } |
818 | ||
819 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
820 | unsigned int *needs_clflush) | |
821 | { | |
822 | int ret; | |
823 | ||
e95433c7 CW |
824 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
825 | ||
43394c7d CW |
826 | *needs_clflush = 0; |
827 | if (!i915_gem_object_has_struct_page(obj)) | |
828 | return -ENODEV; | |
829 | ||
e95433c7 CW |
830 | ret = i915_gem_object_wait(obj, |
831 | I915_WAIT_INTERRUPTIBLE | | |
832 | I915_WAIT_LOCKED | | |
833 | I915_WAIT_ALL, | |
834 | MAX_SCHEDULE_TIMEOUT, | |
835 | NULL); | |
43394c7d CW |
836 | if (ret) |
837 | return ret; | |
838 | ||
a4f5ea64 | 839 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
840 | if (ret) |
841 | return ret; | |
842 | ||
a314d5cb CW |
843 | i915_gem_object_flush_gtt_write_domain(obj); |
844 | ||
43394c7d CW |
845 | /* If we're not in the cpu write domain, set ourself into the |
846 | * gtt write domain and manually flush cachelines (as required). | |
847 | * This optimizes for the case when the gpu will use the data | |
848 | * right away and we therefore have to clflush anyway. | |
849 | */ | |
850 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) | |
851 | *needs_clflush |= cpu_write_needs_clflush(obj) << 1; | |
852 | ||
853 | /* Same trick applies to invalidate partially written cachelines read | |
854 | * before writing. | |
855 | */ | |
856 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
857 | *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev, | |
858 | obj->cache_level); | |
859 | ||
43394c7d CW |
860 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
861 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
9764951e CW |
862 | if (ret) |
863 | goto err_unpin; | |
864 | ||
43394c7d CW |
865 | *needs_clflush = 0; |
866 | } | |
867 | ||
868 | if ((*needs_clflush & CLFLUSH_AFTER) == 0) | |
869 | obj->cache_dirty = true; | |
870 | ||
871 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); | |
a4f5ea64 | 872 | obj->mm.dirty = true; |
9764951e | 873 | /* return with the pages pinned */ |
43394c7d | 874 | return 0; |
9764951e CW |
875 | |
876 | err_unpin: | |
877 | i915_gem_object_unpin_pages(obj); | |
878 | return ret; | |
4c914c0c BV |
879 | } |
880 | ||
23c18c71 DV |
881 | static void |
882 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
883 | bool swizzled) | |
884 | { | |
e7e58eb5 | 885 | if (unlikely(swizzled)) { |
23c18c71 DV |
886 | unsigned long start = (unsigned long) addr; |
887 | unsigned long end = (unsigned long) addr + length; | |
888 | ||
889 | /* For swizzling simply ensure that we always flush both | |
890 | * channels. Lame, but simple and it works. Swizzled | |
891 | * pwrite/pread is far from a hotpath - current userspace | |
892 | * doesn't use it at all. */ | |
893 | start = round_down(start, 128); | |
894 | end = round_up(end, 128); | |
895 | ||
896 | drm_clflush_virt_range((void *)start, end - start); | |
897 | } else { | |
898 | drm_clflush_virt_range(addr, length); | |
899 | } | |
900 | ||
901 | } | |
902 | ||
d174bd64 DV |
903 | /* Only difference to the fast-path function is that this can handle bit17 |
904 | * and uses non-atomic copy and kmap functions. */ | |
905 | static int | |
bb6dc8d9 | 906 | shmem_pread_slow(struct page *page, int offset, int length, |
d174bd64 DV |
907 | char __user *user_data, |
908 | bool page_do_bit17_swizzling, bool needs_clflush) | |
909 | { | |
910 | char *vaddr; | |
911 | int ret; | |
912 | ||
913 | vaddr = kmap(page); | |
914 | if (needs_clflush) | |
bb6dc8d9 | 915 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 916 | page_do_bit17_swizzling); |
d174bd64 DV |
917 | |
918 | if (page_do_bit17_swizzling) | |
bb6dc8d9 | 919 | ret = __copy_to_user_swizzled(user_data, vaddr, offset, length); |
d174bd64 | 920 | else |
bb6dc8d9 | 921 | ret = __copy_to_user(user_data, vaddr + offset, length); |
d174bd64 DV |
922 | kunmap(page); |
923 | ||
f60d7f0c | 924 | return ret ? - EFAULT : 0; |
d174bd64 DV |
925 | } |
926 | ||
bb6dc8d9 CW |
927 | static int |
928 | shmem_pread(struct page *page, int offset, int length, char __user *user_data, | |
929 | bool page_do_bit17_swizzling, bool needs_clflush) | |
930 | { | |
931 | int ret; | |
932 | ||
933 | ret = -ENODEV; | |
934 | if (!page_do_bit17_swizzling) { | |
935 | char *vaddr = kmap_atomic(page); | |
936 | ||
937 | if (needs_clflush) | |
938 | drm_clflush_virt_range(vaddr + offset, length); | |
939 | ret = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
940 | kunmap_atomic(vaddr); | |
941 | } | |
942 | if (ret == 0) | |
943 | return 0; | |
944 | ||
945 | return shmem_pread_slow(page, offset, length, user_data, | |
946 | page_do_bit17_swizzling, needs_clflush); | |
947 | } | |
948 | ||
949 | static int | |
950 | i915_gem_shmem_pread(struct drm_i915_gem_object *obj, | |
951 | struct drm_i915_gem_pread *args) | |
952 | { | |
953 | char __user *user_data; | |
954 | u64 remain; | |
955 | unsigned int obj_do_bit17_swizzling; | |
956 | unsigned int needs_clflush; | |
957 | unsigned int idx, offset; | |
958 | int ret; | |
959 | ||
960 | obj_do_bit17_swizzling = 0; | |
961 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
962 | obj_do_bit17_swizzling = BIT(17); | |
963 | ||
964 | ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex); | |
965 | if (ret) | |
966 | return ret; | |
967 | ||
968 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); | |
969 | mutex_unlock(&obj->base.dev->struct_mutex); | |
970 | if (ret) | |
971 | return ret; | |
972 | ||
973 | remain = args->size; | |
974 | user_data = u64_to_user_ptr(args->data_ptr); | |
975 | offset = offset_in_page(args->offset); | |
976 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
977 | struct page *page = i915_gem_object_get_page(obj, idx); | |
978 | int length; | |
979 | ||
980 | length = remain; | |
981 | if (offset + length > PAGE_SIZE) | |
982 | length = PAGE_SIZE - offset; | |
983 | ||
984 | ret = shmem_pread(page, offset, length, user_data, | |
985 | page_to_phys(page) & obj_do_bit17_swizzling, | |
986 | needs_clflush); | |
987 | if (ret) | |
988 | break; | |
989 | ||
990 | remain -= length; | |
991 | user_data += length; | |
992 | offset = 0; | |
993 | } | |
994 | ||
995 | i915_gem_obj_finish_shmem_access(obj); | |
996 | return ret; | |
997 | } | |
998 | ||
999 | static inline bool | |
1000 | gtt_user_read(struct io_mapping *mapping, | |
1001 | loff_t base, int offset, | |
1002 | char __user *user_data, int length) | |
b50a5371 | 1003 | { |
b50a5371 | 1004 | void *vaddr; |
bb6dc8d9 | 1005 | unsigned long unwritten; |
b50a5371 | 1006 | |
b50a5371 | 1007 | /* We can use the cpu mem copy function because this is X86. */ |
bb6dc8d9 CW |
1008 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
1009 | unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
1010 | io_mapping_unmap_atomic(vaddr); | |
1011 | if (unwritten) { | |
1012 | vaddr = (void __force *) | |
1013 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
1014 | unwritten = copy_to_user(user_data, vaddr + offset, length); | |
1015 | io_mapping_unmap(vaddr); | |
1016 | } | |
b50a5371 AS |
1017 | return unwritten; |
1018 | } | |
1019 | ||
1020 | static int | |
bb6dc8d9 CW |
1021 | i915_gem_gtt_pread(struct drm_i915_gem_object *obj, |
1022 | const struct drm_i915_gem_pread *args) | |
b50a5371 | 1023 | { |
bb6dc8d9 CW |
1024 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
1025 | struct i915_ggtt *ggtt = &i915->ggtt; | |
b50a5371 | 1026 | struct drm_mm_node node; |
bb6dc8d9 CW |
1027 | struct i915_vma *vma; |
1028 | void __user *user_data; | |
1029 | u64 remain, offset; | |
b50a5371 AS |
1030 | int ret; |
1031 | ||
bb6dc8d9 CW |
1032 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1033 | if (ret) | |
1034 | return ret; | |
1035 | ||
1036 | intel_runtime_pm_get(i915); | |
1037 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, | |
1038 | PIN_MAPPABLE | PIN_NONBLOCK); | |
18034584 CW |
1039 | if (!IS_ERR(vma)) { |
1040 | node.start = i915_ggtt_offset(vma); | |
1041 | node.allocated = false; | |
49ef5294 | 1042 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1043 | if (ret) { |
1044 | i915_vma_unpin(vma); | |
1045 | vma = ERR_PTR(ret); | |
1046 | } | |
1047 | } | |
058d88c4 | 1048 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1049 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
b50a5371 | 1050 | if (ret) |
bb6dc8d9 CW |
1051 | goto out_unlock; |
1052 | GEM_BUG_ON(!node.allocated); | |
b50a5371 AS |
1053 | } |
1054 | ||
1055 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1056 | if (ret) | |
1057 | goto out_unpin; | |
1058 | ||
bb6dc8d9 | 1059 | mutex_unlock(&i915->drm.struct_mutex); |
b50a5371 | 1060 | |
bb6dc8d9 CW |
1061 | user_data = u64_to_user_ptr(args->data_ptr); |
1062 | remain = args->size; | |
1063 | offset = args->offset; | |
b50a5371 AS |
1064 | |
1065 | while (remain > 0) { | |
1066 | /* Operation in this page | |
1067 | * | |
1068 | * page_base = page offset within aperture | |
1069 | * page_offset = offset within page | |
1070 | * page_length = bytes to copy for this page | |
1071 | */ | |
1072 | u32 page_base = node.start; | |
1073 | unsigned page_offset = offset_in_page(offset); | |
1074 | unsigned page_length = PAGE_SIZE - page_offset; | |
1075 | page_length = remain < page_length ? remain : page_length; | |
1076 | if (node.allocated) { | |
1077 | wmb(); | |
1078 | ggtt->base.insert_page(&ggtt->base, | |
1079 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
bb6dc8d9 | 1080 | node.start, I915_CACHE_NONE, 0); |
b50a5371 AS |
1081 | wmb(); |
1082 | } else { | |
1083 | page_base += offset & PAGE_MASK; | |
1084 | } | |
bb6dc8d9 CW |
1085 | |
1086 | if (gtt_user_read(&ggtt->mappable, page_base, page_offset, | |
1087 | user_data, page_length)) { | |
b50a5371 AS |
1088 | ret = -EFAULT; |
1089 | break; | |
1090 | } | |
1091 | ||
1092 | remain -= page_length; | |
1093 | user_data += page_length; | |
1094 | offset += page_length; | |
1095 | } | |
1096 | ||
bb6dc8d9 | 1097 | mutex_lock(&i915->drm.struct_mutex); |
b50a5371 AS |
1098 | out_unpin: |
1099 | if (node.allocated) { | |
1100 | wmb(); | |
1101 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1102 | node.start, node.size); |
b50a5371 AS |
1103 | remove_mappable_node(&node); |
1104 | } else { | |
058d88c4 | 1105 | i915_vma_unpin(vma); |
b50a5371 | 1106 | } |
bb6dc8d9 CW |
1107 | out_unlock: |
1108 | intel_runtime_pm_put(i915); | |
1109 | mutex_unlock(&i915->drm.struct_mutex); | |
f60d7f0c | 1110 | |
eb01459f EA |
1111 | return ret; |
1112 | } | |
1113 | ||
673a394b EA |
1114 | /** |
1115 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
1116 | * @dev: drm device pointer |
1117 | * @data: ioctl data blob | |
1118 | * @file: drm file pointer | |
673a394b EA |
1119 | * |
1120 | * On error, the contents of *data are undefined. | |
1121 | */ | |
1122 | int | |
1123 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1124 | struct drm_file *file) |
673a394b EA |
1125 | { |
1126 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 1127 | struct drm_i915_gem_object *obj; |
bb6dc8d9 | 1128 | int ret; |
673a394b | 1129 | |
51311d0a CW |
1130 | if (args->size == 0) |
1131 | return 0; | |
1132 | ||
1133 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 1134 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1135 | args->size)) |
1136 | return -EFAULT; | |
1137 | ||
03ac0642 | 1138 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1139 | if (!obj) |
1140 | return -ENOENT; | |
673a394b | 1141 | |
7dcd2499 | 1142 | /* Bounds check source. */ |
966d5bf5 | 1143 | if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { |
ce9d419d | 1144 | ret = -EINVAL; |
bb6dc8d9 | 1145 | goto out; |
ce9d419d CW |
1146 | } |
1147 | ||
db53a302 CW |
1148 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
1149 | ||
e95433c7 CW |
1150 | ret = i915_gem_object_wait(obj, |
1151 | I915_WAIT_INTERRUPTIBLE, | |
1152 | MAX_SCHEDULE_TIMEOUT, | |
1153 | to_rps_client(file)); | |
258a5ede | 1154 | if (ret) |
bb6dc8d9 | 1155 | goto out; |
258a5ede | 1156 | |
bb6dc8d9 | 1157 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1158 | if (ret) |
bb6dc8d9 | 1159 | goto out; |
673a394b | 1160 | |
bb6dc8d9 | 1161 | ret = i915_gem_shmem_pread(obj, args); |
9c870d03 | 1162 | if (ret == -EFAULT || ret == -ENODEV) |
bb6dc8d9 | 1163 | ret = i915_gem_gtt_pread(obj, args); |
b50a5371 | 1164 | |
bb6dc8d9 CW |
1165 | i915_gem_object_unpin_pages(obj); |
1166 | out: | |
f0cd5182 | 1167 | i915_gem_object_put(obj); |
eb01459f | 1168 | return ret; |
673a394b EA |
1169 | } |
1170 | ||
0839ccb8 KP |
1171 | /* This is the fast write path which cannot handle |
1172 | * page faults in the source data | |
9b7530cc | 1173 | */ |
0839ccb8 | 1174 | |
fe115628 CW |
1175 | static inline bool |
1176 | ggtt_write(struct io_mapping *mapping, | |
1177 | loff_t base, int offset, | |
1178 | char __user *user_data, int length) | |
9b7530cc | 1179 | { |
4f0c7cfb | 1180 | void *vaddr; |
0839ccb8 | 1181 | unsigned long unwritten; |
9b7530cc | 1182 | |
4f0c7cfb | 1183 | /* We can use the cpu mem copy function because this is X86. */ |
fe115628 CW |
1184 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
1185 | unwritten = __copy_from_user_inatomic_nocache(vaddr + offset, | |
0839ccb8 | 1186 | user_data, length); |
fe115628 CW |
1187 | io_mapping_unmap_atomic(vaddr); |
1188 | if (unwritten) { | |
1189 | vaddr = (void __force *) | |
1190 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
1191 | unwritten = copy_from_user(vaddr + offset, user_data, length); | |
1192 | io_mapping_unmap(vaddr); | |
1193 | } | |
bb6dc8d9 | 1194 | |
bb6dc8d9 CW |
1195 | return unwritten; |
1196 | } | |
1197 | ||
3de09aa3 EA |
1198 | /** |
1199 | * This is the fast pwrite path, where we copy the data directly from the | |
1200 | * user into the GTT, uncached. | |
fe115628 | 1201 | * @obj: i915 GEM object |
14bb2c11 | 1202 | * @args: pwrite arguments structure |
3de09aa3 | 1203 | */ |
673a394b | 1204 | static int |
fe115628 CW |
1205 | i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, |
1206 | const struct drm_i915_gem_pwrite *args) | |
673a394b | 1207 | { |
fe115628 | 1208 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
4f1959ee AS |
1209 | struct i915_ggtt *ggtt = &i915->ggtt; |
1210 | struct drm_mm_node node; | |
fe115628 CW |
1211 | struct i915_vma *vma; |
1212 | u64 remain, offset; | |
1213 | void __user *user_data; | |
4f1959ee | 1214 | int ret; |
b50a5371 | 1215 | |
fe115628 CW |
1216 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1217 | if (ret) | |
1218 | return ret; | |
935aaa69 | 1219 | |
9c870d03 | 1220 | intel_runtime_pm_get(i915); |
058d88c4 | 1221 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
de895082 | 1222 | PIN_MAPPABLE | PIN_NONBLOCK); |
18034584 CW |
1223 | if (!IS_ERR(vma)) { |
1224 | node.start = i915_ggtt_offset(vma); | |
1225 | node.allocated = false; | |
49ef5294 | 1226 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1227 | if (ret) { |
1228 | i915_vma_unpin(vma); | |
1229 | vma = ERR_PTR(ret); | |
1230 | } | |
1231 | } | |
058d88c4 | 1232 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1233 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
4f1959ee | 1234 | if (ret) |
fe115628 CW |
1235 | goto out_unlock; |
1236 | GEM_BUG_ON(!node.allocated); | |
4f1959ee | 1237 | } |
935aaa69 DV |
1238 | |
1239 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1240 | if (ret) | |
1241 | goto out_unpin; | |
1242 | ||
fe115628 CW |
1243 | mutex_unlock(&i915->drm.struct_mutex); |
1244 | ||
b19482d7 | 1245 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1246 | |
4f1959ee AS |
1247 | user_data = u64_to_user_ptr(args->data_ptr); |
1248 | offset = args->offset; | |
1249 | remain = args->size; | |
1250 | while (remain) { | |
673a394b EA |
1251 | /* Operation in this page |
1252 | * | |
0839ccb8 KP |
1253 | * page_base = page offset within aperture |
1254 | * page_offset = offset within page | |
1255 | * page_length = bytes to copy for this page | |
673a394b | 1256 | */ |
4f1959ee | 1257 | u32 page_base = node.start; |
bb6dc8d9 CW |
1258 | unsigned int page_offset = offset_in_page(offset); |
1259 | unsigned int page_length = PAGE_SIZE - page_offset; | |
4f1959ee AS |
1260 | page_length = remain < page_length ? remain : page_length; |
1261 | if (node.allocated) { | |
1262 | wmb(); /* flush the write before we modify the GGTT */ | |
1263 | ggtt->base.insert_page(&ggtt->base, | |
1264 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1265 | node.start, I915_CACHE_NONE, 0); | |
1266 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1267 | } else { | |
1268 | page_base += offset & PAGE_MASK; | |
1269 | } | |
0839ccb8 | 1270 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1271 | * source page isn't available. Return the error and we'll |
1272 | * retry in the slow path. | |
b50a5371 AS |
1273 | * If the object is non-shmem backed, we retry again with the |
1274 | * path that handles page fault. | |
0839ccb8 | 1275 | */ |
fe115628 CW |
1276 | if (ggtt_write(&ggtt->mappable, page_base, page_offset, |
1277 | user_data, page_length)) { | |
1278 | ret = -EFAULT; | |
1279 | break; | |
935aaa69 | 1280 | } |
673a394b | 1281 | |
0839ccb8 KP |
1282 | remain -= page_length; |
1283 | user_data += page_length; | |
1284 | offset += page_length; | |
673a394b | 1285 | } |
b19482d7 | 1286 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
fe115628 CW |
1287 | |
1288 | mutex_lock(&i915->drm.struct_mutex); | |
935aaa69 | 1289 | out_unpin: |
4f1959ee AS |
1290 | if (node.allocated) { |
1291 | wmb(); | |
1292 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1293 | node.start, node.size); |
4f1959ee AS |
1294 | remove_mappable_node(&node); |
1295 | } else { | |
058d88c4 | 1296 | i915_vma_unpin(vma); |
4f1959ee | 1297 | } |
fe115628 | 1298 | out_unlock: |
9c870d03 | 1299 | intel_runtime_pm_put(i915); |
fe115628 | 1300 | mutex_unlock(&i915->drm.struct_mutex); |
3de09aa3 | 1301 | return ret; |
673a394b EA |
1302 | } |
1303 | ||
3043c60c | 1304 | static int |
fe115628 | 1305 | shmem_pwrite_slow(struct page *page, int offset, int length, |
d174bd64 DV |
1306 | char __user *user_data, |
1307 | bool page_do_bit17_swizzling, | |
1308 | bool needs_clflush_before, | |
1309 | bool needs_clflush_after) | |
673a394b | 1310 | { |
d174bd64 DV |
1311 | char *vaddr; |
1312 | int ret; | |
e5281ccd | 1313 | |
d174bd64 | 1314 | vaddr = kmap(page); |
e7e58eb5 | 1315 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
fe115628 | 1316 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1317 | page_do_bit17_swizzling); |
d174bd64 | 1318 | if (page_do_bit17_swizzling) |
fe115628 CW |
1319 | ret = __copy_from_user_swizzled(vaddr, offset, user_data, |
1320 | length); | |
d174bd64 | 1321 | else |
fe115628 | 1322 | ret = __copy_from_user(vaddr + offset, user_data, length); |
d174bd64 | 1323 | if (needs_clflush_after) |
fe115628 | 1324 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1325 | page_do_bit17_swizzling); |
d174bd64 | 1326 | kunmap(page); |
40123c1f | 1327 | |
755d2218 | 1328 | return ret ? -EFAULT : 0; |
40123c1f EA |
1329 | } |
1330 | ||
fe115628 CW |
1331 | /* Per-page copy function for the shmem pwrite fastpath. |
1332 | * Flushes invalid cachelines before writing to the target if | |
1333 | * needs_clflush_before is set and flushes out any written cachelines after | |
1334 | * writing if needs_clflush is set. | |
1335 | */ | |
40123c1f | 1336 | static int |
fe115628 CW |
1337 | shmem_pwrite(struct page *page, int offset, int len, char __user *user_data, |
1338 | bool page_do_bit17_swizzling, | |
1339 | bool needs_clflush_before, | |
1340 | bool needs_clflush_after) | |
40123c1f | 1341 | { |
fe115628 CW |
1342 | int ret; |
1343 | ||
1344 | ret = -ENODEV; | |
1345 | if (!page_do_bit17_swizzling) { | |
1346 | char *vaddr = kmap_atomic(page); | |
1347 | ||
1348 | if (needs_clflush_before) | |
1349 | drm_clflush_virt_range(vaddr + offset, len); | |
1350 | ret = __copy_from_user_inatomic(vaddr + offset, user_data, len); | |
1351 | if (needs_clflush_after) | |
1352 | drm_clflush_virt_range(vaddr + offset, len); | |
1353 | ||
1354 | kunmap_atomic(vaddr); | |
1355 | } | |
1356 | if (ret == 0) | |
1357 | return ret; | |
1358 | ||
1359 | return shmem_pwrite_slow(page, offset, len, user_data, | |
1360 | page_do_bit17_swizzling, | |
1361 | needs_clflush_before, | |
1362 | needs_clflush_after); | |
1363 | } | |
1364 | ||
1365 | static int | |
1366 | i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, | |
1367 | const struct drm_i915_gem_pwrite *args) | |
1368 | { | |
1369 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
1370 | void __user *user_data; | |
1371 | u64 remain; | |
1372 | unsigned int obj_do_bit17_swizzling; | |
1373 | unsigned int partial_cacheline_write; | |
43394c7d | 1374 | unsigned int needs_clflush; |
fe115628 CW |
1375 | unsigned int offset, idx; |
1376 | int ret; | |
40123c1f | 1377 | |
fe115628 | 1378 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
755d2218 CW |
1379 | if (ret) |
1380 | return ret; | |
1381 | ||
fe115628 CW |
1382 | ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); |
1383 | mutex_unlock(&i915->drm.struct_mutex); | |
1384 | if (ret) | |
1385 | return ret; | |
673a394b | 1386 | |
fe115628 CW |
1387 | obj_do_bit17_swizzling = 0; |
1388 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
1389 | obj_do_bit17_swizzling = BIT(17); | |
e5281ccd | 1390 | |
fe115628 CW |
1391 | /* If we don't overwrite a cacheline completely we need to be |
1392 | * careful to have up-to-date data by first clflushing. Don't | |
1393 | * overcomplicate things and flush the entire patch. | |
1394 | */ | |
1395 | partial_cacheline_write = 0; | |
1396 | if (needs_clflush & CLFLUSH_BEFORE) | |
1397 | partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1; | |
9da3da66 | 1398 | |
fe115628 CW |
1399 | user_data = u64_to_user_ptr(args->data_ptr); |
1400 | remain = args->size; | |
1401 | offset = offset_in_page(args->offset); | |
1402 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
1403 | struct page *page = i915_gem_object_get_page(obj, idx); | |
1404 | int length; | |
40123c1f | 1405 | |
fe115628 CW |
1406 | length = remain; |
1407 | if (offset + length > PAGE_SIZE) | |
1408 | length = PAGE_SIZE - offset; | |
755d2218 | 1409 | |
fe115628 CW |
1410 | ret = shmem_pwrite(page, offset, length, user_data, |
1411 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1412 | (offset | length) & partial_cacheline_write, | |
1413 | needs_clflush & CLFLUSH_AFTER); | |
755d2218 | 1414 | if (ret) |
fe115628 | 1415 | break; |
755d2218 | 1416 | |
fe115628 CW |
1417 | remain -= length; |
1418 | user_data += length; | |
1419 | offset = 0; | |
8c59967c | 1420 | } |
673a394b | 1421 | |
de152b62 | 1422 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
fe115628 | 1423 | i915_gem_obj_finish_shmem_access(obj); |
40123c1f | 1424 | return ret; |
673a394b EA |
1425 | } |
1426 | ||
1427 | /** | |
1428 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1429 | * @dev: drm device |
1430 | * @data: ioctl data blob | |
1431 | * @file: drm file | |
673a394b EA |
1432 | * |
1433 | * On error, the contents of the buffer that were to be modified are undefined. | |
1434 | */ | |
1435 | int | |
1436 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1437 | struct drm_file *file) |
673a394b EA |
1438 | { |
1439 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1440 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1441 | int ret; |
1442 | ||
1443 | if (args->size == 0) | |
1444 | return 0; | |
1445 | ||
1446 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1447 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1448 | args->size)) |
1449 | return -EFAULT; | |
1450 | ||
03ac0642 | 1451 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1452 | if (!obj) |
1453 | return -ENOENT; | |
673a394b | 1454 | |
7dcd2499 | 1455 | /* Bounds check destination. */ |
966d5bf5 | 1456 | if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { |
ce9d419d | 1457 | ret = -EINVAL; |
258a5ede | 1458 | goto err; |
ce9d419d CW |
1459 | } |
1460 | ||
db53a302 CW |
1461 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1462 | ||
e95433c7 CW |
1463 | ret = i915_gem_object_wait(obj, |
1464 | I915_WAIT_INTERRUPTIBLE | | |
1465 | I915_WAIT_ALL, | |
1466 | MAX_SCHEDULE_TIMEOUT, | |
1467 | to_rps_client(file)); | |
258a5ede CW |
1468 | if (ret) |
1469 | goto err; | |
1470 | ||
fe115628 | 1471 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1472 | if (ret) |
fe115628 | 1473 | goto err; |
258a5ede | 1474 | |
935aaa69 | 1475 | ret = -EFAULT; |
673a394b EA |
1476 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1477 | * it would end up going through the fenced access, and we'll get | |
1478 | * different detiling behavior between reading and writing. | |
1479 | * pread/pwrite currently are reading and writing from the CPU | |
1480 | * perspective, requiring manual detiling by the client. | |
1481 | */ | |
6eae0059 | 1482 | if (!i915_gem_object_has_struct_page(obj) || |
9c870d03 | 1483 | cpu_write_needs_clflush(obj)) |
935aaa69 DV |
1484 | /* Note that the gtt paths might fail with non-page-backed user |
1485 | * pointers (e.g. gtt mappings when moving data between | |
9c870d03 CW |
1486 | * textures). Fallback to the shmem path in that case. |
1487 | */ | |
fe115628 | 1488 | ret = i915_gem_gtt_pwrite_fast(obj, args); |
673a394b | 1489 | |
d1054ee4 | 1490 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1491 | if (obj->phys_handle) |
1492 | ret = i915_gem_phys_pwrite(obj, args, file); | |
b50a5371 | 1493 | else |
fe115628 | 1494 | ret = i915_gem_shmem_pwrite(obj, args); |
6a2c4232 | 1495 | } |
5c0480f2 | 1496 | |
fe115628 | 1497 | i915_gem_object_unpin_pages(obj); |
258a5ede | 1498 | err: |
f0cd5182 | 1499 | i915_gem_object_put(obj); |
258a5ede | 1500 | return ret; |
673a394b EA |
1501 | } |
1502 | ||
d243ad82 | 1503 | static inline enum fb_op_origin |
aeecc969 CW |
1504 | write_origin(struct drm_i915_gem_object *obj, unsigned domain) |
1505 | { | |
50349247 CW |
1506 | return (domain == I915_GEM_DOMAIN_GTT ? |
1507 | obj->frontbuffer_ggtt_origin : ORIGIN_CPU); | |
aeecc969 CW |
1508 | } |
1509 | ||
40e62d5d CW |
1510 | static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj) |
1511 | { | |
1512 | struct drm_i915_private *i915; | |
1513 | struct list_head *list; | |
1514 | struct i915_vma *vma; | |
1515 | ||
1516 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
1517 | if (!i915_vma_is_ggtt(vma)) | |
1518 | continue; | |
1519 | ||
1520 | if (i915_vma_is_active(vma)) | |
1521 | continue; | |
1522 | ||
1523 | if (!drm_mm_node_allocated(&vma->node)) | |
1524 | continue; | |
1525 | ||
1526 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
1527 | } | |
1528 | ||
1529 | i915 = to_i915(obj->base.dev); | |
1530 | list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list; | |
56cea323 | 1531 | list_move_tail(&obj->global_link, list); |
40e62d5d CW |
1532 | } |
1533 | ||
673a394b | 1534 | /** |
2ef7eeaa EA |
1535 | * Called when user space prepares to use an object with the CPU, either |
1536 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1537 | * @dev: drm device |
1538 | * @data: ioctl data blob | |
1539 | * @file: drm file | |
673a394b EA |
1540 | */ |
1541 | int | |
1542 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1543 | struct drm_file *file) |
673a394b EA |
1544 | { |
1545 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1546 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1547 | uint32_t read_domains = args->read_domains; |
1548 | uint32_t write_domain = args->write_domain; | |
40e62d5d | 1549 | int err; |
673a394b | 1550 | |
2ef7eeaa | 1551 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1552 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1553 | return -EINVAL; |
1554 | ||
1555 | /* Having something in the write domain implies it's in the read | |
1556 | * domain, and only that read domain. Enforce that in the request. | |
1557 | */ | |
1558 | if (write_domain != 0 && read_domains != write_domain) | |
1559 | return -EINVAL; | |
1560 | ||
03ac0642 | 1561 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1562 | if (!obj) |
1563 | return -ENOENT; | |
673a394b | 1564 | |
3236f57a CW |
1565 | /* Try to flush the object off the GPU without holding the lock. |
1566 | * We will repeat the flush holding the lock in the normal manner | |
1567 | * to catch cases where we are gazumped. | |
1568 | */ | |
40e62d5d | 1569 | err = i915_gem_object_wait(obj, |
e95433c7 CW |
1570 | I915_WAIT_INTERRUPTIBLE | |
1571 | (write_domain ? I915_WAIT_ALL : 0), | |
1572 | MAX_SCHEDULE_TIMEOUT, | |
1573 | to_rps_client(file)); | |
40e62d5d | 1574 | if (err) |
f0cd5182 | 1575 | goto out; |
b8f9096d | 1576 | |
40e62d5d CW |
1577 | /* Flush and acquire obj->pages so that we are coherent through |
1578 | * direct access in memory with previous cached writes through | |
1579 | * shmemfs and that our cache domain tracking remains valid. | |
1580 | * For example, if the obj->filp was moved to swap without us | |
1581 | * being notified and releasing the pages, we would mistakenly | |
1582 | * continue to assume that the obj remained out of the CPU cached | |
1583 | * domain. | |
1584 | */ | |
1585 | err = i915_gem_object_pin_pages(obj); | |
1586 | if (err) | |
f0cd5182 | 1587 | goto out; |
40e62d5d CW |
1588 | |
1589 | err = i915_mutex_lock_interruptible(dev); | |
1590 | if (err) | |
f0cd5182 | 1591 | goto out_unpin; |
3236f57a | 1592 | |
43566ded | 1593 | if (read_domains & I915_GEM_DOMAIN_GTT) |
40e62d5d | 1594 | err = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1595 | else |
40e62d5d | 1596 | err = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1597 | |
40e62d5d CW |
1598 | /* And bump the LRU for this access */ |
1599 | i915_gem_object_bump_inactive_ggtt(obj); | |
031b698a | 1600 | |
673a394b | 1601 | mutex_unlock(&dev->struct_mutex); |
b8f9096d | 1602 | |
40e62d5d CW |
1603 | if (write_domain != 0) |
1604 | intel_fb_obj_invalidate(obj, write_origin(obj, write_domain)); | |
1605 | ||
f0cd5182 | 1606 | out_unpin: |
40e62d5d | 1607 | i915_gem_object_unpin_pages(obj); |
f0cd5182 CW |
1608 | out: |
1609 | i915_gem_object_put(obj); | |
40e62d5d | 1610 | return err; |
673a394b EA |
1611 | } |
1612 | ||
1613 | /** | |
1614 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1615 | * @dev: drm device |
1616 | * @data: ioctl data blob | |
1617 | * @file: drm file | |
673a394b EA |
1618 | */ |
1619 | int | |
1620 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1621 | struct drm_file *file) |
673a394b EA |
1622 | { |
1623 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1624 | struct drm_i915_gem_object *obj; |
c21724cc | 1625 | int err = 0; |
1d7cfea1 | 1626 | |
03ac0642 | 1627 | obj = i915_gem_object_lookup(file, args->handle); |
c21724cc CW |
1628 | if (!obj) |
1629 | return -ENOENT; | |
673a394b | 1630 | |
673a394b | 1631 | /* Pinned buffers may be scanout, so flush the cache */ |
c21724cc CW |
1632 | if (READ_ONCE(obj->pin_display)) { |
1633 | err = i915_mutex_lock_interruptible(dev); | |
1634 | if (!err) { | |
1635 | i915_gem_object_flush_cpu_write_domain(obj); | |
1636 | mutex_unlock(&dev->struct_mutex); | |
1637 | } | |
1638 | } | |
e47c68e9 | 1639 | |
f0cd5182 | 1640 | i915_gem_object_put(obj); |
c21724cc | 1641 | return err; |
673a394b EA |
1642 | } |
1643 | ||
1644 | /** | |
14bb2c11 TU |
1645 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1646 | * it is mapped to. | |
1647 | * @dev: drm device | |
1648 | * @data: ioctl data blob | |
1649 | * @file: drm file | |
673a394b EA |
1650 | * |
1651 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1652 | * imply a ref on the object itself. | |
34367381 DV |
1653 | * |
1654 | * IMPORTANT: | |
1655 | * | |
1656 | * DRM driver writers who look a this function as an example for how to do GEM | |
1657 | * mmap support, please don't implement mmap support like here. The modern way | |
1658 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1659 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1660 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1661 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1662 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1663 | */ |
1664 | int | |
1665 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1666 | struct drm_file *file) |
673a394b EA |
1667 | { |
1668 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1669 | struct drm_i915_gem_object *obj; |
673a394b EA |
1670 | unsigned long addr; |
1671 | ||
1816f923 AG |
1672 | if (args->flags & ~(I915_MMAP_WC)) |
1673 | return -EINVAL; | |
1674 | ||
568a58e5 | 1675 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1676 | return -ENODEV; |
1677 | ||
03ac0642 CW |
1678 | obj = i915_gem_object_lookup(file, args->handle); |
1679 | if (!obj) | |
bf79cb91 | 1680 | return -ENOENT; |
673a394b | 1681 | |
1286ff73 DV |
1682 | /* prime objects have no backing filp to GEM mmap |
1683 | * pages from. | |
1684 | */ | |
03ac0642 | 1685 | if (!obj->base.filp) { |
f0cd5182 | 1686 | i915_gem_object_put(obj); |
1286ff73 DV |
1687 | return -EINVAL; |
1688 | } | |
1689 | ||
03ac0642 | 1690 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1691 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1692 | args->offset); | |
1816f923 AG |
1693 | if (args->flags & I915_MMAP_WC) { |
1694 | struct mm_struct *mm = current->mm; | |
1695 | struct vm_area_struct *vma; | |
1696 | ||
80a89a5e | 1697 | if (down_write_killable(&mm->mmap_sem)) { |
f0cd5182 | 1698 | i915_gem_object_put(obj); |
80a89a5e MH |
1699 | return -EINTR; |
1700 | } | |
1816f923 AG |
1701 | vma = find_vma(mm, addr); |
1702 | if (vma) | |
1703 | vma->vm_page_prot = | |
1704 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1705 | else | |
1706 | addr = -ENOMEM; | |
1707 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1708 | |
1709 | /* This may race, but that's ok, it only gets set */ | |
50349247 | 1710 | WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU); |
1816f923 | 1711 | } |
f0cd5182 | 1712 | i915_gem_object_put(obj); |
673a394b EA |
1713 | if (IS_ERR((void *)addr)) |
1714 | return addr; | |
1715 | ||
1716 | args->addr_ptr = (uint64_t) addr; | |
1717 | ||
1718 | return 0; | |
1719 | } | |
1720 | ||
03af84fe CW |
1721 | static unsigned int tile_row_pages(struct drm_i915_gem_object *obj) |
1722 | { | |
1723 | u64 size; | |
1724 | ||
1725 | size = i915_gem_object_get_stride(obj); | |
1726 | size *= i915_gem_object_get_tiling(obj) == I915_TILING_Y ? 32 : 8; | |
1727 | ||
1728 | return size >> PAGE_SHIFT; | |
1729 | } | |
1730 | ||
4cc69075 CW |
1731 | /** |
1732 | * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps | |
1733 | * | |
1734 | * A history of the GTT mmap interface: | |
1735 | * | |
1736 | * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to | |
1737 | * aligned and suitable for fencing, and still fit into the available | |
1738 | * mappable space left by the pinned display objects. A classic problem | |
1739 | * we called the page-fault-of-doom where we would ping-pong between | |
1740 | * two objects that could not fit inside the GTT and so the memcpy | |
1741 | * would page one object in at the expense of the other between every | |
1742 | * single byte. | |
1743 | * | |
1744 | * 1 - Objects can be any size, and have any compatible fencing (X Y, or none | |
1745 | * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the | |
1746 | * object is too large for the available space (or simply too large | |
1747 | * for the mappable aperture!), a view is created instead and faulted | |
1748 | * into userspace. (This view is aligned and sized appropriately for | |
1749 | * fenced access.) | |
1750 | * | |
1751 | * Restrictions: | |
1752 | * | |
1753 | * * snoopable objects cannot be accessed via the GTT. It can cause machine | |
1754 | * hangs on some architectures, corruption on others. An attempt to service | |
1755 | * a GTT page fault from a snoopable object will generate a SIGBUS. | |
1756 | * | |
1757 | * * the object must be able to fit into RAM (physical memory, though no | |
1758 | * limited to the mappable aperture). | |
1759 | * | |
1760 | * | |
1761 | * Caveats: | |
1762 | * | |
1763 | * * a new GTT page fault will synchronize rendering from the GPU and flush | |
1764 | * all data to system memory. Subsequent access will not be synchronized. | |
1765 | * | |
1766 | * * all mappings are revoked on runtime device suspend. | |
1767 | * | |
1768 | * * there are only 8, 16 or 32 fence registers to share between all users | |
1769 | * (older machines require fence register for display and blitter access | |
1770 | * as well). Contention of the fence registers will cause the previous users | |
1771 | * to be unmapped and any new access will generate new page faults. | |
1772 | * | |
1773 | * * running out of memory while servicing a fault may generate a SIGBUS, | |
1774 | * rather than the expected SIGSEGV. | |
1775 | */ | |
1776 | int i915_gem_mmap_gtt_version(void) | |
1777 | { | |
1778 | return 1; | |
1779 | } | |
1780 | ||
de151cf6 JB |
1781 | /** |
1782 | * i915_gem_fault - fault a page into the GTT | |
058d88c4 | 1783 | * @area: CPU VMA in question |
d9072a3e | 1784 | * @vmf: fault info |
de151cf6 JB |
1785 | * |
1786 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1787 | * from userspace. The fault handler takes care of binding the object to | |
1788 | * the GTT (if needed), allocating and programming a fence register (again, | |
1789 | * only if needed based on whether the old reg is still valid or the object | |
1790 | * is tiled) and inserting a new PTE into the faulting process. | |
1791 | * | |
1792 | * Note that the faulting process may involve evicting existing objects | |
1793 | * from the GTT and/or fence registers to make room. So performance may | |
1794 | * suffer if the GTT working set is large or there are few fence registers | |
1795 | * left. | |
4cc69075 CW |
1796 | * |
1797 | * The current feature set supported by i915_gem_fault() and thus GTT mmaps | |
1798 | * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version). | |
de151cf6 | 1799 | */ |
058d88c4 | 1800 | int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf) |
de151cf6 | 1801 | { |
03af84fe | 1802 | #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */ |
058d88c4 | 1803 | struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data); |
05394f39 | 1804 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
1805 | struct drm_i915_private *dev_priv = to_i915(dev); |
1806 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b8f9096d | 1807 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
058d88c4 | 1808 | struct i915_vma *vma; |
de151cf6 | 1809 | pgoff_t page_offset; |
82118877 | 1810 | unsigned int flags; |
b8f9096d | 1811 | int ret; |
f65c9168 | 1812 | |
de151cf6 | 1813 | /* We don't use vmf->pgoff since that has the fake offset */ |
058d88c4 | 1814 | page_offset = ((unsigned long)vmf->virtual_address - area->vm_start) >> |
de151cf6 JB |
1815 | PAGE_SHIFT; |
1816 | ||
db53a302 CW |
1817 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1818 | ||
6e4930f6 | 1819 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 1820 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
1821 | * repeat the flush holding the lock in the normal manner to catch cases |
1822 | * where we are gazumped. | |
1823 | */ | |
e95433c7 CW |
1824 | ret = i915_gem_object_wait(obj, |
1825 | I915_WAIT_INTERRUPTIBLE, | |
1826 | MAX_SCHEDULE_TIMEOUT, | |
1827 | NULL); | |
6e4930f6 | 1828 | if (ret) |
b8f9096d CW |
1829 | goto err; |
1830 | ||
40e62d5d CW |
1831 | ret = i915_gem_object_pin_pages(obj); |
1832 | if (ret) | |
1833 | goto err; | |
1834 | ||
b8f9096d CW |
1835 | intel_runtime_pm_get(dev_priv); |
1836 | ||
1837 | ret = i915_mutex_lock_interruptible(dev); | |
1838 | if (ret) | |
1839 | goto err_rpm; | |
6e4930f6 | 1840 | |
eb119bd6 | 1841 | /* Access to snoopable pages through the GTT is incoherent. */ |
0031fb96 | 1842 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) { |
ddeff6ee | 1843 | ret = -EFAULT; |
b8f9096d | 1844 | goto err_unlock; |
eb119bd6 CW |
1845 | } |
1846 | ||
82118877 CW |
1847 | /* If the object is smaller than a couple of partial vma, it is |
1848 | * not worth only creating a single partial vma - we may as well | |
1849 | * clear enough space for the full object. | |
1850 | */ | |
1851 | flags = PIN_MAPPABLE; | |
1852 | if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT) | |
1853 | flags |= PIN_NONBLOCK | PIN_NONFAULT; | |
1854 | ||
a61007a8 | 1855 | /* Now pin it into the GTT as needed */ |
82118877 | 1856 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags); |
a61007a8 CW |
1857 | if (IS_ERR(vma)) { |
1858 | struct i915_ggtt_view view; | |
03af84fe CW |
1859 | unsigned int chunk_size; |
1860 | ||
a61007a8 | 1861 | /* Use a partial view if it is bigger than available space */ |
03af84fe CW |
1862 | chunk_size = MIN_CHUNK_PAGES; |
1863 | if (i915_gem_object_is_tiled(obj)) | |
0ef723cb | 1864 | chunk_size = roundup(chunk_size, tile_row_pages(obj)); |
e7ded2d7 | 1865 | |
c5ad54cf JL |
1866 | memset(&view, 0, sizeof(view)); |
1867 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1868 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1869 | view.params.partial.size = | |
a61007a8 | 1870 | min_t(unsigned int, chunk_size, |
908b1232 | 1871 | vma_pages(area) - view.params.partial.offset); |
c5ad54cf | 1872 | |
aa136d9d CW |
1873 | /* If the partial covers the entire object, just create a |
1874 | * normal VMA. | |
1875 | */ | |
1876 | if (chunk_size >= obj->base.size >> PAGE_SHIFT) | |
1877 | view.type = I915_GGTT_VIEW_NORMAL; | |
1878 | ||
50349247 CW |
1879 | /* Userspace is now writing through an untracked VMA, abandon |
1880 | * all hope that the hardware is able to track future writes. | |
1881 | */ | |
1882 | obj->frontbuffer_ggtt_origin = ORIGIN_CPU; | |
1883 | ||
a61007a8 CW |
1884 | vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
1885 | } | |
058d88c4 CW |
1886 | if (IS_ERR(vma)) { |
1887 | ret = PTR_ERR(vma); | |
b8f9096d | 1888 | goto err_unlock; |
058d88c4 | 1889 | } |
4a684a41 | 1890 | |
c9839303 CW |
1891 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1892 | if (ret) | |
b8f9096d | 1893 | goto err_unpin; |
74898d7e | 1894 | |
49ef5294 | 1895 | ret = i915_vma_get_fence(vma); |
d9e86c0e | 1896 | if (ret) |
b8f9096d | 1897 | goto err_unpin; |
7d1c4804 | 1898 | |
275f039d | 1899 | /* Mark as being mmapped into userspace for later revocation */ |
9c870d03 | 1900 | assert_rpm_wakelock_held(dev_priv); |
275f039d CW |
1901 | if (list_empty(&obj->userfault_link)) |
1902 | list_add(&obj->userfault_link, &dev_priv->mm.userfault_list); | |
275f039d | 1903 | |
b90b91d8 | 1904 | /* Finally, remap it using the new GTT offset */ |
c58305af CW |
1905 | ret = remap_io_mapping(area, |
1906 | area->vm_start + (vma->ggtt_view.params.partial.offset << PAGE_SHIFT), | |
1907 | (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT, | |
1908 | min_t(u64, vma->size, area->vm_end - area->vm_start), | |
1909 | &ggtt->mappable); | |
a61007a8 | 1910 | |
b8f9096d | 1911 | err_unpin: |
058d88c4 | 1912 | __i915_vma_unpin(vma); |
b8f9096d | 1913 | err_unlock: |
de151cf6 | 1914 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
1915 | err_rpm: |
1916 | intel_runtime_pm_put(dev_priv); | |
40e62d5d | 1917 | i915_gem_object_unpin_pages(obj); |
b8f9096d | 1918 | err: |
de151cf6 | 1919 | switch (ret) { |
d9bc7e9f | 1920 | case -EIO: |
2232f031 DV |
1921 | /* |
1922 | * We eat errors when the gpu is terminally wedged to avoid | |
1923 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1924 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1925 | * and so needs to be reported. | |
1926 | */ | |
1927 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1928 | ret = VM_FAULT_SIGBUS; |
1929 | break; | |
1930 | } | |
045e769a | 1931 | case -EAGAIN: |
571c608d DV |
1932 | /* |
1933 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1934 | * handler to reset everything when re-faulting in | |
1935 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1936 | */ |
c715089f CW |
1937 | case 0: |
1938 | case -ERESTARTSYS: | |
bed636ab | 1939 | case -EINTR: |
e79e0fe3 DR |
1940 | case -EBUSY: |
1941 | /* | |
1942 | * EBUSY is ok: this just means that another thread | |
1943 | * already did the job. | |
1944 | */ | |
f65c9168 PZ |
1945 | ret = VM_FAULT_NOPAGE; |
1946 | break; | |
de151cf6 | 1947 | case -ENOMEM: |
f65c9168 PZ |
1948 | ret = VM_FAULT_OOM; |
1949 | break; | |
a7c2e1aa | 1950 | case -ENOSPC: |
45d67817 | 1951 | case -EFAULT: |
f65c9168 PZ |
1952 | ret = VM_FAULT_SIGBUS; |
1953 | break; | |
de151cf6 | 1954 | default: |
a7c2e1aa | 1955 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1956 | ret = VM_FAULT_SIGBUS; |
1957 | break; | |
de151cf6 | 1958 | } |
f65c9168 | 1959 | return ret; |
de151cf6 JB |
1960 | } |
1961 | ||
901782b2 CW |
1962 | /** |
1963 | * i915_gem_release_mmap - remove physical page mappings | |
1964 | * @obj: obj in question | |
1965 | * | |
af901ca1 | 1966 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1967 | * relinquish ownership of the pages back to the system. |
1968 | * | |
1969 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1970 | * object through the GTT and then lose the fence register due to | |
1971 | * resource pressure. Similarly if the object has been moved out of the | |
1972 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1973 | * mapping will then trigger a page fault on the next user access, allowing | |
1974 | * fixup by i915_gem_fault(). | |
1975 | */ | |
d05ca301 | 1976 | void |
05394f39 | 1977 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1978 | { |
275f039d | 1979 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
275f039d | 1980 | |
349f2ccf CW |
1981 | /* Serialisation between user GTT access and our code depends upon |
1982 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1983 | * pagefault then has to wait until we release the mutex. | |
9c870d03 CW |
1984 | * |
1985 | * Note that RPM complicates somewhat by adding an additional | |
1986 | * requirement that operations to the GGTT be made holding the RPM | |
1987 | * wakeref. | |
349f2ccf | 1988 | */ |
275f039d | 1989 | lockdep_assert_held(&i915->drm.struct_mutex); |
9c870d03 | 1990 | intel_runtime_pm_get(i915); |
349f2ccf | 1991 | |
3594a3e2 | 1992 | if (list_empty(&obj->userfault_link)) |
9c870d03 | 1993 | goto out; |
901782b2 | 1994 | |
3594a3e2 | 1995 | list_del_init(&obj->userfault_link); |
6796cb16 DR |
1996 | drm_vma_node_unmap(&obj->base.vma_node, |
1997 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1998 | |
1999 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
2000 | * memory transactions from userspace before we return. The TLB | |
2001 | * flushing implied above by changing the PTE above *should* be | |
2002 | * sufficient, an extra barrier here just provides us with a bit | |
2003 | * of paranoid documentation about our requirement to serialise | |
2004 | * memory writes before touching registers / GSM. | |
2005 | */ | |
2006 | wmb(); | |
9c870d03 CW |
2007 | |
2008 | out: | |
2009 | intel_runtime_pm_put(i915); | |
901782b2 CW |
2010 | } |
2011 | ||
7c108fd8 | 2012 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) |
eedd10f4 | 2013 | { |
3594a3e2 | 2014 | struct drm_i915_gem_object *obj, *on; |
7c108fd8 | 2015 | int i; |
eedd10f4 | 2016 | |
3594a3e2 CW |
2017 | /* |
2018 | * Only called during RPM suspend. All users of the userfault_list | |
2019 | * must be holding an RPM wakeref to ensure that this can not | |
2020 | * run concurrently with themselves (and use the struct_mutex for | |
2021 | * protection between themselves). | |
2022 | */ | |
275f039d | 2023 | |
3594a3e2 CW |
2024 | list_for_each_entry_safe(obj, on, |
2025 | &dev_priv->mm.userfault_list, userfault_link) { | |
2026 | list_del_init(&obj->userfault_link); | |
275f039d CW |
2027 | drm_vma_node_unmap(&obj->base.vma_node, |
2028 | obj->base.dev->anon_inode->i_mapping); | |
275f039d | 2029 | } |
7c108fd8 CW |
2030 | |
2031 | /* The fence will be lost when the device powers down. If any were | |
2032 | * in use by hardware (i.e. they are pinned), we should not be powering | |
2033 | * down! All other fences will be reacquired by the user upon waking. | |
2034 | */ | |
2035 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
2036 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
2037 | ||
2038 | if (WARN_ON(reg->pin_count)) | |
2039 | continue; | |
2040 | ||
2041 | if (!reg->vma) | |
2042 | continue; | |
2043 | ||
2044 | GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link)); | |
2045 | reg->dirty = true; | |
2046 | } | |
eedd10f4 CW |
2047 | } |
2048 | ||
ad1a7d20 CW |
2049 | /** |
2050 | * i915_gem_get_ggtt_size - return required global GTT size for an object | |
a9f1481f | 2051 | * @dev_priv: i915 device |
ad1a7d20 CW |
2052 | * @size: object size |
2053 | * @tiling_mode: tiling mode | |
2054 | * | |
2055 | * Return the required global GTT size for an object, taking into account | |
2056 | * potential fence register mapping. | |
2057 | */ | |
a9f1481f CW |
2058 | u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, |
2059 | u64 size, int tiling_mode) | |
92b88aeb | 2060 | { |
ad1a7d20 | 2061 | u64 ggtt_size; |
92b88aeb | 2062 | |
ad1a7d20 CW |
2063 | GEM_BUG_ON(size == 0); |
2064 | ||
a9f1481f | 2065 | if (INTEL_GEN(dev_priv) >= 4 || |
e28f8711 CW |
2066 | tiling_mode == I915_TILING_NONE) |
2067 | return size; | |
92b88aeb CW |
2068 | |
2069 | /* Previous chips need a power-of-two fence region when tiling */ | |
a9f1481f | 2070 | if (IS_GEN3(dev_priv)) |
ad1a7d20 | 2071 | ggtt_size = 1024*1024; |
92b88aeb | 2072 | else |
ad1a7d20 | 2073 | ggtt_size = 512*1024; |
92b88aeb | 2074 | |
ad1a7d20 CW |
2075 | while (ggtt_size < size) |
2076 | ggtt_size <<= 1; | |
92b88aeb | 2077 | |
ad1a7d20 | 2078 | return ggtt_size; |
92b88aeb CW |
2079 | } |
2080 | ||
de151cf6 | 2081 | /** |
ad1a7d20 | 2082 | * i915_gem_get_ggtt_alignment - return required global GTT alignment |
a9f1481f | 2083 | * @dev_priv: i915 device |
14bb2c11 TU |
2084 | * @size: object size |
2085 | * @tiling_mode: tiling mode | |
ad1a7d20 | 2086 | * @fenced: is fenced alignment required or not |
de151cf6 | 2087 | * |
ad1a7d20 | 2088 | * Return the required global GTT alignment for an object, taking into account |
5e783301 | 2089 | * potential fence register mapping. |
de151cf6 | 2090 | */ |
a9f1481f | 2091 | u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, |
ad1a7d20 | 2092 | int tiling_mode, bool fenced) |
de151cf6 | 2093 | { |
ad1a7d20 CW |
2094 | GEM_BUG_ON(size == 0); |
2095 | ||
de151cf6 JB |
2096 | /* |
2097 | * Minimum alignment is 4k (GTT page size), but might be greater | |
2098 | * if a fence register is needed for the object. | |
2099 | */ | |
73f67aa8 JN |
2100 | if (INTEL_GEN(dev_priv) >= 4 || |
2101 | (!fenced && (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))) || | |
e28f8711 | 2102 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
2103 | return 4096; |
2104 | ||
a00b10c3 CW |
2105 | /* |
2106 | * Previous chips need to be aligned to the size of the smallest | |
2107 | * fence register that can contain the object. | |
2108 | */ | |
a9f1481f | 2109 | return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode); |
a00b10c3 CW |
2110 | } |
2111 | ||
d8cb5086 CW |
2112 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2113 | { | |
fac5e23e | 2114 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 2115 | int err; |
da494d7c | 2116 | |
f3f6184c CW |
2117 | err = drm_gem_create_mmap_offset(&obj->base); |
2118 | if (!err) | |
2119 | return 0; | |
d8cb5086 | 2120 | |
f3f6184c CW |
2121 | /* We can idle the GPU locklessly to flush stale objects, but in order |
2122 | * to claim that space for ourselves, we need to take the big | |
2123 | * struct_mutex to free the requests+objects and allocate our slot. | |
d8cb5086 | 2124 | */ |
ea746f36 | 2125 | err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE); |
f3f6184c CW |
2126 | if (err) |
2127 | return err; | |
2128 | ||
2129 | err = i915_mutex_lock_interruptible(&dev_priv->drm); | |
2130 | if (!err) { | |
2131 | i915_gem_retire_requests(dev_priv); | |
2132 | err = drm_gem_create_mmap_offset(&obj->base); | |
2133 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
2134 | } | |
da494d7c | 2135 | |
f3f6184c | 2136 | return err; |
d8cb5086 CW |
2137 | } |
2138 | ||
2139 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2140 | { | |
d8cb5086 CW |
2141 | drm_gem_free_mmap_offset(&obj->base); |
2142 | } | |
2143 | ||
da6b51d0 | 2144 | int |
ff72145b DA |
2145 | i915_gem_mmap_gtt(struct drm_file *file, |
2146 | struct drm_device *dev, | |
da6b51d0 | 2147 | uint32_t handle, |
ff72145b | 2148 | uint64_t *offset) |
de151cf6 | 2149 | { |
05394f39 | 2150 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2151 | int ret; |
2152 | ||
03ac0642 | 2153 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
2154 | if (!obj) |
2155 | return -ENOENT; | |
ab18282d | 2156 | |
d8cb5086 | 2157 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
2158 | if (ret == 0) |
2159 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 2160 | |
f0cd5182 | 2161 | i915_gem_object_put(obj); |
1d7cfea1 | 2162 | return ret; |
de151cf6 JB |
2163 | } |
2164 | ||
ff72145b DA |
2165 | /** |
2166 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2167 | * @dev: DRM device | |
2168 | * @data: GTT mapping ioctl data | |
2169 | * @file: GEM object info | |
2170 | * | |
2171 | * Simply returns the fake offset to userspace so it can mmap it. | |
2172 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2173 | * up so we can get faults in the handler above. | |
2174 | * | |
2175 | * The fault handler will take care of binding the object into the GTT | |
2176 | * (since it may have been evicted to make room for something), allocating | |
2177 | * a fence register, and mapping the appropriate aperture address into | |
2178 | * userspace. | |
2179 | */ | |
2180 | int | |
2181 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2182 | struct drm_file *file) | |
2183 | { | |
2184 | struct drm_i915_gem_mmap_gtt *args = data; | |
2185 | ||
da6b51d0 | 2186 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2187 | } |
2188 | ||
225067ee DV |
2189 | /* Immediately discard the backing storage */ |
2190 | static void | |
2191 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2192 | { |
4d6294bf | 2193 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2194 | |
4d6294bf CW |
2195 | if (obj->base.filp == NULL) |
2196 | return; | |
e5281ccd | 2197 | |
225067ee DV |
2198 | /* Our goal here is to return as much of the memory as |
2199 | * is possible back to the system as we are called from OOM. | |
2200 | * To do this we must instruct the shmfs to drop all of its | |
2201 | * backing pages, *now*. | |
2202 | */ | |
5537252b | 2203 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
a4f5ea64 | 2204 | obj->mm.madv = __I915_MADV_PURGED; |
225067ee | 2205 | } |
e5281ccd | 2206 | |
5537252b | 2207 | /* Try to discard unwanted pages */ |
03ac84f1 | 2208 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
225067ee | 2209 | { |
5537252b CW |
2210 | struct address_space *mapping; |
2211 | ||
1233e2db CW |
2212 | lockdep_assert_held(&obj->mm.lock); |
2213 | GEM_BUG_ON(obj->mm.pages); | |
2214 | ||
a4f5ea64 | 2215 | switch (obj->mm.madv) { |
5537252b CW |
2216 | case I915_MADV_DONTNEED: |
2217 | i915_gem_object_truncate(obj); | |
2218 | case __I915_MADV_PURGED: | |
2219 | return; | |
2220 | } | |
2221 | ||
2222 | if (obj->base.filp == NULL) | |
2223 | return; | |
2224 | ||
93c76a3d | 2225 | mapping = obj->base.filp->f_mapping, |
5537252b | 2226 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
e5281ccd CW |
2227 | } |
2228 | ||
5cdf5881 | 2229 | static void |
03ac84f1 CW |
2230 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj, |
2231 | struct sg_table *pages) | |
673a394b | 2232 | { |
85d1225e DG |
2233 | struct sgt_iter sgt_iter; |
2234 | struct page *page; | |
1286ff73 | 2235 | |
2b3c8317 | 2236 | __i915_gem_object_release_shmem(obj, pages); |
673a394b | 2237 | |
03ac84f1 | 2238 | i915_gem_gtt_finish_pages(obj, pages); |
e2273302 | 2239 | |
6dacfd2f | 2240 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2241 | i915_gem_object_save_bit_17_swizzle(obj, pages); |
280b713b | 2242 | |
03ac84f1 | 2243 | for_each_sgt_page(page, sgt_iter, pages) { |
a4f5ea64 | 2244 | if (obj->mm.dirty) |
9da3da66 | 2245 | set_page_dirty(page); |
3ef94daa | 2246 | |
a4f5ea64 | 2247 | if (obj->mm.madv == I915_MADV_WILLNEED) |
9da3da66 | 2248 | mark_page_accessed(page); |
3ef94daa | 2249 | |
09cbfeaf | 2250 | put_page(page); |
3ef94daa | 2251 | } |
a4f5ea64 | 2252 | obj->mm.dirty = false; |
673a394b | 2253 | |
03ac84f1 CW |
2254 | sg_free_table(pages); |
2255 | kfree(pages); | |
37e680a1 | 2256 | } |
6c085a72 | 2257 | |
96d77634 CW |
2258 | static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj) |
2259 | { | |
2260 | struct radix_tree_iter iter; | |
2261 | void **slot; | |
2262 | ||
a4f5ea64 CW |
2263 | radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0) |
2264 | radix_tree_delete(&obj->mm.get_page.radix, iter.index); | |
96d77634 CW |
2265 | } |
2266 | ||
548625ee CW |
2267 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, |
2268 | enum i915_mm_subclass subclass) | |
37e680a1 | 2269 | { |
03ac84f1 | 2270 | struct sg_table *pages; |
37e680a1 | 2271 | |
a4f5ea64 | 2272 | if (i915_gem_object_has_pinned_pages(obj)) |
03ac84f1 | 2273 | return; |
a5570178 | 2274 | |
15717de2 | 2275 | GEM_BUG_ON(obj->bind_count); |
1233e2db CW |
2276 | if (!READ_ONCE(obj->mm.pages)) |
2277 | return; | |
2278 | ||
2279 | /* May be called by shrinker from within get_pages() (on another bo) */ | |
548625ee | 2280 | mutex_lock_nested(&obj->mm.lock, subclass); |
1233e2db CW |
2281 | if (unlikely(atomic_read(&obj->mm.pages_pin_count))) |
2282 | goto unlock; | |
3e123027 | 2283 | |
a2165e31 CW |
2284 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2285 | * array, hence protect them from being reaped by removing them from gtt | |
2286 | * lists early. */ | |
03ac84f1 CW |
2287 | pages = fetch_and_zero(&obj->mm.pages); |
2288 | GEM_BUG_ON(!pages); | |
a2165e31 | 2289 | |
a4f5ea64 | 2290 | if (obj->mm.mapping) { |
4b30cb23 CW |
2291 | void *ptr; |
2292 | ||
a4f5ea64 | 2293 | ptr = ptr_mask_bits(obj->mm.mapping); |
4b30cb23 CW |
2294 | if (is_vmalloc_addr(ptr)) |
2295 | vunmap(ptr); | |
fb8621d3 | 2296 | else |
4b30cb23 CW |
2297 | kunmap(kmap_to_page(ptr)); |
2298 | ||
a4f5ea64 | 2299 | obj->mm.mapping = NULL; |
0a798eb9 CW |
2300 | } |
2301 | ||
96d77634 CW |
2302 | __i915_gem_object_reset_page_iter(obj); |
2303 | ||
03ac84f1 | 2304 | obj->ops->put_pages(obj, pages); |
1233e2db CW |
2305 | unlock: |
2306 | mutex_unlock(&obj->mm.lock); | |
6c085a72 CW |
2307 | } |
2308 | ||
4ff340f0 | 2309 | static unsigned int swiotlb_max_size(void) |
871dfbd6 CW |
2310 | { |
2311 | #if IS_ENABLED(CONFIG_SWIOTLB) | |
2312 | return rounddown(swiotlb_nr_tbl() << IO_TLB_SHIFT, PAGE_SIZE); | |
2313 | #else | |
2314 | return 0; | |
2315 | #endif | |
2316 | } | |
2317 | ||
0c40ce13 TU |
2318 | static void i915_sg_trim(struct sg_table *orig_st) |
2319 | { | |
2320 | struct sg_table new_st; | |
2321 | struct scatterlist *sg, *new_sg; | |
2322 | unsigned int i; | |
2323 | ||
2324 | if (orig_st->nents == orig_st->orig_nents) | |
2325 | return; | |
2326 | ||
2327 | if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL)) | |
2328 | return; | |
2329 | ||
2330 | new_sg = new_st.sgl; | |
2331 | for_each_sg(orig_st->sgl, sg, orig_st->nents, i) { | |
2332 | sg_set_page(new_sg, sg_page(sg), sg->length, 0); | |
2333 | /* called before being DMA mapped, no need to copy sg->dma_* */ | |
2334 | new_sg = sg_next(new_sg); | |
2335 | } | |
2336 | ||
2337 | sg_free_table(orig_st); | |
2338 | ||
2339 | *orig_st = new_st; | |
2340 | } | |
2341 | ||
03ac84f1 | 2342 | static struct sg_table * |
6c085a72 | 2343 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2344 | { |
fac5e23e | 2345 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d766ef53 CW |
2346 | const unsigned long page_count = obj->base.size / PAGE_SIZE; |
2347 | unsigned long i; | |
e5281ccd | 2348 | struct address_space *mapping; |
9da3da66 CW |
2349 | struct sg_table *st; |
2350 | struct scatterlist *sg; | |
85d1225e | 2351 | struct sgt_iter sgt_iter; |
e5281ccd | 2352 | struct page *page; |
90797e6d | 2353 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
4ff340f0 | 2354 | unsigned int max_segment; |
e2273302 | 2355 | int ret; |
6c085a72 | 2356 | gfp_t gfp; |
e5281ccd | 2357 | |
6c085a72 CW |
2358 | /* Assert that the object is not currently in any GPU domain. As it |
2359 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2360 | * a GPU cache | |
2361 | */ | |
03ac84f1 CW |
2362 | GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2363 | GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
6c085a72 | 2364 | |
871dfbd6 CW |
2365 | max_segment = swiotlb_max_size(); |
2366 | if (!max_segment) | |
4ff340f0 | 2367 | max_segment = rounddown(UINT_MAX, PAGE_SIZE); |
871dfbd6 | 2368 | |
9da3da66 CW |
2369 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2370 | if (st == NULL) | |
03ac84f1 | 2371 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2372 | |
d766ef53 | 2373 | rebuild_st: |
9da3da66 | 2374 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2375 | kfree(st); |
03ac84f1 | 2376 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2377 | } |
e5281ccd | 2378 | |
9da3da66 CW |
2379 | /* Get the list of pages out of our struct file. They'll be pinned |
2380 | * at this point until we release them. | |
2381 | * | |
2382 | * Fail silently without starting the shrinker | |
2383 | */ | |
93c76a3d | 2384 | mapping = obj->base.filp->f_mapping; |
c62d2555 | 2385 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2386 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2387 | sg = st->sgl; |
2388 | st->nents = 0; | |
2389 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2390 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2391 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2392 | i915_gem_shrink(dev_priv, |
2393 | page_count, | |
2394 | I915_SHRINK_BOUND | | |
2395 | I915_SHRINK_UNBOUND | | |
2396 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2397 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2398 | } | |
2399 | if (IS_ERR(page)) { | |
2400 | /* We've tried hard to allocate the memory by reaping | |
2401 | * our own buffer, now let the real VM do its job and | |
2402 | * go down in flames if truly OOM. | |
2403 | */ | |
f461d1be | 2404 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2405 | if (IS_ERR(page)) { |
2406 | ret = PTR_ERR(page); | |
b17993b7 | 2407 | goto err_sg; |
e2273302 | 2408 | } |
6c085a72 | 2409 | } |
871dfbd6 CW |
2410 | if (!i || |
2411 | sg->length >= max_segment || | |
2412 | page_to_pfn(page) != last_pfn + 1) { | |
90797e6d ID |
2413 | if (i) |
2414 | sg = sg_next(sg); | |
2415 | st->nents++; | |
2416 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2417 | } else { | |
2418 | sg->length += PAGE_SIZE; | |
2419 | } | |
2420 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2421 | |
2422 | /* Check that the i965g/gm workaround works. */ | |
2423 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2424 | } |
871dfbd6 | 2425 | if (sg) /* loop terminated early; short sg table */ |
426729dc | 2426 | sg_mark_end(sg); |
74ce6b6c | 2427 | |
0c40ce13 TU |
2428 | /* Trim unused sg entries to avoid wasting memory. */ |
2429 | i915_sg_trim(st); | |
2430 | ||
03ac84f1 | 2431 | ret = i915_gem_gtt_prepare_pages(obj, st); |
d766ef53 CW |
2432 | if (ret) { |
2433 | /* DMA remapping failed? One possible cause is that | |
2434 | * it could not reserve enough large entries, asking | |
2435 | * for PAGE_SIZE chunks instead may be helpful. | |
2436 | */ | |
2437 | if (max_segment > PAGE_SIZE) { | |
2438 | for_each_sgt_page(page, sgt_iter, st) | |
2439 | put_page(page); | |
2440 | sg_free_table(st); | |
2441 | ||
2442 | max_segment = PAGE_SIZE; | |
2443 | goto rebuild_st; | |
2444 | } else { | |
2445 | dev_warn(&dev_priv->drm.pdev->dev, | |
2446 | "Failed to DMA remap %lu pages\n", | |
2447 | page_count); | |
2448 | goto err_pages; | |
2449 | } | |
2450 | } | |
e2273302 | 2451 | |
6dacfd2f | 2452 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2453 | i915_gem_object_do_bit_17_swizzle(obj, st); |
e5281ccd | 2454 | |
03ac84f1 | 2455 | return st; |
e5281ccd | 2456 | |
b17993b7 | 2457 | err_sg: |
90797e6d | 2458 | sg_mark_end(sg); |
b17993b7 | 2459 | err_pages: |
85d1225e DG |
2460 | for_each_sgt_page(page, sgt_iter, st) |
2461 | put_page(page); | |
9da3da66 CW |
2462 | sg_free_table(st); |
2463 | kfree(st); | |
0820baf3 CW |
2464 | |
2465 | /* shmemfs first checks if there is enough memory to allocate the page | |
2466 | * and reports ENOSPC should there be insufficient, along with the usual | |
2467 | * ENOMEM for a genuine allocation failure. | |
2468 | * | |
2469 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2470 | * space and so want to translate the error from shmemfs back to our | |
2471 | * usual understanding of ENOMEM. | |
2472 | */ | |
e2273302 ID |
2473 | if (ret == -ENOSPC) |
2474 | ret = -ENOMEM; | |
2475 | ||
03ac84f1 CW |
2476 | return ERR_PTR(ret); |
2477 | } | |
2478 | ||
2479 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, | |
2480 | struct sg_table *pages) | |
2481 | { | |
1233e2db | 2482 | lockdep_assert_held(&obj->mm.lock); |
03ac84f1 CW |
2483 | |
2484 | obj->mm.get_page.sg_pos = pages->sgl; | |
2485 | obj->mm.get_page.sg_idx = 0; | |
2486 | ||
2487 | obj->mm.pages = pages; | |
2c3a3f44 CW |
2488 | |
2489 | if (i915_gem_object_is_tiled(obj) && | |
2490 | to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
2491 | GEM_BUG_ON(obj->mm.quirked); | |
2492 | __i915_gem_object_pin_pages(obj); | |
2493 | obj->mm.quirked = true; | |
2494 | } | |
03ac84f1 CW |
2495 | } |
2496 | ||
2497 | static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2498 | { | |
2499 | struct sg_table *pages; | |
2500 | ||
2c3a3f44 CW |
2501 | GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); |
2502 | ||
03ac84f1 CW |
2503 | if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { |
2504 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); | |
2505 | return -EFAULT; | |
2506 | } | |
2507 | ||
2508 | pages = obj->ops->get_pages(obj); | |
2509 | if (unlikely(IS_ERR(pages))) | |
2510 | return PTR_ERR(pages); | |
2511 | ||
2512 | __i915_gem_object_set_pages(obj, pages); | |
2513 | return 0; | |
673a394b EA |
2514 | } |
2515 | ||
37e680a1 | 2516 | /* Ensure that the associated pages are gathered from the backing storage |
1233e2db | 2517 | * and pinned into our object. i915_gem_object_pin_pages() may be called |
37e680a1 | 2518 | * multiple times before they are released by a single call to |
1233e2db | 2519 | * i915_gem_object_unpin_pages() - once the pages are no longer referenced |
37e680a1 CW |
2520 | * either as a result of memory pressure (reaping pages under the shrinker) |
2521 | * or as the object is itself released. | |
2522 | */ | |
a4f5ea64 | 2523 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
37e680a1 | 2524 | { |
03ac84f1 | 2525 | int err; |
37e680a1 | 2526 | |
1233e2db CW |
2527 | err = mutex_lock_interruptible(&obj->mm.lock); |
2528 | if (err) | |
2529 | return err; | |
4c7d62c6 | 2530 | |
2c3a3f44 CW |
2531 | if (unlikely(!obj->mm.pages)) { |
2532 | err = ____i915_gem_object_get_pages(obj); | |
2533 | if (err) | |
2534 | goto unlock; | |
37e680a1 | 2535 | |
2c3a3f44 CW |
2536 | smp_mb__before_atomic(); |
2537 | } | |
2538 | atomic_inc(&obj->mm.pages_pin_count); | |
ee286370 | 2539 | |
1233e2db CW |
2540 | unlock: |
2541 | mutex_unlock(&obj->mm.lock); | |
03ac84f1 | 2542 | return err; |
673a394b EA |
2543 | } |
2544 | ||
dd6034c6 | 2545 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
d31d7cb1 CW |
2546 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, |
2547 | enum i915_map_type type) | |
dd6034c6 DG |
2548 | { |
2549 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
a4f5ea64 | 2550 | struct sg_table *sgt = obj->mm.pages; |
85d1225e DG |
2551 | struct sgt_iter sgt_iter; |
2552 | struct page *page; | |
b338fa47 DG |
2553 | struct page *stack_pages[32]; |
2554 | struct page **pages = stack_pages; | |
dd6034c6 | 2555 | unsigned long i = 0; |
d31d7cb1 | 2556 | pgprot_t pgprot; |
dd6034c6 DG |
2557 | void *addr; |
2558 | ||
2559 | /* A single page can always be kmapped */ | |
d31d7cb1 | 2560 | if (n_pages == 1 && type == I915_MAP_WB) |
dd6034c6 DG |
2561 | return kmap(sg_page(sgt->sgl)); |
2562 | ||
b338fa47 DG |
2563 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2564 | /* Too big for stack -- allocate temporary array instead */ | |
2565 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2566 | if (!pages) | |
2567 | return NULL; | |
2568 | } | |
dd6034c6 | 2569 | |
85d1225e DG |
2570 | for_each_sgt_page(page, sgt_iter, sgt) |
2571 | pages[i++] = page; | |
dd6034c6 DG |
2572 | |
2573 | /* Check that we have the expected number of pages */ | |
2574 | GEM_BUG_ON(i != n_pages); | |
2575 | ||
d31d7cb1 CW |
2576 | switch (type) { |
2577 | case I915_MAP_WB: | |
2578 | pgprot = PAGE_KERNEL; | |
2579 | break; | |
2580 | case I915_MAP_WC: | |
2581 | pgprot = pgprot_writecombine(PAGE_KERNEL_IO); | |
2582 | break; | |
2583 | } | |
2584 | addr = vmap(pages, n_pages, 0, pgprot); | |
dd6034c6 | 2585 | |
b338fa47 DG |
2586 | if (pages != stack_pages) |
2587 | drm_free_large(pages); | |
dd6034c6 DG |
2588 | |
2589 | return addr; | |
2590 | } | |
2591 | ||
2592 | /* get, pin, and map the pages of the object into kernel space */ | |
d31d7cb1 CW |
2593 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
2594 | enum i915_map_type type) | |
0a798eb9 | 2595 | { |
d31d7cb1 CW |
2596 | enum i915_map_type has_type; |
2597 | bool pinned; | |
2598 | void *ptr; | |
0a798eb9 CW |
2599 | int ret; |
2600 | ||
d31d7cb1 | 2601 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); |
0a798eb9 | 2602 | |
1233e2db | 2603 | ret = mutex_lock_interruptible(&obj->mm.lock); |
0a798eb9 CW |
2604 | if (ret) |
2605 | return ERR_PTR(ret); | |
2606 | ||
1233e2db CW |
2607 | pinned = true; |
2608 | if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) { | |
2c3a3f44 CW |
2609 | if (unlikely(!obj->mm.pages)) { |
2610 | ret = ____i915_gem_object_get_pages(obj); | |
2611 | if (ret) | |
2612 | goto err_unlock; | |
1233e2db | 2613 | |
2c3a3f44 CW |
2614 | smp_mb__before_atomic(); |
2615 | } | |
2616 | atomic_inc(&obj->mm.pages_pin_count); | |
1233e2db CW |
2617 | pinned = false; |
2618 | } | |
2619 | GEM_BUG_ON(!obj->mm.pages); | |
0a798eb9 | 2620 | |
a4f5ea64 | 2621 | ptr = ptr_unpack_bits(obj->mm.mapping, has_type); |
d31d7cb1 CW |
2622 | if (ptr && has_type != type) { |
2623 | if (pinned) { | |
2624 | ret = -EBUSY; | |
1233e2db | 2625 | goto err_unpin; |
0a798eb9 | 2626 | } |
d31d7cb1 CW |
2627 | |
2628 | if (is_vmalloc_addr(ptr)) | |
2629 | vunmap(ptr); | |
2630 | else | |
2631 | kunmap(kmap_to_page(ptr)); | |
2632 | ||
a4f5ea64 | 2633 | ptr = obj->mm.mapping = NULL; |
0a798eb9 CW |
2634 | } |
2635 | ||
d31d7cb1 CW |
2636 | if (!ptr) { |
2637 | ptr = i915_gem_object_map(obj, type); | |
2638 | if (!ptr) { | |
2639 | ret = -ENOMEM; | |
1233e2db | 2640 | goto err_unpin; |
d31d7cb1 CW |
2641 | } |
2642 | ||
a4f5ea64 | 2643 | obj->mm.mapping = ptr_pack_bits(ptr, type); |
d31d7cb1 CW |
2644 | } |
2645 | ||
1233e2db CW |
2646 | out_unlock: |
2647 | mutex_unlock(&obj->mm.lock); | |
d31d7cb1 CW |
2648 | return ptr; |
2649 | ||
1233e2db CW |
2650 | err_unpin: |
2651 | atomic_dec(&obj->mm.pages_pin_count); | |
2652 | err_unlock: | |
2653 | ptr = ERR_PTR(ret); | |
2654 | goto out_unlock; | |
0a798eb9 CW |
2655 | } |
2656 | ||
7b4d3a16 | 2657 | static bool i915_context_is_banned(const struct i915_gem_context *ctx) |
be62acb4 | 2658 | { |
bc1d53c6 | 2659 | if (ctx->banned) |
be62acb4 MK |
2660 | return true; |
2661 | ||
bc1d53c6 | 2662 | if (!ctx->bannable) |
e5e1fc47 MK |
2663 | return false; |
2664 | ||
bc1d53c6 | 2665 | if (ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD) { |
e5e1fc47 MK |
2666 | DRM_DEBUG("context hanging too often, banning!\n"); |
2667 | return true; | |
2668 | } | |
2669 | ||
be62acb4 MK |
2670 | return false; |
2671 | } | |
2672 | ||
e5e1fc47 | 2673 | static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx) |
aa60c664 | 2674 | { |
bc1d53c6 | 2675 | ctx->ban_score += CONTEXT_SCORE_GUILTY; |
e5e1fc47 | 2676 | |
bc1d53c6 MK |
2677 | ctx->banned = i915_context_is_banned(ctx); |
2678 | ctx->guilty_count++; | |
b083a087 MK |
2679 | |
2680 | DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n", | |
bc1d53c6 MK |
2681 | ctx->name, ctx->ban_score, |
2682 | yesno(ctx->banned)); | |
b083a087 | 2683 | |
d9e9da64 | 2684 | if (!ctx->banned || IS_ERR_OR_NULL(ctx->file_priv)) |
b083a087 MK |
2685 | return; |
2686 | ||
d9e9da64 CW |
2687 | ctx->file_priv->context_bans++; |
2688 | DRM_DEBUG_DRIVER("client %s has had %d context banned\n", | |
2689 | ctx->name, ctx->file_priv->context_bans); | |
e5e1fc47 MK |
2690 | } |
2691 | ||
2692 | static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx) | |
2693 | { | |
bc1d53c6 | 2694 | ctx->active_count++; |
aa60c664 MK |
2695 | } |
2696 | ||
8d9fc7fd | 2697 | struct drm_i915_gem_request * |
0bc40be8 | 2698 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2699 | { |
4db080f9 CW |
2700 | struct drm_i915_gem_request *request; |
2701 | ||
f69a02c9 CW |
2702 | /* We are called by the error capture and reset at a random |
2703 | * point in time. In particular, note that neither is crucially | |
2704 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2705 | * assume that no more writes can happen (we waited long enough for | |
2706 | * all writes that were in transaction to be flushed) - adding an | |
2707 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2708 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2709 | */ | |
73cb9701 | 2710 | list_for_each_entry(request, &engine->timeline->requests, link) { |
80b204bc | 2711 | if (__i915_gem_request_completed(request)) |
4db080f9 | 2712 | continue; |
aa60c664 | 2713 | |
b6b0fac0 | 2714 | return request; |
4db080f9 | 2715 | } |
b6b0fac0 MK |
2716 | |
2717 | return NULL; | |
2718 | } | |
2719 | ||
821ed7df CW |
2720 | static void reset_request(struct drm_i915_gem_request *request) |
2721 | { | |
2722 | void *vaddr = request->ring->vaddr; | |
2723 | u32 head; | |
2724 | ||
2725 | /* As this request likely depends on state from the lost | |
2726 | * context, clear out all the user operations leaving the | |
2727 | * breadcrumb at the end (so we get the fence notifications). | |
2728 | */ | |
2729 | head = request->head; | |
2730 | if (request->postfix < head) { | |
2731 | memset(vaddr + head, 0, request->ring->size - head); | |
2732 | head = 0; | |
2733 | } | |
2734 | memset(vaddr + head, 0, request->postfix - head); | |
2735 | } | |
2736 | ||
2737 | static void i915_gem_reset_engine(struct intel_engine_cs *engine) | |
b6b0fac0 MK |
2738 | { |
2739 | struct drm_i915_gem_request *request; | |
821ed7df | 2740 | struct i915_gem_context *incomplete_ctx; |
80b204bc | 2741 | struct intel_timeline *timeline; |
b6b0fac0 MK |
2742 | bool ring_hung; |
2743 | ||
821ed7df CW |
2744 | if (engine->irq_seqno_barrier) |
2745 | engine->irq_seqno_barrier(engine); | |
2746 | ||
0bc40be8 | 2747 | request = i915_gem_find_active_request(engine); |
821ed7df | 2748 | if (!request) |
b6b0fac0 MK |
2749 | return; |
2750 | ||
3fe3b030 MK |
2751 | ring_hung = engine->hangcheck.stalled; |
2752 | if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) { | |
2753 | DRM_DEBUG_DRIVER("%s pardoned, was guilty? %s\n", | |
2754 | engine->name, | |
2755 | yesno(ring_hung)); | |
77c60701 | 2756 | ring_hung = false; |
3fe3b030 | 2757 | } |
77c60701 | 2758 | |
e5e1fc47 MK |
2759 | if (ring_hung) |
2760 | i915_gem_context_mark_guilty(request->ctx); | |
2761 | else | |
2762 | i915_gem_context_mark_innocent(request->ctx); | |
2763 | ||
821ed7df CW |
2764 | if (!ring_hung) |
2765 | return; | |
2766 | ||
2767 | DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", | |
65e4760e | 2768 | engine->name, request->global_seqno); |
821ed7df CW |
2769 | |
2770 | /* Setup the CS to resume from the breadcrumb of the hung request */ | |
2771 | engine->reset_hw(engine, request); | |
2772 | ||
2773 | /* Users of the default context do not rely on logical state | |
2774 | * preserved between batches. They have to emit full state on | |
2775 | * every batch and so it is safe to execute queued requests following | |
2776 | * the hang. | |
2777 | * | |
2778 | * Other contexts preserve state, now corrupt. We want to skip all | |
2779 | * queued requests that reference the corrupt context. | |
2780 | */ | |
2781 | incomplete_ctx = request->ctx; | |
2782 | if (i915_gem_context_is_default(incomplete_ctx)) | |
2783 | return; | |
2784 | ||
73cb9701 | 2785 | list_for_each_entry_continue(request, &engine->timeline->requests, link) |
821ed7df CW |
2786 | if (request->ctx == incomplete_ctx) |
2787 | reset_request(request); | |
80b204bc CW |
2788 | |
2789 | timeline = i915_gem_context_lookup_timeline(incomplete_ctx, engine); | |
2790 | list_for_each_entry(request, &timeline->requests, link) | |
2791 | reset_request(request); | |
4db080f9 | 2792 | } |
aa60c664 | 2793 | |
821ed7df | 2794 | void i915_gem_reset(struct drm_i915_private *dev_priv) |
4db080f9 | 2795 | { |
821ed7df | 2796 | struct intel_engine_cs *engine; |
3b3f1650 | 2797 | enum intel_engine_id id; |
608c1a52 | 2798 | |
4c7d62c6 CW |
2799 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2800 | ||
821ed7df CW |
2801 | i915_gem_retire_requests(dev_priv); |
2802 | ||
3b3f1650 | 2803 | for_each_engine(engine, dev_priv, id) |
821ed7df CW |
2804 | i915_gem_reset_engine(engine); |
2805 | ||
4362f4f6 | 2806 | i915_gem_restore_fences(dev_priv); |
f2a91d1a CW |
2807 | |
2808 | if (dev_priv->gt.awake) { | |
2809 | intel_sanitize_gt_powersave(dev_priv); | |
2810 | intel_enable_gt_powersave(dev_priv); | |
2811 | if (INTEL_GEN(dev_priv) >= 6) | |
2812 | gen6_rps_busy(dev_priv); | |
2813 | } | |
821ed7df CW |
2814 | } |
2815 | ||
2816 | static void nop_submit_request(struct drm_i915_gem_request *request) | |
2817 | { | |
3dcf93f7 CW |
2818 | i915_gem_request_submit(request); |
2819 | intel_engine_init_global_seqno(request->engine, request->global_seqno); | |
821ed7df CW |
2820 | } |
2821 | ||
2822 | static void i915_gem_cleanup_engine(struct intel_engine_cs *engine) | |
2823 | { | |
20e4933c CW |
2824 | /* We need to be sure that no thread is running the old callback as |
2825 | * we install the nop handler (otherwise we would submit a request | |
2826 | * to hardware that will never complete). In order to prevent this | |
2827 | * race, we wait until the machine is idle before making the swap | |
2828 | * (using stop_machine()). | |
2829 | */ | |
821ed7df | 2830 | engine->submit_request = nop_submit_request; |
70c2a24d | 2831 | |
c4b0930b CW |
2832 | /* Mark all pending requests as complete so that any concurrent |
2833 | * (lockless) lookup doesn't try and wait upon the request as we | |
2834 | * reset it. | |
2835 | */ | |
73cb9701 | 2836 | intel_engine_init_global_seqno(engine, |
cb399eab | 2837 | intel_engine_last_submit(engine)); |
c4b0930b | 2838 | |
dcb4c12a OM |
2839 | /* |
2840 | * Clear the execlists queue up before freeing the requests, as those | |
2841 | * are the ones that keep the context and ringbuffer backing objects | |
2842 | * pinned in place. | |
2843 | */ | |
dcb4c12a | 2844 | |
7de1691a | 2845 | if (i915.enable_execlists) { |
663f71e7 CW |
2846 | unsigned long flags; |
2847 | ||
2848 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
2849 | ||
70c2a24d CW |
2850 | i915_gem_request_put(engine->execlist_port[0].request); |
2851 | i915_gem_request_put(engine->execlist_port[1].request); | |
2852 | memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); | |
20311bd3 CW |
2853 | engine->execlist_queue = RB_ROOT; |
2854 | engine->execlist_first = NULL; | |
663f71e7 CW |
2855 | |
2856 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
dcb4c12a | 2857 | } |
673a394b EA |
2858 | } |
2859 | ||
20e4933c | 2860 | static int __i915_gem_set_wedged_BKL(void *data) |
673a394b | 2861 | { |
20e4933c | 2862 | struct drm_i915_private *i915 = data; |
e2f80391 | 2863 | struct intel_engine_cs *engine; |
3b3f1650 | 2864 | enum intel_engine_id id; |
673a394b | 2865 | |
20e4933c CW |
2866 | for_each_engine(engine, i915, id) |
2867 | i915_gem_cleanup_engine(engine); | |
2868 | ||
2869 | return 0; | |
2870 | } | |
2871 | ||
2872 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv) | |
2873 | { | |
821ed7df CW |
2874 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2875 | set_bit(I915_WEDGED, &dev_priv->gpu_error.flags); | |
4db080f9 | 2876 | |
20e4933c | 2877 | stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL); |
dfaae392 | 2878 | |
20e4933c | 2879 | i915_gem_context_lost(dev_priv); |
821ed7df | 2880 | i915_gem_retire_requests(dev_priv); |
20e4933c CW |
2881 | |
2882 | mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); | |
673a394b EA |
2883 | } |
2884 | ||
75ef9da2 | 2885 | static void |
673a394b EA |
2886 | i915_gem_retire_work_handler(struct work_struct *work) |
2887 | { | |
b29c19b6 | 2888 | struct drm_i915_private *dev_priv = |
67d97da3 | 2889 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 2890 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 2891 | |
891b48cf | 2892 | /* Come back later if the device is busy... */ |
b29c19b6 | 2893 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 2894 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 2895 | mutex_unlock(&dev->struct_mutex); |
673a394b | 2896 | } |
67d97da3 CW |
2897 | |
2898 | /* Keep the retire handler running until we are finally idle. | |
2899 | * We do not need to do this test under locking as in the worst-case | |
2900 | * we queue the retire worker once too often. | |
2901 | */ | |
c9615613 CW |
2902 | if (READ_ONCE(dev_priv->gt.awake)) { |
2903 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
2904 | queue_delayed_work(dev_priv->wq, |
2905 | &dev_priv->gt.retire_work, | |
bcb45086 | 2906 | round_jiffies_up_relative(HZ)); |
c9615613 | 2907 | } |
b29c19b6 | 2908 | } |
0a58705b | 2909 | |
b29c19b6 CW |
2910 | static void |
2911 | i915_gem_idle_work_handler(struct work_struct *work) | |
2912 | { | |
2913 | struct drm_i915_private *dev_priv = | |
67d97da3 | 2914 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 2915 | struct drm_device *dev = &dev_priv->drm; |
b4ac5afc | 2916 | struct intel_engine_cs *engine; |
3b3f1650 | 2917 | enum intel_engine_id id; |
67d97da3 CW |
2918 | bool rearm_hangcheck; |
2919 | ||
2920 | if (!READ_ONCE(dev_priv->gt.awake)) | |
2921 | return; | |
2922 | ||
0cb5670b ID |
2923 | /* |
2924 | * Wait for last execlists context complete, but bail out in case a | |
2925 | * new request is submitted. | |
2926 | */ | |
2927 | wait_for(READ_ONCE(dev_priv->gt.active_requests) || | |
2928 | intel_execlists_idle(dev_priv), 10); | |
2929 | ||
28176ef4 | 2930 | if (READ_ONCE(dev_priv->gt.active_requests)) |
67d97da3 CW |
2931 | return; |
2932 | ||
2933 | rearm_hangcheck = | |
2934 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
2935 | ||
2936 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2937 | /* Currently busy, come back later */ | |
2938 | mod_delayed_work(dev_priv->wq, | |
2939 | &dev_priv->gt.idle_work, | |
2940 | msecs_to_jiffies(50)); | |
2941 | goto out_rearm; | |
2942 | } | |
2943 | ||
93c97dc1 ID |
2944 | /* |
2945 | * New request retired after this work handler started, extend active | |
2946 | * period until next instance of the work. | |
2947 | */ | |
2948 | if (work_pending(work)) | |
2949 | goto out_unlock; | |
2950 | ||
28176ef4 | 2951 | if (dev_priv->gt.active_requests) |
67d97da3 | 2952 | goto out_unlock; |
b29c19b6 | 2953 | |
0cb5670b ID |
2954 | if (wait_for(intel_execlists_idle(dev_priv), 10)) |
2955 | DRM_ERROR("Timeout waiting for engines to idle\n"); | |
2956 | ||
3b3f1650 | 2957 | for_each_engine(engine, dev_priv, id) |
67d97da3 | 2958 | i915_gem_batch_pool_fini(&engine->batch_pool); |
35c94185 | 2959 | |
67d97da3 CW |
2960 | GEM_BUG_ON(!dev_priv->gt.awake); |
2961 | dev_priv->gt.awake = false; | |
2962 | rearm_hangcheck = false; | |
30ecad77 | 2963 | |
67d97da3 CW |
2964 | if (INTEL_GEN(dev_priv) >= 6) |
2965 | gen6_rps_idle(dev_priv); | |
2966 | intel_runtime_pm_put(dev_priv); | |
2967 | out_unlock: | |
2968 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 2969 | |
67d97da3 CW |
2970 | out_rearm: |
2971 | if (rearm_hangcheck) { | |
2972 | GEM_BUG_ON(!dev_priv->gt.awake); | |
2973 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 2974 | } |
673a394b EA |
2975 | } |
2976 | ||
b1f788c6 CW |
2977 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
2978 | { | |
2979 | struct drm_i915_gem_object *obj = to_intel_bo(gem); | |
2980 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
2981 | struct i915_vma *vma, *vn; | |
2982 | ||
2983 | mutex_lock(&obj->base.dev->struct_mutex); | |
2984 | list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) | |
2985 | if (vma->vm->file == fpriv) | |
2986 | i915_vma_close(vma); | |
f8a7fde4 CW |
2987 | |
2988 | if (i915_gem_object_is_active(obj) && | |
2989 | !i915_gem_object_has_active_reference(obj)) { | |
2990 | i915_gem_object_set_active_reference(obj); | |
2991 | i915_gem_object_get(obj); | |
2992 | } | |
b1f788c6 CW |
2993 | mutex_unlock(&obj->base.dev->struct_mutex); |
2994 | } | |
2995 | ||
e95433c7 CW |
2996 | static unsigned long to_wait_timeout(s64 timeout_ns) |
2997 | { | |
2998 | if (timeout_ns < 0) | |
2999 | return MAX_SCHEDULE_TIMEOUT; | |
3000 | ||
3001 | if (timeout_ns == 0) | |
3002 | return 0; | |
3003 | ||
3004 | return nsecs_to_jiffies_timeout(timeout_ns); | |
3005 | } | |
3006 | ||
23ba4fd0 BW |
3007 | /** |
3008 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
3009 | * @dev: drm device pointer |
3010 | * @data: ioctl data blob | |
3011 | * @file: drm file pointer | |
23ba4fd0 BW |
3012 | * |
3013 | * Returns 0 if successful, else an error is returned with the remaining time in | |
3014 | * the timeout parameter. | |
3015 | * -ETIME: object is still busy after timeout | |
3016 | * -ERESTARTSYS: signal interrupted the wait | |
3017 | * -ENONENT: object doesn't exist | |
3018 | * Also possible, but rare: | |
3019 | * -EAGAIN: GPU wedged | |
3020 | * -ENOMEM: damn | |
3021 | * -ENODEV: Internal IRQ fail | |
3022 | * -E?: The add request failed | |
3023 | * | |
3024 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
3025 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
3026 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
3027 | * without holding struct_mutex the object may become re-busied before this | |
3028 | * function completes. A similar but shorter * race condition exists in the busy | |
3029 | * ioctl | |
3030 | */ | |
3031 | int | |
3032 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
3033 | { | |
3034 | struct drm_i915_gem_wait *args = data; | |
3035 | struct drm_i915_gem_object *obj; | |
e95433c7 CW |
3036 | ktime_t start; |
3037 | long ret; | |
23ba4fd0 | 3038 | |
11b5d511 DV |
3039 | if (args->flags != 0) |
3040 | return -EINVAL; | |
3041 | ||
03ac0642 | 3042 | obj = i915_gem_object_lookup(file, args->bo_handle); |
033d549b | 3043 | if (!obj) |
23ba4fd0 | 3044 | return -ENOENT; |
23ba4fd0 | 3045 | |
e95433c7 CW |
3046 | start = ktime_get(); |
3047 | ||
3048 | ret = i915_gem_object_wait(obj, | |
3049 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL, | |
3050 | to_wait_timeout(args->timeout_ns), | |
3051 | to_rps_client(file)); | |
3052 | ||
3053 | if (args->timeout_ns > 0) { | |
3054 | args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start)); | |
3055 | if (args->timeout_ns < 0) | |
3056 | args->timeout_ns = 0; | |
b4716185 CW |
3057 | } |
3058 | ||
f0cd5182 | 3059 | i915_gem_object_put(obj); |
ff865885 | 3060 | return ret; |
23ba4fd0 BW |
3061 | } |
3062 | ||
73cb9701 | 3063 | static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) |
4df2faf4 | 3064 | { |
73cb9701 | 3065 | int ret, i; |
4df2faf4 | 3066 | |
73cb9701 CW |
3067 | for (i = 0; i < ARRAY_SIZE(tl->engine); i++) { |
3068 | ret = i915_gem_active_wait(&tl->engine[i].last_request, flags); | |
3069 | if (ret) | |
3070 | return ret; | |
3071 | } | |
62e63007 | 3072 | |
73cb9701 CW |
3073 | return 0; |
3074 | } | |
3075 | ||
3076 | int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags) | |
3077 | { | |
73cb9701 CW |
3078 | int ret; |
3079 | ||
9caa34aa CW |
3080 | if (flags & I915_WAIT_LOCKED) { |
3081 | struct i915_gem_timeline *tl; | |
3082 | ||
3083 | lockdep_assert_held(&i915->drm.struct_mutex); | |
3084 | ||
3085 | list_for_each_entry(tl, &i915->gt.timelines, link) { | |
3086 | ret = wait_for_timeline(tl, flags); | |
3087 | if (ret) | |
3088 | return ret; | |
3089 | } | |
3090 | } else { | |
3091 | ret = wait_for_timeline(&i915->gt.global_timeline, flags); | |
1ec14ad3 CW |
3092 | if (ret) |
3093 | return ret; | |
3094 | } | |
4df2faf4 | 3095 | |
8a1a49f9 | 3096 | return 0; |
4df2faf4 DV |
3097 | } |
3098 | ||
d0da48cf CW |
3099 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3100 | bool force) | |
673a394b | 3101 | { |
673a394b EA |
3102 | /* If we don't have a page list set up, then we're not pinned |
3103 | * to GPU, and we can ignore the cache flush because it'll happen | |
3104 | * again at bind time. | |
3105 | */ | |
a4f5ea64 | 3106 | if (!obj->mm.pages) |
d0da48cf | 3107 | return; |
673a394b | 3108 | |
769ce464 ID |
3109 | /* |
3110 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3111 | * marked as wc by the system, or the system is cache-coherent. | |
3112 | */ | |
6a2c4232 | 3113 | if (obj->stolen || obj->phys_handle) |
d0da48cf | 3114 | return; |
769ce464 | 3115 | |
9c23f7fc CW |
3116 | /* If the GPU is snooping the contents of the CPU cache, |
3117 | * we do not need to manually clear the CPU cache lines. However, | |
3118 | * the caches are only snooped when the render cache is | |
3119 | * flushed/invalidated. As we always have to emit invalidations | |
3120 | * and flushes when moving into and out of the RENDER domain, correct | |
3121 | * snooping behaviour occurs naturally as the result of our domain | |
3122 | * tracking. | |
3123 | */ | |
0f71979a CW |
3124 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3125 | obj->cache_dirty = true; | |
d0da48cf | 3126 | return; |
0f71979a | 3127 | } |
9c23f7fc | 3128 | |
1c5d22f7 | 3129 | trace_i915_gem_object_clflush(obj); |
a4f5ea64 | 3130 | drm_clflush_sg(obj->mm.pages); |
0f71979a | 3131 | obj->cache_dirty = false; |
e47c68e9 EA |
3132 | } |
3133 | ||
3134 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3135 | static void | |
05394f39 | 3136 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3137 | { |
3b5724d7 | 3138 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
1c5d22f7 | 3139 | |
05394f39 | 3140 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3141 | return; |
3142 | ||
63256ec5 | 3143 | /* No actual flushing is required for the GTT write domain. Writes |
3b5724d7 | 3144 | * to it "immediately" go to main memory as far as we know, so there's |
e47c68e9 | 3145 | * no chipset flush. It also doesn't land in render cache. |
63256ec5 CW |
3146 | * |
3147 | * However, we do have to enforce the order so that all writes through | |
3148 | * the GTT land before any writes to the device, such as updates to | |
3149 | * the GATT itself. | |
3b5724d7 CW |
3150 | * |
3151 | * We also have to wait a bit for the writes to land from the GTT. | |
3152 | * An uncached read (i.e. mmio) seems to be ideal for the round-trip | |
3153 | * timing. This issue has only been observed when switching quickly | |
3154 | * between GTT writes and CPU reads from inside the kernel on recent hw, | |
3155 | * and it appears to only affect discrete GTT blocks (i.e. on LLC | |
3156 | * system agents we cannot reproduce this behaviour). | |
e47c68e9 | 3157 | */ |
63256ec5 | 3158 | wmb(); |
3b5724d7 | 3159 | if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) |
3b3f1650 | 3160 | POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base)); |
63256ec5 | 3161 | |
d243ad82 | 3162 | intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT)); |
f99d7069 | 3163 | |
b0dc465f | 3164 | obj->base.write_domain = 0; |
1c5d22f7 | 3165 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3166 | obj->base.read_domains, |
b0dc465f | 3167 | I915_GEM_DOMAIN_GTT); |
e47c68e9 EA |
3168 | } |
3169 | ||
3170 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3171 | static void | |
e62b59e4 | 3172 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3173 | { |
05394f39 | 3174 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3175 | return; |
3176 | ||
d0da48cf | 3177 | i915_gem_clflush_object(obj, obj->pin_display); |
de152b62 | 3178 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3179 | |
b0dc465f | 3180 | obj->base.write_domain = 0; |
1c5d22f7 | 3181 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3182 | obj->base.read_domains, |
b0dc465f | 3183 | I915_GEM_DOMAIN_CPU); |
e47c68e9 EA |
3184 | } |
3185 | ||
2ef7eeaa EA |
3186 | /** |
3187 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3188 | * @obj: object to act on |
3189 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3190 | * |
3191 | * This function returns when the move is complete, including waiting on | |
3192 | * flushes to occur. | |
3193 | */ | |
79e53945 | 3194 | int |
2021746e | 3195 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3196 | { |
1c5d22f7 | 3197 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3198 | int ret; |
2ef7eeaa | 3199 | |
e95433c7 | 3200 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3201 | |
e95433c7 CW |
3202 | ret = i915_gem_object_wait(obj, |
3203 | I915_WAIT_INTERRUPTIBLE | | |
3204 | I915_WAIT_LOCKED | | |
3205 | (write ? I915_WAIT_ALL : 0), | |
3206 | MAX_SCHEDULE_TIMEOUT, | |
3207 | NULL); | |
88241785 CW |
3208 | if (ret) |
3209 | return ret; | |
3210 | ||
c13d87ea CW |
3211 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3212 | return 0; | |
3213 | ||
43566ded CW |
3214 | /* Flush and acquire obj->pages so that we are coherent through |
3215 | * direct access in memory with previous cached writes through | |
3216 | * shmemfs and that our cache domain tracking remains valid. | |
3217 | * For example, if the obj->filp was moved to swap without us | |
3218 | * being notified and releasing the pages, we would mistakenly | |
3219 | * continue to assume that the obj remained out of the CPU cached | |
3220 | * domain. | |
3221 | */ | |
a4f5ea64 | 3222 | ret = i915_gem_object_pin_pages(obj); |
43566ded CW |
3223 | if (ret) |
3224 | return ret; | |
3225 | ||
e62b59e4 | 3226 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3227 | |
d0a57789 CW |
3228 | /* Serialise direct access to this object with the barriers for |
3229 | * coherent writes from the GPU, by effectively invalidating the | |
3230 | * GTT domain upon first access. | |
3231 | */ | |
3232 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3233 | mb(); | |
3234 | ||
05394f39 CW |
3235 | old_write_domain = obj->base.write_domain; |
3236 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3237 | |
e47c68e9 EA |
3238 | /* It should now be out of any other write domains, and we can update |
3239 | * the domain values for our changes. | |
3240 | */ | |
40e62d5d | 3241 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
05394f39 | 3242 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
e47c68e9 | 3243 | if (write) { |
05394f39 CW |
3244 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3245 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
a4f5ea64 | 3246 | obj->mm.dirty = true; |
2ef7eeaa EA |
3247 | } |
3248 | ||
1c5d22f7 CW |
3249 | trace_i915_gem_object_change_domain(obj, |
3250 | old_read_domains, | |
3251 | old_write_domain); | |
3252 | ||
a4f5ea64 | 3253 | i915_gem_object_unpin_pages(obj); |
e47c68e9 EA |
3254 | return 0; |
3255 | } | |
3256 | ||
ef55f92a CW |
3257 | /** |
3258 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3259 | * @obj: object to act on |
3260 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3261 | * |
3262 | * After this function returns, the object will be in the new cache-level | |
3263 | * across all GTT and the contents of the backing storage will be coherent, | |
3264 | * with respect to the new cache-level. In order to keep the backing storage | |
3265 | * coherent for all users, we only allow a single cache level to be set | |
3266 | * globally on the object and prevent it from being changed whilst the | |
3267 | * hardware is reading from the object. That is if the object is currently | |
3268 | * on the scanout it will be set to uncached (or equivalent display | |
3269 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3270 | * that all direct access to the scanout remains coherent. | |
3271 | */ | |
e4ffd173 CW |
3272 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3273 | enum i915_cache_level cache_level) | |
3274 | { | |
aa653a68 | 3275 | struct i915_vma *vma; |
a6a7cc4b | 3276 | int ret; |
e4ffd173 | 3277 | |
4c7d62c6 CW |
3278 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3279 | ||
e4ffd173 | 3280 | if (obj->cache_level == cache_level) |
a6a7cc4b | 3281 | return 0; |
e4ffd173 | 3282 | |
ef55f92a CW |
3283 | /* Inspect the list of currently bound VMA and unbind any that would |
3284 | * be invalid given the new cache-level. This is principally to | |
3285 | * catch the issue of the CS prefetch crossing page boundaries and | |
3286 | * reading an invalid PTE on older architectures. | |
3287 | */ | |
aa653a68 CW |
3288 | restart: |
3289 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3290 | if (!drm_mm_node_allocated(&vma->node)) |
3291 | continue; | |
3292 | ||
20dfbde4 | 3293 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3294 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3295 | return -EBUSY; | |
3296 | } | |
3297 | ||
aa653a68 CW |
3298 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3299 | continue; | |
3300 | ||
3301 | ret = i915_vma_unbind(vma); | |
3302 | if (ret) | |
3303 | return ret; | |
3304 | ||
3305 | /* As unbinding may affect other elements in the | |
3306 | * obj->vma_list (due to side-effects from retiring | |
3307 | * an active vma), play safe and restart the iterator. | |
3308 | */ | |
3309 | goto restart; | |
42d6ab48 CW |
3310 | } |
3311 | ||
ef55f92a CW |
3312 | /* We can reuse the existing drm_mm nodes but need to change the |
3313 | * cache-level on the PTE. We could simply unbind them all and | |
3314 | * rebind with the correct cache-level on next use. However since | |
3315 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3316 | * rewrite the PTE in the belief that doing so tramples upon less | |
3317 | * state and so involves less work. | |
3318 | */ | |
15717de2 | 3319 | if (obj->bind_count) { |
ef55f92a CW |
3320 | /* Before we change the PTE, the GPU must not be accessing it. |
3321 | * If we wait upon the object, we know that all the bound | |
3322 | * VMA are no longer active. | |
3323 | */ | |
e95433c7 CW |
3324 | ret = i915_gem_object_wait(obj, |
3325 | I915_WAIT_INTERRUPTIBLE | | |
3326 | I915_WAIT_LOCKED | | |
3327 | I915_WAIT_ALL, | |
3328 | MAX_SCHEDULE_TIMEOUT, | |
3329 | NULL); | |
e4ffd173 CW |
3330 | if (ret) |
3331 | return ret; | |
3332 | ||
0031fb96 TU |
3333 | if (!HAS_LLC(to_i915(obj->base.dev)) && |
3334 | cache_level != I915_CACHE_NONE) { | |
ef55f92a CW |
3335 | /* Access to snoopable pages through the GTT is |
3336 | * incoherent and on some machines causes a hard | |
3337 | * lockup. Relinquish the CPU mmaping to force | |
3338 | * userspace to refault in the pages and we can | |
3339 | * then double check if the GTT mapping is still | |
3340 | * valid for that pointer access. | |
3341 | */ | |
3342 | i915_gem_release_mmap(obj); | |
3343 | ||
3344 | /* As we no longer need a fence for GTT access, | |
3345 | * we can relinquish it now (and so prevent having | |
3346 | * to steal a fence from someone else on the next | |
3347 | * fence request). Note GPU activity would have | |
3348 | * dropped the fence as all snoopable access is | |
3349 | * supposed to be linear. | |
3350 | */ | |
49ef5294 CW |
3351 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3352 | ret = i915_vma_put_fence(vma); | |
3353 | if (ret) | |
3354 | return ret; | |
3355 | } | |
ef55f92a CW |
3356 | } else { |
3357 | /* We either have incoherent backing store and | |
3358 | * so no GTT access or the architecture is fully | |
3359 | * coherent. In such cases, existing GTT mmaps | |
3360 | * ignore the cache bit in the PTE and we can | |
3361 | * rewrite it without confusing the GPU or having | |
3362 | * to force userspace to fault back in its mmaps. | |
3363 | */ | |
e4ffd173 CW |
3364 | } |
3365 | ||
1c7f4bca | 3366 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3367 | if (!drm_mm_node_allocated(&vma->node)) |
3368 | continue; | |
3369 | ||
3370 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3371 | if (ret) | |
3372 | return ret; | |
3373 | } | |
e4ffd173 CW |
3374 | } |
3375 | ||
a6a7cc4b CW |
3376 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU && |
3377 | cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
3378 | obj->cache_dirty = true; | |
3379 | ||
1c7f4bca | 3380 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3381 | vma->node.color = cache_level; |
3382 | obj->cache_level = cache_level; | |
3383 | ||
e4ffd173 CW |
3384 | return 0; |
3385 | } | |
3386 | ||
199adf40 BW |
3387 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3388 | struct drm_file *file) | |
e6994aee | 3389 | { |
199adf40 | 3390 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3391 | struct drm_i915_gem_object *obj; |
fbbd37b3 | 3392 | int err = 0; |
e6994aee | 3393 | |
fbbd37b3 CW |
3394 | rcu_read_lock(); |
3395 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
3396 | if (!obj) { | |
3397 | err = -ENOENT; | |
3398 | goto out; | |
3399 | } | |
e6994aee | 3400 | |
651d794f CW |
3401 | switch (obj->cache_level) { |
3402 | case I915_CACHE_LLC: | |
3403 | case I915_CACHE_L3_LLC: | |
3404 | args->caching = I915_CACHING_CACHED; | |
3405 | break; | |
3406 | ||
4257d3ba CW |
3407 | case I915_CACHE_WT: |
3408 | args->caching = I915_CACHING_DISPLAY; | |
3409 | break; | |
3410 | ||
651d794f CW |
3411 | default: |
3412 | args->caching = I915_CACHING_NONE; | |
3413 | break; | |
3414 | } | |
fbbd37b3 CW |
3415 | out: |
3416 | rcu_read_unlock(); | |
3417 | return err; | |
e6994aee CW |
3418 | } |
3419 | ||
199adf40 BW |
3420 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3421 | struct drm_file *file) | |
e6994aee | 3422 | { |
9c870d03 | 3423 | struct drm_i915_private *i915 = to_i915(dev); |
199adf40 | 3424 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3425 | struct drm_i915_gem_object *obj; |
3426 | enum i915_cache_level level; | |
3427 | int ret; | |
3428 | ||
199adf40 BW |
3429 | switch (args->caching) { |
3430 | case I915_CACHING_NONE: | |
e6994aee CW |
3431 | level = I915_CACHE_NONE; |
3432 | break; | |
199adf40 | 3433 | case I915_CACHING_CACHED: |
e5756c10 ID |
3434 | /* |
3435 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3436 | * snooped mapping may leave stale data in a corresponding CPU | |
3437 | * cacheline, whereas normally such cachelines would get | |
3438 | * invalidated. | |
3439 | */ | |
9c870d03 | 3440 | if (!HAS_LLC(i915) && !HAS_SNOOP(i915)) |
e5756c10 ID |
3441 | return -ENODEV; |
3442 | ||
e6994aee CW |
3443 | level = I915_CACHE_LLC; |
3444 | break; | |
4257d3ba | 3445 | case I915_CACHING_DISPLAY: |
9c870d03 | 3446 | level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE; |
4257d3ba | 3447 | break; |
e6994aee CW |
3448 | default: |
3449 | return -EINVAL; | |
3450 | } | |
3451 | ||
3bc2913e BW |
3452 | ret = i915_mutex_lock_interruptible(dev); |
3453 | if (ret) | |
9c870d03 | 3454 | return ret; |
3bc2913e | 3455 | |
03ac0642 CW |
3456 | obj = i915_gem_object_lookup(file, args->handle); |
3457 | if (!obj) { | |
e6994aee CW |
3458 | ret = -ENOENT; |
3459 | goto unlock; | |
3460 | } | |
3461 | ||
3462 | ret = i915_gem_object_set_cache_level(obj, level); | |
f8c417cd | 3463 | i915_gem_object_put(obj); |
e6994aee CW |
3464 | unlock: |
3465 | mutex_unlock(&dev->struct_mutex); | |
3466 | return ret; | |
3467 | } | |
3468 | ||
b9241ea3 | 3469 | /* |
2da3b9b9 CW |
3470 | * Prepare buffer for display plane (scanout, cursors, etc). |
3471 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3472 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 | 3473 | */ |
058d88c4 | 3474 | struct i915_vma * |
2da3b9b9 CW |
3475 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3476 | u32 alignment, | |
e6617330 | 3477 | const struct i915_ggtt_view *view) |
b9241ea3 | 3478 | { |
058d88c4 | 3479 | struct i915_vma *vma; |
2da3b9b9 | 3480 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3481 | int ret; |
3482 | ||
4c7d62c6 CW |
3483 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3484 | ||
cc98b413 CW |
3485 | /* Mark the pin_display early so that we account for the |
3486 | * display coherency whilst setting up the cache domains. | |
3487 | */ | |
8a0c39b1 | 3488 | obj->pin_display++; |
cc98b413 | 3489 | |
a7ef0640 EA |
3490 | /* The display engine is not coherent with the LLC cache on gen6. As |
3491 | * a result, we make sure that the pinning that is about to occur is | |
3492 | * done with uncached PTEs. This is lowest common denominator for all | |
3493 | * chipsets. | |
3494 | * | |
3495 | * However for gen6+, we could do better by using the GFDT bit instead | |
3496 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3497 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3498 | */ | |
651d794f | 3499 | ret = i915_gem_object_set_cache_level(obj, |
8652744b TU |
3500 | HAS_WT(to_i915(obj->base.dev)) ? |
3501 | I915_CACHE_WT : I915_CACHE_NONE); | |
058d88c4 CW |
3502 | if (ret) { |
3503 | vma = ERR_PTR(ret); | |
cc98b413 | 3504 | goto err_unpin_display; |
058d88c4 | 3505 | } |
a7ef0640 | 3506 | |
2da3b9b9 CW |
3507 | /* As the user may map the buffer once pinned in the display plane |
3508 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2efb813d CW |
3509 | * always use map_and_fenceable for all scanout buffers. However, |
3510 | * it may simply be too big to fit into mappable, in which case | |
3511 | * put it anyway and hope that userspace can cope (but always first | |
3512 | * try to preserve the existing ABI). | |
2da3b9b9 | 3513 | */ |
2efb813d CW |
3514 | vma = ERR_PTR(-ENOSPC); |
3515 | if (view->type == I915_GGTT_VIEW_NORMAL) | |
3516 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, | |
3517 | PIN_MAPPABLE | PIN_NONBLOCK); | |
767a222e CW |
3518 | if (IS_ERR(vma)) { |
3519 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
3520 | unsigned int flags; | |
3521 | ||
3522 | /* Valleyview is definitely limited to scanning out the first | |
3523 | * 512MiB. Lets presume this behaviour was inherited from the | |
3524 | * g4x display engine and that all earlier gen are similarly | |
3525 | * limited. Testing suggests that it is a little more | |
3526 | * complicated than this. For example, Cherryview appears quite | |
3527 | * happy to scanout from anywhere within its global aperture. | |
3528 | */ | |
3529 | flags = 0; | |
3530 | if (HAS_GMCH_DISPLAY(i915)) | |
3531 | flags = PIN_MAPPABLE; | |
3532 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags); | |
3533 | } | |
058d88c4 | 3534 | if (IS_ERR(vma)) |
cc98b413 | 3535 | goto err_unpin_display; |
2da3b9b9 | 3536 | |
d8923dcf CW |
3537 | vma->display_alignment = max_t(u64, vma->display_alignment, alignment); |
3538 | ||
a6a7cc4b CW |
3539 | /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ |
3540 | if (obj->cache_dirty) { | |
3541 | i915_gem_clflush_object(obj, true); | |
3542 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); | |
3543 | } | |
b118c1e3 | 3544 | |
2da3b9b9 | 3545 | old_write_domain = obj->base.write_domain; |
05394f39 | 3546 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3547 | |
3548 | /* It should now be out of any other write domains, and we can update | |
3549 | * the domain values for our changes. | |
3550 | */ | |
e5f1d962 | 3551 | obj->base.write_domain = 0; |
05394f39 | 3552 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3553 | |
3554 | trace_i915_gem_object_change_domain(obj, | |
3555 | old_read_domains, | |
2da3b9b9 | 3556 | old_write_domain); |
b9241ea3 | 3557 | |
058d88c4 | 3558 | return vma; |
cc98b413 CW |
3559 | |
3560 | err_unpin_display: | |
8a0c39b1 | 3561 | obj->pin_display--; |
058d88c4 | 3562 | return vma; |
cc98b413 CW |
3563 | } |
3564 | ||
3565 | void | |
058d88c4 | 3566 | i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) |
cc98b413 | 3567 | { |
49d73912 | 3568 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
4c7d62c6 | 3569 | |
058d88c4 | 3570 | if (WARN_ON(vma->obj->pin_display == 0)) |
8a0c39b1 TU |
3571 | return; |
3572 | ||
d8923dcf CW |
3573 | if (--vma->obj->pin_display == 0) |
3574 | vma->display_alignment = 0; | |
e6617330 | 3575 | |
383d5823 CW |
3576 | /* Bump the LRU to try and avoid premature eviction whilst flipping */ |
3577 | if (!i915_vma_is_active(vma)) | |
3578 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
3579 | ||
058d88c4 | 3580 | i915_vma_unpin(vma); |
b9241ea3 ZW |
3581 | } |
3582 | ||
e47c68e9 EA |
3583 | /** |
3584 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3585 | * @obj: object to act on |
3586 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3587 | * |
3588 | * This function returns when the move is complete, including waiting on | |
3589 | * flushes to occur. | |
3590 | */ | |
dabdfe02 | 3591 | int |
919926ae | 3592 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3593 | { |
1c5d22f7 | 3594 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3595 | int ret; |
3596 | ||
e95433c7 | 3597 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3598 | |
e95433c7 CW |
3599 | ret = i915_gem_object_wait(obj, |
3600 | I915_WAIT_INTERRUPTIBLE | | |
3601 | I915_WAIT_LOCKED | | |
3602 | (write ? I915_WAIT_ALL : 0), | |
3603 | MAX_SCHEDULE_TIMEOUT, | |
3604 | NULL); | |
88241785 CW |
3605 | if (ret) |
3606 | return ret; | |
3607 | ||
c13d87ea CW |
3608 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3609 | return 0; | |
3610 | ||
e47c68e9 | 3611 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3612 | |
05394f39 CW |
3613 | old_write_domain = obj->base.write_domain; |
3614 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3615 | |
e47c68e9 | 3616 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3617 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3618 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3619 | |
05394f39 | 3620 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3621 | } |
3622 | ||
3623 | /* It should now be out of any other write domains, and we can update | |
3624 | * the domain values for our changes. | |
3625 | */ | |
40e62d5d | 3626 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3627 | |
3628 | /* If we're writing through the CPU, then the GPU read domains will | |
3629 | * need to be invalidated at next use. | |
3630 | */ | |
3631 | if (write) { | |
05394f39 CW |
3632 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3633 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3634 | } |
2ef7eeaa | 3635 | |
1c5d22f7 CW |
3636 | trace_i915_gem_object_change_domain(obj, |
3637 | old_read_domains, | |
3638 | old_write_domain); | |
3639 | ||
2ef7eeaa EA |
3640 | return 0; |
3641 | } | |
3642 | ||
673a394b EA |
3643 | /* Throttle our rendering by waiting until the ring has completed our requests |
3644 | * emitted over 20 msec ago. | |
3645 | * | |
b962442e EA |
3646 | * Note that if we were to use the current jiffies each time around the loop, |
3647 | * we wouldn't escape the function with any frames outstanding if the time to | |
3648 | * render a frame was over 20ms. | |
3649 | * | |
673a394b EA |
3650 | * This should get us reasonable parallelism between CPU and GPU but also |
3651 | * relatively low latency when blocking on a particular request to finish. | |
3652 | */ | |
40a5f0de | 3653 | static int |
f787a5f5 | 3654 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3655 | { |
fac5e23e | 3656 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3657 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3658 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3659 | struct drm_i915_gem_request *request, *target = NULL; |
e95433c7 | 3660 | long ret; |
93533c29 | 3661 | |
f4457ae7 CW |
3662 | /* ABI: return -EIO if already wedged */ |
3663 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3664 | return -EIO; | |
e110e8d6 | 3665 | |
1c25595f | 3666 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3667 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3668 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3669 | break; | |
40a5f0de | 3670 | |
fcfa423c JH |
3671 | /* |
3672 | * Note that the request might not have been submitted yet. | |
3673 | * In which case emitted_jiffies will be zero. | |
3674 | */ | |
3675 | if (!request->emitted_jiffies) | |
3676 | continue; | |
3677 | ||
54fb2411 | 3678 | target = request; |
b962442e | 3679 | } |
ff865885 | 3680 | if (target) |
e8a261ea | 3681 | i915_gem_request_get(target); |
1c25595f | 3682 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3683 | |
54fb2411 | 3684 | if (target == NULL) |
f787a5f5 | 3685 | return 0; |
2bc43b5c | 3686 | |
e95433c7 CW |
3687 | ret = i915_wait_request(target, |
3688 | I915_WAIT_INTERRUPTIBLE, | |
3689 | MAX_SCHEDULE_TIMEOUT); | |
e8a261ea | 3690 | i915_gem_request_put(target); |
ff865885 | 3691 | |
e95433c7 | 3692 | return ret < 0 ? ret : 0; |
40a5f0de EA |
3693 | } |
3694 | ||
058d88c4 | 3695 | struct i915_vma * |
ec7adb6e JL |
3696 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3697 | const struct i915_ggtt_view *view, | |
91b2db6f | 3698 | u64 size, |
2ffffd0f CW |
3699 | u64 alignment, |
3700 | u64 flags) | |
ec7adb6e | 3701 | { |
ad16d2ed CW |
3702 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
3703 | struct i915_address_space *vm = &dev_priv->ggtt.base; | |
59bfa124 CW |
3704 | struct i915_vma *vma; |
3705 | int ret; | |
72e96d64 | 3706 | |
4c7d62c6 CW |
3707 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3708 | ||
058d88c4 | 3709 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm, view); |
59bfa124 | 3710 | if (IS_ERR(vma)) |
058d88c4 | 3711 | return vma; |
59bfa124 CW |
3712 | |
3713 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
3714 | if (flags & PIN_NONBLOCK && | |
3715 | (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))) | |
058d88c4 | 3716 | return ERR_PTR(-ENOSPC); |
59bfa124 | 3717 | |
ad16d2ed CW |
3718 | if (flags & PIN_MAPPABLE) { |
3719 | u32 fence_size; | |
3720 | ||
3721 | fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size, | |
3722 | i915_gem_object_get_tiling(obj)); | |
3723 | /* If the required space is larger than the available | |
3724 | * aperture, we will not able to find a slot for the | |
3725 | * object and unbinding the object now will be in | |
3726 | * vain. Worse, doing so may cause us to ping-pong | |
3727 | * the object in and out of the Global GTT and | |
3728 | * waste a lot of cycles under the mutex. | |
3729 | */ | |
3730 | if (fence_size > dev_priv->ggtt.mappable_end) | |
3731 | return ERR_PTR(-E2BIG); | |
3732 | ||
3733 | /* If NONBLOCK is set the caller is optimistically | |
3734 | * trying to cache the full object within the mappable | |
3735 | * aperture, and *must* have a fallback in place for | |
3736 | * situations where we cannot bind the object. We | |
3737 | * can be a little more lax here and use the fallback | |
3738 | * more often to avoid costly migrations of ourselves | |
3739 | * and other objects within the aperture. | |
3740 | * | |
3741 | * Half-the-aperture is used as a simple heuristic. | |
3742 | * More interesting would to do search for a free | |
3743 | * block prior to making the commitment to unbind. | |
3744 | * That caters for the self-harm case, and with a | |
3745 | * little more heuristics (e.g. NOFAULT, NOEVICT) | |
3746 | * we could try to minimise harm to others. | |
3747 | */ | |
3748 | if (flags & PIN_NONBLOCK && | |
3749 | fence_size > dev_priv->ggtt.mappable_end / 2) | |
3750 | return ERR_PTR(-ENOSPC); | |
3751 | } | |
3752 | ||
59bfa124 CW |
3753 | WARN(i915_vma_is_pinned(vma), |
3754 | "bo is already pinned in ggtt with incorrect alignment:" | |
05a20d09 CW |
3755 | " offset=%08x, req.alignment=%llx," |
3756 | " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n", | |
3757 | i915_ggtt_offset(vma), alignment, | |
59bfa124 | 3758 | !!(flags & PIN_MAPPABLE), |
05a20d09 | 3759 | i915_vma_is_map_and_fenceable(vma)); |
59bfa124 CW |
3760 | ret = i915_vma_unbind(vma); |
3761 | if (ret) | |
058d88c4 | 3762 | return ERR_PTR(ret); |
59bfa124 CW |
3763 | } |
3764 | ||
058d88c4 CW |
3765 | ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); |
3766 | if (ret) | |
3767 | return ERR_PTR(ret); | |
ec7adb6e | 3768 | |
058d88c4 | 3769 | return vma; |
673a394b EA |
3770 | } |
3771 | ||
edf6b76f | 3772 | static __always_inline unsigned int __busy_read_flag(unsigned int id) |
3fdc13c7 CW |
3773 | { |
3774 | /* Note that we could alias engines in the execbuf API, but | |
3775 | * that would be very unwise as it prevents userspace from | |
3776 | * fine control over engine selection. Ahem. | |
3777 | * | |
3778 | * This should be something like EXEC_MAX_ENGINE instead of | |
3779 | * I915_NUM_ENGINES. | |
3780 | */ | |
3781 | BUILD_BUG_ON(I915_NUM_ENGINES > 16); | |
3782 | return 0x10000 << id; | |
3783 | } | |
3784 | ||
3785 | static __always_inline unsigned int __busy_write_id(unsigned int id) | |
3786 | { | |
70cb472c CW |
3787 | /* The uABI guarantees an active writer is also amongst the read |
3788 | * engines. This would be true if we accessed the activity tracking | |
3789 | * under the lock, but as we perform the lookup of the object and | |
3790 | * its activity locklessly we can not guarantee that the last_write | |
3791 | * being active implies that we have set the same engine flag from | |
3792 | * last_read - hence we always set both read and write busy for | |
3793 | * last_write. | |
3794 | */ | |
3795 | return id | __busy_read_flag(id); | |
3fdc13c7 CW |
3796 | } |
3797 | ||
edf6b76f | 3798 | static __always_inline unsigned int |
d07f0e59 | 3799 | __busy_set_if_active(const struct dma_fence *fence, |
3fdc13c7 CW |
3800 | unsigned int (*flag)(unsigned int id)) |
3801 | { | |
d07f0e59 | 3802 | struct drm_i915_gem_request *rq; |
3fdc13c7 | 3803 | |
d07f0e59 CW |
3804 | /* We have to check the current hw status of the fence as the uABI |
3805 | * guarantees forward progress. We could rely on the idle worker | |
3806 | * to eventually flush us, but to minimise latency just ask the | |
3807 | * hardware. | |
1255501d | 3808 | * |
d07f0e59 | 3809 | * Note we only report on the status of native fences. |
1255501d | 3810 | */ |
d07f0e59 CW |
3811 | if (!dma_fence_is_i915(fence)) |
3812 | return 0; | |
3813 | ||
3814 | /* opencode to_request() in order to avoid const warnings */ | |
3815 | rq = container_of(fence, struct drm_i915_gem_request, fence); | |
3816 | if (i915_gem_request_completed(rq)) | |
3817 | return 0; | |
3818 | ||
3819 | return flag(rq->engine->exec_id); | |
3fdc13c7 CW |
3820 | } |
3821 | ||
edf6b76f | 3822 | static __always_inline unsigned int |
d07f0e59 | 3823 | busy_check_reader(const struct dma_fence *fence) |
3fdc13c7 | 3824 | { |
d07f0e59 | 3825 | return __busy_set_if_active(fence, __busy_read_flag); |
3fdc13c7 CW |
3826 | } |
3827 | ||
edf6b76f | 3828 | static __always_inline unsigned int |
d07f0e59 | 3829 | busy_check_writer(const struct dma_fence *fence) |
3fdc13c7 | 3830 | { |
d07f0e59 CW |
3831 | if (!fence) |
3832 | return 0; | |
3833 | ||
3834 | return __busy_set_if_active(fence, __busy_write_id); | |
3fdc13c7 CW |
3835 | } |
3836 | ||
673a394b EA |
3837 | int |
3838 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3839 | struct drm_file *file) |
673a394b EA |
3840 | { |
3841 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3842 | struct drm_i915_gem_object *obj; |
d07f0e59 CW |
3843 | struct reservation_object_list *list; |
3844 | unsigned int seq; | |
fbbd37b3 | 3845 | int err; |
673a394b | 3846 | |
d07f0e59 | 3847 | err = -ENOENT; |
fbbd37b3 CW |
3848 | rcu_read_lock(); |
3849 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
d07f0e59 | 3850 | if (!obj) |
fbbd37b3 | 3851 | goto out; |
d1b851fc | 3852 | |
d07f0e59 CW |
3853 | /* A discrepancy here is that we do not report the status of |
3854 | * non-i915 fences, i.e. even though we may report the object as idle, | |
3855 | * a call to set-domain may still stall waiting for foreign rendering. | |
3856 | * This also means that wait-ioctl may report an object as busy, | |
3857 | * where busy-ioctl considers it idle. | |
3858 | * | |
3859 | * We trade the ability to warn of foreign fences to report on which | |
3860 | * i915 engines are active for the object. | |
3861 | * | |
3862 | * Alternatively, we can trade that extra information on read/write | |
3863 | * activity with | |
3864 | * args->busy = | |
3865 | * !reservation_object_test_signaled_rcu(obj->resv, true); | |
3866 | * to report the overall busyness. This is what the wait-ioctl does. | |
3867 | * | |
3868 | */ | |
3869 | retry: | |
3870 | seq = raw_read_seqcount(&obj->resv->seq); | |
426960be | 3871 | |
d07f0e59 CW |
3872 | /* Translate the exclusive fence to the READ *and* WRITE engine */ |
3873 | args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl)); | |
3fdc13c7 | 3874 | |
d07f0e59 CW |
3875 | /* Translate shared fences to READ set of engines */ |
3876 | list = rcu_dereference(obj->resv->fence); | |
3877 | if (list) { | |
3878 | unsigned int shared_count = list->shared_count, i; | |
3fdc13c7 | 3879 | |
d07f0e59 CW |
3880 | for (i = 0; i < shared_count; ++i) { |
3881 | struct dma_fence *fence = | |
3882 | rcu_dereference(list->shared[i]); | |
3883 | ||
3884 | args->busy |= busy_check_reader(fence); | |
3885 | } | |
426960be | 3886 | } |
673a394b | 3887 | |
d07f0e59 CW |
3888 | if (args->busy && read_seqcount_retry(&obj->resv->seq, seq)) |
3889 | goto retry; | |
3890 | ||
3891 | err = 0; | |
fbbd37b3 CW |
3892 | out: |
3893 | rcu_read_unlock(); | |
3894 | return err; | |
673a394b EA |
3895 | } |
3896 | ||
3897 | int | |
3898 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3899 | struct drm_file *file_priv) | |
3900 | { | |
0206e353 | 3901 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3902 | } |
3903 | ||
3ef94daa CW |
3904 | int |
3905 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3906 | struct drm_file *file_priv) | |
3907 | { | |
fac5e23e | 3908 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 3909 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 3910 | struct drm_i915_gem_object *obj; |
1233e2db | 3911 | int err; |
3ef94daa CW |
3912 | |
3913 | switch (args->madv) { | |
3914 | case I915_MADV_DONTNEED: | |
3915 | case I915_MADV_WILLNEED: | |
3916 | break; | |
3917 | default: | |
3918 | return -EINVAL; | |
3919 | } | |
3920 | ||
03ac0642 | 3921 | obj = i915_gem_object_lookup(file_priv, args->handle); |
1233e2db CW |
3922 | if (!obj) |
3923 | return -ENOENT; | |
3924 | ||
3925 | err = mutex_lock_interruptible(&obj->mm.lock); | |
3926 | if (err) | |
3927 | goto out; | |
3ef94daa | 3928 | |
a4f5ea64 | 3929 | if (obj->mm.pages && |
3e510a8e | 3930 | i915_gem_object_is_tiled(obj) && |
656bfa3a | 3931 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
bc0629a7 CW |
3932 | if (obj->mm.madv == I915_MADV_WILLNEED) { |
3933 | GEM_BUG_ON(!obj->mm.quirked); | |
a4f5ea64 | 3934 | __i915_gem_object_unpin_pages(obj); |
bc0629a7 CW |
3935 | obj->mm.quirked = false; |
3936 | } | |
3937 | if (args->madv == I915_MADV_WILLNEED) { | |
2c3a3f44 | 3938 | GEM_BUG_ON(obj->mm.quirked); |
a4f5ea64 | 3939 | __i915_gem_object_pin_pages(obj); |
bc0629a7 CW |
3940 | obj->mm.quirked = true; |
3941 | } | |
656bfa3a DV |
3942 | } |
3943 | ||
a4f5ea64 CW |
3944 | if (obj->mm.madv != __I915_MADV_PURGED) |
3945 | obj->mm.madv = args->madv; | |
3ef94daa | 3946 | |
6c085a72 | 3947 | /* if the object is no longer attached, discard its backing storage */ |
a4f5ea64 | 3948 | if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages) |
2d7ef395 CW |
3949 | i915_gem_object_truncate(obj); |
3950 | ||
a4f5ea64 | 3951 | args->retained = obj->mm.madv != __I915_MADV_PURGED; |
1233e2db | 3952 | mutex_unlock(&obj->mm.lock); |
bb6baf76 | 3953 | |
1233e2db | 3954 | out: |
f8c417cd | 3955 | i915_gem_object_put(obj); |
1233e2db | 3956 | return err; |
3ef94daa CW |
3957 | } |
3958 | ||
5b8c8aec CW |
3959 | static void |
3960 | frontbuffer_retire(struct i915_gem_active *active, | |
3961 | struct drm_i915_gem_request *request) | |
3962 | { | |
3963 | struct drm_i915_gem_object *obj = | |
3964 | container_of(active, typeof(*obj), frontbuffer_write); | |
3965 | ||
3966 | intel_fb_obj_flush(obj, true, ORIGIN_CS); | |
3967 | } | |
3968 | ||
37e680a1 CW |
3969 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3970 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3971 | { |
1233e2db CW |
3972 | mutex_init(&obj->mm.lock); |
3973 | ||
56cea323 | 3974 | INIT_LIST_HEAD(&obj->global_link); |
275f039d | 3975 | INIT_LIST_HEAD(&obj->userfault_link); |
b25cb2f8 | 3976 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 3977 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 3978 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 3979 | |
37e680a1 CW |
3980 | obj->ops = ops; |
3981 | ||
d07f0e59 CW |
3982 | reservation_object_init(&obj->__builtin_resv); |
3983 | obj->resv = &obj->__builtin_resv; | |
3984 | ||
50349247 | 3985 | obj->frontbuffer_ggtt_origin = ORIGIN_GTT; |
5b8c8aec | 3986 | init_request_active(&obj->frontbuffer_write, frontbuffer_retire); |
a4f5ea64 CW |
3987 | |
3988 | obj->mm.madv = I915_MADV_WILLNEED; | |
3989 | INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN); | |
3990 | mutex_init(&obj->mm.get_page.lock); | |
0327d6ba | 3991 | |
f19ec8cb | 3992 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
3993 | } |
3994 | ||
37e680a1 | 3995 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3599a91c TU |
3996 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE | |
3997 | I915_GEM_OBJECT_IS_SHRINKABLE, | |
37e680a1 CW |
3998 | .get_pages = i915_gem_object_get_pages_gtt, |
3999 | .put_pages = i915_gem_object_put_pages_gtt, | |
4000 | }; | |
4001 | ||
b4bcbe2a CW |
4002 | /* Note we don't consider signbits :| */ |
4003 | #define overflows_type(x, T) \ | |
4004 | (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE)) | |
4005 | ||
4006 | struct drm_i915_gem_object * | |
12d79d78 | 4007 | i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) |
ac52bc56 | 4008 | { |
c397b908 | 4009 | struct drm_i915_gem_object *obj; |
5949eac4 | 4010 | struct address_space *mapping; |
1a240d4d | 4011 | gfp_t mask; |
fe3db79b | 4012 | int ret; |
ac52bc56 | 4013 | |
b4bcbe2a CW |
4014 | /* There is a prevalence of the assumption that we fit the object's |
4015 | * page count inside a 32bit _signed_ variable. Let's document this and | |
4016 | * catch if we ever need to fix it. In the meantime, if you do spot | |
4017 | * such a local variable, please consider fixing! | |
4018 | */ | |
4019 | if (WARN_ON(size >> PAGE_SHIFT > INT_MAX)) | |
4020 | return ERR_PTR(-E2BIG); | |
4021 | ||
4022 | if (overflows_type(size, obj->base.size)) | |
4023 | return ERR_PTR(-E2BIG); | |
4024 | ||
187685cb | 4025 | obj = i915_gem_object_alloc(dev_priv); |
c397b908 | 4026 | if (obj == NULL) |
fe3db79b | 4027 | return ERR_PTR(-ENOMEM); |
673a394b | 4028 | |
12d79d78 | 4029 | ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size); |
fe3db79b CW |
4030 | if (ret) |
4031 | goto fail; | |
673a394b | 4032 | |
bed1ea95 | 4033 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
c0f86832 | 4034 | if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) { |
bed1ea95 CW |
4035 | /* 965gm cannot relocate objects above 4GiB. */ |
4036 | mask &= ~__GFP_HIGHMEM; | |
4037 | mask |= __GFP_DMA32; | |
4038 | } | |
4039 | ||
93c76a3d | 4040 | mapping = obj->base.filp->f_mapping; |
bed1ea95 | 4041 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4042 | |
37e680a1 | 4043 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4044 | |
c397b908 DV |
4045 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4046 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4047 | |
0031fb96 | 4048 | if (HAS_LLC(dev_priv)) { |
3d29b842 | 4049 | /* On some devices, we can have the GPU use the LLC (the CPU |
a1871112 EA |
4050 | * cache) for about a 10% performance improvement |
4051 | * compared to uncached. Graphics requests other than | |
4052 | * display scanout are coherent with the CPU in | |
4053 | * accessing this cache. This means in this mode we | |
4054 | * don't need to clflush on the CPU side, and on the | |
4055 | * GPU side we only need to flush internal caches to | |
4056 | * get data visible to the CPU. | |
4057 | * | |
4058 | * However, we maintain the display planes as UC, and so | |
4059 | * need to rebind when first used as such. | |
4060 | */ | |
4061 | obj->cache_level = I915_CACHE_LLC; | |
4062 | } else | |
4063 | obj->cache_level = I915_CACHE_NONE; | |
4064 | ||
d861e338 DV |
4065 | trace_i915_gem_object_create(obj); |
4066 | ||
05394f39 | 4067 | return obj; |
fe3db79b CW |
4068 | |
4069 | fail: | |
4070 | i915_gem_object_free(obj); | |
fe3db79b | 4071 | return ERR_PTR(ret); |
c397b908 DV |
4072 | } |
4073 | ||
340fbd8c CW |
4074 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4075 | { | |
4076 | /* If we are the last user of the backing storage (be it shmemfs | |
4077 | * pages or stolen etc), we know that the pages are going to be | |
4078 | * immediately released. In this case, we can then skip copying | |
4079 | * back the contents from the GPU. | |
4080 | */ | |
4081 | ||
a4f5ea64 | 4082 | if (obj->mm.madv != I915_MADV_WILLNEED) |
340fbd8c CW |
4083 | return false; |
4084 | ||
4085 | if (obj->base.filp == NULL) | |
4086 | return true; | |
4087 | ||
4088 | /* At first glance, this looks racy, but then again so would be | |
4089 | * userspace racing mmap against close. However, the first external | |
4090 | * reference to the filp can only be obtained through the | |
4091 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4092 | * acquiring such a reference whilst we are in the middle of | |
4093 | * freeing the object. | |
4094 | */ | |
4095 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4096 | } | |
4097 | ||
fbbd37b3 CW |
4098 | static void __i915_gem_free_objects(struct drm_i915_private *i915, |
4099 | struct llist_node *freed) | |
673a394b | 4100 | { |
fbbd37b3 | 4101 | struct drm_i915_gem_object *obj, *on; |
673a394b | 4102 | |
fbbd37b3 CW |
4103 | mutex_lock(&i915->drm.struct_mutex); |
4104 | intel_runtime_pm_get(i915); | |
4105 | llist_for_each_entry(obj, freed, freed) { | |
4106 | struct i915_vma *vma, *vn; | |
4107 | ||
4108 | trace_i915_gem_object_destroy(obj); | |
4109 | ||
4110 | GEM_BUG_ON(i915_gem_object_is_active(obj)); | |
4111 | list_for_each_entry_safe(vma, vn, | |
4112 | &obj->vma_list, obj_link) { | |
4113 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); | |
4114 | GEM_BUG_ON(i915_vma_is_active(vma)); | |
4115 | vma->flags &= ~I915_VMA_PIN_MASK; | |
4116 | i915_vma_close(vma); | |
4117 | } | |
db6c2b41 CW |
4118 | GEM_BUG_ON(!list_empty(&obj->vma_list)); |
4119 | GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree)); | |
fbbd37b3 | 4120 | |
56cea323 | 4121 | list_del(&obj->global_link); |
fbbd37b3 CW |
4122 | } |
4123 | intel_runtime_pm_put(i915); | |
4124 | mutex_unlock(&i915->drm.struct_mutex); | |
4125 | ||
4126 | llist_for_each_entry_safe(obj, on, freed, freed) { | |
4127 | GEM_BUG_ON(obj->bind_count); | |
4128 | GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits)); | |
4129 | ||
4130 | if (obj->ops->release) | |
4131 | obj->ops->release(obj); | |
f65c9168 | 4132 | |
fbbd37b3 CW |
4133 | if (WARN_ON(i915_gem_object_has_pinned_pages(obj))) |
4134 | atomic_set(&obj->mm.pages_pin_count, 0); | |
548625ee | 4135 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
fbbd37b3 CW |
4136 | GEM_BUG_ON(obj->mm.pages); |
4137 | ||
4138 | if (obj->base.import_attach) | |
4139 | drm_prime_gem_destroy(&obj->base, NULL); | |
4140 | ||
d07f0e59 | 4141 | reservation_object_fini(&obj->__builtin_resv); |
fbbd37b3 CW |
4142 | drm_gem_object_release(&obj->base); |
4143 | i915_gem_info_remove_obj(i915, obj->base.size); | |
4144 | ||
4145 | kfree(obj->bit_17); | |
4146 | i915_gem_object_free(obj); | |
4147 | } | |
4148 | } | |
4149 | ||
4150 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915) | |
4151 | { | |
4152 | struct llist_node *freed; | |
4153 | ||
4154 | freed = llist_del_all(&i915->mm.free_list); | |
4155 | if (unlikely(freed)) | |
4156 | __i915_gem_free_objects(i915, freed); | |
4157 | } | |
4158 | ||
4159 | static void __i915_gem_free_work(struct work_struct *work) | |
4160 | { | |
4161 | struct drm_i915_private *i915 = | |
4162 | container_of(work, struct drm_i915_private, mm.free_work); | |
4163 | struct llist_node *freed; | |
26e12f89 | 4164 | |
b1f788c6 CW |
4165 | /* All file-owned VMA should have been released by this point through |
4166 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
4167 | * However, the object may also be bound into the global GTT (e.g. | |
4168 | * older GPUs without per-process support, or for direct access through | |
4169 | * the GTT either for the user or for scanout). Those VMA still need to | |
4170 | * unbound now. | |
4171 | */ | |
1488fc08 | 4172 | |
fbbd37b3 CW |
4173 | while ((freed = llist_del_all(&i915->mm.free_list))) |
4174 | __i915_gem_free_objects(i915, freed); | |
4175 | } | |
a071fa00 | 4176 | |
fbbd37b3 CW |
4177 | static void __i915_gem_free_object_rcu(struct rcu_head *head) |
4178 | { | |
4179 | struct drm_i915_gem_object *obj = | |
4180 | container_of(head, typeof(*obj), rcu); | |
4181 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
4182 | ||
4183 | /* We can't simply use call_rcu() from i915_gem_free_object() | |
4184 | * as we need to block whilst unbinding, and the call_rcu | |
4185 | * task may be called from softirq context. So we take a | |
4186 | * detour through a worker. | |
4187 | */ | |
4188 | if (llist_add(&obj->freed, &i915->mm.free_list)) | |
4189 | schedule_work(&i915->mm.free_work); | |
4190 | } | |
656bfa3a | 4191 | |
fbbd37b3 CW |
4192 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
4193 | { | |
4194 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); | |
a4f5ea64 | 4195 | |
bc0629a7 CW |
4196 | if (obj->mm.quirked) |
4197 | __i915_gem_object_unpin_pages(obj); | |
4198 | ||
340fbd8c | 4199 | if (discard_backing_storage(obj)) |
a4f5ea64 | 4200 | obj->mm.madv = I915_MADV_DONTNEED; |
de151cf6 | 4201 | |
fbbd37b3 CW |
4202 | /* Before we free the object, make sure any pure RCU-only |
4203 | * read-side critical sections are complete, e.g. | |
4204 | * i915_gem_busy_ioctl(). For the corresponding synchronized | |
4205 | * lookup see i915_gem_object_lookup_rcu(). | |
4206 | */ | |
4207 | call_rcu(&obj->rcu, __i915_gem_free_object_rcu); | |
673a394b EA |
4208 | } |
4209 | ||
f8a7fde4 CW |
4210 | void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj) |
4211 | { | |
4212 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
4213 | ||
4214 | GEM_BUG_ON(i915_gem_object_has_active_reference(obj)); | |
4215 | if (i915_gem_object_is_active(obj)) | |
4216 | i915_gem_object_set_active_reference(obj); | |
4217 | else | |
4218 | i915_gem_object_put(obj); | |
4219 | } | |
4220 | ||
3033acab CW |
4221 | static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv) |
4222 | { | |
4223 | struct intel_engine_cs *engine; | |
4224 | enum intel_engine_id id; | |
4225 | ||
4226 | for_each_engine(engine, dev_priv, id) | |
e8a9c58f | 4227 | GEM_BUG_ON(engine->last_retired_context != dev_priv->kernel_context); |
3033acab CW |
4228 | } |
4229 | ||
bf9e8429 | 4230 | int i915_gem_suspend(struct drm_i915_private *dev_priv) |
29105ccc | 4231 | { |
bf9e8429 | 4232 | struct drm_device *dev = &dev_priv->drm; |
dcff85c8 | 4233 | int ret; |
28dfe52a | 4234 | |
54b4f68f CW |
4235 | intel_suspend_gt_powersave(dev_priv); |
4236 | ||
45c5f202 | 4237 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4238 | |
4239 | /* We have to flush all the executing contexts to main memory so | |
4240 | * that they can saved in the hibernation image. To ensure the last | |
4241 | * context image is coherent, we have to switch away from it. That | |
4242 | * leaves the dev_priv->kernel_context still active when | |
4243 | * we actually suspend, and its image in memory may not match the GPU | |
4244 | * state. Fortunately, the kernel_context is disposable and we do | |
4245 | * not rely on its state. | |
4246 | */ | |
4247 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4248 | if (ret) | |
4249 | goto err; | |
4250 | ||
22dd3bb9 CW |
4251 | ret = i915_gem_wait_for_idle(dev_priv, |
4252 | I915_WAIT_INTERRUPTIBLE | | |
4253 | I915_WAIT_LOCKED); | |
f7403347 | 4254 | if (ret) |
45c5f202 | 4255 | goto err; |
f7403347 | 4256 | |
c033666a | 4257 | i915_gem_retire_requests(dev_priv); |
28176ef4 | 4258 | GEM_BUG_ON(dev_priv->gt.active_requests); |
673a394b | 4259 | |
3033acab | 4260 | assert_kernel_context_is_current(dev_priv); |
b2e862d0 | 4261 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4262 | mutex_unlock(&dev->struct_mutex); |
4263 | ||
737b1506 | 4264 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 CW |
4265 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
4266 | flush_delayed_work(&dev_priv->gt.idle_work); | |
fbbd37b3 | 4267 | flush_work(&dev_priv->mm.free_work); |
29105ccc | 4268 | |
bdcf120b CW |
4269 | /* Assert that we sucessfully flushed all the work and |
4270 | * reset the GPU back to its idle, low power state. | |
4271 | */ | |
67d97da3 | 4272 | WARN_ON(dev_priv->gt.awake); |
31ab49ab | 4273 | WARN_ON(!intel_execlists_idle(dev_priv)); |
bdcf120b | 4274 | |
1c777c5d ID |
4275 | /* |
4276 | * Neither the BIOS, ourselves or any other kernel | |
4277 | * expects the system to be in execlists mode on startup, | |
4278 | * so we need to reset the GPU back to legacy mode. And the only | |
4279 | * known way to disable logical contexts is through a GPU reset. | |
4280 | * | |
4281 | * So in order to leave the system in a known default configuration, | |
4282 | * always reset the GPU upon unload and suspend. Afterwards we then | |
4283 | * clean up the GEM state tracking, flushing off the requests and | |
4284 | * leaving the system in a known idle state. | |
4285 | * | |
4286 | * Note that is of the upmost importance that the GPU is idle and | |
4287 | * all stray writes are flushed *before* we dismantle the backing | |
4288 | * storage for the pinned objects. | |
4289 | * | |
4290 | * However, since we are uncertain that resetting the GPU on older | |
4291 | * machines is a good idea, we don't - just in case it leaves the | |
4292 | * machine in an unusable condition. | |
4293 | */ | |
0031fb96 | 4294 | if (HAS_HW_CONTEXTS(dev_priv)) { |
1c777c5d ID |
4295 | int reset = intel_gpu_reset(dev_priv, ALL_ENGINES); |
4296 | WARN_ON(reset && reset != -ENODEV); | |
4297 | } | |
4298 | ||
673a394b | 4299 | return 0; |
45c5f202 CW |
4300 | |
4301 | err: | |
4302 | mutex_unlock(&dev->struct_mutex); | |
4303 | return ret; | |
673a394b EA |
4304 | } |
4305 | ||
bf9e8429 | 4306 | void i915_gem_resume(struct drm_i915_private *dev_priv) |
5ab57c70 | 4307 | { |
bf9e8429 | 4308 | struct drm_device *dev = &dev_priv->drm; |
5ab57c70 | 4309 | |
31ab49ab ID |
4310 | WARN_ON(dev_priv->gt.awake); |
4311 | ||
5ab57c70 | 4312 | mutex_lock(&dev->struct_mutex); |
275a991c | 4313 | i915_gem_restore_gtt_mappings(dev_priv); |
5ab57c70 CW |
4314 | |
4315 | /* As we didn't flush the kernel context before suspend, we cannot | |
4316 | * guarantee that the context image is complete. So let's just reset | |
4317 | * it and start again. | |
4318 | */ | |
821ed7df | 4319 | dev_priv->gt.resume(dev_priv); |
5ab57c70 CW |
4320 | |
4321 | mutex_unlock(&dev->struct_mutex); | |
4322 | } | |
4323 | ||
c6be607a | 4324 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) |
f691e2f4 | 4325 | { |
c6be607a | 4326 | if (INTEL_GEN(dev_priv) < 5 || |
f691e2f4 DV |
4327 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4328 | return; | |
4329 | ||
4330 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4331 | DISP_TILE_SURFACE_SWIZZLING); | |
4332 | ||
5db94019 | 4333 | if (IS_GEN5(dev_priv)) |
11782b02 DV |
4334 | return; |
4335 | ||
f691e2f4 | 4336 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
5db94019 | 4337 | if (IS_GEN6(dev_priv)) |
6b26c86d | 4338 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
5db94019 | 4339 | else if (IS_GEN7(dev_priv)) |
6b26c86d | 4340 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
5db94019 | 4341 | else if (IS_GEN8(dev_priv)) |
31a5336e | 4342 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
8782e26c BW |
4343 | else |
4344 | BUG(); | |
f691e2f4 | 4345 | } |
e21af88d | 4346 | |
50a0bc90 | 4347 | static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base) |
81e7f200 | 4348 | { |
81e7f200 VS |
4349 | I915_WRITE(RING_CTL(base), 0); |
4350 | I915_WRITE(RING_HEAD(base), 0); | |
4351 | I915_WRITE(RING_TAIL(base), 0); | |
4352 | I915_WRITE(RING_START(base), 0); | |
4353 | } | |
4354 | ||
50a0bc90 | 4355 | static void init_unused_rings(struct drm_i915_private *dev_priv) |
81e7f200 | 4356 | { |
50a0bc90 TU |
4357 | if (IS_I830(dev_priv)) { |
4358 | init_unused_ring(dev_priv, PRB1_BASE); | |
4359 | init_unused_ring(dev_priv, SRB0_BASE); | |
4360 | init_unused_ring(dev_priv, SRB1_BASE); | |
4361 | init_unused_ring(dev_priv, SRB2_BASE); | |
4362 | init_unused_ring(dev_priv, SRB3_BASE); | |
4363 | } else if (IS_GEN2(dev_priv)) { | |
4364 | init_unused_ring(dev_priv, SRB0_BASE); | |
4365 | init_unused_ring(dev_priv, SRB1_BASE); | |
4366 | } else if (IS_GEN3(dev_priv)) { | |
4367 | init_unused_ring(dev_priv, PRB1_BASE); | |
4368 | init_unused_ring(dev_priv, PRB2_BASE); | |
81e7f200 VS |
4369 | } |
4370 | } | |
4371 | ||
4fc7c971 | 4372 | int |
bf9e8429 | 4373 | i915_gem_init_hw(struct drm_i915_private *dev_priv) |
4fc7c971 | 4374 | { |
e2f80391 | 4375 | struct intel_engine_cs *engine; |
3b3f1650 | 4376 | enum intel_engine_id id; |
d200cda6 | 4377 | int ret; |
4fc7c971 | 4378 | |
de867c20 CW |
4379 | dev_priv->gt.last_init_time = ktime_get(); |
4380 | ||
5e4f5189 CW |
4381 | /* Double layer security blanket, see i915_gem_init() */ |
4382 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4383 | ||
0031fb96 | 4384 | if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4385 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4386 | |
772c2a51 | 4387 | if (IS_HASWELL(dev_priv)) |
50a0bc90 | 4388 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ? |
0bf21347 | 4389 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
9435373e | 4390 | |
6e266956 | 4391 | if (HAS_PCH_NOP(dev_priv)) { |
fd6b8f43 | 4392 | if (IS_IVYBRIDGE(dev_priv)) { |
6ba844b0 DV |
4393 | u32 temp = I915_READ(GEN7_MSG_CTL); |
4394 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4395 | I915_WRITE(GEN7_MSG_CTL, temp); | |
c6be607a | 4396 | } else if (INTEL_GEN(dev_priv) >= 7) { |
6ba844b0 DV |
4397 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
4398 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4399 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4400 | } | |
88a2b2a3 BW |
4401 | } |
4402 | ||
c6be607a | 4403 | i915_gem_init_swizzling(dev_priv); |
4fc7c971 | 4404 | |
d5abdfda DV |
4405 | /* |
4406 | * At least 830 can leave some of the unused rings | |
4407 | * "active" (ie. head != tail) after resume which | |
4408 | * will prevent c3 entry. Makes sure all unused rings | |
4409 | * are totally idle. | |
4410 | */ | |
50a0bc90 | 4411 | init_unused_rings(dev_priv); |
d5abdfda | 4412 | |
ed54c1a1 | 4413 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4414 | |
c6be607a | 4415 | ret = i915_ppgtt_init_hw(dev_priv); |
4ad2fd88 JH |
4416 | if (ret) { |
4417 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4418 | goto out; | |
4419 | } | |
4420 | ||
4421 | /* Need to do basic initialisation of all rings first: */ | |
3b3f1650 | 4422 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 4423 | ret = engine->init_hw(engine); |
35a57ffb | 4424 | if (ret) |
5e4f5189 | 4425 | goto out; |
35a57ffb | 4426 | } |
99433931 | 4427 | |
bf9e8429 | 4428 | intel_mocs_init_l3cc_table(dev_priv); |
0ccdacf6 | 4429 | |
33a732f4 | 4430 | /* We can't enable contexts until all firmware is loaded */ |
bf9e8429 | 4431 | ret = intel_guc_setup(dev_priv); |
e556f7c1 DG |
4432 | if (ret) |
4433 | goto out; | |
33a732f4 | 4434 | |
5e4f5189 CW |
4435 | out: |
4436 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4437 | return ret; |
8187a2b7 ZN |
4438 | } |
4439 | ||
39df9190 CW |
4440 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4441 | { | |
4442 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4443 | return false; | |
4444 | ||
4445 | /* TODO: make semaphores and Execlists play nicely together */ | |
4446 | if (i915.enable_execlists) | |
4447 | return false; | |
4448 | ||
4449 | if (value >= 0) | |
4450 | return value; | |
4451 | ||
4452 | #ifdef CONFIG_INTEL_IOMMU | |
4453 | /* Enable semaphores on SNB when IO remapping is off */ | |
4454 | if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped) | |
4455 | return false; | |
4456 | #endif | |
4457 | ||
4458 | return true; | |
4459 | } | |
4460 | ||
bf9e8429 | 4461 | int i915_gem_init(struct drm_i915_private *dev_priv) |
1070a42b | 4462 | { |
1070a42b CW |
4463 | int ret; |
4464 | ||
bf9e8429 | 4465 | mutex_lock(&dev_priv->drm.struct_mutex); |
d62b4892 | 4466 | |
a83014d3 | 4467 | if (!i915.enable_execlists) { |
821ed7df | 4468 | dev_priv->gt.resume = intel_legacy_submission_resume; |
7e37f889 | 4469 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
454afebd | 4470 | } else { |
821ed7df | 4471 | dev_priv->gt.resume = intel_lr_context_resume; |
117897f4 | 4472 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
a83014d3 OM |
4473 | } |
4474 | ||
5e4f5189 CW |
4475 | /* This is just a security blanket to placate dragons. |
4476 | * On some systems, we very sporadically observe that the first TLBs | |
4477 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4478 | * we hold the forcewake during initialisation these problems | |
4479 | * just magically go away. | |
4480 | */ | |
4481 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4482 | ||
72778cb2 | 4483 | i915_gem_init_userptr(dev_priv); |
f6b9d5ca CW |
4484 | |
4485 | ret = i915_gem_init_ggtt(dev_priv); | |
4486 | if (ret) | |
4487 | goto out_unlock; | |
d62b4892 | 4488 | |
bf9e8429 | 4489 | ret = i915_gem_context_init(dev_priv); |
7bcc3777 JN |
4490 | if (ret) |
4491 | goto out_unlock; | |
2fa48d8d | 4492 | |
bf9e8429 | 4493 | ret = intel_engines_init(dev_priv); |
35a57ffb | 4494 | if (ret) |
7bcc3777 | 4495 | goto out_unlock; |
2fa48d8d | 4496 | |
bf9e8429 | 4497 | ret = i915_gem_init_hw(dev_priv); |
60990320 | 4498 | if (ret == -EIO) { |
7e21d648 | 4499 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4500 | * wedged. But we only want to do this where the GPU is angry, |
4501 | * for all other failure, such as an allocation failure, bail. | |
4502 | */ | |
4503 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
821ed7df | 4504 | i915_gem_set_wedged(dev_priv); |
60990320 | 4505 | ret = 0; |
1070a42b | 4506 | } |
7bcc3777 JN |
4507 | |
4508 | out_unlock: | |
5e4f5189 | 4509 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
bf9e8429 | 4510 | mutex_unlock(&dev_priv->drm.struct_mutex); |
1070a42b | 4511 | |
60990320 | 4512 | return ret; |
1070a42b CW |
4513 | } |
4514 | ||
8187a2b7 | 4515 | void |
cb15d9f8 | 4516 | i915_gem_cleanup_engines(struct drm_i915_private *dev_priv) |
8187a2b7 | 4517 | { |
e2f80391 | 4518 | struct intel_engine_cs *engine; |
3b3f1650 | 4519 | enum intel_engine_id id; |
8187a2b7 | 4520 | |
3b3f1650 | 4521 | for_each_engine(engine, dev_priv, id) |
117897f4 | 4522 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4523 | } |
4524 | ||
40ae4e16 ID |
4525 | void |
4526 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4527 | { | |
49ef5294 | 4528 | int i; |
40ae4e16 ID |
4529 | |
4530 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4531 | !IS_CHERRYVIEW(dev_priv)) | |
4532 | dev_priv->num_fence_regs = 32; | |
73f67aa8 JN |
4533 | else if (INTEL_INFO(dev_priv)->gen >= 4 || |
4534 | IS_I945G(dev_priv) || IS_I945GM(dev_priv) || | |
4535 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) | |
40ae4e16 ID |
4536 | dev_priv->num_fence_regs = 16; |
4537 | else | |
4538 | dev_priv->num_fence_regs = 8; | |
4539 | ||
c033666a | 4540 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4541 | dev_priv->num_fence_regs = |
4542 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4543 | ||
4544 | /* Initialize fence registers to zero */ | |
49ef5294 CW |
4545 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
4546 | struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i]; | |
4547 | ||
4548 | fence->i915 = dev_priv; | |
4549 | fence->id = i; | |
4550 | list_add_tail(&fence->link, &dev_priv->mm.fence_list); | |
4551 | } | |
4362f4f6 | 4552 | i915_gem_restore_fences(dev_priv); |
40ae4e16 | 4553 | |
4362f4f6 | 4554 | i915_gem_detect_bit_6_swizzle(dev_priv); |
40ae4e16 ID |
4555 | } |
4556 | ||
73cb9701 | 4557 | int |
cb15d9f8 | 4558 | i915_gem_load_init(struct drm_i915_private *dev_priv) |
673a394b | 4559 | { |
a933568e | 4560 | int err = -ENOMEM; |
42dcedd4 | 4561 | |
a933568e TU |
4562 | dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN); |
4563 | if (!dev_priv->objects) | |
73cb9701 | 4564 | goto err_out; |
73cb9701 | 4565 | |
a933568e TU |
4566 | dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN); |
4567 | if (!dev_priv->vmas) | |
73cb9701 | 4568 | goto err_objects; |
73cb9701 | 4569 | |
a933568e TU |
4570 | dev_priv->requests = KMEM_CACHE(drm_i915_gem_request, |
4571 | SLAB_HWCACHE_ALIGN | | |
4572 | SLAB_RECLAIM_ACCOUNT | | |
4573 | SLAB_DESTROY_BY_RCU); | |
4574 | if (!dev_priv->requests) | |
73cb9701 | 4575 | goto err_vmas; |
73cb9701 | 4576 | |
52e54209 CW |
4577 | dev_priv->dependencies = KMEM_CACHE(i915_dependency, |
4578 | SLAB_HWCACHE_ALIGN | | |
4579 | SLAB_RECLAIM_ACCOUNT); | |
4580 | if (!dev_priv->dependencies) | |
4581 | goto err_requests; | |
4582 | ||
73cb9701 CW |
4583 | mutex_lock(&dev_priv->drm.struct_mutex); |
4584 | INIT_LIST_HEAD(&dev_priv->gt.timelines); | |
bb89485e | 4585 | err = i915_gem_timeline_init__global(dev_priv); |
73cb9701 CW |
4586 | mutex_unlock(&dev_priv->drm.struct_mutex); |
4587 | if (err) | |
52e54209 | 4588 | goto err_dependencies; |
673a394b | 4589 | |
a33afea5 | 4590 | INIT_LIST_HEAD(&dev_priv->context_list); |
fbbd37b3 CW |
4591 | INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work); |
4592 | init_llist_head(&dev_priv->mm.free_list); | |
6c085a72 CW |
4593 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4594 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4595 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
275f039d | 4596 | INIT_LIST_HEAD(&dev_priv->mm.userfault_list); |
67d97da3 | 4597 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4598 | i915_gem_retire_work_handler); |
67d97da3 | 4599 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4600 | i915_gem_idle_work_handler); |
1f15b76f | 4601 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4602 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4603 | |
72bfa19c CW |
4604 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4605 | ||
6b95a207 | 4606 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4607 | |
ce453d81 CW |
4608 | dev_priv->mm.interruptible = true; |
4609 | ||
6f633402 JL |
4610 | atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); |
4611 | ||
b5add959 | 4612 | spin_lock_init(&dev_priv->fb_tracking.lock); |
73cb9701 CW |
4613 | |
4614 | return 0; | |
4615 | ||
52e54209 CW |
4616 | err_dependencies: |
4617 | kmem_cache_destroy(dev_priv->dependencies); | |
73cb9701 CW |
4618 | err_requests: |
4619 | kmem_cache_destroy(dev_priv->requests); | |
4620 | err_vmas: | |
4621 | kmem_cache_destroy(dev_priv->vmas); | |
4622 | err_objects: | |
4623 | kmem_cache_destroy(dev_priv->objects); | |
4624 | err_out: | |
4625 | return err; | |
673a394b | 4626 | } |
71acb5eb | 4627 | |
cb15d9f8 | 4628 | void i915_gem_load_cleanup(struct drm_i915_private *dev_priv) |
d64aa096 | 4629 | { |
7d5d59e5 CW |
4630 | WARN_ON(!llist_empty(&dev_priv->mm.free_list)); |
4631 | ||
ea84aa77 MA |
4632 | mutex_lock(&dev_priv->drm.struct_mutex); |
4633 | i915_gem_timeline_fini(&dev_priv->gt.global_timeline); | |
4634 | WARN_ON(!list_empty(&dev_priv->gt.timelines)); | |
4635 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4636 | ||
52e54209 | 4637 | kmem_cache_destroy(dev_priv->dependencies); |
d64aa096 ID |
4638 | kmem_cache_destroy(dev_priv->requests); |
4639 | kmem_cache_destroy(dev_priv->vmas); | |
4640 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
4641 | |
4642 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
4643 | rcu_barrier(); | |
d64aa096 ID |
4644 | } |
4645 | ||
6a800eab CW |
4646 | int i915_gem_freeze(struct drm_i915_private *dev_priv) |
4647 | { | |
4648 | intel_runtime_pm_get(dev_priv); | |
4649 | ||
4650 | mutex_lock(&dev_priv->drm.struct_mutex); | |
4651 | i915_gem_shrink_all(dev_priv); | |
4652 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4653 | ||
4654 | intel_runtime_pm_put(dev_priv); | |
4655 | ||
4656 | return 0; | |
4657 | } | |
4658 | ||
461fb99c CW |
4659 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4660 | { | |
4661 | struct drm_i915_gem_object *obj; | |
7aab2d53 CW |
4662 | struct list_head *phases[] = { |
4663 | &dev_priv->mm.unbound_list, | |
4664 | &dev_priv->mm.bound_list, | |
4665 | NULL | |
4666 | }, **p; | |
461fb99c CW |
4667 | |
4668 | /* Called just before we write the hibernation image. | |
4669 | * | |
4670 | * We need to update the domain tracking to reflect that the CPU | |
4671 | * will be accessing all the pages to create and restore from the | |
4672 | * hibernation, and so upon restoration those pages will be in the | |
4673 | * CPU domain. | |
4674 | * | |
4675 | * To make sure the hibernation image contains the latest state, | |
4676 | * we update that state just before writing out the image. | |
7aab2d53 CW |
4677 | * |
4678 | * To try and reduce the hibernation image, we manually shrink | |
4679 | * the objects as well. | |
461fb99c CW |
4680 | */ |
4681 | ||
6a800eab CW |
4682 | mutex_lock(&dev_priv->drm.struct_mutex); |
4683 | i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND); | |
461fb99c | 4684 | |
7aab2d53 | 4685 | for (p = phases; *p; p++) { |
56cea323 | 4686 | list_for_each_entry(obj, *p, global_link) { |
7aab2d53 CW |
4687 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4688 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4689 | } | |
461fb99c | 4690 | } |
6a800eab | 4691 | mutex_unlock(&dev_priv->drm.struct_mutex); |
461fb99c CW |
4692 | |
4693 | return 0; | |
4694 | } | |
4695 | ||
f787a5f5 | 4696 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4697 | { |
f787a5f5 | 4698 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 4699 | struct drm_i915_gem_request *request; |
b962442e EA |
4700 | |
4701 | /* Clean up our request list when the client is going away, so that | |
4702 | * later retire_requests won't dereference our soon-to-be-gone | |
4703 | * file_priv. | |
4704 | */ | |
1c25595f | 4705 | spin_lock(&file_priv->mm.lock); |
15f7bbc7 | 4706 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) |
f787a5f5 | 4707 | request->file_priv = NULL; |
1c25595f | 4708 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 4709 | |
2e1b8730 | 4710 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 4711 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 4712 | list_del(&file_priv->rps.link); |
8d3afd7d | 4713 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 4714 | } |
b29c19b6 CW |
4715 | } |
4716 | ||
4717 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4718 | { | |
4719 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4720 | int ret; |
b29c19b6 | 4721 | |
c4c29d7b | 4722 | DRM_DEBUG("\n"); |
b29c19b6 CW |
4723 | |
4724 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4725 | if (!file_priv) | |
4726 | return -ENOMEM; | |
4727 | ||
4728 | file->driver_priv = file_priv; | |
f19ec8cb | 4729 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 4730 | file_priv->file = file; |
2e1b8730 | 4731 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
4732 | |
4733 | spin_lock_init(&file_priv->mm.lock); | |
4734 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 4735 | |
c80ff16e | 4736 | file_priv->bsd_engine = -1; |
de1add36 | 4737 | |
e422b888 BW |
4738 | ret = i915_gem_context_open(dev, file); |
4739 | if (ret) | |
4740 | kfree(file_priv); | |
b29c19b6 | 4741 | |
e422b888 | 4742 | return ret; |
b29c19b6 CW |
4743 | } |
4744 | ||
b680c37a DV |
4745 | /** |
4746 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
4747 | * @old: current GEM buffer for the frontbuffer slots |
4748 | * @new: new GEM buffer for the frontbuffer slots | |
4749 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
4750 | * |
4751 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
4752 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
4753 | */ | |
a071fa00 DV |
4754 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4755 | struct drm_i915_gem_object *new, | |
4756 | unsigned frontbuffer_bits) | |
4757 | { | |
faf5bf0a CW |
4758 | /* Control of individual bits within the mask are guarded by |
4759 | * the owning plane->mutex, i.e. we can never see concurrent | |
4760 | * manipulation of individual bits. But since the bitfield as a whole | |
4761 | * is updated using RMW, we need to use atomics in order to update | |
4762 | * the bits. | |
4763 | */ | |
4764 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
4765 | sizeof(atomic_t) * BITS_PER_BYTE); | |
4766 | ||
a071fa00 | 4767 | if (old) { |
faf5bf0a CW |
4768 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
4769 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
4770 | } |
4771 | ||
4772 | if (new) { | |
faf5bf0a CW |
4773 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
4774 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
4775 | } |
4776 | } | |
4777 | ||
ea70299d DG |
4778 | /* Allocate a new GEM object and fill it with the supplied data */ |
4779 | struct drm_i915_gem_object * | |
12d79d78 | 4780 | i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, |
ea70299d DG |
4781 | const void *data, size_t size) |
4782 | { | |
4783 | struct drm_i915_gem_object *obj; | |
4784 | struct sg_table *sg; | |
4785 | size_t bytes; | |
4786 | int ret; | |
4787 | ||
12d79d78 | 4788 | obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE)); |
fe3db79b | 4789 | if (IS_ERR(obj)) |
ea70299d DG |
4790 | return obj; |
4791 | ||
4792 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
4793 | if (ret) | |
4794 | goto fail; | |
4795 | ||
a4f5ea64 | 4796 | ret = i915_gem_object_pin_pages(obj); |
ea70299d DG |
4797 | if (ret) |
4798 | goto fail; | |
4799 | ||
a4f5ea64 | 4800 | sg = obj->mm.pages; |
ea70299d | 4801 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); |
a4f5ea64 | 4802 | obj->mm.dirty = true; /* Backing store is now out of date */ |
ea70299d DG |
4803 | i915_gem_object_unpin_pages(obj); |
4804 | ||
4805 | if (WARN_ON(bytes != size)) { | |
4806 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
4807 | ret = -EFAULT; | |
4808 | goto fail; | |
4809 | } | |
4810 | ||
4811 | return obj; | |
4812 | ||
4813 | fail: | |
f8c417cd | 4814 | i915_gem_object_put(obj); |
ea70299d DG |
4815 | return ERR_PTR(ret); |
4816 | } | |
96d77634 CW |
4817 | |
4818 | struct scatterlist * | |
4819 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
4820 | unsigned int n, | |
4821 | unsigned int *offset) | |
4822 | { | |
a4f5ea64 | 4823 | struct i915_gem_object_page_iter *iter = &obj->mm.get_page; |
96d77634 CW |
4824 | struct scatterlist *sg; |
4825 | unsigned int idx, count; | |
4826 | ||
4827 | might_sleep(); | |
4828 | GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT); | |
a4f5ea64 | 4829 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
96d77634 CW |
4830 | |
4831 | /* As we iterate forward through the sg, we record each entry in a | |
4832 | * radixtree for quick repeated (backwards) lookups. If we have seen | |
4833 | * this index previously, we will have an entry for it. | |
4834 | * | |
4835 | * Initial lookup is O(N), but this is amortized to O(1) for | |
4836 | * sequential page access (where each new request is consecutive | |
4837 | * to the previous one). Repeated lookups are O(lg(obj->base.size)), | |
4838 | * i.e. O(1) with a large constant! | |
4839 | */ | |
4840 | if (n < READ_ONCE(iter->sg_idx)) | |
4841 | goto lookup; | |
4842 | ||
4843 | mutex_lock(&iter->lock); | |
4844 | ||
4845 | /* We prefer to reuse the last sg so that repeated lookup of this | |
4846 | * (or the subsequent) sg are fast - comparing against the last | |
4847 | * sg is faster than going through the radixtree. | |
4848 | */ | |
4849 | ||
4850 | sg = iter->sg_pos; | |
4851 | idx = iter->sg_idx; | |
4852 | count = __sg_page_count(sg); | |
4853 | ||
4854 | while (idx + count <= n) { | |
4855 | unsigned long exception, i; | |
4856 | int ret; | |
4857 | ||
4858 | /* If we cannot allocate and insert this entry, or the | |
4859 | * individual pages from this range, cancel updating the | |
4860 | * sg_idx so that on this lookup we are forced to linearly | |
4861 | * scan onwards, but on future lookups we will try the | |
4862 | * insertion again (in which case we need to be careful of | |
4863 | * the error return reporting that we have already inserted | |
4864 | * this index). | |
4865 | */ | |
4866 | ret = radix_tree_insert(&iter->radix, idx, sg); | |
4867 | if (ret && ret != -EEXIST) | |
4868 | goto scan; | |
4869 | ||
4870 | exception = | |
4871 | RADIX_TREE_EXCEPTIONAL_ENTRY | | |
4872 | idx << RADIX_TREE_EXCEPTIONAL_SHIFT; | |
4873 | for (i = 1; i < count; i++) { | |
4874 | ret = radix_tree_insert(&iter->radix, idx + i, | |
4875 | (void *)exception); | |
4876 | if (ret && ret != -EEXIST) | |
4877 | goto scan; | |
4878 | } | |
4879 | ||
4880 | idx += count; | |
4881 | sg = ____sg_next(sg); | |
4882 | count = __sg_page_count(sg); | |
4883 | } | |
4884 | ||
4885 | scan: | |
4886 | iter->sg_pos = sg; | |
4887 | iter->sg_idx = idx; | |
4888 | ||
4889 | mutex_unlock(&iter->lock); | |
4890 | ||
4891 | if (unlikely(n < idx)) /* insertion completed by another thread */ | |
4892 | goto lookup; | |
4893 | ||
4894 | /* In case we failed to insert the entry into the radixtree, we need | |
4895 | * to look beyond the current sg. | |
4896 | */ | |
4897 | while (idx + count <= n) { | |
4898 | idx += count; | |
4899 | sg = ____sg_next(sg); | |
4900 | count = __sg_page_count(sg); | |
4901 | } | |
4902 | ||
4903 | *offset = n - idx; | |
4904 | return sg; | |
4905 | ||
4906 | lookup: | |
4907 | rcu_read_lock(); | |
4908 | ||
4909 | sg = radix_tree_lookup(&iter->radix, n); | |
4910 | GEM_BUG_ON(!sg); | |
4911 | ||
4912 | /* If this index is in the middle of multi-page sg entry, | |
4913 | * the radixtree will contain an exceptional entry that points | |
4914 | * to the start of that range. We will return the pointer to | |
4915 | * the base page and the offset of this page within the | |
4916 | * sg entry's range. | |
4917 | */ | |
4918 | *offset = 0; | |
4919 | if (unlikely(radix_tree_exception(sg))) { | |
4920 | unsigned long base = | |
4921 | (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT; | |
4922 | ||
4923 | sg = radix_tree_lookup(&iter->radix, base); | |
4924 | GEM_BUG_ON(!sg); | |
4925 | ||
4926 | *offset = n - base; | |
4927 | } | |
4928 | ||
4929 | rcu_read_unlock(); | |
4930 | ||
4931 | return sg; | |
4932 | } | |
4933 | ||
4934 | struct page * | |
4935 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n) | |
4936 | { | |
4937 | struct scatterlist *sg; | |
4938 | unsigned int offset; | |
4939 | ||
4940 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); | |
4941 | ||
4942 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
4943 | return nth_page(sg_page(sg), offset); | |
4944 | } | |
4945 | ||
4946 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ | |
4947 | struct page * | |
4948 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
4949 | unsigned int n) | |
4950 | { | |
4951 | struct page *page; | |
4952 | ||
4953 | page = i915_gem_object_get_page(obj, n); | |
a4f5ea64 | 4954 | if (!obj->mm.dirty) |
96d77634 CW |
4955 | set_page_dirty(page); |
4956 | ||
4957 | return page; | |
4958 | } | |
4959 | ||
4960 | dma_addr_t | |
4961 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
4962 | unsigned long n) | |
4963 | { | |
4964 | struct scatterlist *sg; | |
4965 | unsigned int offset; | |
4966 | ||
4967 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
4968 | return sg_dma_address(sg) + (offset << PAGE_SHIFT); | |
4969 | } |