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Commit | Line | Data |
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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
57822dc6 | 32 | #include "i915_gem_clflush.h" |
eb82289a | 33 | #include "i915_vgpu.h" |
1c5d22f7 | 34 | #include "i915_trace.h" |
652c393a | 35 | #include "intel_drv.h" |
5d723d7a | 36 | #include "intel_frontbuffer.h" |
0ccdacf6 | 37 | #include "intel_mocs.h" |
59b449d5 | 38 | #include "intel_workarounds.h" |
465c403c | 39 | #include "i915_gemfs.h" |
6b5e90f5 | 40 | #include <linux/dma-fence-array.h> |
fe3288b5 | 41 | #include <linux/kthread.h> |
c13d87ea | 42 | #include <linux/reservation.h> |
5949eac4 | 43 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 44 | #include <linux/slab.h> |
20e4933c | 45 | #include <linux/stop_machine.h> |
673a394b | 46 | #include <linux/swap.h> |
79e53945 | 47 | #include <linux/pci.h> |
1286ff73 | 48 | #include <linux/dma-buf.h> |
673a394b | 49 | |
fbbd37b3 | 50 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915); |
61050808 | 51 | |
2c22569b CW |
52 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
53 | { | |
e27ab73d | 54 | if (obj->cache_dirty) |
b50a5371 AS |
55 | return false; |
56 | ||
b8f55be6 | 57 | if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE)) |
2c22569b CW |
58 | return true; |
59 | ||
bd3d2252 | 60 | return obj->pin_global; /* currently in use by HW, keep flushed */ |
2c22569b CW |
61 | } |
62 | ||
4f1959ee | 63 | static int |
bb6dc8d9 | 64 | insert_mappable_node(struct i915_ggtt *ggtt, |
4f1959ee AS |
65 | struct drm_mm_node *node, u32 size) |
66 | { | |
67 | memset(node, 0, sizeof(*node)); | |
82ad6443 | 68 | return drm_mm_insert_node_in_range(&ggtt->vm.mm, node, |
4e64e553 CW |
69 | size, 0, I915_COLOR_UNEVICTABLE, |
70 | 0, ggtt->mappable_end, | |
71 | DRM_MM_INSERT_LOW); | |
4f1959ee AS |
72 | } |
73 | ||
74 | static void | |
75 | remove_mappable_node(struct drm_mm_node *node) | |
76 | { | |
77 | drm_mm_remove_node(node); | |
78 | } | |
79 | ||
73aa808f CW |
80 | /* some bookkeeping */ |
81 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 82 | u64 size) |
73aa808f | 83 | { |
c20e8355 | 84 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
85 | dev_priv->mm.object_count++; |
86 | dev_priv->mm.object_memory += size; | |
c20e8355 | 87 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
88 | } |
89 | ||
90 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 91 | u64 size) |
73aa808f | 92 | { |
c20e8355 | 93 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
94 | dev_priv->mm.object_count--; |
95 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 96 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
97 | } |
98 | ||
21dd3734 | 99 | static int |
33196ded | 100 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 101 | { |
30dbf0c0 CW |
102 | int ret; |
103 | ||
4c7d62c6 CW |
104 | might_sleep(); |
105 | ||
0a6759c6 DV |
106 | /* |
107 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
108 | * userspace. If it takes that long something really bad is going on and | |
109 | * we should simply try to bail out and fail as gracefully as possible. | |
110 | */ | |
1f83fee0 | 111 | ret = wait_event_interruptible_timeout(error->reset_queue, |
8c185eca | 112 | !i915_reset_backoff(error), |
b52992c0 | 113 | I915_RESET_TIMEOUT); |
0a6759c6 DV |
114 | if (ret == 0) { |
115 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
116 | return -EIO; | |
117 | } else if (ret < 0) { | |
30dbf0c0 | 118 | return ret; |
d98c52cf CW |
119 | } else { |
120 | return 0; | |
0a6759c6 | 121 | } |
30dbf0c0 CW |
122 | } |
123 | ||
54cf91dc | 124 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 125 | { |
fac5e23e | 126 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
127 | int ret; |
128 | ||
33196ded | 129 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
130 | if (ret) |
131 | return ret; | |
132 | ||
133 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
134 | if (ret) | |
135 | return ret; | |
136 | ||
76c1dec1 CW |
137 | return 0; |
138 | } | |
30dbf0c0 | 139 | |
e4d2006f CW |
140 | static u32 __i915_gem_park(struct drm_i915_private *i915) |
141 | { | |
4dfacb0b CW |
142 | GEM_TRACE("\n"); |
143 | ||
e4d2006f CW |
144 | lockdep_assert_held(&i915->drm.struct_mutex); |
145 | GEM_BUG_ON(i915->gt.active_requests); | |
643b450a | 146 | GEM_BUG_ON(!list_empty(&i915->gt.active_rings)); |
e4d2006f CW |
147 | |
148 | if (!i915->gt.awake) | |
149 | return I915_EPOCH_INVALID; | |
150 | ||
151 | GEM_BUG_ON(i915->gt.epoch == I915_EPOCH_INVALID); | |
152 | ||
153 | /* | |
154 | * Be paranoid and flush a concurrent interrupt to make sure | |
155 | * we don't reactivate any irq tasklets after parking. | |
156 | * | |
157 | * FIXME: Note that even though we have waited for execlists to be idle, | |
158 | * there may still be an in-flight interrupt even though the CSB | |
159 | * is now empty. synchronize_irq() makes sure that a residual interrupt | |
160 | * is completed before we continue, but it doesn't prevent the HW from | |
161 | * raising a spurious interrupt later. To complete the shield we should | |
162 | * coordinate disabling the CS irq with flushing the interrupts. | |
163 | */ | |
164 | synchronize_irq(i915->drm.irq); | |
165 | ||
166 | intel_engines_park(i915); | |
a89d1f92 | 167 | i915_timelines_park(i915); |
e4d2006f CW |
168 | |
169 | i915_pmu_gt_parked(i915); | |
3365e226 | 170 | i915_vma_parked(i915); |
e4d2006f CW |
171 | |
172 | i915->gt.awake = false; | |
173 | ||
174 | if (INTEL_GEN(i915) >= 6) | |
175 | gen6_rps_idle(i915); | |
176 | ||
177 | intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ); | |
178 | ||
179 | intel_runtime_pm_put(i915); | |
180 | ||
181 | return i915->gt.epoch; | |
182 | } | |
183 | ||
184 | void i915_gem_park(struct drm_i915_private *i915) | |
185 | { | |
4dfacb0b CW |
186 | GEM_TRACE("\n"); |
187 | ||
e4d2006f CW |
188 | lockdep_assert_held(&i915->drm.struct_mutex); |
189 | GEM_BUG_ON(i915->gt.active_requests); | |
190 | ||
191 | if (!i915->gt.awake) | |
192 | return; | |
193 | ||
194 | /* Defer the actual call to __i915_gem_park() to prevent ping-pongs */ | |
195 | mod_delayed_work(i915->wq, &i915->gt.idle_work, msecs_to_jiffies(100)); | |
196 | } | |
197 | ||
198 | void i915_gem_unpark(struct drm_i915_private *i915) | |
199 | { | |
4dfacb0b CW |
200 | GEM_TRACE("\n"); |
201 | ||
e4d2006f CW |
202 | lockdep_assert_held(&i915->drm.struct_mutex); |
203 | GEM_BUG_ON(!i915->gt.active_requests); | |
204 | ||
205 | if (i915->gt.awake) | |
206 | return; | |
207 | ||
208 | intel_runtime_pm_get_noresume(i915); | |
209 | ||
210 | /* | |
211 | * It seems that the DMC likes to transition between the DC states a lot | |
212 | * when there are no connected displays (no active power domains) during | |
213 | * command submission. | |
214 | * | |
215 | * This activity has negative impact on the performance of the chip with | |
216 | * huge latencies observed in the interrupt handler and elsewhere. | |
217 | * | |
218 | * Work around it by grabbing a GT IRQ power domain whilst there is any | |
219 | * GT activity, preventing any DC state transitions. | |
220 | */ | |
221 | intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ); | |
222 | ||
223 | i915->gt.awake = true; | |
224 | if (unlikely(++i915->gt.epoch == 0)) /* keep 0 as invalid */ | |
225 | i915->gt.epoch = 1; | |
226 | ||
227 | intel_enable_gt_powersave(i915); | |
228 | i915_update_gfx_val(i915); | |
229 | if (INTEL_GEN(i915) >= 6) | |
230 | gen6_rps_busy(i915); | |
231 | i915_pmu_gt_unparked(i915); | |
232 | ||
233 | intel_engines_unpark(i915); | |
234 | ||
235 | i915_queue_hangcheck(i915); | |
236 | ||
237 | queue_delayed_work(i915->wq, | |
238 | &i915->gt.retire_work, | |
239 | round_jiffies_up_relative(HZ)); | |
240 | } | |
241 | ||
5a125c3c EA |
242 | int |
243 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 244 | struct drm_file *file) |
5a125c3c | 245 | { |
72e96d64 | 246 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 247 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 248 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 249 | struct i915_vma *vma; |
ff8f7975 | 250 | u64 pinned; |
5a125c3c | 251 | |
82ad6443 | 252 | pinned = ggtt->vm.reserved; |
73aa808f | 253 | mutex_lock(&dev->struct_mutex); |
82ad6443 | 254 | list_for_each_entry(vma, &ggtt->vm.active_list, vm_link) |
20dfbde4 | 255 | if (i915_vma_is_pinned(vma)) |
ca1543be | 256 | pinned += vma->node.size; |
82ad6443 | 257 | list_for_each_entry(vma, &ggtt->vm.inactive_list, vm_link) |
20dfbde4 | 258 | if (i915_vma_is_pinned(vma)) |
ca1543be | 259 | pinned += vma->node.size; |
73aa808f | 260 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 261 | |
82ad6443 | 262 | args->aper_size = ggtt->vm.total; |
0206e353 | 263 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 264 | |
5a125c3c EA |
265 | return 0; |
266 | } | |
267 | ||
b91b09ee | 268 | static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
00731155 | 269 | { |
93c76a3d | 270 | struct address_space *mapping = obj->base.filp->f_mapping; |
dbb4351b | 271 | drm_dma_handle_t *phys; |
6a2c4232 CW |
272 | struct sg_table *st; |
273 | struct scatterlist *sg; | |
dbb4351b | 274 | char *vaddr; |
6a2c4232 | 275 | int i; |
b91b09ee | 276 | int err; |
00731155 | 277 | |
6a2c4232 | 278 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
b91b09ee | 279 | return -EINVAL; |
6a2c4232 | 280 | |
dbb4351b CW |
281 | /* Always aligning to the object size, allows a single allocation |
282 | * to handle all possible callers, and given typical object sizes, | |
283 | * the alignment of the buddy allocation will naturally match. | |
284 | */ | |
285 | phys = drm_pci_alloc(obj->base.dev, | |
750fae23 | 286 | roundup_pow_of_two(obj->base.size), |
dbb4351b CW |
287 | roundup_pow_of_two(obj->base.size)); |
288 | if (!phys) | |
b91b09ee | 289 | return -ENOMEM; |
dbb4351b CW |
290 | |
291 | vaddr = phys->vaddr; | |
6a2c4232 CW |
292 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
293 | struct page *page; | |
294 | char *src; | |
295 | ||
296 | page = shmem_read_mapping_page(mapping, i); | |
dbb4351b | 297 | if (IS_ERR(page)) { |
b91b09ee | 298 | err = PTR_ERR(page); |
dbb4351b CW |
299 | goto err_phys; |
300 | } | |
6a2c4232 CW |
301 | |
302 | src = kmap_atomic(page); | |
303 | memcpy(vaddr, src, PAGE_SIZE); | |
304 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
305 | kunmap_atomic(src); | |
306 | ||
09cbfeaf | 307 | put_page(page); |
6a2c4232 CW |
308 | vaddr += PAGE_SIZE; |
309 | } | |
310 | ||
c033666a | 311 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
312 | |
313 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
dbb4351b | 314 | if (!st) { |
b91b09ee | 315 | err = -ENOMEM; |
dbb4351b CW |
316 | goto err_phys; |
317 | } | |
6a2c4232 CW |
318 | |
319 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
320 | kfree(st); | |
b91b09ee | 321 | err = -ENOMEM; |
dbb4351b | 322 | goto err_phys; |
6a2c4232 CW |
323 | } |
324 | ||
325 | sg = st->sgl; | |
326 | sg->offset = 0; | |
327 | sg->length = obj->base.size; | |
00731155 | 328 | |
dbb4351b | 329 | sg_dma_address(sg) = phys->busaddr; |
6a2c4232 CW |
330 | sg_dma_len(sg) = obj->base.size; |
331 | ||
dbb4351b | 332 | obj->phys_handle = phys; |
b91b09ee | 333 | |
a5c08166 | 334 | __i915_gem_object_set_pages(obj, st, sg->length); |
b91b09ee MA |
335 | |
336 | return 0; | |
dbb4351b CW |
337 | |
338 | err_phys: | |
339 | drm_pci_free(obj->base.dev, phys); | |
b91b09ee MA |
340 | |
341 | return err; | |
6a2c4232 CW |
342 | } |
343 | ||
e27ab73d CW |
344 | static void __start_cpu_write(struct drm_i915_gem_object *obj) |
345 | { | |
c0a51fd0 CK |
346 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
347 | obj->write_domain = I915_GEM_DOMAIN_CPU; | |
e27ab73d CW |
348 | if (cpu_write_needs_clflush(obj)) |
349 | obj->cache_dirty = true; | |
350 | } | |
351 | ||
6a2c4232 | 352 | static void |
2b3c8317 | 353 | __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, |
e5facdf9 CW |
354 | struct sg_table *pages, |
355 | bool needs_clflush) | |
6a2c4232 | 356 | { |
a4f5ea64 | 357 | GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED); |
00731155 | 358 | |
a4f5ea64 CW |
359 | if (obj->mm.madv == I915_MADV_DONTNEED) |
360 | obj->mm.dirty = false; | |
6a2c4232 | 361 | |
e5facdf9 | 362 | if (needs_clflush && |
c0a51fd0 | 363 | (obj->read_domains & I915_GEM_DOMAIN_CPU) == 0 && |
b8f55be6 | 364 | !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) |
2b3c8317 | 365 | drm_clflush_sg(pages); |
03ac84f1 | 366 | |
e27ab73d | 367 | __start_cpu_write(obj); |
03ac84f1 CW |
368 | } |
369 | ||
370 | static void | |
371 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj, | |
372 | struct sg_table *pages) | |
373 | { | |
e5facdf9 | 374 | __i915_gem_object_release_shmem(obj, pages, false); |
03ac84f1 | 375 | |
a4f5ea64 | 376 | if (obj->mm.dirty) { |
93c76a3d | 377 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 | 378 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
379 | int i; |
380 | ||
381 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
382 | struct page *page; |
383 | char *dst; | |
384 | ||
385 | page = shmem_read_mapping_page(mapping, i); | |
386 | if (IS_ERR(page)) | |
387 | continue; | |
388 | ||
389 | dst = kmap_atomic(page); | |
390 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
391 | memcpy(dst, vaddr, PAGE_SIZE); | |
392 | kunmap_atomic(dst); | |
393 | ||
394 | set_page_dirty(page); | |
a4f5ea64 | 395 | if (obj->mm.madv == I915_MADV_WILLNEED) |
00731155 | 396 | mark_page_accessed(page); |
09cbfeaf | 397 | put_page(page); |
00731155 CW |
398 | vaddr += PAGE_SIZE; |
399 | } | |
a4f5ea64 | 400 | obj->mm.dirty = false; |
00731155 CW |
401 | } |
402 | ||
03ac84f1 CW |
403 | sg_free_table(pages); |
404 | kfree(pages); | |
dbb4351b CW |
405 | |
406 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
6a2c4232 CW |
407 | } |
408 | ||
409 | static void | |
410 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
411 | { | |
a4f5ea64 | 412 | i915_gem_object_unpin_pages(obj); |
6a2c4232 CW |
413 | } |
414 | ||
415 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
416 | .get_pages = i915_gem_object_get_pages_phys, | |
417 | .put_pages = i915_gem_object_put_pages_phys, | |
418 | .release = i915_gem_object_release_phys, | |
419 | }; | |
420 | ||
581ab1fe CW |
421 | static const struct drm_i915_gem_object_ops i915_gem_object_ops; |
422 | ||
35a9611c | 423 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
aa653a68 CW |
424 | { |
425 | struct i915_vma *vma; | |
426 | LIST_HEAD(still_in_list); | |
02bef8f9 CW |
427 | int ret; |
428 | ||
429 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
aa653a68 | 430 | |
02bef8f9 CW |
431 | /* Closed vma are removed from the obj->vma_list - but they may |
432 | * still have an active binding on the object. To remove those we | |
433 | * must wait for all rendering to complete to the object (as unbinding | |
434 | * must anyway), and retire the requests. | |
aa653a68 | 435 | */ |
5888fc9e | 436 | ret = i915_gem_object_set_to_cpu_domain(obj, false); |
02bef8f9 CW |
437 | if (ret) |
438 | return ret; | |
439 | ||
aa653a68 CW |
440 | while ((vma = list_first_entry_or_null(&obj->vma_list, |
441 | struct i915_vma, | |
442 | obj_link))) { | |
443 | list_move_tail(&vma->obj_link, &still_in_list); | |
444 | ret = i915_vma_unbind(vma); | |
445 | if (ret) | |
446 | break; | |
447 | } | |
448 | list_splice(&still_in_list, &obj->vma_list); | |
449 | ||
450 | return ret; | |
451 | } | |
452 | ||
e95433c7 CW |
453 | static long |
454 | i915_gem_object_wait_fence(struct dma_fence *fence, | |
455 | unsigned int flags, | |
456 | long timeout, | |
562d9bae | 457 | struct intel_rps_client *rps_client) |
00e60f26 | 458 | { |
e61e0f51 | 459 | struct i915_request *rq; |
00e60f26 | 460 | |
e95433c7 | 461 | BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1); |
00e60f26 | 462 | |
e95433c7 CW |
463 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
464 | return timeout; | |
465 | ||
466 | if (!dma_fence_is_i915(fence)) | |
467 | return dma_fence_wait_timeout(fence, | |
468 | flags & I915_WAIT_INTERRUPTIBLE, | |
469 | timeout); | |
470 | ||
471 | rq = to_request(fence); | |
e61e0f51 | 472 | if (i915_request_completed(rq)) |
e95433c7 CW |
473 | goto out; |
474 | ||
e9af4ea2 CW |
475 | /* |
476 | * This client is about to stall waiting for the GPU. In many cases | |
e95433c7 CW |
477 | * this is undesirable and limits the throughput of the system, as |
478 | * many clients cannot continue processing user input/output whilst | |
479 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
480 | * to the GPU load and thus incurs additional latency for the client. | |
481 | * We can circumvent that by promoting the GPU frequency to maximum | |
482 | * before we wait. This makes the GPU throttle up much more quickly | |
483 | * (good for benchmarks and user experience, e.g. window animations), | |
484 | * but at a cost of spending more power processing the workload | |
485 | * (bad for battery). Not all clients even want their results | |
486 | * immediately and for them we should just let the GPU select its own | |
487 | * frequency to maximise efficiency. To prevent a single client from | |
488 | * forcing the clocks too high for the whole system, we only allow | |
489 | * each client to waitboost once in a busy period. | |
490 | */ | |
e61e0f51 | 491 | if (rps_client && !i915_request_started(rq)) { |
e95433c7 | 492 | if (INTEL_GEN(rq->i915) >= 6) |
562d9bae | 493 | gen6_rps_boost(rq, rps_client); |
00e60f26 CW |
494 | } |
495 | ||
e61e0f51 | 496 | timeout = i915_request_wait(rq, flags, timeout); |
e95433c7 CW |
497 | |
498 | out: | |
e61e0f51 CW |
499 | if (flags & I915_WAIT_LOCKED && i915_request_completed(rq)) |
500 | i915_request_retire_upto(rq); | |
e95433c7 | 501 | |
e95433c7 CW |
502 | return timeout; |
503 | } | |
504 | ||
505 | static long | |
506 | i915_gem_object_wait_reservation(struct reservation_object *resv, | |
507 | unsigned int flags, | |
508 | long timeout, | |
562d9bae | 509 | struct intel_rps_client *rps_client) |
e95433c7 | 510 | { |
e54ca977 | 511 | unsigned int seq = __read_seqcount_begin(&resv->seq); |
e95433c7 | 512 | struct dma_fence *excl; |
e54ca977 | 513 | bool prune_fences = false; |
e95433c7 CW |
514 | |
515 | if (flags & I915_WAIT_ALL) { | |
516 | struct dma_fence **shared; | |
517 | unsigned int count, i; | |
00e60f26 CW |
518 | int ret; |
519 | ||
e95433c7 CW |
520 | ret = reservation_object_get_fences_rcu(resv, |
521 | &excl, &count, &shared); | |
00e60f26 CW |
522 | if (ret) |
523 | return ret; | |
00e60f26 | 524 | |
e95433c7 CW |
525 | for (i = 0; i < count; i++) { |
526 | timeout = i915_gem_object_wait_fence(shared[i], | |
527 | flags, timeout, | |
562d9bae | 528 | rps_client); |
d892e939 | 529 | if (timeout < 0) |
e95433c7 | 530 | break; |
00e60f26 | 531 | |
e95433c7 CW |
532 | dma_fence_put(shared[i]); |
533 | } | |
534 | ||
535 | for (; i < count; i++) | |
536 | dma_fence_put(shared[i]); | |
537 | kfree(shared); | |
e54ca977 | 538 | |
fa73055b CW |
539 | /* |
540 | * If both shared fences and an exclusive fence exist, | |
541 | * then by construction the shared fences must be later | |
542 | * than the exclusive fence. If we successfully wait for | |
543 | * all the shared fences, we know that the exclusive fence | |
544 | * must all be signaled. If all the shared fences are | |
545 | * signaled, we can prune the array and recover the | |
546 | * floating references on the fences/requests. | |
547 | */ | |
e54ca977 | 548 | prune_fences = count && timeout >= 0; |
e95433c7 CW |
549 | } else { |
550 | excl = reservation_object_get_excl_rcu(resv); | |
00e60f26 CW |
551 | } |
552 | ||
fa73055b | 553 | if (excl && timeout >= 0) |
562d9bae SAK |
554 | timeout = i915_gem_object_wait_fence(excl, flags, timeout, |
555 | rps_client); | |
e95433c7 CW |
556 | |
557 | dma_fence_put(excl); | |
558 | ||
fa73055b CW |
559 | /* |
560 | * Opportunistically prune the fences iff we know they have *all* been | |
03d1cac6 CW |
561 | * signaled and that the reservation object has not been changed (i.e. |
562 | * no new fences have been added). | |
563 | */ | |
e54ca977 | 564 | if (prune_fences && !__read_seqcount_retry(&resv->seq, seq)) { |
03d1cac6 CW |
565 | if (reservation_object_trylock(resv)) { |
566 | if (!__read_seqcount_retry(&resv->seq, seq)) | |
567 | reservation_object_add_excl_fence(resv, NULL); | |
568 | reservation_object_unlock(resv); | |
569 | } | |
e54ca977 CW |
570 | } |
571 | ||
e95433c7 | 572 | return timeout; |
00e60f26 CW |
573 | } |
574 | ||
b7268c5e CW |
575 | static void __fence_set_priority(struct dma_fence *fence, |
576 | const struct i915_sched_attr *attr) | |
6b5e90f5 | 577 | { |
e61e0f51 | 578 | struct i915_request *rq; |
6b5e90f5 CW |
579 | struct intel_engine_cs *engine; |
580 | ||
c218ee03 | 581 | if (dma_fence_is_signaled(fence) || !dma_fence_is_i915(fence)) |
6b5e90f5 CW |
582 | return; |
583 | ||
584 | rq = to_request(fence); | |
585 | engine = rq->engine; | |
6b5e90f5 | 586 | |
4f6d8fcf CW |
587 | local_bh_disable(); |
588 | rcu_read_lock(); /* RCU serialisation for set-wedged protection */ | |
47650db0 | 589 | if (engine->schedule) |
b7268c5e | 590 | engine->schedule(rq, attr); |
47650db0 | 591 | rcu_read_unlock(); |
4f6d8fcf | 592 | local_bh_enable(); /* kick the tasklets if queues were reprioritised */ |
6b5e90f5 CW |
593 | } |
594 | ||
b7268c5e CW |
595 | static void fence_set_priority(struct dma_fence *fence, |
596 | const struct i915_sched_attr *attr) | |
6b5e90f5 CW |
597 | { |
598 | /* Recurse once into a fence-array */ | |
599 | if (dma_fence_is_array(fence)) { | |
600 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
601 | int i; | |
602 | ||
603 | for (i = 0; i < array->num_fences; i++) | |
b7268c5e | 604 | __fence_set_priority(array->fences[i], attr); |
6b5e90f5 | 605 | } else { |
b7268c5e | 606 | __fence_set_priority(fence, attr); |
6b5e90f5 CW |
607 | } |
608 | } | |
609 | ||
610 | int | |
611 | i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, | |
612 | unsigned int flags, | |
b7268c5e | 613 | const struct i915_sched_attr *attr) |
6b5e90f5 CW |
614 | { |
615 | struct dma_fence *excl; | |
616 | ||
617 | if (flags & I915_WAIT_ALL) { | |
618 | struct dma_fence **shared; | |
619 | unsigned int count, i; | |
620 | int ret; | |
621 | ||
622 | ret = reservation_object_get_fences_rcu(obj->resv, | |
623 | &excl, &count, &shared); | |
624 | if (ret) | |
625 | return ret; | |
626 | ||
627 | for (i = 0; i < count; i++) { | |
b7268c5e | 628 | fence_set_priority(shared[i], attr); |
6b5e90f5 CW |
629 | dma_fence_put(shared[i]); |
630 | } | |
631 | ||
632 | kfree(shared); | |
633 | } else { | |
634 | excl = reservation_object_get_excl_rcu(obj->resv); | |
635 | } | |
636 | ||
637 | if (excl) { | |
b7268c5e | 638 | fence_set_priority(excl, attr); |
6b5e90f5 CW |
639 | dma_fence_put(excl); |
640 | } | |
641 | return 0; | |
642 | } | |
643 | ||
e95433c7 CW |
644 | /** |
645 | * Waits for rendering to the object to be completed | |
646 | * @obj: i915 gem object | |
647 | * @flags: how to wait (under a lock, for all rendering or just for writes etc) | |
648 | * @timeout: how long to wait | |
a0a8b1cf | 649 | * @rps_client: client (user process) to charge for any waitboosting |
00e60f26 | 650 | */ |
e95433c7 CW |
651 | int |
652 | i915_gem_object_wait(struct drm_i915_gem_object *obj, | |
653 | unsigned int flags, | |
654 | long timeout, | |
562d9bae | 655 | struct intel_rps_client *rps_client) |
00e60f26 | 656 | { |
e95433c7 CW |
657 | might_sleep(); |
658 | #if IS_ENABLED(CONFIG_LOCKDEP) | |
659 | GEM_BUG_ON(debug_locks && | |
660 | !!lockdep_is_held(&obj->base.dev->struct_mutex) != | |
661 | !!(flags & I915_WAIT_LOCKED)); | |
662 | #endif | |
663 | GEM_BUG_ON(timeout < 0); | |
00e60f26 | 664 | |
d07f0e59 CW |
665 | timeout = i915_gem_object_wait_reservation(obj->resv, |
666 | flags, timeout, | |
562d9bae | 667 | rps_client); |
e95433c7 | 668 | return timeout < 0 ? timeout : 0; |
00e60f26 CW |
669 | } |
670 | ||
671 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
672 | { | |
673 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
674 | ||
562d9bae | 675 | return &fpriv->rps_client; |
00e60f26 CW |
676 | } |
677 | ||
00731155 CW |
678 | static int |
679 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
680 | struct drm_i915_gem_pwrite *args, | |
03ac84f1 | 681 | struct drm_file *file) |
00731155 | 682 | { |
00731155 | 683 | void *vaddr = obj->phys_handle->vaddr + args->offset; |
3ed605bc | 684 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
6a2c4232 CW |
685 | |
686 | /* We manually control the domain here and pretend that it | |
687 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
688 | */ | |
77a0d1ca | 689 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
10466d2a CW |
690 | if (copy_from_user(vaddr, user_data, args->size)) |
691 | return -EFAULT; | |
00731155 | 692 | |
6a2c4232 | 693 | drm_clflush_virt_range(vaddr, args->size); |
10466d2a | 694 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
063e4e6b | 695 | |
d59b21ec | 696 | intel_fb_obj_flush(obj, ORIGIN_CPU); |
10466d2a | 697 | return 0; |
00731155 CW |
698 | } |
699 | ||
187685cb | 700 | void *i915_gem_object_alloc(struct drm_i915_private *dev_priv) |
42dcedd4 | 701 | { |
efab6d8d | 702 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
703 | } |
704 | ||
705 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
706 | { | |
fac5e23e | 707 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 708 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
709 | } |
710 | ||
ff72145b DA |
711 | static int |
712 | i915_gem_create(struct drm_file *file, | |
12d79d78 | 713 | struct drm_i915_private *dev_priv, |
ff72145b DA |
714 | uint64_t size, |
715 | uint32_t *handle_p) | |
673a394b | 716 | { |
05394f39 | 717 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
718 | int ret; |
719 | u32 handle; | |
673a394b | 720 | |
ff72145b | 721 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
722 | if (size == 0) |
723 | return -EINVAL; | |
673a394b EA |
724 | |
725 | /* Allocate the new object */ | |
12d79d78 | 726 | obj = i915_gem_object_create(dev_priv, size); |
fe3db79b CW |
727 | if (IS_ERR(obj)) |
728 | return PTR_ERR(obj); | |
673a394b | 729 | |
05394f39 | 730 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 731 | /* drop reference from allocate - handle holds it now */ |
f0cd5182 | 732 | i915_gem_object_put(obj); |
d861e338 DV |
733 | if (ret) |
734 | return ret; | |
202f2fef | 735 | |
ff72145b | 736 | *handle_p = handle; |
673a394b EA |
737 | return 0; |
738 | } | |
739 | ||
ff72145b DA |
740 | int |
741 | i915_gem_dumb_create(struct drm_file *file, | |
742 | struct drm_device *dev, | |
743 | struct drm_mode_create_dumb *args) | |
744 | { | |
745 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 746 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b | 747 | args->size = args->pitch * args->height; |
12d79d78 | 748 | return i915_gem_create(file, to_i915(dev), |
da6b51d0 | 749 | args->size, &args->handle); |
ff72145b DA |
750 | } |
751 | ||
e27ab73d CW |
752 | static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
753 | { | |
754 | return !(obj->cache_level == I915_CACHE_NONE || | |
755 | obj->cache_level == I915_CACHE_WT); | |
756 | } | |
757 | ||
ff72145b DA |
758 | /** |
759 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
760 | * @dev: drm device pointer |
761 | * @data: ioctl data blob | |
762 | * @file: drm file pointer | |
ff72145b DA |
763 | */ |
764 | int | |
765 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
766 | struct drm_file *file) | |
767 | { | |
12d79d78 | 768 | struct drm_i915_private *dev_priv = to_i915(dev); |
ff72145b | 769 | struct drm_i915_gem_create *args = data; |
63ed2cb2 | 770 | |
12d79d78 | 771 | i915_gem_flush_free_objects(dev_priv); |
fbbd37b3 | 772 | |
12d79d78 | 773 | return i915_gem_create(file, dev_priv, |
da6b51d0 | 774 | args->size, &args->handle); |
ff72145b DA |
775 | } |
776 | ||
ef74921b CW |
777 | static inline enum fb_op_origin |
778 | fb_write_origin(struct drm_i915_gem_object *obj, unsigned int domain) | |
779 | { | |
780 | return (domain == I915_GEM_DOMAIN_GTT ? | |
781 | obj->frontbuffer_ggtt_origin : ORIGIN_CPU); | |
782 | } | |
783 | ||
7125397b | 784 | void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv) |
ef74921b | 785 | { |
7125397b CW |
786 | /* |
787 | * No actual flushing is required for the GTT write domain for reads | |
788 | * from the GTT domain. Writes to it "immediately" go to main memory | |
789 | * as far as we know, so there's no chipset flush. It also doesn't | |
790 | * land in the GPU render cache. | |
ef74921b CW |
791 | * |
792 | * However, we do have to enforce the order so that all writes through | |
793 | * the GTT land before any writes to the device, such as updates to | |
794 | * the GATT itself. | |
795 | * | |
796 | * We also have to wait a bit for the writes to land from the GTT. | |
797 | * An uncached read (i.e. mmio) seems to be ideal for the round-trip | |
798 | * timing. This issue has only been observed when switching quickly | |
799 | * between GTT writes and CPU reads from inside the kernel on recent hw, | |
800 | * and it appears to only affect discrete GTT blocks (i.e. on LLC | |
7125397b CW |
801 | * system agents we cannot reproduce this behaviour, until Cannonlake |
802 | * that was!). | |
ef74921b | 803 | */ |
7125397b | 804 | |
900ccf30 CW |
805 | wmb(); |
806 | ||
807 | if (INTEL_INFO(dev_priv)->has_coherent_ggtt) | |
808 | return; | |
809 | ||
a8bd3b88 | 810 | i915_gem_chipset_flush(dev_priv); |
ef74921b | 811 | |
7125397b CW |
812 | intel_runtime_pm_get(dev_priv); |
813 | spin_lock_irq(&dev_priv->uncore.lock); | |
814 | ||
815 | POSTING_READ_FW(RING_HEAD(RENDER_RING_BASE)); | |
816 | ||
817 | spin_unlock_irq(&dev_priv->uncore.lock); | |
818 | intel_runtime_pm_put(dev_priv); | |
819 | } | |
820 | ||
821 | static void | |
822 | flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) | |
823 | { | |
824 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); | |
825 | struct i915_vma *vma; | |
826 | ||
c0a51fd0 | 827 | if (!(obj->write_domain & flush_domains)) |
7125397b CW |
828 | return; |
829 | ||
c0a51fd0 | 830 | switch (obj->write_domain) { |
ef74921b | 831 | case I915_GEM_DOMAIN_GTT: |
7125397b | 832 | i915_gem_flush_ggtt_writes(dev_priv); |
ef74921b CW |
833 | |
834 | intel_fb_obj_flush(obj, | |
835 | fb_write_origin(obj, I915_GEM_DOMAIN_GTT)); | |
7125397b | 836 | |
e2189dd0 | 837 | for_each_ggtt_vma(vma, obj) { |
7125397b CW |
838 | if (vma->iomap) |
839 | continue; | |
840 | ||
841 | i915_vma_unset_ggtt_write(vma); | |
842 | } | |
ef74921b CW |
843 | break; |
844 | ||
add00e6d CW |
845 | case I915_GEM_DOMAIN_WC: |
846 | wmb(); | |
847 | break; | |
848 | ||
ef74921b CW |
849 | case I915_GEM_DOMAIN_CPU: |
850 | i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC); | |
851 | break; | |
e27ab73d CW |
852 | |
853 | case I915_GEM_DOMAIN_RENDER: | |
854 | if (gpu_write_needs_clflush(obj)) | |
855 | obj->cache_dirty = true; | |
856 | break; | |
ef74921b CW |
857 | } |
858 | ||
c0a51fd0 | 859 | obj->write_domain = 0; |
ef74921b CW |
860 | } |
861 | ||
8461d226 DV |
862 | static inline int |
863 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
864 | const char *gpu_vaddr, int gpu_offset, | |
865 | int length) | |
866 | { | |
867 | int ret, cpu_offset = 0; | |
868 | ||
869 | while (length > 0) { | |
870 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
871 | int this_length = min(cacheline_end - gpu_offset, length); | |
872 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
873 | ||
874 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
875 | gpu_vaddr + swizzled_gpu_offset, | |
876 | this_length); | |
877 | if (ret) | |
878 | return ret + length; | |
879 | ||
880 | cpu_offset += this_length; | |
881 | gpu_offset += this_length; | |
882 | length -= this_length; | |
883 | } | |
884 | ||
885 | return 0; | |
886 | } | |
887 | ||
8c59967c | 888 | static inline int |
4f0c7cfb BW |
889 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
890 | const char __user *cpu_vaddr, | |
8c59967c DV |
891 | int length) |
892 | { | |
893 | int ret, cpu_offset = 0; | |
894 | ||
895 | while (length > 0) { | |
896 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
897 | int this_length = min(cacheline_end - gpu_offset, length); | |
898 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
899 | ||
900 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
901 | cpu_vaddr + cpu_offset, | |
902 | this_length); | |
903 | if (ret) | |
904 | return ret + length; | |
905 | ||
906 | cpu_offset += this_length; | |
907 | gpu_offset += this_length; | |
908 | length -= this_length; | |
909 | } | |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
4c914c0c BV |
914 | /* |
915 | * Pins the specified object's pages and synchronizes the object with | |
916 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
917 | * flush the object from the CPU cache. | |
918 | */ | |
919 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
43394c7d | 920 | unsigned int *needs_clflush) |
4c914c0c BV |
921 | { |
922 | int ret; | |
923 | ||
e95433c7 | 924 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c914c0c | 925 | |
e95433c7 | 926 | *needs_clflush = 0; |
43394c7d CW |
927 | if (!i915_gem_object_has_struct_page(obj)) |
928 | return -ENODEV; | |
4c914c0c | 929 | |
e95433c7 CW |
930 | ret = i915_gem_object_wait(obj, |
931 | I915_WAIT_INTERRUPTIBLE | | |
932 | I915_WAIT_LOCKED, | |
933 | MAX_SCHEDULE_TIMEOUT, | |
934 | NULL); | |
c13d87ea CW |
935 | if (ret) |
936 | return ret; | |
937 | ||
a4f5ea64 | 938 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
939 | if (ret) |
940 | return ret; | |
941 | ||
b8f55be6 CW |
942 | if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ || |
943 | !static_cpu_has(X86_FEATURE_CLFLUSH)) { | |
7f5f95d8 CW |
944 | ret = i915_gem_object_set_to_cpu_domain(obj, false); |
945 | if (ret) | |
946 | goto err_unpin; | |
947 | else | |
948 | goto out; | |
949 | } | |
950 | ||
ef74921b | 951 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); |
a314d5cb | 952 | |
43394c7d CW |
953 | /* If we're not in the cpu read domain, set ourself into the gtt |
954 | * read domain and manually flush cachelines (if required). This | |
955 | * optimizes for the case when the gpu will dirty the data | |
956 | * anyway again before the next pread happens. | |
957 | */ | |
e27ab73d | 958 | if (!obj->cache_dirty && |
c0a51fd0 | 959 | !(obj->read_domains & I915_GEM_DOMAIN_CPU)) |
7f5f95d8 | 960 | *needs_clflush = CLFLUSH_BEFORE; |
4c914c0c | 961 | |
7f5f95d8 | 962 | out: |
9764951e | 963 | /* return with the pages pinned */ |
43394c7d | 964 | return 0; |
9764951e CW |
965 | |
966 | err_unpin: | |
967 | i915_gem_object_unpin_pages(obj); | |
968 | return ret; | |
43394c7d CW |
969 | } |
970 | ||
971 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
972 | unsigned int *needs_clflush) | |
973 | { | |
974 | int ret; | |
975 | ||
e95433c7 CW |
976 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
977 | ||
43394c7d CW |
978 | *needs_clflush = 0; |
979 | if (!i915_gem_object_has_struct_page(obj)) | |
980 | return -ENODEV; | |
981 | ||
e95433c7 CW |
982 | ret = i915_gem_object_wait(obj, |
983 | I915_WAIT_INTERRUPTIBLE | | |
984 | I915_WAIT_LOCKED | | |
985 | I915_WAIT_ALL, | |
986 | MAX_SCHEDULE_TIMEOUT, | |
987 | NULL); | |
43394c7d CW |
988 | if (ret) |
989 | return ret; | |
990 | ||
a4f5ea64 | 991 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
992 | if (ret) |
993 | return ret; | |
994 | ||
b8f55be6 CW |
995 | if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE || |
996 | !static_cpu_has(X86_FEATURE_CLFLUSH)) { | |
7f5f95d8 CW |
997 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
998 | if (ret) | |
999 | goto err_unpin; | |
1000 | else | |
1001 | goto out; | |
1002 | } | |
1003 | ||
ef74921b | 1004 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); |
a314d5cb | 1005 | |
43394c7d CW |
1006 | /* If we're not in the cpu write domain, set ourself into the |
1007 | * gtt write domain and manually flush cachelines (as required). | |
1008 | * This optimizes for the case when the gpu will use the data | |
1009 | * right away and we therefore have to clflush anyway. | |
1010 | */ | |
e27ab73d | 1011 | if (!obj->cache_dirty) { |
7f5f95d8 | 1012 | *needs_clflush |= CLFLUSH_AFTER; |
43394c7d | 1013 | |
e27ab73d CW |
1014 | /* |
1015 | * Same trick applies to invalidate partially written | |
1016 | * cachelines read before writing. | |
1017 | */ | |
c0a51fd0 | 1018 | if (!(obj->read_domains & I915_GEM_DOMAIN_CPU)) |
e27ab73d CW |
1019 | *needs_clflush |= CLFLUSH_BEFORE; |
1020 | } | |
43394c7d | 1021 | |
7f5f95d8 | 1022 | out: |
43394c7d | 1023 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
a4f5ea64 | 1024 | obj->mm.dirty = true; |
9764951e | 1025 | /* return with the pages pinned */ |
43394c7d | 1026 | return 0; |
9764951e CW |
1027 | |
1028 | err_unpin: | |
1029 | i915_gem_object_unpin_pages(obj); | |
1030 | return ret; | |
4c914c0c BV |
1031 | } |
1032 | ||
23c18c71 DV |
1033 | static void |
1034 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
1035 | bool swizzled) | |
1036 | { | |
e7e58eb5 | 1037 | if (unlikely(swizzled)) { |
23c18c71 DV |
1038 | unsigned long start = (unsigned long) addr; |
1039 | unsigned long end = (unsigned long) addr + length; | |
1040 | ||
1041 | /* For swizzling simply ensure that we always flush both | |
1042 | * channels. Lame, but simple and it works. Swizzled | |
1043 | * pwrite/pread is far from a hotpath - current userspace | |
1044 | * doesn't use it at all. */ | |
1045 | start = round_down(start, 128); | |
1046 | end = round_up(end, 128); | |
1047 | ||
1048 | drm_clflush_virt_range((void *)start, end - start); | |
1049 | } else { | |
1050 | drm_clflush_virt_range(addr, length); | |
1051 | } | |
1052 | ||
1053 | } | |
1054 | ||
d174bd64 DV |
1055 | /* Only difference to the fast-path function is that this can handle bit17 |
1056 | * and uses non-atomic copy and kmap functions. */ | |
1057 | static int | |
bb6dc8d9 | 1058 | shmem_pread_slow(struct page *page, int offset, int length, |
d174bd64 DV |
1059 | char __user *user_data, |
1060 | bool page_do_bit17_swizzling, bool needs_clflush) | |
1061 | { | |
1062 | char *vaddr; | |
1063 | int ret; | |
1064 | ||
1065 | vaddr = kmap(page); | |
1066 | if (needs_clflush) | |
bb6dc8d9 | 1067 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1068 | page_do_bit17_swizzling); |
d174bd64 DV |
1069 | |
1070 | if (page_do_bit17_swizzling) | |
bb6dc8d9 | 1071 | ret = __copy_to_user_swizzled(user_data, vaddr, offset, length); |
d174bd64 | 1072 | else |
bb6dc8d9 | 1073 | ret = __copy_to_user(user_data, vaddr + offset, length); |
d174bd64 DV |
1074 | kunmap(page); |
1075 | ||
f60d7f0c | 1076 | return ret ? - EFAULT : 0; |
d174bd64 DV |
1077 | } |
1078 | ||
bb6dc8d9 CW |
1079 | static int |
1080 | shmem_pread(struct page *page, int offset, int length, char __user *user_data, | |
1081 | bool page_do_bit17_swizzling, bool needs_clflush) | |
1082 | { | |
1083 | int ret; | |
1084 | ||
1085 | ret = -ENODEV; | |
1086 | if (!page_do_bit17_swizzling) { | |
1087 | char *vaddr = kmap_atomic(page); | |
1088 | ||
1089 | if (needs_clflush) | |
1090 | drm_clflush_virt_range(vaddr + offset, length); | |
1091 | ret = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
1092 | kunmap_atomic(vaddr); | |
1093 | } | |
1094 | if (ret == 0) | |
1095 | return 0; | |
1096 | ||
1097 | return shmem_pread_slow(page, offset, length, user_data, | |
1098 | page_do_bit17_swizzling, needs_clflush); | |
1099 | } | |
1100 | ||
1101 | static int | |
1102 | i915_gem_shmem_pread(struct drm_i915_gem_object *obj, | |
1103 | struct drm_i915_gem_pread *args) | |
1104 | { | |
1105 | char __user *user_data; | |
1106 | u64 remain; | |
1107 | unsigned int obj_do_bit17_swizzling; | |
1108 | unsigned int needs_clflush; | |
1109 | unsigned int idx, offset; | |
1110 | int ret; | |
1111 | ||
1112 | obj_do_bit17_swizzling = 0; | |
1113 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
1114 | obj_do_bit17_swizzling = BIT(17); | |
1115 | ||
1116 | ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex); | |
1117 | if (ret) | |
1118 | return ret; | |
1119 | ||
1120 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); | |
1121 | mutex_unlock(&obj->base.dev->struct_mutex); | |
1122 | if (ret) | |
1123 | return ret; | |
1124 | ||
1125 | remain = args->size; | |
1126 | user_data = u64_to_user_ptr(args->data_ptr); | |
1127 | offset = offset_in_page(args->offset); | |
1128 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
1129 | struct page *page = i915_gem_object_get_page(obj, idx); | |
1130 | int length; | |
1131 | ||
1132 | length = remain; | |
1133 | if (offset + length > PAGE_SIZE) | |
1134 | length = PAGE_SIZE - offset; | |
1135 | ||
1136 | ret = shmem_pread(page, offset, length, user_data, | |
1137 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1138 | needs_clflush); | |
1139 | if (ret) | |
1140 | break; | |
1141 | ||
1142 | remain -= length; | |
1143 | user_data += length; | |
1144 | offset = 0; | |
1145 | } | |
1146 | ||
1147 | i915_gem_obj_finish_shmem_access(obj); | |
1148 | return ret; | |
1149 | } | |
1150 | ||
1151 | static inline bool | |
1152 | gtt_user_read(struct io_mapping *mapping, | |
1153 | loff_t base, int offset, | |
1154 | char __user *user_data, int length) | |
b50a5371 | 1155 | { |
afe722be | 1156 | void __iomem *vaddr; |
bb6dc8d9 | 1157 | unsigned long unwritten; |
b50a5371 | 1158 | |
b50a5371 | 1159 | /* We can use the cpu mem copy function because this is X86. */ |
afe722be VS |
1160 | vaddr = io_mapping_map_atomic_wc(mapping, base); |
1161 | unwritten = __copy_to_user_inatomic(user_data, | |
1162 | (void __force *)vaddr + offset, | |
1163 | length); | |
bb6dc8d9 CW |
1164 | io_mapping_unmap_atomic(vaddr); |
1165 | if (unwritten) { | |
afe722be VS |
1166 | vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE); |
1167 | unwritten = copy_to_user(user_data, | |
1168 | (void __force *)vaddr + offset, | |
1169 | length); | |
bb6dc8d9 CW |
1170 | io_mapping_unmap(vaddr); |
1171 | } | |
b50a5371 AS |
1172 | return unwritten; |
1173 | } | |
1174 | ||
1175 | static int | |
bb6dc8d9 CW |
1176 | i915_gem_gtt_pread(struct drm_i915_gem_object *obj, |
1177 | const struct drm_i915_gem_pread *args) | |
b50a5371 | 1178 | { |
bb6dc8d9 CW |
1179 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
1180 | struct i915_ggtt *ggtt = &i915->ggtt; | |
b50a5371 | 1181 | struct drm_mm_node node; |
bb6dc8d9 CW |
1182 | struct i915_vma *vma; |
1183 | void __user *user_data; | |
1184 | u64 remain, offset; | |
b50a5371 AS |
1185 | int ret; |
1186 | ||
bb6dc8d9 CW |
1187 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1188 | if (ret) | |
1189 | return ret; | |
1190 | ||
1191 | intel_runtime_pm_get(i915); | |
1192 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, | |
a3259ca9 CW |
1193 | PIN_MAPPABLE | |
1194 | PIN_NONFAULT | | |
1195 | PIN_NONBLOCK); | |
18034584 CW |
1196 | if (!IS_ERR(vma)) { |
1197 | node.start = i915_ggtt_offset(vma); | |
1198 | node.allocated = false; | |
49ef5294 | 1199 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1200 | if (ret) { |
1201 | i915_vma_unpin(vma); | |
1202 | vma = ERR_PTR(ret); | |
1203 | } | |
1204 | } | |
058d88c4 | 1205 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1206 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
b50a5371 | 1207 | if (ret) |
bb6dc8d9 CW |
1208 | goto out_unlock; |
1209 | GEM_BUG_ON(!node.allocated); | |
b50a5371 AS |
1210 | } |
1211 | ||
1212 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1213 | if (ret) | |
1214 | goto out_unpin; | |
1215 | ||
bb6dc8d9 | 1216 | mutex_unlock(&i915->drm.struct_mutex); |
b50a5371 | 1217 | |
bb6dc8d9 CW |
1218 | user_data = u64_to_user_ptr(args->data_ptr); |
1219 | remain = args->size; | |
1220 | offset = args->offset; | |
b50a5371 AS |
1221 | |
1222 | while (remain > 0) { | |
1223 | /* Operation in this page | |
1224 | * | |
1225 | * page_base = page offset within aperture | |
1226 | * page_offset = offset within page | |
1227 | * page_length = bytes to copy for this page | |
1228 | */ | |
1229 | u32 page_base = node.start; | |
1230 | unsigned page_offset = offset_in_page(offset); | |
1231 | unsigned page_length = PAGE_SIZE - page_offset; | |
1232 | page_length = remain < page_length ? remain : page_length; | |
1233 | if (node.allocated) { | |
1234 | wmb(); | |
82ad6443 CW |
1235 | ggtt->vm.insert_page(&ggtt->vm, |
1236 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1237 | node.start, I915_CACHE_NONE, 0); | |
b50a5371 AS |
1238 | wmb(); |
1239 | } else { | |
1240 | page_base += offset & PAGE_MASK; | |
1241 | } | |
bb6dc8d9 | 1242 | |
73ebd503 | 1243 | if (gtt_user_read(&ggtt->iomap, page_base, page_offset, |
bb6dc8d9 | 1244 | user_data, page_length)) { |
b50a5371 AS |
1245 | ret = -EFAULT; |
1246 | break; | |
1247 | } | |
1248 | ||
1249 | remain -= page_length; | |
1250 | user_data += page_length; | |
1251 | offset += page_length; | |
1252 | } | |
1253 | ||
bb6dc8d9 | 1254 | mutex_lock(&i915->drm.struct_mutex); |
b50a5371 AS |
1255 | out_unpin: |
1256 | if (node.allocated) { | |
1257 | wmb(); | |
82ad6443 | 1258 | ggtt->vm.clear_range(&ggtt->vm, node.start, node.size); |
b50a5371 AS |
1259 | remove_mappable_node(&node); |
1260 | } else { | |
058d88c4 | 1261 | i915_vma_unpin(vma); |
b50a5371 | 1262 | } |
bb6dc8d9 CW |
1263 | out_unlock: |
1264 | intel_runtime_pm_put(i915); | |
1265 | mutex_unlock(&i915->drm.struct_mutex); | |
f60d7f0c | 1266 | |
eb01459f EA |
1267 | return ret; |
1268 | } | |
1269 | ||
673a394b EA |
1270 | /** |
1271 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
1272 | * @dev: drm device pointer |
1273 | * @data: ioctl data blob | |
1274 | * @file: drm file pointer | |
673a394b EA |
1275 | * |
1276 | * On error, the contents of *data are undefined. | |
1277 | */ | |
1278 | int | |
1279 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1280 | struct drm_file *file) |
673a394b EA |
1281 | { |
1282 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 1283 | struct drm_i915_gem_object *obj; |
bb6dc8d9 | 1284 | int ret; |
673a394b | 1285 | |
51311d0a CW |
1286 | if (args->size == 0) |
1287 | return 0; | |
1288 | ||
1289 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 1290 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1291 | args->size)) |
1292 | return -EFAULT; | |
1293 | ||
03ac0642 | 1294 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1295 | if (!obj) |
1296 | return -ENOENT; | |
673a394b | 1297 | |
7dcd2499 | 1298 | /* Bounds check source. */ |
966d5bf5 | 1299 | if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { |
ce9d419d | 1300 | ret = -EINVAL; |
bb6dc8d9 | 1301 | goto out; |
ce9d419d CW |
1302 | } |
1303 | ||
db53a302 CW |
1304 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
1305 | ||
e95433c7 CW |
1306 | ret = i915_gem_object_wait(obj, |
1307 | I915_WAIT_INTERRUPTIBLE, | |
1308 | MAX_SCHEDULE_TIMEOUT, | |
1309 | to_rps_client(file)); | |
258a5ede | 1310 | if (ret) |
bb6dc8d9 | 1311 | goto out; |
258a5ede | 1312 | |
bb6dc8d9 | 1313 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1314 | if (ret) |
bb6dc8d9 | 1315 | goto out; |
673a394b | 1316 | |
bb6dc8d9 | 1317 | ret = i915_gem_shmem_pread(obj, args); |
9c870d03 | 1318 | if (ret == -EFAULT || ret == -ENODEV) |
bb6dc8d9 | 1319 | ret = i915_gem_gtt_pread(obj, args); |
b50a5371 | 1320 | |
bb6dc8d9 CW |
1321 | i915_gem_object_unpin_pages(obj); |
1322 | out: | |
f0cd5182 | 1323 | i915_gem_object_put(obj); |
eb01459f | 1324 | return ret; |
673a394b EA |
1325 | } |
1326 | ||
0839ccb8 KP |
1327 | /* This is the fast write path which cannot handle |
1328 | * page faults in the source data | |
9b7530cc | 1329 | */ |
0839ccb8 | 1330 | |
fe115628 CW |
1331 | static inline bool |
1332 | ggtt_write(struct io_mapping *mapping, | |
1333 | loff_t base, int offset, | |
1334 | char __user *user_data, int length) | |
9b7530cc | 1335 | { |
afe722be | 1336 | void __iomem *vaddr; |
0839ccb8 | 1337 | unsigned long unwritten; |
9b7530cc | 1338 | |
4f0c7cfb | 1339 | /* We can use the cpu mem copy function because this is X86. */ |
afe722be VS |
1340 | vaddr = io_mapping_map_atomic_wc(mapping, base); |
1341 | unwritten = __copy_from_user_inatomic_nocache((void __force *)vaddr + offset, | |
0839ccb8 | 1342 | user_data, length); |
fe115628 CW |
1343 | io_mapping_unmap_atomic(vaddr); |
1344 | if (unwritten) { | |
afe722be VS |
1345 | vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE); |
1346 | unwritten = copy_from_user((void __force *)vaddr + offset, | |
1347 | user_data, length); | |
fe115628 CW |
1348 | io_mapping_unmap(vaddr); |
1349 | } | |
bb6dc8d9 | 1350 | |
bb6dc8d9 CW |
1351 | return unwritten; |
1352 | } | |
1353 | ||
3de09aa3 EA |
1354 | /** |
1355 | * This is the fast pwrite path, where we copy the data directly from the | |
1356 | * user into the GTT, uncached. | |
fe115628 | 1357 | * @obj: i915 GEM object |
14bb2c11 | 1358 | * @args: pwrite arguments structure |
3de09aa3 | 1359 | */ |
673a394b | 1360 | static int |
fe115628 CW |
1361 | i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, |
1362 | const struct drm_i915_gem_pwrite *args) | |
673a394b | 1363 | { |
fe115628 | 1364 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
4f1959ee AS |
1365 | struct i915_ggtt *ggtt = &i915->ggtt; |
1366 | struct drm_mm_node node; | |
fe115628 CW |
1367 | struct i915_vma *vma; |
1368 | u64 remain, offset; | |
1369 | void __user *user_data; | |
4f1959ee | 1370 | int ret; |
b50a5371 | 1371 | |
fe115628 CW |
1372 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1373 | if (ret) | |
1374 | return ret; | |
935aaa69 | 1375 | |
8bd81815 CW |
1376 | if (i915_gem_object_has_struct_page(obj)) { |
1377 | /* | |
1378 | * Avoid waking the device up if we can fallback, as | |
1379 | * waking/resuming is very slow (worst-case 10-100 ms | |
1380 | * depending on PCI sleeps and our own resume time). | |
1381 | * This easily dwarfs any performance advantage from | |
1382 | * using the cache bypass of indirect GGTT access. | |
1383 | */ | |
1384 | if (!intel_runtime_pm_get_if_in_use(i915)) { | |
1385 | ret = -EFAULT; | |
1386 | goto out_unlock; | |
1387 | } | |
1388 | } else { | |
1389 | /* No backing pages, no fallback, we must force GGTT access */ | |
1390 | intel_runtime_pm_get(i915); | |
1391 | } | |
1392 | ||
058d88c4 | 1393 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
a3259ca9 CW |
1394 | PIN_MAPPABLE | |
1395 | PIN_NONFAULT | | |
1396 | PIN_NONBLOCK); | |
18034584 CW |
1397 | if (!IS_ERR(vma)) { |
1398 | node.start = i915_ggtt_offset(vma); | |
1399 | node.allocated = false; | |
49ef5294 | 1400 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1401 | if (ret) { |
1402 | i915_vma_unpin(vma); | |
1403 | vma = ERR_PTR(ret); | |
1404 | } | |
1405 | } | |
058d88c4 | 1406 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1407 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
4f1959ee | 1408 | if (ret) |
8bd81815 | 1409 | goto out_rpm; |
fe115628 | 1410 | GEM_BUG_ON(!node.allocated); |
4f1959ee | 1411 | } |
935aaa69 DV |
1412 | |
1413 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1414 | if (ret) | |
1415 | goto out_unpin; | |
1416 | ||
fe115628 CW |
1417 | mutex_unlock(&i915->drm.struct_mutex); |
1418 | ||
b19482d7 | 1419 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1420 | |
4f1959ee AS |
1421 | user_data = u64_to_user_ptr(args->data_ptr); |
1422 | offset = args->offset; | |
1423 | remain = args->size; | |
1424 | while (remain) { | |
673a394b EA |
1425 | /* Operation in this page |
1426 | * | |
0839ccb8 KP |
1427 | * page_base = page offset within aperture |
1428 | * page_offset = offset within page | |
1429 | * page_length = bytes to copy for this page | |
673a394b | 1430 | */ |
4f1959ee | 1431 | u32 page_base = node.start; |
bb6dc8d9 CW |
1432 | unsigned int page_offset = offset_in_page(offset); |
1433 | unsigned int page_length = PAGE_SIZE - page_offset; | |
4f1959ee AS |
1434 | page_length = remain < page_length ? remain : page_length; |
1435 | if (node.allocated) { | |
1436 | wmb(); /* flush the write before we modify the GGTT */ | |
82ad6443 CW |
1437 | ggtt->vm.insert_page(&ggtt->vm, |
1438 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1439 | node.start, I915_CACHE_NONE, 0); | |
4f1959ee AS |
1440 | wmb(); /* flush modifications to the GGTT (insert_page) */ |
1441 | } else { | |
1442 | page_base += offset & PAGE_MASK; | |
1443 | } | |
0839ccb8 | 1444 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1445 | * source page isn't available. Return the error and we'll |
1446 | * retry in the slow path. | |
b50a5371 AS |
1447 | * If the object is non-shmem backed, we retry again with the |
1448 | * path that handles page fault. | |
0839ccb8 | 1449 | */ |
73ebd503 | 1450 | if (ggtt_write(&ggtt->iomap, page_base, page_offset, |
fe115628 CW |
1451 | user_data, page_length)) { |
1452 | ret = -EFAULT; | |
1453 | break; | |
935aaa69 | 1454 | } |
673a394b | 1455 | |
0839ccb8 KP |
1456 | remain -= page_length; |
1457 | user_data += page_length; | |
1458 | offset += page_length; | |
673a394b | 1459 | } |
d59b21ec | 1460 | intel_fb_obj_flush(obj, ORIGIN_CPU); |
fe115628 CW |
1461 | |
1462 | mutex_lock(&i915->drm.struct_mutex); | |
935aaa69 | 1463 | out_unpin: |
4f1959ee AS |
1464 | if (node.allocated) { |
1465 | wmb(); | |
82ad6443 | 1466 | ggtt->vm.clear_range(&ggtt->vm, node.start, node.size); |
4f1959ee AS |
1467 | remove_mappable_node(&node); |
1468 | } else { | |
058d88c4 | 1469 | i915_vma_unpin(vma); |
4f1959ee | 1470 | } |
8bd81815 | 1471 | out_rpm: |
9c870d03 | 1472 | intel_runtime_pm_put(i915); |
8bd81815 | 1473 | out_unlock: |
fe115628 | 1474 | mutex_unlock(&i915->drm.struct_mutex); |
3de09aa3 | 1475 | return ret; |
673a394b EA |
1476 | } |
1477 | ||
3043c60c | 1478 | static int |
fe115628 | 1479 | shmem_pwrite_slow(struct page *page, int offset, int length, |
d174bd64 DV |
1480 | char __user *user_data, |
1481 | bool page_do_bit17_swizzling, | |
1482 | bool needs_clflush_before, | |
1483 | bool needs_clflush_after) | |
673a394b | 1484 | { |
d174bd64 DV |
1485 | char *vaddr; |
1486 | int ret; | |
e5281ccd | 1487 | |
d174bd64 | 1488 | vaddr = kmap(page); |
e7e58eb5 | 1489 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
fe115628 | 1490 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1491 | page_do_bit17_swizzling); |
d174bd64 | 1492 | if (page_do_bit17_swizzling) |
fe115628 CW |
1493 | ret = __copy_from_user_swizzled(vaddr, offset, user_data, |
1494 | length); | |
d174bd64 | 1495 | else |
fe115628 | 1496 | ret = __copy_from_user(vaddr + offset, user_data, length); |
d174bd64 | 1497 | if (needs_clflush_after) |
fe115628 | 1498 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1499 | page_do_bit17_swizzling); |
d174bd64 | 1500 | kunmap(page); |
40123c1f | 1501 | |
755d2218 | 1502 | return ret ? -EFAULT : 0; |
40123c1f EA |
1503 | } |
1504 | ||
fe115628 CW |
1505 | /* Per-page copy function for the shmem pwrite fastpath. |
1506 | * Flushes invalid cachelines before writing to the target if | |
1507 | * needs_clflush_before is set and flushes out any written cachelines after | |
1508 | * writing if needs_clflush is set. | |
1509 | */ | |
40123c1f | 1510 | static int |
fe115628 CW |
1511 | shmem_pwrite(struct page *page, int offset, int len, char __user *user_data, |
1512 | bool page_do_bit17_swizzling, | |
1513 | bool needs_clflush_before, | |
1514 | bool needs_clflush_after) | |
40123c1f | 1515 | { |
fe115628 CW |
1516 | int ret; |
1517 | ||
1518 | ret = -ENODEV; | |
1519 | if (!page_do_bit17_swizzling) { | |
1520 | char *vaddr = kmap_atomic(page); | |
1521 | ||
1522 | if (needs_clflush_before) | |
1523 | drm_clflush_virt_range(vaddr + offset, len); | |
1524 | ret = __copy_from_user_inatomic(vaddr + offset, user_data, len); | |
1525 | if (needs_clflush_after) | |
1526 | drm_clflush_virt_range(vaddr + offset, len); | |
1527 | ||
1528 | kunmap_atomic(vaddr); | |
1529 | } | |
1530 | if (ret == 0) | |
1531 | return ret; | |
1532 | ||
1533 | return shmem_pwrite_slow(page, offset, len, user_data, | |
1534 | page_do_bit17_swizzling, | |
1535 | needs_clflush_before, | |
1536 | needs_clflush_after); | |
1537 | } | |
1538 | ||
1539 | static int | |
1540 | i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, | |
1541 | const struct drm_i915_gem_pwrite *args) | |
1542 | { | |
1543 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
1544 | void __user *user_data; | |
1545 | u64 remain; | |
1546 | unsigned int obj_do_bit17_swizzling; | |
1547 | unsigned int partial_cacheline_write; | |
43394c7d | 1548 | unsigned int needs_clflush; |
fe115628 CW |
1549 | unsigned int offset, idx; |
1550 | int ret; | |
40123c1f | 1551 | |
fe115628 | 1552 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
755d2218 CW |
1553 | if (ret) |
1554 | return ret; | |
1555 | ||
fe115628 CW |
1556 | ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); |
1557 | mutex_unlock(&i915->drm.struct_mutex); | |
1558 | if (ret) | |
1559 | return ret; | |
673a394b | 1560 | |
fe115628 CW |
1561 | obj_do_bit17_swizzling = 0; |
1562 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
1563 | obj_do_bit17_swizzling = BIT(17); | |
e5281ccd | 1564 | |
fe115628 CW |
1565 | /* If we don't overwrite a cacheline completely we need to be |
1566 | * careful to have up-to-date data by first clflushing. Don't | |
1567 | * overcomplicate things and flush the entire patch. | |
1568 | */ | |
1569 | partial_cacheline_write = 0; | |
1570 | if (needs_clflush & CLFLUSH_BEFORE) | |
1571 | partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1; | |
9da3da66 | 1572 | |
fe115628 CW |
1573 | user_data = u64_to_user_ptr(args->data_ptr); |
1574 | remain = args->size; | |
1575 | offset = offset_in_page(args->offset); | |
1576 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
1577 | struct page *page = i915_gem_object_get_page(obj, idx); | |
1578 | int length; | |
40123c1f | 1579 | |
fe115628 CW |
1580 | length = remain; |
1581 | if (offset + length > PAGE_SIZE) | |
1582 | length = PAGE_SIZE - offset; | |
755d2218 | 1583 | |
fe115628 CW |
1584 | ret = shmem_pwrite(page, offset, length, user_data, |
1585 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1586 | (offset | length) & partial_cacheline_write, | |
1587 | needs_clflush & CLFLUSH_AFTER); | |
755d2218 | 1588 | if (ret) |
fe115628 | 1589 | break; |
755d2218 | 1590 | |
fe115628 CW |
1591 | remain -= length; |
1592 | user_data += length; | |
1593 | offset = 0; | |
8c59967c | 1594 | } |
673a394b | 1595 | |
d59b21ec | 1596 | intel_fb_obj_flush(obj, ORIGIN_CPU); |
fe115628 | 1597 | i915_gem_obj_finish_shmem_access(obj); |
40123c1f | 1598 | return ret; |
673a394b EA |
1599 | } |
1600 | ||
1601 | /** | |
1602 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1603 | * @dev: drm device |
1604 | * @data: ioctl data blob | |
1605 | * @file: drm file | |
673a394b EA |
1606 | * |
1607 | * On error, the contents of the buffer that were to be modified are undefined. | |
1608 | */ | |
1609 | int | |
1610 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1611 | struct drm_file *file) |
673a394b EA |
1612 | { |
1613 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1614 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1615 | int ret; |
1616 | ||
1617 | if (args->size == 0) | |
1618 | return 0; | |
1619 | ||
1620 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1621 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1622 | args->size)) |
1623 | return -EFAULT; | |
1624 | ||
03ac0642 | 1625 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1626 | if (!obj) |
1627 | return -ENOENT; | |
673a394b | 1628 | |
7dcd2499 | 1629 | /* Bounds check destination. */ |
966d5bf5 | 1630 | if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { |
ce9d419d | 1631 | ret = -EINVAL; |
258a5ede | 1632 | goto err; |
ce9d419d CW |
1633 | } |
1634 | ||
f8c1cce3 CW |
1635 | /* Writes not allowed into this read-only object */ |
1636 | if (i915_gem_object_is_readonly(obj)) { | |
1637 | ret = -EINVAL; | |
1638 | goto err; | |
1639 | } | |
1640 | ||
db53a302 CW |
1641 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1642 | ||
7c55e2c5 CW |
1643 | ret = -ENODEV; |
1644 | if (obj->ops->pwrite) | |
1645 | ret = obj->ops->pwrite(obj, args); | |
1646 | if (ret != -ENODEV) | |
1647 | goto err; | |
1648 | ||
e95433c7 CW |
1649 | ret = i915_gem_object_wait(obj, |
1650 | I915_WAIT_INTERRUPTIBLE | | |
1651 | I915_WAIT_ALL, | |
1652 | MAX_SCHEDULE_TIMEOUT, | |
1653 | to_rps_client(file)); | |
258a5ede CW |
1654 | if (ret) |
1655 | goto err; | |
1656 | ||
fe115628 | 1657 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1658 | if (ret) |
fe115628 | 1659 | goto err; |
258a5ede | 1660 | |
935aaa69 | 1661 | ret = -EFAULT; |
673a394b EA |
1662 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1663 | * it would end up going through the fenced access, and we'll get | |
1664 | * different detiling behavior between reading and writing. | |
1665 | * pread/pwrite currently are reading and writing from the CPU | |
1666 | * perspective, requiring manual detiling by the client. | |
1667 | */ | |
6eae0059 | 1668 | if (!i915_gem_object_has_struct_page(obj) || |
9c870d03 | 1669 | cpu_write_needs_clflush(obj)) |
935aaa69 DV |
1670 | /* Note that the gtt paths might fail with non-page-backed user |
1671 | * pointers (e.g. gtt mappings when moving data between | |
9c870d03 CW |
1672 | * textures). Fallback to the shmem path in that case. |
1673 | */ | |
fe115628 | 1674 | ret = i915_gem_gtt_pwrite_fast(obj, args); |
673a394b | 1675 | |
d1054ee4 | 1676 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1677 | if (obj->phys_handle) |
1678 | ret = i915_gem_phys_pwrite(obj, args, file); | |
b50a5371 | 1679 | else |
fe115628 | 1680 | ret = i915_gem_shmem_pwrite(obj, args); |
6a2c4232 | 1681 | } |
5c0480f2 | 1682 | |
fe115628 | 1683 | i915_gem_object_unpin_pages(obj); |
258a5ede | 1684 | err: |
f0cd5182 | 1685 | i915_gem_object_put(obj); |
258a5ede | 1686 | return ret; |
673a394b EA |
1687 | } |
1688 | ||
40e62d5d CW |
1689 | static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj) |
1690 | { | |
1691 | struct drm_i915_private *i915; | |
1692 | struct list_head *list; | |
1693 | struct i915_vma *vma; | |
1694 | ||
f2123818 CW |
1695 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
1696 | ||
e2189dd0 | 1697 | for_each_ggtt_vma(vma, obj) { |
40e62d5d CW |
1698 | if (i915_vma_is_active(vma)) |
1699 | continue; | |
1700 | ||
1701 | if (!drm_mm_node_allocated(&vma->node)) | |
1702 | continue; | |
1703 | ||
1704 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
1705 | } | |
1706 | ||
1707 | i915 = to_i915(obj->base.dev); | |
f2123818 | 1708 | spin_lock(&i915->mm.obj_lock); |
40e62d5d | 1709 | list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list; |
f2123818 CW |
1710 | list_move_tail(&obj->mm.link, list); |
1711 | spin_unlock(&i915->mm.obj_lock); | |
40e62d5d CW |
1712 | } |
1713 | ||
673a394b | 1714 | /** |
2ef7eeaa EA |
1715 | * Called when user space prepares to use an object with the CPU, either |
1716 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1717 | * @dev: drm device |
1718 | * @data: ioctl data blob | |
1719 | * @file: drm file | |
673a394b EA |
1720 | */ |
1721 | int | |
1722 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1723 | struct drm_file *file) |
673a394b EA |
1724 | { |
1725 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1726 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1727 | uint32_t read_domains = args->read_domains; |
1728 | uint32_t write_domain = args->write_domain; | |
40e62d5d | 1729 | int err; |
673a394b | 1730 | |
2ef7eeaa | 1731 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1732 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1733 | return -EINVAL; |
1734 | ||
1735 | /* Having something in the write domain implies it's in the read | |
1736 | * domain, and only that read domain. Enforce that in the request. | |
1737 | */ | |
1738 | if (write_domain != 0 && read_domains != write_domain) | |
1739 | return -EINVAL; | |
1740 | ||
03ac0642 | 1741 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1742 | if (!obj) |
1743 | return -ENOENT; | |
673a394b | 1744 | |
3236f57a CW |
1745 | /* Try to flush the object off the GPU without holding the lock. |
1746 | * We will repeat the flush holding the lock in the normal manner | |
1747 | * to catch cases where we are gazumped. | |
1748 | */ | |
40e62d5d | 1749 | err = i915_gem_object_wait(obj, |
e95433c7 CW |
1750 | I915_WAIT_INTERRUPTIBLE | |
1751 | (write_domain ? I915_WAIT_ALL : 0), | |
1752 | MAX_SCHEDULE_TIMEOUT, | |
1753 | to_rps_client(file)); | |
40e62d5d | 1754 | if (err) |
f0cd5182 | 1755 | goto out; |
b8f9096d | 1756 | |
a03f395a TZ |
1757 | /* |
1758 | * Proxy objects do not control access to the backing storage, ergo | |
1759 | * they cannot be used as a means to manipulate the cache domain | |
1760 | * tracking for that backing storage. The proxy object is always | |
1761 | * considered to be outside of any cache domain. | |
1762 | */ | |
1763 | if (i915_gem_object_is_proxy(obj)) { | |
1764 | err = -ENXIO; | |
1765 | goto out; | |
1766 | } | |
1767 | ||
1768 | /* | |
1769 | * Flush and acquire obj->pages so that we are coherent through | |
40e62d5d CW |
1770 | * direct access in memory with previous cached writes through |
1771 | * shmemfs and that our cache domain tracking remains valid. | |
1772 | * For example, if the obj->filp was moved to swap without us | |
1773 | * being notified and releasing the pages, we would mistakenly | |
1774 | * continue to assume that the obj remained out of the CPU cached | |
1775 | * domain. | |
1776 | */ | |
1777 | err = i915_gem_object_pin_pages(obj); | |
1778 | if (err) | |
f0cd5182 | 1779 | goto out; |
40e62d5d CW |
1780 | |
1781 | err = i915_mutex_lock_interruptible(dev); | |
1782 | if (err) | |
f0cd5182 | 1783 | goto out_unpin; |
3236f57a | 1784 | |
e22d8e3c CW |
1785 | if (read_domains & I915_GEM_DOMAIN_WC) |
1786 | err = i915_gem_object_set_to_wc_domain(obj, write_domain); | |
1787 | else if (read_domains & I915_GEM_DOMAIN_GTT) | |
1788 | err = i915_gem_object_set_to_gtt_domain(obj, write_domain); | |
43566ded | 1789 | else |
e22d8e3c | 1790 | err = i915_gem_object_set_to_cpu_domain(obj, write_domain); |
2ef7eeaa | 1791 | |
40e62d5d CW |
1792 | /* And bump the LRU for this access */ |
1793 | i915_gem_object_bump_inactive_ggtt(obj); | |
031b698a | 1794 | |
673a394b | 1795 | mutex_unlock(&dev->struct_mutex); |
b8f9096d | 1796 | |
40e62d5d | 1797 | if (write_domain != 0) |
ef74921b CW |
1798 | intel_fb_obj_invalidate(obj, |
1799 | fb_write_origin(obj, write_domain)); | |
40e62d5d | 1800 | |
f0cd5182 | 1801 | out_unpin: |
40e62d5d | 1802 | i915_gem_object_unpin_pages(obj); |
f0cd5182 CW |
1803 | out: |
1804 | i915_gem_object_put(obj); | |
40e62d5d | 1805 | return err; |
673a394b EA |
1806 | } |
1807 | ||
1808 | /** | |
1809 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1810 | * @dev: drm device |
1811 | * @data: ioctl data blob | |
1812 | * @file: drm file | |
673a394b EA |
1813 | */ |
1814 | int | |
1815 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1816 | struct drm_file *file) |
673a394b EA |
1817 | { |
1818 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1819 | struct drm_i915_gem_object *obj; |
1d7cfea1 | 1820 | |
03ac0642 | 1821 | obj = i915_gem_object_lookup(file, args->handle); |
c21724cc CW |
1822 | if (!obj) |
1823 | return -ENOENT; | |
673a394b | 1824 | |
a03f395a TZ |
1825 | /* |
1826 | * Proxy objects are barred from CPU access, so there is no | |
1827 | * need to ban sw_finish as it is a nop. | |
1828 | */ | |
1829 | ||
673a394b | 1830 | /* Pinned buffers may be scanout, so flush the cache */ |
5a97bcc6 | 1831 | i915_gem_object_flush_if_display(obj); |
f0cd5182 | 1832 | i915_gem_object_put(obj); |
5a97bcc6 CW |
1833 | |
1834 | return 0; | |
673a394b EA |
1835 | } |
1836 | ||
1837 | /** | |
14bb2c11 TU |
1838 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1839 | * it is mapped to. | |
1840 | * @dev: drm device | |
1841 | * @data: ioctl data blob | |
1842 | * @file: drm file | |
673a394b EA |
1843 | * |
1844 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1845 | * imply a ref on the object itself. | |
34367381 DV |
1846 | * |
1847 | * IMPORTANT: | |
1848 | * | |
1849 | * DRM driver writers who look a this function as an example for how to do GEM | |
1850 | * mmap support, please don't implement mmap support like here. The modern way | |
1851 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1852 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1853 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1854 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1855 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1856 | */ |
1857 | int | |
1858 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1859 | struct drm_file *file) |
673a394b EA |
1860 | { |
1861 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1862 | struct drm_i915_gem_object *obj; |
673a394b EA |
1863 | unsigned long addr; |
1864 | ||
1816f923 AG |
1865 | if (args->flags & ~(I915_MMAP_WC)) |
1866 | return -EINVAL; | |
1867 | ||
568a58e5 | 1868 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1869 | return -ENODEV; |
1870 | ||
03ac0642 CW |
1871 | obj = i915_gem_object_lookup(file, args->handle); |
1872 | if (!obj) | |
bf79cb91 | 1873 | return -ENOENT; |
673a394b | 1874 | |
1286ff73 DV |
1875 | /* prime objects have no backing filp to GEM mmap |
1876 | * pages from. | |
1877 | */ | |
03ac0642 | 1878 | if (!obj->base.filp) { |
f0cd5182 | 1879 | i915_gem_object_put(obj); |
274b2462 | 1880 | return -ENXIO; |
1286ff73 DV |
1881 | } |
1882 | ||
03ac0642 | 1883 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1884 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1885 | args->offset); | |
1816f923 AG |
1886 | if (args->flags & I915_MMAP_WC) { |
1887 | struct mm_struct *mm = current->mm; | |
1888 | struct vm_area_struct *vma; | |
1889 | ||
80a89a5e | 1890 | if (down_write_killable(&mm->mmap_sem)) { |
f0cd5182 | 1891 | i915_gem_object_put(obj); |
80a89a5e MH |
1892 | return -EINTR; |
1893 | } | |
1816f923 AG |
1894 | vma = find_vma(mm, addr); |
1895 | if (vma) | |
1896 | vma->vm_page_prot = | |
1897 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1898 | else | |
1899 | addr = -ENOMEM; | |
1900 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1901 | |
1902 | /* This may race, but that's ok, it only gets set */ | |
50349247 | 1903 | WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU); |
1816f923 | 1904 | } |
f0cd5182 | 1905 | i915_gem_object_put(obj); |
673a394b EA |
1906 | if (IS_ERR((void *)addr)) |
1907 | return addr; | |
1908 | ||
1909 | args->addr_ptr = (uint64_t) addr; | |
1910 | ||
1911 | return 0; | |
1912 | } | |
1913 | ||
d899aceb | 1914 | static unsigned int tile_row_pages(const struct drm_i915_gem_object *obj) |
03af84fe | 1915 | { |
6649a0b6 | 1916 | return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT; |
03af84fe CW |
1917 | } |
1918 | ||
4cc69075 CW |
1919 | /** |
1920 | * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps | |
1921 | * | |
1922 | * A history of the GTT mmap interface: | |
1923 | * | |
1924 | * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to | |
1925 | * aligned and suitable for fencing, and still fit into the available | |
1926 | * mappable space left by the pinned display objects. A classic problem | |
1927 | * we called the page-fault-of-doom where we would ping-pong between | |
1928 | * two objects that could not fit inside the GTT and so the memcpy | |
1929 | * would page one object in at the expense of the other between every | |
1930 | * single byte. | |
1931 | * | |
1932 | * 1 - Objects can be any size, and have any compatible fencing (X Y, or none | |
1933 | * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the | |
1934 | * object is too large for the available space (or simply too large | |
1935 | * for the mappable aperture!), a view is created instead and faulted | |
1936 | * into userspace. (This view is aligned and sized appropriately for | |
1937 | * fenced access.) | |
1938 | * | |
e22d8e3c CW |
1939 | * 2 - Recognise WC as a separate cache domain so that we can flush the |
1940 | * delayed writes via GTT before performing direct access via WC. | |
1941 | * | |
4cc69075 CW |
1942 | * Restrictions: |
1943 | * | |
1944 | * * snoopable objects cannot be accessed via the GTT. It can cause machine | |
1945 | * hangs on some architectures, corruption on others. An attempt to service | |
1946 | * a GTT page fault from a snoopable object will generate a SIGBUS. | |
1947 | * | |
1948 | * * the object must be able to fit into RAM (physical memory, though no | |
1949 | * limited to the mappable aperture). | |
1950 | * | |
1951 | * | |
1952 | * Caveats: | |
1953 | * | |
1954 | * * a new GTT page fault will synchronize rendering from the GPU and flush | |
1955 | * all data to system memory. Subsequent access will not be synchronized. | |
1956 | * | |
1957 | * * all mappings are revoked on runtime device suspend. | |
1958 | * | |
1959 | * * there are only 8, 16 or 32 fence registers to share between all users | |
1960 | * (older machines require fence register for display and blitter access | |
1961 | * as well). Contention of the fence registers will cause the previous users | |
1962 | * to be unmapped and any new access will generate new page faults. | |
1963 | * | |
1964 | * * running out of memory while servicing a fault may generate a SIGBUS, | |
1965 | * rather than the expected SIGSEGV. | |
1966 | */ | |
1967 | int i915_gem_mmap_gtt_version(void) | |
1968 | { | |
e22d8e3c | 1969 | return 2; |
4cc69075 CW |
1970 | } |
1971 | ||
2d4281bb | 1972 | static inline struct i915_ggtt_view |
d899aceb | 1973 | compute_partial_view(const struct drm_i915_gem_object *obj, |
2d4281bb CW |
1974 | pgoff_t page_offset, |
1975 | unsigned int chunk) | |
1976 | { | |
1977 | struct i915_ggtt_view view; | |
1978 | ||
1979 | if (i915_gem_object_is_tiled(obj)) | |
1980 | chunk = roundup(chunk, tile_row_pages(obj)); | |
1981 | ||
2d4281bb | 1982 | view.type = I915_GGTT_VIEW_PARTIAL; |
8bab1193 CW |
1983 | view.partial.offset = rounddown(page_offset, chunk); |
1984 | view.partial.size = | |
2d4281bb | 1985 | min_t(unsigned int, chunk, |
8bab1193 | 1986 | (obj->base.size >> PAGE_SHIFT) - view.partial.offset); |
2d4281bb CW |
1987 | |
1988 | /* If the partial covers the entire object, just create a normal VMA. */ | |
1989 | if (chunk >= obj->base.size >> PAGE_SHIFT) | |
1990 | view.type = I915_GGTT_VIEW_NORMAL; | |
1991 | ||
1992 | return view; | |
1993 | } | |
1994 | ||
de151cf6 JB |
1995 | /** |
1996 | * i915_gem_fault - fault a page into the GTT | |
d9072a3e | 1997 | * @vmf: fault info |
de151cf6 JB |
1998 | * |
1999 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
2000 | * from userspace. The fault handler takes care of binding the object to | |
2001 | * the GTT (if needed), allocating and programming a fence register (again, | |
2002 | * only if needed based on whether the old reg is still valid or the object | |
2003 | * is tiled) and inserting a new PTE into the faulting process. | |
2004 | * | |
2005 | * Note that the faulting process may involve evicting existing objects | |
2006 | * from the GTT and/or fence registers to make room. So performance may | |
2007 | * suffer if the GTT working set is large or there are few fence registers | |
2008 | * left. | |
4cc69075 CW |
2009 | * |
2010 | * The current feature set supported by i915_gem_fault() and thus GTT mmaps | |
2011 | * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version). | |
de151cf6 | 2012 | */ |
52137010 | 2013 | vm_fault_t i915_gem_fault(struct vm_fault *vmf) |
de151cf6 | 2014 | { |
420980ca | 2015 | #define MIN_CHUNK_PAGES (SZ_1M >> PAGE_SHIFT) |
11bac800 | 2016 | struct vm_area_struct *area = vmf->vma; |
058d88c4 | 2017 | struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data); |
05394f39 | 2018 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
2019 | struct drm_i915_private *dev_priv = to_i915(dev); |
2020 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
aae7c06b | 2021 | bool write = area->vm_flags & VM_WRITE; |
058d88c4 | 2022 | struct i915_vma *vma; |
de151cf6 | 2023 | pgoff_t page_offset; |
b8f9096d | 2024 | int ret; |
f65c9168 | 2025 | |
3e977ac6 CW |
2026 | /* Sanity check that we allow writing into this object */ |
2027 | if (i915_gem_object_is_readonly(obj) && write) | |
2028 | return VM_FAULT_SIGBUS; | |
2029 | ||
de151cf6 | 2030 | /* We don't use vmf->pgoff since that has the fake offset */ |
1a29d85e | 2031 | page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT; |
de151cf6 | 2032 | |
db53a302 CW |
2033 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
2034 | ||
6e4930f6 | 2035 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 2036 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
2037 | * repeat the flush holding the lock in the normal manner to catch cases |
2038 | * where we are gazumped. | |
2039 | */ | |
e95433c7 CW |
2040 | ret = i915_gem_object_wait(obj, |
2041 | I915_WAIT_INTERRUPTIBLE, | |
2042 | MAX_SCHEDULE_TIMEOUT, | |
2043 | NULL); | |
6e4930f6 | 2044 | if (ret) |
b8f9096d CW |
2045 | goto err; |
2046 | ||
40e62d5d CW |
2047 | ret = i915_gem_object_pin_pages(obj); |
2048 | if (ret) | |
2049 | goto err; | |
2050 | ||
b8f9096d CW |
2051 | intel_runtime_pm_get(dev_priv); |
2052 | ||
2053 | ret = i915_mutex_lock_interruptible(dev); | |
2054 | if (ret) | |
2055 | goto err_rpm; | |
6e4930f6 | 2056 | |
eb119bd6 | 2057 | /* Access to snoopable pages through the GTT is incoherent. */ |
0031fb96 | 2058 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) { |
ddeff6ee | 2059 | ret = -EFAULT; |
b8f9096d | 2060 | goto err_unlock; |
eb119bd6 CW |
2061 | } |
2062 | ||
82118877 | 2063 | |
a61007a8 | 2064 | /* Now pin it into the GTT as needed */ |
7e7367d3 CW |
2065 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
2066 | PIN_MAPPABLE | | |
2067 | PIN_NONBLOCK | | |
2068 | PIN_NONFAULT); | |
a61007a8 | 2069 | if (IS_ERR(vma)) { |
a61007a8 | 2070 | /* Use a partial view if it is bigger than available space */ |
2d4281bb | 2071 | struct i915_ggtt_view view = |
8201c1fa | 2072 | compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES); |
7e7367d3 | 2073 | unsigned int flags; |
aa136d9d | 2074 | |
7e7367d3 CW |
2075 | flags = PIN_MAPPABLE; |
2076 | if (view.type == I915_GGTT_VIEW_NORMAL) | |
2077 | flags |= PIN_NONBLOCK; /* avoid warnings for pinned */ | |
2078 | ||
2079 | /* | |
2080 | * Userspace is now writing through an untracked VMA, abandon | |
50349247 CW |
2081 | * all hope that the hardware is able to track future writes. |
2082 | */ | |
2083 | obj->frontbuffer_ggtt_origin = ORIGIN_CPU; | |
2084 | ||
7e7367d3 CW |
2085 | vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, flags); |
2086 | if (IS_ERR(vma) && !view.type) { | |
2087 | flags = PIN_MAPPABLE; | |
2088 | view.type = I915_GGTT_VIEW_PARTIAL; | |
2089 | vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, flags); | |
2090 | } | |
a61007a8 | 2091 | } |
058d88c4 CW |
2092 | if (IS_ERR(vma)) { |
2093 | ret = PTR_ERR(vma); | |
b8f9096d | 2094 | goto err_unlock; |
058d88c4 | 2095 | } |
4a684a41 | 2096 | |
c9839303 CW |
2097 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
2098 | if (ret) | |
b8f9096d | 2099 | goto err_unpin; |
74898d7e | 2100 | |
3bd40735 | 2101 | ret = i915_vma_pin_fence(vma); |
d9e86c0e | 2102 | if (ret) |
b8f9096d | 2103 | goto err_unpin; |
7d1c4804 | 2104 | |
b90b91d8 | 2105 | /* Finally, remap it using the new GTT offset */ |
c58305af | 2106 | ret = remap_io_mapping(area, |
8bab1193 | 2107 | area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT), |
73ebd503 | 2108 | (ggtt->gmadr.start + vma->node.start) >> PAGE_SHIFT, |
c58305af | 2109 | min_t(u64, vma->size, area->vm_end - area->vm_start), |
73ebd503 | 2110 | &ggtt->iomap); |
a65adaf8 CW |
2111 | if (ret) |
2112 | goto err_fence; | |
a61007a8 | 2113 | |
a65adaf8 CW |
2114 | /* Mark as being mmapped into userspace for later revocation */ |
2115 | assert_rpm_wakelock_held(dev_priv); | |
2116 | if (!i915_vma_set_userfault(vma) && !obj->userfault_count++) | |
2117 | list_add(&obj->userfault_link, &dev_priv->mm.userfault_list); | |
2118 | GEM_BUG_ON(!obj->userfault_count); | |
2119 | ||
7125397b CW |
2120 | i915_vma_set_ggtt_write(vma); |
2121 | ||
a65adaf8 | 2122 | err_fence: |
3bd40735 | 2123 | i915_vma_unpin_fence(vma); |
b8f9096d | 2124 | err_unpin: |
058d88c4 | 2125 | __i915_vma_unpin(vma); |
b8f9096d | 2126 | err_unlock: |
de151cf6 | 2127 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
2128 | err_rpm: |
2129 | intel_runtime_pm_put(dev_priv); | |
40e62d5d | 2130 | i915_gem_object_unpin_pages(obj); |
b8f9096d | 2131 | err: |
de151cf6 | 2132 | switch (ret) { |
d9bc7e9f | 2133 | case -EIO: |
2232f031 DV |
2134 | /* |
2135 | * We eat errors when the gpu is terminally wedged to avoid | |
2136 | * userspace unduly crashing (gl has no provisions for mmaps to | |
2137 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
2138 | * and so needs to be reported. | |
2139 | */ | |
52137010 CW |
2140 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) |
2141 | return VM_FAULT_SIGBUS; | |
f0d759f0 | 2142 | /* else: fall through */ |
045e769a | 2143 | case -EAGAIN: |
571c608d DV |
2144 | /* |
2145 | * EAGAIN means the gpu is hung and we'll wait for the error | |
2146 | * handler to reset everything when re-faulting in | |
2147 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 2148 | */ |
c715089f CW |
2149 | case 0: |
2150 | case -ERESTARTSYS: | |
bed636ab | 2151 | case -EINTR: |
e79e0fe3 DR |
2152 | case -EBUSY: |
2153 | /* | |
2154 | * EBUSY is ok: this just means that another thread | |
2155 | * already did the job. | |
2156 | */ | |
52137010 | 2157 | return VM_FAULT_NOPAGE; |
de151cf6 | 2158 | case -ENOMEM: |
52137010 | 2159 | return VM_FAULT_OOM; |
a7c2e1aa | 2160 | case -ENOSPC: |
45d67817 | 2161 | case -EFAULT: |
52137010 | 2162 | return VM_FAULT_SIGBUS; |
de151cf6 | 2163 | default: |
a7c2e1aa | 2164 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
52137010 | 2165 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
2166 | } |
2167 | } | |
2168 | ||
a65adaf8 CW |
2169 | static void __i915_gem_object_release_mmap(struct drm_i915_gem_object *obj) |
2170 | { | |
2171 | struct i915_vma *vma; | |
2172 | ||
2173 | GEM_BUG_ON(!obj->userfault_count); | |
2174 | ||
2175 | obj->userfault_count = 0; | |
2176 | list_del(&obj->userfault_link); | |
2177 | drm_vma_node_unmap(&obj->base.vma_node, | |
2178 | obj->base.dev->anon_inode->i_mapping); | |
2179 | ||
e2189dd0 | 2180 | for_each_ggtt_vma(vma, obj) |
a65adaf8 | 2181 | i915_vma_unset_userfault(vma); |
a65adaf8 CW |
2182 | } |
2183 | ||
901782b2 CW |
2184 | /** |
2185 | * i915_gem_release_mmap - remove physical page mappings | |
2186 | * @obj: obj in question | |
2187 | * | |
af901ca1 | 2188 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
2189 | * relinquish ownership of the pages back to the system. |
2190 | * | |
2191 | * It is vital that we remove the page mapping if we have mapped a tiled | |
2192 | * object through the GTT and then lose the fence register due to | |
2193 | * resource pressure. Similarly if the object has been moved out of the | |
2194 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
2195 | * mapping will then trigger a page fault on the next user access, allowing | |
2196 | * fixup by i915_gem_fault(). | |
2197 | */ | |
d05ca301 | 2198 | void |
05394f39 | 2199 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 2200 | { |
275f039d | 2201 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
275f039d | 2202 | |
349f2ccf CW |
2203 | /* Serialisation between user GTT access and our code depends upon |
2204 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
2205 | * pagefault then has to wait until we release the mutex. | |
9c870d03 CW |
2206 | * |
2207 | * Note that RPM complicates somewhat by adding an additional | |
2208 | * requirement that operations to the GGTT be made holding the RPM | |
2209 | * wakeref. | |
349f2ccf | 2210 | */ |
275f039d | 2211 | lockdep_assert_held(&i915->drm.struct_mutex); |
9c870d03 | 2212 | intel_runtime_pm_get(i915); |
349f2ccf | 2213 | |
a65adaf8 | 2214 | if (!obj->userfault_count) |
9c870d03 | 2215 | goto out; |
901782b2 | 2216 | |
a65adaf8 | 2217 | __i915_gem_object_release_mmap(obj); |
349f2ccf CW |
2218 | |
2219 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
2220 | * memory transactions from userspace before we return. The TLB | |
2221 | * flushing implied above by changing the PTE above *should* be | |
2222 | * sufficient, an extra barrier here just provides us with a bit | |
2223 | * of paranoid documentation about our requirement to serialise | |
2224 | * memory writes before touching registers / GSM. | |
2225 | */ | |
2226 | wmb(); | |
9c870d03 CW |
2227 | |
2228 | out: | |
2229 | intel_runtime_pm_put(i915); | |
901782b2 CW |
2230 | } |
2231 | ||
7c108fd8 | 2232 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) |
eedd10f4 | 2233 | { |
3594a3e2 | 2234 | struct drm_i915_gem_object *obj, *on; |
7c108fd8 | 2235 | int i; |
eedd10f4 | 2236 | |
3594a3e2 CW |
2237 | /* |
2238 | * Only called during RPM suspend. All users of the userfault_list | |
2239 | * must be holding an RPM wakeref to ensure that this can not | |
2240 | * run concurrently with themselves (and use the struct_mutex for | |
2241 | * protection between themselves). | |
2242 | */ | |
275f039d | 2243 | |
3594a3e2 | 2244 | list_for_each_entry_safe(obj, on, |
a65adaf8 CW |
2245 | &dev_priv->mm.userfault_list, userfault_link) |
2246 | __i915_gem_object_release_mmap(obj); | |
7c108fd8 CW |
2247 | |
2248 | /* The fence will be lost when the device powers down. If any were | |
2249 | * in use by hardware (i.e. they are pinned), we should not be powering | |
2250 | * down! All other fences will be reacquired by the user upon waking. | |
2251 | */ | |
2252 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
2253 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
2254 | ||
e0ec3ec6 CW |
2255 | /* Ideally we want to assert that the fence register is not |
2256 | * live at this point (i.e. that no piece of code will be | |
2257 | * trying to write through fence + GTT, as that both violates | |
2258 | * our tracking of activity and associated locking/barriers, | |
2259 | * but also is illegal given that the hw is powered down). | |
2260 | * | |
2261 | * Previously we used reg->pin_count as a "liveness" indicator. | |
2262 | * That is not sufficient, and we need a more fine-grained | |
2263 | * tool if we want to have a sanity check here. | |
2264 | */ | |
7c108fd8 CW |
2265 | |
2266 | if (!reg->vma) | |
2267 | continue; | |
2268 | ||
a65adaf8 | 2269 | GEM_BUG_ON(i915_vma_has_userfault(reg->vma)); |
7c108fd8 CW |
2270 | reg->dirty = true; |
2271 | } | |
eedd10f4 CW |
2272 | } |
2273 | ||
d8cb5086 CW |
2274 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2275 | { | |
fac5e23e | 2276 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 2277 | int err; |
da494d7c | 2278 | |
f3f6184c | 2279 | err = drm_gem_create_mmap_offset(&obj->base); |
b42a13d9 | 2280 | if (likely(!err)) |
f3f6184c | 2281 | return 0; |
d8cb5086 | 2282 | |
b42a13d9 CW |
2283 | /* Attempt to reap some mmap space from dead objects */ |
2284 | do { | |
ec625fb9 CW |
2285 | err = i915_gem_wait_for_idle(dev_priv, |
2286 | I915_WAIT_INTERRUPTIBLE, | |
2287 | MAX_SCHEDULE_TIMEOUT); | |
b42a13d9 CW |
2288 | if (err) |
2289 | break; | |
f3f6184c | 2290 | |
b42a13d9 | 2291 | i915_gem_drain_freed_objects(dev_priv); |
f3f6184c | 2292 | err = drm_gem_create_mmap_offset(&obj->base); |
b42a13d9 CW |
2293 | if (!err) |
2294 | break; | |
2295 | ||
2296 | } while (flush_delayed_work(&dev_priv->gt.retire_work)); | |
da494d7c | 2297 | |
f3f6184c | 2298 | return err; |
d8cb5086 CW |
2299 | } |
2300 | ||
2301 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2302 | { | |
d8cb5086 CW |
2303 | drm_gem_free_mmap_offset(&obj->base); |
2304 | } | |
2305 | ||
da6b51d0 | 2306 | int |
ff72145b DA |
2307 | i915_gem_mmap_gtt(struct drm_file *file, |
2308 | struct drm_device *dev, | |
da6b51d0 | 2309 | uint32_t handle, |
ff72145b | 2310 | uint64_t *offset) |
de151cf6 | 2311 | { |
05394f39 | 2312 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2313 | int ret; |
2314 | ||
03ac0642 | 2315 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
2316 | if (!obj) |
2317 | return -ENOENT; | |
ab18282d | 2318 | |
d8cb5086 | 2319 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
2320 | if (ret == 0) |
2321 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 2322 | |
f0cd5182 | 2323 | i915_gem_object_put(obj); |
1d7cfea1 | 2324 | return ret; |
de151cf6 JB |
2325 | } |
2326 | ||
ff72145b DA |
2327 | /** |
2328 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2329 | * @dev: DRM device | |
2330 | * @data: GTT mapping ioctl data | |
2331 | * @file: GEM object info | |
2332 | * | |
2333 | * Simply returns the fake offset to userspace so it can mmap it. | |
2334 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2335 | * up so we can get faults in the handler above. | |
2336 | * | |
2337 | * The fault handler will take care of binding the object into the GTT | |
2338 | * (since it may have been evicted to make room for something), allocating | |
2339 | * a fence register, and mapping the appropriate aperture address into | |
2340 | * userspace. | |
2341 | */ | |
2342 | int | |
2343 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2344 | struct drm_file *file) | |
2345 | { | |
2346 | struct drm_i915_gem_mmap_gtt *args = data; | |
2347 | ||
da6b51d0 | 2348 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2349 | } |
2350 | ||
225067ee DV |
2351 | /* Immediately discard the backing storage */ |
2352 | static void | |
2353 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2354 | { |
4d6294bf | 2355 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2356 | |
4d6294bf CW |
2357 | if (obj->base.filp == NULL) |
2358 | return; | |
e5281ccd | 2359 | |
225067ee DV |
2360 | /* Our goal here is to return as much of the memory as |
2361 | * is possible back to the system as we are called from OOM. | |
2362 | * To do this we must instruct the shmfs to drop all of its | |
2363 | * backing pages, *now*. | |
2364 | */ | |
5537252b | 2365 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
a4f5ea64 | 2366 | obj->mm.madv = __I915_MADV_PURGED; |
4e5462ee | 2367 | obj->mm.pages = ERR_PTR(-EFAULT); |
225067ee | 2368 | } |
e5281ccd | 2369 | |
5537252b | 2370 | /* Try to discard unwanted pages */ |
03ac84f1 | 2371 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
225067ee | 2372 | { |
5537252b CW |
2373 | struct address_space *mapping; |
2374 | ||
1233e2db | 2375 | lockdep_assert_held(&obj->mm.lock); |
f1fa4f44 | 2376 | GEM_BUG_ON(i915_gem_object_has_pages(obj)); |
1233e2db | 2377 | |
a4f5ea64 | 2378 | switch (obj->mm.madv) { |
5537252b CW |
2379 | case I915_MADV_DONTNEED: |
2380 | i915_gem_object_truncate(obj); | |
2381 | case __I915_MADV_PURGED: | |
2382 | return; | |
2383 | } | |
2384 | ||
2385 | if (obj->base.filp == NULL) | |
2386 | return; | |
2387 | ||
93c76a3d | 2388 | mapping = obj->base.filp->f_mapping, |
5537252b | 2389 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
e5281ccd CW |
2390 | } |
2391 | ||
5cdf5881 | 2392 | static void |
03ac84f1 CW |
2393 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj, |
2394 | struct sg_table *pages) | |
673a394b | 2395 | { |
85d1225e DG |
2396 | struct sgt_iter sgt_iter; |
2397 | struct page *page; | |
1286ff73 | 2398 | |
e5facdf9 | 2399 | __i915_gem_object_release_shmem(obj, pages, true); |
673a394b | 2400 | |
03ac84f1 | 2401 | i915_gem_gtt_finish_pages(obj, pages); |
e2273302 | 2402 | |
6dacfd2f | 2403 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2404 | i915_gem_object_save_bit_17_swizzle(obj, pages); |
280b713b | 2405 | |
03ac84f1 | 2406 | for_each_sgt_page(page, sgt_iter, pages) { |
a4f5ea64 | 2407 | if (obj->mm.dirty) |
9da3da66 | 2408 | set_page_dirty(page); |
3ef94daa | 2409 | |
a4f5ea64 | 2410 | if (obj->mm.madv == I915_MADV_WILLNEED) |
9da3da66 | 2411 | mark_page_accessed(page); |
3ef94daa | 2412 | |
09cbfeaf | 2413 | put_page(page); |
3ef94daa | 2414 | } |
a4f5ea64 | 2415 | obj->mm.dirty = false; |
673a394b | 2416 | |
03ac84f1 CW |
2417 | sg_free_table(pages); |
2418 | kfree(pages); | |
37e680a1 | 2419 | } |
6c085a72 | 2420 | |
96d77634 CW |
2421 | static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj) |
2422 | { | |
2423 | struct radix_tree_iter iter; | |
c23aa71b | 2424 | void __rcu **slot; |
96d77634 | 2425 | |
bea6e987 | 2426 | rcu_read_lock(); |
a4f5ea64 CW |
2427 | radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0) |
2428 | radix_tree_delete(&obj->mm.get_page.radix, iter.index); | |
bea6e987 | 2429 | rcu_read_unlock(); |
96d77634 CW |
2430 | } |
2431 | ||
acd1c1e6 CW |
2432 | static struct sg_table * |
2433 | __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj) | |
37e680a1 | 2434 | { |
f2123818 | 2435 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
03ac84f1 | 2436 | struct sg_table *pages; |
37e680a1 | 2437 | |
03ac84f1 | 2438 | pages = fetch_and_zero(&obj->mm.pages); |
acd1c1e6 CW |
2439 | if (!pages) |
2440 | return NULL; | |
a2165e31 | 2441 | |
f2123818 CW |
2442 | spin_lock(&i915->mm.obj_lock); |
2443 | list_del(&obj->mm.link); | |
2444 | spin_unlock(&i915->mm.obj_lock); | |
2445 | ||
a4f5ea64 | 2446 | if (obj->mm.mapping) { |
4b30cb23 CW |
2447 | void *ptr; |
2448 | ||
0ce81788 | 2449 | ptr = page_mask_bits(obj->mm.mapping); |
4b30cb23 CW |
2450 | if (is_vmalloc_addr(ptr)) |
2451 | vunmap(ptr); | |
fb8621d3 | 2452 | else |
4b30cb23 CW |
2453 | kunmap(kmap_to_page(ptr)); |
2454 | ||
a4f5ea64 | 2455 | obj->mm.mapping = NULL; |
0a798eb9 CW |
2456 | } |
2457 | ||
96d77634 | 2458 | __i915_gem_object_reset_page_iter(obj); |
acd1c1e6 CW |
2459 | obj->mm.page_sizes.phys = obj->mm.page_sizes.sg = 0; |
2460 | ||
2461 | return pages; | |
2462 | } | |
96d77634 | 2463 | |
acd1c1e6 CW |
2464 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, |
2465 | enum i915_mm_subclass subclass) | |
2466 | { | |
2467 | struct sg_table *pages; | |
2468 | ||
2469 | if (i915_gem_object_has_pinned_pages(obj)) | |
2470 | return; | |
2471 | ||
2472 | GEM_BUG_ON(obj->bind_count); | |
2473 | if (!i915_gem_object_has_pages(obj)) | |
2474 | return; | |
2475 | ||
2476 | /* May be called by shrinker from within get_pages() (on another bo) */ | |
2477 | mutex_lock_nested(&obj->mm.lock, subclass); | |
2478 | if (unlikely(atomic_read(&obj->mm.pages_pin_count))) | |
2479 | goto unlock; | |
2480 | ||
2481 | /* | |
2482 | * ->put_pages might need to allocate memory for the bit17 swizzle | |
2483 | * array, hence protect them from being reaped by removing them from gtt | |
2484 | * lists early. | |
2485 | */ | |
2486 | pages = __i915_gem_object_unset_pages(obj); | |
4e5462ee CW |
2487 | if (!IS_ERR(pages)) |
2488 | obj->ops->put_pages(obj, pages); | |
2489 | ||
1233e2db CW |
2490 | unlock: |
2491 | mutex_unlock(&obj->mm.lock); | |
6c085a72 CW |
2492 | } |
2493 | ||
935a2f77 | 2494 | static bool i915_sg_trim(struct sg_table *orig_st) |
0c40ce13 TU |
2495 | { |
2496 | struct sg_table new_st; | |
2497 | struct scatterlist *sg, *new_sg; | |
2498 | unsigned int i; | |
2499 | ||
2500 | if (orig_st->nents == orig_st->orig_nents) | |
935a2f77 | 2501 | return false; |
0c40ce13 | 2502 | |
8bfc478f | 2503 | if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN)) |
935a2f77 | 2504 | return false; |
0c40ce13 TU |
2505 | |
2506 | new_sg = new_st.sgl; | |
2507 | for_each_sg(orig_st->sgl, sg, orig_st->nents, i) { | |
2508 | sg_set_page(new_sg, sg_page(sg), sg->length, 0); | |
c6d22ab6 MA |
2509 | sg_dma_address(new_sg) = sg_dma_address(sg); |
2510 | sg_dma_len(new_sg) = sg_dma_len(sg); | |
2511 | ||
0c40ce13 TU |
2512 | new_sg = sg_next(new_sg); |
2513 | } | |
c2dc6cc9 | 2514 | GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */ |
0c40ce13 TU |
2515 | |
2516 | sg_free_table(orig_st); | |
2517 | ||
2518 | *orig_st = new_st; | |
935a2f77 | 2519 | return true; |
0c40ce13 TU |
2520 | } |
2521 | ||
b91b09ee | 2522 | static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2523 | { |
fac5e23e | 2524 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d766ef53 CW |
2525 | const unsigned long page_count = obj->base.size / PAGE_SIZE; |
2526 | unsigned long i; | |
e5281ccd | 2527 | struct address_space *mapping; |
9da3da66 CW |
2528 | struct sg_table *st; |
2529 | struct scatterlist *sg; | |
85d1225e | 2530 | struct sgt_iter sgt_iter; |
e5281ccd | 2531 | struct page *page; |
90797e6d | 2532 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
5602452e | 2533 | unsigned int max_segment = i915_sg_segment_size(); |
84e8978e | 2534 | unsigned int sg_page_sizes; |
4846bf0c | 2535 | gfp_t noreclaim; |
e2273302 | 2536 | int ret; |
e5281ccd | 2537 | |
e0ff7a7c CW |
2538 | /* |
2539 | * Assert that the object is not currently in any GPU domain. As it | |
6c085a72 CW |
2540 | * wasn't in the GTT, there shouldn't be any way it could have been in |
2541 | * a GPU cache | |
2542 | */ | |
c0a51fd0 CK |
2543 | GEM_BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2544 | GEM_BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
6c085a72 | 2545 | |
e0ff7a7c CW |
2546 | /* |
2547 | * If there's no chance of allocating enough pages for the whole | |
2548 | * object, bail early. | |
2549 | */ | |
2550 | if (page_count > totalram_pages) | |
2551 | return -ENOMEM; | |
2552 | ||
9da3da66 CW |
2553 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2554 | if (st == NULL) | |
b91b09ee | 2555 | return -ENOMEM; |
9da3da66 | 2556 | |
d766ef53 | 2557 | rebuild_st: |
9da3da66 | 2558 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2559 | kfree(st); |
b91b09ee | 2560 | return -ENOMEM; |
9da3da66 | 2561 | } |
e5281ccd | 2562 | |
e0ff7a7c CW |
2563 | /* |
2564 | * Get the list of pages out of our struct file. They'll be pinned | |
9da3da66 CW |
2565 | * at this point until we release them. |
2566 | * | |
2567 | * Fail silently without starting the shrinker | |
2568 | */ | |
93c76a3d | 2569 | mapping = obj->base.filp->f_mapping; |
0f6ab55d | 2570 | noreclaim = mapping_gfp_constraint(mapping, ~__GFP_RECLAIM); |
4846bf0c CW |
2571 | noreclaim |= __GFP_NORETRY | __GFP_NOWARN; |
2572 | ||
90797e6d ID |
2573 | sg = st->sgl; |
2574 | st->nents = 0; | |
84e8978e | 2575 | sg_page_sizes = 0; |
90797e6d | 2576 | for (i = 0; i < page_count; i++) { |
4846bf0c CW |
2577 | const unsigned int shrink[] = { |
2578 | I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_PURGEABLE, | |
2579 | 0, | |
2580 | }, *s = shrink; | |
2581 | gfp_t gfp = noreclaim; | |
2582 | ||
2583 | do { | |
6c085a72 | 2584 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
4846bf0c CW |
2585 | if (likely(!IS_ERR(page))) |
2586 | break; | |
2587 | ||
2588 | if (!*s) { | |
2589 | ret = PTR_ERR(page); | |
2590 | goto err_sg; | |
2591 | } | |
2592 | ||
912d572d | 2593 | i915_gem_shrink(dev_priv, 2 * page_count, NULL, *s++); |
4846bf0c | 2594 | cond_resched(); |
24f8e00a | 2595 | |
e0ff7a7c CW |
2596 | /* |
2597 | * We've tried hard to allocate the memory by reaping | |
6c085a72 CW |
2598 | * our own buffer, now let the real VM do its job and |
2599 | * go down in flames if truly OOM. | |
24f8e00a CW |
2600 | * |
2601 | * However, since graphics tend to be disposable, | |
2602 | * defer the oom here by reporting the ENOMEM back | |
2603 | * to userspace. | |
6c085a72 | 2604 | */ |
4846bf0c CW |
2605 | if (!*s) { |
2606 | /* reclaim and warn, but no oom */ | |
2607 | gfp = mapping_gfp_mask(mapping); | |
eaf41801 | 2608 | |
e0ff7a7c CW |
2609 | /* |
2610 | * Our bo are always dirty and so we require | |
eaf41801 CW |
2611 | * kswapd to reclaim our pages (direct reclaim |
2612 | * does not effectively begin pageout of our | |
2613 | * buffers on its own). However, direct reclaim | |
2614 | * only waits for kswapd when under allocation | |
2615 | * congestion. So as a result __GFP_RECLAIM is | |
2616 | * unreliable and fails to actually reclaim our | |
2617 | * dirty pages -- unless you try over and over | |
2618 | * again with !__GFP_NORETRY. However, we still | |
2619 | * want to fail this allocation rather than | |
2620 | * trigger the out-of-memory killer and for | |
dbb32956 | 2621 | * this we want __GFP_RETRY_MAYFAIL. |
eaf41801 | 2622 | */ |
dbb32956 | 2623 | gfp |= __GFP_RETRY_MAYFAIL; |
e2273302 | 2624 | } |
4846bf0c CW |
2625 | } while (1); |
2626 | ||
871dfbd6 CW |
2627 | if (!i || |
2628 | sg->length >= max_segment || | |
2629 | page_to_pfn(page) != last_pfn + 1) { | |
a5c08166 | 2630 | if (i) { |
84e8978e | 2631 | sg_page_sizes |= sg->length; |
90797e6d | 2632 | sg = sg_next(sg); |
a5c08166 | 2633 | } |
90797e6d ID |
2634 | st->nents++; |
2635 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2636 | } else { | |
2637 | sg->length += PAGE_SIZE; | |
2638 | } | |
2639 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2640 | |
2641 | /* Check that the i965g/gm workaround works. */ | |
2642 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2643 | } |
a5c08166 | 2644 | if (sg) { /* loop terminated early; short sg table */ |
84e8978e | 2645 | sg_page_sizes |= sg->length; |
426729dc | 2646 | sg_mark_end(sg); |
a5c08166 | 2647 | } |
74ce6b6c | 2648 | |
0c40ce13 TU |
2649 | /* Trim unused sg entries to avoid wasting memory. */ |
2650 | i915_sg_trim(st); | |
2651 | ||
03ac84f1 | 2652 | ret = i915_gem_gtt_prepare_pages(obj, st); |
d766ef53 | 2653 | if (ret) { |
e0ff7a7c CW |
2654 | /* |
2655 | * DMA remapping failed? One possible cause is that | |
d766ef53 CW |
2656 | * it could not reserve enough large entries, asking |
2657 | * for PAGE_SIZE chunks instead may be helpful. | |
2658 | */ | |
2659 | if (max_segment > PAGE_SIZE) { | |
2660 | for_each_sgt_page(page, sgt_iter, st) | |
2661 | put_page(page); | |
2662 | sg_free_table(st); | |
2663 | ||
2664 | max_segment = PAGE_SIZE; | |
2665 | goto rebuild_st; | |
2666 | } else { | |
2667 | dev_warn(&dev_priv->drm.pdev->dev, | |
2668 | "Failed to DMA remap %lu pages\n", | |
2669 | page_count); | |
2670 | goto err_pages; | |
2671 | } | |
2672 | } | |
e2273302 | 2673 | |
6dacfd2f | 2674 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2675 | i915_gem_object_do_bit_17_swizzle(obj, st); |
e5281ccd | 2676 | |
84e8978e | 2677 | __i915_gem_object_set_pages(obj, st, sg_page_sizes); |
b91b09ee MA |
2678 | |
2679 | return 0; | |
e5281ccd | 2680 | |
b17993b7 | 2681 | err_sg: |
90797e6d | 2682 | sg_mark_end(sg); |
b17993b7 | 2683 | err_pages: |
85d1225e DG |
2684 | for_each_sgt_page(page, sgt_iter, st) |
2685 | put_page(page); | |
9da3da66 CW |
2686 | sg_free_table(st); |
2687 | kfree(st); | |
0820baf3 | 2688 | |
e0ff7a7c CW |
2689 | /* |
2690 | * shmemfs first checks if there is enough memory to allocate the page | |
0820baf3 CW |
2691 | * and reports ENOSPC should there be insufficient, along with the usual |
2692 | * ENOMEM for a genuine allocation failure. | |
2693 | * | |
2694 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2695 | * space and so want to translate the error from shmemfs back to our | |
2696 | * usual understanding of ENOMEM. | |
2697 | */ | |
e2273302 ID |
2698 | if (ret == -ENOSPC) |
2699 | ret = -ENOMEM; | |
2700 | ||
b91b09ee | 2701 | return ret; |
03ac84f1 CW |
2702 | } |
2703 | ||
2704 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, | |
a5c08166 | 2705 | struct sg_table *pages, |
84e8978e | 2706 | unsigned int sg_page_sizes) |
03ac84f1 | 2707 | { |
a5c08166 MA |
2708 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
2709 | unsigned long supported = INTEL_INFO(i915)->page_sizes; | |
2710 | int i; | |
2711 | ||
1233e2db | 2712 | lockdep_assert_held(&obj->mm.lock); |
03ac84f1 CW |
2713 | |
2714 | obj->mm.get_page.sg_pos = pages->sgl; | |
2715 | obj->mm.get_page.sg_idx = 0; | |
2716 | ||
2717 | obj->mm.pages = pages; | |
2c3a3f44 CW |
2718 | |
2719 | if (i915_gem_object_is_tiled(obj) && | |
f2123818 | 2720 | i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
2c3a3f44 CW |
2721 | GEM_BUG_ON(obj->mm.quirked); |
2722 | __i915_gem_object_pin_pages(obj); | |
2723 | obj->mm.quirked = true; | |
2724 | } | |
a5c08166 | 2725 | |
84e8978e MA |
2726 | GEM_BUG_ON(!sg_page_sizes); |
2727 | obj->mm.page_sizes.phys = sg_page_sizes; | |
a5c08166 MA |
2728 | |
2729 | /* | |
84e8978e MA |
2730 | * Calculate the supported page-sizes which fit into the given |
2731 | * sg_page_sizes. This will give us the page-sizes which we may be able | |
2732 | * to use opportunistically when later inserting into the GTT. For | |
2733 | * example if phys=2G, then in theory we should be able to use 1G, 2M, | |
2734 | * 64K or 4K pages, although in practice this will depend on a number of | |
2735 | * other factors. | |
a5c08166 MA |
2736 | */ |
2737 | obj->mm.page_sizes.sg = 0; | |
2738 | for_each_set_bit(i, &supported, ilog2(I915_GTT_MAX_PAGE_SIZE) + 1) { | |
2739 | if (obj->mm.page_sizes.phys & ~0u << i) | |
2740 | obj->mm.page_sizes.sg |= BIT(i); | |
2741 | } | |
a5c08166 | 2742 | GEM_BUG_ON(!HAS_PAGE_SIZES(i915, obj->mm.page_sizes.sg)); |
f2123818 CW |
2743 | |
2744 | spin_lock(&i915->mm.obj_lock); | |
2745 | list_add(&obj->mm.link, &i915->mm.unbound_list); | |
2746 | spin_unlock(&i915->mm.obj_lock); | |
03ac84f1 CW |
2747 | } |
2748 | ||
2749 | static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2750 | { | |
b91b09ee | 2751 | int err; |
03ac84f1 CW |
2752 | |
2753 | if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { | |
2754 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); | |
2755 | return -EFAULT; | |
2756 | } | |
2757 | ||
b91b09ee | 2758 | err = obj->ops->get_pages(obj); |
b65a9b98 | 2759 | GEM_BUG_ON(!err && !i915_gem_object_has_pages(obj)); |
03ac84f1 | 2760 | |
b91b09ee | 2761 | return err; |
673a394b EA |
2762 | } |
2763 | ||
37e680a1 | 2764 | /* Ensure that the associated pages are gathered from the backing storage |
1233e2db | 2765 | * and pinned into our object. i915_gem_object_pin_pages() may be called |
37e680a1 | 2766 | * multiple times before they are released by a single call to |
1233e2db | 2767 | * i915_gem_object_unpin_pages() - once the pages are no longer referenced |
37e680a1 CW |
2768 | * either as a result of memory pressure (reaping pages under the shrinker) |
2769 | * or as the object is itself released. | |
2770 | */ | |
a4f5ea64 | 2771 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
37e680a1 | 2772 | { |
03ac84f1 | 2773 | int err; |
37e680a1 | 2774 | |
1233e2db CW |
2775 | err = mutex_lock_interruptible(&obj->mm.lock); |
2776 | if (err) | |
2777 | return err; | |
4c7d62c6 | 2778 | |
f1fa4f44 | 2779 | if (unlikely(!i915_gem_object_has_pages(obj))) { |
88c880bb CW |
2780 | GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); |
2781 | ||
2c3a3f44 CW |
2782 | err = ____i915_gem_object_get_pages(obj); |
2783 | if (err) | |
2784 | goto unlock; | |
37e680a1 | 2785 | |
2c3a3f44 CW |
2786 | smp_mb__before_atomic(); |
2787 | } | |
2788 | atomic_inc(&obj->mm.pages_pin_count); | |
ee286370 | 2789 | |
1233e2db CW |
2790 | unlock: |
2791 | mutex_unlock(&obj->mm.lock); | |
03ac84f1 | 2792 | return err; |
673a394b EA |
2793 | } |
2794 | ||
dd6034c6 | 2795 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
d31d7cb1 CW |
2796 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, |
2797 | enum i915_map_type type) | |
dd6034c6 DG |
2798 | { |
2799 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
a4f5ea64 | 2800 | struct sg_table *sgt = obj->mm.pages; |
85d1225e DG |
2801 | struct sgt_iter sgt_iter; |
2802 | struct page *page; | |
b338fa47 DG |
2803 | struct page *stack_pages[32]; |
2804 | struct page **pages = stack_pages; | |
dd6034c6 | 2805 | unsigned long i = 0; |
d31d7cb1 | 2806 | pgprot_t pgprot; |
dd6034c6 DG |
2807 | void *addr; |
2808 | ||
2809 | /* A single page can always be kmapped */ | |
d31d7cb1 | 2810 | if (n_pages == 1 && type == I915_MAP_WB) |
dd6034c6 DG |
2811 | return kmap(sg_page(sgt->sgl)); |
2812 | ||
b338fa47 DG |
2813 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2814 | /* Too big for stack -- allocate temporary array instead */ | |
0ee931c4 | 2815 | pages = kvmalloc_array(n_pages, sizeof(*pages), GFP_KERNEL); |
b338fa47 DG |
2816 | if (!pages) |
2817 | return NULL; | |
2818 | } | |
dd6034c6 | 2819 | |
85d1225e DG |
2820 | for_each_sgt_page(page, sgt_iter, sgt) |
2821 | pages[i++] = page; | |
dd6034c6 DG |
2822 | |
2823 | /* Check that we have the expected number of pages */ | |
2824 | GEM_BUG_ON(i != n_pages); | |
2825 | ||
d31d7cb1 | 2826 | switch (type) { |
a575c676 CW |
2827 | default: |
2828 | MISSING_CASE(type); | |
2829 | /* fallthrough to use PAGE_KERNEL anyway */ | |
d31d7cb1 CW |
2830 | case I915_MAP_WB: |
2831 | pgprot = PAGE_KERNEL; | |
2832 | break; | |
2833 | case I915_MAP_WC: | |
2834 | pgprot = pgprot_writecombine(PAGE_KERNEL_IO); | |
2835 | break; | |
2836 | } | |
2837 | addr = vmap(pages, n_pages, 0, pgprot); | |
dd6034c6 | 2838 | |
b338fa47 | 2839 | if (pages != stack_pages) |
2098105e | 2840 | kvfree(pages); |
dd6034c6 DG |
2841 | |
2842 | return addr; | |
2843 | } | |
2844 | ||
2845 | /* get, pin, and map the pages of the object into kernel space */ | |
d31d7cb1 CW |
2846 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
2847 | enum i915_map_type type) | |
0a798eb9 | 2848 | { |
d31d7cb1 CW |
2849 | enum i915_map_type has_type; |
2850 | bool pinned; | |
2851 | void *ptr; | |
0a798eb9 CW |
2852 | int ret; |
2853 | ||
a03f395a TZ |
2854 | if (unlikely(!i915_gem_object_has_struct_page(obj))) |
2855 | return ERR_PTR(-ENXIO); | |
0a798eb9 | 2856 | |
1233e2db | 2857 | ret = mutex_lock_interruptible(&obj->mm.lock); |
0a798eb9 CW |
2858 | if (ret) |
2859 | return ERR_PTR(ret); | |
2860 | ||
a575c676 CW |
2861 | pinned = !(type & I915_MAP_OVERRIDE); |
2862 | type &= ~I915_MAP_OVERRIDE; | |
2863 | ||
1233e2db | 2864 | if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) { |
f1fa4f44 | 2865 | if (unlikely(!i915_gem_object_has_pages(obj))) { |
88c880bb CW |
2866 | GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); |
2867 | ||
2c3a3f44 CW |
2868 | ret = ____i915_gem_object_get_pages(obj); |
2869 | if (ret) | |
2870 | goto err_unlock; | |
1233e2db | 2871 | |
2c3a3f44 CW |
2872 | smp_mb__before_atomic(); |
2873 | } | |
2874 | atomic_inc(&obj->mm.pages_pin_count); | |
1233e2db CW |
2875 | pinned = false; |
2876 | } | |
f1fa4f44 | 2877 | GEM_BUG_ON(!i915_gem_object_has_pages(obj)); |
0a798eb9 | 2878 | |
0ce81788 | 2879 | ptr = page_unpack_bits(obj->mm.mapping, &has_type); |
d31d7cb1 CW |
2880 | if (ptr && has_type != type) { |
2881 | if (pinned) { | |
2882 | ret = -EBUSY; | |
1233e2db | 2883 | goto err_unpin; |
0a798eb9 | 2884 | } |
d31d7cb1 CW |
2885 | |
2886 | if (is_vmalloc_addr(ptr)) | |
2887 | vunmap(ptr); | |
2888 | else | |
2889 | kunmap(kmap_to_page(ptr)); | |
2890 | ||
a4f5ea64 | 2891 | ptr = obj->mm.mapping = NULL; |
0a798eb9 CW |
2892 | } |
2893 | ||
d31d7cb1 CW |
2894 | if (!ptr) { |
2895 | ptr = i915_gem_object_map(obj, type); | |
2896 | if (!ptr) { | |
2897 | ret = -ENOMEM; | |
1233e2db | 2898 | goto err_unpin; |
d31d7cb1 CW |
2899 | } |
2900 | ||
0ce81788 | 2901 | obj->mm.mapping = page_pack_bits(ptr, type); |
d31d7cb1 CW |
2902 | } |
2903 | ||
1233e2db CW |
2904 | out_unlock: |
2905 | mutex_unlock(&obj->mm.lock); | |
d31d7cb1 CW |
2906 | return ptr; |
2907 | ||
1233e2db CW |
2908 | err_unpin: |
2909 | atomic_dec(&obj->mm.pages_pin_count); | |
2910 | err_unlock: | |
2911 | ptr = ERR_PTR(ret); | |
2912 | goto out_unlock; | |
0a798eb9 CW |
2913 | } |
2914 | ||
7c55e2c5 CW |
2915 | static int |
2916 | i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj, | |
2917 | const struct drm_i915_gem_pwrite *arg) | |
2918 | { | |
2919 | struct address_space *mapping = obj->base.filp->f_mapping; | |
2920 | char __user *user_data = u64_to_user_ptr(arg->data_ptr); | |
2921 | u64 remain, offset; | |
2922 | unsigned int pg; | |
2923 | ||
2924 | /* Before we instantiate/pin the backing store for our use, we | |
2925 | * can prepopulate the shmemfs filp efficiently using a write into | |
2926 | * the pagecache. We avoid the penalty of instantiating all the | |
2927 | * pages, important if the user is just writing to a few and never | |
2928 | * uses the object on the GPU, and using a direct write into shmemfs | |
2929 | * allows it to avoid the cost of retrieving a page (either swapin | |
2930 | * or clearing-before-use) before it is overwritten. | |
2931 | */ | |
f1fa4f44 | 2932 | if (i915_gem_object_has_pages(obj)) |
7c55e2c5 CW |
2933 | return -ENODEV; |
2934 | ||
a6d65e45 CW |
2935 | if (obj->mm.madv != I915_MADV_WILLNEED) |
2936 | return -EFAULT; | |
2937 | ||
7c55e2c5 CW |
2938 | /* Before the pages are instantiated the object is treated as being |
2939 | * in the CPU domain. The pages will be clflushed as required before | |
2940 | * use, and we can freely write into the pages directly. If userspace | |
2941 | * races pwrite with any other operation; corruption will ensue - | |
2942 | * that is userspace's prerogative! | |
2943 | */ | |
2944 | ||
2945 | remain = arg->size; | |
2946 | offset = arg->offset; | |
2947 | pg = offset_in_page(offset); | |
2948 | ||
2949 | do { | |
2950 | unsigned int len, unwritten; | |
2951 | struct page *page; | |
2952 | void *data, *vaddr; | |
2953 | int err; | |
2954 | ||
2955 | len = PAGE_SIZE - pg; | |
2956 | if (len > remain) | |
2957 | len = remain; | |
2958 | ||
2959 | err = pagecache_write_begin(obj->base.filp, mapping, | |
2960 | offset, len, 0, | |
2961 | &page, &data); | |
2962 | if (err < 0) | |
2963 | return err; | |
2964 | ||
2965 | vaddr = kmap(page); | |
2966 | unwritten = copy_from_user(vaddr + pg, user_data, len); | |
2967 | kunmap(page); | |
2968 | ||
2969 | err = pagecache_write_end(obj->base.filp, mapping, | |
2970 | offset, len, len - unwritten, | |
2971 | page, data); | |
2972 | if (err < 0) | |
2973 | return err; | |
2974 | ||
2975 | if (unwritten) | |
2976 | return -EFAULT; | |
2977 | ||
2978 | remain -= len; | |
2979 | user_data += len; | |
2980 | offset += len; | |
2981 | pg = 0; | |
2982 | } while (remain); | |
2983 | ||
2984 | return 0; | |
2985 | } | |
2986 | ||
14921f3c MK |
2987 | static void i915_gem_client_mark_guilty(struct drm_i915_file_private *file_priv, |
2988 | const struct i915_gem_context *ctx) | |
2989 | { | |
2990 | unsigned int score; | |
2991 | unsigned long prev_hang; | |
2992 | ||
2993 | if (i915_gem_context_is_banned(ctx)) | |
2994 | score = I915_CLIENT_SCORE_CONTEXT_BAN; | |
2995 | else | |
2996 | score = 0; | |
2997 | ||
2998 | prev_hang = xchg(&file_priv->hang_timestamp, jiffies); | |
2999 | if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES)) | |
3000 | score += I915_CLIENT_SCORE_HANG_FAST; | |
3001 | ||
3002 | if (score) { | |
3003 | atomic_add(score, &file_priv->ban_score); | |
3004 | ||
3005 | DRM_DEBUG_DRIVER("client %s: gained %u ban score, now %u\n", | |
3006 | ctx->name, score, | |
3007 | atomic_read(&file_priv->ban_score)); | |
3008 | } | |
3009 | } | |
3010 | ||
e5e1fc47 | 3011 | static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx) |
aa60c664 | 3012 | { |
14921f3c MK |
3013 | unsigned int score; |
3014 | bool banned, bannable; | |
b083a087 | 3015 | |
77b25a97 | 3016 | atomic_inc(&ctx->guilty_count); |
b083a087 | 3017 | |
14921f3c MK |
3018 | bannable = i915_gem_context_is_bannable(ctx); |
3019 | score = atomic_add_return(CONTEXT_SCORE_GUILTY, &ctx->ban_score); | |
3020 | banned = score >= CONTEXT_SCORE_BAN_THRESHOLD; | |
24eae08d | 3021 | |
14921f3c MK |
3022 | /* Cool contexts don't accumulate client ban score */ |
3023 | if (!bannable) | |
b083a087 MK |
3024 | return; |
3025 | ||
bcc2661e CW |
3026 | if (banned) { |
3027 | DRM_DEBUG_DRIVER("context %s: guilty %d, score %u, banned\n", | |
3028 | ctx->name, atomic_read(&ctx->guilty_count), | |
3029 | score); | |
14921f3c | 3030 | i915_gem_context_set_banned(ctx); |
bcc2661e | 3031 | } |
14921f3c MK |
3032 | |
3033 | if (!IS_ERR_OR_NULL(ctx->file_priv)) | |
3034 | i915_gem_client_mark_guilty(ctx->file_priv, ctx); | |
e5e1fc47 MK |
3035 | } |
3036 | ||
3037 | static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx) | |
3038 | { | |
77b25a97 | 3039 | atomic_inc(&ctx->active_count); |
aa60c664 MK |
3040 | } |
3041 | ||
e61e0f51 | 3042 | struct i915_request * |
0bc40be8 | 3043 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 3044 | { |
e61e0f51 | 3045 | struct i915_request *request, *active = NULL; |
754c9fd5 | 3046 | unsigned long flags; |
4db080f9 | 3047 | |
cc7cc534 CW |
3048 | /* |
3049 | * We are called by the error capture, reset and to dump engine | |
3050 | * state at random points in time. In particular, note that neither is | |
3051 | * crucially ordered with an interrupt. After a hang, the GPU is dead | |
3052 | * and we assume that no more writes can happen (we waited long enough | |
3053 | * for all writes that were in transaction to be flushed) - adding an | |
f69a02c9 CW |
3054 | * extra delay for a recent interrupt is pointless. Hence, we do |
3055 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
cc7cc534 CW |
3056 | * At all other times, we must assume the GPU is still running, but |
3057 | * we only care about the snapshot of this moment. | |
f69a02c9 | 3058 | */ |
a89d1f92 CW |
3059 | spin_lock_irqsave(&engine->timeline.lock, flags); |
3060 | list_for_each_entry(request, &engine->timeline.requests, link) { | |
e61e0f51 | 3061 | if (__i915_request_completed(request, request->global_seqno)) |
4db080f9 | 3062 | continue; |
aa60c664 | 3063 | |
754c9fd5 CW |
3064 | active = request; |
3065 | break; | |
4db080f9 | 3066 | } |
a89d1f92 | 3067 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
b6b0fac0 | 3068 | |
754c9fd5 | 3069 | return active; |
b6b0fac0 MK |
3070 | } |
3071 | ||
a1ef70e1 MT |
3072 | /* |
3073 | * Ensure irq handler finishes, and not run again. | |
3074 | * Also return the active request so that we only search for it once. | |
3075 | */ | |
e61e0f51 | 3076 | struct i915_request * |
a1ef70e1 MT |
3077 | i915_gem_reset_prepare_engine(struct intel_engine_cs *engine) |
3078 | { | |
5adfb772 | 3079 | struct i915_request *request; |
a1ef70e1 | 3080 | |
1749d90f CW |
3081 | /* |
3082 | * During the reset sequence, we must prevent the engine from | |
3083 | * entering RC6. As the context state is undefined until we restart | |
3084 | * the engine, if it does enter RC6 during the reset, the state | |
3085 | * written to the powercontext is undefined and so we may lose | |
3086 | * GPU state upon resume, i.e. fail to restart after a reset. | |
3087 | */ | |
3088 | intel_uncore_forcewake_get(engine->i915, FORCEWAKE_ALL); | |
3089 | ||
5adfb772 | 3090 | request = engine->reset.prepare(engine); |
d1d1ebf4 CW |
3091 | if (request && request->fence.error == -EIO) |
3092 | request = ERR_PTR(-EIO); /* Previous reset failed! */ | |
a1ef70e1 MT |
3093 | |
3094 | return request; | |
3095 | } | |
3096 | ||
0e178aef | 3097 | int i915_gem_reset_prepare(struct drm_i915_private *dev_priv) |
4c965543 CW |
3098 | { |
3099 | struct intel_engine_cs *engine; | |
e61e0f51 | 3100 | struct i915_request *request; |
4c965543 | 3101 | enum intel_engine_id id; |
0e178aef | 3102 | int err = 0; |
4c965543 | 3103 | |
0e178aef | 3104 | for_each_engine(engine, dev_priv, id) { |
a1ef70e1 MT |
3105 | request = i915_gem_reset_prepare_engine(engine); |
3106 | if (IS_ERR(request)) { | |
3107 | err = PTR_ERR(request); | |
3108 | continue; | |
0e178aef | 3109 | } |
c64992e0 MT |
3110 | |
3111 | engine->hangcheck.active_request = request; | |
0e178aef CW |
3112 | } |
3113 | ||
4c965543 | 3114 | i915_gem_revoke_fences(dev_priv); |
c37d5728 | 3115 | intel_uc_sanitize(dev_priv); |
0e178aef CW |
3116 | |
3117 | return err; | |
4c965543 CW |
3118 | } |
3119 | ||
e61e0f51 | 3120 | static void engine_skip_context(struct i915_request *request) |
36193acd MK |
3121 | { |
3122 | struct intel_engine_cs *engine = request->engine; | |
4e0d64db | 3123 | struct i915_gem_context *hung_ctx = request->gem_context; |
a89d1f92 | 3124 | struct i915_timeline *timeline = request->timeline; |
36193acd MK |
3125 | unsigned long flags; |
3126 | ||
a89d1f92 | 3127 | GEM_BUG_ON(timeline == &engine->timeline); |
36193acd | 3128 | |
a89d1f92 | 3129 | spin_lock_irqsave(&engine->timeline.lock, flags); |
890fd185 | 3130 | spin_lock(&timeline->lock); |
36193acd | 3131 | |
a89d1f92 | 3132 | list_for_each_entry_continue(request, &engine->timeline.requests, link) |
4e0d64db | 3133 | if (request->gem_context == hung_ctx) |
6dd7526f | 3134 | i915_request_skip(request, -EIO); |
36193acd MK |
3135 | |
3136 | list_for_each_entry(request, &timeline->requests, link) | |
6dd7526f | 3137 | i915_request_skip(request, -EIO); |
36193acd MK |
3138 | |
3139 | spin_unlock(&timeline->lock); | |
a89d1f92 | 3140 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
36193acd MK |
3141 | } |
3142 | ||
d1d1ebf4 | 3143 | /* Returns the request if it was guilty of the hang */ |
e61e0f51 | 3144 | static struct i915_request * |
d1d1ebf4 | 3145 | i915_gem_reset_request(struct intel_engine_cs *engine, |
bba0869b CW |
3146 | struct i915_request *request, |
3147 | bool stalled) | |
61da5362 | 3148 | { |
71895a08 MK |
3149 | /* The guilty request will get skipped on a hung engine. |
3150 | * | |
3151 | * Users of client default contexts do not rely on logical | |
3152 | * state preserved between batches so it is safe to execute | |
3153 | * queued requests following the hang. Non default contexts | |
3154 | * rely on preserved state, so skipping a batch loses the | |
3155 | * evolution of the state and it needs to be considered corrupted. | |
3156 | * Executing more queued batches on top of corrupted state is | |
3157 | * risky. But we take the risk by trying to advance through | |
3158 | * the queued requests in order to make the client behaviour | |
3159 | * more predictable around resets, by not throwing away random | |
3160 | * amount of batches it has prepared for execution. Sophisticated | |
3161 | * clients can use gem_reset_stats_ioctl and dma fence status | |
3162 | * (exported via sync_file info ioctl on explicit fences) to observe | |
3163 | * when it loses the context state and should rebuild accordingly. | |
3164 | * | |
3165 | * The context ban, and ultimately the client ban, mechanism are safety | |
3166 | * valves if client submission ends up resulting in nothing more than | |
3167 | * subsequent hangs. | |
3168 | */ | |
3169 | ||
bba0869b CW |
3170 | if (i915_request_completed(request)) { |
3171 | GEM_TRACE("%s pardoned global=%d (fence %llx:%d), current %d\n", | |
3172 | engine->name, request->global_seqno, | |
3173 | request->fence.context, request->fence.seqno, | |
3174 | intel_engine_get_seqno(engine)); | |
3175 | stalled = false; | |
3176 | } | |
3177 | ||
3178 | if (stalled) { | |
4e0d64db | 3179 | i915_gem_context_mark_guilty(request->gem_context); |
6dd7526f | 3180 | i915_request_skip(request, -EIO); |
d1d1ebf4 CW |
3181 | |
3182 | /* If this context is now banned, skip all pending requests. */ | |
4e0d64db | 3183 | if (i915_gem_context_is_banned(request->gem_context)) |
d1d1ebf4 | 3184 | engine_skip_context(request); |
61da5362 | 3185 | } else { |
d1d1ebf4 CW |
3186 | /* |
3187 | * Since this is not the hung engine, it may have advanced | |
3188 | * since the hang declaration. Double check by refinding | |
3189 | * the active request at the time of the reset. | |
3190 | */ | |
3191 | request = i915_gem_find_active_request(engine); | |
3192 | if (request) { | |
042ed2db CW |
3193 | unsigned long flags; |
3194 | ||
4e0d64db | 3195 | i915_gem_context_mark_innocent(request->gem_context); |
d1d1ebf4 CW |
3196 | dma_fence_set_error(&request->fence, -EAGAIN); |
3197 | ||
3198 | /* Rewind the engine to replay the incomplete rq */ | |
042ed2db | 3199 | spin_lock_irqsave(&engine->timeline.lock, flags); |
d1d1ebf4 | 3200 | request = list_prev_entry(request, link); |
a89d1f92 | 3201 | if (&request->link == &engine->timeline.requests) |
d1d1ebf4 | 3202 | request = NULL; |
042ed2db | 3203 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
d1d1ebf4 | 3204 | } |
61da5362 MK |
3205 | } |
3206 | ||
d1d1ebf4 | 3207 | return request; |
61da5362 MK |
3208 | } |
3209 | ||
a1ef70e1 | 3210 | void i915_gem_reset_engine(struct intel_engine_cs *engine, |
bba0869b CW |
3211 | struct i915_request *request, |
3212 | bool stalled) | |
b6b0fac0 | 3213 | { |
fcb1de54 CW |
3214 | /* |
3215 | * Make sure this write is visible before we re-enable the interrupt | |
3216 | * handlers on another CPU, as tasklet_enable() resolves to just | |
3217 | * a compiler barrier which is insufficient for our purpose here. | |
3218 | */ | |
3219 | smp_store_mb(engine->irq_posted, 0); | |
ed454f2c | 3220 | |
d1d1ebf4 | 3221 | if (request) |
bba0869b | 3222 | request = i915_gem_reset_request(engine, request, stalled); |
d1d1ebf4 | 3223 | |
821ed7df | 3224 | /* Setup the CS to resume from the breadcrumb of the hung request */ |
5adfb772 | 3225 | engine->reset.reset(engine, request); |
4db080f9 | 3226 | } |
aa60c664 | 3227 | |
d0667e9c CW |
3228 | void i915_gem_reset(struct drm_i915_private *dev_priv, |
3229 | unsigned int stalled_mask) | |
4db080f9 | 3230 | { |
821ed7df | 3231 | struct intel_engine_cs *engine; |
3b3f1650 | 3232 | enum intel_engine_id id; |
608c1a52 | 3233 | |
4c7d62c6 CW |
3234 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
3235 | ||
e61e0f51 | 3236 | i915_retire_requests(dev_priv); |
821ed7df | 3237 | |
2ae55738 | 3238 | for_each_engine(engine, dev_priv, id) { |
1fc44d9b | 3239 | struct intel_context *ce; |
2ae55738 | 3240 | |
bba0869b CW |
3241 | i915_gem_reset_engine(engine, |
3242 | engine->hangcheck.active_request, | |
d0667e9c | 3243 | stalled_mask & ENGINE_MASK(id)); |
1fc44d9b CW |
3244 | ce = fetch_and_zero(&engine->last_retired_context); |
3245 | if (ce) | |
3246 | intel_context_unpin(ce); | |
7b6da818 CW |
3247 | |
3248 | /* | |
3249 | * Ostensibily, we always want a context loaded for powersaving, | |
3250 | * so if the engine is idle after the reset, send a request | |
3251 | * to load our scratch kernel_context. | |
3252 | * | |
3253 | * More mysteriously, if we leave the engine idle after a reset, | |
3254 | * the next userspace batch may hang, with what appears to be | |
3255 | * an incoherent read by the CS (presumably stale TLB). An | |
3256 | * empty request appears sufficient to paper over the glitch. | |
3257 | */ | |
01b8fdc5 | 3258 | if (intel_engine_is_idle(engine)) { |
e61e0f51 | 3259 | struct i915_request *rq; |
7b6da818 | 3260 | |
e61e0f51 CW |
3261 | rq = i915_request_alloc(engine, |
3262 | dev_priv->kernel_context); | |
7b6da818 | 3263 | if (!IS_ERR(rq)) |
697b9a87 | 3264 | i915_request_add(rq); |
7b6da818 | 3265 | } |
2ae55738 | 3266 | } |
821ed7df | 3267 | |
4362f4f6 | 3268 | i915_gem_restore_fences(dev_priv); |
821ed7df CW |
3269 | } |
3270 | ||
a1ef70e1 MT |
3271 | void i915_gem_reset_finish_engine(struct intel_engine_cs *engine) |
3272 | { | |
5adfb772 CW |
3273 | engine->reset.finish(engine); |
3274 | ||
1749d90f | 3275 | intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL); |
a1ef70e1 MT |
3276 | } |
3277 | ||
d8027093 CW |
3278 | void i915_gem_reset_finish(struct drm_i915_private *dev_priv) |
3279 | { | |
1f7b847d CW |
3280 | struct intel_engine_cs *engine; |
3281 | enum intel_engine_id id; | |
3282 | ||
d8027093 | 3283 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
1f7b847d | 3284 | |
fe3288b5 | 3285 | for_each_engine(engine, dev_priv, id) { |
c64992e0 | 3286 | engine->hangcheck.active_request = NULL; |
a1ef70e1 | 3287 | i915_gem_reset_finish_engine(engine); |
fe3288b5 | 3288 | } |
d8027093 CW |
3289 | } |
3290 | ||
e61e0f51 | 3291 | static void nop_submit_request(struct i915_request *request) |
af7a8ffa | 3292 | { |
d9b13c4d CW |
3293 | GEM_TRACE("%s fence %llx:%d -> -EIO\n", |
3294 | request->engine->name, | |
3295 | request->fence.context, request->fence.seqno); | |
af7a8ffa DV |
3296 | dma_fence_set_error(&request->fence, -EIO); |
3297 | ||
e61e0f51 | 3298 | i915_request_submit(request); |
af7a8ffa DV |
3299 | } |
3300 | ||
e61e0f51 | 3301 | static void nop_complete_submit_request(struct i915_request *request) |
821ed7df | 3302 | { |
8d550824 CW |
3303 | unsigned long flags; |
3304 | ||
d9b13c4d CW |
3305 | GEM_TRACE("%s fence %llx:%d -> -EIO\n", |
3306 | request->engine->name, | |
3307 | request->fence.context, request->fence.seqno); | |
3cd9442f | 3308 | dma_fence_set_error(&request->fence, -EIO); |
8d550824 | 3309 | |
a89d1f92 | 3310 | spin_lock_irqsave(&request->engine->timeline.lock, flags); |
e61e0f51 | 3311 | __i915_request_submit(request); |
3dcf93f7 | 3312 | intel_engine_init_global_seqno(request->engine, request->global_seqno); |
a89d1f92 | 3313 | spin_unlock_irqrestore(&request->engine->timeline.lock, flags); |
821ed7df CW |
3314 | } |
3315 | ||
af7a8ffa | 3316 | void i915_gem_set_wedged(struct drm_i915_private *i915) |
821ed7df | 3317 | { |
af7a8ffa DV |
3318 | struct intel_engine_cs *engine; |
3319 | enum intel_engine_id id; | |
3320 | ||
d9b13c4d CW |
3321 | GEM_TRACE("start\n"); |
3322 | ||
7f961d79 | 3323 | if (GEM_SHOW_DEBUG()) { |
559e040f CW |
3324 | struct drm_printer p = drm_debug_printer(__func__); |
3325 | ||
3326 | for_each_engine(engine, i915, id) | |
3327 | intel_engine_dump(engine, &p, "%s\n", engine->name); | |
3328 | } | |
3329 | ||
3970c65c CW |
3330 | if (test_and_set_bit(I915_WEDGED, &i915->gpu_error.flags)) |
3331 | goto out; | |
0d73e7a0 | 3332 | |
af7a8ffa DV |
3333 | /* |
3334 | * First, stop submission to hw, but do not yet complete requests by | |
3335 | * rolling the global seqno forward (since this would complete requests | |
3336 | * for which we haven't set the fence error to EIO yet). | |
3337 | */ | |
963ddd63 CW |
3338 | for_each_engine(engine, i915, id) { |
3339 | i915_gem_reset_prepare_engine(engine); | |
47650db0 | 3340 | |
af7a8ffa | 3341 | engine->submit_request = nop_submit_request; |
47650db0 | 3342 | engine->schedule = NULL; |
963ddd63 | 3343 | } |
47650db0 | 3344 | i915->caps.scheduler = 0; |
af7a8ffa | 3345 | |
ac697ae8 | 3346 | /* Even if the GPU reset fails, it should still stop the engines */ |
ec5b65a9 CW |
3347 | if (INTEL_GEN(i915) >= 5) |
3348 | intel_gpu_reset(i915, ALL_ENGINES); | |
ac697ae8 | 3349 | |
af7a8ffa DV |
3350 | /* |
3351 | * Make sure no one is running the old callback before we proceed with | |
3352 | * cancelling requests and resetting the completion tracking. Otherwise | |
3353 | * we might submit a request to the hardware which never completes. | |
20e4933c | 3354 | */ |
af7a8ffa | 3355 | synchronize_rcu(); |
70c2a24d | 3356 | |
af7a8ffa DV |
3357 | for_each_engine(engine, i915, id) { |
3358 | /* Mark all executing requests as skipped */ | |
3359 | engine->cancel_requests(engine); | |
5e32d748 | 3360 | |
af7a8ffa DV |
3361 | /* |
3362 | * Only once we've force-cancelled all in-flight requests can we | |
3363 | * start to complete all requests. | |
3364 | */ | |
3365 | engine->submit_request = nop_complete_submit_request; | |
3366 | } | |
3367 | ||
3368 | /* | |
3369 | * Make sure no request can slip through without getting completed by | |
3370 | * either this call here to intel_engine_init_global_seqno, or the one | |
3371 | * in nop_complete_submit_request. | |
5e32d748 | 3372 | */ |
af7a8ffa | 3373 | synchronize_rcu(); |
673a394b | 3374 | |
af7a8ffa DV |
3375 | for_each_engine(engine, i915, id) { |
3376 | unsigned long flags; | |
673a394b | 3377 | |
0d73e7a0 CW |
3378 | /* |
3379 | * Mark all pending requests as complete so that any concurrent | |
af7a8ffa DV |
3380 | * (lockless) lookup doesn't try and wait upon the request as we |
3381 | * reset it. | |
3382 | */ | |
a89d1f92 | 3383 | spin_lock_irqsave(&engine->timeline.lock, flags); |
af7a8ffa DV |
3384 | intel_engine_init_global_seqno(engine, |
3385 | intel_engine_last_submit(engine)); | |
a89d1f92 | 3386 | spin_unlock_irqrestore(&engine->timeline.lock, flags); |
963ddd63 CW |
3387 | |
3388 | i915_gem_reset_finish_engine(engine); | |
af7a8ffa | 3389 | } |
20e4933c | 3390 | |
3970c65c | 3391 | out: |
d9b13c4d CW |
3392 | GEM_TRACE("end\n"); |
3393 | ||
3d7adbbf | 3394 | wake_up_all(&i915->gpu_error.reset_queue); |
673a394b EA |
3395 | } |
3396 | ||
2e8f9d32 CW |
3397 | bool i915_gem_unset_wedged(struct drm_i915_private *i915) |
3398 | { | |
a89d1f92 | 3399 | struct i915_timeline *tl; |
2e8f9d32 CW |
3400 | |
3401 | lockdep_assert_held(&i915->drm.struct_mutex); | |
3402 | if (!test_bit(I915_WEDGED, &i915->gpu_error.flags)) | |
3403 | return true; | |
3404 | ||
d9b13c4d CW |
3405 | GEM_TRACE("start\n"); |
3406 | ||
2d4ecace CW |
3407 | /* |
3408 | * Before unwedging, make sure that all pending operations | |
2e8f9d32 CW |
3409 | * are flushed and errored out - we may have requests waiting upon |
3410 | * third party fences. We marked all inflight requests as EIO, and | |
3411 | * every execbuf since returned EIO, for consistency we want all | |
3412 | * the currently pending requests to also be marked as EIO, which | |
3413 | * is done inside our nop_submit_request - and so we must wait. | |
3414 | * | |
3415 | * No more can be submitted until we reset the wedged bit. | |
3416 | */ | |
3417 | list_for_each_entry(tl, &i915->gt.timelines, link) { | |
a89d1f92 | 3418 | struct i915_request *rq; |
2e8f9d32 | 3419 | |
a89d1f92 CW |
3420 | rq = i915_gem_active_peek(&tl->last_request, |
3421 | &i915->drm.struct_mutex); | |
3422 | if (!rq) | |
3423 | continue; | |
2e8f9d32 | 3424 | |
a89d1f92 CW |
3425 | /* |
3426 | * We can't use our normal waiter as we want to | |
3427 | * avoid recursively trying to handle the current | |
3428 | * reset. The basic dma_fence_default_wait() installs | |
3429 | * a callback for dma_fence_signal(), which is | |
3430 | * triggered by our nop handler (indirectly, the | |
3431 | * callback enables the signaler thread which is | |
3432 | * woken by the nop_submit_request() advancing the seqno | |
3433 | * and when the seqno passes the fence, the signaler | |
3434 | * then signals the fence waking us up). | |
3435 | */ | |
3436 | if (dma_fence_default_wait(&rq->fence, true, | |
3437 | MAX_SCHEDULE_TIMEOUT) < 0) | |
3438 | return false; | |
2e8f9d32 | 3439 | } |
2d4ecace CW |
3440 | i915_retire_requests(i915); |
3441 | GEM_BUG_ON(i915->gt.active_requests); | |
2e8f9d32 | 3442 | |
8db601f0 CW |
3443 | if (!intel_gpu_reset(i915, ALL_ENGINES)) |
3444 | intel_engines_sanitize(i915); | |
3445 | ||
2d4ecace CW |
3446 | /* |
3447 | * Undo nop_submit_request. We prevent all new i915 requests from | |
2e8f9d32 CW |
3448 | * being queued (by disallowing execbuf whilst wedged) so having |
3449 | * waited for all active requests above, we know the system is idle | |
3450 | * and do not have to worry about a thread being inside | |
3451 | * engine->submit_request() as we swap over. So unlike installing | |
3452 | * the nop_submit_request on reset, we can do this from normal | |
3453 | * context and do not require stop_machine(). | |
3454 | */ | |
3455 | intel_engines_reset_default_submission(i915); | |
36703e79 | 3456 | i915_gem_contexts_lost(i915); |
2e8f9d32 | 3457 | |
d9b13c4d CW |
3458 | GEM_TRACE("end\n"); |
3459 | ||
2e8f9d32 CW |
3460 | smp_mb__before_atomic(); /* complete takeover before enabling execbuf */ |
3461 | clear_bit(I915_WEDGED, &i915->gpu_error.flags); | |
3462 | ||
3463 | return true; | |
3464 | } | |
3465 | ||
75ef9da2 | 3466 | static void |
673a394b EA |
3467 | i915_gem_retire_work_handler(struct work_struct *work) |
3468 | { | |
b29c19b6 | 3469 | struct drm_i915_private *dev_priv = |
67d97da3 | 3470 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 3471 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 3472 | |
891b48cf | 3473 | /* Come back later if the device is busy... */ |
b29c19b6 | 3474 | if (mutex_trylock(&dev->struct_mutex)) { |
e61e0f51 | 3475 | i915_retire_requests(dev_priv); |
b29c19b6 | 3476 | mutex_unlock(&dev->struct_mutex); |
673a394b | 3477 | } |
67d97da3 | 3478 | |
88923048 CW |
3479 | /* |
3480 | * Keep the retire handler running until we are finally idle. | |
67d97da3 CW |
3481 | * We do not need to do this test under locking as in the worst-case |
3482 | * we queue the retire worker once too often. | |
3483 | */ | |
88923048 | 3484 | if (READ_ONCE(dev_priv->gt.awake)) |
67d97da3 CW |
3485 | queue_delayed_work(dev_priv->wq, |
3486 | &dev_priv->gt.retire_work, | |
bcb45086 | 3487 | round_jiffies_up_relative(HZ)); |
b29c19b6 | 3488 | } |
0a58705b | 3489 | |
84a10749 CW |
3490 | static void shrink_caches(struct drm_i915_private *i915) |
3491 | { | |
3492 | /* | |
3493 | * kmem_cache_shrink() discards empty slabs and reorders partially | |
3494 | * filled slabs to prioritise allocating from the mostly full slabs, | |
3495 | * with the aim of reducing fragmentation. | |
3496 | */ | |
3497 | kmem_cache_shrink(i915->priorities); | |
3498 | kmem_cache_shrink(i915->dependencies); | |
3499 | kmem_cache_shrink(i915->requests); | |
3500 | kmem_cache_shrink(i915->luts); | |
3501 | kmem_cache_shrink(i915->vmas); | |
3502 | kmem_cache_shrink(i915->objects); | |
3503 | } | |
3504 | ||
3505 | struct sleep_rcu_work { | |
3506 | union { | |
3507 | struct rcu_head rcu; | |
3508 | struct work_struct work; | |
3509 | }; | |
3510 | struct drm_i915_private *i915; | |
3511 | unsigned int epoch; | |
3512 | }; | |
3513 | ||
3514 | static inline bool | |
3515 | same_epoch(struct drm_i915_private *i915, unsigned int epoch) | |
3516 | { | |
3517 | /* | |
3518 | * There is a small chance that the epoch wrapped since we started | |
3519 | * sleeping. If we assume that epoch is at least a u32, then it will | |
3520 | * take at least 2^32 * 100ms for it to wrap, or about 326 years. | |
3521 | */ | |
3522 | return epoch == READ_ONCE(i915->gt.epoch); | |
3523 | } | |
3524 | ||
3525 | static void __sleep_work(struct work_struct *work) | |
3526 | { | |
3527 | struct sleep_rcu_work *s = container_of(work, typeof(*s), work); | |
3528 | struct drm_i915_private *i915 = s->i915; | |
3529 | unsigned int epoch = s->epoch; | |
3530 | ||
3531 | kfree(s); | |
3532 | if (same_epoch(i915, epoch)) | |
3533 | shrink_caches(i915); | |
3534 | } | |
3535 | ||
3536 | static void __sleep_rcu(struct rcu_head *rcu) | |
3537 | { | |
3538 | struct sleep_rcu_work *s = container_of(rcu, typeof(*s), rcu); | |
3539 | struct drm_i915_private *i915 = s->i915; | |
3540 | ||
3541 | if (same_epoch(i915, s->epoch)) { | |
3542 | INIT_WORK(&s->work, __sleep_work); | |
3543 | queue_work(i915->wq, &s->work); | |
3544 | } else { | |
3545 | kfree(s); | |
3546 | } | |
3547 | } | |
3548 | ||
5427f207 CW |
3549 | static inline bool |
3550 | new_requests_since_last_retire(const struct drm_i915_private *i915) | |
3551 | { | |
3552 | return (READ_ONCE(i915->gt.active_requests) || | |
3553 | work_pending(&i915->gt.idle_work.work)); | |
3554 | } | |
3555 | ||
1934f5de CW |
3556 | static void assert_kernel_context_is_current(struct drm_i915_private *i915) |
3557 | { | |
3558 | struct intel_engine_cs *engine; | |
3559 | enum intel_engine_id id; | |
3560 | ||
3561 | if (i915_terminally_wedged(&i915->gpu_error)) | |
3562 | return; | |
3563 | ||
3564 | GEM_BUG_ON(i915->gt.active_requests); | |
3565 | for_each_engine(engine, i915, id) { | |
3566 | GEM_BUG_ON(__i915_gem_active_peek(&engine->timeline.last_request)); | |
3567 | GEM_BUG_ON(engine->last_retired_context != | |
3568 | to_intel_context(i915->kernel_context, engine)); | |
3569 | } | |
3570 | } | |
3571 | ||
b29c19b6 CW |
3572 | static void |
3573 | i915_gem_idle_work_handler(struct work_struct *work) | |
3574 | { | |
3575 | struct drm_i915_private *dev_priv = | |
67d97da3 | 3576 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
84a10749 | 3577 | unsigned int epoch = I915_EPOCH_INVALID; |
67d97da3 CW |
3578 | bool rearm_hangcheck; |
3579 | ||
3580 | if (!READ_ONCE(dev_priv->gt.awake)) | |
3581 | return; | |
3582 | ||
4dfacb0b CW |
3583 | if (READ_ONCE(dev_priv->gt.active_requests)) |
3584 | return; | |
3585 | ||
3586 | /* | |
3587 | * Flush out the last user context, leaving only the pinned | |
3588 | * kernel context resident. When we are idling on the kernel_context, | |
3589 | * no more new requests (with a context switch) are emitted and we | |
3590 | * can finally rest. A consequence is that the idle work handler is | |
3591 | * always called at least twice before idling (and if the system is | |
3592 | * idle that implies a round trip through the retire worker). | |
3593 | */ | |
3594 | mutex_lock(&dev_priv->drm.struct_mutex); | |
3595 | i915_gem_switch_to_kernel_context(dev_priv); | |
3596 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
3597 | ||
3598 | GEM_TRACE("active_requests=%d (after switch-to-kernel-context)\n", | |
3599 | READ_ONCE(dev_priv->gt.active_requests)); | |
3600 | ||
0cb5670b ID |
3601 | /* |
3602 | * Wait for last execlists context complete, but bail out in case a | |
ffed7bd2 CW |
3603 | * new request is submitted. As we don't trust the hardware, we |
3604 | * continue on if the wait times out. This is necessary to allow | |
3605 | * the machine to suspend even if the hardware dies, and we will | |
3606 | * try to recover in resume (after depriving the hardware of power, | |
3607 | * it may be in a better mmod). | |
0cb5670b | 3608 | */ |
ffed7bd2 CW |
3609 | __wait_for(if (new_requests_since_last_retire(dev_priv)) return, |
3610 | intel_engines_are_idle(dev_priv), | |
3611 | I915_IDLE_ENGINES_TIMEOUT * 1000, | |
3612 | 10, 500); | |
67d97da3 CW |
3613 | |
3614 | rearm_hangcheck = | |
3615 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
3616 | ||
5427f207 | 3617 | if (!mutex_trylock(&dev_priv->drm.struct_mutex)) { |
67d97da3 CW |
3618 | /* Currently busy, come back later */ |
3619 | mod_delayed_work(dev_priv->wq, | |
3620 | &dev_priv->gt.idle_work, | |
3621 | msecs_to_jiffies(50)); | |
3622 | goto out_rearm; | |
3623 | } | |
3624 | ||
93c97dc1 ID |
3625 | /* |
3626 | * New request retired after this work handler started, extend active | |
3627 | * period until next instance of the work. | |
3628 | */ | |
5427f207 | 3629 | if (new_requests_since_last_retire(dev_priv)) |
67d97da3 | 3630 | goto out_unlock; |
b29c19b6 | 3631 | |
e4d2006f | 3632 | epoch = __i915_gem_park(dev_priv); |
35c94185 | 3633 | |
1934f5de CW |
3634 | assert_kernel_context_is_current(dev_priv); |
3635 | ||
67d97da3 | 3636 | rearm_hangcheck = false; |
67d97da3 | 3637 | out_unlock: |
5427f207 | 3638 | mutex_unlock(&dev_priv->drm.struct_mutex); |
b29c19b6 | 3639 | |
67d97da3 CW |
3640 | out_rearm: |
3641 | if (rearm_hangcheck) { | |
3642 | GEM_BUG_ON(!dev_priv->gt.awake); | |
3643 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 3644 | } |
84a10749 CW |
3645 | |
3646 | /* | |
3647 | * When we are idle, it is an opportune time to reap our caches. | |
3648 | * However, we have many objects that utilise RCU and the ordered | |
3649 | * i915->wq that this work is executing on. To try and flush any | |
3650 | * pending frees now we are idle, we first wait for an RCU grace | |
3651 | * period, and then queue a task (that will run last on the wq) to | |
3652 | * shrink and re-optimize the caches. | |
3653 | */ | |
3654 | if (same_epoch(dev_priv, epoch)) { | |
3655 | struct sleep_rcu_work *s = kmalloc(sizeof(*s), GFP_KERNEL); | |
3656 | if (s) { | |
3657 | s->i915 = dev_priv; | |
3658 | s->epoch = epoch; | |
3659 | call_rcu(&s->rcu, __sleep_rcu); | |
3660 | } | |
3661 | } | |
673a394b EA |
3662 | } |
3663 | ||
b1f788c6 CW |
3664 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
3665 | { | |
d1b48c1e | 3666 | struct drm_i915_private *i915 = to_i915(gem->dev); |
b1f788c6 CW |
3667 | struct drm_i915_gem_object *obj = to_intel_bo(gem); |
3668 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
d1b48c1e | 3669 | struct i915_lut_handle *lut, *ln; |
b1f788c6 | 3670 | |
d1b48c1e CW |
3671 | mutex_lock(&i915->drm.struct_mutex); |
3672 | ||
3673 | list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { | |
3674 | struct i915_gem_context *ctx = lut->ctx; | |
3675 | struct i915_vma *vma; | |
3676 | ||
432295d7 | 3677 | GEM_BUG_ON(ctx->file_priv == ERR_PTR(-EBADF)); |
d1b48c1e CW |
3678 | if (ctx->file_priv != fpriv) |
3679 | continue; | |
3680 | ||
3681 | vma = radix_tree_delete(&ctx->handles_vma, lut->handle); | |
3ffff017 CW |
3682 | GEM_BUG_ON(vma->obj != obj); |
3683 | ||
3684 | /* We allow the process to have multiple handles to the same | |
3685 | * vma, in the same fd namespace, by virtue of flink/open. | |
3686 | */ | |
3687 | GEM_BUG_ON(!vma->open_count); | |
3688 | if (!--vma->open_count && !i915_vma_is_ggtt(vma)) | |
b1f788c6 | 3689 | i915_vma_close(vma); |
f8a7fde4 | 3690 | |
d1b48c1e CW |
3691 | list_del(&lut->obj_link); |
3692 | list_del(&lut->ctx_link); | |
4ff4b44c | 3693 | |
d1b48c1e CW |
3694 | kmem_cache_free(i915->luts, lut); |
3695 | __i915_gem_object_release_unless_active(obj); | |
f8a7fde4 | 3696 | } |
d1b48c1e CW |
3697 | |
3698 | mutex_unlock(&i915->drm.struct_mutex); | |
b1f788c6 CW |
3699 | } |
3700 | ||
e95433c7 CW |
3701 | static unsigned long to_wait_timeout(s64 timeout_ns) |
3702 | { | |
3703 | if (timeout_ns < 0) | |
3704 | return MAX_SCHEDULE_TIMEOUT; | |
3705 | ||
3706 | if (timeout_ns == 0) | |
3707 | return 0; | |
3708 | ||
3709 | return nsecs_to_jiffies_timeout(timeout_ns); | |
3710 | } | |
3711 | ||
23ba4fd0 BW |
3712 | /** |
3713 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
3714 | * @dev: drm device pointer |
3715 | * @data: ioctl data blob | |
3716 | * @file: drm file pointer | |
23ba4fd0 BW |
3717 | * |
3718 | * Returns 0 if successful, else an error is returned with the remaining time in | |
3719 | * the timeout parameter. | |
3720 | * -ETIME: object is still busy after timeout | |
3721 | * -ERESTARTSYS: signal interrupted the wait | |
3722 | * -ENONENT: object doesn't exist | |
3723 | * Also possible, but rare: | |
b8050148 | 3724 | * -EAGAIN: incomplete, restart syscall |
23ba4fd0 BW |
3725 | * -ENOMEM: damn |
3726 | * -ENODEV: Internal IRQ fail | |
3727 | * -E?: The add request failed | |
3728 | * | |
3729 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
3730 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
3731 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
3732 | * without holding struct_mutex the object may become re-busied before this | |
3733 | * function completes. A similar but shorter * race condition exists in the busy | |
3734 | * ioctl | |
3735 | */ | |
3736 | int | |
3737 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
3738 | { | |
3739 | struct drm_i915_gem_wait *args = data; | |
3740 | struct drm_i915_gem_object *obj; | |
e95433c7 CW |
3741 | ktime_t start; |
3742 | long ret; | |
23ba4fd0 | 3743 | |
11b5d511 DV |
3744 | if (args->flags != 0) |
3745 | return -EINVAL; | |
3746 | ||
03ac0642 | 3747 | obj = i915_gem_object_lookup(file, args->bo_handle); |
033d549b | 3748 | if (!obj) |
23ba4fd0 | 3749 | return -ENOENT; |
23ba4fd0 | 3750 | |
e95433c7 CW |
3751 | start = ktime_get(); |
3752 | ||
3753 | ret = i915_gem_object_wait(obj, | |
3754 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL, | |
3755 | to_wait_timeout(args->timeout_ns), | |
3756 | to_rps_client(file)); | |
3757 | ||
3758 | if (args->timeout_ns > 0) { | |
3759 | args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start)); | |
3760 | if (args->timeout_ns < 0) | |
3761 | args->timeout_ns = 0; | |
c1d2061b CW |
3762 | |
3763 | /* | |
3764 | * Apparently ktime isn't accurate enough and occasionally has a | |
3765 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
3766 | * things up to make the test happy. We allow up to 1 jiffy. | |
3767 | * | |
3768 | * This is a regression from the timespec->ktime conversion. | |
3769 | */ | |
3770 | if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns)) | |
3771 | args->timeout_ns = 0; | |
b8050148 CW |
3772 | |
3773 | /* Asked to wait beyond the jiffie/scheduler precision? */ | |
3774 | if (ret == -ETIME && args->timeout_ns) | |
3775 | ret = -EAGAIN; | |
b4716185 CW |
3776 | } |
3777 | ||
f0cd5182 | 3778 | i915_gem_object_put(obj); |
ff865885 | 3779 | return ret; |
23ba4fd0 BW |
3780 | } |
3781 | ||
ec625fb9 CW |
3782 | static long wait_for_timeline(struct i915_timeline *tl, |
3783 | unsigned int flags, long timeout) | |
4df2faf4 | 3784 | { |
0606035f | 3785 | struct i915_request *rq; |
0606035f CW |
3786 | |
3787 | rq = i915_gem_active_get_unlocked(&tl->last_request); | |
3788 | if (!rq) | |
ec625fb9 | 3789 | return timeout; |
0606035f CW |
3790 | |
3791 | /* | |
3792 | * "Race-to-idle". | |
3793 | * | |
3794 | * Switching to the kernel context is often used a synchronous | |
3795 | * step prior to idling, e.g. in suspend for flushing all | |
3796 | * current operations to memory before sleeping. These we | |
3797 | * want to complete as quickly as possible to avoid prolonged | |
3798 | * stalls, so allow the gpu to boost to maximum clocks. | |
3799 | */ | |
3800 | if (flags & I915_WAIT_FOR_IDLE_BOOST) | |
3801 | gen6_rps_boost(rq, NULL); | |
3802 | ||
ec625fb9 | 3803 | timeout = i915_request_wait(rq, flags, timeout); |
0606035f CW |
3804 | i915_request_put(rq); |
3805 | ||
ec625fb9 | 3806 | return timeout; |
73cb9701 CW |
3807 | } |
3808 | ||
25112b64 CW |
3809 | static int wait_for_engines(struct drm_i915_private *i915) |
3810 | { | |
ee42c00e | 3811 | if (wait_for(intel_engines_are_idle(i915), I915_IDLE_ENGINES_TIMEOUT)) { |
59e4b19d CW |
3812 | dev_err(i915->drm.dev, |
3813 | "Failed to idle engines, declaring wedged!\n"); | |
629820fc | 3814 | GEM_TRACE_DUMP(); |
cad9946c CW |
3815 | i915_gem_set_wedged(i915); |
3816 | return -EIO; | |
25112b64 CW |
3817 | } |
3818 | ||
3819 | return 0; | |
3820 | } | |
3821 | ||
ec625fb9 CW |
3822 | int i915_gem_wait_for_idle(struct drm_i915_private *i915, |
3823 | unsigned int flags, long timeout) | |
73cb9701 | 3824 | { |
ec625fb9 CW |
3825 | GEM_TRACE("flags=%x (%s), timeout=%ld%s\n", |
3826 | flags, flags & I915_WAIT_LOCKED ? "locked" : "unlocked", | |
3827 | timeout, timeout == MAX_SCHEDULE_TIMEOUT ? " (forever)" : ""); | |
09a4c02e | 3828 | |
863e9fde CW |
3829 | /* If the device is asleep, we have no requests outstanding */ |
3830 | if (!READ_ONCE(i915->gt.awake)) | |
3831 | return 0; | |
3832 | ||
9caa34aa | 3833 | if (flags & I915_WAIT_LOCKED) { |
a89d1f92 CW |
3834 | struct i915_timeline *tl; |
3835 | int err; | |
9caa34aa CW |
3836 | |
3837 | lockdep_assert_held(&i915->drm.struct_mutex); | |
3838 | ||
3839 | list_for_each_entry(tl, &i915->gt.timelines, link) { | |
ec625fb9 CW |
3840 | timeout = wait_for_timeline(tl, flags, timeout); |
3841 | if (timeout < 0) | |
3842 | return timeout; | |
9caa34aa | 3843 | } |
c1e63f6d CW |
3844 | if (GEM_SHOW_DEBUG() && !timeout) { |
3845 | /* Presume that timeout was non-zero to begin with! */ | |
3846 | dev_warn(&i915->drm.pdev->dev, | |
3847 | "Missed idle-completion interrupt!\n"); | |
3848 | GEM_TRACE_DUMP(); | |
3849 | } | |
a61b47f6 CW |
3850 | |
3851 | err = wait_for_engines(i915); | |
3852 | if (err) | |
3853 | return err; | |
3854 | ||
e61e0f51 | 3855 | i915_retire_requests(i915); |
09a4c02e | 3856 | GEM_BUG_ON(i915->gt.active_requests); |
9caa34aa | 3857 | } else { |
a89d1f92 CW |
3858 | struct intel_engine_cs *engine; |
3859 | enum intel_engine_id id; | |
4df2faf4 | 3860 | |
a89d1f92 | 3861 | for_each_engine(engine, i915, id) { |
ec625fb9 CW |
3862 | struct i915_timeline *tl = &engine->timeline; |
3863 | ||
3864 | timeout = wait_for_timeline(tl, flags, timeout); | |
3865 | if (timeout < 0) | |
3866 | return timeout; | |
a89d1f92 | 3867 | } |
a89d1f92 | 3868 | } |
a61b47f6 CW |
3869 | |
3870 | return 0; | |
4df2faf4 DV |
3871 | } |
3872 | ||
5a97bcc6 CW |
3873 | static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj) |
3874 | { | |
e27ab73d CW |
3875 | /* |
3876 | * We manually flush the CPU domain so that we can override and | |
3877 | * force the flush for the display, and perform it asyncrhonously. | |
3878 | */ | |
3879 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); | |
3880 | if (obj->cache_dirty) | |
3881 | i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE); | |
c0a51fd0 | 3882 | obj->write_domain = 0; |
5a97bcc6 CW |
3883 | } |
3884 | ||
3885 | void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj) | |
3886 | { | |
bd3d2252 | 3887 | if (!READ_ONCE(obj->pin_global)) |
5a97bcc6 CW |
3888 | return; |
3889 | ||
3890 | mutex_lock(&obj->base.dev->struct_mutex); | |
3891 | __i915_gem_object_flush_for_display(obj); | |
3892 | mutex_unlock(&obj->base.dev->struct_mutex); | |
3893 | } | |
3894 | ||
e22d8e3c CW |
3895 | /** |
3896 | * Moves a single object to the WC read, and possibly write domain. | |
3897 | * @obj: object to act on | |
3898 | * @write: ask for write access or read only | |
3899 | * | |
3900 | * This function returns when the move is complete, including waiting on | |
3901 | * flushes to occur. | |
3902 | */ | |
3903 | int | |
3904 | i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write) | |
3905 | { | |
3906 | int ret; | |
3907 | ||
3908 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
3909 | ||
3910 | ret = i915_gem_object_wait(obj, | |
3911 | I915_WAIT_INTERRUPTIBLE | | |
3912 | I915_WAIT_LOCKED | | |
3913 | (write ? I915_WAIT_ALL : 0), | |
3914 | MAX_SCHEDULE_TIMEOUT, | |
3915 | NULL); | |
3916 | if (ret) | |
3917 | return ret; | |
3918 | ||
c0a51fd0 | 3919 | if (obj->write_domain == I915_GEM_DOMAIN_WC) |
e22d8e3c CW |
3920 | return 0; |
3921 | ||
3922 | /* Flush and acquire obj->pages so that we are coherent through | |
3923 | * direct access in memory with previous cached writes through | |
3924 | * shmemfs and that our cache domain tracking remains valid. | |
3925 | * For example, if the obj->filp was moved to swap without us | |
3926 | * being notified and releasing the pages, we would mistakenly | |
3927 | * continue to assume that the obj remained out of the CPU cached | |
3928 | * domain. | |
3929 | */ | |
3930 | ret = i915_gem_object_pin_pages(obj); | |
3931 | if (ret) | |
3932 | return ret; | |
3933 | ||
3934 | flush_write_domain(obj, ~I915_GEM_DOMAIN_WC); | |
3935 | ||
3936 | /* Serialise direct access to this object with the barriers for | |
3937 | * coherent writes from the GPU, by effectively invalidating the | |
3938 | * WC domain upon first access. | |
3939 | */ | |
c0a51fd0 | 3940 | if ((obj->read_domains & I915_GEM_DOMAIN_WC) == 0) |
e22d8e3c CW |
3941 | mb(); |
3942 | ||
3943 | /* It should now be out of any other write domains, and we can update | |
3944 | * the domain values for our changes. | |
3945 | */ | |
c0a51fd0 CK |
3946 | GEM_BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_WC) != 0); |
3947 | obj->read_domains |= I915_GEM_DOMAIN_WC; | |
e22d8e3c | 3948 | if (write) { |
c0a51fd0 CK |
3949 | obj->read_domains = I915_GEM_DOMAIN_WC; |
3950 | obj->write_domain = I915_GEM_DOMAIN_WC; | |
e22d8e3c CW |
3951 | obj->mm.dirty = true; |
3952 | } | |
3953 | ||
3954 | i915_gem_object_unpin_pages(obj); | |
3955 | return 0; | |
3956 | } | |
3957 | ||
2ef7eeaa EA |
3958 | /** |
3959 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3960 | * @obj: object to act on |
3961 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3962 | * |
3963 | * This function returns when the move is complete, including waiting on | |
3964 | * flushes to occur. | |
3965 | */ | |
79e53945 | 3966 | int |
2021746e | 3967 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3968 | { |
e47c68e9 | 3969 | int ret; |
2ef7eeaa | 3970 | |
e95433c7 | 3971 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3972 | |
e95433c7 CW |
3973 | ret = i915_gem_object_wait(obj, |
3974 | I915_WAIT_INTERRUPTIBLE | | |
3975 | I915_WAIT_LOCKED | | |
3976 | (write ? I915_WAIT_ALL : 0), | |
3977 | MAX_SCHEDULE_TIMEOUT, | |
3978 | NULL); | |
88241785 CW |
3979 | if (ret) |
3980 | return ret; | |
3981 | ||
c0a51fd0 | 3982 | if (obj->write_domain == I915_GEM_DOMAIN_GTT) |
c13d87ea CW |
3983 | return 0; |
3984 | ||
43566ded CW |
3985 | /* Flush and acquire obj->pages so that we are coherent through |
3986 | * direct access in memory with previous cached writes through | |
3987 | * shmemfs and that our cache domain tracking remains valid. | |
3988 | * For example, if the obj->filp was moved to swap without us | |
3989 | * being notified and releasing the pages, we would mistakenly | |
3990 | * continue to assume that the obj remained out of the CPU cached | |
3991 | * domain. | |
3992 | */ | |
a4f5ea64 | 3993 | ret = i915_gem_object_pin_pages(obj); |
43566ded CW |
3994 | if (ret) |
3995 | return ret; | |
3996 | ||
ef74921b | 3997 | flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT); |
1c5d22f7 | 3998 | |
d0a57789 CW |
3999 | /* Serialise direct access to this object with the barriers for |
4000 | * coherent writes from the GPU, by effectively invalidating the | |
4001 | * GTT domain upon first access. | |
4002 | */ | |
c0a51fd0 | 4003 | if ((obj->read_domains & I915_GEM_DOMAIN_GTT) == 0) |
d0a57789 CW |
4004 | mb(); |
4005 | ||
e47c68e9 EA |
4006 | /* It should now be out of any other write domains, and we can update |
4007 | * the domain values for our changes. | |
4008 | */ | |
c0a51fd0 CK |
4009 | GEM_BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
4010 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 4011 | if (write) { |
c0a51fd0 CK |
4012 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
4013 | obj->write_domain = I915_GEM_DOMAIN_GTT; | |
a4f5ea64 | 4014 | obj->mm.dirty = true; |
2ef7eeaa EA |
4015 | } |
4016 | ||
a4f5ea64 | 4017 | i915_gem_object_unpin_pages(obj); |
e47c68e9 EA |
4018 | return 0; |
4019 | } | |
4020 | ||
ef55f92a CW |
4021 | /** |
4022 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
4023 | * @obj: object to act on |
4024 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
4025 | * |
4026 | * After this function returns, the object will be in the new cache-level | |
4027 | * across all GTT and the contents of the backing storage will be coherent, | |
4028 | * with respect to the new cache-level. In order to keep the backing storage | |
4029 | * coherent for all users, we only allow a single cache level to be set | |
4030 | * globally on the object and prevent it from being changed whilst the | |
4031 | * hardware is reading from the object. That is if the object is currently | |
4032 | * on the scanout it will be set to uncached (or equivalent display | |
4033 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
4034 | * that all direct access to the scanout remains coherent. | |
4035 | */ | |
e4ffd173 CW |
4036 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
4037 | enum i915_cache_level cache_level) | |
4038 | { | |
aa653a68 | 4039 | struct i915_vma *vma; |
a6a7cc4b | 4040 | int ret; |
e4ffd173 | 4041 | |
4c7d62c6 CW |
4042 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4043 | ||
e4ffd173 | 4044 | if (obj->cache_level == cache_level) |
a6a7cc4b | 4045 | return 0; |
e4ffd173 | 4046 | |
ef55f92a CW |
4047 | /* Inspect the list of currently bound VMA and unbind any that would |
4048 | * be invalid given the new cache-level. This is principally to | |
4049 | * catch the issue of the CS prefetch crossing page boundaries and | |
4050 | * reading an invalid PTE on older architectures. | |
4051 | */ | |
aa653a68 CW |
4052 | restart: |
4053 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
4054 | if (!drm_mm_node_allocated(&vma->node)) |
4055 | continue; | |
4056 | ||
20dfbde4 | 4057 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
4058 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
4059 | return -EBUSY; | |
4060 | } | |
4061 | ||
010e3e68 CW |
4062 | if (!i915_vma_is_closed(vma) && |
4063 | i915_gem_valid_gtt_space(vma, cache_level)) | |
aa653a68 CW |
4064 | continue; |
4065 | ||
4066 | ret = i915_vma_unbind(vma); | |
4067 | if (ret) | |
4068 | return ret; | |
4069 | ||
4070 | /* As unbinding may affect other elements in the | |
4071 | * obj->vma_list (due to side-effects from retiring | |
4072 | * an active vma), play safe and restart the iterator. | |
4073 | */ | |
4074 | goto restart; | |
42d6ab48 CW |
4075 | } |
4076 | ||
ef55f92a CW |
4077 | /* We can reuse the existing drm_mm nodes but need to change the |
4078 | * cache-level on the PTE. We could simply unbind them all and | |
4079 | * rebind with the correct cache-level on next use. However since | |
4080 | * we already have a valid slot, dma mapping, pages etc, we may as | |
4081 | * rewrite the PTE in the belief that doing so tramples upon less | |
4082 | * state and so involves less work. | |
4083 | */ | |
15717de2 | 4084 | if (obj->bind_count) { |
ef55f92a CW |
4085 | /* Before we change the PTE, the GPU must not be accessing it. |
4086 | * If we wait upon the object, we know that all the bound | |
4087 | * VMA are no longer active. | |
4088 | */ | |
e95433c7 CW |
4089 | ret = i915_gem_object_wait(obj, |
4090 | I915_WAIT_INTERRUPTIBLE | | |
4091 | I915_WAIT_LOCKED | | |
4092 | I915_WAIT_ALL, | |
4093 | MAX_SCHEDULE_TIMEOUT, | |
4094 | NULL); | |
e4ffd173 CW |
4095 | if (ret) |
4096 | return ret; | |
4097 | ||
0031fb96 TU |
4098 | if (!HAS_LLC(to_i915(obj->base.dev)) && |
4099 | cache_level != I915_CACHE_NONE) { | |
ef55f92a CW |
4100 | /* Access to snoopable pages through the GTT is |
4101 | * incoherent and on some machines causes a hard | |
4102 | * lockup. Relinquish the CPU mmaping to force | |
4103 | * userspace to refault in the pages and we can | |
4104 | * then double check if the GTT mapping is still | |
4105 | * valid for that pointer access. | |
4106 | */ | |
4107 | i915_gem_release_mmap(obj); | |
4108 | ||
4109 | /* As we no longer need a fence for GTT access, | |
4110 | * we can relinquish it now (and so prevent having | |
4111 | * to steal a fence from someone else on the next | |
4112 | * fence request). Note GPU activity would have | |
4113 | * dropped the fence as all snoopable access is | |
4114 | * supposed to be linear. | |
4115 | */ | |
e2189dd0 | 4116 | for_each_ggtt_vma(vma, obj) { |
49ef5294 CW |
4117 | ret = i915_vma_put_fence(vma); |
4118 | if (ret) | |
4119 | return ret; | |
4120 | } | |
ef55f92a CW |
4121 | } else { |
4122 | /* We either have incoherent backing store and | |
4123 | * so no GTT access or the architecture is fully | |
4124 | * coherent. In such cases, existing GTT mmaps | |
4125 | * ignore the cache bit in the PTE and we can | |
4126 | * rewrite it without confusing the GPU or having | |
4127 | * to force userspace to fault back in its mmaps. | |
4128 | */ | |
e4ffd173 CW |
4129 | } |
4130 | ||
1c7f4bca | 4131 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
4132 | if (!drm_mm_node_allocated(&vma->node)) |
4133 | continue; | |
4134 | ||
4135 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
4136 | if (ret) | |
4137 | return ret; | |
4138 | } | |
e4ffd173 CW |
4139 | } |
4140 | ||
1c7f4bca | 4141 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b | 4142 | vma->node.color = cache_level; |
b8f55be6 | 4143 | i915_gem_object_set_cache_coherency(obj, cache_level); |
e27ab73d | 4144 | obj->cache_dirty = true; /* Always invalidate stale cachelines */ |
2c22569b | 4145 | |
e4ffd173 CW |
4146 | return 0; |
4147 | } | |
4148 | ||
199adf40 BW |
4149 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
4150 | struct drm_file *file) | |
e6994aee | 4151 | { |
199adf40 | 4152 | struct drm_i915_gem_caching *args = data; |
e6994aee | 4153 | struct drm_i915_gem_object *obj; |
fbbd37b3 | 4154 | int err = 0; |
e6994aee | 4155 | |
fbbd37b3 CW |
4156 | rcu_read_lock(); |
4157 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
4158 | if (!obj) { | |
4159 | err = -ENOENT; | |
4160 | goto out; | |
4161 | } | |
e6994aee | 4162 | |
651d794f CW |
4163 | switch (obj->cache_level) { |
4164 | case I915_CACHE_LLC: | |
4165 | case I915_CACHE_L3_LLC: | |
4166 | args->caching = I915_CACHING_CACHED; | |
4167 | break; | |
4168 | ||
4257d3ba CW |
4169 | case I915_CACHE_WT: |
4170 | args->caching = I915_CACHING_DISPLAY; | |
4171 | break; | |
4172 | ||
651d794f CW |
4173 | default: |
4174 | args->caching = I915_CACHING_NONE; | |
4175 | break; | |
4176 | } | |
fbbd37b3 CW |
4177 | out: |
4178 | rcu_read_unlock(); | |
4179 | return err; | |
e6994aee CW |
4180 | } |
4181 | ||
199adf40 BW |
4182 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
4183 | struct drm_file *file) | |
e6994aee | 4184 | { |
9c870d03 | 4185 | struct drm_i915_private *i915 = to_i915(dev); |
199adf40 | 4186 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
4187 | struct drm_i915_gem_object *obj; |
4188 | enum i915_cache_level level; | |
d65415df | 4189 | int ret = 0; |
e6994aee | 4190 | |
199adf40 BW |
4191 | switch (args->caching) { |
4192 | case I915_CACHING_NONE: | |
e6994aee CW |
4193 | level = I915_CACHE_NONE; |
4194 | break; | |
199adf40 | 4195 | case I915_CACHING_CACHED: |
e5756c10 ID |
4196 | /* |
4197 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
4198 | * snooped mapping may leave stale data in a corresponding CPU | |
4199 | * cacheline, whereas normally such cachelines would get | |
4200 | * invalidated. | |
4201 | */ | |
9c870d03 | 4202 | if (!HAS_LLC(i915) && !HAS_SNOOP(i915)) |
e5756c10 ID |
4203 | return -ENODEV; |
4204 | ||
e6994aee CW |
4205 | level = I915_CACHE_LLC; |
4206 | break; | |
4257d3ba | 4207 | case I915_CACHING_DISPLAY: |
9c870d03 | 4208 | level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE; |
4257d3ba | 4209 | break; |
e6994aee CW |
4210 | default: |
4211 | return -EINVAL; | |
4212 | } | |
4213 | ||
d65415df CW |
4214 | obj = i915_gem_object_lookup(file, args->handle); |
4215 | if (!obj) | |
4216 | return -ENOENT; | |
4217 | ||
a03f395a TZ |
4218 | /* |
4219 | * The caching mode of proxy object is handled by its generator, and | |
4220 | * not allowed to be changed by userspace. | |
4221 | */ | |
4222 | if (i915_gem_object_is_proxy(obj)) { | |
4223 | ret = -ENXIO; | |
4224 | goto out; | |
4225 | } | |
4226 | ||
d65415df CW |
4227 | if (obj->cache_level == level) |
4228 | goto out; | |
4229 | ||
4230 | ret = i915_gem_object_wait(obj, | |
4231 | I915_WAIT_INTERRUPTIBLE, | |
4232 | MAX_SCHEDULE_TIMEOUT, | |
4233 | to_rps_client(file)); | |
3bc2913e | 4234 | if (ret) |
d65415df | 4235 | goto out; |
3bc2913e | 4236 | |
d65415df CW |
4237 | ret = i915_mutex_lock_interruptible(dev); |
4238 | if (ret) | |
4239 | goto out; | |
e6994aee CW |
4240 | |
4241 | ret = i915_gem_object_set_cache_level(obj, level); | |
e6994aee | 4242 | mutex_unlock(&dev->struct_mutex); |
d65415df CW |
4243 | |
4244 | out: | |
4245 | i915_gem_object_put(obj); | |
e6994aee CW |
4246 | return ret; |
4247 | } | |
4248 | ||
b9241ea3 | 4249 | /* |
07bcd99b DP |
4250 | * Prepare buffer for display plane (scanout, cursors, etc). Can be called from |
4251 | * an uninterruptible phase (modesetting) and allows any flushes to be pipelined | |
4252 | * (for pageflips). We only flush the caches while preparing the buffer for | |
4253 | * display, the callers are responsible for frontbuffer flush. | |
b9241ea3 | 4254 | */ |
058d88c4 | 4255 | struct i915_vma * |
2da3b9b9 CW |
4256 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
4257 | u32 alignment, | |
5935485f CW |
4258 | const struct i915_ggtt_view *view, |
4259 | unsigned int flags) | |
b9241ea3 | 4260 | { |
058d88c4 | 4261 | struct i915_vma *vma; |
b9241ea3 ZW |
4262 | int ret; |
4263 | ||
4c7d62c6 CW |
4264 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4265 | ||
bd3d2252 | 4266 | /* Mark the global pin early so that we account for the |
cc98b413 CW |
4267 | * display coherency whilst setting up the cache domains. |
4268 | */ | |
bd3d2252 | 4269 | obj->pin_global++; |
cc98b413 | 4270 | |
a7ef0640 EA |
4271 | /* The display engine is not coherent with the LLC cache on gen6. As |
4272 | * a result, we make sure that the pinning that is about to occur is | |
4273 | * done with uncached PTEs. This is lowest common denominator for all | |
4274 | * chipsets. | |
4275 | * | |
4276 | * However for gen6+, we could do better by using the GFDT bit instead | |
4277 | * of uncaching, which would allow us to flush all the LLC-cached data | |
4278 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
4279 | */ | |
651d794f | 4280 | ret = i915_gem_object_set_cache_level(obj, |
8652744b TU |
4281 | HAS_WT(to_i915(obj->base.dev)) ? |
4282 | I915_CACHE_WT : I915_CACHE_NONE); | |
058d88c4 CW |
4283 | if (ret) { |
4284 | vma = ERR_PTR(ret); | |
bd3d2252 | 4285 | goto err_unpin_global; |
058d88c4 | 4286 | } |
a7ef0640 | 4287 | |
2da3b9b9 CW |
4288 | /* As the user may map the buffer once pinned in the display plane |
4289 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2efb813d CW |
4290 | * always use map_and_fenceable for all scanout buffers. However, |
4291 | * it may simply be too big to fit into mappable, in which case | |
4292 | * put it anyway and hope that userspace can cope (but always first | |
4293 | * try to preserve the existing ABI). | |
2da3b9b9 | 4294 | */ |
2efb813d | 4295 | vma = ERR_PTR(-ENOSPC); |
5935485f CW |
4296 | if ((flags & PIN_MAPPABLE) == 0 && |
4297 | (!view || view->type == I915_GGTT_VIEW_NORMAL)) | |
2efb813d | 4298 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, |
5935485f CW |
4299 | flags | |
4300 | PIN_MAPPABLE | | |
4301 | PIN_NONBLOCK); | |
4302 | if (IS_ERR(vma)) | |
767a222e | 4303 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags); |
058d88c4 | 4304 | if (IS_ERR(vma)) |
bd3d2252 | 4305 | goto err_unpin_global; |
2da3b9b9 | 4306 | |
d8923dcf CW |
4307 | vma->display_alignment = max_t(u64, vma->display_alignment, alignment); |
4308 | ||
5a97bcc6 | 4309 | __i915_gem_object_flush_for_display(obj); |
b118c1e3 | 4310 | |
2da3b9b9 CW |
4311 | /* It should now be out of any other write domains, and we can update |
4312 | * the domain values for our changes. | |
4313 | */ | |
c0a51fd0 | 4314 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 | 4315 | |
058d88c4 | 4316 | return vma; |
cc98b413 | 4317 | |
bd3d2252 CW |
4318 | err_unpin_global: |
4319 | obj->pin_global--; | |
058d88c4 | 4320 | return vma; |
cc98b413 CW |
4321 | } |
4322 | ||
4323 | void | |
058d88c4 | 4324 | i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) |
cc98b413 | 4325 | { |
49d73912 | 4326 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
4c7d62c6 | 4327 | |
bd3d2252 | 4328 | if (WARN_ON(vma->obj->pin_global == 0)) |
8a0c39b1 TU |
4329 | return; |
4330 | ||
bd3d2252 | 4331 | if (--vma->obj->pin_global == 0) |
f51455d4 | 4332 | vma->display_alignment = I915_GTT_MIN_ALIGNMENT; |
e6617330 | 4333 | |
383d5823 | 4334 | /* Bump the LRU to try and avoid premature eviction whilst flipping */ |
befedbb7 | 4335 | i915_gem_object_bump_inactive_ggtt(vma->obj); |
383d5823 | 4336 | |
058d88c4 | 4337 | i915_vma_unpin(vma); |
b9241ea3 ZW |
4338 | } |
4339 | ||
e47c68e9 EA |
4340 | /** |
4341 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
4342 | * @obj: object to act on |
4343 | * @write: requesting write or read-only access | |
e47c68e9 EA |
4344 | * |
4345 | * This function returns when the move is complete, including waiting on | |
4346 | * flushes to occur. | |
4347 | */ | |
dabdfe02 | 4348 | int |
919926ae | 4349 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 4350 | { |
e47c68e9 EA |
4351 | int ret; |
4352 | ||
e95433c7 | 4353 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 4354 | |
e95433c7 CW |
4355 | ret = i915_gem_object_wait(obj, |
4356 | I915_WAIT_INTERRUPTIBLE | | |
4357 | I915_WAIT_LOCKED | | |
4358 | (write ? I915_WAIT_ALL : 0), | |
4359 | MAX_SCHEDULE_TIMEOUT, | |
4360 | NULL); | |
88241785 CW |
4361 | if (ret) |
4362 | return ret; | |
4363 | ||
ef74921b | 4364 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); |
2ef7eeaa | 4365 | |
e47c68e9 | 4366 | /* Flush the CPU cache if it's still invalid. */ |
c0a51fd0 | 4367 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
57822dc6 | 4368 | i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC); |
c0a51fd0 | 4369 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
4370 | } |
4371 | ||
4372 | /* It should now be out of any other write domains, and we can update | |
4373 | * the domain values for our changes. | |
4374 | */ | |
c0a51fd0 | 4375 | GEM_BUG_ON(obj->write_domain & ~I915_GEM_DOMAIN_CPU); |
e47c68e9 EA |
4376 | |
4377 | /* If we're writing through the CPU, then the GPU read domains will | |
4378 | * need to be invalidated at next use. | |
4379 | */ | |
e27ab73d CW |
4380 | if (write) |
4381 | __start_cpu_write(obj); | |
2ef7eeaa EA |
4382 | |
4383 | return 0; | |
4384 | } | |
4385 | ||
673a394b EA |
4386 | /* Throttle our rendering by waiting until the ring has completed our requests |
4387 | * emitted over 20 msec ago. | |
4388 | * | |
b962442e EA |
4389 | * Note that if we were to use the current jiffies each time around the loop, |
4390 | * we wouldn't escape the function with any frames outstanding if the time to | |
4391 | * render a frame was over 20ms. | |
4392 | * | |
673a394b EA |
4393 | * This should get us reasonable parallelism between CPU and GPU but also |
4394 | * relatively low latency when blocking on a particular request to finish. | |
4395 | */ | |
40a5f0de | 4396 | static int |
f787a5f5 | 4397 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4398 | { |
fac5e23e | 4399 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 4400 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 4401 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
e61e0f51 | 4402 | struct i915_request *request, *target = NULL; |
e95433c7 | 4403 | long ret; |
93533c29 | 4404 | |
f4457ae7 CW |
4405 | /* ABI: return -EIO if already wedged */ |
4406 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
4407 | return -EIO; | |
e110e8d6 | 4408 | |
1c25595f | 4409 | spin_lock(&file_priv->mm.lock); |
c8659efa | 4410 | list_for_each_entry(request, &file_priv->mm.request_list, client_link) { |
b962442e EA |
4411 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4412 | break; | |
40a5f0de | 4413 | |
c8659efa CW |
4414 | if (target) { |
4415 | list_del(&target->client_link); | |
4416 | target->file_priv = NULL; | |
4417 | } | |
fcfa423c | 4418 | |
54fb2411 | 4419 | target = request; |
b962442e | 4420 | } |
ff865885 | 4421 | if (target) |
e61e0f51 | 4422 | i915_request_get(target); |
1c25595f | 4423 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4424 | |
54fb2411 | 4425 | if (target == NULL) |
f787a5f5 | 4426 | return 0; |
2bc43b5c | 4427 | |
e61e0f51 | 4428 | ret = i915_request_wait(target, |
e95433c7 CW |
4429 | I915_WAIT_INTERRUPTIBLE, |
4430 | MAX_SCHEDULE_TIMEOUT); | |
e61e0f51 | 4431 | i915_request_put(target); |
ff865885 | 4432 | |
e95433c7 | 4433 | return ret < 0 ? ret : 0; |
40a5f0de EA |
4434 | } |
4435 | ||
058d88c4 | 4436 | struct i915_vma * |
ec7adb6e JL |
4437 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
4438 | const struct i915_ggtt_view *view, | |
91b2db6f | 4439 | u64 size, |
2ffffd0f CW |
4440 | u64 alignment, |
4441 | u64 flags) | |
ec7adb6e | 4442 | { |
ad16d2ed | 4443 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
82ad6443 | 4444 | struct i915_address_space *vm = &dev_priv->ggtt.vm; |
59bfa124 CW |
4445 | struct i915_vma *vma; |
4446 | int ret; | |
72e96d64 | 4447 | |
4c7d62c6 CW |
4448 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4449 | ||
ac87a6fd CW |
4450 | if (flags & PIN_MAPPABLE && |
4451 | (!view || view->type == I915_GGTT_VIEW_NORMAL)) { | |
43ae70d9 CW |
4452 | /* If the required space is larger than the available |
4453 | * aperture, we will not able to find a slot for the | |
4454 | * object and unbinding the object now will be in | |
4455 | * vain. Worse, doing so may cause us to ping-pong | |
4456 | * the object in and out of the Global GTT and | |
4457 | * waste a lot of cycles under the mutex. | |
4458 | */ | |
4459 | if (obj->base.size > dev_priv->ggtt.mappable_end) | |
4460 | return ERR_PTR(-E2BIG); | |
4461 | ||
4462 | /* If NONBLOCK is set the caller is optimistically | |
4463 | * trying to cache the full object within the mappable | |
4464 | * aperture, and *must* have a fallback in place for | |
4465 | * situations where we cannot bind the object. We | |
4466 | * can be a little more lax here and use the fallback | |
4467 | * more often to avoid costly migrations of ourselves | |
4468 | * and other objects within the aperture. | |
4469 | * | |
4470 | * Half-the-aperture is used as a simple heuristic. | |
4471 | * More interesting would to do search for a free | |
4472 | * block prior to making the commitment to unbind. | |
4473 | * That caters for the self-harm case, and with a | |
4474 | * little more heuristics (e.g. NOFAULT, NOEVICT) | |
4475 | * we could try to minimise harm to others. | |
4476 | */ | |
4477 | if (flags & PIN_NONBLOCK && | |
4478 | obj->base.size > dev_priv->ggtt.mappable_end / 2) | |
4479 | return ERR_PTR(-ENOSPC); | |
4480 | } | |
4481 | ||
718659a6 | 4482 | vma = i915_vma_instance(obj, vm, view); |
e0216b76 | 4483 | if (unlikely(IS_ERR(vma))) |
058d88c4 | 4484 | return vma; |
59bfa124 CW |
4485 | |
4486 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
43ae70d9 CW |
4487 | if (flags & PIN_NONBLOCK) { |
4488 | if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)) | |
4489 | return ERR_PTR(-ENOSPC); | |
59bfa124 | 4490 | |
43ae70d9 | 4491 | if (flags & PIN_MAPPABLE && |
944397f0 | 4492 | vma->fence_size > dev_priv->ggtt.mappable_end / 2) |
ad16d2ed CW |
4493 | return ERR_PTR(-ENOSPC); |
4494 | } | |
4495 | ||
59bfa124 CW |
4496 | WARN(i915_vma_is_pinned(vma), |
4497 | "bo is already pinned in ggtt with incorrect alignment:" | |
05a20d09 CW |
4498 | " offset=%08x, req.alignment=%llx," |
4499 | " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n", | |
4500 | i915_ggtt_offset(vma), alignment, | |
59bfa124 | 4501 | !!(flags & PIN_MAPPABLE), |
05a20d09 | 4502 | i915_vma_is_map_and_fenceable(vma)); |
59bfa124 CW |
4503 | ret = i915_vma_unbind(vma); |
4504 | if (ret) | |
058d88c4 | 4505 | return ERR_PTR(ret); |
59bfa124 CW |
4506 | } |
4507 | ||
058d88c4 CW |
4508 | ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); |
4509 | if (ret) | |
4510 | return ERR_PTR(ret); | |
ec7adb6e | 4511 | |
058d88c4 | 4512 | return vma; |
673a394b EA |
4513 | } |
4514 | ||
edf6b76f | 4515 | static __always_inline unsigned int __busy_read_flag(unsigned int id) |
3fdc13c7 CW |
4516 | { |
4517 | /* Note that we could alias engines in the execbuf API, but | |
4518 | * that would be very unwise as it prevents userspace from | |
4519 | * fine control over engine selection. Ahem. | |
4520 | * | |
4521 | * This should be something like EXEC_MAX_ENGINE instead of | |
4522 | * I915_NUM_ENGINES. | |
4523 | */ | |
4524 | BUILD_BUG_ON(I915_NUM_ENGINES > 16); | |
4525 | return 0x10000 << id; | |
4526 | } | |
4527 | ||
4528 | static __always_inline unsigned int __busy_write_id(unsigned int id) | |
4529 | { | |
70cb472c CW |
4530 | /* The uABI guarantees an active writer is also amongst the read |
4531 | * engines. This would be true if we accessed the activity tracking | |
4532 | * under the lock, but as we perform the lookup of the object and | |
4533 | * its activity locklessly we can not guarantee that the last_write | |
4534 | * being active implies that we have set the same engine flag from | |
4535 | * last_read - hence we always set both read and write busy for | |
4536 | * last_write. | |
4537 | */ | |
4538 | return id | __busy_read_flag(id); | |
3fdc13c7 CW |
4539 | } |
4540 | ||
edf6b76f | 4541 | static __always_inline unsigned int |
d07f0e59 | 4542 | __busy_set_if_active(const struct dma_fence *fence, |
3fdc13c7 CW |
4543 | unsigned int (*flag)(unsigned int id)) |
4544 | { | |
e61e0f51 | 4545 | struct i915_request *rq; |
3fdc13c7 | 4546 | |
d07f0e59 CW |
4547 | /* We have to check the current hw status of the fence as the uABI |
4548 | * guarantees forward progress. We could rely on the idle worker | |
4549 | * to eventually flush us, but to minimise latency just ask the | |
4550 | * hardware. | |
1255501d | 4551 | * |
d07f0e59 | 4552 | * Note we only report on the status of native fences. |
1255501d | 4553 | */ |
d07f0e59 CW |
4554 | if (!dma_fence_is_i915(fence)) |
4555 | return 0; | |
4556 | ||
4557 | /* opencode to_request() in order to avoid const warnings */ | |
e61e0f51 CW |
4558 | rq = container_of(fence, struct i915_request, fence); |
4559 | if (i915_request_completed(rq)) | |
d07f0e59 CW |
4560 | return 0; |
4561 | ||
1d39f281 | 4562 | return flag(rq->engine->uabi_id); |
3fdc13c7 CW |
4563 | } |
4564 | ||
edf6b76f | 4565 | static __always_inline unsigned int |
d07f0e59 | 4566 | busy_check_reader(const struct dma_fence *fence) |
3fdc13c7 | 4567 | { |
d07f0e59 | 4568 | return __busy_set_if_active(fence, __busy_read_flag); |
3fdc13c7 CW |
4569 | } |
4570 | ||
edf6b76f | 4571 | static __always_inline unsigned int |
d07f0e59 | 4572 | busy_check_writer(const struct dma_fence *fence) |
3fdc13c7 | 4573 | { |
d07f0e59 CW |
4574 | if (!fence) |
4575 | return 0; | |
4576 | ||
4577 | return __busy_set_if_active(fence, __busy_write_id); | |
3fdc13c7 CW |
4578 | } |
4579 | ||
673a394b EA |
4580 | int |
4581 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4582 | struct drm_file *file) |
673a394b EA |
4583 | { |
4584 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4585 | struct drm_i915_gem_object *obj; |
d07f0e59 CW |
4586 | struct reservation_object_list *list; |
4587 | unsigned int seq; | |
fbbd37b3 | 4588 | int err; |
673a394b | 4589 | |
d07f0e59 | 4590 | err = -ENOENT; |
fbbd37b3 CW |
4591 | rcu_read_lock(); |
4592 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
d07f0e59 | 4593 | if (!obj) |
fbbd37b3 | 4594 | goto out; |
d1b851fc | 4595 | |
d07f0e59 CW |
4596 | /* A discrepancy here is that we do not report the status of |
4597 | * non-i915 fences, i.e. even though we may report the object as idle, | |
4598 | * a call to set-domain may still stall waiting for foreign rendering. | |
4599 | * This also means that wait-ioctl may report an object as busy, | |
4600 | * where busy-ioctl considers it idle. | |
4601 | * | |
4602 | * We trade the ability to warn of foreign fences to report on which | |
4603 | * i915 engines are active for the object. | |
4604 | * | |
4605 | * Alternatively, we can trade that extra information on read/write | |
4606 | * activity with | |
4607 | * args->busy = | |
4608 | * !reservation_object_test_signaled_rcu(obj->resv, true); | |
4609 | * to report the overall busyness. This is what the wait-ioctl does. | |
4610 | * | |
4611 | */ | |
4612 | retry: | |
4613 | seq = raw_read_seqcount(&obj->resv->seq); | |
426960be | 4614 | |
d07f0e59 CW |
4615 | /* Translate the exclusive fence to the READ *and* WRITE engine */ |
4616 | args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl)); | |
3fdc13c7 | 4617 | |
d07f0e59 CW |
4618 | /* Translate shared fences to READ set of engines */ |
4619 | list = rcu_dereference(obj->resv->fence); | |
4620 | if (list) { | |
4621 | unsigned int shared_count = list->shared_count, i; | |
3fdc13c7 | 4622 | |
d07f0e59 CW |
4623 | for (i = 0; i < shared_count; ++i) { |
4624 | struct dma_fence *fence = | |
4625 | rcu_dereference(list->shared[i]); | |
4626 | ||
4627 | args->busy |= busy_check_reader(fence); | |
4628 | } | |
426960be | 4629 | } |
673a394b | 4630 | |
d07f0e59 CW |
4631 | if (args->busy && read_seqcount_retry(&obj->resv->seq, seq)) |
4632 | goto retry; | |
4633 | ||
4634 | err = 0; | |
fbbd37b3 CW |
4635 | out: |
4636 | rcu_read_unlock(); | |
4637 | return err; | |
673a394b EA |
4638 | } |
4639 | ||
4640 | int | |
4641 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4642 | struct drm_file *file_priv) | |
4643 | { | |
0206e353 | 4644 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4645 | } |
4646 | ||
3ef94daa CW |
4647 | int |
4648 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4649 | struct drm_file *file_priv) | |
4650 | { | |
fac5e23e | 4651 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 4652 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4653 | struct drm_i915_gem_object *obj; |
1233e2db | 4654 | int err; |
3ef94daa CW |
4655 | |
4656 | switch (args->madv) { | |
4657 | case I915_MADV_DONTNEED: | |
4658 | case I915_MADV_WILLNEED: | |
4659 | break; | |
4660 | default: | |
4661 | return -EINVAL; | |
4662 | } | |
4663 | ||
03ac0642 | 4664 | obj = i915_gem_object_lookup(file_priv, args->handle); |
1233e2db CW |
4665 | if (!obj) |
4666 | return -ENOENT; | |
4667 | ||
4668 | err = mutex_lock_interruptible(&obj->mm.lock); | |
4669 | if (err) | |
4670 | goto out; | |
3ef94daa | 4671 | |
f1fa4f44 | 4672 | if (i915_gem_object_has_pages(obj) && |
3e510a8e | 4673 | i915_gem_object_is_tiled(obj) && |
656bfa3a | 4674 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
bc0629a7 CW |
4675 | if (obj->mm.madv == I915_MADV_WILLNEED) { |
4676 | GEM_BUG_ON(!obj->mm.quirked); | |
a4f5ea64 | 4677 | __i915_gem_object_unpin_pages(obj); |
bc0629a7 CW |
4678 | obj->mm.quirked = false; |
4679 | } | |
4680 | if (args->madv == I915_MADV_WILLNEED) { | |
2c3a3f44 | 4681 | GEM_BUG_ON(obj->mm.quirked); |
a4f5ea64 | 4682 | __i915_gem_object_pin_pages(obj); |
bc0629a7 CW |
4683 | obj->mm.quirked = true; |
4684 | } | |
656bfa3a DV |
4685 | } |
4686 | ||
a4f5ea64 CW |
4687 | if (obj->mm.madv != __I915_MADV_PURGED) |
4688 | obj->mm.madv = args->madv; | |
3ef94daa | 4689 | |
6c085a72 | 4690 | /* if the object is no longer attached, discard its backing storage */ |
f1fa4f44 CW |
4691 | if (obj->mm.madv == I915_MADV_DONTNEED && |
4692 | !i915_gem_object_has_pages(obj)) | |
2d7ef395 CW |
4693 | i915_gem_object_truncate(obj); |
4694 | ||
a4f5ea64 | 4695 | args->retained = obj->mm.madv != __I915_MADV_PURGED; |
1233e2db | 4696 | mutex_unlock(&obj->mm.lock); |
bb6baf76 | 4697 | |
1233e2db | 4698 | out: |
f8c417cd | 4699 | i915_gem_object_put(obj); |
1233e2db | 4700 | return err; |
3ef94daa CW |
4701 | } |
4702 | ||
5b8c8aec | 4703 | static void |
e61e0f51 | 4704 | frontbuffer_retire(struct i915_gem_active *active, struct i915_request *request) |
5b8c8aec CW |
4705 | { |
4706 | struct drm_i915_gem_object *obj = | |
4707 | container_of(active, typeof(*obj), frontbuffer_write); | |
4708 | ||
d59b21ec | 4709 | intel_fb_obj_flush(obj, ORIGIN_CS); |
5b8c8aec CW |
4710 | } |
4711 | ||
37e680a1 CW |
4712 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4713 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4714 | { |
1233e2db CW |
4715 | mutex_init(&obj->mm.lock); |
4716 | ||
2f633156 | 4717 | INIT_LIST_HEAD(&obj->vma_list); |
d1b48c1e | 4718 | INIT_LIST_HEAD(&obj->lut_list); |
8d9d5744 | 4719 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4720 | |
37e680a1 CW |
4721 | obj->ops = ops; |
4722 | ||
d07f0e59 CW |
4723 | reservation_object_init(&obj->__builtin_resv); |
4724 | obj->resv = &obj->__builtin_resv; | |
4725 | ||
50349247 | 4726 | obj->frontbuffer_ggtt_origin = ORIGIN_GTT; |
5b8c8aec | 4727 | init_request_active(&obj->frontbuffer_write, frontbuffer_retire); |
a4f5ea64 CW |
4728 | |
4729 | obj->mm.madv = I915_MADV_WILLNEED; | |
4730 | INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN); | |
4731 | mutex_init(&obj->mm.get_page.lock); | |
0327d6ba | 4732 | |
f19ec8cb | 4733 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
4734 | } |
4735 | ||
37e680a1 | 4736 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3599a91c TU |
4737 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE | |
4738 | I915_GEM_OBJECT_IS_SHRINKABLE, | |
7c55e2c5 | 4739 | |
37e680a1 CW |
4740 | .get_pages = i915_gem_object_get_pages_gtt, |
4741 | .put_pages = i915_gem_object_put_pages_gtt, | |
7c55e2c5 CW |
4742 | |
4743 | .pwrite = i915_gem_object_pwrite_gtt, | |
37e680a1 CW |
4744 | }; |
4745 | ||
465c403c MA |
4746 | static int i915_gem_object_create_shmem(struct drm_device *dev, |
4747 | struct drm_gem_object *obj, | |
4748 | size_t size) | |
4749 | { | |
4750 | struct drm_i915_private *i915 = to_i915(dev); | |
4751 | unsigned long flags = VM_NORESERVE; | |
4752 | struct file *filp; | |
4753 | ||
4754 | drm_gem_private_object_init(dev, obj, size); | |
4755 | ||
4756 | if (i915->mm.gemfs) | |
4757 | filp = shmem_file_setup_with_mnt(i915->mm.gemfs, "i915", size, | |
4758 | flags); | |
4759 | else | |
4760 | filp = shmem_file_setup("i915", size, flags); | |
4761 | ||
4762 | if (IS_ERR(filp)) | |
4763 | return PTR_ERR(filp); | |
4764 | ||
4765 | obj->filp = filp; | |
4766 | ||
4767 | return 0; | |
4768 | } | |
4769 | ||
b4bcbe2a | 4770 | struct drm_i915_gem_object * |
12d79d78 | 4771 | i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) |
ac52bc56 | 4772 | { |
c397b908 | 4773 | struct drm_i915_gem_object *obj; |
5949eac4 | 4774 | struct address_space *mapping; |
b8f55be6 | 4775 | unsigned int cache_level; |
1a240d4d | 4776 | gfp_t mask; |
fe3db79b | 4777 | int ret; |
ac52bc56 | 4778 | |
b4bcbe2a CW |
4779 | /* There is a prevalence of the assumption that we fit the object's |
4780 | * page count inside a 32bit _signed_ variable. Let's document this and | |
4781 | * catch if we ever need to fix it. In the meantime, if you do spot | |
4782 | * such a local variable, please consider fixing! | |
4783 | */ | |
7a3ee5de | 4784 | if (size >> PAGE_SHIFT > INT_MAX) |
b4bcbe2a CW |
4785 | return ERR_PTR(-E2BIG); |
4786 | ||
4787 | if (overflows_type(size, obj->base.size)) | |
4788 | return ERR_PTR(-E2BIG); | |
4789 | ||
187685cb | 4790 | obj = i915_gem_object_alloc(dev_priv); |
c397b908 | 4791 | if (obj == NULL) |
fe3db79b | 4792 | return ERR_PTR(-ENOMEM); |
673a394b | 4793 | |
465c403c | 4794 | ret = i915_gem_object_create_shmem(&dev_priv->drm, &obj->base, size); |
fe3db79b CW |
4795 | if (ret) |
4796 | goto fail; | |
673a394b | 4797 | |
bed1ea95 | 4798 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
c0f86832 | 4799 | if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) { |
bed1ea95 CW |
4800 | /* 965gm cannot relocate objects above 4GiB. */ |
4801 | mask &= ~__GFP_HIGHMEM; | |
4802 | mask |= __GFP_DMA32; | |
4803 | } | |
4804 | ||
93c76a3d | 4805 | mapping = obj->base.filp->f_mapping; |
bed1ea95 | 4806 | mapping_set_gfp_mask(mapping, mask); |
4846bf0c | 4807 | GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM)); |
5949eac4 | 4808 | |
37e680a1 | 4809 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4810 | |
c0a51fd0 CK |
4811 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
4812 | obj->read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4813 | |
b8f55be6 | 4814 | if (HAS_LLC(dev_priv)) |
3d29b842 | 4815 | /* On some devices, we can have the GPU use the LLC (the CPU |
a1871112 EA |
4816 | * cache) for about a 10% performance improvement |
4817 | * compared to uncached. Graphics requests other than | |
4818 | * display scanout are coherent with the CPU in | |
4819 | * accessing this cache. This means in this mode we | |
4820 | * don't need to clflush on the CPU side, and on the | |
4821 | * GPU side we only need to flush internal caches to | |
4822 | * get data visible to the CPU. | |
4823 | * | |
4824 | * However, we maintain the display planes as UC, and so | |
4825 | * need to rebind when first used as such. | |
4826 | */ | |
b8f55be6 CW |
4827 | cache_level = I915_CACHE_LLC; |
4828 | else | |
4829 | cache_level = I915_CACHE_NONE; | |
a1871112 | 4830 | |
b8f55be6 | 4831 | i915_gem_object_set_cache_coherency(obj, cache_level); |
e27ab73d | 4832 | |
d861e338 DV |
4833 | trace_i915_gem_object_create(obj); |
4834 | ||
05394f39 | 4835 | return obj; |
fe3db79b CW |
4836 | |
4837 | fail: | |
4838 | i915_gem_object_free(obj); | |
fe3db79b | 4839 | return ERR_PTR(ret); |
c397b908 DV |
4840 | } |
4841 | ||
340fbd8c CW |
4842 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4843 | { | |
4844 | /* If we are the last user of the backing storage (be it shmemfs | |
4845 | * pages or stolen etc), we know that the pages are going to be | |
4846 | * immediately released. In this case, we can then skip copying | |
4847 | * back the contents from the GPU. | |
4848 | */ | |
4849 | ||
a4f5ea64 | 4850 | if (obj->mm.madv != I915_MADV_WILLNEED) |
340fbd8c CW |
4851 | return false; |
4852 | ||
4853 | if (obj->base.filp == NULL) | |
4854 | return true; | |
4855 | ||
4856 | /* At first glance, this looks racy, but then again so would be | |
4857 | * userspace racing mmap against close. However, the first external | |
4858 | * reference to the filp can only be obtained through the | |
4859 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4860 | * acquiring such a reference whilst we are in the middle of | |
4861 | * freeing the object. | |
4862 | */ | |
4863 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4864 | } | |
4865 | ||
fbbd37b3 CW |
4866 | static void __i915_gem_free_objects(struct drm_i915_private *i915, |
4867 | struct llist_node *freed) | |
673a394b | 4868 | { |
fbbd37b3 | 4869 | struct drm_i915_gem_object *obj, *on; |
673a394b | 4870 | |
fbbd37b3 | 4871 | intel_runtime_pm_get(i915); |
cc731f5a | 4872 | llist_for_each_entry_safe(obj, on, freed, freed) { |
fbbd37b3 CW |
4873 | struct i915_vma *vma, *vn; |
4874 | ||
4875 | trace_i915_gem_object_destroy(obj); | |
4876 | ||
cc731f5a CW |
4877 | mutex_lock(&i915->drm.struct_mutex); |
4878 | ||
fbbd37b3 CW |
4879 | GEM_BUG_ON(i915_gem_object_is_active(obj)); |
4880 | list_for_each_entry_safe(vma, vn, | |
4881 | &obj->vma_list, obj_link) { | |
fbbd37b3 CW |
4882 | GEM_BUG_ON(i915_vma_is_active(vma)); |
4883 | vma->flags &= ~I915_VMA_PIN_MASK; | |
3365e226 | 4884 | i915_vma_destroy(vma); |
fbbd37b3 | 4885 | } |
db6c2b41 CW |
4886 | GEM_BUG_ON(!list_empty(&obj->vma_list)); |
4887 | GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree)); | |
fbbd37b3 | 4888 | |
f2123818 CW |
4889 | /* This serializes freeing with the shrinker. Since the free |
4890 | * is delayed, first by RCU then by the workqueue, we want the | |
4891 | * shrinker to be able to free pages of unreferenced objects, | |
4892 | * or else we may oom whilst there are plenty of deferred | |
4893 | * freed objects. | |
4894 | */ | |
4895 | if (i915_gem_object_has_pages(obj)) { | |
4896 | spin_lock(&i915->mm.obj_lock); | |
4897 | list_del_init(&obj->mm.link); | |
4898 | spin_unlock(&i915->mm.obj_lock); | |
4899 | } | |
4900 | ||
cc731f5a | 4901 | mutex_unlock(&i915->drm.struct_mutex); |
fbbd37b3 | 4902 | |
fbbd37b3 | 4903 | GEM_BUG_ON(obj->bind_count); |
a65adaf8 | 4904 | GEM_BUG_ON(obj->userfault_count); |
fbbd37b3 | 4905 | GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits)); |
67b48040 | 4906 | GEM_BUG_ON(!list_empty(&obj->lut_list)); |
fbbd37b3 CW |
4907 | |
4908 | if (obj->ops->release) | |
4909 | obj->ops->release(obj); | |
f65c9168 | 4910 | |
fbbd37b3 CW |
4911 | if (WARN_ON(i915_gem_object_has_pinned_pages(obj))) |
4912 | atomic_set(&obj->mm.pages_pin_count, 0); | |
548625ee | 4913 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
f1fa4f44 | 4914 | GEM_BUG_ON(i915_gem_object_has_pages(obj)); |
fbbd37b3 CW |
4915 | |
4916 | if (obj->base.import_attach) | |
4917 | drm_prime_gem_destroy(&obj->base, NULL); | |
4918 | ||
d07f0e59 | 4919 | reservation_object_fini(&obj->__builtin_resv); |
fbbd37b3 CW |
4920 | drm_gem_object_release(&obj->base); |
4921 | i915_gem_info_remove_obj(i915, obj->base.size); | |
4922 | ||
4923 | kfree(obj->bit_17); | |
4924 | i915_gem_object_free(obj); | |
cc731f5a | 4925 | |
c9c70471 CW |
4926 | GEM_BUG_ON(!atomic_read(&i915->mm.free_count)); |
4927 | atomic_dec(&i915->mm.free_count); | |
4928 | ||
cc731f5a CW |
4929 | if (on) |
4930 | cond_resched(); | |
fbbd37b3 | 4931 | } |
cc731f5a | 4932 | intel_runtime_pm_put(i915); |
fbbd37b3 CW |
4933 | } |
4934 | ||
4935 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915) | |
4936 | { | |
4937 | struct llist_node *freed; | |
4938 | ||
87701b4b CW |
4939 | /* Free the oldest, most stale object to keep the free_list short */ |
4940 | freed = NULL; | |
4941 | if (!llist_empty(&i915->mm.free_list)) { /* quick test for hotpath */ | |
4942 | /* Only one consumer of llist_del_first() allowed */ | |
4943 | spin_lock(&i915->mm.free_lock); | |
4944 | freed = llist_del_first(&i915->mm.free_list); | |
4945 | spin_unlock(&i915->mm.free_lock); | |
4946 | } | |
4947 | if (unlikely(freed)) { | |
4948 | freed->next = NULL; | |
fbbd37b3 | 4949 | __i915_gem_free_objects(i915, freed); |
87701b4b | 4950 | } |
fbbd37b3 CW |
4951 | } |
4952 | ||
4953 | static void __i915_gem_free_work(struct work_struct *work) | |
4954 | { | |
4955 | struct drm_i915_private *i915 = | |
4956 | container_of(work, struct drm_i915_private, mm.free_work); | |
4957 | struct llist_node *freed; | |
26e12f89 | 4958 | |
2ef1e729 CW |
4959 | /* |
4960 | * All file-owned VMA should have been released by this point through | |
b1f788c6 CW |
4961 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). |
4962 | * However, the object may also be bound into the global GTT (e.g. | |
4963 | * older GPUs without per-process support, or for direct access through | |
4964 | * the GTT either for the user or for scanout). Those VMA still need to | |
4965 | * unbound now. | |
4966 | */ | |
1488fc08 | 4967 | |
f991c492 | 4968 | spin_lock(&i915->mm.free_lock); |
5ad08be7 | 4969 | while ((freed = llist_del_all(&i915->mm.free_list))) { |
f991c492 CW |
4970 | spin_unlock(&i915->mm.free_lock); |
4971 | ||
fbbd37b3 | 4972 | __i915_gem_free_objects(i915, freed); |
5ad08be7 | 4973 | if (need_resched()) |
f991c492 CW |
4974 | return; |
4975 | ||
4976 | spin_lock(&i915->mm.free_lock); | |
5ad08be7 | 4977 | } |
f991c492 | 4978 | spin_unlock(&i915->mm.free_lock); |
fbbd37b3 | 4979 | } |
a071fa00 | 4980 | |
fbbd37b3 CW |
4981 | static void __i915_gem_free_object_rcu(struct rcu_head *head) |
4982 | { | |
4983 | struct drm_i915_gem_object *obj = | |
4984 | container_of(head, typeof(*obj), rcu); | |
4985 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
4986 | ||
2ef1e729 CW |
4987 | /* |
4988 | * Since we require blocking on struct_mutex to unbind the freed | |
4989 | * object from the GPU before releasing resources back to the | |
4990 | * system, we can not do that directly from the RCU callback (which may | |
4991 | * be a softirq context), but must instead then defer that work onto a | |
4992 | * kthread. We use the RCU callback rather than move the freed object | |
4993 | * directly onto the work queue so that we can mix between using the | |
4994 | * worker and performing frees directly from subsequent allocations for | |
4995 | * crude but effective memory throttling. | |
fbbd37b3 CW |
4996 | */ |
4997 | if (llist_add(&obj->freed, &i915->mm.free_list)) | |
beacbd16 | 4998 | queue_work(i915->wq, &i915->mm.free_work); |
fbbd37b3 | 4999 | } |
656bfa3a | 5000 | |
fbbd37b3 CW |
5001 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
5002 | { | |
5003 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); | |
a4f5ea64 | 5004 | |
bc0629a7 CW |
5005 | if (obj->mm.quirked) |
5006 | __i915_gem_object_unpin_pages(obj); | |
5007 | ||
340fbd8c | 5008 | if (discard_backing_storage(obj)) |
a4f5ea64 | 5009 | obj->mm.madv = I915_MADV_DONTNEED; |
de151cf6 | 5010 | |
2ef1e729 CW |
5011 | /* |
5012 | * Before we free the object, make sure any pure RCU-only | |
fbbd37b3 CW |
5013 | * read-side critical sections are complete, e.g. |
5014 | * i915_gem_busy_ioctl(). For the corresponding synchronized | |
5015 | * lookup see i915_gem_object_lookup_rcu(). | |
5016 | */ | |
c9c70471 | 5017 | atomic_inc(&to_i915(obj->base.dev)->mm.free_count); |
fbbd37b3 | 5018 | call_rcu(&obj->rcu, __i915_gem_free_object_rcu); |
673a394b EA |
5019 | } |
5020 | ||
f8a7fde4 CW |
5021 | void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj) |
5022 | { | |
5023 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
5024 | ||
d1b48c1e CW |
5025 | if (!i915_gem_object_has_active_reference(obj) && |
5026 | i915_gem_object_is_active(obj)) | |
f8a7fde4 CW |
5027 | i915_gem_object_set_active_reference(obj); |
5028 | else | |
5029 | i915_gem_object_put(obj); | |
5030 | } | |
5031 | ||
24145517 CW |
5032 | void i915_gem_sanitize(struct drm_i915_private *i915) |
5033 | { | |
4fdd5b4e | 5034 | int err; |
c3160da9 CW |
5035 | |
5036 | GEM_TRACE("\n"); | |
5037 | ||
4dfacb0b | 5038 | mutex_lock(&i915->drm.struct_mutex); |
c3160da9 CW |
5039 | |
5040 | intel_runtime_pm_get(i915); | |
5041 | intel_uncore_forcewake_get(i915, FORCEWAKE_ALL); | |
5042 | ||
5043 | /* | |
5044 | * As we have just resumed the machine and woken the device up from | |
5045 | * deep PCI sleep (presumably D3_cold), assume the HW has been reset | |
5046 | * back to defaults, recovering from whatever wedged state we left it | |
5047 | * in and so worth trying to use the device once more. | |
5048 | */ | |
4dfacb0b | 5049 | if (i915_terminally_wedged(&i915->gpu_error)) |
f36325f3 | 5050 | i915_gem_unset_wedged(i915); |
f36325f3 | 5051 | |
24145517 CW |
5052 | /* |
5053 | * If we inherit context state from the BIOS or earlier occupants | |
5054 | * of the GPU, the GPU may be in an inconsistent state when we | |
5055 | * try to take over. The only way to remove the earlier state | |
5056 | * is by resetting. However, resetting on earlier gen is tricky as | |
5057 | * it may impact the display and we are uncertain about the stability | |
ea117b8d | 5058 | * of the reset, so this could be applied to even earlier gen. |
24145517 | 5059 | */ |
4fdd5b4e | 5060 | err = -ENODEV; |
ce1599a4 | 5061 | if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915)) |
4fdd5b4e CW |
5062 | err = WARN_ON(intel_gpu_reset(i915, ALL_ENGINES)); |
5063 | if (!err) | |
5064 | intel_engines_sanitize(i915); | |
c3160da9 CW |
5065 | |
5066 | intel_uncore_forcewake_put(i915, FORCEWAKE_ALL); | |
5067 | intel_runtime_pm_put(i915); | |
5068 | ||
4dfacb0b CW |
5069 | i915_gem_contexts_lost(i915); |
5070 | mutex_unlock(&i915->drm.struct_mutex); | |
24145517 CW |
5071 | } |
5072 | ||
bf06112f | 5073 | int i915_gem_suspend(struct drm_i915_private *i915) |
29105ccc | 5074 | { |
dcff85c8 | 5075 | int ret; |
28dfe52a | 5076 | |
09a4c02e CW |
5077 | GEM_TRACE("\n"); |
5078 | ||
bf06112f CW |
5079 | intel_runtime_pm_get(i915); |
5080 | intel_suspend_gt_powersave(i915); | |
54b4f68f | 5081 | |
bf06112f | 5082 | mutex_lock(&i915->drm.struct_mutex); |
5ab57c70 | 5083 | |
bf06112f CW |
5084 | /* |
5085 | * We have to flush all the executing contexts to main memory so | |
5ab57c70 CW |
5086 | * that they can saved in the hibernation image. To ensure the last |
5087 | * context image is coherent, we have to switch away from it. That | |
bf06112f | 5088 | * leaves the i915->kernel_context still active when |
5ab57c70 CW |
5089 | * we actually suspend, and its image in memory may not match the GPU |
5090 | * state. Fortunately, the kernel_context is disposable and we do | |
5091 | * not rely on its state. | |
5092 | */ | |
bf06112f CW |
5093 | if (!i915_terminally_wedged(&i915->gpu_error)) { |
5094 | ret = i915_gem_switch_to_kernel_context(i915); | |
ecf73eb2 CW |
5095 | if (ret) |
5096 | goto err_unlock; | |
5ab57c70 | 5097 | |
bf06112f | 5098 | ret = i915_gem_wait_for_idle(i915, |
ecf73eb2 | 5099 | I915_WAIT_INTERRUPTIBLE | |
0606035f | 5100 | I915_WAIT_LOCKED | |
ec625fb9 CW |
5101 | I915_WAIT_FOR_IDLE_BOOST, |
5102 | MAX_SCHEDULE_TIMEOUT); | |
ecf73eb2 CW |
5103 | if (ret && ret != -EIO) |
5104 | goto err_unlock; | |
f7403347 | 5105 | |
bf06112f | 5106 | assert_kernel_context_is_current(i915); |
ecf73eb2 | 5107 | } |
01f8f33e CW |
5108 | i915_retire_requests(i915); /* ensure we flush after wedging */ |
5109 | ||
bf06112f | 5110 | mutex_unlock(&i915->drm.struct_mutex); |
45c5f202 | 5111 | |
bf06112f | 5112 | intel_uc_suspend(i915); |
63987bfe | 5113 | |
bf06112f CW |
5114 | cancel_delayed_work_sync(&i915->gpu_error.hangcheck_work); |
5115 | cancel_delayed_work_sync(&i915->gt.retire_work); | |
bdeb9785 | 5116 | |
bf06112f CW |
5117 | /* |
5118 | * As the idle_work is rearming if it detects a race, play safe and | |
bdeb9785 CW |
5119 | * repeat the flush until it is definitely idle. |
5120 | */ | |
bf06112f | 5121 | drain_delayed_work(&i915->gt.idle_work); |
bdeb9785 | 5122 | |
bf06112f CW |
5123 | /* |
5124 | * Assert that we successfully flushed all the work and | |
bdcf120b CW |
5125 | * reset the GPU back to its idle, low power state. |
5126 | */ | |
bf06112f CW |
5127 | WARN_ON(i915->gt.awake); |
5128 | if (WARN_ON(!intel_engines_are_idle(i915))) | |
5129 | i915_gem_set_wedged(i915); /* no hope, discard everything */ | |
bdcf120b | 5130 | |
bf06112f | 5131 | intel_runtime_pm_put(i915); |
ec92ad00 CW |
5132 | return 0; |
5133 | ||
5134 | err_unlock: | |
bf06112f CW |
5135 | mutex_unlock(&i915->drm.struct_mutex); |
5136 | intel_runtime_pm_put(i915); | |
ec92ad00 CW |
5137 | return ret; |
5138 | } | |
5139 | ||
5140 | void i915_gem_suspend_late(struct drm_i915_private *i915) | |
5141 | { | |
9776f472 CW |
5142 | struct drm_i915_gem_object *obj; |
5143 | struct list_head *phases[] = { | |
5144 | &i915->mm.unbound_list, | |
5145 | &i915->mm.bound_list, | |
5146 | NULL | |
5147 | }, **phase; | |
5148 | ||
1c777c5d ID |
5149 | /* |
5150 | * Neither the BIOS, ourselves or any other kernel | |
5151 | * expects the system to be in execlists mode on startup, | |
5152 | * so we need to reset the GPU back to legacy mode. And the only | |
5153 | * known way to disable logical contexts is through a GPU reset. | |
5154 | * | |
5155 | * So in order to leave the system in a known default configuration, | |
5156 | * always reset the GPU upon unload and suspend. Afterwards we then | |
5157 | * clean up the GEM state tracking, flushing off the requests and | |
5158 | * leaving the system in a known idle state. | |
5159 | * | |
5160 | * Note that is of the upmost importance that the GPU is idle and | |
5161 | * all stray writes are flushed *before* we dismantle the backing | |
5162 | * storage for the pinned objects. | |
5163 | * | |
5164 | * However, since we are uncertain that resetting the GPU on older | |
5165 | * machines is a good idea, we don't - just in case it leaves the | |
5166 | * machine in an unusable condition. | |
5167 | */ | |
1c777c5d | 5168 | |
9776f472 CW |
5169 | mutex_lock(&i915->drm.struct_mutex); |
5170 | for (phase = phases; *phase; phase++) { | |
5171 | list_for_each_entry(obj, *phase, mm.link) | |
5172 | WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); | |
5173 | } | |
5174 | mutex_unlock(&i915->drm.struct_mutex); | |
5175 | ||
ec92ad00 CW |
5176 | intel_uc_sanitize(i915); |
5177 | i915_gem_sanitize(i915); | |
673a394b EA |
5178 | } |
5179 | ||
37cd3300 | 5180 | void i915_gem_resume(struct drm_i915_private *i915) |
5ab57c70 | 5181 | { |
4dfacb0b CW |
5182 | GEM_TRACE("\n"); |
5183 | ||
37cd3300 | 5184 | WARN_ON(i915->gt.awake); |
5ab57c70 | 5185 | |
37cd3300 CW |
5186 | mutex_lock(&i915->drm.struct_mutex); |
5187 | intel_uncore_forcewake_get(i915, FORCEWAKE_ALL); | |
31ab49ab | 5188 | |
37cd3300 CW |
5189 | i915_gem_restore_gtt_mappings(i915); |
5190 | i915_gem_restore_fences(i915); | |
5ab57c70 | 5191 | |
6ca9a2be CW |
5192 | /* |
5193 | * As we didn't flush the kernel context before suspend, we cannot | |
5ab57c70 CW |
5194 | * guarantee that the context image is complete. So let's just reset |
5195 | * it and start again. | |
5196 | */ | |
37cd3300 | 5197 | i915->gt.resume(i915); |
5ab57c70 | 5198 | |
37cd3300 CW |
5199 | if (i915_gem_init_hw(i915)) |
5200 | goto err_wedged; | |
5201 | ||
7cfca4af | 5202 | intel_uc_resume(i915); |
7469c62c | 5203 | |
37cd3300 CW |
5204 | /* Always reload a context for powersaving. */ |
5205 | if (i915_gem_switch_to_kernel_context(i915)) | |
5206 | goto err_wedged; | |
5207 | ||
5208 | out_unlock: | |
5209 | intel_uncore_forcewake_put(i915, FORCEWAKE_ALL); | |
5210 | mutex_unlock(&i915->drm.struct_mutex); | |
5211 | return; | |
5212 | ||
5213 | err_wedged: | |
6ca9a2be CW |
5214 | if (!i915_terminally_wedged(&i915->gpu_error)) { |
5215 | DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n"); | |
5216 | i915_gem_set_wedged(i915); | |
5217 | } | |
37cd3300 | 5218 | goto out_unlock; |
5ab57c70 CW |
5219 | } |
5220 | ||
c6be607a | 5221 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) |
f691e2f4 | 5222 | { |
c6be607a | 5223 | if (INTEL_GEN(dev_priv) < 5 || |
f691e2f4 DV |
5224 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
5225 | return; | |
5226 | ||
5227 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
5228 | DISP_TILE_SURFACE_SWIZZLING); | |
5229 | ||
5db94019 | 5230 | if (IS_GEN5(dev_priv)) |
11782b02 DV |
5231 | return; |
5232 | ||
f691e2f4 | 5233 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
5db94019 | 5234 | if (IS_GEN6(dev_priv)) |
6b26c86d | 5235 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
5db94019 | 5236 | else if (IS_GEN7(dev_priv)) |
6b26c86d | 5237 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
5db94019 | 5238 | else if (IS_GEN8(dev_priv)) |
31a5336e | 5239 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
8782e26c BW |
5240 | else |
5241 | BUG(); | |
f691e2f4 | 5242 | } |
e21af88d | 5243 | |
50a0bc90 | 5244 | static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base) |
81e7f200 | 5245 | { |
81e7f200 VS |
5246 | I915_WRITE(RING_CTL(base), 0); |
5247 | I915_WRITE(RING_HEAD(base), 0); | |
5248 | I915_WRITE(RING_TAIL(base), 0); | |
5249 | I915_WRITE(RING_START(base), 0); | |
5250 | } | |
5251 | ||
50a0bc90 | 5252 | static void init_unused_rings(struct drm_i915_private *dev_priv) |
81e7f200 | 5253 | { |
50a0bc90 TU |
5254 | if (IS_I830(dev_priv)) { |
5255 | init_unused_ring(dev_priv, PRB1_BASE); | |
5256 | init_unused_ring(dev_priv, SRB0_BASE); | |
5257 | init_unused_ring(dev_priv, SRB1_BASE); | |
5258 | init_unused_ring(dev_priv, SRB2_BASE); | |
5259 | init_unused_ring(dev_priv, SRB3_BASE); | |
5260 | } else if (IS_GEN2(dev_priv)) { | |
5261 | init_unused_ring(dev_priv, SRB0_BASE); | |
5262 | init_unused_ring(dev_priv, SRB1_BASE); | |
5263 | } else if (IS_GEN3(dev_priv)) { | |
5264 | init_unused_ring(dev_priv, PRB1_BASE); | |
5265 | init_unused_ring(dev_priv, PRB2_BASE); | |
81e7f200 VS |
5266 | } |
5267 | } | |
5268 | ||
20a8a74a | 5269 | static int __i915_gem_restart_engines(void *data) |
4fc7c971 | 5270 | { |
20a8a74a | 5271 | struct drm_i915_private *i915 = data; |
e2f80391 | 5272 | struct intel_engine_cs *engine; |
3b3f1650 | 5273 | enum intel_engine_id id; |
20a8a74a CW |
5274 | int err; |
5275 | ||
5276 | for_each_engine(engine, i915, id) { | |
5277 | err = engine->init_hw(engine); | |
8177e112 CW |
5278 | if (err) { |
5279 | DRM_ERROR("Failed to restart %s (%d)\n", | |
5280 | engine->name, err); | |
20a8a74a | 5281 | return err; |
8177e112 | 5282 | } |
20a8a74a CW |
5283 | } |
5284 | ||
5285 | return 0; | |
5286 | } | |
5287 | ||
5288 | int i915_gem_init_hw(struct drm_i915_private *dev_priv) | |
5289 | { | |
d200cda6 | 5290 | int ret; |
4fc7c971 | 5291 | |
de867c20 CW |
5292 | dev_priv->gt.last_init_time = ktime_get(); |
5293 | ||
5e4f5189 CW |
5294 | /* Double layer security blanket, see i915_gem_init() */ |
5295 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
5296 | ||
0031fb96 | 5297 | if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 5298 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 5299 | |
772c2a51 | 5300 | if (IS_HASWELL(dev_priv)) |
50a0bc90 | 5301 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ? |
0bf21347 | 5302 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
9435373e | 5303 | |
6e266956 | 5304 | if (HAS_PCH_NOP(dev_priv)) { |
fd6b8f43 | 5305 | if (IS_IVYBRIDGE(dev_priv)) { |
6ba844b0 DV |
5306 | u32 temp = I915_READ(GEN7_MSG_CTL); |
5307 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
5308 | I915_WRITE(GEN7_MSG_CTL, temp); | |
c6be607a | 5309 | } else if (INTEL_GEN(dev_priv) >= 7) { |
6ba844b0 DV |
5310 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
5311 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5312 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
5313 | } | |
88a2b2a3 BW |
5314 | } |
5315 | ||
59b449d5 OM |
5316 | intel_gt_workarounds_apply(dev_priv); |
5317 | ||
c6be607a | 5318 | i915_gem_init_swizzling(dev_priv); |
4fc7c971 | 5319 | |
d5abdfda DV |
5320 | /* |
5321 | * At least 830 can leave some of the unused rings | |
5322 | * "active" (ie. head != tail) after resume which | |
5323 | * will prevent c3 entry. Makes sure all unused rings | |
5324 | * are totally idle. | |
5325 | */ | |
50a0bc90 | 5326 | init_unused_rings(dev_priv); |
d5abdfda | 5327 | |
ed54c1a1 | 5328 | BUG_ON(!dev_priv->kernel_context); |
6f74b36b CW |
5329 | if (i915_terminally_wedged(&dev_priv->gpu_error)) { |
5330 | ret = -EIO; | |
5331 | goto out; | |
5332 | } | |
90638cc1 | 5333 | |
c6be607a | 5334 | ret = i915_ppgtt_init_hw(dev_priv); |
4ad2fd88 | 5335 | if (ret) { |
8177e112 | 5336 | DRM_ERROR("Enabling PPGTT failed (%d)\n", ret); |
4ad2fd88 JH |
5337 | goto out; |
5338 | } | |
5339 | ||
f08e2035 JL |
5340 | ret = intel_wopcm_init_hw(&dev_priv->wopcm); |
5341 | if (ret) { | |
5342 | DRM_ERROR("Enabling WOPCM failed (%d)\n", ret); | |
5343 | goto out; | |
5344 | } | |
5345 | ||
9bdc3573 MW |
5346 | /* We can't enable contexts until all firmware is loaded */ |
5347 | ret = intel_uc_init_hw(dev_priv); | |
8177e112 CW |
5348 | if (ret) { |
5349 | DRM_ERROR("Enabling uc failed (%d)\n", ret); | |
9bdc3573 | 5350 | goto out; |
8177e112 | 5351 | } |
9bdc3573 | 5352 | |
bf9e8429 | 5353 | intel_mocs_init_l3cc_table(dev_priv); |
0ccdacf6 | 5354 | |
136109c6 CW |
5355 | /* Only when the HW is re-initialised, can we replay the requests */ |
5356 | ret = __i915_gem_restart_engines(dev_priv); | |
b96f6ebf MW |
5357 | if (ret) |
5358 | goto cleanup_uc; | |
60c0a66e | 5359 | |
5e4f5189 | 5360 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60c0a66e MW |
5361 | |
5362 | return 0; | |
b96f6ebf MW |
5363 | |
5364 | cleanup_uc: | |
5365 | intel_uc_fini_hw(dev_priv); | |
60c0a66e MW |
5366 | out: |
5367 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
5368 | ||
5369 | return ret; | |
8187a2b7 ZN |
5370 | } |
5371 | ||
d2b4b979 CW |
5372 | static int __intel_engines_record_defaults(struct drm_i915_private *i915) |
5373 | { | |
5374 | struct i915_gem_context *ctx; | |
5375 | struct intel_engine_cs *engine; | |
5376 | enum intel_engine_id id; | |
5377 | int err; | |
5378 | ||
5379 | /* | |
5380 | * As we reset the gpu during very early sanitisation, the current | |
5381 | * register state on the GPU should reflect its defaults values. | |
5382 | * We load a context onto the hw (with restore-inhibit), then switch | |
5383 | * over to a second context to save that default register state. We | |
5384 | * can then prime every new context with that state so they all start | |
5385 | * from the same default HW values. | |
5386 | */ | |
5387 | ||
5388 | ctx = i915_gem_context_create_kernel(i915, 0); | |
5389 | if (IS_ERR(ctx)) | |
5390 | return PTR_ERR(ctx); | |
5391 | ||
5392 | for_each_engine(engine, i915, id) { | |
e61e0f51 | 5393 | struct i915_request *rq; |
d2b4b979 | 5394 | |
e61e0f51 | 5395 | rq = i915_request_alloc(engine, ctx); |
d2b4b979 CW |
5396 | if (IS_ERR(rq)) { |
5397 | err = PTR_ERR(rq); | |
5398 | goto out_ctx; | |
5399 | } | |
5400 | ||
3fef5cda | 5401 | err = 0; |
d2b4b979 CW |
5402 | if (engine->init_context) |
5403 | err = engine->init_context(rq); | |
5404 | ||
697b9a87 | 5405 | i915_request_add(rq); |
d2b4b979 CW |
5406 | if (err) |
5407 | goto err_active; | |
5408 | } | |
5409 | ||
5410 | err = i915_gem_switch_to_kernel_context(i915); | |
5411 | if (err) | |
5412 | goto err_active; | |
5413 | ||
2621cefa CW |
5414 | if (i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED, HZ / 5)) { |
5415 | i915_gem_set_wedged(i915); | |
5416 | err = -EIO; /* Caller will declare us wedged */ | |
d2b4b979 | 5417 | goto err_active; |
2621cefa | 5418 | } |
d2b4b979 CW |
5419 | |
5420 | assert_kernel_context_is_current(i915); | |
5421 | ||
8e1cb32d CW |
5422 | /* |
5423 | * Immediately park the GPU so that we enable powersaving and | |
5424 | * treat it as idle. The next time we issue a request, we will | |
5425 | * unpark and start using the engine->pinned_default_state, otherwise | |
5426 | * it is in limbo and an early reset may fail. | |
5427 | */ | |
5428 | __i915_gem_park(i915); | |
5429 | ||
d2b4b979 CW |
5430 | for_each_engine(engine, i915, id) { |
5431 | struct i915_vma *state; | |
37d7c9cc | 5432 | void *vaddr; |
d2b4b979 | 5433 | |
666424ab CW |
5434 | GEM_BUG_ON(to_intel_context(ctx, engine)->pin_count); |
5435 | ||
ab82a063 | 5436 | state = to_intel_context(ctx, engine)->state; |
d2b4b979 CW |
5437 | if (!state) |
5438 | continue; | |
5439 | ||
5440 | /* | |
5441 | * As we will hold a reference to the logical state, it will | |
5442 | * not be torn down with the context, and importantly the | |
5443 | * object will hold onto its vma (making it possible for a | |
5444 | * stray GTT write to corrupt our defaults). Unmap the vma | |
5445 | * from the GTT to prevent such accidents and reclaim the | |
5446 | * space. | |
5447 | */ | |
5448 | err = i915_vma_unbind(state); | |
5449 | if (err) | |
5450 | goto err_active; | |
5451 | ||
5452 | err = i915_gem_object_set_to_cpu_domain(state->obj, false); | |
5453 | if (err) | |
5454 | goto err_active; | |
5455 | ||
5456 | engine->default_state = i915_gem_object_get(state->obj); | |
37d7c9cc CW |
5457 | |
5458 | /* Check we can acquire the image of the context state */ | |
5459 | vaddr = i915_gem_object_pin_map(engine->default_state, | |
666424ab | 5460 | I915_MAP_FORCE_WB); |
37d7c9cc CW |
5461 | if (IS_ERR(vaddr)) { |
5462 | err = PTR_ERR(vaddr); | |
5463 | goto err_active; | |
5464 | } | |
5465 | ||
5466 | i915_gem_object_unpin_map(engine->default_state); | |
d2b4b979 CW |
5467 | } |
5468 | ||
5469 | if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) { | |
5470 | unsigned int found = intel_engines_has_context_isolation(i915); | |
5471 | ||
5472 | /* | |
5473 | * Make sure that classes with multiple engine instances all | |
5474 | * share the same basic configuration. | |
5475 | */ | |
5476 | for_each_engine(engine, i915, id) { | |
5477 | unsigned int bit = BIT(engine->uabi_class); | |
5478 | unsigned int expected = engine->default_state ? bit : 0; | |
5479 | ||
5480 | if ((found & bit) != expected) { | |
5481 | DRM_ERROR("mismatching default context state for class %d on engine %s\n", | |
5482 | engine->uabi_class, engine->name); | |
5483 | } | |
5484 | } | |
5485 | } | |
5486 | ||
5487 | out_ctx: | |
5488 | i915_gem_context_set_closed(ctx); | |
5489 | i915_gem_context_put(ctx); | |
5490 | return err; | |
5491 | ||
5492 | err_active: | |
5493 | /* | |
5494 | * If we have to abandon now, we expect the engines to be idle | |
5495 | * and ready to be torn-down. First try to flush any remaining | |
5496 | * request, ensure we are pointing at the kernel context and | |
5497 | * then remove it. | |
5498 | */ | |
5499 | if (WARN_ON(i915_gem_switch_to_kernel_context(i915))) | |
5500 | goto out_ctx; | |
5501 | ||
ec625fb9 CW |
5502 | if (WARN_ON(i915_gem_wait_for_idle(i915, |
5503 | I915_WAIT_LOCKED, | |
5504 | MAX_SCHEDULE_TIMEOUT))) | |
d2b4b979 CW |
5505 | goto out_ctx; |
5506 | ||
5507 | i915_gem_contexts_lost(i915); | |
5508 | goto out_ctx; | |
5509 | } | |
5510 | ||
bf9e8429 | 5511 | int i915_gem_init(struct drm_i915_private *dev_priv) |
1070a42b | 5512 | { |
1070a42b CW |
5513 | int ret; |
5514 | ||
52b2416c CD |
5515 | /* We need to fallback to 4K pages if host doesn't support huge gtt. */ |
5516 | if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv)) | |
da9fe3f3 MA |
5517 | mkwrite_device_info(dev_priv)->page_sizes = |
5518 | I915_GTT_PAGE_SIZE_4K; | |
5519 | ||
94312828 | 5520 | dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1); |
57822dc6 | 5521 | |
fb5c551a | 5522 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv)) { |
821ed7df | 5523 | dev_priv->gt.resume = intel_lr_context_resume; |
117897f4 | 5524 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
fb5c551a CW |
5525 | } else { |
5526 | dev_priv->gt.resume = intel_legacy_submission_resume; | |
5527 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; | |
a83014d3 OM |
5528 | } |
5529 | ||
ee48700d CW |
5530 | ret = i915_gem_init_userptr(dev_priv); |
5531 | if (ret) | |
5532 | return ret; | |
5533 | ||
f7dc0157 | 5534 | ret = intel_uc_init_misc(dev_priv); |
6b0478fb JL |
5535 | if (ret) |
5536 | return ret; | |
5537 | ||
f7dc0157 | 5538 | ret = intel_wopcm_init(&dev_priv->wopcm); |
3176ff49 | 5539 | if (ret) |
f7dc0157 | 5540 | goto err_uc_misc; |
3176ff49 | 5541 | |
5e4f5189 CW |
5542 | /* This is just a security blanket to placate dragons. |
5543 | * On some systems, we very sporadically observe that the first TLBs | |
5544 | * used by the CS may be stale, despite us poking the TLB reset. If | |
5545 | * we hold the forcewake during initialisation these problems | |
5546 | * just magically go away. | |
5547 | */ | |
ee48700d | 5548 | mutex_lock(&dev_priv->drm.struct_mutex); |
5e4f5189 CW |
5549 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
5550 | ||
f6b9d5ca | 5551 | ret = i915_gem_init_ggtt(dev_priv); |
6ca9a2be CW |
5552 | if (ret) { |
5553 | GEM_BUG_ON(ret == -EIO); | |
5554 | goto err_unlock; | |
5555 | } | |
d62b4892 | 5556 | |
829a0af2 | 5557 | ret = i915_gem_contexts_init(dev_priv); |
6ca9a2be CW |
5558 | if (ret) { |
5559 | GEM_BUG_ON(ret == -EIO); | |
5560 | goto err_ggtt; | |
5561 | } | |
2fa48d8d | 5562 | |
bf9e8429 | 5563 | ret = intel_engines_init(dev_priv); |
6ca9a2be CW |
5564 | if (ret) { |
5565 | GEM_BUG_ON(ret == -EIO); | |
5566 | goto err_context; | |
5567 | } | |
2fa48d8d | 5568 | |
f58d13d5 CW |
5569 | intel_init_gt_powersave(dev_priv); |
5570 | ||
61b5c158 | 5571 | ret = intel_uc_init(dev_priv); |
cc6a818a | 5572 | if (ret) |
6ca9a2be | 5573 | goto err_pm; |
cc6a818a | 5574 | |
61b5c158 MW |
5575 | ret = i915_gem_init_hw(dev_priv); |
5576 | if (ret) | |
5577 | goto err_uc_init; | |
5578 | ||
cc6a818a CW |
5579 | /* |
5580 | * Despite its name intel_init_clock_gating applies both display | |
5581 | * clock gating workarounds; GT mmio workarounds and the occasional | |
5582 | * GT power context workaround. Worse, sometimes it includes a context | |
5583 | * register workaround which we need to apply before we record the | |
5584 | * default HW state for all contexts. | |
5585 | * | |
5586 | * FIXME: break up the workarounds and apply them at the right time! | |
5587 | */ | |
5588 | intel_init_clock_gating(dev_priv); | |
5589 | ||
d2b4b979 | 5590 | ret = __intel_engines_record_defaults(dev_priv); |
6ca9a2be CW |
5591 | if (ret) |
5592 | goto err_init_hw; | |
5593 | ||
5594 | if (i915_inject_load_failure()) { | |
5595 | ret = -ENODEV; | |
5596 | goto err_init_hw; | |
5597 | } | |
5598 | ||
5599 | if (i915_inject_load_failure()) { | |
5600 | ret = -EIO; | |
5601 | goto err_init_hw; | |
5602 | } | |
5603 | ||
5604 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
5605 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
5606 | ||
5607 | return 0; | |
5608 | ||
5609 | /* | |
5610 | * Unwinding is complicated by that we want to handle -EIO to mean | |
5611 | * disable GPU submission but keep KMS alive. We want to mark the | |
5612 | * HW as irrevisibly wedged, but keep enough state around that the | |
5613 | * driver doesn't explode during runtime. | |
5614 | */ | |
5615 | err_init_hw: | |
8571a05a CW |
5616 | mutex_unlock(&dev_priv->drm.struct_mutex); |
5617 | ||
5618 | WARN_ON(i915_gem_suspend(dev_priv)); | |
5619 | i915_gem_suspend_late(dev_priv); | |
5620 | ||
8bcf9f70 CW |
5621 | i915_gem_drain_workqueue(dev_priv); |
5622 | ||
8571a05a | 5623 | mutex_lock(&dev_priv->drm.struct_mutex); |
6ca9a2be | 5624 | intel_uc_fini_hw(dev_priv); |
61b5c158 MW |
5625 | err_uc_init: |
5626 | intel_uc_fini(dev_priv); | |
6ca9a2be CW |
5627 | err_pm: |
5628 | if (ret != -EIO) { | |
5629 | intel_cleanup_gt_powersave(dev_priv); | |
5630 | i915_gem_cleanup_engines(dev_priv); | |
5631 | } | |
5632 | err_context: | |
5633 | if (ret != -EIO) | |
5634 | i915_gem_contexts_fini(dev_priv); | |
5635 | err_ggtt: | |
5636 | err_unlock: | |
5637 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
5638 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
5639 | ||
f7dc0157 | 5640 | err_uc_misc: |
70deeadd | 5641 | intel_uc_fini_misc(dev_priv); |
da943b5a | 5642 | |
6ca9a2be CW |
5643 | if (ret != -EIO) |
5644 | i915_gem_cleanup_userptr(dev_priv); | |
5645 | ||
60990320 | 5646 | if (ret == -EIO) { |
7ed43df7 CW |
5647 | mutex_lock(&dev_priv->drm.struct_mutex); |
5648 | ||
6ca9a2be CW |
5649 | /* |
5650 | * Allow engine initialisation to fail by marking the GPU as | |
60990320 CW |
5651 | * wedged. But we only want to do this where the GPU is angry, |
5652 | * for all other failure, such as an allocation failure, bail. | |
5653 | */ | |
6f74b36b | 5654 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { |
51c18bf7 CW |
5655 | i915_load_error(dev_priv, |
5656 | "Failed to initialize GPU, declaring it wedged!\n"); | |
6f74b36b CW |
5657 | i915_gem_set_wedged(dev_priv); |
5658 | } | |
7ed43df7 CW |
5659 | |
5660 | /* Minimal basic recovery for KMS */ | |
5661 | ret = i915_ggtt_enable_hw(dev_priv); | |
5662 | i915_gem_restore_gtt_mappings(dev_priv); | |
5663 | i915_gem_restore_fences(dev_priv); | |
5664 | intel_init_clock_gating(dev_priv); | |
5665 | ||
5666 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
1070a42b CW |
5667 | } |
5668 | ||
6ca9a2be | 5669 | i915_gem_drain_freed_objects(dev_priv); |
60990320 | 5670 | return ret; |
1070a42b CW |
5671 | } |
5672 | ||
8979187a MW |
5673 | void i915_gem_fini(struct drm_i915_private *dev_priv) |
5674 | { | |
5675 | i915_gem_suspend_late(dev_priv); | |
30b71084 | 5676 | intel_disable_gt_powersave(dev_priv); |
8979187a MW |
5677 | |
5678 | /* Flush any outstanding unpin_work. */ | |
5679 | i915_gem_drain_workqueue(dev_priv); | |
5680 | ||
5681 | mutex_lock(&dev_priv->drm.struct_mutex); | |
5682 | intel_uc_fini_hw(dev_priv); | |
5683 | intel_uc_fini(dev_priv); | |
5684 | i915_gem_cleanup_engines(dev_priv); | |
5685 | i915_gem_contexts_fini(dev_priv); | |
5686 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
5687 | ||
30b71084 CW |
5688 | intel_cleanup_gt_powersave(dev_priv); |
5689 | ||
8979187a MW |
5690 | intel_uc_fini_misc(dev_priv); |
5691 | i915_gem_cleanup_userptr(dev_priv); | |
5692 | ||
5693 | i915_gem_drain_freed_objects(dev_priv); | |
5694 | ||
5695 | WARN_ON(!list_empty(&dev_priv->contexts.list)); | |
5696 | } | |
5697 | ||
24145517 CW |
5698 | void i915_gem_init_mmio(struct drm_i915_private *i915) |
5699 | { | |
5700 | i915_gem_sanitize(i915); | |
5701 | } | |
5702 | ||
8187a2b7 | 5703 | void |
cb15d9f8 | 5704 | i915_gem_cleanup_engines(struct drm_i915_private *dev_priv) |
8187a2b7 | 5705 | { |
e2f80391 | 5706 | struct intel_engine_cs *engine; |
3b3f1650 | 5707 | enum intel_engine_id id; |
8187a2b7 | 5708 | |
3b3f1650 | 5709 | for_each_engine(engine, dev_priv, id) |
117897f4 | 5710 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
5711 | } |
5712 | ||
40ae4e16 ID |
5713 | void |
5714 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
5715 | { | |
49ef5294 | 5716 | int i; |
40ae4e16 | 5717 | |
c56b89f1 | 5718 | if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) && |
40ae4e16 ID |
5719 | !IS_CHERRYVIEW(dev_priv)) |
5720 | dev_priv->num_fence_regs = 32; | |
c56b89f1 | 5721 | else if (INTEL_GEN(dev_priv) >= 4 || |
73f67aa8 JN |
5722 | IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
5723 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) | |
40ae4e16 ID |
5724 | dev_priv->num_fence_regs = 16; |
5725 | else | |
5726 | dev_priv->num_fence_regs = 8; | |
5727 | ||
c033666a | 5728 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
5729 | dev_priv->num_fence_regs = |
5730 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
5731 | ||
5732 | /* Initialize fence registers to zero */ | |
49ef5294 CW |
5733 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
5734 | struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i]; | |
5735 | ||
5736 | fence->i915 = dev_priv; | |
5737 | fence->id = i; | |
5738 | list_add_tail(&fence->link, &dev_priv->mm.fence_list); | |
5739 | } | |
4362f4f6 | 5740 | i915_gem_restore_fences(dev_priv); |
40ae4e16 | 5741 | |
4362f4f6 | 5742 | i915_gem_detect_bit_6_swizzle(dev_priv); |
40ae4e16 ID |
5743 | } |
5744 | ||
9c52d1c8 CW |
5745 | static void i915_gem_init__mm(struct drm_i915_private *i915) |
5746 | { | |
5747 | spin_lock_init(&i915->mm.object_stat_lock); | |
5748 | spin_lock_init(&i915->mm.obj_lock); | |
5749 | spin_lock_init(&i915->mm.free_lock); | |
5750 | ||
5751 | init_llist_head(&i915->mm.free_list); | |
5752 | ||
5753 | INIT_LIST_HEAD(&i915->mm.unbound_list); | |
5754 | INIT_LIST_HEAD(&i915->mm.bound_list); | |
5755 | INIT_LIST_HEAD(&i915->mm.fence_list); | |
5756 | INIT_LIST_HEAD(&i915->mm.userfault_list); | |
5757 | ||
5758 | INIT_WORK(&i915->mm.free_work, __i915_gem_free_work); | |
5759 | } | |
5760 | ||
a0de908d | 5761 | int i915_gem_init_early(struct drm_i915_private *dev_priv) |
673a394b | 5762 | { |
a933568e | 5763 | int err = -ENOMEM; |
42dcedd4 | 5764 | |
a933568e TU |
5765 | dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN); |
5766 | if (!dev_priv->objects) | |
73cb9701 | 5767 | goto err_out; |
73cb9701 | 5768 | |
a933568e TU |
5769 | dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN); |
5770 | if (!dev_priv->vmas) | |
73cb9701 | 5771 | goto err_objects; |
73cb9701 | 5772 | |
d1b48c1e CW |
5773 | dev_priv->luts = KMEM_CACHE(i915_lut_handle, 0); |
5774 | if (!dev_priv->luts) | |
5775 | goto err_vmas; | |
5776 | ||
e61e0f51 | 5777 | dev_priv->requests = KMEM_CACHE(i915_request, |
a933568e TU |
5778 | SLAB_HWCACHE_ALIGN | |
5779 | SLAB_RECLAIM_ACCOUNT | | |
5f0d5a3a | 5780 | SLAB_TYPESAFE_BY_RCU); |
a933568e | 5781 | if (!dev_priv->requests) |
d1b48c1e | 5782 | goto err_luts; |
73cb9701 | 5783 | |
52e54209 CW |
5784 | dev_priv->dependencies = KMEM_CACHE(i915_dependency, |
5785 | SLAB_HWCACHE_ALIGN | | |
5786 | SLAB_RECLAIM_ACCOUNT); | |
5787 | if (!dev_priv->dependencies) | |
5788 | goto err_requests; | |
5789 | ||
c5cf9a91 CW |
5790 | dev_priv->priorities = KMEM_CACHE(i915_priolist, SLAB_HWCACHE_ALIGN); |
5791 | if (!dev_priv->priorities) | |
5792 | goto err_dependencies; | |
5793 | ||
73cb9701 | 5794 | INIT_LIST_HEAD(&dev_priv->gt.timelines); |
643b450a | 5795 | INIT_LIST_HEAD(&dev_priv->gt.active_rings); |
3365e226 | 5796 | INIT_LIST_HEAD(&dev_priv->gt.closed_vma); |
643b450a | 5797 | |
9c52d1c8 | 5798 | i915_gem_init__mm(dev_priv); |
f2123818 | 5799 | |
67d97da3 | 5800 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 5801 | i915_gem_retire_work_handler); |
67d97da3 | 5802 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 5803 | i915_gem_idle_work_handler); |
1f15b76f | 5804 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 5805 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 5806 | |
6f633402 JL |
5807 | atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); |
5808 | ||
b5add959 | 5809 | spin_lock_init(&dev_priv->fb_tracking.lock); |
73cb9701 | 5810 | |
465c403c MA |
5811 | err = i915_gemfs_init(dev_priv); |
5812 | if (err) | |
5813 | DRM_NOTE("Unable to create a private tmpfs mount, hugepage support will be disabled(%d).\n", err); | |
5814 | ||
73cb9701 CW |
5815 | return 0; |
5816 | ||
52e54209 CW |
5817 | err_dependencies: |
5818 | kmem_cache_destroy(dev_priv->dependencies); | |
73cb9701 CW |
5819 | err_requests: |
5820 | kmem_cache_destroy(dev_priv->requests); | |
d1b48c1e CW |
5821 | err_luts: |
5822 | kmem_cache_destroy(dev_priv->luts); | |
73cb9701 CW |
5823 | err_vmas: |
5824 | kmem_cache_destroy(dev_priv->vmas); | |
5825 | err_objects: | |
5826 | kmem_cache_destroy(dev_priv->objects); | |
5827 | err_out: | |
5828 | return err; | |
673a394b | 5829 | } |
71acb5eb | 5830 | |
a0de908d | 5831 | void i915_gem_cleanup_early(struct drm_i915_private *dev_priv) |
d64aa096 | 5832 | { |
c4d4c1c6 | 5833 | i915_gem_drain_freed_objects(dev_priv); |
c9c70471 CW |
5834 | GEM_BUG_ON(!llist_empty(&dev_priv->mm.free_list)); |
5835 | GEM_BUG_ON(atomic_read(&dev_priv->mm.free_count)); | |
c4d4c1c6 | 5836 | WARN_ON(dev_priv->mm.object_count); |
ea84aa77 | 5837 | WARN_ON(!list_empty(&dev_priv->gt.timelines)); |
ea84aa77 | 5838 | |
c5cf9a91 | 5839 | kmem_cache_destroy(dev_priv->priorities); |
52e54209 | 5840 | kmem_cache_destroy(dev_priv->dependencies); |
d64aa096 | 5841 | kmem_cache_destroy(dev_priv->requests); |
d1b48c1e | 5842 | kmem_cache_destroy(dev_priv->luts); |
d64aa096 ID |
5843 | kmem_cache_destroy(dev_priv->vmas); |
5844 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
5845 | |
5846 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
5847 | rcu_barrier(); | |
465c403c MA |
5848 | |
5849 | i915_gemfs_fini(dev_priv); | |
d64aa096 ID |
5850 | } |
5851 | ||
6a800eab CW |
5852 | int i915_gem_freeze(struct drm_i915_private *dev_priv) |
5853 | { | |
d0aa301a CW |
5854 | /* Discard all purgeable objects, let userspace recover those as |
5855 | * required after resuming. | |
5856 | */ | |
6a800eab | 5857 | i915_gem_shrink_all(dev_priv); |
6a800eab | 5858 | |
6a800eab CW |
5859 | return 0; |
5860 | } | |
5861 | ||
95c778da | 5862 | int i915_gem_freeze_late(struct drm_i915_private *i915) |
461fb99c CW |
5863 | { |
5864 | struct drm_i915_gem_object *obj; | |
7aab2d53 | 5865 | struct list_head *phases[] = { |
95c778da CW |
5866 | &i915->mm.unbound_list, |
5867 | &i915->mm.bound_list, | |
7aab2d53 | 5868 | NULL |
95c778da | 5869 | }, **phase; |
461fb99c | 5870 | |
95c778da CW |
5871 | /* |
5872 | * Called just before we write the hibernation image. | |
461fb99c CW |
5873 | * |
5874 | * We need to update the domain tracking to reflect that the CPU | |
5875 | * will be accessing all the pages to create and restore from the | |
5876 | * hibernation, and so upon restoration those pages will be in the | |
5877 | * CPU domain. | |
5878 | * | |
5879 | * To make sure the hibernation image contains the latest state, | |
5880 | * we update that state just before writing out the image. | |
7aab2d53 CW |
5881 | * |
5882 | * To try and reduce the hibernation image, we manually shrink | |
d0aa301a | 5883 | * the objects as well, see i915_gem_freeze() |
461fb99c CW |
5884 | */ |
5885 | ||
95c778da CW |
5886 | i915_gem_shrink(i915, -1UL, NULL, I915_SHRINK_UNBOUND); |
5887 | i915_gem_drain_freed_objects(i915); | |
461fb99c | 5888 | |
95c778da CW |
5889 | mutex_lock(&i915->drm.struct_mutex); |
5890 | for (phase = phases; *phase; phase++) { | |
5891 | list_for_each_entry(obj, *phase, mm.link) | |
5892 | WARN_ON(i915_gem_object_set_to_cpu_domain(obj, true)); | |
461fb99c | 5893 | } |
95c778da | 5894 | mutex_unlock(&i915->drm.struct_mutex); |
461fb99c CW |
5895 | |
5896 | return 0; | |
5897 | } | |
5898 | ||
f787a5f5 | 5899 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5900 | { |
f787a5f5 | 5901 | struct drm_i915_file_private *file_priv = file->driver_priv; |
e61e0f51 | 5902 | struct i915_request *request; |
b962442e EA |
5903 | |
5904 | /* Clean up our request list when the client is going away, so that | |
5905 | * later retire_requests won't dereference our soon-to-be-gone | |
5906 | * file_priv. | |
5907 | */ | |
1c25595f | 5908 | spin_lock(&file_priv->mm.lock); |
c8659efa | 5909 | list_for_each_entry(request, &file_priv->mm.request_list, client_link) |
f787a5f5 | 5910 | request->file_priv = NULL; |
1c25595f | 5911 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 CW |
5912 | } |
5913 | ||
829a0af2 | 5914 | int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file) |
b29c19b6 CW |
5915 | { |
5916 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5917 | int ret; |
b29c19b6 | 5918 | |
c4c29d7b | 5919 | DRM_DEBUG("\n"); |
b29c19b6 CW |
5920 | |
5921 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5922 | if (!file_priv) | |
5923 | return -ENOMEM; | |
5924 | ||
5925 | file->driver_priv = file_priv; | |
829a0af2 | 5926 | file_priv->dev_priv = i915; |
ab0e7ff9 | 5927 | file_priv->file = file; |
b29c19b6 CW |
5928 | |
5929 | spin_lock_init(&file_priv->mm.lock); | |
5930 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 5931 | |
c80ff16e | 5932 | file_priv->bsd_engine = -1; |
14921f3c | 5933 | file_priv->hang_timestamp = jiffies; |
de1add36 | 5934 | |
829a0af2 | 5935 | ret = i915_gem_context_open(i915, file); |
e422b888 BW |
5936 | if (ret) |
5937 | kfree(file_priv); | |
b29c19b6 | 5938 | |
e422b888 | 5939 | return ret; |
b29c19b6 CW |
5940 | } |
5941 | ||
b680c37a DV |
5942 | /** |
5943 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
5944 | * @old: current GEM buffer for the frontbuffer slots |
5945 | * @new: new GEM buffer for the frontbuffer slots | |
5946 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
5947 | * |
5948 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5949 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5950 | */ | |
a071fa00 DV |
5951 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5952 | struct drm_i915_gem_object *new, | |
5953 | unsigned frontbuffer_bits) | |
5954 | { | |
faf5bf0a CW |
5955 | /* Control of individual bits within the mask are guarded by |
5956 | * the owning plane->mutex, i.e. we can never see concurrent | |
5957 | * manipulation of individual bits. But since the bitfield as a whole | |
5958 | * is updated using RMW, we need to use atomics in order to update | |
5959 | * the bits. | |
5960 | */ | |
5961 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
5962 | sizeof(atomic_t) * BITS_PER_BYTE); | |
5963 | ||
a071fa00 | 5964 | if (old) { |
faf5bf0a CW |
5965 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
5966 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
5967 | } |
5968 | ||
5969 | if (new) { | |
faf5bf0a CW |
5970 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
5971 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
5972 | } |
5973 | } | |
5974 | ||
ea70299d DG |
5975 | /* Allocate a new GEM object and fill it with the supplied data */ |
5976 | struct drm_i915_gem_object * | |
12d79d78 | 5977 | i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, |
ea70299d DG |
5978 | const void *data, size_t size) |
5979 | { | |
5980 | struct drm_i915_gem_object *obj; | |
be062fa4 CW |
5981 | struct file *file; |
5982 | size_t offset; | |
5983 | int err; | |
ea70299d | 5984 | |
12d79d78 | 5985 | obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE)); |
fe3db79b | 5986 | if (IS_ERR(obj)) |
ea70299d DG |
5987 | return obj; |
5988 | ||
c0a51fd0 | 5989 | GEM_BUG_ON(obj->write_domain != I915_GEM_DOMAIN_CPU); |
ea70299d | 5990 | |
be062fa4 CW |
5991 | file = obj->base.filp; |
5992 | offset = 0; | |
5993 | do { | |
5994 | unsigned int len = min_t(typeof(size), size, PAGE_SIZE); | |
5995 | struct page *page; | |
5996 | void *pgdata, *vaddr; | |
ea70299d | 5997 | |
be062fa4 CW |
5998 | err = pagecache_write_begin(file, file->f_mapping, |
5999 | offset, len, 0, | |
6000 | &page, &pgdata); | |
6001 | if (err < 0) | |
6002 | goto fail; | |
ea70299d | 6003 | |
be062fa4 CW |
6004 | vaddr = kmap(page); |
6005 | memcpy(vaddr, data, len); | |
6006 | kunmap(page); | |
6007 | ||
6008 | err = pagecache_write_end(file, file->f_mapping, | |
6009 | offset, len, len, | |
6010 | page, pgdata); | |
6011 | if (err < 0) | |
6012 | goto fail; | |
6013 | ||
6014 | size -= len; | |
6015 | data += len; | |
6016 | offset += len; | |
6017 | } while (size); | |
ea70299d DG |
6018 | |
6019 | return obj; | |
6020 | ||
6021 | fail: | |
f8c417cd | 6022 | i915_gem_object_put(obj); |
be062fa4 | 6023 | return ERR_PTR(err); |
ea70299d | 6024 | } |
96d77634 CW |
6025 | |
6026 | struct scatterlist * | |
6027 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
6028 | unsigned int n, | |
6029 | unsigned int *offset) | |
6030 | { | |
a4f5ea64 | 6031 | struct i915_gem_object_page_iter *iter = &obj->mm.get_page; |
96d77634 CW |
6032 | struct scatterlist *sg; |
6033 | unsigned int idx, count; | |
6034 | ||
6035 | might_sleep(); | |
6036 | GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT); | |
a4f5ea64 | 6037 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
96d77634 CW |
6038 | |
6039 | /* As we iterate forward through the sg, we record each entry in a | |
6040 | * radixtree for quick repeated (backwards) lookups. If we have seen | |
6041 | * this index previously, we will have an entry for it. | |
6042 | * | |
6043 | * Initial lookup is O(N), but this is amortized to O(1) for | |
6044 | * sequential page access (where each new request is consecutive | |
6045 | * to the previous one). Repeated lookups are O(lg(obj->base.size)), | |
6046 | * i.e. O(1) with a large constant! | |
6047 | */ | |
6048 | if (n < READ_ONCE(iter->sg_idx)) | |
6049 | goto lookup; | |
6050 | ||
6051 | mutex_lock(&iter->lock); | |
6052 | ||
6053 | /* We prefer to reuse the last sg so that repeated lookup of this | |
6054 | * (or the subsequent) sg are fast - comparing against the last | |
6055 | * sg is faster than going through the radixtree. | |
6056 | */ | |
6057 | ||
6058 | sg = iter->sg_pos; | |
6059 | idx = iter->sg_idx; | |
6060 | count = __sg_page_count(sg); | |
6061 | ||
6062 | while (idx + count <= n) { | |
6063 | unsigned long exception, i; | |
6064 | int ret; | |
6065 | ||
6066 | /* If we cannot allocate and insert this entry, or the | |
6067 | * individual pages from this range, cancel updating the | |
6068 | * sg_idx so that on this lookup we are forced to linearly | |
6069 | * scan onwards, but on future lookups we will try the | |
6070 | * insertion again (in which case we need to be careful of | |
6071 | * the error return reporting that we have already inserted | |
6072 | * this index). | |
6073 | */ | |
6074 | ret = radix_tree_insert(&iter->radix, idx, sg); | |
6075 | if (ret && ret != -EEXIST) | |
6076 | goto scan; | |
6077 | ||
6078 | exception = | |
6079 | RADIX_TREE_EXCEPTIONAL_ENTRY | | |
6080 | idx << RADIX_TREE_EXCEPTIONAL_SHIFT; | |
6081 | for (i = 1; i < count; i++) { | |
6082 | ret = radix_tree_insert(&iter->radix, idx + i, | |
6083 | (void *)exception); | |
6084 | if (ret && ret != -EEXIST) | |
6085 | goto scan; | |
6086 | } | |
6087 | ||
6088 | idx += count; | |
6089 | sg = ____sg_next(sg); | |
6090 | count = __sg_page_count(sg); | |
6091 | } | |
6092 | ||
6093 | scan: | |
6094 | iter->sg_pos = sg; | |
6095 | iter->sg_idx = idx; | |
6096 | ||
6097 | mutex_unlock(&iter->lock); | |
6098 | ||
6099 | if (unlikely(n < idx)) /* insertion completed by another thread */ | |
6100 | goto lookup; | |
6101 | ||
6102 | /* In case we failed to insert the entry into the radixtree, we need | |
6103 | * to look beyond the current sg. | |
6104 | */ | |
6105 | while (idx + count <= n) { | |
6106 | idx += count; | |
6107 | sg = ____sg_next(sg); | |
6108 | count = __sg_page_count(sg); | |
6109 | } | |
6110 | ||
6111 | *offset = n - idx; | |
6112 | return sg; | |
6113 | ||
6114 | lookup: | |
6115 | rcu_read_lock(); | |
6116 | ||
6117 | sg = radix_tree_lookup(&iter->radix, n); | |
6118 | GEM_BUG_ON(!sg); | |
6119 | ||
6120 | /* If this index is in the middle of multi-page sg entry, | |
6121 | * the radixtree will contain an exceptional entry that points | |
6122 | * to the start of that range. We will return the pointer to | |
6123 | * the base page and the offset of this page within the | |
6124 | * sg entry's range. | |
6125 | */ | |
6126 | *offset = 0; | |
6127 | if (unlikely(radix_tree_exception(sg))) { | |
6128 | unsigned long base = | |
6129 | (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT; | |
6130 | ||
6131 | sg = radix_tree_lookup(&iter->radix, base); | |
6132 | GEM_BUG_ON(!sg); | |
6133 | ||
6134 | *offset = n - base; | |
6135 | } | |
6136 | ||
6137 | rcu_read_unlock(); | |
6138 | ||
6139 | return sg; | |
6140 | } | |
6141 | ||
6142 | struct page * | |
6143 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n) | |
6144 | { | |
6145 | struct scatterlist *sg; | |
6146 | unsigned int offset; | |
6147 | ||
6148 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); | |
6149 | ||
6150 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
6151 | return nth_page(sg_page(sg), offset); | |
6152 | } | |
6153 | ||
6154 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ | |
6155 | struct page * | |
6156 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
6157 | unsigned int n) | |
6158 | { | |
6159 | struct page *page; | |
6160 | ||
6161 | page = i915_gem_object_get_page(obj, n); | |
a4f5ea64 | 6162 | if (!obj->mm.dirty) |
96d77634 CW |
6163 | set_page_dirty(page); |
6164 | ||
6165 | return page; | |
6166 | } | |
6167 | ||
6168 | dma_addr_t | |
6169 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
6170 | unsigned long n) | |
6171 | { | |
6172 | struct scatterlist *sg; | |
6173 | unsigned int offset; | |
6174 | ||
6175 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
6176 | return sg_dma_address(sg) + (offset << PAGE_SHIFT); | |
6177 | } | |
935a2f77 | 6178 | |
8eeb7906 CW |
6179 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align) |
6180 | { | |
6181 | struct sg_table *pages; | |
6182 | int err; | |
6183 | ||
6184 | if (align > obj->base.size) | |
6185 | return -EINVAL; | |
6186 | ||
6187 | if (obj->ops == &i915_gem_phys_ops) | |
6188 | return 0; | |
6189 | ||
6190 | if (obj->ops != &i915_gem_object_ops) | |
6191 | return -EINVAL; | |
6192 | ||
6193 | err = i915_gem_object_unbind(obj); | |
6194 | if (err) | |
6195 | return err; | |
6196 | ||
6197 | mutex_lock(&obj->mm.lock); | |
6198 | ||
6199 | if (obj->mm.madv != I915_MADV_WILLNEED) { | |
6200 | err = -EFAULT; | |
6201 | goto err_unlock; | |
6202 | } | |
6203 | ||
6204 | if (obj->mm.quirked) { | |
6205 | err = -EFAULT; | |
6206 | goto err_unlock; | |
6207 | } | |
6208 | ||
6209 | if (obj->mm.mapping) { | |
6210 | err = -EBUSY; | |
6211 | goto err_unlock; | |
6212 | } | |
6213 | ||
acd1c1e6 | 6214 | pages = __i915_gem_object_unset_pages(obj); |
f2123818 | 6215 | |
8eeb7906 CW |
6216 | obj->ops = &i915_gem_phys_ops; |
6217 | ||
8fb6a5df | 6218 | err = ____i915_gem_object_get_pages(obj); |
8eeb7906 CW |
6219 | if (err) |
6220 | goto err_xfer; | |
6221 | ||
6222 | /* Perma-pin (until release) the physical set of pages */ | |
6223 | __i915_gem_object_pin_pages(obj); | |
6224 | ||
6225 | if (!IS_ERR_OR_NULL(pages)) | |
6226 | i915_gem_object_ops.put_pages(obj, pages); | |
6227 | mutex_unlock(&obj->mm.lock); | |
6228 | return 0; | |
6229 | ||
6230 | err_xfer: | |
6231 | obj->ops = &i915_gem_object_ops; | |
acd1c1e6 CW |
6232 | if (!IS_ERR_OR_NULL(pages)) { |
6233 | unsigned int sg_page_sizes = i915_sg_page_sizes(pages->sgl); | |
6234 | ||
6235 | __i915_gem_object_set_pages(obj, pages, sg_page_sizes); | |
6236 | } | |
8eeb7906 CW |
6237 | err_unlock: |
6238 | mutex_unlock(&obj->mm.lock); | |
6239 | return err; | |
6240 | } | |
6241 | ||
935a2f77 CW |
6242 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) |
6243 | #include "selftests/scatterlist.c" | |
66d9cb5d | 6244 | #include "selftests/mock_gem_device.c" |
44653988 | 6245 | #include "selftests/huge_gem_object.c" |
4049866f | 6246 | #include "selftests/huge_pages.c" |
8335fd65 | 6247 | #include "selftests/i915_gem_object.c" |
17059450 | 6248 | #include "selftests/i915_gem_coherency.c" |
3f51b7e1 | 6249 | #include "selftests/i915_gem.c" |
935a2f77 | 6250 | #endif |