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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
5bab6f60 | 27 | #include <linux/stop_machine.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
76aaf220 | 30 | #include "i915_drv.h" |
5dda8fa3 | 31 | #include "i915_vgpu.h" |
76aaf220 DV |
32 | #include "i915_trace.h" |
33 | #include "intel_drv.h" | |
d07f0e59 | 34 | #include "intel_frontbuffer.h" |
76aaf220 | 35 | |
bb8f9cff CW |
36 | #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM) |
37 | ||
45f8f69a TU |
38 | /** |
39 | * DOC: Global GTT views | |
40 | * | |
41 | * Background and previous state | |
42 | * | |
43 | * Historically objects could exists (be bound) in global GTT space only as | |
44 | * singular instances with a view representing all of the object's backing pages | |
45 | * in a linear fashion. This view will be called a normal view. | |
46 | * | |
47 | * To support multiple views of the same object, where the number of mapped | |
48 | * pages is not equal to the backing store, or where the layout of the pages | |
49 | * is not linear, concept of a GGTT view was added. | |
50 | * | |
51 | * One example of an alternative view is a stereo display driven by a single | |
52 | * image. In this case we would have a framebuffer looking like this | |
53 | * (2x2 pages): | |
54 | * | |
55 | * 12 | |
56 | * 34 | |
57 | * | |
58 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
59 | * rendering. In contrast, fed to the display engine would be an alternative | |
60 | * view which could look something like this: | |
61 | * | |
62 | * 1212 | |
63 | * 3434 | |
64 | * | |
65 | * In this example both the size and layout of pages in the alternative view is | |
66 | * different from the normal view. | |
67 | * | |
68 | * Implementation and usage | |
69 | * | |
70 | * GGTT views are implemented using VMAs and are distinguished via enum | |
71 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
72 | * | |
73 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
74 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
75 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
76 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
77 | * |
78 | * As a helper for callers which are only interested in the normal view, | |
79 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
80 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
81 | * or with the normal GGTT view. | |
82 | * | |
83 | * Code wanting to add or use a new GGTT view needs to: | |
84 | * | |
85 | * 1. Add a new enum with a suitable name. | |
86 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
87 | * 3. Add support to i915_get_vma_pages(). | |
88 | * | |
89 | * New views are required to build a scatter-gather table from within the | |
90 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
91 | * exists for the lifetime of an VMA. | |
92 | * | |
93 | * Core API is designed to have copy semantics which means that passed in | |
94 | * struct i915_ggtt_view does not need to be persistent (left around after | |
95 | * calling the core API functions). | |
96 | * | |
97 | */ | |
98 | ||
70b9f6f8 DV |
99 | static int |
100 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
101 | ||
b5e16987 VS |
102 | const struct i915_ggtt_view i915_ggtt_view_normal = { |
103 | .type = I915_GGTT_VIEW_NORMAL, | |
104 | }; | |
9abc4648 | 105 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
b5e16987 | 106 | .type = I915_GGTT_VIEW_ROTATED, |
9abc4648 | 107 | }; |
fe14d5f4 | 108 | |
c033666a CW |
109 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
110 | int enable_ppgtt) | |
cfa7c862 | 111 | { |
1893a71b CW |
112 | bool has_aliasing_ppgtt; |
113 | bool has_full_ppgtt; | |
1f9a99e0 | 114 | bool has_full_48bit_ppgtt; |
1893a71b | 115 | |
9e1d0e60 MT |
116 | has_aliasing_ppgtt = dev_priv->info.has_aliasing_ppgtt; |
117 | has_full_ppgtt = dev_priv->info.has_full_ppgtt; | |
118 | has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt; | |
1893a71b | 119 | |
e320d400 ZW |
120 | if (intel_vgpu_active(dev_priv)) { |
121 | /* emulation is too hard */ | |
122 | has_full_ppgtt = false; | |
123 | has_full_48bit_ppgtt = false; | |
124 | } | |
71ba2d64 | 125 | |
0e4ca100 CW |
126 | if (!has_aliasing_ppgtt) |
127 | return 0; | |
128 | ||
70ee45e1 DL |
129 | /* |
130 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
131 | * execlists, the sole mechanism available to submit work. | |
132 | */ | |
c033666a | 133 | if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) |
cfa7c862 DV |
134 | return 0; |
135 | ||
136 | if (enable_ppgtt == 1) | |
137 | return 1; | |
138 | ||
1893a71b | 139 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
140 | return 2; |
141 | ||
1f9a99e0 MT |
142 | if (enable_ppgtt == 3 && has_full_48bit_ppgtt) |
143 | return 3; | |
144 | ||
93a25a9e DV |
145 | #ifdef CONFIG_INTEL_IOMMU |
146 | /* Disable ppgtt on SNB if VT-d is on. */ | |
c033666a | 147 | if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) { |
93a25a9e | 148 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
cfa7c862 | 149 | return 0; |
93a25a9e DV |
150 | } |
151 | #endif | |
152 | ||
62942ed7 | 153 | /* Early VLV doesn't have this */ |
91c8a326 | 154 | if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) { |
62942ed7 JB |
155 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
156 | return 0; | |
157 | } | |
158 | ||
e320d400 | 159 | if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) |
1f9a99e0 | 160 | return has_full_48bit_ppgtt ? 3 : 2; |
2f82bbdf MT |
161 | else |
162 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
163 | } |
164 | ||
70b9f6f8 DV |
165 | static int ppgtt_bind_vma(struct i915_vma *vma, |
166 | enum i915_cache_level cache_level, | |
167 | u32 unused) | |
47552659 DV |
168 | { |
169 | u32 pte_flags = 0; | |
170 | ||
a4f5ea64 | 171 | vma->pages = vma->obj->mm.pages; |
247177dd | 172 | |
47552659 DV |
173 | /* Currently applicable only to VLV */ |
174 | if (vma->obj->gt_ro) | |
175 | pte_flags |= PTE_READ_ONLY; | |
176 | ||
247177dd | 177 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
47552659 | 178 | cache_level, pte_flags); |
70b9f6f8 DV |
179 | |
180 | return 0; | |
47552659 DV |
181 | } |
182 | ||
183 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
184 | { | |
185 | vma->vm->clear_range(vma->vm, | |
186 | vma->node.start, | |
4fb84d99 | 187 | vma->size); |
47552659 | 188 | } |
6f65e29a | 189 | |
2c642b07 | 190 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
4fb84d99 | 191 | enum i915_cache_level level) |
94ec8f61 | 192 | { |
4fb84d99 | 193 | gen8_pte_t pte = _PAGE_PRESENT | _PAGE_RW; |
94ec8f61 | 194 | pte |= addr; |
63c42e56 BW |
195 | |
196 | switch (level) { | |
197 | case I915_CACHE_NONE: | |
fbe5d36e | 198 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
199 | break; |
200 | case I915_CACHE_WT: | |
201 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
202 | break; | |
203 | default: | |
204 | pte |= PPAT_CACHED_INDEX; | |
205 | break; | |
206 | } | |
207 | ||
94ec8f61 BW |
208 | return pte; |
209 | } | |
210 | ||
fe36f55d MK |
211 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
212 | const enum i915_cache_level level) | |
b1fe6673 | 213 | { |
07749ef3 | 214 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
215 | pde |= addr; |
216 | if (level != I915_CACHE_NONE) | |
217 | pde |= PPAT_CACHED_PDE_INDEX; | |
218 | else | |
219 | pde |= PPAT_UNCACHED_INDEX; | |
220 | return pde; | |
221 | } | |
222 | ||
762d9936 MT |
223 | #define gen8_pdpe_encode gen8_pde_encode |
224 | #define gen8_pml4e_encode gen8_pde_encode | |
225 | ||
07749ef3 MT |
226 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
227 | enum i915_cache_level level, | |
4fb84d99 | 228 | u32 unused) |
54d12527 | 229 | { |
4fb84d99 | 230 | gen6_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 231 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
232 | |
233 | switch (level) { | |
350ec881 CW |
234 | case I915_CACHE_L3_LLC: |
235 | case I915_CACHE_LLC: | |
236 | pte |= GEN6_PTE_CACHE_LLC; | |
237 | break; | |
238 | case I915_CACHE_NONE: | |
239 | pte |= GEN6_PTE_UNCACHED; | |
240 | break; | |
241 | default: | |
5f77eeb0 | 242 | MISSING_CASE(level); |
350ec881 CW |
243 | } |
244 | ||
245 | return pte; | |
246 | } | |
247 | ||
07749ef3 MT |
248 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
249 | enum i915_cache_level level, | |
4fb84d99 | 250 | u32 unused) |
350ec881 | 251 | { |
4fb84d99 | 252 | gen6_pte_t pte = GEN6_PTE_VALID; |
350ec881 CW |
253 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
254 | ||
255 | switch (level) { | |
256 | case I915_CACHE_L3_LLC: | |
257 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
258 | break; |
259 | case I915_CACHE_LLC: | |
260 | pte |= GEN6_PTE_CACHE_LLC; | |
261 | break; | |
262 | case I915_CACHE_NONE: | |
9119708c | 263 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
264 | break; |
265 | default: | |
5f77eeb0 | 266 | MISSING_CASE(level); |
e7210c3c BW |
267 | } |
268 | ||
54d12527 BW |
269 | return pte; |
270 | } | |
271 | ||
07749ef3 MT |
272 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
273 | enum i915_cache_level level, | |
4fb84d99 | 274 | u32 flags) |
93c34e70 | 275 | { |
4fb84d99 | 276 | gen6_pte_t pte = GEN6_PTE_VALID; |
93c34e70 KG |
277 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
278 | ||
24f3a8cf AG |
279 | if (!(flags & PTE_READ_ONLY)) |
280 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
281 | |
282 | if (level != I915_CACHE_NONE) | |
283 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
284 | ||
285 | return pte; | |
286 | } | |
287 | ||
07749ef3 MT |
288 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
289 | enum i915_cache_level level, | |
4fb84d99 | 290 | u32 unused) |
9119708c | 291 | { |
4fb84d99 | 292 | gen6_pte_t pte = GEN6_PTE_VALID; |
0d8ff15e | 293 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
294 | |
295 | if (level != I915_CACHE_NONE) | |
87a6b688 | 296 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
297 | |
298 | return pte; | |
299 | } | |
300 | ||
07749ef3 MT |
301 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
302 | enum i915_cache_level level, | |
4fb84d99 | 303 | u32 unused) |
4d15c145 | 304 | { |
4fb84d99 | 305 | gen6_pte_t pte = GEN6_PTE_VALID; |
4d15c145 BW |
306 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
307 | ||
651d794f CW |
308 | switch (level) { |
309 | case I915_CACHE_NONE: | |
310 | break; | |
311 | case I915_CACHE_WT: | |
c51e9701 | 312 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
313 | break; |
314 | default: | |
c51e9701 | 315 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
316 | break; |
317 | } | |
4d15c145 BW |
318 | |
319 | return pte; | |
320 | } | |
321 | ||
275a991c | 322 | static int __setup_page_dma(struct drm_i915_private *dev_priv, |
c114f76a | 323 | struct i915_page_dma *p, gfp_t flags) |
678d96fb | 324 | { |
275a991c | 325 | struct device *kdev = &dev_priv->drm.pdev->dev; |
678d96fb | 326 | |
c114f76a | 327 | p->page = alloc_page(flags); |
44159ddb MK |
328 | if (!p->page) |
329 | return -ENOMEM; | |
678d96fb | 330 | |
c49d13ee | 331 | p->daddr = dma_map_page(kdev, |
44159ddb | 332 | p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL); |
678d96fb | 333 | |
c49d13ee | 334 | if (dma_mapping_error(kdev, p->daddr)) { |
44159ddb MK |
335 | __free_page(p->page); |
336 | return -EINVAL; | |
337 | } | |
1266cdb1 MT |
338 | |
339 | return 0; | |
678d96fb BW |
340 | } |
341 | ||
275a991c TU |
342 | static int setup_page_dma(struct drm_i915_private *dev_priv, |
343 | struct i915_page_dma *p) | |
c114f76a | 344 | { |
275a991c | 345 | return __setup_page_dma(dev_priv, p, I915_GFP_DMA); |
c114f76a MK |
346 | } |
347 | ||
275a991c TU |
348 | static void cleanup_page_dma(struct drm_i915_private *dev_priv, |
349 | struct i915_page_dma *p) | |
06fda602 | 350 | { |
275a991c | 351 | struct pci_dev *pdev = dev_priv->drm.pdev; |
52a05c30 | 352 | |
44159ddb | 353 | if (WARN_ON(!p->page)) |
06fda602 | 354 | return; |
678d96fb | 355 | |
52a05c30 | 356 | dma_unmap_page(&pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL); |
44159ddb MK |
357 | __free_page(p->page); |
358 | memset(p, 0, sizeof(*p)); | |
359 | } | |
360 | ||
d1c54acd | 361 | static void *kmap_page_dma(struct i915_page_dma *p) |
73eeea53 | 362 | { |
d1c54acd MK |
363 | return kmap_atomic(p->page); |
364 | } | |
73eeea53 | 365 | |
d1c54acd MK |
366 | /* We use the flushing unmap only with ppgtt structures: |
367 | * page directories, page tables and scratch pages. | |
368 | */ | |
e2d214ae | 369 | static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr) |
d1c54acd | 370 | { |
73eeea53 MK |
371 | /* There are only few exceptions for gen >=6. chv and bxt. |
372 | * And we are not sure about the latter so play safe for now. | |
373 | */ | |
cc3f90f0 | 374 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
73eeea53 MK |
375 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
376 | ||
377 | kunmap_atomic(vaddr); | |
378 | } | |
379 | ||
567047be | 380 | #define kmap_px(px) kmap_page_dma(px_base(px)) |
e2d214ae | 381 | #define kunmap_px(ppgtt, vaddr) \ |
49d73912 | 382 | kunmap_page_dma((ppgtt)->base.i915, (vaddr)) |
d1c54acd | 383 | |
275a991c TU |
384 | #define setup_px(dev_priv, px) setup_page_dma((dev_priv), px_base(px)) |
385 | #define cleanup_px(dev_priv, px) cleanup_page_dma((dev_priv), px_base(px)) | |
e2d214ae TU |
386 | #define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v)) |
387 | #define fill32_px(dev_priv, px, v) \ | |
388 | fill_page_dma_32((dev_priv), px_base(px), (v)) | |
567047be | 389 | |
e2d214ae TU |
390 | static void fill_page_dma(struct drm_i915_private *dev_priv, |
391 | struct i915_page_dma *p, const uint64_t val) | |
d1c54acd MK |
392 | { |
393 | int i; | |
394 | uint64_t * const vaddr = kmap_page_dma(p); | |
395 | ||
396 | for (i = 0; i < 512; i++) | |
397 | vaddr[i] = val; | |
398 | ||
e2d214ae | 399 | kunmap_page_dma(dev_priv, vaddr); |
d1c54acd MK |
400 | } |
401 | ||
e2d214ae TU |
402 | static void fill_page_dma_32(struct drm_i915_private *dev_priv, |
403 | struct i915_page_dma *p, const uint32_t val32) | |
73eeea53 MK |
404 | { |
405 | uint64_t v = val32; | |
406 | ||
407 | v = v << 32 | val32; | |
408 | ||
e2d214ae | 409 | fill_page_dma(dev_priv, p, v); |
73eeea53 MK |
410 | } |
411 | ||
8bcdd0f7 | 412 | static int |
275a991c | 413 | setup_scratch_page(struct drm_i915_private *dev_priv, |
bb8f9cff CW |
414 | struct i915_page_dma *scratch, |
415 | gfp_t gfp) | |
4ad2af1e | 416 | { |
275a991c | 417 | return __setup_page_dma(dev_priv, scratch, gfp | __GFP_ZERO); |
4ad2af1e MK |
418 | } |
419 | ||
275a991c | 420 | static void cleanup_scratch_page(struct drm_i915_private *dev_priv, |
8bcdd0f7 | 421 | struct i915_page_dma *scratch) |
4ad2af1e | 422 | { |
275a991c | 423 | cleanup_page_dma(dev_priv, scratch); |
4ad2af1e MK |
424 | } |
425 | ||
275a991c | 426 | static struct i915_page_table *alloc_pt(struct drm_i915_private *dev_priv) |
06fda602 | 427 | { |
ec565b3c | 428 | struct i915_page_table *pt; |
275a991c | 429 | const size_t count = INTEL_GEN(dev_priv) >= 8 ? GEN8_PTES : GEN6_PTES; |
678d96fb | 430 | int ret = -ENOMEM; |
06fda602 BW |
431 | |
432 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
433 | if (!pt) | |
434 | return ERR_PTR(-ENOMEM); | |
435 | ||
678d96fb BW |
436 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
437 | GFP_KERNEL); | |
438 | ||
439 | if (!pt->used_ptes) | |
440 | goto fail_bitmap; | |
441 | ||
275a991c | 442 | ret = setup_px(dev_priv, pt); |
678d96fb | 443 | if (ret) |
44159ddb | 444 | goto fail_page_m; |
06fda602 BW |
445 | |
446 | return pt; | |
678d96fb | 447 | |
44159ddb | 448 | fail_page_m: |
678d96fb BW |
449 | kfree(pt->used_ptes); |
450 | fail_bitmap: | |
451 | kfree(pt); | |
452 | ||
453 | return ERR_PTR(ret); | |
06fda602 BW |
454 | } |
455 | ||
275a991c TU |
456 | static void free_pt(struct drm_i915_private *dev_priv, |
457 | struct i915_page_table *pt) | |
06fda602 | 458 | { |
275a991c | 459 | cleanup_px(dev_priv, pt); |
2e906bea MK |
460 | kfree(pt->used_ptes); |
461 | kfree(pt); | |
462 | } | |
463 | ||
464 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
465 | struct i915_page_table *pt) | |
466 | { | |
467 | gen8_pte_t scratch_pte; | |
468 | ||
8bcdd0f7 | 469 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 470 | I915_CACHE_LLC); |
2e906bea | 471 | |
49d73912 | 472 | fill_px(vm->i915, pt, scratch_pte); |
2e906bea MK |
473 | } |
474 | ||
475 | static void gen6_initialize_pt(struct i915_address_space *vm, | |
476 | struct i915_page_table *pt) | |
477 | { | |
478 | gen6_pte_t scratch_pte; | |
479 | ||
8bcdd0f7 | 480 | WARN_ON(vm->scratch_page.daddr == 0); |
2e906bea | 481 | |
8bcdd0f7 | 482 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 483 | I915_CACHE_LLC, 0); |
2e906bea | 484 | |
49d73912 | 485 | fill32_px(vm->i915, pt, scratch_pte); |
06fda602 BW |
486 | } |
487 | ||
275a991c | 488 | static struct i915_page_directory *alloc_pd(struct drm_i915_private *dev_priv) |
06fda602 | 489 | { |
ec565b3c | 490 | struct i915_page_directory *pd; |
33c8819f | 491 | int ret = -ENOMEM; |
06fda602 BW |
492 | |
493 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
494 | if (!pd) | |
495 | return ERR_PTR(-ENOMEM); | |
496 | ||
33c8819f MT |
497 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
498 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
499 | if (!pd->used_pdes) | |
a08e111a | 500 | goto fail_bitmap; |
33c8819f | 501 | |
275a991c | 502 | ret = setup_px(dev_priv, pd); |
33c8819f | 503 | if (ret) |
a08e111a | 504 | goto fail_page_m; |
e5815a2e | 505 | |
06fda602 | 506 | return pd; |
33c8819f | 507 | |
a08e111a | 508 | fail_page_m: |
33c8819f | 509 | kfree(pd->used_pdes); |
a08e111a | 510 | fail_bitmap: |
33c8819f MT |
511 | kfree(pd); |
512 | ||
513 | return ERR_PTR(ret); | |
06fda602 BW |
514 | } |
515 | ||
275a991c TU |
516 | static void free_pd(struct drm_i915_private *dev_priv, |
517 | struct i915_page_directory *pd) | |
2e906bea MK |
518 | { |
519 | if (px_page(pd)) { | |
275a991c | 520 | cleanup_px(dev_priv, pd); |
2e906bea MK |
521 | kfree(pd->used_pdes); |
522 | kfree(pd); | |
523 | } | |
524 | } | |
525 | ||
526 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
527 | struct i915_page_directory *pd) | |
528 | { | |
529 | gen8_pde_t scratch_pde; | |
530 | ||
531 | scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); | |
532 | ||
49d73912 | 533 | fill_px(vm->i915, pd, scratch_pde); |
2e906bea MK |
534 | } |
535 | ||
275a991c | 536 | static int __pdp_init(struct drm_i915_private *dev_priv, |
6ac18502 MT |
537 | struct i915_page_directory_pointer *pdp) |
538 | { | |
275a991c | 539 | size_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
6ac18502 MT |
540 | |
541 | pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes), | |
542 | sizeof(unsigned long), | |
543 | GFP_KERNEL); | |
544 | if (!pdp->used_pdpes) | |
545 | return -ENOMEM; | |
546 | ||
547 | pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory), | |
548 | GFP_KERNEL); | |
549 | if (!pdp->page_directory) { | |
550 | kfree(pdp->used_pdpes); | |
551 | /* the PDP might be the statically allocated top level. Keep it | |
552 | * as clean as possible */ | |
553 | pdp->used_pdpes = NULL; | |
554 | return -ENOMEM; | |
555 | } | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
560 | static void __pdp_fini(struct i915_page_directory_pointer *pdp) | |
561 | { | |
562 | kfree(pdp->used_pdpes); | |
563 | kfree(pdp->page_directory); | |
564 | pdp->page_directory = NULL; | |
565 | } | |
566 | ||
762d9936 | 567 | static struct |
275a991c | 568 | i915_page_directory_pointer *alloc_pdp(struct drm_i915_private *dev_priv) |
762d9936 MT |
569 | { |
570 | struct i915_page_directory_pointer *pdp; | |
571 | int ret = -ENOMEM; | |
572 | ||
275a991c | 573 | WARN_ON(!USES_FULL_48BIT_PPGTT(dev_priv)); |
762d9936 MT |
574 | |
575 | pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); | |
576 | if (!pdp) | |
577 | return ERR_PTR(-ENOMEM); | |
578 | ||
275a991c | 579 | ret = __pdp_init(dev_priv, pdp); |
762d9936 MT |
580 | if (ret) |
581 | goto fail_bitmap; | |
582 | ||
275a991c | 583 | ret = setup_px(dev_priv, pdp); |
762d9936 MT |
584 | if (ret) |
585 | goto fail_page_m; | |
586 | ||
587 | return pdp; | |
588 | ||
589 | fail_page_m: | |
590 | __pdp_fini(pdp); | |
591 | fail_bitmap: | |
592 | kfree(pdp); | |
593 | ||
594 | return ERR_PTR(ret); | |
595 | } | |
596 | ||
275a991c | 597 | static void free_pdp(struct drm_i915_private *dev_priv, |
6ac18502 MT |
598 | struct i915_page_directory_pointer *pdp) |
599 | { | |
600 | __pdp_fini(pdp); | |
275a991c TU |
601 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
602 | cleanup_px(dev_priv, pdp); | |
762d9936 MT |
603 | kfree(pdp); |
604 | } | |
605 | } | |
606 | ||
69ab76fd MT |
607 | static void gen8_initialize_pdp(struct i915_address_space *vm, |
608 | struct i915_page_directory_pointer *pdp) | |
609 | { | |
610 | gen8_ppgtt_pdpe_t scratch_pdpe; | |
611 | ||
612 | scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
613 | ||
49d73912 | 614 | fill_px(vm->i915, pdp, scratch_pdpe); |
69ab76fd MT |
615 | } |
616 | ||
617 | static void gen8_initialize_pml4(struct i915_address_space *vm, | |
618 | struct i915_pml4 *pml4) | |
619 | { | |
620 | gen8_ppgtt_pml4e_t scratch_pml4e; | |
621 | ||
622 | scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp), | |
623 | I915_CACHE_LLC); | |
624 | ||
49d73912 | 625 | fill_px(vm->i915, pml4, scratch_pml4e); |
69ab76fd MT |
626 | } |
627 | ||
762d9936 MT |
628 | static void |
629 | gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt, | |
630 | struct i915_page_directory_pointer *pdp, | |
631 | struct i915_page_directory *pd, | |
632 | int index) | |
633 | { | |
634 | gen8_ppgtt_pdpe_t *page_directorypo; | |
635 | ||
275a991c | 636 | if (!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev))) |
762d9936 MT |
637 | return; |
638 | ||
639 | page_directorypo = kmap_px(pdp); | |
640 | page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); | |
641 | kunmap_px(ppgtt, page_directorypo); | |
642 | } | |
643 | ||
644 | static void | |
645 | gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt, | |
646 | struct i915_pml4 *pml4, | |
647 | struct i915_page_directory_pointer *pdp, | |
648 | int index) | |
649 | { | |
650 | gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4); | |
651 | ||
275a991c | 652 | WARN_ON(!USES_FULL_48BIT_PPGTT(to_i915(ppgtt->base.dev))); |
762d9936 MT |
653 | pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); |
654 | kunmap_px(ppgtt, pagemap); | |
6ac18502 MT |
655 | } |
656 | ||
94e409c1 | 657 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 658 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
659 | unsigned entry, |
660 | dma_addr_t addr) | |
94e409c1 | 661 | { |
7e37f889 | 662 | struct intel_ring *ring = req->ring; |
4a570db5 | 663 | struct intel_engine_cs *engine = req->engine; |
94e409c1 BW |
664 | int ret; |
665 | ||
666 | BUG_ON(entry >= 4); | |
667 | ||
5fb9de1a | 668 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
669 | if (ret) |
670 | return ret; | |
671 | ||
b5321f30 CW |
672 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
673 | intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, entry)); | |
674 | intel_ring_emit(ring, upper_32_bits(addr)); | |
675 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
676 | intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, entry)); | |
677 | intel_ring_emit(ring, lower_32_bits(addr)); | |
678 | intel_ring_advance(ring); | |
94e409c1 BW |
679 | |
680 | return 0; | |
681 | } | |
682 | ||
2dba3239 MT |
683 | static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt, |
684 | struct drm_i915_gem_request *req) | |
94e409c1 | 685 | { |
eeb9488e | 686 | int i, ret; |
94e409c1 | 687 | |
7cb6d7ac | 688 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
689 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
690 | ||
e85b26dc | 691 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
692 | if (ret) |
693 | return ret; | |
94e409c1 | 694 | } |
d595bd4b | 695 | |
eeb9488e | 696 | return 0; |
94e409c1 BW |
697 | } |
698 | ||
2dba3239 MT |
699 | static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt, |
700 | struct drm_i915_gem_request *req) | |
701 | { | |
702 | return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4)); | |
703 | } | |
704 | ||
fce93755 MK |
705 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
706 | * the page table structures, we mark them dirty so that | |
707 | * context switching/execlist queuing code takes extra steps | |
708 | * to ensure that tlbs are flushed. | |
709 | */ | |
710 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
711 | { | |
49d73912 | 712 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask; |
fce93755 MK |
713 | } |
714 | ||
2ce5179f MW |
715 | /* Removes entries from a single page table, releasing it if it's empty. |
716 | * Caller can use the return value to update higher-level entries. | |
717 | */ | |
718 | static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm, | |
d209b9c3 MW |
719 | struct i915_page_table *pt, |
720 | uint64_t start, | |
721 | uint64_t length) | |
459108b8 | 722 | { |
e5716f55 | 723 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 | 724 | unsigned int num_entries = gen8_pte_count(start, length); |
37c63934 MK |
725 | unsigned int pte = gen8_pte_index(start); |
726 | unsigned int pte_end = pte + num_entries; | |
f9b5b782 | 727 | gen8_pte_t *pt_vaddr; |
d209b9c3 MW |
728 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
729 | I915_CACHE_LLC); | |
459108b8 | 730 | |
d209b9c3 | 731 | if (WARN_ON(!px_page(pt))) |
2ce5179f | 732 | return false; |
459108b8 | 733 | |
37c63934 MK |
734 | GEM_BUG_ON(pte_end > GEN8_PTES); |
735 | ||
736 | bitmap_clear(pt->used_ptes, pte, num_entries); | |
06fda602 | 737 | |
a18dbba8 | 738 | if (bitmap_empty(pt->used_ptes, GEN8_PTES)) |
2ce5179f | 739 | return true; |
2ce5179f | 740 | |
d209b9c3 MW |
741 | pt_vaddr = kmap_px(pt); |
742 | ||
37c63934 MK |
743 | while (pte < pte_end) |
744 | pt_vaddr[pte++] = scratch_pte; | |
06fda602 | 745 | |
d209b9c3 | 746 | kunmap_px(ppgtt, pt_vaddr); |
2ce5179f MW |
747 | |
748 | return false; | |
d209b9c3 | 749 | } |
06fda602 | 750 | |
2ce5179f MW |
751 | /* Removes entries from a single page dir, releasing it if it's empty. |
752 | * Caller can use the return value to update higher-level entries | |
753 | */ | |
754 | static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm, | |
d209b9c3 MW |
755 | struct i915_page_directory *pd, |
756 | uint64_t start, | |
757 | uint64_t length) | |
758 | { | |
2ce5179f | 759 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
760 | struct i915_page_table *pt; |
761 | uint64_t pde; | |
2ce5179f MW |
762 | gen8_pde_t *pde_vaddr; |
763 | gen8_pde_t scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), | |
764 | I915_CACHE_LLC); | |
d209b9c3 MW |
765 | |
766 | gen8_for_each_pde(pt, pd, start, length, pde) { | |
06fda602 | 767 | if (WARN_ON(!pd->page_table[pde])) |
00245266 | 768 | break; |
06fda602 | 769 | |
2ce5179f MW |
770 | if (gen8_ppgtt_clear_pt(vm, pt, start, length)) { |
771 | __clear_bit(pde, pd->used_pdes); | |
772 | pde_vaddr = kmap_px(pd); | |
773 | pde_vaddr[pde] = scratch_pde; | |
774 | kunmap_px(ppgtt, pde_vaddr); | |
49d73912 | 775 | free_pt(vm->i915, pt); |
2ce5179f MW |
776 | } |
777 | } | |
778 | ||
a18dbba8 | 779 | if (bitmap_empty(pd->used_pdes, I915_PDES)) |
2ce5179f | 780 | return true; |
2ce5179f MW |
781 | |
782 | return false; | |
d209b9c3 | 783 | } |
06fda602 | 784 | |
2ce5179f MW |
785 | /* Removes entries from a single page dir pointer, releasing it if it's empty. |
786 | * Caller can use the return value to update higher-level entries | |
787 | */ | |
788 | static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm, | |
d209b9c3 MW |
789 | struct i915_page_directory_pointer *pdp, |
790 | uint64_t start, | |
791 | uint64_t length) | |
792 | { | |
2ce5179f | 793 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
794 | struct i915_page_directory *pd; |
795 | uint64_t pdpe; | |
2ce5179f MW |
796 | gen8_ppgtt_pdpe_t *pdpe_vaddr; |
797 | gen8_ppgtt_pdpe_t scratch_pdpe = | |
798 | gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
06fda602 | 799 | |
d209b9c3 MW |
800 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
801 | if (WARN_ON(!pdp->page_directory[pdpe])) | |
802 | break; | |
459108b8 | 803 | |
2ce5179f MW |
804 | if (gen8_ppgtt_clear_pd(vm, pd, start, length)) { |
805 | __clear_bit(pdpe, pdp->used_pdpes); | |
275a991c | 806 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
2ce5179f MW |
807 | pdpe_vaddr = kmap_px(pdp); |
808 | pdpe_vaddr[pdpe] = scratch_pdpe; | |
809 | kunmap_px(ppgtt, pdpe_vaddr); | |
810 | } | |
49d73912 | 811 | free_pd(vm->i915, pd); |
2ce5179f MW |
812 | } |
813 | } | |
814 | ||
fce93755 MK |
815 | mark_tlbs_dirty(ppgtt); |
816 | ||
a18dbba8 | 817 | if (bitmap_empty(pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv))) |
2ce5179f | 818 | return true; |
2ce5179f MW |
819 | |
820 | return false; | |
d209b9c3 | 821 | } |
459108b8 | 822 | |
2ce5179f MW |
823 | /* Removes entries from a single pml4. |
824 | * This is the top-level structure in 4-level page tables used on gen8+. | |
825 | * Empty entries are always scratch pml4e. | |
826 | */ | |
d209b9c3 MW |
827 | static void gen8_ppgtt_clear_pml4(struct i915_address_space *vm, |
828 | struct i915_pml4 *pml4, | |
829 | uint64_t start, | |
830 | uint64_t length) | |
831 | { | |
2ce5179f | 832 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
d209b9c3 MW |
833 | struct i915_page_directory_pointer *pdp; |
834 | uint64_t pml4e; | |
2ce5179f MW |
835 | gen8_ppgtt_pml4e_t *pml4e_vaddr; |
836 | gen8_ppgtt_pml4e_t scratch_pml4e = | |
837 | gen8_pml4e_encode(px_dma(vm->scratch_pdp), I915_CACHE_LLC); | |
838 | ||
49d73912 | 839 | GEM_BUG_ON(!USES_FULL_48BIT_PPGTT(vm->i915)); |
459108b8 | 840 | |
d209b9c3 MW |
841 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
842 | if (WARN_ON(!pml4->pdps[pml4e])) | |
843 | break; | |
459108b8 | 844 | |
2ce5179f MW |
845 | if (gen8_ppgtt_clear_pdp(vm, pdp, start, length)) { |
846 | __clear_bit(pml4e, pml4->used_pml4es); | |
847 | pml4e_vaddr = kmap_px(pml4); | |
848 | pml4e_vaddr[pml4e] = scratch_pml4e; | |
849 | kunmap_px(ppgtt, pml4e_vaddr); | |
49d73912 | 850 | free_pdp(vm->i915, pdp); |
2ce5179f | 851 | } |
459108b8 BW |
852 | } |
853 | } | |
854 | ||
f9b5b782 | 855 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
4fb84d99 | 856 | uint64_t start, uint64_t length) |
9df15b49 | 857 | { |
e5716f55 | 858 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
f9b5b782 | 859 | |
c6385c94 | 860 | if (USES_FULL_48BIT_PPGTT(vm->i915)) |
d209b9c3 MW |
861 | gen8_ppgtt_clear_pml4(vm, &ppgtt->pml4, start, length); |
862 | else | |
863 | gen8_ppgtt_clear_pdp(vm, &ppgtt->pdp, start, length); | |
f9b5b782 MT |
864 | } |
865 | ||
866 | static void | |
867 | gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, | |
868 | struct i915_page_directory_pointer *pdp, | |
3387d433 | 869 | struct sg_page_iter *sg_iter, |
f9b5b782 MT |
870 | uint64_t start, |
871 | enum i915_cache_level cache_level) | |
872 | { | |
e5716f55 | 873 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 874 | gen8_pte_t *pt_vaddr; |
de5ba8eb MT |
875 | unsigned pdpe = gen8_pdpe_index(start); |
876 | unsigned pde = gen8_pde_index(start); | |
877 | unsigned pte = gen8_pte_index(start); | |
9df15b49 | 878 | |
6f1cc993 | 879 | pt_vaddr = NULL; |
7ad47cf2 | 880 | |
3387d433 | 881 | while (__sg_page_iter_next(sg_iter)) { |
d7b3de91 | 882 | if (pt_vaddr == NULL) { |
d4ec9da0 | 883 | struct i915_page_directory *pd = pdp->page_directory[pdpe]; |
ec565b3c | 884 | struct i915_page_table *pt = pd->page_table[pde]; |
d1c54acd | 885 | pt_vaddr = kmap_px(pt); |
d7b3de91 | 886 | } |
9df15b49 | 887 | |
7ad47cf2 | 888 | pt_vaddr[pte] = |
3387d433 | 889 | gen8_pte_encode(sg_page_iter_dma_address(sg_iter), |
4fb84d99 | 890 | cache_level); |
07749ef3 | 891 | if (++pte == GEN8_PTES) { |
d1c54acd | 892 | kunmap_px(ppgtt, pt_vaddr); |
6f1cc993 | 893 | pt_vaddr = NULL; |
07749ef3 | 894 | if (++pde == I915_PDES) { |
c6385c94 | 895 | if (++pdpe == I915_PDPES_PER_PDP(vm->i915)) |
de5ba8eb | 896 | break; |
7ad47cf2 BW |
897 | pde = 0; |
898 | } | |
899 | pte = 0; | |
9df15b49 BW |
900 | } |
901 | } | |
d1c54acd MK |
902 | |
903 | if (pt_vaddr) | |
904 | kunmap_px(ppgtt, pt_vaddr); | |
9df15b49 BW |
905 | } |
906 | ||
f9b5b782 MT |
907 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
908 | struct sg_table *pages, | |
909 | uint64_t start, | |
910 | enum i915_cache_level cache_level, | |
911 | u32 unused) | |
912 | { | |
e5716f55 | 913 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3387d433 | 914 | struct sg_page_iter sg_iter; |
f9b5b782 | 915 | |
3387d433 | 916 | __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0); |
de5ba8eb | 917 | |
c6385c94 | 918 | if (!USES_FULL_48BIT_PPGTT(vm->i915)) { |
de5ba8eb MT |
919 | gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start, |
920 | cache_level); | |
921 | } else { | |
922 | struct i915_page_directory_pointer *pdp; | |
e8ebd8e2 | 923 | uint64_t pml4e; |
de5ba8eb MT |
924 | uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT; |
925 | ||
e8ebd8e2 | 926 | gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) { |
de5ba8eb MT |
927 | gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter, |
928 | start, cache_level); | |
929 | } | |
930 | } | |
f9b5b782 MT |
931 | } |
932 | ||
275a991c | 933 | static void gen8_free_page_tables(struct drm_i915_private *dev_priv, |
f37c0505 | 934 | struct i915_page_directory *pd) |
7ad47cf2 BW |
935 | { |
936 | int i; | |
937 | ||
567047be | 938 | if (!px_page(pd)) |
7ad47cf2 BW |
939 | return; |
940 | ||
33c8819f | 941 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
942 | if (WARN_ON(!pd->page_table[i])) |
943 | continue; | |
7ad47cf2 | 944 | |
275a991c | 945 | free_pt(dev_priv, pd->page_table[i]); |
06fda602 BW |
946 | pd->page_table[i] = NULL; |
947 | } | |
d7b3de91 BW |
948 | } |
949 | ||
8776f02b MK |
950 | static int gen8_init_scratch(struct i915_address_space *vm) |
951 | { | |
49d73912 | 952 | struct drm_i915_private *dev_priv = vm->i915; |
64c050db | 953 | int ret; |
8776f02b | 954 | |
275a991c | 955 | ret = setup_scratch_page(dev_priv, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
956 | if (ret) |
957 | return ret; | |
8776f02b | 958 | |
275a991c | 959 | vm->scratch_pt = alloc_pt(dev_priv); |
8776f02b | 960 | if (IS_ERR(vm->scratch_pt)) { |
64c050db MA |
961 | ret = PTR_ERR(vm->scratch_pt); |
962 | goto free_scratch_page; | |
8776f02b MK |
963 | } |
964 | ||
275a991c | 965 | vm->scratch_pd = alloc_pd(dev_priv); |
8776f02b | 966 | if (IS_ERR(vm->scratch_pd)) { |
64c050db MA |
967 | ret = PTR_ERR(vm->scratch_pd); |
968 | goto free_pt; | |
8776f02b MK |
969 | } |
970 | ||
275a991c TU |
971 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
972 | vm->scratch_pdp = alloc_pdp(dev_priv); | |
69ab76fd | 973 | if (IS_ERR(vm->scratch_pdp)) { |
64c050db MA |
974 | ret = PTR_ERR(vm->scratch_pdp); |
975 | goto free_pd; | |
69ab76fd MT |
976 | } |
977 | } | |
978 | ||
8776f02b MK |
979 | gen8_initialize_pt(vm, vm->scratch_pt); |
980 | gen8_initialize_pd(vm, vm->scratch_pd); | |
275a991c | 981 | if (USES_FULL_48BIT_PPGTT(dev_priv)) |
69ab76fd | 982 | gen8_initialize_pdp(vm, vm->scratch_pdp); |
8776f02b MK |
983 | |
984 | return 0; | |
64c050db MA |
985 | |
986 | free_pd: | |
275a991c | 987 | free_pd(dev_priv, vm->scratch_pd); |
64c050db | 988 | free_pt: |
275a991c | 989 | free_pt(dev_priv, vm->scratch_pt); |
64c050db | 990 | free_scratch_page: |
275a991c | 991 | cleanup_scratch_page(dev_priv, &vm->scratch_page); |
64c050db MA |
992 | |
993 | return ret; | |
8776f02b MK |
994 | } |
995 | ||
650da34c ZL |
996 | static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) |
997 | { | |
998 | enum vgt_g2v_type msg; | |
49d73912 | 999 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
650da34c ZL |
1000 | int i; |
1001 | ||
df28564d | 1002 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
650da34c ZL |
1003 | u64 daddr = px_dma(&ppgtt->pml4); |
1004 | ||
ab75bb5d VS |
1005 | I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr)); |
1006 | I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1007 | |
1008 | msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : | |
1009 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); | |
1010 | } else { | |
1011 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
1012 | u64 daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1013 | ||
ab75bb5d VS |
1014 | I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr)); |
1015 | I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr)); | |
650da34c ZL |
1016 | } |
1017 | ||
1018 | msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : | |
1019 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); | |
1020 | } | |
1021 | ||
1022 | I915_WRITE(vgtif_reg(g2v_notify), msg); | |
1023 | ||
1024 | return 0; | |
1025 | } | |
1026 | ||
8776f02b MK |
1027 | static void gen8_free_scratch(struct i915_address_space *vm) |
1028 | { | |
49d73912 | 1029 | struct drm_i915_private *dev_priv = vm->i915; |
8776f02b | 1030 | |
275a991c TU |
1031 | if (USES_FULL_48BIT_PPGTT(dev_priv)) |
1032 | free_pdp(dev_priv, vm->scratch_pdp); | |
1033 | free_pd(dev_priv, vm->scratch_pd); | |
1034 | free_pt(dev_priv, vm->scratch_pt); | |
1035 | cleanup_scratch_page(dev_priv, &vm->scratch_page); | |
8776f02b MK |
1036 | } |
1037 | ||
275a991c | 1038 | static void gen8_ppgtt_cleanup_3lvl(struct drm_i915_private *dev_priv, |
762d9936 | 1039 | struct i915_page_directory_pointer *pdp) |
b45a6715 BW |
1040 | { |
1041 | int i; | |
1042 | ||
275a991c | 1043 | for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev_priv)) { |
d4ec9da0 | 1044 | if (WARN_ON(!pdp->page_directory[i])) |
06fda602 BW |
1045 | continue; |
1046 | ||
275a991c TU |
1047 | gen8_free_page_tables(dev_priv, pdp->page_directory[i]); |
1048 | free_pd(dev_priv, pdp->page_directory[i]); | |
7ad47cf2 | 1049 | } |
69876bed | 1050 | |
275a991c | 1051 | free_pdp(dev_priv, pdp); |
762d9936 MT |
1052 | } |
1053 | ||
1054 | static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) | |
1055 | { | |
49d73912 | 1056 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
762d9936 MT |
1057 | int i; |
1058 | ||
1059 | for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) { | |
1060 | if (WARN_ON(!ppgtt->pml4.pdps[i])) | |
1061 | continue; | |
1062 | ||
275a991c | 1063 | gen8_ppgtt_cleanup_3lvl(dev_priv, ppgtt->pml4.pdps[i]); |
762d9936 MT |
1064 | } |
1065 | ||
275a991c | 1066 | cleanup_px(dev_priv, &ppgtt->pml4); |
762d9936 MT |
1067 | } |
1068 | ||
1069 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) | |
1070 | { | |
49d73912 | 1071 | struct drm_i915_private *dev_priv = vm->i915; |
e5716f55 | 1072 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1073 | |
275a991c | 1074 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1075 | gen8_ppgtt_notify_vgt(ppgtt, false); |
1076 | ||
275a991c TU |
1077 | if (!USES_FULL_48BIT_PPGTT(dev_priv)) |
1078 | gen8_ppgtt_cleanup_3lvl(dev_priv, &ppgtt->pdp); | |
762d9936 MT |
1079 | else |
1080 | gen8_ppgtt_cleanup_4lvl(ppgtt); | |
d4ec9da0 | 1081 | |
8776f02b | 1082 | gen8_free_scratch(vm); |
b45a6715 BW |
1083 | } |
1084 | ||
d7b2633d MT |
1085 | /** |
1086 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
d4ec9da0 MT |
1087 | * @vm: Master vm structure. |
1088 | * @pd: Page directory for this address range. | |
d7b2633d | 1089 | * @start: Starting virtual address to begin allocations. |
d4ec9da0 | 1090 | * @length: Size of the allocations. |
d7b2633d MT |
1091 | * @new_pts: Bitmap set by function with new allocations. Likely used by the |
1092 | * caller to free on error. | |
1093 | * | |
1094 | * Allocate the required number of page tables. Extremely similar to | |
1095 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
1096 | * the page directory boundary (instead of the page directory pointer). That | |
1097 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
1098 | * possible, and likely that the caller will need to use multiple calls of this | |
1099 | * function to achieve the appropriate allocation. | |
1100 | * | |
1101 | * Return: 0 if success; negative error code otherwise. | |
1102 | */ | |
d4ec9da0 | 1103 | static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, |
e5815a2e | 1104 | struct i915_page_directory *pd, |
5441f0cb | 1105 | uint64_t start, |
d7b2633d MT |
1106 | uint64_t length, |
1107 | unsigned long *new_pts) | |
bf2b4ed2 | 1108 | { |
49d73912 | 1109 | struct drm_i915_private *dev_priv = vm->i915; |
d7b2633d | 1110 | struct i915_page_table *pt; |
5441f0cb | 1111 | uint32_t pde; |
bf2b4ed2 | 1112 | |
e8ebd8e2 | 1113 | gen8_for_each_pde(pt, pd, start, length, pde) { |
d7b2633d | 1114 | /* Don't reallocate page tables */ |
6ac18502 | 1115 | if (test_bit(pde, pd->used_pdes)) { |
d7b2633d | 1116 | /* Scratch is never allocated this way */ |
d4ec9da0 | 1117 | WARN_ON(pt == vm->scratch_pt); |
d7b2633d MT |
1118 | continue; |
1119 | } | |
1120 | ||
275a991c | 1121 | pt = alloc_pt(dev_priv); |
d7b2633d | 1122 | if (IS_ERR(pt)) |
5441f0cb MT |
1123 | goto unwind_out; |
1124 | ||
d4ec9da0 | 1125 | gen8_initialize_pt(vm, pt); |
d7b2633d | 1126 | pd->page_table[pde] = pt; |
966082c9 | 1127 | __set_bit(pde, new_pts); |
4c06ec8d | 1128 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT); |
7ad47cf2 BW |
1129 | } |
1130 | ||
bf2b4ed2 | 1131 | return 0; |
7ad47cf2 BW |
1132 | |
1133 | unwind_out: | |
d7b2633d | 1134 | for_each_set_bit(pde, new_pts, I915_PDES) |
275a991c | 1135 | free_pt(dev_priv, pd->page_table[pde]); |
7ad47cf2 | 1136 | |
d7b3de91 | 1137 | return -ENOMEM; |
bf2b4ed2 BW |
1138 | } |
1139 | ||
d7b2633d MT |
1140 | /** |
1141 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
d4ec9da0 | 1142 | * @vm: Master vm structure. |
d7b2633d MT |
1143 | * @pdp: Page directory pointer for this address range. |
1144 | * @start: Starting virtual address to begin allocations. | |
d4ec9da0 MT |
1145 | * @length: Size of the allocations. |
1146 | * @new_pds: Bitmap set by function with new allocations. Likely used by the | |
d7b2633d MT |
1147 | * caller to free on error. |
1148 | * | |
1149 | * Allocate the required number of page directories starting at the pde index of | |
1150 | * @start, and ending at the pde index @start + @length. This function will skip | |
1151 | * over already allocated page directories within the range, and only allocate | |
1152 | * new ones, setting the appropriate pointer within the pdp as well as the | |
1153 | * correct position in the bitmap @new_pds. | |
1154 | * | |
1155 | * The function will only allocate the pages within the range for a give page | |
1156 | * directory pointer. In other words, if @start + @length straddles a virtually | |
1157 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
1158 | * required by the caller, This is not currently possible, and the BUG in the | |
1159 | * code will prevent it. | |
1160 | * | |
1161 | * Return: 0 if success; negative error code otherwise. | |
1162 | */ | |
d4ec9da0 MT |
1163 | static int |
1164 | gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, | |
1165 | struct i915_page_directory_pointer *pdp, | |
1166 | uint64_t start, | |
1167 | uint64_t length, | |
1168 | unsigned long *new_pds) | |
bf2b4ed2 | 1169 | { |
49d73912 | 1170 | struct drm_i915_private *dev_priv = vm->i915; |
d7b2633d | 1171 | struct i915_page_directory *pd; |
69876bed | 1172 | uint32_t pdpe; |
275a991c | 1173 | uint32_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
69876bed | 1174 | |
6ac18502 | 1175 | WARN_ON(!bitmap_empty(new_pds, pdpes)); |
d7b2633d | 1176 | |
e8ebd8e2 | 1177 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
6ac18502 | 1178 | if (test_bit(pdpe, pdp->used_pdpes)) |
d7b2633d | 1179 | continue; |
33c8819f | 1180 | |
275a991c | 1181 | pd = alloc_pd(dev_priv); |
d7b2633d | 1182 | if (IS_ERR(pd)) |
d7b3de91 | 1183 | goto unwind_out; |
69876bed | 1184 | |
d4ec9da0 | 1185 | gen8_initialize_pd(vm, pd); |
d7b2633d | 1186 | pdp->page_directory[pdpe] = pd; |
966082c9 | 1187 | __set_bit(pdpe, new_pds); |
4c06ec8d | 1188 | trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT); |
d7b3de91 BW |
1189 | } |
1190 | ||
bf2b4ed2 | 1191 | return 0; |
d7b3de91 BW |
1192 | |
1193 | unwind_out: | |
6ac18502 | 1194 | for_each_set_bit(pdpe, new_pds, pdpes) |
275a991c | 1195 | free_pd(dev_priv, pdp->page_directory[pdpe]); |
d7b3de91 BW |
1196 | |
1197 | return -ENOMEM; | |
bf2b4ed2 BW |
1198 | } |
1199 | ||
762d9936 MT |
1200 | /** |
1201 | * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range. | |
1202 | * @vm: Master vm structure. | |
1203 | * @pml4: Page map level 4 for this address range. | |
1204 | * @start: Starting virtual address to begin allocations. | |
1205 | * @length: Size of the allocations. | |
1206 | * @new_pdps: Bitmap set by function with new allocations. Likely used by the | |
1207 | * caller to free on error. | |
1208 | * | |
1209 | * Allocate the required number of page directory pointers. Extremely similar to | |
1210 | * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs(). | |
1211 | * The main difference is here we are limited by the pml4 boundary (instead of | |
1212 | * the page directory pointer). | |
1213 | * | |
1214 | * Return: 0 if success; negative error code otherwise. | |
1215 | */ | |
1216 | static int | |
1217 | gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, | |
1218 | struct i915_pml4 *pml4, | |
1219 | uint64_t start, | |
1220 | uint64_t length, | |
1221 | unsigned long *new_pdps) | |
1222 | { | |
49d73912 | 1223 | struct drm_i915_private *dev_priv = vm->i915; |
762d9936 | 1224 | struct i915_page_directory_pointer *pdp; |
762d9936 MT |
1225 | uint32_t pml4e; |
1226 | ||
1227 | WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4)); | |
1228 | ||
e8ebd8e2 | 1229 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 | 1230 | if (!test_bit(pml4e, pml4->used_pml4es)) { |
275a991c | 1231 | pdp = alloc_pdp(dev_priv); |
762d9936 MT |
1232 | if (IS_ERR(pdp)) |
1233 | goto unwind_out; | |
1234 | ||
69ab76fd | 1235 | gen8_initialize_pdp(vm, pdp); |
762d9936 MT |
1236 | pml4->pdps[pml4e] = pdp; |
1237 | __set_bit(pml4e, new_pdps); | |
1238 | trace_i915_page_directory_pointer_entry_alloc(vm, | |
1239 | pml4e, | |
1240 | start, | |
1241 | GEN8_PML4E_SHIFT); | |
1242 | } | |
1243 | } | |
1244 | ||
1245 | return 0; | |
1246 | ||
1247 | unwind_out: | |
1248 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
275a991c | 1249 | free_pdp(dev_priv, pml4->pdps[pml4e]); |
762d9936 MT |
1250 | |
1251 | return -ENOMEM; | |
1252 | } | |
1253 | ||
d7b2633d | 1254 | static void |
3a41a05d | 1255 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts) |
d7b2633d | 1256 | { |
d7b2633d MT |
1257 | kfree(new_pts); |
1258 | kfree(new_pds); | |
1259 | } | |
1260 | ||
1261 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
1262 | * of these are based on the number of PDPEs in the system. | |
1263 | */ | |
1264 | static | |
1265 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
3a41a05d | 1266 | unsigned long **new_pts, |
6ac18502 | 1267 | uint32_t pdpes) |
d7b2633d | 1268 | { |
d7b2633d | 1269 | unsigned long *pds; |
3a41a05d | 1270 | unsigned long *pts; |
d7b2633d | 1271 | |
3a41a05d | 1272 | pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY); |
d7b2633d MT |
1273 | if (!pds) |
1274 | return -ENOMEM; | |
1275 | ||
3a41a05d MW |
1276 | pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long), |
1277 | GFP_TEMPORARY); | |
1278 | if (!pts) | |
1279 | goto err_out; | |
d7b2633d MT |
1280 | |
1281 | *new_pds = pds; | |
1282 | *new_pts = pts; | |
1283 | ||
1284 | return 0; | |
1285 | ||
1286 | err_out: | |
3a41a05d | 1287 | free_gen8_temp_bitmaps(pds, pts); |
d7b2633d MT |
1288 | return -ENOMEM; |
1289 | } | |
1290 | ||
762d9936 MT |
1291 | static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, |
1292 | struct i915_page_directory_pointer *pdp, | |
1293 | uint64_t start, | |
1294 | uint64_t length) | |
bf2b4ed2 | 1295 | { |
e5716f55 | 1296 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3a41a05d | 1297 | unsigned long *new_page_dirs, *new_page_tables; |
49d73912 | 1298 | struct drm_i915_private *dev_priv = vm->i915; |
5441f0cb | 1299 | struct i915_page_directory *pd; |
33c8819f MT |
1300 | const uint64_t orig_start = start; |
1301 | const uint64_t orig_length = length; | |
5441f0cb | 1302 | uint32_t pdpe; |
275a991c | 1303 | uint32_t pdpes = I915_PDPES_PER_PDP(dev_priv); |
bf2b4ed2 BW |
1304 | int ret; |
1305 | ||
6ac18502 | 1306 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); |
bf2b4ed2 BW |
1307 | if (ret) |
1308 | return ret; | |
1309 | ||
d7b2633d | 1310 | /* Do the allocations first so we can easily bail out */ |
d4ec9da0 MT |
1311 | ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length, |
1312 | new_page_dirs); | |
d7b2633d | 1313 | if (ret) { |
3a41a05d | 1314 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
d7b2633d MT |
1315 | return ret; |
1316 | } | |
1317 | ||
1318 | /* For every page directory referenced, allocate page tables */ | |
e8ebd8e2 | 1319 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d4ec9da0 | 1320 | ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length, |
3a41a05d | 1321 | new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES)); |
5441f0cb MT |
1322 | if (ret) |
1323 | goto err_out; | |
5441f0cb MT |
1324 | } |
1325 | ||
33c8819f MT |
1326 | start = orig_start; |
1327 | length = orig_length; | |
1328 | ||
d7b2633d MT |
1329 | /* Allocations have completed successfully, so set the bitmaps, and do |
1330 | * the mappings. */ | |
e8ebd8e2 | 1331 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d1c54acd | 1332 | gen8_pde_t *const page_directory = kmap_px(pd); |
33c8819f | 1333 | struct i915_page_table *pt; |
09120d4e | 1334 | uint64_t pd_len = length; |
33c8819f MT |
1335 | uint64_t pd_start = start; |
1336 | uint32_t pde; | |
1337 | ||
d7b2633d MT |
1338 | /* Every pd should be allocated, we just did that above. */ |
1339 | WARN_ON(!pd); | |
1340 | ||
e8ebd8e2 | 1341 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
d7b2633d MT |
1342 | /* Same reasoning as pd */ |
1343 | WARN_ON(!pt); | |
1344 | WARN_ON(!pd_len); | |
1345 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
1346 | ||
1347 | /* Set our used ptes within the page table */ | |
1348 | bitmap_set(pt->used_ptes, | |
1349 | gen8_pte_index(pd_start), | |
1350 | gen8_pte_count(pd_start, pd_len)); | |
1351 | ||
1352 | /* Our pde is now pointing to the pagetable, pt */ | |
966082c9 | 1353 | __set_bit(pde, pd->used_pdes); |
d7b2633d MT |
1354 | |
1355 | /* Map the PDE to the page table */ | |
fe36f55d MK |
1356 | page_directory[pde] = gen8_pde_encode(px_dma(pt), |
1357 | I915_CACHE_LLC); | |
4c06ec8d MT |
1358 | trace_i915_page_table_entry_map(&ppgtt->base, pde, pt, |
1359 | gen8_pte_index(start), | |
1360 | gen8_pte_count(start, length), | |
1361 | GEN8_PTES); | |
d7b2633d MT |
1362 | |
1363 | /* NB: We haven't yet mapped ptes to pages. At this | |
1364 | * point we're still relying on insert_entries() */ | |
33c8819f | 1365 | } |
d7b2633d | 1366 | |
d1c54acd | 1367 | kunmap_px(ppgtt, page_directory); |
d4ec9da0 | 1368 | __set_bit(pdpe, pdp->used_pdpes); |
762d9936 | 1369 | gen8_setup_page_directory(ppgtt, pdp, pd, pdpe); |
33c8819f MT |
1370 | } |
1371 | ||
3a41a05d | 1372 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1373 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 1374 | return 0; |
bf2b4ed2 | 1375 | |
d7b3de91 | 1376 | err_out: |
d7b2633d | 1377 | while (pdpe--) { |
e8ebd8e2 DG |
1378 | unsigned long temp; |
1379 | ||
3a41a05d MW |
1380 | for_each_set_bit(temp, new_page_tables + pdpe * |
1381 | BITS_TO_LONGS(I915_PDES), I915_PDES) | |
275a991c TU |
1382 | free_pt(dev_priv, |
1383 | pdp->page_directory[pdpe]->page_table[temp]); | |
d7b2633d MT |
1384 | } |
1385 | ||
6ac18502 | 1386 | for_each_set_bit(pdpe, new_page_dirs, pdpes) |
275a991c | 1387 | free_pd(dev_priv, pdp->page_directory[pdpe]); |
d7b2633d | 1388 | |
3a41a05d | 1389 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1390 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
1391 | return ret; |
1392 | } | |
1393 | ||
762d9936 MT |
1394 | static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, |
1395 | struct i915_pml4 *pml4, | |
1396 | uint64_t start, | |
1397 | uint64_t length) | |
1398 | { | |
1399 | DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4); | |
e5716f55 | 1400 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1401 | struct i915_page_directory_pointer *pdp; |
e8ebd8e2 | 1402 | uint64_t pml4e; |
762d9936 MT |
1403 | int ret = 0; |
1404 | ||
1405 | /* Do the pml4 allocations first, so we don't need to track the newly | |
1406 | * allocated tables below the pdp */ | |
1407 | bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4); | |
1408 | ||
1409 | /* The pagedirectory and pagetable allocations are done in the shared 3 | |
1410 | * and 4 level code. Just allocate the pdps. | |
1411 | */ | |
1412 | ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length, | |
1413 | new_pdps); | |
1414 | if (ret) | |
1415 | return ret; | |
1416 | ||
1417 | WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2, | |
1418 | "The allocation has spanned more than 512GB. " | |
1419 | "It is highly likely this is incorrect."); | |
1420 | ||
e8ebd8e2 | 1421 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 MT |
1422 | WARN_ON(!pdp); |
1423 | ||
1424 | ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length); | |
1425 | if (ret) | |
1426 | goto err_out; | |
1427 | ||
1428 | gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e); | |
1429 | } | |
1430 | ||
1431 | bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es, | |
1432 | GEN8_PML4ES_PER_PML4); | |
1433 | ||
1434 | return 0; | |
1435 | ||
1436 | err_out: | |
1437 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
49d73912 | 1438 | gen8_ppgtt_cleanup_3lvl(vm->i915, pml4->pdps[pml4e]); |
762d9936 MT |
1439 | |
1440 | return ret; | |
1441 | } | |
1442 | ||
1443 | static int gen8_alloc_va_range(struct i915_address_space *vm, | |
1444 | uint64_t start, uint64_t length) | |
1445 | { | |
e5716f55 | 1446 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1447 | |
c6385c94 | 1448 | if (USES_FULL_48BIT_PPGTT(vm->i915)) |
762d9936 MT |
1449 | return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); |
1450 | else | |
1451 | return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length); | |
1452 | } | |
1453 | ||
ea91e401 MT |
1454 | static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp, |
1455 | uint64_t start, uint64_t length, | |
1456 | gen8_pte_t scratch_pte, | |
1457 | struct seq_file *m) | |
1458 | { | |
1459 | struct i915_page_directory *pd; | |
ea91e401 MT |
1460 | uint32_t pdpe; |
1461 | ||
e8ebd8e2 | 1462 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
ea91e401 MT |
1463 | struct i915_page_table *pt; |
1464 | uint64_t pd_len = length; | |
1465 | uint64_t pd_start = start; | |
1466 | uint32_t pde; | |
1467 | ||
1468 | if (!test_bit(pdpe, pdp->used_pdpes)) | |
1469 | continue; | |
1470 | ||
1471 | seq_printf(m, "\tPDPE #%d\n", pdpe); | |
e8ebd8e2 | 1472 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
ea91e401 MT |
1473 | uint32_t pte; |
1474 | gen8_pte_t *pt_vaddr; | |
1475 | ||
1476 | if (!test_bit(pde, pd->used_pdes)) | |
1477 | continue; | |
1478 | ||
1479 | pt_vaddr = kmap_px(pt); | |
1480 | for (pte = 0; pte < GEN8_PTES; pte += 4) { | |
1481 | uint64_t va = | |
1482 | (pdpe << GEN8_PDPE_SHIFT) | | |
1483 | (pde << GEN8_PDE_SHIFT) | | |
1484 | (pte << GEN8_PTE_SHIFT); | |
1485 | int i; | |
1486 | bool found = false; | |
1487 | ||
1488 | for (i = 0; i < 4; i++) | |
1489 | if (pt_vaddr[pte + i] != scratch_pte) | |
1490 | found = true; | |
1491 | if (!found) | |
1492 | continue; | |
1493 | ||
1494 | seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte); | |
1495 | for (i = 0; i < 4; i++) { | |
1496 | if (pt_vaddr[pte + i] != scratch_pte) | |
1497 | seq_printf(m, " %llx", pt_vaddr[pte + i]); | |
1498 | else | |
1499 | seq_puts(m, " SCRATCH "); | |
1500 | } | |
1501 | seq_puts(m, "\n"); | |
1502 | } | |
1503 | /* don't use kunmap_px, it could trigger | |
1504 | * an unnecessary flush. | |
1505 | */ | |
1506 | kunmap_atomic(pt_vaddr); | |
1507 | } | |
1508 | } | |
1509 | } | |
1510 | ||
1511 | static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) | |
1512 | { | |
1513 | struct i915_address_space *vm = &ppgtt->base; | |
1514 | uint64_t start = ppgtt->base.start; | |
1515 | uint64_t length = ppgtt->base.total; | |
8bcdd0f7 | 1516 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1517 | I915_CACHE_LLC); |
ea91e401 | 1518 | |
c6385c94 | 1519 | if (!USES_FULL_48BIT_PPGTT(vm->i915)) { |
ea91e401 MT |
1520 | gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m); |
1521 | } else { | |
e8ebd8e2 | 1522 | uint64_t pml4e; |
ea91e401 MT |
1523 | struct i915_pml4 *pml4 = &ppgtt->pml4; |
1524 | struct i915_page_directory_pointer *pdp; | |
1525 | ||
e8ebd8e2 | 1526 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
ea91e401 MT |
1527 | if (!test_bit(pml4e, pml4->used_pml4es)) |
1528 | continue; | |
1529 | ||
1530 | seq_printf(m, " PML4E #%llu\n", pml4e); | |
1531 | gen8_dump_pdp(pdp, start, length, scratch_pte, m); | |
1532 | } | |
1533 | } | |
1534 | } | |
1535 | ||
331f38e7 ZL |
1536 | static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt) |
1537 | { | |
3a41a05d | 1538 | unsigned long *new_page_dirs, *new_page_tables; |
275a991c | 1539 | uint32_t pdpes = I915_PDPES_PER_PDP(to_i915(ppgtt->base.dev)); |
331f38e7 ZL |
1540 | int ret; |
1541 | ||
1542 | /* We allocate temp bitmap for page tables for no gain | |
1543 | * but as this is for init only, lets keep the things simple | |
1544 | */ | |
1545 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); | |
1546 | if (ret) | |
1547 | return ret; | |
1548 | ||
1549 | /* Allocate for all pdps regardless of how the ppgtt | |
1550 | * was defined. | |
1551 | */ | |
1552 | ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp, | |
1553 | 0, 1ULL << 32, | |
1554 | new_page_dirs); | |
1555 | if (!ret) | |
1556 | *ppgtt->pdp.used_pdpes = *new_page_dirs; | |
1557 | ||
3a41a05d | 1558 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
331f38e7 ZL |
1559 | |
1560 | return ret; | |
1561 | } | |
1562 | ||
eb0b44ad | 1563 | /* |
f3a964b9 BW |
1564 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1565 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1566 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1567 | * space. | |
37aca44a | 1568 | * |
f3a964b9 | 1569 | */ |
5c5f6457 | 1570 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 1571 | { |
49d73912 | 1572 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
8776f02b | 1573 | int ret; |
7cb6d7ac | 1574 | |
8776f02b MK |
1575 | ret = gen8_init_scratch(&ppgtt->base); |
1576 | if (ret) | |
1577 | return ret; | |
69876bed | 1578 | |
d7b2633d | 1579 | ppgtt->base.start = 0; |
d7b2633d | 1580 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 1581 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 1582 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 1583 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
1584 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1585 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
ea91e401 | 1586 | ppgtt->debug_dump = gen8_dump_ppgtt; |
d7b2633d | 1587 | |
275a991c TU |
1588 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
1589 | ret = setup_px(dev_priv, &ppgtt->pml4); | |
762d9936 MT |
1590 | if (ret) |
1591 | goto free_scratch; | |
6ac18502 | 1592 | |
69ab76fd MT |
1593 | gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4); |
1594 | ||
762d9936 | 1595 | ppgtt->base.total = 1ULL << 48; |
2dba3239 | 1596 | ppgtt->switch_mm = gen8_48b_mm_switch; |
762d9936 | 1597 | } else { |
275a991c | 1598 | ret = __pdp_init(dev_priv, &ppgtt->pdp); |
81ba8aef MT |
1599 | if (ret) |
1600 | goto free_scratch; | |
1601 | ||
1602 | ppgtt->base.total = 1ULL << 32; | |
2dba3239 | 1603 | ppgtt->switch_mm = gen8_legacy_mm_switch; |
762d9936 MT |
1604 | trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base, |
1605 | 0, 0, | |
1606 | GEN8_PML4E_SHIFT); | |
331f38e7 | 1607 | |
275a991c | 1608 | if (intel_vgpu_active(dev_priv)) { |
331f38e7 ZL |
1609 | ret = gen8_preallocate_top_level_pdps(ppgtt); |
1610 | if (ret) | |
1611 | goto free_scratch; | |
1612 | } | |
81ba8aef | 1613 | } |
6ac18502 | 1614 | |
275a991c | 1615 | if (intel_vgpu_active(dev_priv)) |
650da34c ZL |
1616 | gen8_ppgtt_notify_vgt(ppgtt, true); |
1617 | ||
d7b2633d | 1618 | return 0; |
6ac18502 MT |
1619 | |
1620 | free_scratch: | |
1621 | gen8_free_scratch(&ppgtt->base); | |
1622 | return ret; | |
d7b2633d MT |
1623 | } |
1624 | ||
87d60b63 BW |
1625 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
1626 | { | |
87d60b63 | 1627 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 1628 | struct i915_page_table *unused; |
07749ef3 | 1629 | gen6_pte_t scratch_pte; |
87d60b63 | 1630 | uint32_t pd_entry; |
731f74c5 | 1631 | uint32_t pte, pde; |
09942c65 | 1632 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; |
87d60b63 | 1633 | |
8bcdd0f7 | 1634 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1635 | I915_CACHE_LLC, 0); |
87d60b63 | 1636 | |
731f74c5 | 1637 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) { |
87d60b63 | 1638 | u32 expected; |
07749ef3 | 1639 | gen6_pte_t *pt_vaddr; |
567047be | 1640 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 1641 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
1642 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
1643 | ||
1644 | if (pd_entry != expected) | |
1645 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1646 | pde, | |
1647 | pd_entry, | |
1648 | expected); | |
1649 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1650 | ||
d1c54acd MK |
1651 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
1652 | ||
07749ef3 | 1653 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1654 | unsigned long va = |
07749ef3 | 1655 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1656 | (pte * PAGE_SIZE); |
1657 | int i; | |
1658 | bool found = false; | |
1659 | for (i = 0; i < 4; i++) | |
1660 | if (pt_vaddr[pte + i] != scratch_pte) | |
1661 | found = true; | |
1662 | if (!found) | |
1663 | continue; | |
1664 | ||
1665 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1666 | for (i = 0; i < 4; i++) { | |
1667 | if (pt_vaddr[pte + i] != scratch_pte) | |
1668 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1669 | else | |
1670 | seq_puts(m, " SCRATCH "); | |
1671 | } | |
1672 | seq_puts(m, "\n"); | |
1673 | } | |
d1c54acd | 1674 | kunmap_px(ppgtt, pt_vaddr); |
87d60b63 BW |
1675 | } |
1676 | } | |
1677 | ||
678d96fb | 1678 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1679 | static void gen6_write_pde(struct i915_page_directory *pd, |
1680 | const int pde, struct i915_page_table *pt) | |
6197349b | 1681 | { |
678d96fb BW |
1682 | /* Caller needs to make sure the write completes if necessary */ |
1683 | struct i915_hw_ppgtt *ppgtt = | |
1684 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1685 | u32 pd_entry; | |
6197349b | 1686 | |
567047be | 1687 | pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); |
678d96fb | 1688 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1689 | |
678d96fb BW |
1690 | writel(pd_entry, ppgtt->pd_addr + pde); |
1691 | } | |
6197349b | 1692 | |
678d96fb BW |
1693 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1694 | * directories. */ | |
1695 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1696 | struct i915_page_directory *pd, |
678d96fb BW |
1697 | uint32_t start, uint32_t length) |
1698 | { | |
72e96d64 | 1699 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ec565b3c | 1700 | struct i915_page_table *pt; |
731f74c5 | 1701 | uint32_t pde; |
678d96fb | 1702 | |
731f74c5 | 1703 | gen6_for_each_pde(pt, pd, start, length, pde) |
678d96fb BW |
1704 | gen6_write_pde(pd, pde, pt); |
1705 | ||
1706 | /* Make sure write is complete before other code can use this page | |
1707 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1708 | readl(ggtt->gsm); |
3e302542 BW |
1709 | } |
1710 | ||
b4a74e3a | 1711 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1712 | { |
44159ddb | 1713 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1714 | |
44159ddb | 1715 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1716 | } |
1717 | ||
90252e5c | 1718 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1719 | struct drm_i915_gem_request *req) |
90252e5c | 1720 | { |
7e37f889 | 1721 | struct intel_ring *ring = req->ring; |
4a570db5 | 1722 | struct intel_engine_cs *engine = req->engine; |
90252e5c BW |
1723 | int ret; |
1724 | ||
90252e5c | 1725 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1726 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1727 | if (ret) |
1728 | return ret; | |
1729 | ||
5fb9de1a | 1730 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1731 | if (ret) |
1732 | return ret; | |
1733 | ||
b5321f30 CW |
1734 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1735 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1736 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1737 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1738 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1739 | intel_ring_emit(ring, MI_NOOP); | |
1740 | intel_ring_advance(ring); | |
90252e5c BW |
1741 | |
1742 | return 0; | |
1743 | } | |
1744 | ||
48a10389 | 1745 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1746 | struct drm_i915_gem_request *req) |
48a10389 | 1747 | { |
7e37f889 | 1748 | struct intel_ring *ring = req->ring; |
4a570db5 | 1749 | struct intel_engine_cs *engine = req->engine; |
48a10389 BW |
1750 | int ret; |
1751 | ||
48a10389 | 1752 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1753 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
48a10389 BW |
1754 | if (ret) |
1755 | return ret; | |
1756 | ||
5fb9de1a | 1757 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1758 | if (ret) |
1759 | return ret; | |
1760 | ||
b5321f30 CW |
1761 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1762 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1763 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1764 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1765 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1766 | intel_ring_emit(ring, MI_NOOP); | |
1767 | intel_ring_advance(ring); | |
48a10389 | 1768 | |
90252e5c | 1769 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
e2f80391 | 1770 | if (engine->id != RCS) { |
7c9cf4e3 | 1771 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1772 | if (ret) |
1773 | return ret; | |
1774 | } | |
1775 | ||
48a10389 BW |
1776 | return 0; |
1777 | } | |
1778 | ||
eeb9488e | 1779 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1780 | struct drm_i915_gem_request *req) |
eeb9488e | 1781 | { |
4a570db5 | 1782 | struct intel_engine_cs *engine = req->engine; |
8eb95204 | 1783 | struct drm_i915_private *dev_priv = req->i915; |
48a10389 | 1784 | |
e2f80391 TU |
1785 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); |
1786 | I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt)); | |
eeb9488e BW |
1787 | return 0; |
1788 | } | |
1789 | ||
c6be607a | 1790 | static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv) |
eeb9488e | 1791 | { |
e2f80391 | 1792 | struct intel_engine_cs *engine; |
3b3f1650 | 1793 | enum intel_engine_id id; |
3e302542 | 1794 | |
3b3f1650 | 1795 | for_each_engine(engine, dev_priv, id) { |
c6be607a TU |
1796 | u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ? |
1797 | GEN8_GFX_PPGTT_48B : 0; | |
e2f80391 | 1798 | I915_WRITE(RING_MODE_GEN7(engine), |
2dba3239 | 1799 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); |
eeb9488e | 1800 | } |
eeb9488e | 1801 | } |
6197349b | 1802 | |
c6be607a | 1803 | static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv) |
3e302542 | 1804 | { |
e2f80391 | 1805 | struct intel_engine_cs *engine; |
b4a74e3a | 1806 | uint32_t ecochk, ecobits; |
3b3f1650 | 1807 | enum intel_engine_id id; |
6197349b | 1808 | |
b4a74e3a BW |
1809 | ecobits = I915_READ(GAC_ECO_BITS); |
1810 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1811 | |
b4a74e3a | 1812 | ecochk = I915_READ(GAM_ECOCHK); |
772c2a51 | 1813 | if (IS_HASWELL(dev_priv)) { |
b4a74e3a BW |
1814 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
1815 | } else { | |
1816 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1817 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1818 | } | |
1819 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1820 | |
3b3f1650 | 1821 | for_each_engine(engine, dev_priv, id) { |
6197349b | 1822 | /* GFX_MODE is per-ring on gen7+ */ |
e2f80391 | 1823 | I915_WRITE(RING_MODE_GEN7(engine), |
b4a74e3a | 1824 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
6197349b | 1825 | } |
b4a74e3a | 1826 | } |
6197349b | 1827 | |
c6be607a | 1828 | static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv) |
b4a74e3a | 1829 | { |
b4a74e3a | 1830 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1831 | |
b4a74e3a BW |
1832 | ecobits = I915_READ(GAC_ECO_BITS); |
1833 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1834 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1835 | |
b4a74e3a BW |
1836 | gab_ctl = I915_READ(GAB_CTL); |
1837 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1838 | ||
1839 | ecochk = I915_READ(GAM_ECOCHK); | |
1840 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1841 | ||
1842 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1843 | } |
1844 | ||
1d2a314c | 1845 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1846 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 | 1847 | uint64_t start, |
4fb84d99 | 1848 | uint64_t length) |
1d2a314c | 1849 | { |
e5716f55 | 1850 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 1851 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1852 | unsigned first_entry = start >> PAGE_SHIFT; |
1853 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1854 | unsigned act_pt = first_entry / GEN6_PTES; |
1855 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1856 | unsigned last_pte, i; |
1d2a314c | 1857 | |
8bcdd0f7 | 1858 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 1859 | I915_CACHE_LLC, 0); |
1d2a314c | 1860 | |
7bddb01f DV |
1861 | while (num_entries) { |
1862 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1863 | if (last_pte > GEN6_PTES) |
1864 | last_pte = GEN6_PTES; | |
7bddb01f | 1865 | |
d1c54acd | 1866 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
1d2a314c | 1867 | |
7bddb01f DV |
1868 | for (i = first_pte; i < last_pte; i++) |
1869 | pt_vaddr[i] = scratch_pte; | |
1d2a314c | 1870 | |
d1c54acd | 1871 | kunmap_px(ppgtt, pt_vaddr); |
1d2a314c | 1872 | |
7bddb01f DV |
1873 | num_entries -= last_pte - first_pte; |
1874 | first_pte = 0; | |
a15326a5 | 1875 | act_pt++; |
7bddb01f | 1876 | } |
1d2a314c DV |
1877 | } |
1878 | ||
853ba5d2 | 1879 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1880 | struct sg_table *pages, |
782f1495 | 1881 | uint64_t start, |
24f3a8cf | 1882 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1883 | { |
e5716f55 | 1884 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
782f1495 | 1885 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1886 | unsigned act_pt = first_entry / GEN6_PTES; |
1887 | unsigned act_pte = first_entry % GEN6_PTES; | |
85d1225e DG |
1888 | gen6_pte_t *pt_vaddr = NULL; |
1889 | struct sgt_iter sgt_iter; | |
1890 | dma_addr_t addr; | |
6e995e23 | 1891 | |
85d1225e | 1892 | for_each_sgt_dma(addr, sgt_iter, pages) { |
cc79714f | 1893 | if (pt_vaddr == NULL) |
d1c54acd | 1894 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
6e995e23 | 1895 | |
cc79714f | 1896 | pt_vaddr[act_pte] = |
4fb84d99 | 1897 | vm->pte_encode(addr, cache_level, flags); |
24f3a8cf | 1898 | |
07749ef3 | 1899 | if (++act_pte == GEN6_PTES) { |
d1c54acd | 1900 | kunmap_px(ppgtt, pt_vaddr); |
cc79714f | 1901 | pt_vaddr = NULL; |
a15326a5 | 1902 | act_pt++; |
6e995e23 | 1903 | act_pte = 0; |
def886c3 | 1904 | } |
def886c3 | 1905 | } |
85d1225e | 1906 | |
cc79714f | 1907 | if (pt_vaddr) |
d1c54acd | 1908 | kunmap_px(ppgtt, pt_vaddr); |
def886c3 DV |
1909 | } |
1910 | ||
678d96fb | 1911 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1912 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1913 | { |
4933d519 | 1914 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
49d73912 | 1915 | struct drm_i915_private *dev_priv = vm->i915; |
72e96d64 | 1916 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
e5716f55 | 1917 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
ec565b3c | 1918 | struct i915_page_table *pt; |
a05d80ee | 1919 | uint32_t start, length, start_save, length_save; |
731f74c5 | 1920 | uint32_t pde; |
4933d519 MT |
1921 | int ret; |
1922 | ||
a05d80ee MK |
1923 | start = start_save = start_in; |
1924 | length = length_save = length_in; | |
4933d519 MT |
1925 | |
1926 | bitmap_zero(new_page_tables, I915_PDES); | |
1927 | ||
1928 | /* The allocation is done in two stages so that we can bail out with | |
1929 | * minimal amount of pain. The first stage finds new page tables that | |
1930 | * need allocation. The second stage marks use ptes within the page | |
1931 | * tables. | |
1932 | */ | |
731f74c5 | 1933 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
79ab9370 | 1934 | if (pt != vm->scratch_pt) { |
4933d519 MT |
1935 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); |
1936 | continue; | |
1937 | } | |
1938 | ||
1939 | /* We've already allocated a page table */ | |
1940 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1941 | ||
275a991c | 1942 | pt = alloc_pt(dev_priv); |
4933d519 MT |
1943 | if (IS_ERR(pt)) { |
1944 | ret = PTR_ERR(pt); | |
1945 | goto unwind_out; | |
1946 | } | |
1947 | ||
1948 | gen6_initialize_pt(vm, pt); | |
1949 | ||
1950 | ppgtt->pd.page_table[pde] = pt; | |
966082c9 | 1951 | __set_bit(pde, new_page_tables); |
72744cb1 | 1952 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1953 | } |
1954 | ||
1955 | start = start_save; | |
1956 | length = length_save; | |
678d96fb | 1957 | |
731f74c5 | 1958 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
678d96fb BW |
1959 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); |
1960 | ||
1961 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1962 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1963 | gen6_pte_count(start, length)); | |
1964 | ||
966082c9 | 1965 | if (__test_and_clear_bit(pde, new_page_tables)) |
4933d519 MT |
1966 | gen6_write_pde(&ppgtt->pd, pde, pt); |
1967 | ||
72744cb1 MT |
1968 | trace_i915_page_table_entry_map(vm, pde, pt, |
1969 | gen6_pte_index(start), | |
1970 | gen6_pte_count(start, length), | |
1971 | GEN6_PTES); | |
4933d519 | 1972 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1973 | GEN6_PTES); |
1974 | } | |
1975 | ||
4933d519 MT |
1976 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1977 | ||
1978 | /* Make sure write is complete before other code can use this page | |
1979 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1980 | readl(ggtt->gsm); |
4933d519 | 1981 | |
563222a7 | 1982 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1983 | return 0; |
4933d519 MT |
1984 | |
1985 | unwind_out: | |
1986 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1987 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 | 1988 | |
79ab9370 | 1989 | ppgtt->pd.page_table[pde] = vm->scratch_pt; |
275a991c | 1990 | free_pt(dev_priv, pt); |
4933d519 MT |
1991 | } |
1992 | ||
1993 | mark_tlbs_dirty(ppgtt); | |
1994 | return ret; | |
678d96fb BW |
1995 | } |
1996 | ||
8776f02b MK |
1997 | static int gen6_init_scratch(struct i915_address_space *vm) |
1998 | { | |
49d73912 | 1999 | struct drm_i915_private *dev_priv = vm->i915; |
8bcdd0f7 | 2000 | int ret; |
8776f02b | 2001 | |
275a991c | 2002 | ret = setup_scratch_page(dev_priv, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
2003 | if (ret) |
2004 | return ret; | |
8776f02b | 2005 | |
275a991c | 2006 | vm->scratch_pt = alloc_pt(dev_priv); |
8776f02b | 2007 | if (IS_ERR(vm->scratch_pt)) { |
275a991c | 2008 | cleanup_scratch_page(dev_priv, &vm->scratch_page); |
8776f02b MK |
2009 | return PTR_ERR(vm->scratch_pt); |
2010 | } | |
2011 | ||
2012 | gen6_initialize_pt(vm, vm->scratch_pt); | |
2013 | ||
2014 | return 0; | |
2015 | } | |
2016 | ||
2017 | static void gen6_free_scratch(struct i915_address_space *vm) | |
2018 | { | |
49d73912 | 2019 | struct drm_i915_private *dev_priv = vm->i915; |
8776f02b | 2020 | |
275a991c TU |
2021 | free_pt(dev_priv, vm->scratch_pt); |
2022 | cleanup_scratch_page(dev_priv, &vm->scratch_page); | |
8776f02b MK |
2023 | } |
2024 | ||
061dd493 | 2025 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 2026 | { |
e5716f55 | 2027 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
731f74c5 | 2028 | struct i915_page_directory *pd = &ppgtt->pd; |
49d73912 | 2029 | struct drm_i915_private *dev_priv = vm->i915; |
09942c65 MT |
2030 | struct i915_page_table *pt; |
2031 | uint32_t pde; | |
4933d519 | 2032 | |
061dd493 DV |
2033 | drm_mm_remove_node(&ppgtt->node); |
2034 | ||
731f74c5 | 2035 | gen6_for_all_pdes(pt, pd, pde) |
79ab9370 | 2036 | if (pt != vm->scratch_pt) |
275a991c | 2037 | free_pt(dev_priv, pt); |
06fda602 | 2038 | |
8776f02b | 2039 | gen6_free_scratch(vm); |
3440d265 DV |
2040 | } |
2041 | ||
b146520f | 2042 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 2043 | { |
8776f02b | 2044 | struct i915_address_space *vm = &ppgtt->base; |
49d73912 | 2045 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 2046 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
e3cc1995 | 2047 | bool retried = false; |
b146520f | 2048 | int ret; |
1d2a314c | 2049 | |
c8d4c0d6 BW |
2050 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
2051 | * allocator works in address space sizes, so it's multiplied by page | |
2052 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
2053 | */ | |
72e96d64 | 2054 | BUG_ON(!drm_mm_initialized(&ggtt->base.mm)); |
4933d519 | 2055 | |
8776f02b MK |
2056 | ret = gen6_init_scratch(vm); |
2057 | if (ret) | |
2058 | return ret; | |
4933d519 | 2059 | |
e3cc1995 | 2060 | alloc: |
85fd4f58 CW |
2061 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, &ppgtt->node, |
2062 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
2063 | I915_COLOR_UNEVICTABLE, | |
72e96d64 | 2064 | 0, ggtt->base.total, |
3e8b5ae9 | 2065 | DRM_MM_TOPDOWN); |
e3cc1995 | 2066 | if (ret == -ENOSPC && !retried) { |
e522ac23 | 2067 | ret = i915_gem_evict_something(&ggtt->base, |
e3cc1995 | 2068 | GEN6_PD_SIZE, GEN6_PD_ALIGN, |
85fd4f58 | 2069 | I915_COLOR_UNEVICTABLE, |
72e96d64 | 2070 | 0, ggtt->base.total, |
d23db88c | 2071 | 0); |
e3cc1995 | 2072 | if (ret) |
678d96fb | 2073 | goto err_out; |
e3cc1995 BW |
2074 | |
2075 | retried = true; | |
2076 | goto alloc; | |
2077 | } | |
c8d4c0d6 | 2078 | |
c8c26622 | 2079 | if (ret) |
678d96fb BW |
2080 | goto err_out; |
2081 | ||
c8c26622 | 2082 | |
72e96d64 | 2083 | if (ppgtt->node.start < ggtt->mappable_end) |
c8d4c0d6 | 2084 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
1d2a314c | 2085 | |
c8c26622 | 2086 | return 0; |
678d96fb BW |
2087 | |
2088 | err_out: | |
8776f02b | 2089 | gen6_free_scratch(vm); |
678d96fb | 2090 | return ret; |
b146520f BW |
2091 | } |
2092 | ||
b146520f BW |
2093 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
2094 | { | |
2f2cf682 | 2095 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 2096 | } |
06dc68d6 | 2097 | |
4933d519 MT |
2098 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
2099 | uint64_t start, uint64_t length) | |
2100 | { | |
ec565b3c | 2101 | struct i915_page_table *unused; |
731f74c5 | 2102 | uint32_t pde; |
1d2a314c | 2103 | |
731f74c5 | 2104 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) |
79ab9370 | 2105 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
2106 | } |
2107 | ||
5c5f6457 | 2108 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f | 2109 | { |
49d73912 | 2110 | struct drm_i915_private *dev_priv = ppgtt->base.i915; |
72e96d64 | 2111 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
b146520f BW |
2112 | int ret; |
2113 | ||
72e96d64 | 2114 | ppgtt->base.pte_encode = ggtt->base.pte_encode; |
5db94019 | 2115 | if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv)) |
b146520f | 2116 | ppgtt->switch_mm = gen6_mm_switch; |
772c2a51 | 2117 | else if (IS_HASWELL(dev_priv)) |
b146520f | 2118 | ppgtt->switch_mm = hsw_mm_switch; |
5db94019 | 2119 | else if (IS_GEN7(dev_priv)) |
b146520f | 2120 | ppgtt->switch_mm = gen7_mm_switch; |
8eb95204 | 2121 | else |
b146520f BW |
2122 | BUG(); |
2123 | ||
2124 | ret = gen6_ppgtt_alloc(ppgtt); | |
2125 | if (ret) | |
2126 | return ret; | |
2127 | ||
5c5f6457 | 2128 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
2129 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
2130 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
2131 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
2132 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 2133 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 2134 | ppgtt->base.start = 0; |
09942c65 | 2135 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 2136 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 2137 | |
44159ddb | 2138 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 2139 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 2140 | |
72e96d64 | 2141 | ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + |
44159ddb | 2142 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 2143 | |
5c5f6457 | 2144 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 2145 | |
678d96fb BW |
2146 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
2147 | ||
440fd528 | 2148 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
2149 | ppgtt->node.size >> 20, |
2150 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 2151 | |
fa76da34 | 2152 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 2153 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 2154 | |
b146520f | 2155 | return 0; |
3440d265 DV |
2156 | } |
2157 | ||
2bfa996e CW |
2158 | static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2159 | struct drm_i915_private *dev_priv) | |
3440d265 | 2160 | { |
49d73912 | 2161 | ppgtt->base.i915 = dev_priv; |
3440d265 | 2162 | |
2bfa996e | 2163 | if (INTEL_INFO(dev_priv)->gen < 8) |
5c5f6457 | 2164 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 2165 | else |
d7b2633d | 2166 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 2167 | } |
c114f76a | 2168 | |
a2cad9df | 2169 | static void i915_address_space_init(struct i915_address_space *vm, |
80b204bc CW |
2170 | struct drm_i915_private *dev_priv, |
2171 | const char *name) | |
a2cad9df | 2172 | { |
80b204bc | 2173 | i915_gem_timeline_init(dev_priv, &vm->timeline, name); |
a2cad9df | 2174 | drm_mm_init(&vm->mm, vm->start, vm->total); |
a2cad9df MW |
2175 | INIT_LIST_HEAD(&vm->active_list); |
2176 | INIT_LIST_HEAD(&vm->inactive_list); | |
50e046b6 | 2177 | INIT_LIST_HEAD(&vm->unbound_list); |
a2cad9df MW |
2178 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
2179 | } | |
2180 | ||
ed9724dd MA |
2181 | static void i915_address_space_fini(struct i915_address_space *vm) |
2182 | { | |
2183 | i915_gem_timeline_fini(&vm->timeline); | |
2184 | drm_mm_takedown(&vm->mm); | |
2185 | list_del(&vm->global_link); | |
2186 | } | |
2187 | ||
c6be607a | 2188 | static void gtt_write_workarounds(struct drm_i915_private *dev_priv) |
d5165ebd | 2189 | { |
d5165ebd TG |
2190 | /* This function is for gtt related workarounds. This function is |
2191 | * called on driver load and after a GPU reset, so you can place | |
2192 | * workarounds here even if they get overwritten by GPU reset. | |
2193 | */ | |
2194 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ | |
8652744b | 2195 | if (IS_BROADWELL(dev_priv)) |
d5165ebd | 2196 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); |
920a14b2 | 2197 | else if (IS_CHERRYVIEW(dev_priv)) |
d5165ebd | 2198 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); |
d9486e65 | 2199 | else if (IS_SKYLAKE(dev_priv)) |
d5165ebd | 2200 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); |
e2d214ae | 2201 | else if (IS_BROXTON(dev_priv)) |
d5165ebd TG |
2202 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); |
2203 | } | |
2204 | ||
2bfa996e CW |
2205 | static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2206 | struct drm_i915_private *dev_priv, | |
80b204bc CW |
2207 | struct drm_i915_file_private *file_priv, |
2208 | const char *name) | |
fa76da34 | 2209 | { |
2bfa996e | 2210 | int ret; |
3ed124b2 | 2211 | |
2bfa996e | 2212 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
fa76da34 | 2213 | if (ret == 0) { |
c7c48dfd | 2214 | kref_init(&ppgtt->ref); |
80b204bc | 2215 | i915_address_space_init(&ppgtt->base, dev_priv, name); |
2bfa996e | 2216 | ppgtt->base.file = file_priv; |
93bd8649 | 2217 | } |
1d2a314c DV |
2218 | |
2219 | return ret; | |
2220 | } | |
2221 | ||
c6be607a | 2222 | int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) |
82460d97 | 2223 | { |
c6be607a | 2224 | gtt_write_workarounds(dev_priv); |
d5165ebd | 2225 | |
671b5013 TD |
2226 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
2227 | * and the PDPs are contained within the context itself. We don't | |
2228 | * need to do anything here. */ | |
2229 | if (i915.enable_execlists) | |
2230 | return 0; | |
2231 | ||
c6be607a | 2232 | if (!USES_PPGTT(dev_priv)) |
82460d97 DV |
2233 | return 0; |
2234 | ||
5db94019 | 2235 | if (IS_GEN6(dev_priv)) |
c6be607a | 2236 | gen6_ppgtt_enable(dev_priv); |
5db94019 | 2237 | else if (IS_GEN7(dev_priv)) |
c6be607a TU |
2238 | gen7_ppgtt_enable(dev_priv); |
2239 | else if (INTEL_GEN(dev_priv) >= 8) | |
2240 | gen8_ppgtt_enable(dev_priv); | |
82460d97 | 2241 | else |
c6be607a | 2242 | MISSING_CASE(INTEL_GEN(dev_priv)); |
82460d97 | 2243 | |
4ad2fd88 JH |
2244 | return 0; |
2245 | } | |
1d2a314c | 2246 | |
4d884705 | 2247 | struct i915_hw_ppgtt * |
2bfa996e | 2248 | i915_ppgtt_create(struct drm_i915_private *dev_priv, |
80b204bc CW |
2249 | struct drm_i915_file_private *fpriv, |
2250 | const char *name) | |
4d884705 DV |
2251 | { |
2252 | struct i915_hw_ppgtt *ppgtt; | |
2253 | int ret; | |
2254 | ||
2255 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2256 | if (!ppgtt) | |
2257 | return ERR_PTR(-ENOMEM); | |
2258 | ||
80b204bc | 2259 | ret = i915_ppgtt_init(ppgtt, dev_priv, fpriv, name); |
4d884705 DV |
2260 | if (ret) { |
2261 | kfree(ppgtt); | |
2262 | return ERR_PTR(ret); | |
2263 | } | |
2264 | ||
198c974d DCS |
2265 | trace_i915_ppgtt_create(&ppgtt->base); |
2266 | ||
4d884705 DV |
2267 | return ppgtt; |
2268 | } | |
2269 | ||
ed9724dd | 2270 | void i915_ppgtt_release(struct kref *kref) |
ee960be7 DV |
2271 | { |
2272 | struct i915_hw_ppgtt *ppgtt = | |
2273 | container_of(kref, struct i915_hw_ppgtt, ref); | |
2274 | ||
198c974d DCS |
2275 | trace_i915_ppgtt_release(&ppgtt->base); |
2276 | ||
50e046b6 | 2277 | /* vmas should already be unbound and destroyed */ |
ee960be7 DV |
2278 | WARN_ON(!list_empty(&ppgtt->base.active_list)); |
2279 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
50e046b6 | 2280 | WARN_ON(!list_empty(&ppgtt->base.unbound_list)); |
ee960be7 | 2281 | |
ed9724dd | 2282 | i915_address_space_fini(&ppgtt->base); |
19dd120c | 2283 | |
ee960be7 DV |
2284 | ppgtt->base.cleanup(&ppgtt->base); |
2285 | kfree(ppgtt); | |
2286 | } | |
1d2a314c | 2287 | |
a81cc00c BW |
2288 | /* Certain Gen5 chipsets require require idling the GPU before |
2289 | * unmapping anything from the GTT when VT-d is enabled. | |
2290 | */ | |
97d6d7ab | 2291 | static bool needs_idle_maps(struct drm_i915_private *dev_priv) |
a81cc00c BW |
2292 | { |
2293 | #ifdef CONFIG_INTEL_IOMMU | |
2294 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
2295 | * was loaded first. | |
2296 | */ | |
97d6d7ab | 2297 | if (IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_iommu_gfx_mapped) |
a81cc00c BW |
2298 | return true; |
2299 | #endif | |
2300 | return false; | |
2301 | } | |
2302 | ||
dc97997a | 2303 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) |
828c7908 | 2304 | { |
e2f80391 | 2305 | struct intel_engine_cs *engine; |
3b3f1650 | 2306 | enum intel_engine_id id; |
828c7908 | 2307 | |
dc97997a | 2308 | if (INTEL_INFO(dev_priv)->gen < 6) |
828c7908 BW |
2309 | return; |
2310 | ||
3b3f1650 | 2311 | for_each_engine(engine, dev_priv, id) { |
828c7908 | 2312 | u32 fault_reg; |
e2f80391 | 2313 | fault_reg = I915_READ(RING_FAULT_REG(engine)); |
828c7908 BW |
2314 | if (fault_reg & RING_FAULT_VALID) { |
2315 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 2316 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
2317 | "\tAddress space: %s\n" |
2318 | "\tSource ID: %d\n" | |
2319 | "\tType: %d\n", | |
2320 | fault_reg & PAGE_MASK, | |
2321 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
2322 | RING_FAULT_SRCID(fault_reg), | |
2323 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
e2f80391 | 2324 | I915_WRITE(RING_FAULT_REG(engine), |
828c7908 BW |
2325 | fault_reg & ~RING_FAULT_VALID); |
2326 | } | |
2327 | } | |
3b3f1650 AG |
2328 | |
2329 | /* Engine specific init may not have been done till this point. */ | |
2330 | if (dev_priv->engine[RCS]) | |
2331 | POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS])); | |
828c7908 BW |
2332 | } |
2333 | ||
91e56499 CW |
2334 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
2335 | { | |
2d1fe073 | 2336 | if (INTEL_INFO(dev_priv)->gen < 6) { |
91e56499 CW |
2337 | intel_gtt_chipset_flush(); |
2338 | } else { | |
2339 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2340 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2341 | } | |
2342 | } | |
2343 | ||
275a991c | 2344 | void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) |
828c7908 | 2345 | { |
72e96d64 | 2346 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
828c7908 BW |
2347 | |
2348 | /* Don't bother messing with faults pre GEN6 as we have little | |
2349 | * documentation supporting that it's a good idea. | |
2350 | */ | |
275a991c | 2351 | if (INTEL_GEN(dev_priv) < 6) |
828c7908 BW |
2352 | return; |
2353 | ||
dc97997a | 2354 | i915_check_and_clear_faults(dev_priv); |
828c7908 | 2355 | |
4fb84d99 | 2356 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total); |
91e56499 CW |
2357 | |
2358 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
2359 | } |
2360 | ||
03ac84f1 CW |
2361 | int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj, |
2362 | struct sg_table *pages) | |
7c2e6fdf | 2363 | { |
03ac84f1 CW |
2364 | if (dma_map_sg(&obj->base.dev->pdev->dev, |
2365 | pages->sgl, pages->nents, | |
2366 | PCI_DMA_BIDIRECTIONAL)) | |
2367 | return 0; | |
9da3da66 | 2368 | |
03ac84f1 | 2369 | return -ENOSPC; |
7c2e6fdf DV |
2370 | } |
2371 | ||
2c642b07 | 2372 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 | 2373 | { |
94ec8f61 | 2374 | writeq(pte, addr); |
94ec8f61 BW |
2375 | } |
2376 | ||
d6473f56 CW |
2377 | static void gen8_ggtt_insert_page(struct i915_address_space *vm, |
2378 | dma_addr_t addr, | |
2379 | uint64_t offset, | |
2380 | enum i915_cache_level level, | |
2381 | u32 unused) | |
2382 | { | |
49d73912 | 2383 | struct drm_i915_private *dev_priv = vm->i915; |
d6473f56 CW |
2384 | gen8_pte_t __iomem *pte = |
2385 | (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2386 | (offset >> PAGE_SHIFT); | |
d6473f56 | 2387 | |
4fb84d99 | 2388 | gen8_set_pte(pte, gen8_pte_encode(addr, level)); |
d6473f56 CW |
2389 | |
2390 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2391 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
d6473f56 CW |
2392 | } |
2393 | ||
94ec8f61 BW |
2394 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
2395 | struct sg_table *st, | |
782f1495 | 2396 | uint64_t start, |
24f3a8cf | 2397 | enum i915_cache_level level, u32 unused) |
94ec8f61 | 2398 | { |
49d73912 | 2399 | struct drm_i915_private *dev_priv = vm->i915; |
ce7fda2e | 2400 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2401 | struct sgt_iter sgt_iter; |
2402 | gen8_pte_t __iomem *gtt_entries; | |
2403 | gen8_pte_t gtt_entry; | |
2404 | dma_addr_t addr; | |
85d1225e | 2405 | int i = 0; |
be69459a | 2406 | |
85d1225e DG |
2407 | gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2408 | ||
2409 | for_each_sgt_dma(addr, sgt_iter, st) { | |
4fb84d99 | 2410 | gtt_entry = gen8_pte_encode(addr, level); |
85d1225e | 2411 | gen8_set_pte(>t_entries[i++], gtt_entry); |
94ec8f61 BW |
2412 | } |
2413 | ||
2414 | /* | |
2415 | * XXX: This serves as a posting read to make sure that the PTE has | |
2416 | * actually been updated. There is some concern that even though | |
2417 | * registers and PTEs are within the same BAR that they are potentially | |
2418 | * of NUMA access patterns. Therefore, even with the way we assume | |
2419 | * hardware should work, we must keep this posting read for paranoia. | |
2420 | */ | |
2421 | if (i != 0) | |
85d1225e | 2422 | WARN_ON(readq(>t_entries[i-1]) != gtt_entry); |
94ec8f61 | 2423 | |
94ec8f61 BW |
2424 | /* This next bit makes the above posting read even more important. We |
2425 | * want to flush the TLBs only after we're certain all the PTE updates | |
2426 | * have finished. | |
2427 | */ | |
2428 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2429 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
2430 | } |
2431 | ||
c140330b CW |
2432 | struct insert_entries { |
2433 | struct i915_address_space *vm; | |
2434 | struct sg_table *st; | |
2435 | uint64_t start; | |
2436 | enum i915_cache_level level; | |
2437 | u32 flags; | |
2438 | }; | |
2439 | ||
2440 | static int gen8_ggtt_insert_entries__cb(void *_arg) | |
2441 | { | |
2442 | struct insert_entries *arg = _arg; | |
2443 | gen8_ggtt_insert_entries(arg->vm, arg->st, | |
2444 | arg->start, arg->level, arg->flags); | |
2445 | return 0; | |
2446 | } | |
2447 | ||
2448 | static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm, | |
2449 | struct sg_table *st, | |
2450 | uint64_t start, | |
2451 | enum i915_cache_level level, | |
2452 | u32 flags) | |
2453 | { | |
2454 | struct insert_entries arg = { vm, st, start, level, flags }; | |
2455 | stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL); | |
2456 | } | |
2457 | ||
d6473f56 CW |
2458 | static void gen6_ggtt_insert_page(struct i915_address_space *vm, |
2459 | dma_addr_t addr, | |
2460 | uint64_t offset, | |
2461 | enum i915_cache_level level, | |
2462 | u32 flags) | |
2463 | { | |
49d73912 | 2464 | struct drm_i915_private *dev_priv = vm->i915; |
d6473f56 CW |
2465 | gen6_pte_t __iomem *pte = |
2466 | (gen6_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2467 | (offset >> PAGE_SHIFT); | |
d6473f56 | 2468 | |
4fb84d99 | 2469 | iowrite32(vm->pte_encode(addr, level, flags), pte); |
d6473f56 CW |
2470 | |
2471 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2472 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
d6473f56 CW |
2473 | } |
2474 | ||
e76e9aeb BW |
2475 | /* |
2476 | * Binds an object into the global gtt with the specified cache level. The object | |
2477 | * will be accessible to the GPU via commands whose operands reference offsets | |
2478 | * within the global GTT as well as accessible by the GPU through the GMADR | |
2479 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
2480 | */ | |
853ba5d2 | 2481 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 2482 | struct sg_table *st, |
782f1495 | 2483 | uint64_t start, |
24f3a8cf | 2484 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 2485 | { |
49d73912 | 2486 | struct drm_i915_private *dev_priv = vm->i915; |
ce7fda2e | 2487 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2488 | struct sgt_iter sgt_iter; |
2489 | gen6_pte_t __iomem *gtt_entries; | |
2490 | gen6_pte_t gtt_entry; | |
2491 | dma_addr_t addr; | |
85d1225e | 2492 | int i = 0; |
be69459a | 2493 | |
85d1225e DG |
2494 | gtt_entries = (gen6_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2495 | ||
2496 | for_each_sgt_dma(addr, sgt_iter, st) { | |
4fb84d99 | 2497 | gtt_entry = vm->pte_encode(addr, level, flags); |
85d1225e | 2498 | iowrite32(gtt_entry, >t_entries[i++]); |
e76e9aeb BW |
2499 | } |
2500 | ||
e76e9aeb BW |
2501 | /* XXX: This serves as a posting read to make sure that the PTE has |
2502 | * actually been updated. There is some concern that even though | |
2503 | * registers and PTEs are within the same BAR that they are potentially | |
2504 | * of NUMA access patterns. Therefore, even with the way we assume | |
2505 | * hardware should work, we must keep this posting read for paranoia. | |
2506 | */ | |
85d1225e DG |
2507 | if (i != 0) |
2508 | WARN_ON(readl(>t_entries[i-1]) != gtt_entry); | |
0f9b91c7 BW |
2509 | |
2510 | /* This next bit makes the above posting read even more important. We | |
2511 | * want to flush the TLBs only after we're certain all the PTE updates | |
2512 | * have finished. | |
2513 | */ | |
2514 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2515 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
2516 | } |
2517 | ||
f7770bfd | 2518 | static void nop_clear_range(struct i915_address_space *vm, |
4fb84d99 | 2519 | uint64_t start, uint64_t length) |
f7770bfd CW |
2520 | { |
2521 | } | |
2522 | ||
94ec8f61 | 2523 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
4fb84d99 | 2524 | uint64_t start, uint64_t length) |
94ec8f61 | 2525 | { |
ce7fda2e | 2526 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2527 | unsigned first_entry = start >> PAGE_SHIFT; |
2528 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2529 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2530 | (gen8_pte_t __iomem *)ggtt->gsm + first_entry; |
2531 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
94ec8f61 BW |
2532 | int i; |
2533 | ||
2534 | if (WARN(num_entries > max_entries, | |
2535 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2536 | first_entry, num_entries, max_entries)) | |
2537 | num_entries = max_entries; | |
2538 | ||
8bcdd0f7 | 2539 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2540 | I915_CACHE_LLC); |
94ec8f61 BW |
2541 | for (i = 0; i < num_entries; i++) |
2542 | gen8_set_pte(>t_base[i], scratch_pte); | |
2543 | readl(gtt_base); | |
2544 | } | |
2545 | ||
853ba5d2 | 2546 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 | 2547 | uint64_t start, |
4fb84d99 | 2548 | uint64_t length) |
7faf1ab2 | 2549 | { |
ce7fda2e | 2550 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2551 | unsigned first_entry = start >> PAGE_SHIFT; |
2552 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2553 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2554 | (gen6_pte_t __iomem *)ggtt->gsm + first_entry; |
2555 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
7faf1ab2 DV |
2556 | int i; |
2557 | ||
2558 | if (WARN(num_entries > max_entries, | |
2559 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2560 | first_entry, num_entries, max_entries)) | |
2561 | num_entries = max_entries; | |
2562 | ||
8bcdd0f7 | 2563 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
4fb84d99 | 2564 | I915_CACHE_LLC, 0); |
828c7908 | 2565 | |
7faf1ab2 DV |
2566 | for (i = 0; i < num_entries; i++) |
2567 | iowrite32(scratch_pte, >t_base[i]); | |
2568 | readl(gtt_base); | |
2569 | } | |
2570 | ||
d6473f56 CW |
2571 | static void i915_ggtt_insert_page(struct i915_address_space *vm, |
2572 | dma_addr_t addr, | |
2573 | uint64_t offset, | |
2574 | enum i915_cache_level cache_level, | |
2575 | u32 unused) | |
2576 | { | |
d6473f56 CW |
2577 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
2578 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
d6473f56 CW |
2579 | |
2580 | intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); | |
d6473f56 CW |
2581 | } |
2582 | ||
d369d2d9 DV |
2583 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
2584 | struct sg_table *pages, | |
2585 | uint64_t start, | |
2586 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 DV |
2587 | { |
2588 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
2589 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
2590 | ||
d369d2d9 | 2591 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 2592 | |
7faf1ab2 DV |
2593 | } |
2594 | ||
853ba5d2 | 2595 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 | 2596 | uint64_t start, |
4fb84d99 | 2597 | uint64_t length) |
7faf1ab2 | 2598 | { |
2eedfc7d | 2599 | intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT); |
7faf1ab2 DV |
2600 | } |
2601 | ||
70b9f6f8 DV |
2602 | static int ggtt_bind_vma(struct i915_vma *vma, |
2603 | enum i915_cache_level cache_level, | |
2604 | u32 flags) | |
0a878716 | 2605 | { |
49d73912 | 2606 | struct drm_i915_private *i915 = vma->vm->i915; |
0a878716 DV |
2607 | struct drm_i915_gem_object *obj = vma->obj; |
2608 | u32 pte_flags = 0; | |
2609 | int ret; | |
2610 | ||
2611 | ret = i915_get_ggtt_vma_pages(vma); | |
2612 | if (ret) | |
2613 | return ret; | |
2614 | ||
2615 | /* Currently applicable only to VLV */ | |
2616 | if (obj->gt_ro) | |
2617 | pte_flags |= PTE_READ_ONLY; | |
2618 | ||
9c870d03 | 2619 | intel_runtime_pm_get(i915); |
247177dd | 2620 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
0a878716 | 2621 | cache_level, pte_flags); |
9c870d03 | 2622 | intel_runtime_pm_put(i915); |
0a878716 DV |
2623 | |
2624 | /* | |
2625 | * Without aliasing PPGTT there's no difference between | |
2626 | * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally | |
2627 | * upgrade to both bound if we bind either to avoid double-binding. | |
2628 | */ | |
3272db53 | 2629 | vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; |
0a878716 DV |
2630 | |
2631 | return 0; | |
2632 | } | |
2633 | ||
2634 | static int aliasing_gtt_bind_vma(struct i915_vma *vma, | |
2635 | enum i915_cache_level cache_level, | |
2636 | u32 flags) | |
d5bd1449 | 2637 | { |
49d73912 | 2638 | struct drm_i915_private *i915 = vma->vm->i915; |
321d178e | 2639 | u32 pte_flags; |
70b9f6f8 DV |
2640 | int ret; |
2641 | ||
2642 | ret = i915_get_ggtt_vma_pages(vma); | |
2643 | if (ret) | |
2644 | return ret; | |
7faf1ab2 | 2645 | |
24f3a8cf | 2646 | /* Currently applicable only to VLV */ |
321d178e CW |
2647 | pte_flags = 0; |
2648 | if (vma->obj->gt_ro) | |
f329f5f6 | 2649 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2650 | |
ec7adb6e | 2651 | |
3272db53 | 2652 | if (flags & I915_VMA_GLOBAL_BIND) { |
9c870d03 | 2653 | intel_runtime_pm_get(i915); |
321d178e | 2654 | vma->vm->insert_entries(vma->vm, |
247177dd | 2655 | vma->pages, vma->node.start, |
0875546c | 2656 | cache_level, pte_flags); |
9c870d03 | 2657 | intel_runtime_pm_put(i915); |
6f65e29a | 2658 | } |
d5bd1449 | 2659 | |
3272db53 | 2660 | if (flags & I915_VMA_LOCAL_BIND) { |
9c870d03 | 2661 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; |
321d178e | 2662 | appgtt->base.insert_entries(&appgtt->base, |
247177dd | 2663 | vma->pages, vma->node.start, |
f329f5f6 | 2664 | cache_level, pte_flags); |
6f65e29a | 2665 | } |
70b9f6f8 DV |
2666 | |
2667 | return 0; | |
d5bd1449 CW |
2668 | } |
2669 | ||
6f65e29a | 2670 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2671 | { |
49d73912 | 2672 | struct drm_i915_private *i915 = vma->vm->i915; |
9c870d03 | 2673 | struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt; |
de180033 | 2674 | const u64 size = min(vma->size, vma->node.size); |
6f65e29a | 2675 | |
9c870d03 CW |
2676 | if (vma->flags & I915_VMA_GLOBAL_BIND) { |
2677 | intel_runtime_pm_get(i915); | |
782f1495 | 2678 | vma->vm->clear_range(vma->vm, |
4fb84d99 | 2679 | vma->node.start, size); |
9c870d03 CW |
2680 | intel_runtime_pm_put(i915); |
2681 | } | |
06615ee5 | 2682 | |
3272db53 | 2683 | if (vma->flags & I915_VMA_LOCAL_BIND && appgtt) |
6f65e29a | 2684 | appgtt->base.clear_range(&appgtt->base, |
4fb84d99 | 2685 | vma->node.start, size); |
74163907 DV |
2686 | } |
2687 | ||
03ac84f1 CW |
2688 | void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj, |
2689 | struct sg_table *pages) | |
7c2e6fdf | 2690 | { |
52a05c30 DW |
2691 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2692 | struct device *kdev = &dev_priv->drm.pdev->dev; | |
307dc25b | 2693 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
5c042287 | 2694 | |
307dc25b | 2695 | if (unlikely(ggtt->do_idle_maps)) { |
22dd3bb9 | 2696 | if (i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED)) { |
307dc25b CW |
2697 | DRM_ERROR("Failed to wait for idle; VT'd may hang.\n"); |
2698 | /* Wait a bit, in hopes it avoids the hang */ | |
2699 | udelay(10); | |
2700 | } | |
2701 | } | |
5c042287 | 2702 | |
03ac84f1 | 2703 | dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL); |
7c2e6fdf | 2704 | } |
644ec02b | 2705 | |
45b186f1 | 2706 | static void i915_gtt_color_adjust(const struct drm_mm_node *node, |
42d6ab48 | 2707 | unsigned long color, |
440fd528 TR |
2708 | u64 *start, |
2709 | u64 *end) | |
42d6ab48 CW |
2710 | { |
2711 | if (node->color != color) | |
2712 | *start += 4096; | |
2713 | ||
b44f97fd CW |
2714 | node = list_next_entry(node, node_list); |
2715 | if (node->allocated && node->color != color) | |
2a1d7752 | 2716 | *end -= 4096; |
42d6ab48 | 2717 | } |
fbe5d36e | 2718 | |
f6b9d5ca | 2719 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) |
644ec02b | 2720 | { |
e78891ca BW |
2721 | /* Let GEM Manage all of the aperture. |
2722 | * | |
2723 | * However, leave one page at the end still bound to the scratch page. | |
2724 | * There are a number of places where the hardware apparently prefetches | |
2725 | * past the end of the object, and we've seen multiple hangs with the | |
2726 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2727 | * aperture. One page should be enough to keep any prefetching inside | |
2728 | * of the aperture. | |
2729 | */ | |
72e96d64 | 2730 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ed2f3452 | 2731 | unsigned long hole_start, hole_end; |
95374d75 | 2732 | struct i915_hw_ppgtt *ppgtt; |
f6b9d5ca | 2733 | struct drm_mm_node *entry; |
fa76da34 | 2734 | int ret; |
644ec02b | 2735 | |
b02d22a3 ZW |
2736 | ret = intel_vgt_balloon(dev_priv); |
2737 | if (ret) | |
2738 | return ret; | |
5dda8fa3 | 2739 | |
95374d75 CW |
2740 | /* Reserve a mappable slot for our lockless error capture */ |
2741 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, | |
2742 | &ggtt->error_capture, | |
85fd4f58 CW |
2743 | 4096, 0, |
2744 | I915_COLOR_UNEVICTABLE, | |
95374d75 CW |
2745 | 0, ggtt->mappable_end, |
2746 | 0, 0); | |
2747 | if (ret) | |
2748 | return ret; | |
2749 | ||
ed2f3452 | 2750 | /* Clear any non-preallocated blocks */ |
72e96d64 | 2751 | drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) { |
ed2f3452 CW |
2752 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2753 | hole_start, hole_end); | |
72e96d64 | 2754 | ggtt->base.clear_range(&ggtt->base, hole_start, |
4fb84d99 | 2755 | hole_end - hole_start); |
ed2f3452 CW |
2756 | } |
2757 | ||
2758 | /* And finally clear the reserved guard page */ | |
f6b9d5ca | 2759 | ggtt->base.clear_range(&ggtt->base, |
4fb84d99 | 2760 | ggtt->base.total - PAGE_SIZE, PAGE_SIZE); |
6c5566a8 | 2761 | |
97d6d7ab | 2762 | if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) { |
fa76da34 | 2763 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
95374d75 CW |
2764 | if (!ppgtt) { |
2765 | ret = -ENOMEM; | |
2766 | goto err; | |
2767 | } | |
fa76da34 | 2768 | |
2bfa996e | 2769 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
95374d75 CW |
2770 | if (ret) |
2771 | goto err_ppgtt; | |
5c5f6457 | 2772 | |
95374d75 | 2773 | if (ppgtt->base.allocate_va_range) { |
5c5f6457 DV |
2774 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, |
2775 | ppgtt->base.total); | |
95374d75 CW |
2776 | if (ret) |
2777 | goto err_ppgtt_cleanup; | |
4933d519 | 2778 | } |
fa76da34 | 2779 | |
5c5f6457 DV |
2780 | ppgtt->base.clear_range(&ppgtt->base, |
2781 | ppgtt->base.start, | |
4fb84d99 | 2782 | ppgtt->base.total); |
5c5f6457 | 2783 | |
fa76da34 | 2784 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
72e96d64 JL |
2785 | WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma); |
2786 | ggtt->base.bind_vma = aliasing_gtt_bind_vma; | |
fa76da34 DV |
2787 | } |
2788 | ||
6c5566a8 | 2789 | return 0; |
95374d75 CW |
2790 | |
2791 | err_ppgtt_cleanup: | |
2792 | ppgtt->base.cleanup(&ppgtt->base); | |
2793 | err_ppgtt: | |
2794 | kfree(ppgtt); | |
2795 | err: | |
2796 | drm_mm_remove_node(&ggtt->error_capture); | |
2797 | return ret; | |
e76e9aeb BW |
2798 | } |
2799 | ||
d85489d3 JL |
2800 | /** |
2801 | * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization | |
97d6d7ab | 2802 | * @dev_priv: i915 device |
d85489d3 | 2803 | */ |
97d6d7ab | 2804 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) |
90d0a0e8 | 2805 | { |
72e96d64 | 2806 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
90d0a0e8 | 2807 | |
70e32544 DV |
2808 | if (dev_priv->mm.aliasing_ppgtt) { |
2809 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
70e32544 | 2810 | ppgtt->base.cleanup(&ppgtt->base); |
cb7f2760 | 2811 | kfree(ppgtt); |
70e32544 DV |
2812 | } |
2813 | ||
97d6d7ab | 2814 | i915_gem_cleanup_stolen(&dev_priv->drm); |
a4eba47b | 2815 | |
95374d75 CW |
2816 | if (drm_mm_node_allocated(&ggtt->error_capture)) |
2817 | drm_mm_remove_node(&ggtt->error_capture); | |
2818 | ||
72e96d64 | 2819 | if (drm_mm_initialized(&ggtt->base.mm)) { |
b02d22a3 | 2820 | intel_vgt_deballoon(dev_priv); |
5dda8fa3 | 2821 | |
ed9724dd MA |
2822 | mutex_lock(&dev_priv->drm.struct_mutex); |
2823 | i915_address_space_fini(&ggtt->base); | |
2824 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
90d0a0e8 DV |
2825 | } |
2826 | ||
72e96d64 | 2827 | ggtt->base.cleanup(&ggtt->base); |
f6b9d5ca CW |
2828 | |
2829 | arch_phys_wc_del(ggtt->mtrr); | |
f7bbe788 | 2830 | io_mapping_fini(&ggtt->mappable); |
90d0a0e8 | 2831 | } |
70e32544 | 2832 | |
2c642b07 | 2833 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2834 | { |
2835 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2836 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2837 | return snb_gmch_ctl << 20; | |
2838 | } | |
2839 | ||
2c642b07 | 2840 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2841 | { |
2842 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2843 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2844 | if (bdw_gmch_ctl) | |
2845 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2846 | |
2847 | #ifdef CONFIG_X86_32 | |
2848 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2849 | if (bdw_gmch_ctl > 4) | |
2850 | bdw_gmch_ctl = 4; | |
2851 | #endif | |
2852 | ||
9459d252 BW |
2853 | return bdw_gmch_ctl << 20; |
2854 | } | |
2855 | ||
2c642b07 | 2856 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2857 | { |
2858 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2859 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2860 | ||
2861 | if (gmch_ctrl) | |
2862 | return 1 << (20 + gmch_ctrl); | |
2863 | ||
2864 | return 0; | |
2865 | } | |
2866 | ||
2c642b07 | 2867 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2868 | { |
2869 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2870 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2871 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2872 | } | |
2873 | ||
2c642b07 | 2874 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2875 | { |
2876 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2877 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2878 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2879 | } | |
2880 | ||
d7f25f23 DL |
2881 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2882 | { | |
2883 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2884 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2885 | ||
2886 | /* | |
2887 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2888 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2889 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2890 | */ | |
2891 | if (gmch_ctrl < 0x11) | |
2892 | return gmch_ctrl << 25; | |
2893 | else if (gmch_ctrl < 0x17) | |
2894 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2895 | else | |
2896 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2897 | } | |
2898 | ||
66375014 DL |
2899 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2900 | { | |
2901 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2902 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2903 | ||
2904 | if (gen9_gmch_ctl < 0xf0) | |
2905 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2906 | else | |
2907 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2908 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2909 | } | |
2910 | ||
34c998b4 | 2911 | static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) |
63340133 | 2912 | { |
49d73912 CW |
2913 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
2914 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
34c998b4 | 2915 | phys_addr_t phys_addr; |
8bcdd0f7 | 2916 | int ret; |
63340133 BW |
2917 | |
2918 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
34c998b4 | 2919 | phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; |
63340133 | 2920 | |
2a073f89 ID |
2921 | /* |
2922 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2923 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2924 | * when the WC buffer is flushed, so we can't use it, but have to | |
2925 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2926 | * readback check when writing GTT PTE entries. | |
2927 | */ | |
cc3f90f0 | 2928 | if (IS_GEN9_LP(dev_priv)) |
34c998b4 | 2929 | ggtt->gsm = ioremap_nocache(phys_addr, size); |
2a073f89 | 2930 | else |
34c998b4 | 2931 | ggtt->gsm = ioremap_wc(phys_addr, size); |
72e96d64 | 2932 | if (!ggtt->gsm) { |
34c998b4 | 2933 | DRM_ERROR("Failed to map the ggtt page table\n"); |
63340133 BW |
2934 | return -ENOMEM; |
2935 | } | |
2936 | ||
275a991c | 2937 | ret = setup_scratch_page(dev_priv, &ggtt->base.scratch_page, GFP_DMA32); |
8bcdd0f7 | 2938 | if (ret) { |
63340133 BW |
2939 | DRM_ERROR("Scratch setup failed\n"); |
2940 | /* iounmap will also get called at remove, but meh */ | |
72e96d64 | 2941 | iounmap(ggtt->gsm); |
8bcdd0f7 | 2942 | return ret; |
63340133 BW |
2943 | } |
2944 | ||
4ad2af1e | 2945 | return 0; |
63340133 BW |
2946 | } |
2947 | ||
fbe5d36e BW |
2948 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2949 | * bits. When using advanced contexts each context stores its own PAT, but | |
2950 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2951 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2952 | { |
fbe5d36e BW |
2953 | uint64_t pat; |
2954 | ||
2955 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2956 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2957 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2958 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2959 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2960 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2961 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2962 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2963 | ||
2d1fe073 | 2964 | if (!USES_PPGTT(dev_priv)) |
d6a8b72e RV |
2965 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
2966 | * so RTL will always use the value corresponding to | |
2967 | * pat_sel = 000". | |
2968 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2969 | * MOCS still can be used though. | |
2970 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2971 | * before this patch, i.e. the same uncached + snooping access | |
2972 | * like on gen6/7 seems to be in effect. | |
2973 | * - So this just fixes blitter/render access. Again it looks | |
2974 | * like it's not just uncached access, but uncached + snooping. | |
2975 | * So we can still hold onto all our assumptions wrt cpu | |
2976 | * clflushing on LLC machines. | |
2977 | */ | |
2978 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2979 | ||
fbe5d36e BW |
2980 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2981 | * write would work. */ | |
7e435ad2 VS |
2982 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
2983 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
fbe5d36e BW |
2984 | } |
2985 | ||
ee0ce478 VS |
2986 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2987 | { | |
2988 | uint64_t pat; | |
2989 | ||
2990 | /* | |
2991 | * Map WB on BDW to snooped on CHV. | |
2992 | * | |
2993 | * Only the snoop bit has meaning for CHV, the rest is | |
2994 | * ignored. | |
2995 | * | |
cf3d262e VS |
2996 | * The hardware will never snoop for certain types of accesses: |
2997 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2998 | * - PPGTT page tables | |
2999 | * - some other special cycles | |
3000 | * | |
3001 | * As with BDW, we also need to consider the following for GT accesses: | |
3002 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
3003 | * so RTL will always use the value corresponding to | |
3004 | * pat_sel = 000". | |
3005 | * Which means we must set the snoop bit in PAT entry 0 | |
3006 | * in order to keep the global status page working. | |
ee0ce478 VS |
3007 | */ |
3008 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
3009 | GEN8_PPAT(1, 0) | | |
3010 | GEN8_PPAT(2, 0) | | |
3011 | GEN8_PPAT(3, 0) | | |
3012 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
3013 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
3014 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
3015 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
3016 | ||
7e435ad2 VS |
3017 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
3018 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
ee0ce478 VS |
3019 | } |
3020 | ||
34c998b4 CW |
3021 | static void gen6_gmch_remove(struct i915_address_space *vm) |
3022 | { | |
3023 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); | |
3024 | ||
3025 | iounmap(ggtt->gsm); | |
49d73912 | 3026 | cleanup_scratch_page(vm->i915, &vm->scratch_page); |
34c998b4 CW |
3027 | } |
3028 | ||
d507d735 | 3029 | static int gen8_gmch_probe(struct i915_ggtt *ggtt) |
63340133 | 3030 | { |
49d73912 | 3031 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 3032 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3033 | unsigned int size; |
63340133 | 3034 | u16 snb_gmch_ctl; |
63340133 BW |
3035 | |
3036 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
97d6d7ab CW |
3037 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3038 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
63340133 | 3039 | |
97d6d7ab CW |
3040 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(39))) |
3041 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39)); | |
63340133 | 3042 | |
97d6d7ab | 3043 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
63340133 | 3044 | |
97d6d7ab | 3045 | if (INTEL_GEN(dev_priv) >= 9) { |
d507d735 | 3046 | ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3047 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
97d6d7ab | 3048 | } else if (IS_CHERRYVIEW(dev_priv)) { |
d507d735 | 3049 | ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3050 | size = chv_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3051 | } else { |
d507d735 | 3052 | ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3053 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3054 | } |
63340133 | 3055 | |
34c998b4 | 3056 | ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 3057 | |
cc3f90f0 | 3058 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
ee0ce478 VS |
3059 | chv_setup_private_ppat(dev_priv); |
3060 | else | |
3061 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 3062 | |
34c998b4 | 3063 | ggtt->base.cleanup = gen6_gmch_remove; |
d507d735 JL |
3064 | ggtt->base.bind_vma = ggtt_bind_vma; |
3065 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
d6473f56 | 3066 | ggtt->base.insert_page = gen8_ggtt_insert_page; |
f7770bfd | 3067 | ggtt->base.clear_range = nop_clear_range; |
48f112fe | 3068 | if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) |
f7770bfd CW |
3069 | ggtt->base.clear_range = gen8_ggtt_clear_range; |
3070 | ||
3071 | ggtt->base.insert_entries = gen8_ggtt_insert_entries; | |
3072 | if (IS_CHERRYVIEW(dev_priv)) | |
3073 | ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL; | |
3074 | ||
34c998b4 | 3075 | return ggtt_probe_common(ggtt, size); |
63340133 BW |
3076 | } |
3077 | ||
d507d735 | 3078 | static int gen6_gmch_probe(struct i915_ggtt *ggtt) |
e76e9aeb | 3079 | { |
49d73912 | 3080 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
97d6d7ab | 3081 | struct pci_dev *pdev = dev_priv->drm.pdev; |
34c998b4 | 3082 | unsigned int size; |
e76e9aeb | 3083 | u16 snb_gmch_ctl; |
e76e9aeb | 3084 | |
97d6d7ab CW |
3085 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3086 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
41907ddc | 3087 | |
baa09f5f BW |
3088 | /* 64/512MB is the current min/max we actually know of, but this is just |
3089 | * a coarse sanity check. | |
e76e9aeb | 3090 | */ |
34c998b4 | 3091 | if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) { |
d507d735 | 3092 | DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end); |
baa09f5f | 3093 | return -ENXIO; |
e76e9aeb BW |
3094 | } |
3095 | ||
97d6d7ab CW |
3096 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(40))) |
3097 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)); | |
3098 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
e76e9aeb | 3099 | |
d507d735 | 3100 | ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 3101 | |
34c998b4 CW |
3102 | size = gen6_get_total_gtt_size(snb_gmch_ctl); |
3103 | ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 3104 | |
d507d735 | 3105 | ggtt->base.clear_range = gen6_ggtt_clear_range; |
d6473f56 | 3106 | ggtt->base.insert_page = gen6_ggtt_insert_page; |
d507d735 JL |
3107 | ggtt->base.insert_entries = gen6_ggtt_insert_entries; |
3108 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3109 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 CW |
3110 | ggtt->base.cleanup = gen6_gmch_remove; |
3111 | ||
3112 | if (HAS_EDRAM(dev_priv)) | |
3113 | ggtt->base.pte_encode = iris_pte_encode; | |
3114 | else if (IS_HASWELL(dev_priv)) | |
3115 | ggtt->base.pte_encode = hsw_pte_encode; | |
3116 | else if (IS_VALLEYVIEW(dev_priv)) | |
3117 | ggtt->base.pte_encode = byt_pte_encode; | |
3118 | else if (INTEL_GEN(dev_priv) >= 7) | |
3119 | ggtt->base.pte_encode = ivb_pte_encode; | |
3120 | else | |
3121 | ggtt->base.pte_encode = snb_pte_encode; | |
7faf1ab2 | 3122 | |
34c998b4 | 3123 | return ggtt_probe_common(ggtt, size); |
e76e9aeb BW |
3124 | } |
3125 | ||
34c998b4 | 3126 | static void i915_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 3127 | { |
34c998b4 | 3128 | intel_gmch_remove(); |
644ec02b | 3129 | } |
baa09f5f | 3130 | |
d507d735 | 3131 | static int i915_gmch_probe(struct i915_ggtt *ggtt) |
baa09f5f | 3132 | { |
49d73912 | 3133 | struct drm_i915_private *dev_priv = ggtt->base.i915; |
baa09f5f BW |
3134 | int ret; |
3135 | ||
91c8a326 | 3136 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); |
baa09f5f BW |
3137 | if (!ret) { |
3138 | DRM_ERROR("failed to set up gmch\n"); | |
3139 | return -EIO; | |
3140 | } | |
3141 | ||
d507d735 JL |
3142 | intel_gtt_get(&ggtt->base.total, &ggtt->stolen_size, |
3143 | &ggtt->mappable_base, &ggtt->mappable_end); | |
baa09f5f | 3144 | |
97d6d7ab | 3145 | ggtt->do_idle_maps = needs_idle_maps(dev_priv); |
d6473f56 | 3146 | ggtt->base.insert_page = i915_ggtt_insert_page; |
d507d735 JL |
3147 | ggtt->base.insert_entries = i915_ggtt_insert_entries; |
3148 | ggtt->base.clear_range = i915_ggtt_clear_range; | |
3149 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3150 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 | 3151 | ggtt->base.cleanup = i915_gmch_remove; |
baa09f5f | 3152 | |
d507d735 | 3153 | if (unlikely(ggtt->do_idle_maps)) |
c0a7f818 CW |
3154 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
3155 | ||
baa09f5f BW |
3156 | return 0; |
3157 | } | |
3158 | ||
d85489d3 | 3159 | /** |
0088e522 | 3160 | * i915_ggtt_probe_hw - Probe GGTT hardware location |
97d6d7ab | 3161 | * @dev_priv: i915 device |
d85489d3 | 3162 | */ |
97d6d7ab | 3163 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) |
baa09f5f | 3164 | { |
62106b4f | 3165 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
baa09f5f BW |
3166 | int ret; |
3167 | ||
49d73912 | 3168 | ggtt->base.i915 = dev_priv; |
c114f76a | 3169 | |
34c998b4 CW |
3170 | if (INTEL_GEN(dev_priv) <= 5) |
3171 | ret = i915_gmch_probe(ggtt); | |
3172 | else if (INTEL_GEN(dev_priv) < 8) | |
3173 | ret = gen6_gmch_probe(ggtt); | |
3174 | else | |
3175 | ret = gen8_gmch_probe(ggtt); | |
a54c0c27 | 3176 | if (ret) |
baa09f5f | 3177 | return ret; |
baa09f5f | 3178 | |
db9309a5 CW |
3179 | /* Trim the GGTT to fit the GuC mappable upper range (when enabled). |
3180 | * This is easier than doing range restriction on the fly, as we | |
3181 | * currently don't have any bits spare to pass in this upper | |
3182 | * restriction! | |
3183 | */ | |
3184 | if (HAS_GUC(dev_priv) && i915.enable_guc_loading) { | |
3185 | ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP); | |
3186 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3187 | } | |
3188 | ||
c890e2d5 CW |
3189 | if ((ggtt->base.total - 1) >> 32) { |
3190 | DRM_ERROR("We never expected a Global GTT with more than 32bits" | |
f6b9d5ca | 3191 | " of address space! Found %lldM!\n", |
c890e2d5 CW |
3192 | ggtt->base.total >> 20); |
3193 | ggtt->base.total = 1ULL << 32; | |
3194 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3195 | } | |
3196 | ||
f6b9d5ca CW |
3197 | if (ggtt->mappable_end > ggtt->base.total) { |
3198 | DRM_ERROR("mappable aperture extends past end of GGTT," | |
3199 | " aperture=%llx, total=%llx\n", | |
3200 | ggtt->mappable_end, ggtt->base.total); | |
3201 | ggtt->mappable_end = ggtt->base.total; | |
3202 | } | |
3203 | ||
baa09f5f | 3204 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 3205 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
62106b4f JL |
3206 | ggtt->base.total >> 20); |
3207 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20); | |
3208 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt->stolen_size >> 20); | |
5db6c735 DV |
3209 | #ifdef CONFIG_INTEL_IOMMU |
3210 | if (intel_iommu_gfx_mapped) | |
3211 | DRM_INFO("VT-d active for gfx access\n"); | |
3212 | #endif | |
baa09f5f BW |
3213 | |
3214 | return 0; | |
0088e522 CW |
3215 | } |
3216 | ||
3217 | /** | |
3218 | * i915_ggtt_init_hw - Initialize GGTT hardware | |
97d6d7ab | 3219 | * @dev_priv: i915 device |
0088e522 | 3220 | */ |
97d6d7ab | 3221 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) |
0088e522 | 3222 | { |
0088e522 CW |
3223 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
3224 | int ret; | |
3225 | ||
f6b9d5ca CW |
3226 | INIT_LIST_HEAD(&dev_priv->vm_list); |
3227 | ||
3228 | /* Subtract the guard page before address space initialization to | |
3229 | * shrink the range used by drm_mm. | |
3230 | */ | |
80b204bc | 3231 | mutex_lock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3232 | ggtt->base.total -= PAGE_SIZE; |
80b204bc | 3233 | i915_address_space_init(&ggtt->base, dev_priv, "[global]"); |
f6b9d5ca CW |
3234 | ggtt->base.total += PAGE_SIZE; |
3235 | if (!HAS_LLC(dev_priv)) | |
3236 | ggtt->base.mm.color_adjust = i915_gtt_color_adjust; | |
80b204bc | 3237 | mutex_unlock(&dev_priv->drm.struct_mutex); |
f6b9d5ca | 3238 | |
f7bbe788 CW |
3239 | if (!io_mapping_init_wc(&dev_priv->ggtt.mappable, |
3240 | dev_priv->ggtt.mappable_base, | |
3241 | dev_priv->ggtt.mappable_end)) { | |
f6b9d5ca CW |
3242 | ret = -EIO; |
3243 | goto out_gtt_cleanup; | |
3244 | } | |
3245 | ||
3246 | ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end); | |
3247 | ||
0088e522 CW |
3248 | /* |
3249 | * Initialise stolen early so that we may reserve preallocated | |
3250 | * objects for the BIOS to KMS transition. | |
3251 | */ | |
7ace3d30 | 3252 | ret = i915_gem_init_stolen(dev_priv); |
0088e522 CW |
3253 | if (ret) |
3254 | goto out_gtt_cleanup; | |
3255 | ||
3256 | return 0; | |
a4eba47b ID |
3257 | |
3258 | out_gtt_cleanup: | |
72e96d64 | 3259 | ggtt->base.cleanup(&ggtt->base); |
a4eba47b | 3260 | return ret; |
baa09f5f | 3261 | } |
6f65e29a | 3262 | |
97d6d7ab | 3263 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) |
ac840ae5 | 3264 | { |
97d6d7ab | 3265 | if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt()) |
ac840ae5 VS |
3266 | return -EIO; |
3267 | ||
3268 | return 0; | |
3269 | } | |
3270 | ||
275a991c | 3271 | void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) |
fa42331b | 3272 | { |
72e96d64 | 3273 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
fbb30a5c | 3274 | struct drm_i915_gem_object *obj, *on; |
fa42331b | 3275 | |
dc97997a | 3276 | i915_check_and_clear_faults(dev_priv); |
fa42331b DV |
3277 | |
3278 | /* First fill our portion of the GTT with scratch pages */ | |
4fb84d99 | 3279 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total); |
fa42331b | 3280 | |
fbb30a5c CW |
3281 | ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */ |
3282 | ||
3283 | /* clflush objects bound into the GGTT and rebind them. */ | |
3284 | list_for_each_entry_safe(obj, on, | |
56cea323 | 3285 | &dev_priv->mm.bound_list, global_link) { |
fbb30a5c CW |
3286 | bool ggtt_bound = false; |
3287 | struct i915_vma *vma; | |
3288 | ||
1c7f4bca | 3289 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
72e96d64 | 3290 | if (vma->vm != &ggtt->base) |
2c3d9984 | 3291 | continue; |
fa42331b | 3292 | |
fbb30a5c CW |
3293 | if (!i915_vma_unbind(vma)) |
3294 | continue; | |
3295 | ||
2c3d9984 TU |
3296 | WARN_ON(i915_vma_bind(vma, obj->cache_level, |
3297 | PIN_UPDATE)); | |
fbb30a5c | 3298 | ggtt_bound = true; |
2c3d9984 TU |
3299 | } |
3300 | ||
fbb30a5c | 3301 | if (ggtt_bound) |
975f7ff4 | 3302 | WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); |
2c3d9984 | 3303 | } |
fa42331b | 3304 | |
fbb30a5c CW |
3305 | ggtt->base.closed = false; |
3306 | ||
275a991c | 3307 | if (INTEL_GEN(dev_priv) >= 8) { |
cc3f90f0 | 3308 | if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) |
fa42331b DV |
3309 | chv_setup_private_ppat(dev_priv); |
3310 | else | |
3311 | bdw_setup_private_ppat(dev_priv); | |
3312 | ||
3313 | return; | |
3314 | } | |
3315 | ||
275a991c | 3316 | if (USES_PPGTT(dev_priv)) { |
72e96d64 JL |
3317 | struct i915_address_space *vm; |
3318 | ||
fa42331b DV |
3319 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3320 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
3321 | ||
e5716f55 | 3322 | struct i915_hw_ppgtt *ppgtt; |
fa42331b | 3323 | |
2bfa996e | 3324 | if (i915_is_ggtt(vm)) |
fa42331b | 3325 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
e5716f55 JL |
3326 | else |
3327 | ppgtt = i915_vm_to_ppgtt(vm); | |
fa42331b DV |
3328 | |
3329 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
3330 | 0, ppgtt->base.total); | |
3331 | } | |
3332 | } | |
3333 | ||
3334 | i915_ggtt_flush(dev_priv); | |
3335 | } | |
3336 | ||
6f65e29a | 3337 | struct i915_vma * |
058d88c4 CW |
3338 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3339 | struct i915_address_space *vm, | |
3340 | const struct i915_ggtt_view *view) | |
ec7adb6e | 3341 | { |
db6c2b41 | 3342 | struct rb_node *rb; |
ec7adb6e | 3343 | |
db6c2b41 CW |
3344 | rb = obj->vma_tree.rb_node; |
3345 | while (rb) { | |
3346 | struct i915_vma *vma = rb_entry(rb, struct i915_vma, obj_node); | |
3347 | long cmp; | |
3348 | ||
b42fe9ca | 3349 | cmp = i915_vma_compare(vma, vm, view); |
db6c2b41 | 3350 | if (cmp == 0) |
058d88c4 | 3351 | return vma; |
ec7adb6e | 3352 | |
db6c2b41 CW |
3353 | if (cmp < 0) |
3354 | rb = rb->rb_right; | |
3355 | else | |
3356 | rb = rb->rb_left; | |
3357 | } | |
3358 | ||
058d88c4 | 3359 | return NULL; |
ec7adb6e JL |
3360 | } |
3361 | ||
3362 | struct i915_vma * | |
058d88c4 CW |
3363 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
3364 | struct i915_address_space *vm, | |
3365 | const struct i915_ggtt_view *view) | |
6f65e29a | 3366 | { |
058d88c4 | 3367 | struct i915_vma *vma; |
ec7adb6e | 3368 | |
4c7d62c6 | 3369 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
058d88c4 | 3370 | GEM_BUG_ON(view && !i915_is_ggtt(vm)); |
de895082 | 3371 | |
058d88c4 | 3372 | vma = i915_gem_obj_to_vma(obj, vm, view); |
db6c2b41 | 3373 | if (!vma) { |
b42fe9ca | 3374 | vma = i915_vma_create(obj, vm, view); |
db6c2b41 CW |
3375 | GEM_BUG_ON(vma != i915_gem_obj_to_vma(obj, vm, view)); |
3376 | } | |
6f65e29a | 3377 | |
3272db53 | 3378 | GEM_BUG_ON(i915_vma_is_closed(vma)); |
6f65e29a BW |
3379 | return vma; |
3380 | } | |
fe14d5f4 | 3381 | |
804beb4b | 3382 | static struct scatterlist * |
2d7f3bdb | 3383 | rotate_pages(const dma_addr_t *in, unsigned int offset, |
804beb4b | 3384 | unsigned int width, unsigned int height, |
87130255 | 3385 | unsigned int stride, |
804beb4b | 3386 | struct sg_table *st, struct scatterlist *sg) |
50470bb0 TU |
3387 | { |
3388 | unsigned int column, row; | |
3389 | unsigned int src_idx; | |
50470bb0 | 3390 | |
50470bb0 | 3391 | for (column = 0; column < width; column++) { |
87130255 | 3392 | src_idx = stride * (height - 1) + column; |
50470bb0 TU |
3393 | for (row = 0; row < height; row++) { |
3394 | st->nents++; | |
3395 | /* We don't need the pages, but need to initialize | |
3396 | * the entries so the sg list can be happily traversed. | |
3397 | * The only thing we need are DMA addresses. | |
3398 | */ | |
3399 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
804beb4b | 3400 | sg_dma_address(sg) = in[offset + src_idx]; |
50470bb0 TU |
3401 | sg_dma_len(sg) = PAGE_SIZE; |
3402 | sg = sg_next(sg); | |
87130255 | 3403 | src_idx -= stride; |
50470bb0 TU |
3404 | } |
3405 | } | |
804beb4b TU |
3406 | |
3407 | return sg; | |
50470bb0 TU |
3408 | } |
3409 | ||
3410 | static struct sg_table * | |
6687c906 | 3411 | intel_rotate_fb_obj_pages(const struct intel_rotation_info *rot_info, |
50470bb0 TU |
3412 | struct drm_i915_gem_object *obj) |
3413 | { | |
85d1225e | 3414 | const size_t n_pages = obj->base.size / PAGE_SIZE; |
6687c906 | 3415 | unsigned int size = intel_rotation_info_size(rot_info); |
85d1225e DG |
3416 | struct sgt_iter sgt_iter; |
3417 | dma_addr_t dma_addr; | |
50470bb0 TU |
3418 | unsigned long i; |
3419 | dma_addr_t *page_addr_list; | |
3420 | struct sg_table *st; | |
89e3e142 | 3421 | struct scatterlist *sg; |
1d00dad5 | 3422 | int ret = -ENOMEM; |
50470bb0 | 3423 | |
50470bb0 | 3424 | /* Allocate a temporary list of source pages for random access. */ |
85d1225e | 3425 | page_addr_list = drm_malloc_gfp(n_pages, |
f2a85e19 CW |
3426 | sizeof(dma_addr_t), |
3427 | GFP_TEMPORARY); | |
50470bb0 TU |
3428 | if (!page_addr_list) |
3429 | return ERR_PTR(ret); | |
3430 | ||
3431 | /* Allocate target SG list. */ | |
3432 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3433 | if (!st) | |
3434 | goto err_st_alloc; | |
3435 | ||
6687c906 | 3436 | ret = sg_alloc_table(st, size, GFP_KERNEL); |
50470bb0 TU |
3437 | if (ret) |
3438 | goto err_sg_alloc; | |
3439 | ||
3440 | /* Populate source page list from the object. */ | |
3441 | i = 0; | |
a4f5ea64 | 3442 | for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages) |
85d1225e | 3443 | page_addr_list[i++] = dma_addr; |
50470bb0 | 3444 | |
85d1225e | 3445 | GEM_BUG_ON(i != n_pages); |
11f20322 VS |
3446 | st->nents = 0; |
3447 | sg = st->sgl; | |
3448 | ||
6687c906 VS |
3449 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) { |
3450 | sg = rotate_pages(page_addr_list, rot_info->plane[i].offset, | |
3451 | rot_info->plane[i].width, rot_info->plane[i].height, | |
3452 | rot_info->plane[i].stride, st, sg); | |
89e3e142 TU |
3453 | } |
3454 | ||
6687c906 VS |
3455 | DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n", |
3456 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
50470bb0 TU |
3457 | |
3458 | drm_free_large(page_addr_list); | |
3459 | ||
3460 | return st; | |
3461 | ||
3462 | err_sg_alloc: | |
3463 | kfree(st); | |
3464 | err_st_alloc: | |
3465 | drm_free_large(page_addr_list); | |
3466 | ||
6687c906 VS |
3467 | DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n", |
3468 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
3469 | ||
50470bb0 TU |
3470 | return ERR_PTR(ret); |
3471 | } | |
ec7adb6e | 3472 | |
8bd7ef16 JL |
3473 | static struct sg_table * |
3474 | intel_partial_pages(const struct i915_ggtt_view *view, | |
3475 | struct drm_i915_gem_object *obj) | |
3476 | { | |
3477 | struct sg_table *st; | |
d2a84a76 CW |
3478 | struct scatterlist *sg, *iter; |
3479 | unsigned int count = view->params.partial.size; | |
3480 | unsigned int offset; | |
8bd7ef16 JL |
3481 | int ret = -ENOMEM; |
3482 | ||
3483 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3484 | if (!st) | |
3485 | goto err_st_alloc; | |
3486 | ||
d2a84a76 | 3487 | ret = sg_alloc_table(st, count, GFP_KERNEL); |
8bd7ef16 JL |
3488 | if (ret) |
3489 | goto err_sg_alloc; | |
3490 | ||
d2a84a76 CW |
3491 | iter = i915_gem_object_get_sg(obj, |
3492 | view->params.partial.offset, | |
3493 | &offset); | |
3494 | GEM_BUG_ON(!iter); | |
3495 | ||
8bd7ef16 JL |
3496 | sg = st->sgl; |
3497 | st->nents = 0; | |
d2a84a76 CW |
3498 | do { |
3499 | unsigned int len; | |
8bd7ef16 | 3500 | |
d2a84a76 CW |
3501 | len = min(iter->length - (offset << PAGE_SHIFT), |
3502 | count << PAGE_SHIFT); | |
3503 | sg_set_page(sg, NULL, len, 0); | |
3504 | sg_dma_address(sg) = | |
3505 | sg_dma_address(iter) + (offset << PAGE_SHIFT); | |
3506 | sg_dma_len(sg) = len; | |
8bd7ef16 | 3507 | |
8bd7ef16 | 3508 | st->nents++; |
d2a84a76 CW |
3509 | count -= len >> PAGE_SHIFT; |
3510 | if (count == 0) { | |
3511 | sg_mark_end(sg); | |
3512 | return st; | |
3513 | } | |
8bd7ef16 | 3514 | |
d2a84a76 CW |
3515 | sg = __sg_next(sg); |
3516 | iter = __sg_next(iter); | |
3517 | offset = 0; | |
3518 | } while (1); | |
8bd7ef16 JL |
3519 | |
3520 | err_sg_alloc: | |
3521 | kfree(st); | |
3522 | err_st_alloc: | |
3523 | return ERR_PTR(ret); | |
3524 | } | |
3525 | ||
70b9f6f8 | 3526 | static int |
50470bb0 | 3527 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 3528 | { |
50470bb0 TU |
3529 | int ret = 0; |
3530 | ||
2c3a3f44 CW |
3531 | /* The vma->pages are only valid within the lifespan of the borrowed |
3532 | * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so | |
3533 | * must be the vma->pages. A simple rule is that vma->pages must only | |
3534 | * be accessed when the obj->mm.pages are pinned. | |
3535 | */ | |
3536 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj)); | |
3537 | ||
247177dd | 3538 | if (vma->pages) |
fe14d5f4 TU |
3539 | return 0; |
3540 | ||
3541 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
a4f5ea64 | 3542 | vma->pages = vma->obj->mm.pages; |
50470bb0 | 3543 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
247177dd | 3544 | vma->pages = |
11d23e6f | 3545 | intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj); |
8bd7ef16 | 3546 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
247177dd | 3547 | vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj); |
fe14d5f4 TU |
3548 | else |
3549 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
3550 | vma->ggtt_view.type); | |
3551 | ||
247177dd | 3552 | if (!vma->pages) { |
ec7adb6e | 3553 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 3554 | vma->ggtt_view.type); |
50470bb0 | 3555 | ret = -EINVAL; |
247177dd CW |
3556 | } else if (IS_ERR(vma->pages)) { |
3557 | ret = PTR_ERR(vma->pages); | |
3558 | vma->pages = NULL; | |
50470bb0 TU |
3559 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", |
3560 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
3561 | } |
3562 | ||
50470bb0 | 3563 | return ret; |
fe14d5f4 TU |
3564 | } |
3565 |