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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
5bab6f60 | 27 | #include <linux/stop_machine.h> |
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
76aaf220 | 30 | #include "i915_drv.h" |
5dda8fa3 | 31 | #include "i915_vgpu.h" |
76aaf220 DV |
32 | #include "i915_trace.h" |
33 | #include "intel_drv.h" | |
34 | ||
bb8f9cff CW |
35 | #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM) |
36 | ||
45f8f69a TU |
37 | /** |
38 | * DOC: Global GTT views | |
39 | * | |
40 | * Background and previous state | |
41 | * | |
42 | * Historically objects could exists (be bound) in global GTT space only as | |
43 | * singular instances with a view representing all of the object's backing pages | |
44 | * in a linear fashion. This view will be called a normal view. | |
45 | * | |
46 | * To support multiple views of the same object, where the number of mapped | |
47 | * pages is not equal to the backing store, or where the layout of the pages | |
48 | * is not linear, concept of a GGTT view was added. | |
49 | * | |
50 | * One example of an alternative view is a stereo display driven by a single | |
51 | * image. In this case we would have a framebuffer looking like this | |
52 | * (2x2 pages): | |
53 | * | |
54 | * 12 | |
55 | * 34 | |
56 | * | |
57 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
58 | * rendering. In contrast, fed to the display engine would be an alternative | |
59 | * view which could look something like this: | |
60 | * | |
61 | * 1212 | |
62 | * 3434 | |
63 | * | |
64 | * In this example both the size and layout of pages in the alternative view is | |
65 | * different from the normal view. | |
66 | * | |
67 | * Implementation and usage | |
68 | * | |
69 | * GGTT views are implemented using VMAs and are distinguished via enum | |
70 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
71 | * | |
72 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
73 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
74 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
75 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
76 | * |
77 | * As a helper for callers which are only interested in the normal view, | |
78 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
79 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
80 | * or with the normal GGTT view. | |
81 | * | |
82 | * Code wanting to add or use a new GGTT view needs to: | |
83 | * | |
84 | * 1. Add a new enum with a suitable name. | |
85 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
86 | * 3. Add support to i915_get_vma_pages(). | |
87 | * | |
88 | * New views are required to build a scatter-gather table from within the | |
89 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
90 | * exists for the lifetime of an VMA. | |
91 | * | |
92 | * Core API is designed to have copy semantics which means that passed in | |
93 | * struct i915_ggtt_view does not need to be persistent (left around after | |
94 | * calling the core API functions). | |
95 | * | |
96 | */ | |
97 | ||
ce7fda2e CW |
98 | static inline struct i915_ggtt * |
99 | i915_vm_to_ggtt(struct i915_address_space *vm) | |
100 | { | |
101 | GEM_BUG_ON(!i915_is_ggtt(vm)); | |
102 | return container_of(vm, struct i915_ggtt, base); | |
103 | } | |
104 | ||
70b9f6f8 DV |
105 | static int |
106 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
107 | ||
b5e16987 VS |
108 | const struct i915_ggtt_view i915_ggtt_view_normal = { |
109 | .type = I915_GGTT_VIEW_NORMAL, | |
110 | }; | |
9abc4648 | 111 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
b5e16987 | 112 | .type = I915_GGTT_VIEW_ROTATED, |
9abc4648 | 113 | }; |
fe14d5f4 | 114 | |
c033666a CW |
115 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
116 | int enable_ppgtt) | |
cfa7c862 | 117 | { |
1893a71b CW |
118 | bool has_aliasing_ppgtt; |
119 | bool has_full_ppgtt; | |
1f9a99e0 | 120 | bool has_full_48bit_ppgtt; |
1893a71b | 121 | |
c033666a CW |
122 | has_aliasing_ppgtt = INTEL_GEN(dev_priv) >= 6; |
123 | has_full_ppgtt = INTEL_GEN(dev_priv) >= 7; | |
124 | has_full_48bit_ppgtt = | |
125 | IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9; | |
1893a71b | 126 | |
e320d400 ZW |
127 | if (intel_vgpu_active(dev_priv)) { |
128 | /* emulation is too hard */ | |
129 | has_full_ppgtt = false; | |
130 | has_full_48bit_ppgtt = false; | |
131 | } | |
71ba2d64 | 132 | |
0e4ca100 CW |
133 | if (!has_aliasing_ppgtt) |
134 | return 0; | |
135 | ||
70ee45e1 DL |
136 | /* |
137 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
138 | * execlists, the sole mechanism available to submit work. | |
139 | */ | |
c033666a | 140 | if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9) |
cfa7c862 DV |
141 | return 0; |
142 | ||
143 | if (enable_ppgtt == 1) | |
144 | return 1; | |
145 | ||
1893a71b | 146 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
147 | return 2; |
148 | ||
1f9a99e0 MT |
149 | if (enable_ppgtt == 3 && has_full_48bit_ppgtt) |
150 | return 3; | |
151 | ||
93a25a9e DV |
152 | #ifdef CONFIG_INTEL_IOMMU |
153 | /* Disable ppgtt on SNB if VT-d is on. */ | |
c033666a | 154 | if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) { |
93a25a9e | 155 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
cfa7c862 | 156 | return 0; |
93a25a9e DV |
157 | } |
158 | #endif | |
159 | ||
62942ed7 | 160 | /* Early VLV doesn't have this */ |
91c8a326 | 161 | if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) { |
62942ed7 JB |
162 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
163 | return 0; | |
164 | } | |
165 | ||
e320d400 | 166 | if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) |
1f9a99e0 | 167 | return has_full_48bit_ppgtt ? 3 : 2; |
2f82bbdf MT |
168 | else |
169 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
170 | } |
171 | ||
70b9f6f8 DV |
172 | static int ppgtt_bind_vma(struct i915_vma *vma, |
173 | enum i915_cache_level cache_level, | |
174 | u32 unused) | |
47552659 DV |
175 | { |
176 | u32 pte_flags = 0; | |
177 | ||
247177dd CW |
178 | vma->pages = vma->obj->pages; |
179 | ||
47552659 DV |
180 | /* Currently applicable only to VLV */ |
181 | if (vma->obj->gt_ro) | |
182 | pte_flags |= PTE_READ_ONLY; | |
183 | ||
247177dd | 184 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
47552659 | 185 | cache_level, pte_flags); |
70b9f6f8 DV |
186 | |
187 | return 0; | |
47552659 DV |
188 | } |
189 | ||
190 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
191 | { | |
192 | vma->vm->clear_range(vma->vm, | |
193 | vma->node.start, | |
de180033 | 194 | vma->size, |
47552659 DV |
195 | true); |
196 | } | |
6f65e29a | 197 | |
2c642b07 DV |
198 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
199 | enum i915_cache_level level, | |
200 | bool valid) | |
94ec8f61 | 201 | { |
07749ef3 | 202 | gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
94ec8f61 | 203 | pte |= addr; |
63c42e56 BW |
204 | |
205 | switch (level) { | |
206 | case I915_CACHE_NONE: | |
fbe5d36e | 207 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
208 | break; |
209 | case I915_CACHE_WT: | |
210 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
211 | break; | |
212 | default: | |
213 | pte |= PPAT_CACHED_INDEX; | |
214 | break; | |
215 | } | |
216 | ||
94ec8f61 BW |
217 | return pte; |
218 | } | |
219 | ||
fe36f55d MK |
220 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
221 | const enum i915_cache_level level) | |
b1fe6673 | 222 | { |
07749ef3 | 223 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
224 | pde |= addr; |
225 | if (level != I915_CACHE_NONE) | |
226 | pde |= PPAT_CACHED_PDE_INDEX; | |
227 | else | |
228 | pde |= PPAT_UNCACHED_INDEX; | |
229 | return pde; | |
230 | } | |
231 | ||
762d9936 MT |
232 | #define gen8_pdpe_encode gen8_pde_encode |
233 | #define gen8_pml4e_encode gen8_pde_encode | |
234 | ||
07749ef3 MT |
235 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
236 | enum i915_cache_level level, | |
237 | bool valid, u32 unused) | |
54d12527 | 238 | { |
07749ef3 | 239 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 240 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
241 | |
242 | switch (level) { | |
350ec881 CW |
243 | case I915_CACHE_L3_LLC: |
244 | case I915_CACHE_LLC: | |
245 | pte |= GEN6_PTE_CACHE_LLC; | |
246 | break; | |
247 | case I915_CACHE_NONE: | |
248 | pte |= GEN6_PTE_UNCACHED; | |
249 | break; | |
250 | default: | |
5f77eeb0 | 251 | MISSING_CASE(level); |
350ec881 CW |
252 | } |
253 | ||
254 | return pte; | |
255 | } | |
256 | ||
07749ef3 MT |
257 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
258 | enum i915_cache_level level, | |
259 | bool valid, u32 unused) | |
350ec881 | 260 | { |
07749ef3 | 261 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
262 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
263 | ||
264 | switch (level) { | |
265 | case I915_CACHE_L3_LLC: | |
266 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
267 | break; |
268 | case I915_CACHE_LLC: | |
269 | pte |= GEN6_PTE_CACHE_LLC; | |
270 | break; | |
271 | case I915_CACHE_NONE: | |
9119708c | 272 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
273 | break; |
274 | default: | |
5f77eeb0 | 275 | MISSING_CASE(level); |
e7210c3c BW |
276 | } |
277 | ||
54d12527 BW |
278 | return pte; |
279 | } | |
280 | ||
07749ef3 MT |
281 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
282 | enum i915_cache_level level, | |
283 | bool valid, u32 flags) | |
93c34e70 | 284 | { |
07749ef3 | 285 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
286 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
287 | ||
24f3a8cf AG |
288 | if (!(flags & PTE_READ_ONLY)) |
289 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
290 | |
291 | if (level != I915_CACHE_NONE) | |
292 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
293 | ||
294 | return pte; | |
295 | } | |
296 | ||
07749ef3 MT |
297 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
298 | enum i915_cache_level level, | |
299 | bool valid, u32 unused) | |
9119708c | 300 | { |
07749ef3 | 301 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 302 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
303 | |
304 | if (level != I915_CACHE_NONE) | |
87a6b688 | 305 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
306 | |
307 | return pte; | |
308 | } | |
309 | ||
07749ef3 MT |
310 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
311 | enum i915_cache_level level, | |
312 | bool valid, u32 unused) | |
4d15c145 | 313 | { |
07749ef3 | 314 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
315 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
316 | ||
651d794f CW |
317 | switch (level) { |
318 | case I915_CACHE_NONE: | |
319 | break; | |
320 | case I915_CACHE_WT: | |
c51e9701 | 321 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
322 | break; |
323 | default: | |
c51e9701 | 324 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
325 | break; |
326 | } | |
4d15c145 BW |
327 | |
328 | return pte; | |
329 | } | |
330 | ||
c114f76a MK |
331 | static int __setup_page_dma(struct drm_device *dev, |
332 | struct i915_page_dma *p, gfp_t flags) | |
678d96fb | 333 | { |
c49d13ee | 334 | struct device *kdev = &dev->pdev->dev; |
678d96fb | 335 | |
c114f76a | 336 | p->page = alloc_page(flags); |
44159ddb MK |
337 | if (!p->page) |
338 | return -ENOMEM; | |
678d96fb | 339 | |
c49d13ee | 340 | p->daddr = dma_map_page(kdev, |
44159ddb | 341 | p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL); |
678d96fb | 342 | |
c49d13ee | 343 | if (dma_mapping_error(kdev, p->daddr)) { |
44159ddb MK |
344 | __free_page(p->page); |
345 | return -EINVAL; | |
346 | } | |
1266cdb1 MT |
347 | |
348 | return 0; | |
678d96fb BW |
349 | } |
350 | ||
c114f76a MK |
351 | static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
352 | { | |
bb8f9cff | 353 | return __setup_page_dma(dev, p, I915_GFP_DMA); |
c114f76a MK |
354 | } |
355 | ||
44159ddb | 356 | static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
06fda602 | 357 | { |
52a05c30 DW |
358 | struct pci_dev *pdev = dev->pdev; |
359 | ||
44159ddb | 360 | if (WARN_ON(!p->page)) |
06fda602 | 361 | return; |
678d96fb | 362 | |
52a05c30 | 363 | dma_unmap_page(&pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL); |
44159ddb MK |
364 | __free_page(p->page); |
365 | memset(p, 0, sizeof(*p)); | |
366 | } | |
367 | ||
d1c54acd | 368 | static void *kmap_page_dma(struct i915_page_dma *p) |
73eeea53 | 369 | { |
d1c54acd MK |
370 | return kmap_atomic(p->page); |
371 | } | |
73eeea53 | 372 | |
d1c54acd MK |
373 | /* We use the flushing unmap only with ppgtt structures: |
374 | * page directories, page tables and scratch pages. | |
375 | */ | |
e2d214ae | 376 | static void kunmap_page_dma(struct drm_i915_private *dev_priv, void *vaddr) |
d1c54acd | 377 | { |
73eeea53 MK |
378 | /* There are only few exceptions for gen >=6. chv and bxt. |
379 | * And we are not sure about the latter so play safe for now. | |
380 | */ | |
e2d214ae | 381 | if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) |
73eeea53 MK |
382 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
383 | ||
384 | kunmap_atomic(vaddr); | |
385 | } | |
386 | ||
567047be | 387 | #define kmap_px(px) kmap_page_dma(px_base(px)) |
e2d214ae TU |
388 | #define kunmap_px(ppgtt, vaddr) \ |
389 | kunmap_page_dma(to_i915((ppgtt)->base.dev), (vaddr)) | |
d1c54acd | 390 | |
567047be MK |
391 | #define setup_px(dev, px) setup_page_dma((dev), px_base(px)) |
392 | #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px)) | |
e2d214ae TU |
393 | #define fill_px(dev_priv, px, v) fill_page_dma((dev_priv), px_base(px), (v)) |
394 | #define fill32_px(dev_priv, px, v) \ | |
395 | fill_page_dma_32((dev_priv), px_base(px), (v)) | |
567047be | 396 | |
e2d214ae TU |
397 | static void fill_page_dma(struct drm_i915_private *dev_priv, |
398 | struct i915_page_dma *p, const uint64_t val) | |
d1c54acd MK |
399 | { |
400 | int i; | |
401 | uint64_t * const vaddr = kmap_page_dma(p); | |
402 | ||
403 | for (i = 0; i < 512; i++) | |
404 | vaddr[i] = val; | |
405 | ||
e2d214ae | 406 | kunmap_page_dma(dev_priv, vaddr); |
d1c54acd MK |
407 | } |
408 | ||
e2d214ae TU |
409 | static void fill_page_dma_32(struct drm_i915_private *dev_priv, |
410 | struct i915_page_dma *p, const uint32_t val32) | |
73eeea53 MK |
411 | { |
412 | uint64_t v = val32; | |
413 | ||
414 | v = v << 32 | val32; | |
415 | ||
e2d214ae | 416 | fill_page_dma(dev_priv, p, v); |
73eeea53 MK |
417 | } |
418 | ||
8bcdd0f7 | 419 | static int |
bb8f9cff CW |
420 | setup_scratch_page(struct drm_device *dev, |
421 | struct i915_page_dma *scratch, | |
422 | gfp_t gfp) | |
4ad2af1e | 423 | { |
bb8f9cff | 424 | return __setup_page_dma(dev, scratch, gfp | __GFP_ZERO); |
4ad2af1e MK |
425 | } |
426 | ||
8bcdd0f7 CW |
427 | static void cleanup_scratch_page(struct drm_device *dev, |
428 | struct i915_page_dma *scratch) | |
4ad2af1e | 429 | { |
8bcdd0f7 | 430 | cleanup_page_dma(dev, scratch); |
4ad2af1e MK |
431 | } |
432 | ||
8a1ebd74 | 433 | static struct i915_page_table *alloc_pt(struct drm_device *dev) |
06fda602 | 434 | { |
ec565b3c | 435 | struct i915_page_table *pt; |
678d96fb BW |
436 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
437 | GEN8_PTES : GEN6_PTES; | |
438 | int ret = -ENOMEM; | |
06fda602 BW |
439 | |
440 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
441 | if (!pt) | |
442 | return ERR_PTR(-ENOMEM); | |
443 | ||
678d96fb BW |
444 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
445 | GFP_KERNEL); | |
446 | ||
447 | if (!pt->used_ptes) | |
448 | goto fail_bitmap; | |
449 | ||
567047be | 450 | ret = setup_px(dev, pt); |
678d96fb | 451 | if (ret) |
44159ddb | 452 | goto fail_page_m; |
06fda602 BW |
453 | |
454 | return pt; | |
678d96fb | 455 | |
44159ddb | 456 | fail_page_m: |
678d96fb BW |
457 | kfree(pt->used_ptes); |
458 | fail_bitmap: | |
459 | kfree(pt); | |
460 | ||
461 | return ERR_PTR(ret); | |
06fda602 BW |
462 | } |
463 | ||
2e906bea | 464 | static void free_pt(struct drm_device *dev, struct i915_page_table *pt) |
06fda602 | 465 | { |
2e906bea MK |
466 | cleanup_px(dev, pt); |
467 | kfree(pt->used_ptes); | |
468 | kfree(pt); | |
469 | } | |
470 | ||
471 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
472 | struct i915_page_table *pt) | |
473 | { | |
474 | gen8_pte_t scratch_pte; | |
475 | ||
8bcdd0f7 | 476 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
2e906bea MK |
477 | I915_CACHE_LLC, true); |
478 | ||
e2d214ae | 479 | fill_px(to_i915(vm->dev), pt, scratch_pte); |
2e906bea MK |
480 | } |
481 | ||
482 | static void gen6_initialize_pt(struct i915_address_space *vm, | |
483 | struct i915_page_table *pt) | |
484 | { | |
485 | gen6_pte_t scratch_pte; | |
486 | ||
8bcdd0f7 | 487 | WARN_ON(vm->scratch_page.daddr == 0); |
2e906bea | 488 | |
8bcdd0f7 | 489 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
2e906bea MK |
490 | I915_CACHE_LLC, true, 0); |
491 | ||
e2d214ae | 492 | fill32_px(to_i915(vm->dev), pt, scratch_pte); |
06fda602 BW |
493 | } |
494 | ||
8a1ebd74 | 495 | static struct i915_page_directory *alloc_pd(struct drm_device *dev) |
06fda602 | 496 | { |
ec565b3c | 497 | struct i915_page_directory *pd; |
33c8819f | 498 | int ret = -ENOMEM; |
06fda602 BW |
499 | |
500 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
501 | if (!pd) | |
502 | return ERR_PTR(-ENOMEM); | |
503 | ||
33c8819f MT |
504 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
505 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
506 | if (!pd->used_pdes) | |
a08e111a | 507 | goto fail_bitmap; |
33c8819f | 508 | |
567047be | 509 | ret = setup_px(dev, pd); |
33c8819f | 510 | if (ret) |
a08e111a | 511 | goto fail_page_m; |
e5815a2e | 512 | |
06fda602 | 513 | return pd; |
33c8819f | 514 | |
a08e111a | 515 | fail_page_m: |
33c8819f | 516 | kfree(pd->used_pdes); |
a08e111a | 517 | fail_bitmap: |
33c8819f MT |
518 | kfree(pd); |
519 | ||
520 | return ERR_PTR(ret); | |
06fda602 BW |
521 | } |
522 | ||
2e906bea MK |
523 | static void free_pd(struct drm_device *dev, struct i915_page_directory *pd) |
524 | { | |
525 | if (px_page(pd)) { | |
526 | cleanup_px(dev, pd); | |
527 | kfree(pd->used_pdes); | |
528 | kfree(pd); | |
529 | } | |
530 | } | |
531 | ||
532 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
533 | struct i915_page_directory *pd) | |
534 | { | |
535 | gen8_pde_t scratch_pde; | |
536 | ||
537 | scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); | |
538 | ||
e2d214ae | 539 | fill_px(to_i915(vm->dev), pd, scratch_pde); |
2e906bea MK |
540 | } |
541 | ||
6ac18502 MT |
542 | static int __pdp_init(struct drm_device *dev, |
543 | struct i915_page_directory_pointer *pdp) | |
544 | { | |
545 | size_t pdpes = I915_PDPES_PER_PDP(dev); | |
546 | ||
547 | pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes), | |
548 | sizeof(unsigned long), | |
549 | GFP_KERNEL); | |
550 | if (!pdp->used_pdpes) | |
551 | return -ENOMEM; | |
552 | ||
553 | pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory), | |
554 | GFP_KERNEL); | |
555 | if (!pdp->page_directory) { | |
556 | kfree(pdp->used_pdpes); | |
557 | /* the PDP might be the statically allocated top level. Keep it | |
558 | * as clean as possible */ | |
559 | pdp->used_pdpes = NULL; | |
560 | return -ENOMEM; | |
561 | } | |
562 | ||
563 | return 0; | |
564 | } | |
565 | ||
566 | static void __pdp_fini(struct i915_page_directory_pointer *pdp) | |
567 | { | |
568 | kfree(pdp->used_pdpes); | |
569 | kfree(pdp->page_directory); | |
570 | pdp->page_directory = NULL; | |
571 | } | |
572 | ||
762d9936 MT |
573 | static struct |
574 | i915_page_directory_pointer *alloc_pdp(struct drm_device *dev) | |
575 | { | |
576 | struct i915_page_directory_pointer *pdp; | |
577 | int ret = -ENOMEM; | |
578 | ||
579 | WARN_ON(!USES_FULL_48BIT_PPGTT(dev)); | |
580 | ||
581 | pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); | |
582 | if (!pdp) | |
583 | return ERR_PTR(-ENOMEM); | |
584 | ||
585 | ret = __pdp_init(dev, pdp); | |
586 | if (ret) | |
587 | goto fail_bitmap; | |
588 | ||
589 | ret = setup_px(dev, pdp); | |
590 | if (ret) | |
591 | goto fail_page_m; | |
592 | ||
593 | return pdp; | |
594 | ||
595 | fail_page_m: | |
596 | __pdp_fini(pdp); | |
597 | fail_bitmap: | |
598 | kfree(pdp); | |
599 | ||
600 | return ERR_PTR(ret); | |
601 | } | |
602 | ||
6ac18502 MT |
603 | static void free_pdp(struct drm_device *dev, |
604 | struct i915_page_directory_pointer *pdp) | |
605 | { | |
606 | __pdp_fini(pdp); | |
762d9936 MT |
607 | if (USES_FULL_48BIT_PPGTT(dev)) { |
608 | cleanup_px(dev, pdp); | |
609 | kfree(pdp); | |
610 | } | |
611 | } | |
612 | ||
69ab76fd MT |
613 | static void gen8_initialize_pdp(struct i915_address_space *vm, |
614 | struct i915_page_directory_pointer *pdp) | |
615 | { | |
616 | gen8_ppgtt_pdpe_t scratch_pdpe; | |
617 | ||
618 | scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC); | |
619 | ||
e2d214ae | 620 | fill_px(to_i915(vm->dev), pdp, scratch_pdpe); |
69ab76fd MT |
621 | } |
622 | ||
623 | static void gen8_initialize_pml4(struct i915_address_space *vm, | |
624 | struct i915_pml4 *pml4) | |
625 | { | |
626 | gen8_ppgtt_pml4e_t scratch_pml4e; | |
627 | ||
628 | scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp), | |
629 | I915_CACHE_LLC); | |
630 | ||
e2d214ae | 631 | fill_px(to_i915(vm->dev), pml4, scratch_pml4e); |
69ab76fd MT |
632 | } |
633 | ||
762d9936 MT |
634 | static void |
635 | gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt, | |
636 | struct i915_page_directory_pointer *pdp, | |
637 | struct i915_page_directory *pd, | |
638 | int index) | |
639 | { | |
640 | gen8_ppgtt_pdpe_t *page_directorypo; | |
641 | ||
642 | if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
643 | return; | |
644 | ||
645 | page_directorypo = kmap_px(pdp); | |
646 | page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); | |
647 | kunmap_px(ppgtt, page_directorypo); | |
648 | } | |
649 | ||
650 | static void | |
651 | gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt, | |
652 | struct i915_pml4 *pml4, | |
653 | struct i915_page_directory_pointer *pdp, | |
654 | int index) | |
655 | { | |
656 | gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4); | |
657 | ||
658 | WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)); | |
659 | pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); | |
660 | kunmap_px(ppgtt, pagemap); | |
6ac18502 MT |
661 | } |
662 | ||
94e409c1 | 663 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 664 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
665 | unsigned entry, |
666 | dma_addr_t addr) | |
94e409c1 | 667 | { |
7e37f889 | 668 | struct intel_ring *ring = req->ring; |
4a570db5 | 669 | struct intel_engine_cs *engine = req->engine; |
94e409c1 BW |
670 | int ret; |
671 | ||
672 | BUG_ON(entry >= 4); | |
673 | ||
5fb9de1a | 674 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
675 | if (ret) |
676 | return ret; | |
677 | ||
b5321f30 CW |
678 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
679 | intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, entry)); | |
680 | intel_ring_emit(ring, upper_32_bits(addr)); | |
681 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
682 | intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, entry)); | |
683 | intel_ring_emit(ring, lower_32_bits(addr)); | |
684 | intel_ring_advance(ring); | |
94e409c1 BW |
685 | |
686 | return 0; | |
687 | } | |
688 | ||
2dba3239 MT |
689 | static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt, |
690 | struct drm_i915_gem_request *req) | |
94e409c1 | 691 | { |
eeb9488e | 692 | int i, ret; |
94e409c1 | 693 | |
7cb6d7ac | 694 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
695 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
696 | ||
e85b26dc | 697 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
698 | if (ret) |
699 | return ret; | |
94e409c1 | 700 | } |
d595bd4b | 701 | |
eeb9488e | 702 | return 0; |
94e409c1 BW |
703 | } |
704 | ||
2dba3239 MT |
705 | static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt, |
706 | struct drm_i915_gem_request *req) | |
707 | { | |
708 | return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4)); | |
709 | } | |
710 | ||
f9b5b782 MT |
711 | static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm, |
712 | struct i915_page_directory_pointer *pdp, | |
713 | uint64_t start, | |
714 | uint64_t length, | |
715 | gen8_pte_t scratch_pte) | |
459108b8 | 716 | { |
e5716f55 | 717 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
f9b5b782 | 718 | gen8_pte_t *pt_vaddr; |
de5ba8eb MT |
719 | unsigned pdpe = gen8_pdpe_index(start); |
720 | unsigned pde = gen8_pde_index(start); | |
721 | unsigned pte = gen8_pte_index(start); | |
782f1495 | 722 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
723 | unsigned last_pte, i; |
724 | ||
f9b5b782 MT |
725 | if (WARN_ON(!pdp)) |
726 | return; | |
459108b8 BW |
727 | |
728 | while (num_entries) { | |
ec565b3c MT |
729 | struct i915_page_directory *pd; |
730 | struct i915_page_table *pt; | |
06fda602 | 731 | |
d4ec9da0 | 732 | if (WARN_ON(!pdp->page_directory[pdpe])) |
00245266 | 733 | break; |
06fda602 | 734 | |
d4ec9da0 | 735 | pd = pdp->page_directory[pdpe]; |
06fda602 BW |
736 | |
737 | if (WARN_ON(!pd->page_table[pde])) | |
00245266 | 738 | break; |
06fda602 BW |
739 | |
740 | pt = pd->page_table[pde]; | |
741 | ||
567047be | 742 | if (WARN_ON(!px_page(pt))) |
00245266 | 743 | break; |
06fda602 | 744 | |
7ad47cf2 | 745 | last_pte = pte + num_entries; |
07749ef3 MT |
746 | if (last_pte > GEN8_PTES) |
747 | last_pte = GEN8_PTES; | |
459108b8 | 748 | |
d1c54acd | 749 | pt_vaddr = kmap_px(pt); |
459108b8 | 750 | |
7ad47cf2 | 751 | for (i = pte; i < last_pte; i++) { |
459108b8 | 752 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
753 | num_entries--; |
754 | } | |
459108b8 | 755 | |
44a71024 | 756 | kunmap_px(ppgtt, pt_vaddr); |
459108b8 | 757 | |
7ad47cf2 | 758 | pte = 0; |
07749ef3 | 759 | if (++pde == I915_PDES) { |
de5ba8eb MT |
760 | if (++pdpe == I915_PDPES_PER_PDP(vm->dev)) |
761 | break; | |
7ad47cf2 BW |
762 | pde = 0; |
763 | } | |
459108b8 BW |
764 | } |
765 | } | |
766 | ||
f9b5b782 MT |
767 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
768 | uint64_t start, | |
769 | uint64_t length, | |
770 | bool use_scratch) | |
9df15b49 | 771 | { |
e5716f55 | 772 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
8bcdd0f7 | 773 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
f9b5b782 MT |
774 | I915_CACHE_LLC, use_scratch); |
775 | ||
de5ba8eb MT |
776 | if (!USES_FULL_48BIT_PPGTT(vm->dev)) { |
777 | gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length, | |
778 | scratch_pte); | |
779 | } else { | |
e8ebd8e2 | 780 | uint64_t pml4e; |
de5ba8eb MT |
781 | struct i915_page_directory_pointer *pdp; |
782 | ||
e8ebd8e2 | 783 | gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) { |
de5ba8eb MT |
784 | gen8_ppgtt_clear_pte_range(vm, pdp, start, length, |
785 | scratch_pte); | |
786 | } | |
787 | } | |
f9b5b782 MT |
788 | } |
789 | ||
790 | static void | |
791 | gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, | |
792 | struct i915_page_directory_pointer *pdp, | |
3387d433 | 793 | struct sg_page_iter *sg_iter, |
f9b5b782 MT |
794 | uint64_t start, |
795 | enum i915_cache_level cache_level) | |
796 | { | |
e5716f55 | 797 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 798 | gen8_pte_t *pt_vaddr; |
de5ba8eb MT |
799 | unsigned pdpe = gen8_pdpe_index(start); |
800 | unsigned pde = gen8_pde_index(start); | |
801 | unsigned pte = gen8_pte_index(start); | |
9df15b49 | 802 | |
6f1cc993 | 803 | pt_vaddr = NULL; |
7ad47cf2 | 804 | |
3387d433 | 805 | while (__sg_page_iter_next(sg_iter)) { |
d7b3de91 | 806 | if (pt_vaddr == NULL) { |
d4ec9da0 | 807 | struct i915_page_directory *pd = pdp->page_directory[pdpe]; |
ec565b3c | 808 | struct i915_page_table *pt = pd->page_table[pde]; |
d1c54acd | 809 | pt_vaddr = kmap_px(pt); |
d7b3de91 | 810 | } |
9df15b49 | 811 | |
7ad47cf2 | 812 | pt_vaddr[pte] = |
3387d433 | 813 | gen8_pte_encode(sg_page_iter_dma_address(sg_iter), |
6f1cc993 | 814 | cache_level, true); |
07749ef3 | 815 | if (++pte == GEN8_PTES) { |
d1c54acd | 816 | kunmap_px(ppgtt, pt_vaddr); |
6f1cc993 | 817 | pt_vaddr = NULL; |
07749ef3 | 818 | if (++pde == I915_PDES) { |
de5ba8eb MT |
819 | if (++pdpe == I915_PDPES_PER_PDP(vm->dev)) |
820 | break; | |
7ad47cf2 BW |
821 | pde = 0; |
822 | } | |
823 | pte = 0; | |
9df15b49 BW |
824 | } |
825 | } | |
d1c54acd MK |
826 | |
827 | if (pt_vaddr) | |
828 | kunmap_px(ppgtt, pt_vaddr); | |
9df15b49 BW |
829 | } |
830 | ||
f9b5b782 MT |
831 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
832 | struct sg_table *pages, | |
833 | uint64_t start, | |
834 | enum i915_cache_level cache_level, | |
835 | u32 unused) | |
836 | { | |
e5716f55 | 837 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3387d433 | 838 | struct sg_page_iter sg_iter; |
f9b5b782 | 839 | |
3387d433 | 840 | __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0); |
de5ba8eb MT |
841 | |
842 | if (!USES_FULL_48BIT_PPGTT(vm->dev)) { | |
843 | gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start, | |
844 | cache_level); | |
845 | } else { | |
846 | struct i915_page_directory_pointer *pdp; | |
e8ebd8e2 | 847 | uint64_t pml4e; |
de5ba8eb MT |
848 | uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT; |
849 | ||
e8ebd8e2 | 850 | gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) { |
de5ba8eb MT |
851 | gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter, |
852 | start, cache_level); | |
853 | } | |
854 | } | |
f9b5b782 MT |
855 | } |
856 | ||
f37c0505 MT |
857 | static void gen8_free_page_tables(struct drm_device *dev, |
858 | struct i915_page_directory *pd) | |
7ad47cf2 BW |
859 | { |
860 | int i; | |
861 | ||
567047be | 862 | if (!px_page(pd)) |
7ad47cf2 BW |
863 | return; |
864 | ||
33c8819f | 865 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
866 | if (WARN_ON(!pd->page_table[i])) |
867 | continue; | |
7ad47cf2 | 868 | |
a08e111a | 869 | free_pt(dev, pd->page_table[i]); |
06fda602 BW |
870 | pd->page_table[i] = NULL; |
871 | } | |
d7b3de91 BW |
872 | } |
873 | ||
8776f02b MK |
874 | static int gen8_init_scratch(struct i915_address_space *vm) |
875 | { | |
876 | struct drm_device *dev = vm->dev; | |
64c050db | 877 | int ret; |
8776f02b | 878 | |
bb8f9cff | 879 | ret = setup_scratch_page(dev, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
880 | if (ret) |
881 | return ret; | |
8776f02b MK |
882 | |
883 | vm->scratch_pt = alloc_pt(dev); | |
884 | if (IS_ERR(vm->scratch_pt)) { | |
64c050db MA |
885 | ret = PTR_ERR(vm->scratch_pt); |
886 | goto free_scratch_page; | |
8776f02b MK |
887 | } |
888 | ||
889 | vm->scratch_pd = alloc_pd(dev); | |
890 | if (IS_ERR(vm->scratch_pd)) { | |
64c050db MA |
891 | ret = PTR_ERR(vm->scratch_pd); |
892 | goto free_pt; | |
8776f02b MK |
893 | } |
894 | ||
69ab76fd MT |
895 | if (USES_FULL_48BIT_PPGTT(dev)) { |
896 | vm->scratch_pdp = alloc_pdp(dev); | |
897 | if (IS_ERR(vm->scratch_pdp)) { | |
64c050db MA |
898 | ret = PTR_ERR(vm->scratch_pdp); |
899 | goto free_pd; | |
69ab76fd MT |
900 | } |
901 | } | |
902 | ||
8776f02b MK |
903 | gen8_initialize_pt(vm, vm->scratch_pt); |
904 | gen8_initialize_pd(vm, vm->scratch_pd); | |
69ab76fd MT |
905 | if (USES_FULL_48BIT_PPGTT(dev)) |
906 | gen8_initialize_pdp(vm, vm->scratch_pdp); | |
8776f02b MK |
907 | |
908 | return 0; | |
64c050db MA |
909 | |
910 | free_pd: | |
911 | free_pd(dev, vm->scratch_pd); | |
912 | free_pt: | |
913 | free_pt(dev, vm->scratch_pt); | |
914 | free_scratch_page: | |
8bcdd0f7 | 915 | cleanup_scratch_page(dev, &vm->scratch_page); |
64c050db MA |
916 | |
917 | return ret; | |
8776f02b MK |
918 | } |
919 | ||
650da34c ZL |
920 | static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) |
921 | { | |
922 | enum vgt_g2v_type msg; | |
df28564d | 923 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); |
650da34c ZL |
924 | int i; |
925 | ||
df28564d | 926 | if (USES_FULL_48BIT_PPGTT(dev_priv)) { |
650da34c ZL |
927 | u64 daddr = px_dma(&ppgtt->pml4); |
928 | ||
ab75bb5d VS |
929 | I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr)); |
930 | I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr)); | |
650da34c ZL |
931 | |
932 | msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : | |
933 | VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); | |
934 | } else { | |
935 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
936 | u64 daddr = i915_page_dir_dma_addr(ppgtt, i); | |
937 | ||
ab75bb5d VS |
938 | I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr)); |
939 | I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr)); | |
650da34c ZL |
940 | } |
941 | ||
942 | msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : | |
943 | VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); | |
944 | } | |
945 | ||
946 | I915_WRITE(vgtif_reg(g2v_notify), msg); | |
947 | ||
948 | return 0; | |
949 | } | |
950 | ||
8776f02b MK |
951 | static void gen8_free_scratch(struct i915_address_space *vm) |
952 | { | |
953 | struct drm_device *dev = vm->dev; | |
954 | ||
69ab76fd MT |
955 | if (USES_FULL_48BIT_PPGTT(dev)) |
956 | free_pdp(dev, vm->scratch_pdp); | |
8776f02b MK |
957 | free_pd(dev, vm->scratch_pd); |
958 | free_pt(dev, vm->scratch_pt); | |
8bcdd0f7 | 959 | cleanup_scratch_page(dev, &vm->scratch_page); |
8776f02b MK |
960 | } |
961 | ||
762d9936 MT |
962 | static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev, |
963 | struct i915_page_directory_pointer *pdp) | |
b45a6715 BW |
964 | { |
965 | int i; | |
966 | ||
d4ec9da0 MT |
967 | for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) { |
968 | if (WARN_ON(!pdp->page_directory[i])) | |
06fda602 BW |
969 | continue; |
970 | ||
d4ec9da0 MT |
971 | gen8_free_page_tables(dev, pdp->page_directory[i]); |
972 | free_pd(dev, pdp->page_directory[i]); | |
7ad47cf2 | 973 | } |
69876bed | 974 | |
d4ec9da0 | 975 | free_pdp(dev, pdp); |
762d9936 MT |
976 | } |
977 | ||
978 | static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) | |
979 | { | |
980 | int i; | |
981 | ||
982 | for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) { | |
983 | if (WARN_ON(!ppgtt->pml4.pdps[i])) | |
984 | continue; | |
985 | ||
986 | gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]); | |
987 | } | |
988 | ||
989 | cleanup_px(ppgtt->base.dev, &ppgtt->pml4); | |
990 | } | |
991 | ||
992 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) | |
993 | { | |
e5716f55 | 994 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 995 | |
c033666a | 996 | if (intel_vgpu_active(to_i915(vm->dev))) |
650da34c ZL |
997 | gen8_ppgtt_notify_vgt(ppgtt, false); |
998 | ||
762d9936 MT |
999 | if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) |
1000 | gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp); | |
1001 | else | |
1002 | gen8_ppgtt_cleanup_4lvl(ppgtt); | |
d4ec9da0 | 1003 | |
8776f02b | 1004 | gen8_free_scratch(vm); |
b45a6715 BW |
1005 | } |
1006 | ||
d7b2633d MT |
1007 | /** |
1008 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
d4ec9da0 MT |
1009 | * @vm: Master vm structure. |
1010 | * @pd: Page directory for this address range. | |
d7b2633d | 1011 | * @start: Starting virtual address to begin allocations. |
d4ec9da0 | 1012 | * @length: Size of the allocations. |
d7b2633d MT |
1013 | * @new_pts: Bitmap set by function with new allocations. Likely used by the |
1014 | * caller to free on error. | |
1015 | * | |
1016 | * Allocate the required number of page tables. Extremely similar to | |
1017 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
1018 | * the page directory boundary (instead of the page directory pointer). That | |
1019 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
1020 | * possible, and likely that the caller will need to use multiple calls of this | |
1021 | * function to achieve the appropriate allocation. | |
1022 | * | |
1023 | * Return: 0 if success; negative error code otherwise. | |
1024 | */ | |
d4ec9da0 | 1025 | static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, |
e5815a2e | 1026 | struct i915_page_directory *pd, |
5441f0cb | 1027 | uint64_t start, |
d7b2633d MT |
1028 | uint64_t length, |
1029 | unsigned long *new_pts) | |
bf2b4ed2 | 1030 | { |
d4ec9da0 | 1031 | struct drm_device *dev = vm->dev; |
d7b2633d | 1032 | struct i915_page_table *pt; |
5441f0cb | 1033 | uint32_t pde; |
bf2b4ed2 | 1034 | |
e8ebd8e2 | 1035 | gen8_for_each_pde(pt, pd, start, length, pde) { |
d7b2633d | 1036 | /* Don't reallocate page tables */ |
6ac18502 | 1037 | if (test_bit(pde, pd->used_pdes)) { |
d7b2633d | 1038 | /* Scratch is never allocated this way */ |
d4ec9da0 | 1039 | WARN_ON(pt == vm->scratch_pt); |
d7b2633d MT |
1040 | continue; |
1041 | } | |
1042 | ||
8a1ebd74 | 1043 | pt = alloc_pt(dev); |
d7b2633d | 1044 | if (IS_ERR(pt)) |
5441f0cb MT |
1045 | goto unwind_out; |
1046 | ||
d4ec9da0 | 1047 | gen8_initialize_pt(vm, pt); |
d7b2633d | 1048 | pd->page_table[pde] = pt; |
966082c9 | 1049 | __set_bit(pde, new_pts); |
4c06ec8d | 1050 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT); |
7ad47cf2 BW |
1051 | } |
1052 | ||
bf2b4ed2 | 1053 | return 0; |
7ad47cf2 BW |
1054 | |
1055 | unwind_out: | |
d7b2633d | 1056 | for_each_set_bit(pde, new_pts, I915_PDES) |
a08e111a | 1057 | free_pt(dev, pd->page_table[pde]); |
7ad47cf2 | 1058 | |
d7b3de91 | 1059 | return -ENOMEM; |
bf2b4ed2 BW |
1060 | } |
1061 | ||
d7b2633d MT |
1062 | /** |
1063 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
d4ec9da0 | 1064 | * @vm: Master vm structure. |
d7b2633d MT |
1065 | * @pdp: Page directory pointer for this address range. |
1066 | * @start: Starting virtual address to begin allocations. | |
d4ec9da0 MT |
1067 | * @length: Size of the allocations. |
1068 | * @new_pds: Bitmap set by function with new allocations. Likely used by the | |
d7b2633d MT |
1069 | * caller to free on error. |
1070 | * | |
1071 | * Allocate the required number of page directories starting at the pde index of | |
1072 | * @start, and ending at the pde index @start + @length. This function will skip | |
1073 | * over already allocated page directories within the range, and only allocate | |
1074 | * new ones, setting the appropriate pointer within the pdp as well as the | |
1075 | * correct position in the bitmap @new_pds. | |
1076 | * | |
1077 | * The function will only allocate the pages within the range for a give page | |
1078 | * directory pointer. In other words, if @start + @length straddles a virtually | |
1079 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
1080 | * required by the caller, This is not currently possible, and the BUG in the | |
1081 | * code will prevent it. | |
1082 | * | |
1083 | * Return: 0 if success; negative error code otherwise. | |
1084 | */ | |
d4ec9da0 MT |
1085 | static int |
1086 | gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, | |
1087 | struct i915_page_directory_pointer *pdp, | |
1088 | uint64_t start, | |
1089 | uint64_t length, | |
1090 | unsigned long *new_pds) | |
bf2b4ed2 | 1091 | { |
d4ec9da0 | 1092 | struct drm_device *dev = vm->dev; |
d7b2633d | 1093 | struct i915_page_directory *pd; |
69876bed | 1094 | uint32_t pdpe; |
6ac18502 | 1095 | uint32_t pdpes = I915_PDPES_PER_PDP(dev); |
69876bed | 1096 | |
6ac18502 | 1097 | WARN_ON(!bitmap_empty(new_pds, pdpes)); |
d7b2633d | 1098 | |
e8ebd8e2 | 1099 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
6ac18502 | 1100 | if (test_bit(pdpe, pdp->used_pdpes)) |
d7b2633d | 1101 | continue; |
33c8819f | 1102 | |
8a1ebd74 | 1103 | pd = alloc_pd(dev); |
d7b2633d | 1104 | if (IS_ERR(pd)) |
d7b3de91 | 1105 | goto unwind_out; |
69876bed | 1106 | |
d4ec9da0 | 1107 | gen8_initialize_pd(vm, pd); |
d7b2633d | 1108 | pdp->page_directory[pdpe] = pd; |
966082c9 | 1109 | __set_bit(pdpe, new_pds); |
4c06ec8d | 1110 | trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT); |
d7b3de91 BW |
1111 | } |
1112 | ||
bf2b4ed2 | 1113 | return 0; |
d7b3de91 BW |
1114 | |
1115 | unwind_out: | |
6ac18502 | 1116 | for_each_set_bit(pdpe, new_pds, pdpes) |
a08e111a | 1117 | free_pd(dev, pdp->page_directory[pdpe]); |
d7b3de91 BW |
1118 | |
1119 | return -ENOMEM; | |
bf2b4ed2 BW |
1120 | } |
1121 | ||
762d9936 MT |
1122 | /** |
1123 | * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range. | |
1124 | * @vm: Master vm structure. | |
1125 | * @pml4: Page map level 4 for this address range. | |
1126 | * @start: Starting virtual address to begin allocations. | |
1127 | * @length: Size of the allocations. | |
1128 | * @new_pdps: Bitmap set by function with new allocations. Likely used by the | |
1129 | * caller to free on error. | |
1130 | * | |
1131 | * Allocate the required number of page directory pointers. Extremely similar to | |
1132 | * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs(). | |
1133 | * The main difference is here we are limited by the pml4 boundary (instead of | |
1134 | * the page directory pointer). | |
1135 | * | |
1136 | * Return: 0 if success; negative error code otherwise. | |
1137 | */ | |
1138 | static int | |
1139 | gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, | |
1140 | struct i915_pml4 *pml4, | |
1141 | uint64_t start, | |
1142 | uint64_t length, | |
1143 | unsigned long *new_pdps) | |
1144 | { | |
1145 | struct drm_device *dev = vm->dev; | |
1146 | struct i915_page_directory_pointer *pdp; | |
762d9936 MT |
1147 | uint32_t pml4e; |
1148 | ||
1149 | WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4)); | |
1150 | ||
e8ebd8e2 | 1151 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 MT |
1152 | if (!test_bit(pml4e, pml4->used_pml4es)) { |
1153 | pdp = alloc_pdp(dev); | |
1154 | if (IS_ERR(pdp)) | |
1155 | goto unwind_out; | |
1156 | ||
69ab76fd | 1157 | gen8_initialize_pdp(vm, pdp); |
762d9936 MT |
1158 | pml4->pdps[pml4e] = pdp; |
1159 | __set_bit(pml4e, new_pdps); | |
1160 | trace_i915_page_directory_pointer_entry_alloc(vm, | |
1161 | pml4e, | |
1162 | start, | |
1163 | GEN8_PML4E_SHIFT); | |
1164 | } | |
1165 | } | |
1166 | ||
1167 | return 0; | |
1168 | ||
1169 | unwind_out: | |
1170 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
1171 | free_pdp(dev, pml4->pdps[pml4e]); | |
1172 | ||
1173 | return -ENOMEM; | |
1174 | } | |
1175 | ||
d7b2633d | 1176 | static void |
3a41a05d | 1177 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts) |
d7b2633d | 1178 | { |
d7b2633d MT |
1179 | kfree(new_pts); |
1180 | kfree(new_pds); | |
1181 | } | |
1182 | ||
1183 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
1184 | * of these are based on the number of PDPEs in the system. | |
1185 | */ | |
1186 | static | |
1187 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
3a41a05d | 1188 | unsigned long **new_pts, |
6ac18502 | 1189 | uint32_t pdpes) |
d7b2633d | 1190 | { |
d7b2633d | 1191 | unsigned long *pds; |
3a41a05d | 1192 | unsigned long *pts; |
d7b2633d | 1193 | |
3a41a05d | 1194 | pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY); |
d7b2633d MT |
1195 | if (!pds) |
1196 | return -ENOMEM; | |
1197 | ||
3a41a05d MW |
1198 | pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long), |
1199 | GFP_TEMPORARY); | |
1200 | if (!pts) | |
1201 | goto err_out; | |
d7b2633d MT |
1202 | |
1203 | *new_pds = pds; | |
1204 | *new_pts = pts; | |
1205 | ||
1206 | return 0; | |
1207 | ||
1208 | err_out: | |
3a41a05d | 1209 | free_gen8_temp_bitmaps(pds, pts); |
d7b2633d MT |
1210 | return -ENOMEM; |
1211 | } | |
1212 | ||
5b7e4c9c MK |
1213 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
1214 | * the page table structures, we mark them dirty so that | |
1215 | * context switching/execlist queuing code takes extra steps | |
1216 | * to ensure that tlbs are flushed. | |
1217 | */ | |
1218 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
1219 | { | |
1220 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; | |
1221 | } | |
1222 | ||
762d9936 MT |
1223 | static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, |
1224 | struct i915_page_directory_pointer *pdp, | |
1225 | uint64_t start, | |
1226 | uint64_t length) | |
bf2b4ed2 | 1227 | { |
e5716f55 | 1228 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
3a41a05d | 1229 | unsigned long *new_page_dirs, *new_page_tables; |
d4ec9da0 | 1230 | struct drm_device *dev = vm->dev; |
5441f0cb | 1231 | struct i915_page_directory *pd; |
33c8819f MT |
1232 | const uint64_t orig_start = start; |
1233 | const uint64_t orig_length = length; | |
5441f0cb | 1234 | uint32_t pdpe; |
d4ec9da0 | 1235 | uint32_t pdpes = I915_PDPES_PER_PDP(dev); |
bf2b4ed2 BW |
1236 | int ret; |
1237 | ||
d7b2633d MT |
1238 | /* Wrap is never okay since we can only represent 48b, and we don't |
1239 | * actually use the other side of the canonical address space. | |
1240 | */ | |
1241 | if (WARN_ON(start + length < start)) | |
a05d80ee MK |
1242 | return -ENODEV; |
1243 | ||
d4ec9da0 | 1244 | if (WARN_ON(start + length > vm->total)) |
a05d80ee | 1245 | return -ENODEV; |
d7b2633d | 1246 | |
6ac18502 | 1247 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); |
bf2b4ed2 BW |
1248 | if (ret) |
1249 | return ret; | |
1250 | ||
d7b2633d | 1251 | /* Do the allocations first so we can easily bail out */ |
d4ec9da0 MT |
1252 | ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length, |
1253 | new_page_dirs); | |
d7b2633d | 1254 | if (ret) { |
3a41a05d | 1255 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
d7b2633d MT |
1256 | return ret; |
1257 | } | |
1258 | ||
1259 | /* For every page directory referenced, allocate page tables */ | |
e8ebd8e2 | 1260 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d4ec9da0 | 1261 | ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length, |
3a41a05d | 1262 | new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES)); |
5441f0cb MT |
1263 | if (ret) |
1264 | goto err_out; | |
5441f0cb MT |
1265 | } |
1266 | ||
33c8819f MT |
1267 | start = orig_start; |
1268 | length = orig_length; | |
1269 | ||
d7b2633d MT |
1270 | /* Allocations have completed successfully, so set the bitmaps, and do |
1271 | * the mappings. */ | |
e8ebd8e2 | 1272 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
d1c54acd | 1273 | gen8_pde_t *const page_directory = kmap_px(pd); |
33c8819f | 1274 | struct i915_page_table *pt; |
09120d4e | 1275 | uint64_t pd_len = length; |
33c8819f MT |
1276 | uint64_t pd_start = start; |
1277 | uint32_t pde; | |
1278 | ||
d7b2633d MT |
1279 | /* Every pd should be allocated, we just did that above. */ |
1280 | WARN_ON(!pd); | |
1281 | ||
e8ebd8e2 | 1282 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
d7b2633d MT |
1283 | /* Same reasoning as pd */ |
1284 | WARN_ON(!pt); | |
1285 | WARN_ON(!pd_len); | |
1286 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
1287 | ||
1288 | /* Set our used ptes within the page table */ | |
1289 | bitmap_set(pt->used_ptes, | |
1290 | gen8_pte_index(pd_start), | |
1291 | gen8_pte_count(pd_start, pd_len)); | |
1292 | ||
1293 | /* Our pde is now pointing to the pagetable, pt */ | |
966082c9 | 1294 | __set_bit(pde, pd->used_pdes); |
d7b2633d MT |
1295 | |
1296 | /* Map the PDE to the page table */ | |
fe36f55d MK |
1297 | page_directory[pde] = gen8_pde_encode(px_dma(pt), |
1298 | I915_CACHE_LLC); | |
4c06ec8d MT |
1299 | trace_i915_page_table_entry_map(&ppgtt->base, pde, pt, |
1300 | gen8_pte_index(start), | |
1301 | gen8_pte_count(start, length), | |
1302 | GEN8_PTES); | |
d7b2633d MT |
1303 | |
1304 | /* NB: We haven't yet mapped ptes to pages. At this | |
1305 | * point we're still relying on insert_entries() */ | |
33c8819f | 1306 | } |
d7b2633d | 1307 | |
d1c54acd | 1308 | kunmap_px(ppgtt, page_directory); |
d4ec9da0 | 1309 | __set_bit(pdpe, pdp->used_pdpes); |
762d9936 | 1310 | gen8_setup_page_directory(ppgtt, pdp, pd, pdpe); |
33c8819f MT |
1311 | } |
1312 | ||
3a41a05d | 1313 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1314 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 1315 | return 0; |
bf2b4ed2 | 1316 | |
d7b3de91 | 1317 | err_out: |
d7b2633d | 1318 | while (pdpe--) { |
e8ebd8e2 DG |
1319 | unsigned long temp; |
1320 | ||
3a41a05d MW |
1321 | for_each_set_bit(temp, new_page_tables + pdpe * |
1322 | BITS_TO_LONGS(I915_PDES), I915_PDES) | |
d4ec9da0 | 1323 | free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]); |
d7b2633d MT |
1324 | } |
1325 | ||
6ac18502 | 1326 | for_each_set_bit(pdpe, new_page_dirs, pdpes) |
d4ec9da0 | 1327 | free_pd(dev, pdp->page_directory[pdpe]); |
d7b2633d | 1328 | |
3a41a05d | 1329 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 1330 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
1331 | return ret; |
1332 | } | |
1333 | ||
762d9936 MT |
1334 | static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, |
1335 | struct i915_pml4 *pml4, | |
1336 | uint64_t start, | |
1337 | uint64_t length) | |
1338 | { | |
1339 | DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4); | |
e5716f55 | 1340 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 | 1341 | struct i915_page_directory_pointer *pdp; |
e8ebd8e2 | 1342 | uint64_t pml4e; |
762d9936 MT |
1343 | int ret = 0; |
1344 | ||
1345 | /* Do the pml4 allocations first, so we don't need to track the newly | |
1346 | * allocated tables below the pdp */ | |
1347 | bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4); | |
1348 | ||
1349 | /* The pagedirectory and pagetable allocations are done in the shared 3 | |
1350 | * and 4 level code. Just allocate the pdps. | |
1351 | */ | |
1352 | ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length, | |
1353 | new_pdps); | |
1354 | if (ret) | |
1355 | return ret; | |
1356 | ||
1357 | WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2, | |
1358 | "The allocation has spanned more than 512GB. " | |
1359 | "It is highly likely this is incorrect."); | |
1360 | ||
e8ebd8e2 | 1361 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
762d9936 MT |
1362 | WARN_ON(!pdp); |
1363 | ||
1364 | ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length); | |
1365 | if (ret) | |
1366 | goto err_out; | |
1367 | ||
1368 | gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e); | |
1369 | } | |
1370 | ||
1371 | bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es, | |
1372 | GEN8_PML4ES_PER_PML4); | |
1373 | ||
1374 | return 0; | |
1375 | ||
1376 | err_out: | |
1377 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
1378 | gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]); | |
1379 | ||
1380 | return ret; | |
1381 | } | |
1382 | ||
1383 | static int gen8_alloc_va_range(struct i915_address_space *vm, | |
1384 | uint64_t start, uint64_t length) | |
1385 | { | |
e5716f55 | 1386 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
762d9936 MT |
1387 | |
1388 | if (USES_FULL_48BIT_PPGTT(vm->dev)) | |
1389 | return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); | |
1390 | else | |
1391 | return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length); | |
1392 | } | |
1393 | ||
ea91e401 MT |
1394 | static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp, |
1395 | uint64_t start, uint64_t length, | |
1396 | gen8_pte_t scratch_pte, | |
1397 | struct seq_file *m) | |
1398 | { | |
1399 | struct i915_page_directory *pd; | |
ea91e401 MT |
1400 | uint32_t pdpe; |
1401 | ||
e8ebd8e2 | 1402 | gen8_for_each_pdpe(pd, pdp, start, length, pdpe) { |
ea91e401 MT |
1403 | struct i915_page_table *pt; |
1404 | uint64_t pd_len = length; | |
1405 | uint64_t pd_start = start; | |
1406 | uint32_t pde; | |
1407 | ||
1408 | if (!test_bit(pdpe, pdp->used_pdpes)) | |
1409 | continue; | |
1410 | ||
1411 | seq_printf(m, "\tPDPE #%d\n", pdpe); | |
e8ebd8e2 | 1412 | gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) { |
ea91e401 MT |
1413 | uint32_t pte; |
1414 | gen8_pte_t *pt_vaddr; | |
1415 | ||
1416 | if (!test_bit(pde, pd->used_pdes)) | |
1417 | continue; | |
1418 | ||
1419 | pt_vaddr = kmap_px(pt); | |
1420 | for (pte = 0; pte < GEN8_PTES; pte += 4) { | |
1421 | uint64_t va = | |
1422 | (pdpe << GEN8_PDPE_SHIFT) | | |
1423 | (pde << GEN8_PDE_SHIFT) | | |
1424 | (pte << GEN8_PTE_SHIFT); | |
1425 | int i; | |
1426 | bool found = false; | |
1427 | ||
1428 | for (i = 0; i < 4; i++) | |
1429 | if (pt_vaddr[pte + i] != scratch_pte) | |
1430 | found = true; | |
1431 | if (!found) | |
1432 | continue; | |
1433 | ||
1434 | seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte); | |
1435 | for (i = 0; i < 4; i++) { | |
1436 | if (pt_vaddr[pte + i] != scratch_pte) | |
1437 | seq_printf(m, " %llx", pt_vaddr[pte + i]); | |
1438 | else | |
1439 | seq_puts(m, " SCRATCH "); | |
1440 | } | |
1441 | seq_puts(m, "\n"); | |
1442 | } | |
1443 | /* don't use kunmap_px, it could trigger | |
1444 | * an unnecessary flush. | |
1445 | */ | |
1446 | kunmap_atomic(pt_vaddr); | |
1447 | } | |
1448 | } | |
1449 | } | |
1450 | ||
1451 | static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) | |
1452 | { | |
1453 | struct i915_address_space *vm = &ppgtt->base; | |
1454 | uint64_t start = ppgtt->base.start; | |
1455 | uint64_t length = ppgtt->base.total; | |
8bcdd0f7 | 1456 | gen8_pte_t scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
ea91e401 MT |
1457 | I915_CACHE_LLC, true); |
1458 | ||
1459 | if (!USES_FULL_48BIT_PPGTT(vm->dev)) { | |
1460 | gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m); | |
1461 | } else { | |
e8ebd8e2 | 1462 | uint64_t pml4e; |
ea91e401 MT |
1463 | struct i915_pml4 *pml4 = &ppgtt->pml4; |
1464 | struct i915_page_directory_pointer *pdp; | |
1465 | ||
e8ebd8e2 | 1466 | gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) { |
ea91e401 MT |
1467 | if (!test_bit(pml4e, pml4->used_pml4es)) |
1468 | continue; | |
1469 | ||
1470 | seq_printf(m, " PML4E #%llu\n", pml4e); | |
1471 | gen8_dump_pdp(pdp, start, length, scratch_pte, m); | |
1472 | } | |
1473 | } | |
1474 | } | |
1475 | ||
331f38e7 ZL |
1476 | static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt) |
1477 | { | |
3a41a05d | 1478 | unsigned long *new_page_dirs, *new_page_tables; |
331f38e7 ZL |
1479 | uint32_t pdpes = I915_PDPES_PER_PDP(dev); |
1480 | int ret; | |
1481 | ||
1482 | /* We allocate temp bitmap for page tables for no gain | |
1483 | * but as this is for init only, lets keep the things simple | |
1484 | */ | |
1485 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); | |
1486 | if (ret) | |
1487 | return ret; | |
1488 | ||
1489 | /* Allocate for all pdps regardless of how the ppgtt | |
1490 | * was defined. | |
1491 | */ | |
1492 | ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp, | |
1493 | 0, 1ULL << 32, | |
1494 | new_page_dirs); | |
1495 | if (!ret) | |
1496 | *ppgtt->pdp.used_pdpes = *new_page_dirs; | |
1497 | ||
3a41a05d | 1498 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
331f38e7 ZL |
1499 | |
1500 | return ret; | |
1501 | } | |
1502 | ||
eb0b44ad | 1503 | /* |
f3a964b9 BW |
1504 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1505 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1506 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1507 | * space. | |
37aca44a | 1508 | * |
f3a964b9 | 1509 | */ |
5c5f6457 | 1510 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 1511 | { |
8776f02b | 1512 | int ret; |
7cb6d7ac | 1513 | |
8776f02b MK |
1514 | ret = gen8_init_scratch(&ppgtt->base); |
1515 | if (ret) | |
1516 | return ret; | |
69876bed | 1517 | |
d7b2633d | 1518 | ppgtt->base.start = 0; |
d7b2633d | 1519 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 1520 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 1521 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 1522 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
1523 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1524 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
ea91e401 | 1525 | ppgtt->debug_dump = gen8_dump_ppgtt; |
d7b2633d | 1526 | |
762d9936 MT |
1527 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
1528 | ret = setup_px(ppgtt->base.dev, &ppgtt->pml4); | |
1529 | if (ret) | |
1530 | goto free_scratch; | |
6ac18502 | 1531 | |
69ab76fd MT |
1532 | gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4); |
1533 | ||
762d9936 | 1534 | ppgtt->base.total = 1ULL << 48; |
2dba3239 | 1535 | ppgtt->switch_mm = gen8_48b_mm_switch; |
762d9936 | 1536 | } else { |
25f50337 | 1537 | ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp); |
81ba8aef MT |
1538 | if (ret) |
1539 | goto free_scratch; | |
1540 | ||
1541 | ppgtt->base.total = 1ULL << 32; | |
2dba3239 | 1542 | ppgtt->switch_mm = gen8_legacy_mm_switch; |
762d9936 MT |
1543 | trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base, |
1544 | 0, 0, | |
1545 | GEN8_PML4E_SHIFT); | |
331f38e7 | 1546 | |
c033666a | 1547 | if (intel_vgpu_active(to_i915(ppgtt->base.dev))) { |
331f38e7 ZL |
1548 | ret = gen8_preallocate_top_level_pdps(ppgtt); |
1549 | if (ret) | |
1550 | goto free_scratch; | |
1551 | } | |
81ba8aef | 1552 | } |
6ac18502 | 1553 | |
c033666a | 1554 | if (intel_vgpu_active(to_i915(ppgtt->base.dev))) |
650da34c ZL |
1555 | gen8_ppgtt_notify_vgt(ppgtt, true); |
1556 | ||
d7b2633d | 1557 | return 0; |
6ac18502 MT |
1558 | |
1559 | free_scratch: | |
1560 | gen8_free_scratch(&ppgtt->base); | |
1561 | return ret; | |
d7b2633d MT |
1562 | } |
1563 | ||
87d60b63 BW |
1564 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
1565 | { | |
87d60b63 | 1566 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 1567 | struct i915_page_table *unused; |
07749ef3 | 1568 | gen6_pte_t scratch_pte; |
87d60b63 | 1569 | uint32_t pd_entry; |
731f74c5 | 1570 | uint32_t pte, pde; |
09942c65 | 1571 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; |
87d60b63 | 1572 | |
8bcdd0f7 | 1573 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
79ab9370 | 1574 | I915_CACHE_LLC, true, 0); |
87d60b63 | 1575 | |
731f74c5 | 1576 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) { |
87d60b63 | 1577 | u32 expected; |
07749ef3 | 1578 | gen6_pte_t *pt_vaddr; |
567047be | 1579 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 1580 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
1581 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
1582 | ||
1583 | if (pd_entry != expected) | |
1584 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1585 | pde, | |
1586 | pd_entry, | |
1587 | expected); | |
1588 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1589 | ||
d1c54acd MK |
1590 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
1591 | ||
07749ef3 | 1592 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1593 | unsigned long va = |
07749ef3 | 1594 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1595 | (pte * PAGE_SIZE); |
1596 | int i; | |
1597 | bool found = false; | |
1598 | for (i = 0; i < 4; i++) | |
1599 | if (pt_vaddr[pte + i] != scratch_pte) | |
1600 | found = true; | |
1601 | if (!found) | |
1602 | continue; | |
1603 | ||
1604 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1605 | for (i = 0; i < 4; i++) { | |
1606 | if (pt_vaddr[pte + i] != scratch_pte) | |
1607 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1608 | else | |
1609 | seq_puts(m, " SCRATCH "); | |
1610 | } | |
1611 | seq_puts(m, "\n"); | |
1612 | } | |
d1c54acd | 1613 | kunmap_px(ppgtt, pt_vaddr); |
87d60b63 BW |
1614 | } |
1615 | } | |
1616 | ||
678d96fb | 1617 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1618 | static void gen6_write_pde(struct i915_page_directory *pd, |
1619 | const int pde, struct i915_page_table *pt) | |
6197349b | 1620 | { |
678d96fb BW |
1621 | /* Caller needs to make sure the write completes if necessary */ |
1622 | struct i915_hw_ppgtt *ppgtt = | |
1623 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1624 | u32 pd_entry; | |
6197349b | 1625 | |
567047be | 1626 | pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); |
678d96fb | 1627 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1628 | |
678d96fb BW |
1629 | writel(pd_entry, ppgtt->pd_addr + pde); |
1630 | } | |
6197349b | 1631 | |
678d96fb BW |
1632 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1633 | * directories. */ | |
1634 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1635 | struct i915_page_directory *pd, |
678d96fb BW |
1636 | uint32_t start, uint32_t length) |
1637 | { | |
72e96d64 | 1638 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ec565b3c | 1639 | struct i915_page_table *pt; |
731f74c5 | 1640 | uint32_t pde; |
678d96fb | 1641 | |
731f74c5 | 1642 | gen6_for_each_pde(pt, pd, start, length, pde) |
678d96fb BW |
1643 | gen6_write_pde(pd, pde, pt); |
1644 | ||
1645 | /* Make sure write is complete before other code can use this page | |
1646 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1647 | readl(ggtt->gsm); |
3e302542 BW |
1648 | } |
1649 | ||
b4a74e3a | 1650 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1651 | { |
44159ddb | 1652 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1653 | |
44159ddb | 1654 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1655 | } |
1656 | ||
90252e5c | 1657 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1658 | struct drm_i915_gem_request *req) |
90252e5c | 1659 | { |
7e37f889 | 1660 | struct intel_ring *ring = req->ring; |
4a570db5 | 1661 | struct intel_engine_cs *engine = req->engine; |
90252e5c BW |
1662 | int ret; |
1663 | ||
90252e5c | 1664 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1665 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1666 | if (ret) |
1667 | return ret; | |
1668 | ||
5fb9de1a | 1669 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1670 | if (ret) |
1671 | return ret; | |
1672 | ||
b5321f30 CW |
1673 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1674 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1675 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1676 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1677 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1678 | intel_ring_emit(ring, MI_NOOP); | |
1679 | intel_ring_advance(ring); | |
90252e5c BW |
1680 | |
1681 | return 0; | |
1682 | } | |
1683 | ||
48a10389 | 1684 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1685 | struct drm_i915_gem_request *req) |
48a10389 | 1686 | { |
7e37f889 | 1687 | struct intel_ring *ring = req->ring; |
4a570db5 | 1688 | struct intel_engine_cs *engine = req->engine; |
48a10389 BW |
1689 | int ret; |
1690 | ||
48a10389 | 1691 | /* NB: TLBs must be flushed and invalidated before a switch */ |
7c9cf4e3 | 1692 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
48a10389 BW |
1693 | if (ret) |
1694 | return ret; | |
1695 | ||
5fb9de1a | 1696 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1697 | if (ret) |
1698 | return ret; | |
1699 | ||
b5321f30 CW |
1700 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
1701 | intel_ring_emit_reg(ring, RING_PP_DIR_DCLV(engine)); | |
1702 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1703 | intel_ring_emit_reg(ring, RING_PP_DIR_BASE(engine)); | |
1704 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1705 | intel_ring_emit(ring, MI_NOOP); | |
1706 | intel_ring_advance(ring); | |
48a10389 | 1707 | |
90252e5c | 1708 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
e2f80391 | 1709 | if (engine->id != RCS) { |
7c9cf4e3 | 1710 | ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH); |
90252e5c BW |
1711 | if (ret) |
1712 | return ret; | |
1713 | } | |
1714 | ||
48a10389 BW |
1715 | return 0; |
1716 | } | |
1717 | ||
eeb9488e | 1718 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1719 | struct drm_i915_gem_request *req) |
eeb9488e | 1720 | { |
4a570db5 | 1721 | struct intel_engine_cs *engine = req->engine; |
8eb95204 | 1722 | struct drm_i915_private *dev_priv = req->i915; |
48a10389 | 1723 | |
e2f80391 TU |
1724 | I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G); |
1725 | I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt)); | |
eeb9488e BW |
1726 | return 0; |
1727 | } | |
1728 | ||
82460d97 | 1729 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 1730 | { |
fac5e23e | 1731 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 1732 | struct intel_engine_cs *engine; |
3b3f1650 | 1733 | enum intel_engine_id id; |
3e302542 | 1734 | |
3b3f1650 | 1735 | for_each_engine(engine, dev_priv, id) { |
2dba3239 | 1736 | u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0; |
e2f80391 | 1737 | I915_WRITE(RING_MODE_GEN7(engine), |
2dba3239 | 1738 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level)); |
eeb9488e | 1739 | } |
eeb9488e | 1740 | } |
6197349b | 1741 | |
82460d97 | 1742 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 1743 | { |
fac5e23e | 1744 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 1745 | struct intel_engine_cs *engine; |
b4a74e3a | 1746 | uint32_t ecochk, ecobits; |
3b3f1650 | 1747 | enum intel_engine_id id; |
6197349b | 1748 | |
b4a74e3a BW |
1749 | ecobits = I915_READ(GAC_ECO_BITS); |
1750 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1751 | |
b4a74e3a | 1752 | ecochk = I915_READ(GAM_ECOCHK); |
772c2a51 | 1753 | if (IS_HASWELL(dev_priv)) { |
b4a74e3a BW |
1754 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
1755 | } else { | |
1756 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1757 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1758 | } | |
1759 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1760 | |
3b3f1650 | 1761 | for_each_engine(engine, dev_priv, id) { |
6197349b | 1762 | /* GFX_MODE is per-ring on gen7+ */ |
e2f80391 | 1763 | I915_WRITE(RING_MODE_GEN7(engine), |
b4a74e3a | 1764 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
6197349b | 1765 | } |
b4a74e3a | 1766 | } |
6197349b | 1767 | |
82460d97 | 1768 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 1769 | { |
fac5e23e | 1770 | struct drm_i915_private *dev_priv = to_i915(dev); |
b4a74e3a | 1771 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1772 | |
b4a74e3a BW |
1773 | ecobits = I915_READ(GAC_ECO_BITS); |
1774 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1775 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1776 | |
b4a74e3a BW |
1777 | gab_ctl = I915_READ(GAB_CTL); |
1778 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1779 | ||
1780 | ecochk = I915_READ(GAM_ECOCHK); | |
1781 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1782 | ||
1783 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1784 | } |
1785 | ||
1d2a314c | 1786 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1787 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1788 | uint64_t start, |
1789 | uint64_t length, | |
828c7908 | 1790 | bool use_scratch) |
1d2a314c | 1791 | { |
e5716f55 | 1792 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
07749ef3 | 1793 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1794 | unsigned first_entry = start >> PAGE_SHIFT; |
1795 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1796 | unsigned act_pt = first_entry / GEN6_PTES; |
1797 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1798 | unsigned last_pte, i; |
1d2a314c | 1799 | |
8bcdd0f7 | 1800 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
c114f76a | 1801 | I915_CACHE_LLC, true, 0); |
1d2a314c | 1802 | |
7bddb01f DV |
1803 | while (num_entries) { |
1804 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1805 | if (last_pte > GEN6_PTES) |
1806 | last_pte = GEN6_PTES; | |
7bddb01f | 1807 | |
d1c54acd | 1808 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
1d2a314c | 1809 | |
7bddb01f DV |
1810 | for (i = first_pte; i < last_pte; i++) |
1811 | pt_vaddr[i] = scratch_pte; | |
1d2a314c | 1812 | |
d1c54acd | 1813 | kunmap_px(ppgtt, pt_vaddr); |
1d2a314c | 1814 | |
7bddb01f DV |
1815 | num_entries -= last_pte - first_pte; |
1816 | first_pte = 0; | |
a15326a5 | 1817 | act_pt++; |
7bddb01f | 1818 | } |
1d2a314c DV |
1819 | } |
1820 | ||
853ba5d2 | 1821 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1822 | struct sg_table *pages, |
782f1495 | 1823 | uint64_t start, |
24f3a8cf | 1824 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1825 | { |
e5716f55 | 1826 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
782f1495 | 1827 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1828 | unsigned act_pt = first_entry / GEN6_PTES; |
1829 | unsigned act_pte = first_entry % GEN6_PTES; | |
85d1225e DG |
1830 | gen6_pte_t *pt_vaddr = NULL; |
1831 | struct sgt_iter sgt_iter; | |
1832 | dma_addr_t addr; | |
6e995e23 | 1833 | |
85d1225e | 1834 | for_each_sgt_dma(addr, sgt_iter, pages) { |
cc79714f | 1835 | if (pt_vaddr == NULL) |
d1c54acd | 1836 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
6e995e23 | 1837 | |
cc79714f | 1838 | pt_vaddr[act_pte] = |
85d1225e | 1839 | vm->pte_encode(addr, cache_level, true, flags); |
24f3a8cf | 1840 | |
07749ef3 | 1841 | if (++act_pte == GEN6_PTES) { |
d1c54acd | 1842 | kunmap_px(ppgtt, pt_vaddr); |
cc79714f | 1843 | pt_vaddr = NULL; |
a15326a5 | 1844 | act_pt++; |
6e995e23 | 1845 | act_pte = 0; |
def886c3 | 1846 | } |
def886c3 | 1847 | } |
85d1225e | 1848 | |
cc79714f | 1849 | if (pt_vaddr) |
d1c54acd | 1850 | kunmap_px(ppgtt, pt_vaddr); |
def886c3 DV |
1851 | } |
1852 | ||
678d96fb | 1853 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1854 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1855 | { |
4933d519 MT |
1856 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
1857 | struct drm_device *dev = vm->dev; | |
72e96d64 JL |
1858 | struct drm_i915_private *dev_priv = to_i915(dev); |
1859 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
e5716f55 | 1860 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
ec565b3c | 1861 | struct i915_page_table *pt; |
a05d80ee | 1862 | uint32_t start, length, start_save, length_save; |
731f74c5 | 1863 | uint32_t pde; |
4933d519 MT |
1864 | int ret; |
1865 | ||
a05d80ee MK |
1866 | if (WARN_ON(start_in + length_in > ppgtt->base.total)) |
1867 | return -ENODEV; | |
1868 | ||
1869 | start = start_save = start_in; | |
1870 | length = length_save = length_in; | |
4933d519 MT |
1871 | |
1872 | bitmap_zero(new_page_tables, I915_PDES); | |
1873 | ||
1874 | /* The allocation is done in two stages so that we can bail out with | |
1875 | * minimal amount of pain. The first stage finds new page tables that | |
1876 | * need allocation. The second stage marks use ptes within the page | |
1877 | * tables. | |
1878 | */ | |
731f74c5 | 1879 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
79ab9370 | 1880 | if (pt != vm->scratch_pt) { |
4933d519 MT |
1881 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); |
1882 | continue; | |
1883 | } | |
1884 | ||
1885 | /* We've already allocated a page table */ | |
1886 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1887 | ||
8a1ebd74 | 1888 | pt = alloc_pt(dev); |
4933d519 MT |
1889 | if (IS_ERR(pt)) { |
1890 | ret = PTR_ERR(pt); | |
1891 | goto unwind_out; | |
1892 | } | |
1893 | ||
1894 | gen6_initialize_pt(vm, pt); | |
1895 | ||
1896 | ppgtt->pd.page_table[pde] = pt; | |
966082c9 | 1897 | __set_bit(pde, new_page_tables); |
72744cb1 | 1898 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1899 | } |
1900 | ||
1901 | start = start_save; | |
1902 | length = length_save; | |
678d96fb | 1903 | |
731f74c5 | 1904 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) { |
678d96fb BW |
1905 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); |
1906 | ||
1907 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1908 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1909 | gen6_pte_count(start, length)); | |
1910 | ||
966082c9 | 1911 | if (__test_and_clear_bit(pde, new_page_tables)) |
4933d519 MT |
1912 | gen6_write_pde(&ppgtt->pd, pde, pt); |
1913 | ||
72744cb1 MT |
1914 | trace_i915_page_table_entry_map(vm, pde, pt, |
1915 | gen6_pte_index(start), | |
1916 | gen6_pte_count(start, length), | |
1917 | GEN6_PTES); | |
4933d519 | 1918 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1919 | GEN6_PTES); |
1920 | } | |
1921 | ||
4933d519 MT |
1922 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1923 | ||
1924 | /* Make sure write is complete before other code can use this page | |
1925 | * table. Also require for WC mapped PTEs */ | |
72e96d64 | 1926 | readl(ggtt->gsm); |
4933d519 | 1927 | |
563222a7 | 1928 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1929 | return 0; |
4933d519 MT |
1930 | |
1931 | unwind_out: | |
1932 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1933 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 | 1934 | |
79ab9370 | 1935 | ppgtt->pd.page_table[pde] = vm->scratch_pt; |
a08e111a | 1936 | free_pt(vm->dev, pt); |
4933d519 MT |
1937 | } |
1938 | ||
1939 | mark_tlbs_dirty(ppgtt); | |
1940 | return ret; | |
678d96fb BW |
1941 | } |
1942 | ||
8776f02b MK |
1943 | static int gen6_init_scratch(struct i915_address_space *vm) |
1944 | { | |
1945 | struct drm_device *dev = vm->dev; | |
8bcdd0f7 | 1946 | int ret; |
8776f02b | 1947 | |
bb8f9cff | 1948 | ret = setup_scratch_page(dev, &vm->scratch_page, I915_GFP_DMA); |
8bcdd0f7 CW |
1949 | if (ret) |
1950 | return ret; | |
8776f02b MK |
1951 | |
1952 | vm->scratch_pt = alloc_pt(dev); | |
1953 | if (IS_ERR(vm->scratch_pt)) { | |
8bcdd0f7 | 1954 | cleanup_scratch_page(dev, &vm->scratch_page); |
8776f02b MK |
1955 | return PTR_ERR(vm->scratch_pt); |
1956 | } | |
1957 | ||
1958 | gen6_initialize_pt(vm, vm->scratch_pt); | |
1959 | ||
1960 | return 0; | |
1961 | } | |
1962 | ||
1963 | static void gen6_free_scratch(struct i915_address_space *vm) | |
1964 | { | |
1965 | struct drm_device *dev = vm->dev; | |
1966 | ||
1967 | free_pt(dev, vm->scratch_pt); | |
8bcdd0f7 | 1968 | cleanup_scratch_page(dev, &vm->scratch_page); |
8776f02b MK |
1969 | } |
1970 | ||
061dd493 | 1971 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 1972 | { |
e5716f55 | 1973 | struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm); |
731f74c5 DG |
1974 | struct i915_page_directory *pd = &ppgtt->pd; |
1975 | struct drm_device *dev = vm->dev; | |
09942c65 MT |
1976 | struct i915_page_table *pt; |
1977 | uint32_t pde; | |
4933d519 | 1978 | |
061dd493 DV |
1979 | drm_mm_remove_node(&ppgtt->node); |
1980 | ||
731f74c5 | 1981 | gen6_for_all_pdes(pt, pd, pde) |
79ab9370 | 1982 | if (pt != vm->scratch_pt) |
731f74c5 | 1983 | free_pt(dev, pt); |
06fda602 | 1984 | |
8776f02b | 1985 | gen6_free_scratch(vm); |
3440d265 DV |
1986 | } |
1987 | ||
b146520f | 1988 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1989 | { |
8776f02b | 1990 | struct i915_address_space *vm = &ppgtt->base; |
853ba5d2 | 1991 | struct drm_device *dev = ppgtt->base.dev; |
72e96d64 JL |
1992 | struct drm_i915_private *dev_priv = to_i915(dev); |
1993 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
e3cc1995 | 1994 | bool retried = false; |
b146520f | 1995 | int ret; |
1d2a314c | 1996 | |
c8d4c0d6 BW |
1997 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1998 | * allocator works in address space sizes, so it's multiplied by page | |
1999 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
2000 | */ | |
72e96d64 | 2001 | BUG_ON(!drm_mm_initialized(&ggtt->base.mm)); |
4933d519 | 2002 | |
8776f02b MK |
2003 | ret = gen6_init_scratch(vm); |
2004 | if (ret) | |
2005 | return ret; | |
4933d519 | 2006 | |
e3cc1995 | 2007 | alloc: |
72e96d64 | 2008 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, |
c8d4c0d6 BW |
2009 | &ppgtt->node, GEN6_PD_SIZE, |
2010 | GEN6_PD_ALIGN, 0, | |
72e96d64 | 2011 | 0, ggtt->base.total, |
3e8b5ae9 | 2012 | DRM_MM_TOPDOWN); |
e3cc1995 | 2013 | if (ret == -ENOSPC && !retried) { |
e522ac23 | 2014 | ret = i915_gem_evict_something(&ggtt->base, |
e3cc1995 | 2015 | GEN6_PD_SIZE, GEN6_PD_ALIGN, |
d23db88c | 2016 | I915_CACHE_NONE, |
72e96d64 | 2017 | 0, ggtt->base.total, |
d23db88c | 2018 | 0); |
e3cc1995 | 2019 | if (ret) |
678d96fb | 2020 | goto err_out; |
e3cc1995 BW |
2021 | |
2022 | retried = true; | |
2023 | goto alloc; | |
2024 | } | |
c8d4c0d6 | 2025 | |
c8c26622 | 2026 | if (ret) |
678d96fb BW |
2027 | goto err_out; |
2028 | ||
c8c26622 | 2029 | |
72e96d64 | 2030 | if (ppgtt->node.start < ggtt->mappable_end) |
c8d4c0d6 | 2031 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
1d2a314c | 2032 | |
c8c26622 | 2033 | return 0; |
678d96fb BW |
2034 | |
2035 | err_out: | |
8776f02b | 2036 | gen6_free_scratch(vm); |
678d96fb | 2037 | return ret; |
b146520f BW |
2038 | } |
2039 | ||
b146520f BW |
2040 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
2041 | { | |
2f2cf682 | 2042 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 2043 | } |
06dc68d6 | 2044 | |
4933d519 MT |
2045 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
2046 | uint64_t start, uint64_t length) | |
2047 | { | |
ec565b3c | 2048 | struct i915_page_table *unused; |
731f74c5 | 2049 | uint32_t pde; |
1d2a314c | 2050 | |
731f74c5 | 2051 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) |
79ab9370 | 2052 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
2053 | } |
2054 | ||
5c5f6457 | 2055 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f BW |
2056 | { |
2057 | struct drm_device *dev = ppgtt->base.dev; | |
72e96d64 JL |
2058 | struct drm_i915_private *dev_priv = to_i915(dev); |
2059 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b146520f BW |
2060 | int ret; |
2061 | ||
72e96d64 | 2062 | ppgtt->base.pte_encode = ggtt->base.pte_encode; |
8eb95204 | 2063 | if (intel_vgpu_active(dev_priv) || IS_GEN6(dev)) |
b146520f | 2064 | ppgtt->switch_mm = gen6_mm_switch; |
772c2a51 | 2065 | else if (IS_HASWELL(dev_priv)) |
b146520f | 2066 | ppgtt->switch_mm = hsw_mm_switch; |
8eb95204 | 2067 | else if (IS_GEN7(dev)) |
b146520f | 2068 | ppgtt->switch_mm = gen7_mm_switch; |
8eb95204 | 2069 | else |
b146520f BW |
2070 | BUG(); |
2071 | ||
2072 | ret = gen6_ppgtt_alloc(ppgtt); | |
2073 | if (ret) | |
2074 | return ret; | |
2075 | ||
5c5f6457 | 2076 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
2077 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
2078 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
2079 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
2080 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 2081 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 2082 | ppgtt->base.start = 0; |
09942c65 | 2083 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 2084 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 2085 | |
44159ddb | 2086 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 2087 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 2088 | |
72e96d64 | 2089 | ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm + |
44159ddb | 2090 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 2091 | |
5c5f6457 | 2092 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 2093 | |
678d96fb BW |
2094 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
2095 | ||
440fd528 | 2096 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
2097 | ppgtt->node.size >> 20, |
2098 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 2099 | |
fa76da34 | 2100 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 2101 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 2102 | |
b146520f | 2103 | return 0; |
3440d265 DV |
2104 | } |
2105 | ||
2bfa996e CW |
2106 | static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2107 | struct drm_i915_private *dev_priv) | |
3440d265 | 2108 | { |
2bfa996e | 2109 | ppgtt->base.dev = &dev_priv->drm; |
3440d265 | 2110 | |
2bfa996e | 2111 | if (INTEL_INFO(dev_priv)->gen < 8) |
5c5f6457 | 2112 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 2113 | else |
d7b2633d | 2114 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 2115 | } |
c114f76a | 2116 | |
a2cad9df MW |
2117 | static void i915_address_space_init(struct i915_address_space *vm, |
2118 | struct drm_i915_private *dev_priv) | |
2119 | { | |
2120 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
a2cad9df MW |
2121 | INIT_LIST_HEAD(&vm->active_list); |
2122 | INIT_LIST_HEAD(&vm->inactive_list); | |
50e046b6 | 2123 | INIT_LIST_HEAD(&vm->unbound_list); |
a2cad9df MW |
2124 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
2125 | } | |
2126 | ||
d5165ebd TG |
2127 | static void gtt_write_workarounds(struct drm_device *dev) |
2128 | { | |
fac5e23e | 2129 | struct drm_i915_private *dev_priv = to_i915(dev); |
d5165ebd TG |
2130 | |
2131 | /* This function is for gtt related workarounds. This function is | |
2132 | * called on driver load and after a GPU reset, so you can place | |
2133 | * workarounds here even if they get overwritten by GPU reset. | |
2134 | */ | |
2135 | /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */ | |
8652744b | 2136 | if (IS_BROADWELL(dev_priv)) |
d5165ebd | 2137 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); |
920a14b2 | 2138 | else if (IS_CHERRYVIEW(dev_priv)) |
d5165ebd | 2139 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); |
d9486e65 | 2140 | else if (IS_SKYLAKE(dev_priv)) |
d5165ebd | 2141 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); |
e2d214ae | 2142 | else if (IS_BROXTON(dev_priv)) |
d5165ebd TG |
2143 | I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); |
2144 | } | |
2145 | ||
2bfa996e CW |
2146 | static int i915_ppgtt_init(struct i915_hw_ppgtt *ppgtt, |
2147 | struct drm_i915_private *dev_priv, | |
2148 | struct drm_i915_file_private *file_priv) | |
fa76da34 | 2149 | { |
2bfa996e | 2150 | int ret; |
3ed124b2 | 2151 | |
2bfa996e | 2152 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
fa76da34 | 2153 | if (ret == 0) { |
c7c48dfd | 2154 | kref_init(&ppgtt->ref); |
a2cad9df | 2155 | i915_address_space_init(&ppgtt->base, dev_priv); |
2bfa996e | 2156 | ppgtt->base.file = file_priv; |
93bd8649 | 2157 | } |
1d2a314c DV |
2158 | |
2159 | return ret; | |
2160 | } | |
2161 | ||
82460d97 DV |
2162 | int i915_ppgtt_init_hw(struct drm_device *dev) |
2163 | { | |
d5165ebd TG |
2164 | gtt_write_workarounds(dev); |
2165 | ||
671b5013 TD |
2166 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
2167 | * and the PDPs are contained within the context itself. We don't | |
2168 | * need to do anything here. */ | |
2169 | if (i915.enable_execlists) | |
2170 | return 0; | |
2171 | ||
82460d97 DV |
2172 | if (!USES_PPGTT(dev)) |
2173 | return 0; | |
2174 | ||
2175 | if (IS_GEN6(dev)) | |
2176 | gen6_ppgtt_enable(dev); | |
2177 | else if (IS_GEN7(dev)) | |
2178 | gen7_ppgtt_enable(dev); | |
2179 | else if (INTEL_INFO(dev)->gen >= 8) | |
2180 | gen8_ppgtt_enable(dev); | |
2181 | else | |
5f77eeb0 | 2182 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 | 2183 | |
4ad2fd88 JH |
2184 | return 0; |
2185 | } | |
1d2a314c | 2186 | |
4d884705 | 2187 | struct i915_hw_ppgtt * |
2bfa996e CW |
2188 | i915_ppgtt_create(struct drm_i915_private *dev_priv, |
2189 | struct drm_i915_file_private *fpriv) | |
4d884705 DV |
2190 | { |
2191 | struct i915_hw_ppgtt *ppgtt; | |
2192 | int ret; | |
2193 | ||
2194 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2195 | if (!ppgtt) | |
2196 | return ERR_PTR(-ENOMEM); | |
2197 | ||
2bfa996e | 2198 | ret = i915_ppgtt_init(ppgtt, dev_priv, fpriv); |
4d884705 DV |
2199 | if (ret) { |
2200 | kfree(ppgtt); | |
2201 | return ERR_PTR(ret); | |
2202 | } | |
2203 | ||
198c974d DCS |
2204 | trace_i915_ppgtt_create(&ppgtt->base); |
2205 | ||
4d884705 DV |
2206 | return ppgtt; |
2207 | } | |
2208 | ||
ee960be7 DV |
2209 | void i915_ppgtt_release(struct kref *kref) |
2210 | { | |
2211 | struct i915_hw_ppgtt *ppgtt = | |
2212 | container_of(kref, struct i915_hw_ppgtt, ref); | |
2213 | ||
198c974d DCS |
2214 | trace_i915_ppgtt_release(&ppgtt->base); |
2215 | ||
50e046b6 | 2216 | /* vmas should already be unbound and destroyed */ |
ee960be7 DV |
2217 | WARN_ON(!list_empty(&ppgtt->base.active_list)); |
2218 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
50e046b6 | 2219 | WARN_ON(!list_empty(&ppgtt->base.unbound_list)); |
ee960be7 | 2220 | |
19dd120c DV |
2221 | list_del(&ppgtt->base.global_link); |
2222 | drm_mm_takedown(&ppgtt->base.mm); | |
2223 | ||
ee960be7 DV |
2224 | ppgtt->base.cleanup(&ppgtt->base); |
2225 | kfree(ppgtt); | |
2226 | } | |
1d2a314c | 2227 | |
a81cc00c BW |
2228 | /* Certain Gen5 chipsets require require idling the GPU before |
2229 | * unmapping anything from the GTT when VT-d is enabled. | |
2230 | */ | |
97d6d7ab | 2231 | static bool needs_idle_maps(struct drm_i915_private *dev_priv) |
a81cc00c BW |
2232 | { |
2233 | #ifdef CONFIG_INTEL_IOMMU | |
2234 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
2235 | * was loaded first. | |
2236 | */ | |
97d6d7ab | 2237 | if (IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_iommu_gfx_mapped) |
a81cc00c BW |
2238 | return true; |
2239 | #endif | |
2240 | return false; | |
2241 | } | |
2242 | ||
dc97997a | 2243 | void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) |
828c7908 | 2244 | { |
e2f80391 | 2245 | struct intel_engine_cs *engine; |
3b3f1650 | 2246 | enum intel_engine_id id; |
828c7908 | 2247 | |
dc97997a | 2248 | if (INTEL_INFO(dev_priv)->gen < 6) |
828c7908 BW |
2249 | return; |
2250 | ||
3b3f1650 | 2251 | for_each_engine(engine, dev_priv, id) { |
828c7908 | 2252 | u32 fault_reg; |
e2f80391 | 2253 | fault_reg = I915_READ(RING_FAULT_REG(engine)); |
828c7908 BW |
2254 | if (fault_reg & RING_FAULT_VALID) { |
2255 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 2256 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
2257 | "\tAddress space: %s\n" |
2258 | "\tSource ID: %d\n" | |
2259 | "\tType: %d\n", | |
2260 | fault_reg & PAGE_MASK, | |
2261 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
2262 | RING_FAULT_SRCID(fault_reg), | |
2263 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
e2f80391 | 2264 | I915_WRITE(RING_FAULT_REG(engine), |
828c7908 BW |
2265 | fault_reg & ~RING_FAULT_VALID); |
2266 | } | |
2267 | } | |
3b3f1650 AG |
2268 | |
2269 | /* Engine specific init may not have been done till this point. */ | |
2270 | if (dev_priv->engine[RCS]) | |
2271 | POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS])); | |
828c7908 BW |
2272 | } |
2273 | ||
91e56499 CW |
2274 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
2275 | { | |
2d1fe073 | 2276 | if (INTEL_INFO(dev_priv)->gen < 6) { |
91e56499 CW |
2277 | intel_gtt_chipset_flush(); |
2278 | } else { | |
2279 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2280 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2281 | } | |
2282 | } | |
2283 | ||
828c7908 BW |
2284 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
2285 | { | |
72e96d64 JL |
2286 | struct drm_i915_private *dev_priv = to_i915(dev); |
2287 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
828c7908 BW |
2288 | |
2289 | /* Don't bother messing with faults pre GEN6 as we have little | |
2290 | * documentation supporting that it's a good idea. | |
2291 | */ | |
2292 | if (INTEL_INFO(dev)->gen < 6) | |
2293 | return; | |
2294 | ||
dc97997a | 2295 | i915_check_and_clear_faults(dev_priv); |
828c7908 | 2296 | |
72e96d64 JL |
2297 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total, |
2298 | true); | |
91e56499 CW |
2299 | |
2300 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
2301 | } |
2302 | ||
74163907 | 2303 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 2304 | { |
9da3da66 CW |
2305 | if (!dma_map_sg(&obj->base.dev->pdev->dev, |
2306 | obj->pages->sgl, obj->pages->nents, | |
2307 | PCI_DMA_BIDIRECTIONAL)) | |
2308 | return -ENOSPC; | |
2309 | ||
2310 | return 0; | |
7c2e6fdf DV |
2311 | } |
2312 | ||
2c642b07 | 2313 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 | 2314 | { |
94ec8f61 | 2315 | writeq(pte, addr); |
94ec8f61 BW |
2316 | } |
2317 | ||
d6473f56 CW |
2318 | static void gen8_ggtt_insert_page(struct i915_address_space *vm, |
2319 | dma_addr_t addr, | |
2320 | uint64_t offset, | |
2321 | enum i915_cache_level level, | |
2322 | u32 unused) | |
2323 | { | |
2324 | struct drm_i915_private *dev_priv = to_i915(vm->dev); | |
2325 | gen8_pte_t __iomem *pte = | |
2326 | (gen8_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2327 | (offset >> PAGE_SHIFT); | |
2328 | int rpm_atomic_seq; | |
2329 | ||
2330 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
2331 | ||
2332 | gen8_set_pte(pte, gen8_pte_encode(addr, level, true)); | |
2333 | ||
2334 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2335 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2336 | ||
2337 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
2338 | } | |
2339 | ||
94ec8f61 BW |
2340 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
2341 | struct sg_table *st, | |
782f1495 | 2342 | uint64_t start, |
24f3a8cf | 2343 | enum i915_cache_level level, u32 unused) |
94ec8f61 | 2344 | { |
72e96d64 | 2345 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
ce7fda2e | 2346 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2347 | struct sgt_iter sgt_iter; |
2348 | gen8_pte_t __iomem *gtt_entries; | |
2349 | gen8_pte_t gtt_entry; | |
2350 | dma_addr_t addr; | |
be69459a | 2351 | int rpm_atomic_seq; |
85d1225e | 2352 | int i = 0; |
be69459a ID |
2353 | |
2354 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
94ec8f61 | 2355 | |
85d1225e DG |
2356 | gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2357 | ||
2358 | for_each_sgt_dma(addr, sgt_iter, st) { | |
2359 | gtt_entry = gen8_pte_encode(addr, level, true); | |
2360 | gen8_set_pte(>t_entries[i++], gtt_entry); | |
94ec8f61 BW |
2361 | } |
2362 | ||
2363 | /* | |
2364 | * XXX: This serves as a posting read to make sure that the PTE has | |
2365 | * actually been updated. There is some concern that even though | |
2366 | * registers and PTEs are within the same BAR that they are potentially | |
2367 | * of NUMA access patterns. Therefore, even with the way we assume | |
2368 | * hardware should work, we must keep this posting read for paranoia. | |
2369 | */ | |
2370 | if (i != 0) | |
85d1225e | 2371 | WARN_ON(readq(>t_entries[i-1]) != gtt_entry); |
94ec8f61 | 2372 | |
94ec8f61 BW |
2373 | /* This next bit makes the above posting read even more important. We |
2374 | * want to flush the TLBs only after we're certain all the PTE updates | |
2375 | * have finished. | |
2376 | */ | |
2377 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2378 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
be69459a ID |
2379 | |
2380 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
94ec8f61 BW |
2381 | } |
2382 | ||
c140330b CW |
2383 | struct insert_entries { |
2384 | struct i915_address_space *vm; | |
2385 | struct sg_table *st; | |
2386 | uint64_t start; | |
2387 | enum i915_cache_level level; | |
2388 | u32 flags; | |
2389 | }; | |
2390 | ||
2391 | static int gen8_ggtt_insert_entries__cb(void *_arg) | |
2392 | { | |
2393 | struct insert_entries *arg = _arg; | |
2394 | gen8_ggtt_insert_entries(arg->vm, arg->st, | |
2395 | arg->start, arg->level, arg->flags); | |
2396 | return 0; | |
2397 | } | |
2398 | ||
2399 | static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm, | |
2400 | struct sg_table *st, | |
2401 | uint64_t start, | |
2402 | enum i915_cache_level level, | |
2403 | u32 flags) | |
2404 | { | |
2405 | struct insert_entries arg = { vm, st, start, level, flags }; | |
2406 | stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL); | |
2407 | } | |
2408 | ||
d6473f56 CW |
2409 | static void gen6_ggtt_insert_page(struct i915_address_space *vm, |
2410 | dma_addr_t addr, | |
2411 | uint64_t offset, | |
2412 | enum i915_cache_level level, | |
2413 | u32 flags) | |
2414 | { | |
2415 | struct drm_i915_private *dev_priv = to_i915(vm->dev); | |
2416 | gen6_pte_t __iomem *pte = | |
2417 | (gen6_pte_t __iomem *)dev_priv->ggtt.gsm + | |
2418 | (offset >> PAGE_SHIFT); | |
2419 | int rpm_atomic_seq; | |
2420 | ||
2421 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
2422 | ||
2423 | iowrite32(vm->pte_encode(addr, level, true, flags), pte); | |
2424 | ||
2425 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2426 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2427 | ||
2428 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
2429 | } | |
2430 | ||
e76e9aeb BW |
2431 | /* |
2432 | * Binds an object into the global gtt with the specified cache level. The object | |
2433 | * will be accessible to the GPU via commands whose operands reference offsets | |
2434 | * within the global GTT as well as accessible by the GPU through the GMADR | |
2435 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
2436 | */ | |
853ba5d2 | 2437 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 2438 | struct sg_table *st, |
782f1495 | 2439 | uint64_t start, |
24f3a8cf | 2440 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 2441 | { |
72e96d64 | 2442 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
ce7fda2e | 2443 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
85d1225e DG |
2444 | struct sgt_iter sgt_iter; |
2445 | gen6_pte_t __iomem *gtt_entries; | |
2446 | gen6_pte_t gtt_entry; | |
2447 | dma_addr_t addr; | |
be69459a | 2448 | int rpm_atomic_seq; |
85d1225e | 2449 | int i = 0; |
be69459a ID |
2450 | |
2451 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
e76e9aeb | 2452 | |
85d1225e DG |
2453 | gtt_entries = (gen6_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT); |
2454 | ||
2455 | for_each_sgt_dma(addr, sgt_iter, st) { | |
2456 | gtt_entry = vm->pte_encode(addr, level, true, flags); | |
2457 | iowrite32(gtt_entry, >t_entries[i++]); | |
e76e9aeb BW |
2458 | } |
2459 | ||
e76e9aeb BW |
2460 | /* XXX: This serves as a posting read to make sure that the PTE has |
2461 | * actually been updated. There is some concern that even though | |
2462 | * registers and PTEs are within the same BAR that they are potentially | |
2463 | * of NUMA access patterns. Therefore, even with the way we assume | |
2464 | * hardware should work, we must keep this posting read for paranoia. | |
2465 | */ | |
85d1225e DG |
2466 | if (i != 0) |
2467 | WARN_ON(readl(>t_entries[i-1]) != gtt_entry); | |
0f9b91c7 BW |
2468 | |
2469 | /* This next bit makes the above posting read even more important. We | |
2470 | * want to flush the TLBs only after we're certain all the PTE updates | |
2471 | * have finished. | |
2472 | */ | |
2473 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2474 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
be69459a ID |
2475 | |
2476 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
e76e9aeb BW |
2477 | } |
2478 | ||
f7770bfd CW |
2479 | static void nop_clear_range(struct i915_address_space *vm, |
2480 | uint64_t start, | |
2481 | uint64_t length, | |
2482 | bool use_scratch) | |
2483 | { | |
2484 | } | |
2485 | ||
94ec8f61 | 2486 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
2487 | uint64_t start, |
2488 | uint64_t length, | |
94ec8f61 BW |
2489 | bool use_scratch) |
2490 | { | |
72e96d64 | 2491 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
ce7fda2e | 2492 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2493 | unsigned first_entry = start >> PAGE_SHIFT; |
2494 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2495 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2496 | (gen8_pte_t __iomem *)ggtt->gsm + first_entry; |
2497 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
94ec8f61 | 2498 | int i; |
be69459a ID |
2499 | int rpm_atomic_seq; |
2500 | ||
2501 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
94ec8f61 BW |
2502 | |
2503 | if (WARN(num_entries > max_entries, | |
2504 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2505 | first_entry, num_entries, max_entries)) | |
2506 | num_entries = max_entries; | |
2507 | ||
8bcdd0f7 | 2508 | scratch_pte = gen8_pte_encode(vm->scratch_page.daddr, |
94ec8f61 BW |
2509 | I915_CACHE_LLC, |
2510 | use_scratch); | |
2511 | for (i = 0; i < num_entries; i++) | |
2512 | gen8_set_pte(>t_base[i], scratch_pte); | |
2513 | readl(gtt_base); | |
be69459a ID |
2514 | |
2515 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
94ec8f61 BW |
2516 | } |
2517 | ||
853ba5d2 | 2518 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
2519 | uint64_t start, |
2520 | uint64_t length, | |
828c7908 | 2521 | bool use_scratch) |
7faf1ab2 | 2522 | { |
72e96d64 | 2523 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
ce7fda2e | 2524 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); |
782f1495 BW |
2525 | unsigned first_entry = start >> PAGE_SHIFT; |
2526 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 | 2527 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
72e96d64 JL |
2528 | (gen6_pte_t __iomem *)ggtt->gsm + first_entry; |
2529 | const int max_entries = ggtt_total_entries(ggtt) - first_entry; | |
7faf1ab2 | 2530 | int i; |
be69459a ID |
2531 | int rpm_atomic_seq; |
2532 | ||
2533 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
7faf1ab2 DV |
2534 | |
2535 | if (WARN(num_entries > max_entries, | |
2536 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2537 | first_entry, num_entries, max_entries)) | |
2538 | num_entries = max_entries; | |
2539 | ||
8bcdd0f7 | 2540 | scratch_pte = vm->pte_encode(vm->scratch_page.daddr, |
c114f76a | 2541 | I915_CACHE_LLC, use_scratch, 0); |
828c7908 | 2542 | |
7faf1ab2 DV |
2543 | for (i = 0; i < num_entries; i++) |
2544 | iowrite32(scratch_pte, >t_base[i]); | |
2545 | readl(gtt_base); | |
be69459a ID |
2546 | |
2547 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
7faf1ab2 DV |
2548 | } |
2549 | ||
d6473f56 CW |
2550 | static void i915_ggtt_insert_page(struct i915_address_space *vm, |
2551 | dma_addr_t addr, | |
2552 | uint64_t offset, | |
2553 | enum i915_cache_level cache_level, | |
2554 | u32 unused) | |
2555 | { | |
2556 | struct drm_i915_private *dev_priv = to_i915(vm->dev); | |
2557 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
2558 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
2559 | int rpm_atomic_seq; | |
2560 | ||
2561 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
2562 | ||
2563 | intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags); | |
2564 | ||
2565 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
2566 | } | |
2567 | ||
d369d2d9 DV |
2568 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
2569 | struct sg_table *pages, | |
2570 | uint64_t start, | |
2571 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 | 2572 | { |
fac5e23e | 2573 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
7faf1ab2 DV |
2574 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
2575 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
be69459a ID |
2576 | int rpm_atomic_seq; |
2577 | ||
2578 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
7faf1ab2 | 2579 | |
d369d2d9 | 2580 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 2581 | |
be69459a ID |
2582 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); |
2583 | ||
7faf1ab2 DV |
2584 | } |
2585 | ||
853ba5d2 | 2586 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
2587 | uint64_t start, |
2588 | uint64_t length, | |
828c7908 | 2589 | bool unused) |
7faf1ab2 | 2590 | { |
fac5e23e | 2591 | struct drm_i915_private *dev_priv = to_i915(vm->dev); |
782f1495 BW |
2592 | unsigned first_entry = start >> PAGE_SHIFT; |
2593 | unsigned num_entries = length >> PAGE_SHIFT; | |
be69459a ID |
2594 | int rpm_atomic_seq; |
2595 | ||
2596 | rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv); | |
2597 | ||
7faf1ab2 | 2598 | intel_gtt_clear_range(first_entry, num_entries); |
be69459a ID |
2599 | |
2600 | assert_rpm_atomic_end(dev_priv, rpm_atomic_seq); | |
7faf1ab2 DV |
2601 | } |
2602 | ||
70b9f6f8 DV |
2603 | static int ggtt_bind_vma(struct i915_vma *vma, |
2604 | enum i915_cache_level cache_level, | |
2605 | u32 flags) | |
0a878716 DV |
2606 | { |
2607 | struct drm_i915_gem_object *obj = vma->obj; | |
2608 | u32 pte_flags = 0; | |
2609 | int ret; | |
2610 | ||
2611 | ret = i915_get_ggtt_vma_pages(vma); | |
2612 | if (ret) | |
2613 | return ret; | |
2614 | ||
2615 | /* Currently applicable only to VLV */ | |
2616 | if (obj->gt_ro) | |
2617 | pte_flags |= PTE_READ_ONLY; | |
2618 | ||
247177dd | 2619 | vma->vm->insert_entries(vma->vm, vma->pages, vma->node.start, |
0a878716 DV |
2620 | cache_level, pte_flags); |
2621 | ||
2622 | /* | |
2623 | * Without aliasing PPGTT there's no difference between | |
2624 | * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally | |
2625 | * upgrade to both bound if we bind either to avoid double-binding. | |
2626 | */ | |
3272db53 | 2627 | vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND; |
0a878716 DV |
2628 | |
2629 | return 0; | |
2630 | } | |
2631 | ||
2632 | static int aliasing_gtt_bind_vma(struct i915_vma *vma, | |
2633 | enum i915_cache_level cache_level, | |
2634 | u32 flags) | |
d5bd1449 | 2635 | { |
321d178e | 2636 | u32 pte_flags; |
70b9f6f8 DV |
2637 | int ret; |
2638 | ||
2639 | ret = i915_get_ggtt_vma_pages(vma); | |
2640 | if (ret) | |
2641 | return ret; | |
7faf1ab2 | 2642 | |
24f3a8cf | 2643 | /* Currently applicable only to VLV */ |
321d178e CW |
2644 | pte_flags = 0; |
2645 | if (vma->obj->gt_ro) | |
f329f5f6 | 2646 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2647 | |
ec7adb6e | 2648 | |
3272db53 | 2649 | if (flags & I915_VMA_GLOBAL_BIND) { |
321d178e | 2650 | vma->vm->insert_entries(vma->vm, |
247177dd | 2651 | vma->pages, vma->node.start, |
0875546c | 2652 | cache_level, pte_flags); |
6f65e29a | 2653 | } |
d5bd1449 | 2654 | |
3272db53 | 2655 | if (flags & I915_VMA_LOCAL_BIND) { |
321d178e CW |
2656 | struct i915_hw_ppgtt *appgtt = |
2657 | to_i915(vma->vm->dev)->mm.aliasing_ppgtt; | |
2658 | appgtt->base.insert_entries(&appgtt->base, | |
247177dd | 2659 | vma->pages, vma->node.start, |
f329f5f6 | 2660 | cache_level, pte_flags); |
6f65e29a | 2661 | } |
70b9f6f8 DV |
2662 | |
2663 | return 0; | |
d5bd1449 CW |
2664 | } |
2665 | ||
6f65e29a | 2666 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2667 | { |
de180033 CW |
2668 | struct i915_hw_ppgtt *appgtt = to_i915(vma->vm->dev)->mm.aliasing_ppgtt; |
2669 | const u64 size = min(vma->size, vma->node.size); | |
6f65e29a | 2670 | |
3272db53 | 2671 | if (vma->flags & I915_VMA_GLOBAL_BIND) |
782f1495 | 2672 | vma->vm->clear_range(vma->vm, |
de180033 | 2673 | vma->node.start, size, |
6f65e29a | 2674 | true); |
06615ee5 | 2675 | |
3272db53 | 2676 | if (vma->flags & I915_VMA_LOCAL_BIND && appgtt) |
6f65e29a | 2677 | appgtt->base.clear_range(&appgtt->base, |
de180033 | 2678 | vma->node.start, size, |
6f65e29a | 2679 | true); |
74163907 DV |
2680 | } |
2681 | ||
2682 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 2683 | { |
52a05c30 DW |
2684 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2685 | struct device *kdev = &dev_priv->drm.pdev->dev; | |
307dc25b | 2686 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
5c042287 | 2687 | |
307dc25b | 2688 | if (unlikely(ggtt->do_idle_maps)) { |
22dd3bb9 | 2689 | if (i915_gem_wait_for_idle(dev_priv, I915_WAIT_LOCKED)) { |
307dc25b CW |
2690 | DRM_ERROR("Failed to wait for idle; VT'd may hang.\n"); |
2691 | /* Wait a bit, in hopes it avoids the hang */ | |
2692 | udelay(10); | |
2693 | } | |
2694 | } | |
5c042287 | 2695 | |
52a05c30 | 2696 | dma_unmap_sg(kdev, obj->pages->sgl, obj->pages->nents, |
5ec5b516 | 2697 | PCI_DMA_BIDIRECTIONAL); |
7c2e6fdf | 2698 | } |
644ec02b | 2699 | |
42d6ab48 CW |
2700 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
2701 | unsigned long color, | |
440fd528 TR |
2702 | u64 *start, |
2703 | u64 *end) | |
42d6ab48 CW |
2704 | { |
2705 | if (node->color != color) | |
2706 | *start += 4096; | |
2707 | ||
2a1d7752 CW |
2708 | node = list_first_entry_or_null(&node->node_list, |
2709 | struct drm_mm_node, | |
2710 | node_list); | |
2711 | if (node && node->allocated && node->color != color) | |
2712 | *end -= 4096; | |
42d6ab48 | 2713 | } |
fbe5d36e | 2714 | |
f6b9d5ca | 2715 | int i915_gem_init_ggtt(struct drm_i915_private *dev_priv) |
644ec02b | 2716 | { |
e78891ca BW |
2717 | /* Let GEM Manage all of the aperture. |
2718 | * | |
2719 | * However, leave one page at the end still bound to the scratch page. | |
2720 | * There are a number of places where the hardware apparently prefetches | |
2721 | * past the end of the object, and we've seen multiple hangs with the | |
2722 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2723 | * aperture. One page should be enough to keep any prefetching inside | |
2724 | * of the aperture. | |
2725 | */ | |
72e96d64 | 2726 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
ed2f3452 | 2727 | unsigned long hole_start, hole_end; |
95374d75 | 2728 | struct i915_hw_ppgtt *ppgtt; |
f6b9d5ca | 2729 | struct drm_mm_node *entry; |
fa76da34 | 2730 | int ret; |
644ec02b | 2731 | |
b02d22a3 ZW |
2732 | ret = intel_vgt_balloon(dev_priv); |
2733 | if (ret) | |
2734 | return ret; | |
5dda8fa3 | 2735 | |
95374d75 CW |
2736 | /* Reserve a mappable slot for our lockless error capture */ |
2737 | ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm, | |
2738 | &ggtt->error_capture, | |
2739 | 4096, 0, -1, | |
2740 | 0, ggtt->mappable_end, | |
2741 | 0, 0); | |
2742 | if (ret) | |
2743 | return ret; | |
2744 | ||
ed2f3452 | 2745 | /* Clear any non-preallocated blocks */ |
72e96d64 | 2746 | drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) { |
ed2f3452 CW |
2747 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2748 | hole_start, hole_end); | |
72e96d64 | 2749 | ggtt->base.clear_range(&ggtt->base, hole_start, |
782f1495 | 2750 | hole_end - hole_start, true); |
ed2f3452 CW |
2751 | } |
2752 | ||
2753 | /* And finally clear the reserved guard page */ | |
f6b9d5ca CW |
2754 | ggtt->base.clear_range(&ggtt->base, |
2755 | ggtt->base.total - PAGE_SIZE, PAGE_SIZE, | |
2756 | true); | |
6c5566a8 | 2757 | |
97d6d7ab | 2758 | if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) { |
fa76da34 | 2759 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
95374d75 CW |
2760 | if (!ppgtt) { |
2761 | ret = -ENOMEM; | |
2762 | goto err; | |
2763 | } | |
fa76da34 | 2764 | |
2bfa996e | 2765 | ret = __hw_ppgtt_init(ppgtt, dev_priv); |
95374d75 CW |
2766 | if (ret) |
2767 | goto err_ppgtt; | |
5c5f6457 | 2768 | |
95374d75 | 2769 | if (ppgtt->base.allocate_va_range) { |
5c5f6457 DV |
2770 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, |
2771 | ppgtt->base.total); | |
95374d75 CW |
2772 | if (ret) |
2773 | goto err_ppgtt_cleanup; | |
4933d519 | 2774 | } |
fa76da34 | 2775 | |
5c5f6457 DV |
2776 | ppgtt->base.clear_range(&ppgtt->base, |
2777 | ppgtt->base.start, | |
2778 | ppgtt->base.total, | |
2779 | true); | |
2780 | ||
fa76da34 | 2781 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
72e96d64 JL |
2782 | WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma); |
2783 | ggtt->base.bind_vma = aliasing_gtt_bind_vma; | |
fa76da34 DV |
2784 | } |
2785 | ||
6c5566a8 | 2786 | return 0; |
95374d75 CW |
2787 | |
2788 | err_ppgtt_cleanup: | |
2789 | ppgtt->base.cleanup(&ppgtt->base); | |
2790 | err_ppgtt: | |
2791 | kfree(ppgtt); | |
2792 | err: | |
2793 | drm_mm_remove_node(&ggtt->error_capture); | |
2794 | return ret; | |
e76e9aeb BW |
2795 | } |
2796 | ||
d85489d3 JL |
2797 | /** |
2798 | * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization | |
97d6d7ab | 2799 | * @dev_priv: i915 device |
d85489d3 | 2800 | */ |
97d6d7ab | 2801 | void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv) |
90d0a0e8 | 2802 | { |
72e96d64 | 2803 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
90d0a0e8 | 2804 | |
70e32544 DV |
2805 | if (dev_priv->mm.aliasing_ppgtt) { |
2806 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
70e32544 | 2807 | ppgtt->base.cleanup(&ppgtt->base); |
cb7f2760 | 2808 | kfree(ppgtt); |
70e32544 DV |
2809 | } |
2810 | ||
97d6d7ab | 2811 | i915_gem_cleanup_stolen(&dev_priv->drm); |
a4eba47b | 2812 | |
95374d75 CW |
2813 | if (drm_mm_node_allocated(&ggtt->error_capture)) |
2814 | drm_mm_remove_node(&ggtt->error_capture); | |
2815 | ||
72e96d64 | 2816 | if (drm_mm_initialized(&ggtt->base.mm)) { |
b02d22a3 | 2817 | intel_vgt_deballoon(dev_priv); |
5dda8fa3 | 2818 | |
72e96d64 JL |
2819 | drm_mm_takedown(&ggtt->base.mm); |
2820 | list_del(&ggtt->base.global_link); | |
90d0a0e8 DV |
2821 | } |
2822 | ||
72e96d64 | 2823 | ggtt->base.cleanup(&ggtt->base); |
f6b9d5ca CW |
2824 | |
2825 | arch_phys_wc_del(ggtt->mtrr); | |
f7bbe788 | 2826 | io_mapping_fini(&ggtt->mappable); |
90d0a0e8 | 2827 | } |
70e32544 | 2828 | |
2c642b07 | 2829 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2830 | { |
2831 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2832 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2833 | return snb_gmch_ctl << 20; | |
2834 | } | |
2835 | ||
2c642b07 | 2836 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2837 | { |
2838 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2839 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2840 | if (bdw_gmch_ctl) | |
2841 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2842 | |
2843 | #ifdef CONFIG_X86_32 | |
2844 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2845 | if (bdw_gmch_ctl > 4) | |
2846 | bdw_gmch_ctl = 4; | |
2847 | #endif | |
2848 | ||
9459d252 BW |
2849 | return bdw_gmch_ctl << 20; |
2850 | } | |
2851 | ||
2c642b07 | 2852 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2853 | { |
2854 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2855 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2856 | ||
2857 | if (gmch_ctrl) | |
2858 | return 1 << (20 + gmch_ctrl); | |
2859 | ||
2860 | return 0; | |
2861 | } | |
2862 | ||
2c642b07 | 2863 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2864 | { |
2865 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2866 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2867 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2868 | } | |
2869 | ||
2c642b07 | 2870 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2871 | { |
2872 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2873 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2874 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2875 | } | |
2876 | ||
d7f25f23 DL |
2877 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2878 | { | |
2879 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2880 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2881 | ||
2882 | /* | |
2883 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2884 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2885 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2886 | */ | |
2887 | if (gmch_ctrl < 0x11) | |
2888 | return gmch_ctrl << 25; | |
2889 | else if (gmch_ctrl < 0x17) | |
2890 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2891 | else | |
2892 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2893 | } | |
2894 | ||
66375014 DL |
2895 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2896 | { | |
2897 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2898 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2899 | ||
2900 | if (gen9_gmch_ctl < 0xf0) | |
2901 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2902 | else | |
2903 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2904 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2905 | } | |
2906 | ||
34c998b4 | 2907 | static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) |
63340133 | 2908 | { |
34c998b4 | 2909 | struct pci_dev *pdev = ggtt->base.dev->pdev; |
34c998b4 | 2910 | phys_addr_t phys_addr; |
8bcdd0f7 | 2911 | int ret; |
63340133 BW |
2912 | |
2913 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
34c998b4 | 2914 | phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2; |
63340133 | 2915 | |
2a073f89 ID |
2916 | /* |
2917 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2918 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2919 | * when the WC buffer is flushed, so we can't use it, but have to | |
2920 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2921 | * readback check when writing GTT PTE entries. | |
2922 | */ | |
e2d214ae | 2923 | if (IS_BROXTON(to_i915(ggtt->base.dev))) |
34c998b4 | 2924 | ggtt->gsm = ioremap_nocache(phys_addr, size); |
2a073f89 | 2925 | else |
34c998b4 | 2926 | ggtt->gsm = ioremap_wc(phys_addr, size); |
72e96d64 | 2927 | if (!ggtt->gsm) { |
34c998b4 | 2928 | DRM_ERROR("Failed to map the ggtt page table\n"); |
63340133 BW |
2929 | return -ENOMEM; |
2930 | } | |
2931 | ||
bb8f9cff CW |
2932 | ret = setup_scratch_page(ggtt->base.dev, |
2933 | &ggtt->base.scratch_page, | |
2934 | GFP_DMA32); | |
8bcdd0f7 | 2935 | if (ret) { |
63340133 BW |
2936 | DRM_ERROR("Scratch setup failed\n"); |
2937 | /* iounmap will also get called at remove, but meh */ | |
72e96d64 | 2938 | iounmap(ggtt->gsm); |
8bcdd0f7 | 2939 | return ret; |
63340133 BW |
2940 | } |
2941 | ||
4ad2af1e | 2942 | return 0; |
63340133 BW |
2943 | } |
2944 | ||
fbe5d36e BW |
2945 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2946 | * bits. When using advanced contexts each context stores its own PAT, but | |
2947 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2948 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2949 | { |
fbe5d36e BW |
2950 | uint64_t pat; |
2951 | ||
2952 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2953 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2954 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2955 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2956 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2957 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2958 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2959 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2960 | ||
2d1fe073 | 2961 | if (!USES_PPGTT(dev_priv)) |
d6a8b72e RV |
2962 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
2963 | * so RTL will always use the value corresponding to | |
2964 | * pat_sel = 000". | |
2965 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2966 | * MOCS still can be used though. | |
2967 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2968 | * before this patch, i.e. the same uncached + snooping access | |
2969 | * like on gen6/7 seems to be in effect. | |
2970 | * - So this just fixes blitter/render access. Again it looks | |
2971 | * like it's not just uncached access, but uncached + snooping. | |
2972 | * So we can still hold onto all our assumptions wrt cpu | |
2973 | * clflushing on LLC machines. | |
2974 | */ | |
2975 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2976 | ||
fbe5d36e BW |
2977 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2978 | * write would work. */ | |
7e435ad2 VS |
2979 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
2980 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
fbe5d36e BW |
2981 | } |
2982 | ||
ee0ce478 VS |
2983 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2984 | { | |
2985 | uint64_t pat; | |
2986 | ||
2987 | /* | |
2988 | * Map WB on BDW to snooped on CHV. | |
2989 | * | |
2990 | * Only the snoop bit has meaning for CHV, the rest is | |
2991 | * ignored. | |
2992 | * | |
cf3d262e VS |
2993 | * The hardware will never snoop for certain types of accesses: |
2994 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2995 | * - PPGTT page tables | |
2996 | * - some other special cycles | |
2997 | * | |
2998 | * As with BDW, we also need to consider the following for GT accesses: | |
2999 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
3000 | * so RTL will always use the value corresponding to | |
3001 | * pat_sel = 000". | |
3002 | * Which means we must set the snoop bit in PAT entry 0 | |
3003 | * in order to keep the global status page working. | |
ee0ce478 VS |
3004 | */ |
3005 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
3006 | GEN8_PPAT(1, 0) | | |
3007 | GEN8_PPAT(2, 0) | | |
3008 | GEN8_PPAT(3, 0) | | |
3009 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
3010 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
3011 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
3012 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
3013 | ||
7e435ad2 VS |
3014 | I915_WRITE(GEN8_PRIVATE_PAT_LO, pat); |
3015 | I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32); | |
ee0ce478 VS |
3016 | } |
3017 | ||
34c998b4 CW |
3018 | static void gen6_gmch_remove(struct i915_address_space *vm) |
3019 | { | |
3020 | struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm); | |
3021 | ||
3022 | iounmap(ggtt->gsm); | |
8bcdd0f7 | 3023 | cleanup_scratch_page(vm->dev, &vm->scratch_page); |
34c998b4 CW |
3024 | } |
3025 | ||
d507d735 | 3026 | static int gen8_gmch_probe(struct i915_ggtt *ggtt) |
63340133 | 3027 | { |
97d6d7ab CW |
3028 | struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev); |
3029 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
34c998b4 | 3030 | unsigned int size; |
63340133 | 3031 | u16 snb_gmch_ctl; |
63340133 BW |
3032 | |
3033 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
97d6d7ab CW |
3034 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3035 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
63340133 | 3036 | |
97d6d7ab CW |
3037 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(39))) |
3038 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39)); | |
63340133 | 3039 | |
97d6d7ab | 3040 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
63340133 | 3041 | |
97d6d7ab | 3042 | if (INTEL_GEN(dev_priv) >= 9) { |
d507d735 | 3043 | ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3044 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
97d6d7ab | 3045 | } else if (IS_CHERRYVIEW(dev_priv)) { |
d507d735 | 3046 | ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3047 | size = chv_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3048 | } else { |
d507d735 | 3049 | ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl); |
34c998b4 | 3050 | size = gen8_get_total_gtt_size(snb_gmch_ctl); |
d7f25f23 | 3051 | } |
63340133 | 3052 | |
34c998b4 | 3053 | ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 3054 | |
97d6d7ab | 3055 | if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) |
ee0ce478 VS |
3056 | chv_setup_private_ppat(dev_priv); |
3057 | else | |
3058 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 3059 | |
34c998b4 | 3060 | ggtt->base.cleanup = gen6_gmch_remove; |
d507d735 JL |
3061 | ggtt->base.bind_vma = ggtt_bind_vma; |
3062 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
d6473f56 | 3063 | ggtt->base.insert_page = gen8_ggtt_insert_page; |
f7770bfd | 3064 | ggtt->base.clear_range = nop_clear_range; |
48f112fe | 3065 | if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) |
f7770bfd CW |
3066 | ggtt->base.clear_range = gen8_ggtt_clear_range; |
3067 | ||
3068 | ggtt->base.insert_entries = gen8_ggtt_insert_entries; | |
3069 | if (IS_CHERRYVIEW(dev_priv)) | |
3070 | ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL; | |
3071 | ||
34c998b4 | 3072 | return ggtt_probe_common(ggtt, size); |
63340133 BW |
3073 | } |
3074 | ||
d507d735 | 3075 | static int gen6_gmch_probe(struct i915_ggtt *ggtt) |
e76e9aeb | 3076 | { |
97d6d7ab CW |
3077 | struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev); |
3078 | struct pci_dev *pdev = dev_priv->drm.pdev; | |
34c998b4 | 3079 | unsigned int size; |
e76e9aeb | 3080 | u16 snb_gmch_ctl; |
e76e9aeb | 3081 | |
97d6d7ab CW |
3082 | ggtt->mappable_base = pci_resource_start(pdev, 2); |
3083 | ggtt->mappable_end = pci_resource_len(pdev, 2); | |
41907ddc | 3084 | |
baa09f5f BW |
3085 | /* 64/512MB is the current min/max we actually know of, but this is just |
3086 | * a coarse sanity check. | |
e76e9aeb | 3087 | */ |
34c998b4 | 3088 | if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) { |
d507d735 | 3089 | DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end); |
baa09f5f | 3090 | return -ENXIO; |
e76e9aeb BW |
3091 | } |
3092 | ||
97d6d7ab CW |
3093 | if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(40))) |
3094 | pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)); | |
3095 | pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
e76e9aeb | 3096 | |
d507d735 | 3097 | ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl); |
e76e9aeb | 3098 | |
34c998b4 CW |
3099 | size = gen6_get_total_gtt_size(snb_gmch_ctl); |
3100 | ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 3101 | |
d507d735 | 3102 | ggtt->base.clear_range = gen6_ggtt_clear_range; |
d6473f56 | 3103 | ggtt->base.insert_page = gen6_ggtt_insert_page; |
d507d735 JL |
3104 | ggtt->base.insert_entries = gen6_ggtt_insert_entries; |
3105 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3106 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 CW |
3107 | ggtt->base.cleanup = gen6_gmch_remove; |
3108 | ||
3109 | if (HAS_EDRAM(dev_priv)) | |
3110 | ggtt->base.pte_encode = iris_pte_encode; | |
3111 | else if (IS_HASWELL(dev_priv)) | |
3112 | ggtt->base.pte_encode = hsw_pte_encode; | |
3113 | else if (IS_VALLEYVIEW(dev_priv)) | |
3114 | ggtt->base.pte_encode = byt_pte_encode; | |
3115 | else if (INTEL_GEN(dev_priv) >= 7) | |
3116 | ggtt->base.pte_encode = ivb_pte_encode; | |
3117 | else | |
3118 | ggtt->base.pte_encode = snb_pte_encode; | |
7faf1ab2 | 3119 | |
34c998b4 | 3120 | return ggtt_probe_common(ggtt, size); |
e76e9aeb BW |
3121 | } |
3122 | ||
34c998b4 | 3123 | static void i915_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 3124 | { |
34c998b4 | 3125 | intel_gmch_remove(); |
644ec02b | 3126 | } |
baa09f5f | 3127 | |
d507d735 | 3128 | static int i915_gmch_probe(struct i915_ggtt *ggtt) |
baa09f5f | 3129 | { |
97d6d7ab | 3130 | struct drm_i915_private *dev_priv = to_i915(ggtt->base.dev); |
baa09f5f BW |
3131 | int ret; |
3132 | ||
91c8a326 | 3133 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL); |
baa09f5f BW |
3134 | if (!ret) { |
3135 | DRM_ERROR("failed to set up gmch\n"); | |
3136 | return -EIO; | |
3137 | } | |
3138 | ||
d507d735 JL |
3139 | intel_gtt_get(&ggtt->base.total, &ggtt->stolen_size, |
3140 | &ggtt->mappable_base, &ggtt->mappable_end); | |
baa09f5f | 3141 | |
97d6d7ab | 3142 | ggtt->do_idle_maps = needs_idle_maps(dev_priv); |
d6473f56 | 3143 | ggtt->base.insert_page = i915_ggtt_insert_page; |
d507d735 JL |
3144 | ggtt->base.insert_entries = i915_ggtt_insert_entries; |
3145 | ggtt->base.clear_range = i915_ggtt_clear_range; | |
3146 | ggtt->base.bind_vma = ggtt_bind_vma; | |
3147 | ggtt->base.unbind_vma = ggtt_unbind_vma; | |
34c998b4 | 3148 | ggtt->base.cleanup = i915_gmch_remove; |
baa09f5f | 3149 | |
d507d735 | 3150 | if (unlikely(ggtt->do_idle_maps)) |
c0a7f818 CW |
3151 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
3152 | ||
baa09f5f BW |
3153 | return 0; |
3154 | } | |
3155 | ||
d85489d3 | 3156 | /** |
0088e522 | 3157 | * i915_ggtt_probe_hw - Probe GGTT hardware location |
97d6d7ab | 3158 | * @dev_priv: i915 device |
d85489d3 | 3159 | */ |
97d6d7ab | 3160 | int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) |
baa09f5f | 3161 | { |
62106b4f | 3162 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
baa09f5f BW |
3163 | int ret; |
3164 | ||
97d6d7ab | 3165 | ggtt->base.dev = &dev_priv->drm; |
c114f76a | 3166 | |
34c998b4 CW |
3167 | if (INTEL_GEN(dev_priv) <= 5) |
3168 | ret = i915_gmch_probe(ggtt); | |
3169 | else if (INTEL_GEN(dev_priv) < 8) | |
3170 | ret = gen6_gmch_probe(ggtt); | |
3171 | else | |
3172 | ret = gen8_gmch_probe(ggtt); | |
a54c0c27 | 3173 | if (ret) |
baa09f5f | 3174 | return ret; |
baa09f5f | 3175 | |
c890e2d5 CW |
3176 | if ((ggtt->base.total - 1) >> 32) { |
3177 | DRM_ERROR("We never expected a Global GTT with more than 32bits" | |
f6b9d5ca | 3178 | " of address space! Found %lldM!\n", |
c890e2d5 CW |
3179 | ggtt->base.total >> 20); |
3180 | ggtt->base.total = 1ULL << 32; | |
3181 | ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total); | |
3182 | } | |
3183 | ||
f6b9d5ca CW |
3184 | if (ggtt->mappable_end > ggtt->base.total) { |
3185 | DRM_ERROR("mappable aperture extends past end of GGTT," | |
3186 | " aperture=%llx, total=%llx\n", | |
3187 | ggtt->mappable_end, ggtt->base.total); | |
3188 | ggtt->mappable_end = ggtt->base.total; | |
3189 | } | |
3190 | ||
baa09f5f | 3191 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 3192 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
62106b4f JL |
3193 | ggtt->base.total >> 20); |
3194 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20); | |
3195 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt->stolen_size >> 20); | |
5db6c735 DV |
3196 | #ifdef CONFIG_INTEL_IOMMU |
3197 | if (intel_iommu_gfx_mapped) | |
3198 | DRM_INFO("VT-d active for gfx access\n"); | |
3199 | #endif | |
baa09f5f BW |
3200 | |
3201 | return 0; | |
0088e522 CW |
3202 | } |
3203 | ||
3204 | /** | |
3205 | * i915_ggtt_init_hw - Initialize GGTT hardware | |
97d6d7ab | 3206 | * @dev_priv: i915 device |
0088e522 | 3207 | */ |
97d6d7ab | 3208 | int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) |
0088e522 | 3209 | { |
0088e522 CW |
3210 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
3211 | int ret; | |
3212 | ||
f6b9d5ca CW |
3213 | INIT_LIST_HEAD(&dev_priv->vm_list); |
3214 | ||
3215 | /* Subtract the guard page before address space initialization to | |
3216 | * shrink the range used by drm_mm. | |
3217 | */ | |
3218 | ggtt->base.total -= PAGE_SIZE; | |
3219 | i915_address_space_init(&ggtt->base, dev_priv); | |
3220 | ggtt->base.total += PAGE_SIZE; | |
3221 | if (!HAS_LLC(dev_priv)) | |
3222 | ggtt->base.mm.color_adjust = i915_gtt_color_adjust; | |
3223 | ||
f7bbe788 CW |
3224 | if (!io_mapping_init_wc(&dev_priv->ggtt.mappable, |
3225 | dev_priv->ggtt.mappable_base, | |
3226 | dev_priv->ggtt.mappable_end)) { | |
f6b9d5ca CW |
3227 | ret = -EIO; |
3228 | goto out_gtt_cleanup; | |
3229 | } | |
3230 | ||
3231 | ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end); | |
3232 | ||
0088e522 CW |
3233 | /* |
3234 | * Initialise stolen early so that we may reserve preallocated | |
3235 | * objects for the BIOS to KMS transition. | |
3236 | */ | |
97d6d7ab | 3237 | ret = i915_gem_init_stolen(&dev_priv->drm); |
0088e522 CW |
3238 | if (ret) |
3239 | goto out_gtt_cleanup; | |
3240 | ||
3241 | return 0; | |
a4eba47b ID |
3242 | |
3243 | out_gtt_cleanup: | |
72e96d64 | 3244 | ggtt->base.cleanup(&ggtt->base); |
a4eba47b | 3245 | return ret; |
baa09f5f | 3246 | } |
6f65e29a | 3247 | |
97d6d7ab | 3248 | int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) |
ac840ae5 | 3249 | { |
97d6d7ab | 3250 | if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt()) |
ac840ae5 VS |
3251 | return -EIO; |
3252 | ||
3253 | return 0; | |
3254 | } | |
3255 | ||
fa42331b DV |
3256 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
3257 | { | |
72e96d64 JL |
3258 | struct drm_i915_private *dev_priv = to_i915(dev); |
3259 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
fbb30a5c | 3260 | struct drm_i915_gem_object *obj, *on; |
fa42331b | 3261 | |
dc97997a | 3262 | i915_check_and_clear_faults(dev_priv); |
fa42331b DV |
3263 | |
3264 | /* First fill our portion of the GTT with scratch pages */ | |
72e96d64 JL |
3265 | ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total, |
3266 | true); | |
fa42331b | 3267 | |
fbb30a5c CW |
3268 | ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */ |
3269 | ||
3270 | /* clflush objects bound into the GGTT and rebind them. */ | |
3271 | list_for_each_entry_safe(obj, on, | |
3272 | &dev_priv->mm.bound_list, global_list) { | |
3273 | bool ggtt_bound = false; | |
3274 | struct i915_vma *vma; | |
3275 | ||
1c7f4bca | 3276 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
72e96d64 | 3277 | if (vma->vm != &ggtt->base) |
2c3d9984 | 3278 | continue; |
fa42331b | 3279 | |
fbb30a5c CW |
3280 | if (!i915_vma_unbind(vma)) |
3281 | continue; | |
3282 | ||
2c3d9984 TU |
3283 | WARN_ON(i915_vma_bind(vma, obj->cache_level, |
3284 | PIN_UPDATE)); | |
fbb30a5c | 3285 | ggtt_bound = true; |
2c3d9984 TU |
3286 | } |
3287 | ||
fbb30a5c | 3288 | if (ggtt_bound) |
975f7ff4 | 3289 | WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false)); |
2c3d9984 | 3290 | } |
fa42331b | 3291 | |
fbb30a5c CW |
3292 | ggtt->base.closed = false; |
3293 | ||
fa42331b | 3294 | if (INTEL_INFO(dev)->gen >= 8) { |
e2d214ae | 3295 | if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv)) |
fa42331b DV |
3296 | chv_setup_private_ppat(dev_priv); |
3297 | else | |
3298 | bdw_setup_private_ppat(dev_priv); | |
3299 | ||
3300 | return; | |
3301 | } | |
3302 | ||
3303 | if (USES_PPGTT(dev)) { | |
72e96d64 JL |
3304 | struct i915_address_space *vm; |
3305 | ||
fa42331b DV |
3306 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
3307 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
3308 | ||
e5716f55 | 3309 | struct i915_hw_ppgtt *ppgtt; |
fa42331b | 3310 | |
2bfa996e | 3311 | if (i915_is_ggtt(vm)) |
fa42331b | 3312 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
e5716f55 JL |
3313 | else |
3314 | ppgtt = i915_vm_to_ppgtt(vm); | |
fa42331b DV |
3315 | |
3316 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
3317 | 0, ppgtt->base.total); | |
3318 | } | |
3319 | } | |
3320 | ||
3321 | i915_ggtt_flush(dev_priv); | |
3322 | } | |
3323 | ||
b0decaf7 CW |
3324 | static void |
3325 | i915_vma_retire(struct i915_gem_active *active, | |
3326 | struct drm_i915_gem_request *rq) | |
3327 | { | |
3328 | const unsigned int idx = rq->engine->id; | |
3329 | struct i915_vma *vma = | |
3330 | container_of(active, struct i915_vma, last_read[idx]); | |
3331 | ||
3332 | GEM_BUG_ON(!i915_vma_has_active_engine(vma, idx)); | |
3333 | ||
3334 | i915_vma_clear_active(vma, idx); | |
3335 | if (i915_vma_is_active(vma)) | |
3336 | return; | |
3337 | ||
3338 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
3272db53 | 3339 | if (unlikely(i915_vma_is_closed(vma) && !i915_vma_is_pinned(vma))) |
b1f788c6 CW |
3340 | WARN_ON(i915_vma_unbind(vma)); |
3341 | } | |
3342 | ||
3343 | void i915_vma_destroy(struct i915_vma *vma) | |
3344 | { | |
3345 | GEM_BUG_ON(vma->node.allocated); | |
3346 | GEM_BUG_ON(i915_vma_is_active(vma)); | |
3272db53 | 3347 | GEM_BUG_ON(!i915_vma_is_closed(vma)); |
49ef5294 | 3348 | GEM_BUG_ON(vma->fence); |
b1f788c6 CW |
3349 | |
3350 | list_del(&vma->vm_link); | |
3272db53 | 3351 | if (!i915_vma_is_ggtt(vma)) |
b1f788c6 CW |
3352 | i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); |
3353 | ||
3354 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); | |
3355 | } | |
3356 | ||
3357 | void i915_vma_close(struct i915_vma *vma) | |
3358 | { | |
3272db53 CW |
3359 | GEM_BUG_ON(i915_vma_is_closed(vma)); |
3360 | vma->flags |= I915_VMA_CLOSED; | |
b1f788c6 CW |
3361 | |
3362 | list_del_init(&vma->obj_link); | |
20dfbde4 | 3363 | if (!i915_vma_is_active(vma) && !i915_vma_is_pinned(vma)) |
df0e9a28 | 3364 | WARN_ON(i915_vma_unbind(vma)); |
b0decaf7 CW |
3365 | } |
3366 | ||
ec7adb6e | 3367 | static struct i915_vma * |
058d88c4 CW |
3368 | __i915_vma_create(struct drm_i915_gem_object *obj, |
3369 | struct i915_address_space *vm, | |
3370 | const struct i915_ggtt_view *view) | |
6f65e29a | 3371 | { |
dabde5c7 | 3372 | struct i915_vma *vma; |
b0decaf7 | 3373 | int i; |
6f65e29a | 3374 | |
50e046b6 CW |
3375 | GEM_BUG_ON(vm->closed); |
3376 | ||
e20d2ab7 | 3377 | vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); |
dabde5c7 DC |
3378 | if (vma == NULL) |
3379 | return ERR_PTR(-ENOMEM); | |
ec7adb6e | 3380 | |
6f65e29a | 3381 | INIT_LIST_HEAD(&vma->exec_list); |
b0decaf7 CW |
3382 | for (i = 0; i < ARRAY_SIZE(vma->last_read); i++) |
3383 | init_request_active(&vma->last_read[i], i915_vma_retire); | |
49ef5294 | 3384 | init_request_active(&vma->last_fence, NULL); |
50e046b6 | 3385 | list_add(&vma->vm_link, &vm->unbound_list); |
6f65e29a BW |
3386 | vma->vm = vm; |
3387 | vma->obj = obj; | |
de180033 | 3388 | vma->size = obj->base.size; |
6f65e29a | 3389 | |
058d88c4 | 3390 | if (view) { |
de180033 CW |
3391 | vma->ggtt_view = *view; |
3392 | if (view->type == I915_GGTT_VIEW_PARTIAL) { | |
3393 | vma->size = view->params.partial.size; | |
3394 | vma->size <<= PAGE_SHIFT; | |
3395 | } else if (view->type == I915_GGTT_VIEW_ROTATED) { | |
3396 | vma->size = | |
3397 | intel_rotation_info_size(&view->params.rotated); | |
3398 | vma->size <<= PAGE_SHIFT; | |
3399 | } | |
058d88c4 CW |
3400 | } |
3401 | ||
3402 | if (i915_is_ggtt(vm)) { | |
3403 | vma->flags |= I915_VMA_GGTT; | |
de180033 | 3404 | } else { |
596c5923 | 3405 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
de180033 | 3406 | } |
6f65e29a | 3407 | |
1c7f4bca | 3408 | list_add_tail(&vma->obj_link, &obj->vma_list); |
6f65e29a BW |
3409 | return vma; |
3410 | } | |
3411 | ||
058d88c4 CW |
3412 | static inline bool vma_matches(struct i915_vma *vma, |
3413 | struct i915_address_space *vm, | |
3414 | const struct i915_ggtt_view *view) | |
3415 | { | |
3416 | if (vma->vm != vm) | |
3417 | return false; | |
3418 | ||
3419 | if (!i915_vma_is_ggtt(vma)) | |
3420 | return true; | |
3421 | ||
3422 | if (!view) | |
3423 | return vma->ggtt_view.type == 0; | |
3424 | ||
3425 | if (vma->ggtt_view.type != view->type) | |
3426 | return false; | |
3427 | ||
3428 | return memcmp(&vma->ggtt_view.params, | |
3429 | &view->params, | |
3430 | sizeof(view->params)) == 0; | |
3431 | } | |
3432 | ||
81a8aa4a CW |
3433 | struct i915_vma * |
3434 | i915_vma_create(struct drm_i915_gem_object *obj, | |
3435 | struct i915_address_space *vm, | |
3436 | const struct i915_ggtt_view *view) | |
3437 | { | |
3438 | GEM_BUG_ON(view && !i915_is_ggtt(vm)); | |
058d88c4 | 3439 | GEM_BUG_ON(i915_gem_obj_to_vma(obj, vm, view)); |
81a8aa4a | 3440 | |
058d88c4 | 3441 | return __i915_vma_create(obj, vm, view); |
81a8aa4a CW |
3442 | } |
3443 | ||
6f65e29a | 3444 | struct i915_vma * |
058d88c4 CW |
3445 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3446 | struct i915_address_space *vm, | |
3447 | const struct i915_ggtt_view *view) | |
ec7adb6e JL |
3448 | { |
3449 | struct i915_vma *vma; | |
3450 | ||
058d88c4 CW |
3451 | list_for_each_entry_reverse(vma, &obj->vma_list, obj_link) |
3452 | if (vma_matches(vma, vm, view)) | |
3453 | return vma; | |
ec7adb6e | 3454 | |
058d88c4 | 3455 | return NULL; |
ec7adb6e JL |
3456 | } |
3457 | ||
3458 | struct i915_vma * | |
058d88c4 CW |
3459 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
3460 | struct i915_address_space *vm, | |
3461 | const struct i915_ggtt_view *view) | |
6f65e29a | 3462 | { |
058d88c4 | 3463 | struct i915_vma *vma; |
ec7adb6e | 3464 | |
058d88c4 | 3465 | GEM_BUG_ON(view && !i915_is_ggtt(vm)); |
de895082 | 3466 | |
058d88c4 | 3467 | vma = i915_gem_obj_to_vma(obj, vm, view); |
6f65e29a | 3468 | if (!vma) |
058d88c4 | 3469 | vma = __i915_vma_create(obj, vm, view); |
6f65e29a | 3470 | |
3272db53 | 3471 | GEM_BUG_ON(i915_vma_is_closed(vma)); |
6f65e29a BW |
3472 | return vma; |
3473 | } | |
fe14d5f4 | 3474 | |
804beb4b | 3475 | static struct scatterlist * |
2d7f3bdb | 3476 | rotate_pages(const dma_addr_t *in, unsigned int offset, |
804beb4b | 3477 | unsigned int width, unsigned int height, |
87130255 | 3478 | unsigned int stride, |
804beb4b | 3479 | struct sg_table *st, struct scatterlist *sg) |
50470bb0 TU |
3480 | { |
3481 | unsigned int column, row; | |
3482 | unsigned int src_idx; | |
50470bb0 | 3483 | |
50470bb0 | 3484 | for (column = 0; column < width; column++) { |
87130255 | 3485 | src_idx = stride * (height - 1) + column; |
50470bb0 TU |
3486 | for (row = 0; row < height; row++) { |
3487 | st->nents++; | |
3488 | /* We don't need the pages, but need to initialize | |
3489 | * the entries so the sg list can be happily traversed. | |
3490 | * The only thing we need are DMA addresses. | |
3491 | */ | |
3492 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
804beb4b | 3493 | sg_dma_address(sg) = in[offset + src_idx]; |
50470bb0 TU |
3494 | sg_dma_len(sg) = PAGE_SIZE; |
3495 | sg = sg_next(sg); | |
87130255 | 3496 | src_idx -= stride; |
50470bb0 TU |
3497 | } |
3498 | } | |
804beb4b TU |
3499 | |
3500 | return sg; | |
50470bb0 TU |
3501 | } |
3502 | ||
3503 | static struct sg_table * | |
6687c906 | 3504 | intel_rotate_fb_obj_pages(const struct intel_rotation_info *rot_info, |
50470bb0 TU |
3505 | struct drm_i915_gem_object *obj) |
3506 | { | |
85d1225e | 3507 | const size_t n_pages = obj->base.size / PAGE_SIZE; |
6687c906 | 3508 | unsigned int size = intel_rotation_info_size(rot_info); |
85d1225e DG |
3509 | struct sgt_iter sgt_iter; |
3510 | dma_addr_t dma_addr; | |
50470bb0 TU |
3511 | unsigned long i; |
3512 | dma_addr_t *page_addr_list; | |
3513 | struct sg_table *st; | |
89e3e142 | 3514 | struct scatterlist *sg; |
1d00dad5 | 3515 | int ret = -ENOMEM; |
50470bb0 | 3516 | |
50470bb0 | 3517 | /* Allocate a temporary list of source pages for random access. */ |
85d1225e | 3518 | page_addr_list = drm_malloc_gfp(n_pages, |
f2a85e19 CW |
3519 | sizeof(dma_addr_t), |
3520 | GFP_TEMPORARY); | |
50470bb0 TU |
3521 | if (!page_addr_list) |
3522 | return ERR_PTR(ret); | |
3523 | ||
3524 | /* Allocate target SG list. */ | |
3525 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3526 | if (!st) | |
3527 | goto err_st_alloc; | |
3528 | ||
6687c906 | 3529 | ret = sg_alloc_table(st, size, GFP_KERNEL); |
50470bb0 TU |
3530 | if (ret) |
3531 | goto err_sg_alloc; | |
3532 | ||
3533 | /* Populate source page list from the object. */ | |
3534 | i = 0; | |
85d1225e DG |
3535 | for_each_sgt_dma(dma_addr, sgt_iter, obj->pages) |
3536 | page_addr_list[i++] = dma_addr; | |
50470bb0 | 3537 | |
85d1225e | 3538 | GEM_BUG_ON(i != n_pages); |
11f20322 VS |
3539 | st->nents = 0; |
3540 | sg = st->sgl; | |
3541 | ||
6687c906 VS |
3542 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) { |
3543 | sg = rotate_pages(page_addr_list, rot_info->plane[i].offset, | |
3544 | rot_info->plane[i].width, rot_info->plane[i].height, | |
3545 | rot_info->plane[i].stride, st, sg); | |
89e3e142 TU |
3546 | } |
3547 | ||
6687c906 VS |
3548 | DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n", |
3549 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
50470bb0 TU |
3550 | |
3551 | drm_free_large(page_addr_list); | |
3552 | ||
3553 | return st; | |
3554 | ||
3555 | err_sg_alloc: | |
3556 | kfree(st); | |
3557 | err_st_alloc: | |
3558 | drm_free_large(page_addr_list); | |
3559 | ||
6687c906 VS |
3560 | DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n", |
3561 | obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size); | |
3562 | ||
50470bb0 TU |
3563 | return ERR_PTR(ret); |
3564 | } | |
ec7adb6e | 3565 | |
8bd7ef16 JL |
3566 | static struct sg_table * |
3567 | intel_partial_pages(const struct i915_ggtt_view *view, | |
3568 | struct drm_i915_gem_object *obj) | |
3569 | { | |
3570 | struct sg_table *st; | |
3571 | struct scatterlist *sg; | |
3572 | struct sg_page_iter obj_sg_iter; | |
3573 | int ret = -ENOMEM; | |
3574 | ||
3575 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3576 | if (!st) | |
3577 | goto err_st_alloc; | |
3578 | ||
3579 | ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL); | |
3580 | if (ret) | |
3581 | goto err_sg_alloc; | |
3582 | ||
3583 | sg = st->sgl; | |
3584 | st->nents = 0; | |
3585 | for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents, | |
3586 | view->params.partial.offset) | |
3587 | { | |
3588 | if (st->nents >= view->params.partial.size) | |
3589 | break; | |
3590 | ||
3591 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
3592 | sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter); | |
3593 | sg_dma_len(sg) = PAGE_SIZE; | |
3594 | ||
3595 | sg = sg_next(sg); | |
3596 | st->nents++; | |
3597 | } | |
3598 | ||
3599 | return st; | |
3600 | ||
3601 | err_sg_alloc: | |
3602 | kfree(st); | |
3603 | err_st_alloc: | |
3604 | return ERR_PTR(ret); | |
3605 | } | |
3606 | ||
70b9f6f8 | 3607 | static int |
50470bb0 | 3608 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 3609 | { |
50470bb0 TU |
3610 | int ret = 0; |
3611 | ||
247177dd | 3612 | if (vma->pages) |
fe14d5f4 TU |
3613 | return 0; |
3614 | ||
3615 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
247177dd | 3616 | vma->pages = vma->obj->pages; |
50470bb0 | 3617 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
247177dd | 3618 | vma->pages = |
11d23e6f | 3619 | intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj); |
8bd7ef16 | 3620 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
247177dd | 3621 | vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj); |
fe14d5f4 TU |
3622 | else |
3623 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
3624 | vma->ggtt_view.type); | |
3625 | ||
247177dd | 3626 | if (!vma->pages) { |
ec7adb6e | 3627 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 3628 | vma->ggtt_view.type); |
50470bb0 | 3629 | ret = -EINVAL; |
247177dd CW |
3630 | } else if (IS_ERR(vma->pages)) { |
3631 | ret = PTR_ERR(vma->pages); | |
3632 | vma->pages = NULL; | |
50470bb0 TU |
3633 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", |
3634 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
3635 | } |
3636 | ||
50470bb0 | 3637 | return ret; |
fe14d5f4 TU |
3638 | } |
3639 | ||
3640 | /** | |
3641 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
3642 | * @vma: VMA to map | |
3643 | * @cache_level: mapping cache level | |
3644 | * @flags: flags like global or local mapping | |
3645 | * | |
3646 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
3647 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
3648 | * Note that DMA addresses are also the only part of the SG table we care about. | |
3649 | */ | |
3650 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
3651 | u32 flags) | |
3652 | { | |
75d04a37 | 3653 | u32 bind_flags; |
3272db53 CW |
3654 | u32 vma_flags; |
3655 | int ret; | |
1d335d1b | 3656 | |
75d04a37 MK |
3657 | if (WARN_ON(flags == 0)) |
3658 | return -EINVAL; | |
1d335d1b | 3659 | |
75d04a37 | 3660 | bind_flags = 0; |
0875546c | 3661 | if (flags & PIN_GLOBAL) |
3272db53 | 3662 | bind_flags |= I915_VMA_GLOBAL_BIND; |
0875546c | 3663 | if (flags & PIN_USER) |
3272db53 | 3664 | bind_flags |= I915_VMA_LOCAL_BIND; |
0875546c | 3665 | |
3272db53 | 3666 | vma_flags = vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND); |
0875546c | 3667 | if (flags & PIN_UPDATE) |
3272db53 | 3668 | bind_flags |= vma_flags; |
0875546c | 3669 | else |
3272db53 | 3670 | bind_flags &= ~vma_flags; |
75d04a37 MK |
3671 | if (bind_flags == 0) |
3672 | return 0; | |
3673 | ||
3272db53 | 3674 | if (vma_flags == 0 && vma->vm->allocate_va_range) { |
596c5923 | 3675 | trace_i915_va_alloc(vma); |
75d04a37 MK |
3676 | ret = vma->vm->allocate_va_range(vma->vm, |
3677 | vma->node.start, | |
3678 | vma->node.size); | |
3679 | if (ret) | |
3680 | return ret; | |
3681 | } | |
3682 | ||
3683 | ret = vma->vm->bind_vma(vma, cache_level, bind_flags); | |
70b9f6f8 DV |
3684 | if (ret) |
3685 | return ret; | |
0875546c | 3686 | |
3272db53 | 3687 | vma->flags |= bind_flags; |
fe14d5f4 TU |
3688 | return 0; |
3689 | } | |
91e6711e | 3690 | |
8ef8561f CW |
3691 | void __iomem *i915_vma_pin_iomap(struct i915_vma *vma) |
3692 | { | |
3693 | void __iomem *ptr; | |
3694 | ||
e5cdb22b CW |
3695 | /* Access through the GTT requires the device to be awake. */ |
3696 | assert_rpm_wakelock_held(to_i915(vma->vm->dev)); | |
3697 | ||
8ef8561f | 3698 | lockdep_assert_held(&vma->vm->dev->struct_mutex); |
05a20d09 | 3699 | if (WARN_ON(!i915_vma_is_map_and_fenceable(vma))) |
406ea8d2 | 3700 | return IO_ERR_PTR(-ENODEV); |
8ef8561f | 3701 | |
3272db53 CW |
3702 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); |
3703 | GEM_BUG_ON((vma->flags & I915_VMA_GLOBAL_BIND) == 0); | |
8ef8561f CW |
3704 | |
3705 | ptr = vma->iomap; | |
3706 | if (ptr == NULL) { | |
f7bbe788 | 3707 | ptr = io_mapping_map_wc(&i915_vm_to_ggtt(vma->vm)->mappable, |
8ef8561f CW |
3708 | vma->node.start, |
3709 | vma->node.size); | |
3710 | if (ptr == NULL) | |
406ea8d2 | 3711 | return IO_ERR_PTR(-ENOMEM); |
8ef8561f CW |
3712 | |
3713 | vma->iomap = ptr; | |
3714 | } | |
3715 | ||
20dfbde4 | 3716 | __i915_vma_pin(vma); |
8ef8561f CW |
3717 | return ptr; |
3718 | } | |
19880c4a CW |
3719 | |
3720 | void i915_vma_unpin_and_release(struct i915_vma **p_vma) | |
3721 | { | |
3722 | struct i915_vma *vma; | |
3723 | ||
3724 | vma = fetch_and_zero(p_vma); | |
3725 | if (!vma) | |
3726 | return; | |
3727 | ||
3728 | i915_vma_unpin(vma); | |
3729 | i915_vma_put(vma); | |
3730 | } |