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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 | 29 | #include "i915_drv.h" |
5dda8fa3 | 30 | #include "i915_vgpu.h" |
76aaf220 DV |
31 | #include "i915_trace.h" |
32 | #include "intel_drv.h" | |
33 | ||
45f8f69a TU |
34 | /** |
35 | * DOC: Global GTT views | |
36 | * | |
37 | * Background and previous state | |
38 | * | |
39 | * Historically objects could exists (be bound) in global GTT space only as | |
40 | * singular instances with a view representing all of the object's backing pages | |
41 | * in a linear fashion. This view will be called a normal view. | |
42 | * | |
43 | * To support multiple views of the same object, where the number of mapped | |
44 | * pages is not equal to the backing store, or where the layout of the pages | |
45 | * is not linear, concept of a GGTT view was added. | |
46 | * | |
47 | * One example of an alternative view is a stereo display driven by a single | |
48 | * image. In this case we would have a framebuffer looking like this | |
49 | * (2x2 pages): | |
50 | * | |
51 | * 12 | |
52 | * 34 | |
53 | * | |
54 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
55 | * rendering. In contrast, fed to the display engine would be an alternative | |
56 | * view which could look something like this: | |
57 | * | |
58 | * 1212 | |
59 | * 3434 | |
60 | * | |
61 | * In this example both the size and layout of pages in the alternative view is | |
62 | * different from the normal view. | |
63 | * | |
64 | * Implementation and usage | |
65 | * | |
66 | * GGTT views are implemented using VMAs and are distinguished via enum | |
67 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
68 | * | |
69 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
70 | * added with the _view suffix. They take the struct i915_ggtt_view parameter | |
71 | * encapsulating all metadata required to implement a view. | |
72 | * | |
73 | * As a helper for callers which are only interested in the normal view, | |
74 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
75 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
76 | * or with the normal GGTT view. | |
77 | * | |
78 | * Code wanting to add or use a new GGTT view needs to: | |
79 | * | |
80 | * 1. Add a new enum with a suitable name. | |
81 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
82 | * 3. Add support to i915_get_vma_pages(). | |
83 | * | |
84 | * New views are required to build a scatter-gather table from within the | |
85 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
86 | * exists for the lifetime of an VMA. | |
87 | * | |
88 | * Core API is designed to have copy semantics which means that passed in | |
89 | * struct i915_ggtt_view does not need to be persistent (left around after | |
90 | * calling the core API functions). | |
91 | * | |
92 | */ | |
93 | ||
fe14d5f4 TU |
94 | const struct i915_ggtt_view i915_ggtt_view_normal; |
95 | ||
ee0ce478 VS |
96 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); |
97 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); | |
a2319c08 | 98 | |
cfa7c862 DV |
99 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
100 | { | |
1893a71b CW |
101 | bool has_aliasing_ppgtt; |
102 | bool has_full_ppgtt; | |
103 | ||
104 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
105 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
1893a71b | 106 | |
71ba2d64 YZ |
107 | if (intel_vgpu_active(dev)) |
108 | has_full_ppgtt = false; /* emulation is too hard */ | |
109 | ||
70ee45e1 DL |
110 | /* |
111 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
112 | * execlists, the sole mechanism available to submit work. | |
113 | */ | |
114 | if (INTEL_INFO(dev)->gen < 9 && | |
115 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) | |
cfa7c862 DV |
116 | return 0; |
117 | ||
118 | if (enable_ppgtt == 1) | |
119 | return 1; | |
120 | ||
1893a71b | 121 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
122 | return 2; |
123 | ||
93a25a9e DV |
124 | #ifdef CONFIG_INTEL_IOMMU |
125 | /* Disable ppgtt on SNB if VT-d is on. */ | |
126 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
127 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 128 | return 0; |
93a25a9e DV |
129 | } |
130 | #endif | |
131 | ||
62942ed7 | 132 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
133 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
134 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
135 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
136 | return 0; | |
137 | } | |
138 | ||
2f82bbdf MT |
139 | if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) |
140 | return 2; | |
141 | else | |
142 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
143 | } |
144 | ||
fbe5d36e | 145 | |
6f65e29a BW |
146 | static void ppgtt_bind_vma(struct i915_vma *vma, |
147 | enum i915_cache_level cache_level, | |
148 | u32 flags); | |
149 | static void ppgtt_unbind_vma(struct i915_vma *vma); | |
150 | ||
94ec8f61 BW |
151 | static inline gen8_gtt_pte_t gen8_pte_encode(dma_addr_t addr, |
152 | enum i915_cache_level level, | |
153 | bool valid) | |
154 | { | |
155 | gen8_gtt_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; | |
156 | pte |= addr; | |
63c42e56 BW |
157 | |
158 | switch (level) { | |
159 | case I915_CACHE_NONE: | |
fbe5d36e | 160 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
161 | break; |
162 | case I915_CACHE_WT: | |
163 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
164 | break; | |
165 | default: | |
166 | pte |= PPAT_CACHED_INDEX; | |
167 | break; | |
168 | } | |
169 | ||
94ec8f61 BW |
170 | return pte; |
171 | } | |
172 | ||
b1fe6673 BW |
173 | static inline gen8_ppgtt_pde_t gen8_pde_encode(struct drm_device *dev, |
174 | dma_addr_t addr, | |
175 | enum i915_cache_level level) | |
176 | { | |
177 | gen8_ppgtt_pde_t pde = _PAGE_PRESENT | _PAGE_RW; | |
178 | pde |= addr; | |
179 | if (level != I915_CACHE_NONE) | |
180 | pde |= PPAT_CACHED_PDE_INDEX; | |
181 | else | |
182 | pde |= PPAT_UNCACHED_INDEX; | |
183 | return pde; | |
184 | } | |
185 | ||
350ec881 | 186 | static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr, |
b35b380e | 187 | enum i915_cache_level level, |
24f3a8cf | 188 | bool valid, u32 unused) |
54d12527 | 189 | { |
b35b380e | 190 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 191 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
192 | |
193 | switch (level) { | |
350ec881 CW |
194 | case I915_CACHE_L3_LLC: |
195 | case I915_CACHE_LLC: | |
196 | pte |= GEN6_PTE_CACHE_LLC; | |
197 | break; | |
198 | case I915_CACHE_NONE: | |
199 | pte |= GEN6_PTE_UNCACHED; | |
200 | break; | |
201 | default: | |
5f77eeb0 | 202 | MISSING_CASE(level); |
350ec881 CW |
203 | } |
204 | ||
205 | return pte; | |
206 | } | |
207 | ||
208 | static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr, | |
b35b380e | 209 | enum i915_cache_level level, |
24f3a8cf | 210 | bool valid, u32 unused) |
350ec881 | 211 | { |
b35b380e | 212 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
213 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
214 | ||
215 | switch (level) { | |
216 | case I915_CACHE_L3_LLC: | |
217 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
218 | break; |
219 | case I915_CACHE_LLC: | |
220 | pte |= GEN6_PTE_CACHE_LLC; | |
221 | break; | |
222 | case I915_CACHE_NONE: | |
9119708c | 223 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
224 | break; |
225 | default: | |
5f77eeb0 | 226 | MISSING_CASE(level); |
e7210c3c BW |
227 | } |
228 | ||
54d12527 BW |
229 | return pte; |
230 | } | |
231 | ||
80a74f7f | 232 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
b35b380e | 233 | enum i915_cache_level level, |
24f3a8cf | 234 | bool valid, u32 flags) |
93c34e70 | 235 | { |
b35b380e | 236 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
237 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
238 | ||
24f3a8cf AG |
239 | if (!(flags & PTE_READ_ONLY)) |
240 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
241 | |
242 | if (level != I915_CACHE_NONE) | |
243 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
244 | ||
245 | return pte; | |
246 | } | |
247 | ||
80a74f7f | 248 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
b35b380e | 249 | enum i915_cache_level level, |
24f3a8cf | 250 | bool valid, u32 unused) |
9119708c | 251 | { |
b35b380e | 252 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 253 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
254 | |
255 | if (level != I915_CACHE_NONE) | |
87a6b688 | 256 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
257 | |
258 | return pte; | |
259 | } | |
260 | ||
4d15c145 | 261 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
b35b380e | 262 | enum i915_cache_level level, |
24f3a8cf | 263 | bool valid, u32 unused) |
4d15c145 | 264 | { |
b35b380e | 265 | gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
266 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
267 | ||
651d794f CW |
268 | switch (level) { |
269 | case I915_CACHE_NONE: | |
270 | break; | |
271 | case I915_CACHE_WT: | |
c51e9701 | 272 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
273 | break; |
274 | default: | |
c51e9701 | 275 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
276 | break; |
277 | } | |
4d15c145 BW |
278 | |
279 | return pte; | |
280 | } | |
281 | ||
94e409c1 | 282 | /* Broadwell Page Directory Pointer Descriptors */ |
a4872ba6 | 283 | static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, |
6689c167 | 284 | uint64_t val) |
94e409c1 BW |
285 | { |
286 | int ret; | |
287 | ||
288 | BUG_ON(entry >= 4); | |
289 | ||
290 | ret = intel_ring_begin(ring, 6); | |
291 | if (ret) | |
292 | return ret; | |
293 | ||
294 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
295 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
296 | intel_ring_emit(ring, (u32)(val >> 32)); | |
297 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
298 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
299 | intel_ring_emit(ring, (u32)(val)); | |
300 | intel_ring_advance(ring); | |
301 | ||
302 | return 0; | |
303 | } | |
304 | ||
eeb9488e | 305 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 306 | struct intel_engine_cs *ring) |
94e409c1 | 307 | { |
eeb9488e | 308 | int i, ret; |
94e409c1 BW |
309 | |
310 | /* bit of a hack to find the actual last used pd */ | |
311 | int used_pd = ppgtt->num_pd_entries / GEN8_PDES_PER_PAGE; | |
312 | ||
94e409c1 | 313 | for (i = used_pd - 1; i >= 0; i--) { |
7324cc04 | 314 | dma_addr_t addr = ppgtt->pdp.page_directory[i].daddr; |
6689c167 | 315 | ret = gen8_write_pdp(ring, i, addr); |
eeb9488e BW |
316 | if (ret) |
317 | return ret; | |
94e409c1 | 318 | } |
d595bd4b | 319 | |
eeb9488e | 320 | return 0; |
94e409c1 BW |
321 | } |
322 | ||
459108b8 | 323 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
324 | uint64_t start, |
325 | uint64_t length, | |
459108b8 BW |
326 | bool use_scratch) |
327 | { | |
328 | struct i915_hw_ppgtt *ppgtt = | |
329 | container_of(vm, struct i915_hw_ppgtt, base); | |
330 | gen8_gtt_pte_t *pt_vaddr, scratch_pte; | |
7ad47cf2 BW |
331 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
332 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
333 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 334 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
335 | unsigned last_pte, i; |
336 | ||
337 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
338 | I915_CACHE_LLC, use_scratch); | |
339 | ||
340 | while (num_entries) { | |
d7b3de91 BW |
341 | struct i915_page_directory_entry *pd = &ppgtt->pdp.page_directory[pdpe]; |
342 | struct page *page_table = pd->page_table[pde].page; | |
459108b8 | 343 | |
7ad47cf2 | 344 | last_pte = pte + num_entries; |
459108b8 BW |
345 | if (last_pte > GEN8_PTES_PER_PAGE) |
346 | last_pte = GEN8_PTES_PER_PAGE; | |
347 | ||
348 | pt_vaddr = kmap_atomic(page_table); | |
349 | ||
7ad47cf2 | 350 | for (i = pte; i < last_pte; i++) { |
459108b8 | 351 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
352 | num_entries--; |
353 | } | |
459108b8 | 354 | |
fd1ab8f4 RB |
355 | if (!HAS_LLC(ppgtt->base.dev)) |
356 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
459108b8 BW |
357 | kunmap_atomic(pt_vaddr); |
358 | ||
7ad47cf2 BW |
359 | pte = 0; |
360 | if (++pde == GEN8_PDES_PER_PAGE) { | |
361 | pdpe++; | |
362 | pde = 0; | |
363 | } | |
459108b8 BW |
364 | } |
365 | } | |
366 | ||
9df15b49 BW |
367 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
368 | struct sg_table *pages, | |
782f1495 | 369 | uint64_t start, |
24f3a8cf | 370 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
371 | { |
372 | struct i915_hw_ppgtt *ppgtt = | |
373 | container_of(vm, struct i915_hw_ppgtt, base); | |
374 | gen8_gtt_pte_t *pt_vaddr; | |
7ad47cf2 BW |
375 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
376 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
377 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
378 | struct sg_page_iter sg_iter; |
379 | ||
6f1cc993 | 380 | pt_vaddr = NULL; |
7ad47cf2 | 381 | |
9df15b49 | 382 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
76643600 | 383 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) |
7ad47cf2 BW |
384 | break; |
385 | ||
d7b3de91 BW |
386 | if (pt_vaddr == NULL) { |
387 | struct i915_page_directory_entry *pd = &ppgtt->pdp.page_directory[pdpe]; | |
388 | struct page *page_table = pd->page_table[pde].page; | |
389 | ||
390 | pt_vaddr = kmap_atomic(page_table); | |
391 | } | |
9df15b49 | 392 | |
7ad47cf2 | 393 | pt_vaddr[pte] = |
6f1cc993 CW |
394 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
395 | cache_level, true); | |
7ad47cf2 | 396 | if (++pte == GEN8_PTES_PER_PAGE) { |
fd1ab8f4 RB |
397 | if (!HAS_LLC(ppgtt->base.dev)) |
398 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
9df15b49 | 399 | kunmap_atomic(pt_vaddr); |
6f1cc993 | 400 | pt_vaddr = NULL; |
7ad47cf2 BW |
401 | if (++pde == GEN8_PDES_PER_PAGE) { |
402 | pdpe++; | |
403 | pde = 0; | |
404 | } | |
405 | pte = 0; | |
9df15b49 BW |
406 | } |
407 | } | |
fd1ab8f4 RB |
408 | if (pt_vaddr) { |
409 | if (!HAS_LLC(ppgtt->base.dev)) | |
410 | drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); | |
6f1cc993 | 411 | kunmap_atomic(pt_vaddr); |
fd1ab8f4 | 412 | } |
9df15b49 BW |
413 | } |
414 | ||
d7b3de91 | 415 | static void gen8_free_page_tables(struct i915_page_directory_entry *pd) |
7ad47cf2 BW |
416 | { |
417 | int i; | |
418 | ||
d7b3de91 | 419 | if (pd->page_table == NULL) |
7ad47cf2 BW |
420 | return; |
421 | ||
422 | for (i = 0; i < GEN8_PDES_PER_PAGE; i++) | |
d7b3de91 BW |
423 | if (pd->page_table[i].page) |
424 | __free_page(pd->page_table[i].page); | |
7ad47cf2 BW |
425 | } |
426 | ||
d7b3de91 BW |
427 | static void gen8_free_page_directory(struct i915_page_directory_entry *pd) |
428 | { | |
429 | gen8_free_page_tables(pd); | |
430 | kfree(pd->page_table); | |
431 | __free_page(pd->page); | |
432 | } | |
433 | ||
434 | static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) | |
b45a6715 BW |
435 | { |
436 | int i; | |
437 | ||
7ad47cf2 | 438 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
d7b3de91 | 439 | gen8_free_page_directory(&ppgtt->pdp.page_directory[i]); |
7ad47cf2 | 440 | } |
b45a6715 BW |
441 | } |
442 | ||
443 | static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) | |
444 | { | |
f3a964b9 | 445 | struct pci_dev *hwdev = ppgtt->base.dev->pdev; |
b45a6715 BW |
446 | int i, j; |
447 | ||
448 | for (i = 0; i < ppgtt->num_pd_pages; i++) { | |
449 | /* TODO: In the future we'll support sparse mappings, so this | |
450 | * will have to change. */ | |
7324cc04 | 451 | if (!ppgtt->pdp.page_directory[i].daddr) |
b45a6715 BW |
452 | continue; |
453 | ||
7324cc04 | 454 | pci_unmap_page(hwdev, ppgtt->pdp.page_directory[i].daddr, PAGE_SIZE, |
f3a964b9 | 455 | PCI_DMA_BIDIRECTIONAL); |
b45a6715 BW |
456 | |
457 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { | |
7324cc04 | 458 | dma_addr_t addr = ppgtt->pdp.page_directory[i].page_table[j].daddr; |
b45a6715 | 459 | if (addr) |
f3a964b9 BW |
460 | pci_unmap_page(hwdev, addr, PAGE_SIZE, |
461 | PCI_DMA_BIDIRECTIONAL); | |
b45a6715 BW |
462 | } |
463 | } | |
464 | } | |
465 | ||
37aca44a BW |
466 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
467 | { | |
468 | struct i915_hw_ppgtt *ppgtt = | |
469 | container_of(vm, struct i915_hw_ppgtt, base); | |
37aca44a | 470 | |
b45a6715 BW |
471 | gen8_ppgtt_unmap_pages(ppgtt); |
472 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
473 | } |
474 | ||
d7b3de91 | 475 | static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) |
bf2b4ed2 | 476 | { |
d7b3de91 | 477 | int i, j; |
bf2b4ed2 | 478 | |
d7b3de91 | 479 | for (i = 0; i < ppgtt->num_pd_pages; i++) { |
7324cc04 | 480 | struct i915_page_directory_entry *pd = &ppgtt->pdp.page_directory[i]; |
d7b3de91 | 481 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
7324cc04 | 482 | struct i915_page_table_entry *pt = &pd->page_table[j]; |
d7b3de91 BW |
483 | |
484 | pt->page = alloc_page(GFP_KERNEL | __GFP_ZERO); | |
485 | if (!pt->page) | |
486 | goto unwind_out; | |
7324cc04 | 487 | |
7ad47cf2 BW |
488 | } |
489 | } | |
490 | ||
bf2b4ed2 | 491 | return 0; |
7ad47cf2 BW |
492 | |
493 | unwind_out: | |
d7b3de91 BW |
494 | while (i--) |
495 | gen8_free_page_tables(&ppgtt->pdp.page_directory[i]); | |
7ad47cf2 | 496 | |
d7b3de91 | 497 | return -ENOMEM; |
bf2b4ed2 BW |
498 | } |
499 | ||
d7b3de91 BW |
500 | static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, |
501 | const int max_pdp) | |
bf2b4ed2 BW |
502 | { |
503 | int i; | |
504 | ||
d7b3de91 BW |
505 | for (i = 0; i < max_pdp; i++) { |
506 | struct i915_page_table_entry *pt; | |
bf2b4ed2 | 507 | |
d7b3de91 BW |
508 | pt = kcalloc(GEN8_PDES_PER_PAGE, sizeof(*pt), GFP_KERNEL); |
509 | if (!pt) | |
510 | goto unwind_out; | |
bf2b4ed2 | 511 | |
d7b3de91 BW |
512 | ppgtt->pdp.page_directory[i].page = alloc_page(GFP_KERNEL); |
513 | if (!ppgtt->pdp.page_directory[i].page) { | |
514 | kfree(pt); | |
515 | goto unwind_out; | |
516 | } | |
bf2b4ed2 | 517 | |
d7b3de91 BW |
518 | ppgtt->pdp.page_directory[i].page_table = pt; |
519 | } | |
520 | ||
521 | ppgtt->num_pd_pages = max_pdp; | |
76643600 | 522 | BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPES); |
bf2b4ed2 BW |
523 | |
524 | return 0; | |
d7b3de91 BW |
525 | |
526 | unwind_out: | |
527 | while (i--) { | |
528 | kfree(ppgtt->pdp.page_directory[i].page_table); | |
529 | __free_page(ppgtt->pdp.page_directory[i].page); | |
530 | } | |
531 | ||
532 | return -ENOMEM; | |
bf2b4ed2 BW |
533 | } |
534 | ||
535 | static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, | |
536 | const int max_pdp) | |
537 | { | |
538 | int ret; | |
539 | ||
540 | ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); | |
541 | if (ret) | |
542 | return ret; | |
543 | ||
d7b3de91 BW |
544 | ret = gen8_ppgtt_allocate_page_tables(ppgtt); |
545 | if (ret) | |
546 | goto err_out; | |
bf2b4ed2 BW |
547 | |
548 | ppgtt->num_pd_entries = max_pdp * GEN8_PDES_PER_PAGE; | |
549 | ||
d7b3de91 | 550 | return 0; |
bf2b4ed2 | 551 | |
d7b3de91 BW |
552 | err_out: |
553 | gen8_ppgtt_free(ppgtt); | |
bf2b4ed2 BW |
554 | return ret; |
555 | } | |
556 | ||
557 | static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, | |
558 | const int pd) | |
559 | { | |
560 | dma_addr_t pd_addr; | |
561 | int ret; | |
562 | ||
563 | pd_addr = pci_map_page(ppgtt->base.dev->pdev, | |
d7b3de91 | 564 | ppgtt->pdp.page_directory[pd].page, 0, |
bf2b4ed2 BW |
565 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
566 | ||
567 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); | |
568 | if (ret) | |
569 | return ret; | |
570 | ||
7324cc04 | 571 | ppgtt->pdp.page_directory[pd].daddr = pd_addr; |
bf2b4ed2 BW |
572 | |
573 | return 0; | |
574 | } | |
575 | ||
576 | static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, | |
577 | const int pd, | |
578 | const int pt) | |
579 | { | |
580 | dma_addr_t pt_addr; | |
7324cc04 BW |
581 | struct i915_page_directory_entry *pdir = &ppgtt->pdp.page_directory[pd]; |
582 | struct i915_page_table_entry *ptab = &pdir->page_table[pt]; | |
583 | struct page *p = ptab->page; | |
bf2b4ed2 BW |
584 | int ret; |
585 | ||
bf2b4ed2 BW |
586 | pt_addr = pci_map_page(ppgtt->base.dev->pdev, |
587 | p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); | |
588 | ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); | |
589 | if (ret) | |
590 | return ret; | |
591 | ||
7324cc04 | 592 | ptab->daddr = pt_addr; |
bf2b4ed2 BW |
593 | |
594 | return 0; | |
595 | } | |
596 | ||
37aca44a | 597 | /** |
f3a964b9 BW |
598 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
599 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
600 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
601 | * space. | |
37aca44a | 602 | * |
f3a964b9 BW |
603 | * FIXME: split allocation into smaller pieces. For now we only ever do this |
604 | * once, but with full PPGTT, the multiple contiguous allocations will be bad. | |
37aca44a | 605 | * TODO: Do something with the size parameter |
f3a964b9 | 606 | */ |
37aca44a BW |
607 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) |
608 | { | |
37aca44a | 609 | const int max_pdp = DIV_ROUND_UP(size, 1 << 30); |
bf2b4ed2 | 610 | const int min_pt_pages = GEN8_PDES_PER_PAGE * max_pdp; |
f3a964b9 | 611 | int i, j, ret; |
37aca44a BW |
612 | |
613 | if (size % (1<<30)) | |
614 | DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); | |
615 | ||
bf2b4ed2 BW |
616 | /* 1. Do all our allocations for page directories and page tables. */ |
617 | ret = gen8_ppgtt_alloc(ppgtt, max_pdp); | |
618 | if (ret) | |
619 | return ret; | |
f3a964b9 | 620 | |
37aca44a | 621 | /* |
bf2b4ed2 | 622 | * 2. Create DMA mappings for the page directories and page tables. |
37aca44a BW |
623 | */ |
624 | for (i = 0; i < max_pdp; i++) { | |
bf2b4ed2 | 625 | ret = gen8_ppgtt_setup_page_directories(ppgtt, i); |
f3a964b9 BW |
626 | if (ret) |
627 | goto bail; | |
37aca44a | 628 | |
37aca44a | 629 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
bf2b4ed2 | 630 | ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); |
f3a964b9 BW |
631 | if (ret) |
632 | goto bail; | |
37aca44a BW |
633 | } |
634 | } | |
635 | ||
f3a964b9 BW |
636 | /* |
637 | * 3. Map all the page directory entires to point to the page tables | |
638 | * we've allocated. | |
639 | * | |
640 | * For now, the PPGTT helper functions all require that the PDEs are | |
b1fe6673 | 641 | * plugged in correctly. So we do that now/here. For aliasing PPGTT, we |
f3a964b9 BW |
642 | * will never need to touch the PDEs again. |
643 | */ | |
b1fe6673 BW |
644 | for (i = 0; i < max_pdp; i++) { |
645 | gen8_ppgtt_pde_t *pd_vaddr; | |
d7b3de91 | 646 | pd_vaddr = kmap_atomic(ppgtt->pdp.page_directory[i].page); |
b1fe6673 | 647 | for (j = 0; j < GEN8_PDES_PER_PAGE; j++) { |
7324cc04 | 648 | dma_addr_t addr = ppgtt->pdp.page_directory[i].page_table[j].daddr; |
b1fe6673 BW |
649 | pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, |
650 | I915_CACHE_LLC); | |
651 | } | |
fd1ab8f4 RB |
652 | if (!HAS_LLC(ppgtt->base.dev)) |
653 | drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); | |
b1fe6673 BW |
654 | kunmap_atomic(pd_vaddr); |
655 | } | |
656 | ||
f3a964b9 BW |
657 | ppgtt->switch_mm = gen8_mm_switch; |
658 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; | |
659 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; | |
660 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; | |
661 | ppgtt->base.start = 0; | |
5abbcca3 | 662 | ppgtt->base.total = ppgtt->num_pd_entries * GEN8_PTES_PER_PAGE * PAGE_SIZE; |
f3a964b9 | 663 | |
5abbcca3 | 664 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
459108b8 | 665 | |
37aca44a BW |
666 | DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", |
667 | ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); | |
668 | DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", | |
5abbcca3 BW |
669 | ppgtt->num_pd_entries, |
670 | (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); | |
28cf5415 | 671 | return 0; |
37aca44a | 672 | |
f3a964b9 BW |
673 | bail: |
674 | gen8_ppgtt_unmap_pages(ppgtt); | |
675 | gen8_ppgtt_free(ppgtt); | |
37aca44a BW |
676 | return ret; |
677 | } | |
678 | ||
87d60b63 BW |
679 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
680 | { | |
681 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; | |
682 | struct i915_address_space *vm = &ppgtt->base; | |
683 | gen6_gtt_pte_t __iomem *pd_addr; | |
684 | gen6_gtt_pte_t scratch_pte; | |
685 | uint32_t pd_entry; | |
686 | int pte, pde; | |
687 | ||
24f3a8cf | 688 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
87d60b63 BW |
689 | |
690 | pd_addr = (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + | |
7324cc04 | 691 | ppgtt->pd.pd_offset / sizeof(gen6_gtt_pte_t); |
87d60b63 BW |
692 | |
693 | seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, | |
7324cc04 BW |
694 | ppgtt->pd.pd_offset, |
695 | ppgtt->pd.pd_offset + ppgtt->num_pd_entries); | |
87d60b63 BW |
696 | for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { |
697 | u32 expected; | |
698 | gen6_gtt_pte_t *pt_vaddr; | |
7324cc04 | 699 | dma_addr_t pt_addr = ppgtt->pd.page_table[pde].daddr; |
87d60b63 BW |
700 | pd_entry = readl(pd_addr + pde); |
701 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); | |
702 | ||
703 | if (pd_entry != expected) | |
704 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
705 | pde, | |
706 | pd_entry, | |
707 | expected); | |
708 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
709 | ||
d7b3de91 | 710 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde].page); |
87d60b63 BW |
711 | for (pte = 0; pte < I915_PPGTT_PT_ENTRIES; pte+=4) { |
712 | unsigned long va = | |
713 | (pde * PAGE_SIZE * I915_PPGTT_PT_ENTRIES) + | |
714 | (pte * PAGE_SIZE); | |
715 | int i; | |
716 | bool found = false; | |
717 | for (i = 0; i < 4; i++) | |
718 | if (pt_vaddr[pte + i] != scratch_pte) | |
719 | found = true; | |
720 | if (!found) | |
721 | continue; | |
722 | ||
723 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
724 | for (i = 0; i < 4; i++) { | |
725 | if (pt_vaddr[pte + i] != scratch_pte) | |
726 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
727 | else | |
728 | seq_puts(m, " SCRATCH "); | |
729 | } | |
730 | seq_puts(m, "\n"); | |
731 | } | |
732 | kunmap_atomic(pt_vaddr); | |
733 | } | |
734 | } | |
735 | ||
3e302542 | 736 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 737 | { |
853ba5d2 | 738 | struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; |
6197349b BW |
739 | gen6_gtt_pte_t __iomem *pd_addr; |
740 | uint32_t pd_entry; | |
741 | int i; | |
742 | ||
7324cc04 | 743 | WARN_ON(ppgtt->pd.pd_offset & 0x3f); |
6197349b | 744 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
7324cc04 | 745 | ppgtt->pd.pd_offset / sizeof(gen6_gtt_pte_t); |
6197349b BW |
746 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
747 | dma_addr_t pt_addr; | |
748 | ||
7324cc04 | 749 | pt_addr = ppgtt->pd.page_table[i].daddr; |
6197349b BW |
750 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); |
751 | pd_entry |= GEN6_PDE_VALID; | |
752 | ||
753 | writel(pd_entry, pd_addr + i); | |
754 | } | |
755 | readl(pd_addr); | |
3e302542 BW |
756 | } |
757 | ||
b4a74e3a | 758 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 759 | { |
7324cc04 | 760 | BUG_ON(ppgtt->pd.pd_offset & 0x3f); |
b4a74e3a | 761 | |
7324cc04 | 762 | return (ppgtt->pd.pd_offset / 64) << 16; |
b4a74e3a BW |
763 | } |
764 | ||
90252e5c | 765 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 766 | struct intel_engine_cs *ring) |
90252e5c | 767 | { |
90252e5c BW |
768 | int ret; |
769 | ||
90252e5c BW |
770 | /* NB: TLBs must be flushed and invalidated before a switch */ |
771 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
772 | if (ret) | |
773 | return ret; | |
774 | ||
775 | ret = intel_ring_begin(ring, 6); | |
776 | if (ret) | |
777 | return ret; | |
778 | ||
779 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
780 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
781 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
782 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
783 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
784 | intel_ring_emit(ring, MI_NOOP); | |
785 | intel_ring_advance(ring); | |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
71ba2d64 YZ |
790 | static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, |
791 | struct intel_engine_cs *ring) | |
792 | { | |
793 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); | |
794 | ||
795 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
796 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
797 | return 0; | |
798 | } | |
799 | ||
48a10389 | 800 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 801 | struct intel_engine_cs *ring) |
48a10389 | 802 | { |
48a10389 BW |
803 | int ret; |
804 | ||
48a10389 BW |
805 | /* NB: TLBs must be flushed and invalidated before a switch */ |
806 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
807 | if (ret) | |
808 | return ret; | |
809 | ||
810 | ret = intel_ring_begin(ring, 6); | |
811 | if (ret) | |
812 | return ret; | |
813 | ||
814 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
815 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
816 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
817 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
818 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
819 | intel_ring_emit(ring, MI_NOOP); | |
820 | intel_ring_advance(ring); | |
821 | ||
90252e5c BW |
822 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
823 | if (ring->id != RCS) { | |
824 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
825 | if (ret) | |
826 | return ret; | |
827 | } | |
828 | ||
48a10389 BW |
829 | return 0; |
830 | } | |
831 | ||
eeb9488e | 832 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
6689c167 | 833 | struct intel_engine_cs *ring) |
eeb9488e BW |
834 | { |
835 | struct drm_device *dev = ppgtt->base.dev; | |
836 | struct drm_i915_private *dev_priv = dev->dev_private; | |
837 | ||
48a10389 | 838 | |
eeb9488e BW |
839 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
840 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
841 | ||
842 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
82460d97 | 847 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 848 | { |
eeb9488e | 849 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 850 | struct intel_engine_cs *ring; |
82460d97 | 851 | int j; |
3e302542 | 852 | |
eeb9488e BW |
853 | for_each_ring(ring, dev_priv, j) { |
854 | I915_WRITE(RING_MODE_GEN7(ring), | |
855 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 856 | } |
eeb9488e | 857 | } |
6197349b | 858 | |
82460d97 | 859 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 860 | { |
50227e1c | 861 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 862 | struct intel_engine_cs *ring; |
b4a74e3a | 863 | uint32_t ecochk, ecobits; |
3e302542 | 864 | int i; |
6197349b | 865 | |
b4a74e3a BW |
866 | ecobits = I915_READ(GAC_ECO_BITS); |
867 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 868 | |
b4a74e3a BW |
869 | ecochk = I915_READ(GAM_ECOCHK); |
870 | if (IS_HASWELL(dev)) { | |
871 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
872 | } else { | |
873 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
874 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
875 | } | |
876 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 877 | |
b4a74e3a | 878 | for_each_ring(ring, dev_priv, i) { |
6197349b | 879 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
880 | I915_WRITE(RING_MODE_GEN7(ring), |
881 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 882 | } |
b4a74e3a | 883 | } |
6197349b | 884 | |
82460d97 | 885 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 886 | { |
50227e1c | 887 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 888 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 889 | |
b4a74e3a BW |
890 | ecobits = I915_READ(GAC_ECO_BITS); |
891 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
892 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 893 | |
b4a74e3a BW |
894 | gab_ctl = I915_READ(GAB_CTL); |
895 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
896 | ||
897 | ecochk = I915_READ(GAM_ECOCHK); | |
898 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
899 | ||
900 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
901 | } |
902 | ||
1d2a314c | 903 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 904 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
905 | uint64_t start, |
906 | uint64_t length, | |
828c7908 | 907 | bool use_scratch) |
1d2a314c | 908 | { |
853ba5d2 BW |
909 | struct i915_hw_ppgtt *ppgtt = |
910 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 911 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
912 | unsigned first_entry = start >> PAGE_SHIFT; |
913 | unsigned num_entries = length >> PAGE_SHIFT; | |
a15326a5 | 914 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
915 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
916 | unsigned last_pte, i; | |
1d2a314c | 917 | |
24f3a8cf | 918 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
1d2a314c | 919 | |
7bddb01f DV |
920 | while (num_entries) { |
921 | last_pte = first_pte + num_entries; | |
922 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
923 | last_pte = I915_PPGTT_PT_ENTRIES; | |
924 | ||
d7b3de91 | 925 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt].page); |
1d2a314c | 926 | |
7bddb01f DV |
927 | for (i = first_pte; i < last_pte; i++) |
928 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
929 | |
930 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 931 | |
7bddb01f DV |
932 | num_entries -= last_pte - first_pte; |
933 | first_pte = 0; | |
a15326a5 | 934 | act_pt++; |
7bddb01f | 935 | } |
1d2a314c DV |
936 | } |
937 | ||
853ba5d2 | 938 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 939 | struct sg_table *pages, |
782f1495 | 940 | uint64_t start, |
24f3a8cf | 941 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 942 | { |
853ba5d2 BW |
943 | struct i915_hw_ppgtt *ppgtt = |
944 | container_of(vm, struct i915_hw_ppgtt, base); | |
e7c2b58b | 945 | gen6_gtt_pte_t *pt_vaddr; |
782f1495 | 946 | unsigned first_entry = start >> PAGE_SHIFT; |
a15326a5 | 947 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
948 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
949 | struct sg_page_iter sg_iter; | |
950 | ||
cc79714f | 951 | pt_vaddr = NULL; |
6e995e23 | 952 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f | 953 | if (pt_vaddr == NULL) |
d7b3de91 | 954 | pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt].page); |
6e995e23 | 955 | |
cc79714f CW |
956 | pt_vaddr[act_pte] = |
957 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
958 | cache_level, true, flags); |
959 | ||
6e995e23 ID |
960 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
961 | kunmap_atomic(pt_vaddr); | |
cc79714f | 962 | pt_vaddr = NULL; |
a15326a5 | 963 | act_pt++; |
6e995e23 | 964 | act_pte = 0; |
def886c3 | 965 | } |
def886c3 | 966 | } |
cc79714f CW |
967 | if (pt_vaddr) |
968 | kunmap_atomic(pt_vaddr); | |
def886c3 DV |
969 | } |
970 | ||
a00d825d | 971 | static void gen6_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 972 | { |
3440d265 DV |
973 | int i; |
974 | ||
7324cc04 BW |
975 | for (i = 0; i < ppgtt->num_pd_entries; i++) |
976 | pci_unmap_page(ppgtt->base.dev->pdev, | |
977 | ppgtt->pd.page_table[i].daddr, | |
978 | 4096, PCI_DMA_BIDIRECTIONAL); | |
a00d825d BW |
979 | } |
980 | ||
981 | static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) | |
982 | { | |
983 | int i; | |
3440d265 | 984 | |
3440d265 | 985 | for (i = 0; i < ppgtt->num_pd_entries; i++) |
d7b3de91 BW |
986 | if (ppgtt->pd.page_table[i].page) |
987 | __free_page(ppgtt->pd.page_table[i].page); | |
988 | kfree(ppgtt->pd.page_table); | |
3440d265 DV |
989 | } |
990 | ||
a00d825d BW |
991 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
992 | { | |
993 | struct i915_hw_ppgtt *ppgtt = | |
994 | container_of(vm, struct i915_hw_ppgtt, base); | |
995 | ||
a00d825d BW |
996 | drm_mm_remove_node(&ppgtt->node); |
997 | ||
998 | gen6_ppgtt_unmap_pages(ppgtt); | |
999 | gen6_ppgtt_free(ppgtt); | |
1000 | } | |
1001 | ||
b146520f | 1002 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1003 | { |
853ba5d2 | 1004 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1005 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1006 | bool retried = false; |
b146520f | 1007 | int ret; |
1d2a314c | 1008 | |
c8d4c0d6 BW |
1009 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1010 | * allocator works in address space sizes, so it's multiplied by page | |
1011 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1012 | */ | |
1013 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
e3cc1995 | 1014 | alloc: |
c8d4c0d6 BW |
1015 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1016 | &ppgtt->node, GEN6_PD_SIZE, | |
1017 | GEN6_PD_ALIGN, 0, | |
1018 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1019 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1020 | if (ret == -ENOSPC && !retried) { |
1021 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1022 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1023 | I915_CACHE_NONE, |
1024 | 0, dev_priv->gtt.base.total, | |
1025 | 0); | |
e3cc1995 BW |
1026 | if (ret) |
1027 | return ret; | |
1028 | ||
1029 | retried = true; | |
1030 | goto alloc; | |
1031 | } | |
c8d4c0d6 | 1032 | |
c8c26622 BW |
1033 | if (ret) |
1034 | return ret; | |
1035 | ||
c8d4c0d6 BW |
1036 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
1037 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1038 | |
6670a5a5 | 1039 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
c8c26622 | 1040 | return 0; |
b146520f BW |
1041 | } |
1042 | ||
1043 | static int gen6_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1044 | { | |
d7b3de91 | 1045 | struct i915_page_table_entry *pt; |
b146520f BW |
1046 | int i; |
1047 | ||
d7b3de91 BW |
1048 | pt = kcalloc(ppgtt->num_pd_entries, sizeof(*pt), GFP_KERNEL); |
1049 | if (!pt) | |
3440d265 | 1050 | return -ENOMEM; |
1d2a314c | 1051 | |
d7b3de91 BW |
1052 | ppgtt->pd.page_table = pt; |
1053 | ||
1d2a314c | 1054 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
d7b3de91 BW |
1055 | pt[i].page = alloc_page(GFP_KERNEL); |
1056 | if (!pt->page) { | |
b146520f BW |
1057 | gen6_ppgtt_free(ppgtt); |
1058 | return -ENOMEM; | |
1059 | } | |
1060 | } | |
1061 | ||
1062 | return 0; | |
1063 | } | |
1064 | ||
1065 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) | |
1066 | { | |
1067 | int ret; | |
1068 | ||
1069 | ret = gen6_ppgtt_allocate_page_directories(ppgtt); | |
1070 | if (ret) | |
1071 | return ret; | |
1072 | ||
1073 | ret = gen6_ppgtt_allocate_page_tables(ppgtt); | |
1074 | if (ret) { | |
1075 | drm_mm_remove_node(&ppgtt->node); | |
1076 | return ret; | |
1d2a314c DV |
1077 | } |
1078 | ||
b146520f BW |
1079 | return 0; |
1080 | } | |
1081 | ||
1082 | static int gen6_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt) | |
1083 | { | |
1084 | struct drm_device *dev = ppgtt->base.dev; | |
1085 | int i; | |
1d2a314c | 1086 | |
8d2e6308 | 1087 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
d7b3de91 | 1088 | struct page *page; |
8d2e6308 | 1089 | dma_addr_t pt_addr; |
211c568b | 1090 | |
d7b3de91 BW |
1091 | page = ppgtt->pd.page_table[i].page; |
1092 | pt_addr = pci_map_page(dev->pdev, page, 0, 4096, | |
8d2e6308 | 1093 | PCI_DMA_BIDIRECTIONAL); |
1d2a314c | 1094 | |
8d2e6308 | 1095 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
b146520f BW |
1096 | gen6_ppgtt_unmap_pages(ppgtt); |
1097 | return -EIO; | |
211c568b | 1098 | } |
b146520f | 1099 | |
7324cc04 | 1100 | ppgtt->pd.page_table[i].daddr = pt_addr; |
1d2a314c | 1101 | } |
1d2a314c | 1102 | |
b146520f BW |
1103 | return 0; |
1104 | } | |
1105 | ||
1106 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
1107 | { | |
1108 | struct drm_device *dev = ppgtt->base.dev; | |
1109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1110 | int ret; | |
1111 | ||
1112 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1113 | if (IS_GEN6(dev)) { | |
b146520f BW |
1114 | ppgtt->switch_mm = gen6_mm_switch; |
1115 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1116 | ppgtt->switch_mm = hsw_mm_switch; |
1117 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1118 | ppgtt->switch_mm = gen7_mm_switch; |
1119 | } else | |
1120 | BUG(); | |
1121 | ||
71ba2d64 YZ |
1122 | if (intel_vgpu_active(dev)) |
1123 | ppgtt->switch_mm = vgpu_mm_switch; | |
1124 | ||
b146520f BW |
1125 | ret = gen6_ppgtt_alloc(ppgtt); |
1126 | if (ret) | |
1127 | return ret; | |
1128 | ||
1129 | ret = gen6_ppgtt_setup_page_tables(ppgtt); | |
1130 | if (ret) { | |
1131 | gen6_ppgtt_free(ppgtt); | |
1132 | return ret; | |
1133 | } | |
1134 | ||
1135 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; | |
1136 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
1137 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; | |
b146520f | 1138 | ppgtt->base.start = 0; |
d7b3de91 | 1139 | ppgtt->base.total = ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES * PAGE_SIZE; |
87d60b63 | 1140 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1141 | |
7324cc04 | 1142 | ppgtt->pd.pd_offset = |
c8d4c0d6 | 1143 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t); |
1d2a314c | 1144 | |
b146520f | 1145 | ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); |
1d2a314c | 1146 | |
b146520f BW |
1147 | DRM_DEBUG_DRIVER("Allocated pde space (%ldM) at GTT entry: %lx\n", |
1148 | ppgtt->node.size >> 20, | |
1149 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1150 | |
fa76da34 DV |
1151 | gen6_write_pdes(ppgtt); |
1152 | DRM_DEBUG("Adding PPGTT at offset %x\n", | |
7324cc04 | 1153 | ppgtt->pd.pd_offset << 10); |
fa76da34 | 1154 | |
b146520f | 1155 | return 0; |
3440d265 DV |
1156 | } |
1157 | ||
fa76da34 | 1158 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1159 | { |
1160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3440d265 | 1161 | |
853ba5d2 | 1162 | ppgtt->base.dev = dev; |
8407bb91 | 1163 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1164 | |
3ed124b2 | 1165 | if (INTEL_INFO(dev)->gen < 8) |
fa76da34 | 1166 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 1167 | else |
1eb0f006 | 1168 | return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); |
fa76da34 DV |
1169 | } |
1170 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) | |
1171 | { | |
1172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1173 | int ret = 0; | |
3ed124b2 | 1174 | |
fa76da34 DV |
1175 | ret = __hw_ppgtt_init(dev, ppgtt); |
1176 | if (ret == 0) { | |
c7c48dfd | 1177 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1178 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1179 | ppgtt->base.total); | |
7e0d96bc | 1180 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1181 | } |
1d2a314c DV |
1182 | |
1183 | return ret; | |
1184 | } | |
1185 | ||
82460d97 DV |
1186 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1187 | { | |
1188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1189 | struct intel_engine_cs *ring; | |
1190 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1191 | int i, ret = 0; | |
1192 | ||
671b5013 TD |
1193 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1194 | * and the PDPs are contained within the context itself. We don't | |
1195 | * need to do anything here. */ | |
1196 | if (i915.enable_execlists) | |
1197 | return 0; | |
1198 | ||
82460d97 DV |
1199 | if (!USES_PPGTT(dev)) |
1200 | return 0; | |
1201 | ||
1202 | if (IS_GEN6(dev)) | |
1203 | gen6_ppgtt_enable(dev); | |
1204 | else if (IS_GEN7(dev)) | |
1205 | gen7_ppgtt_enable(dev); | |
1206 | else if (INTEL_INFO(dev)->gen >= 8) | |
1207 | gen8_ppgtt_enable(dev); | |
1208 | else | |
5f77eeb0 | 1209 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 DV |
1210 | |
1211 | if (ppgtt) { | |
1212 | for_each_ring(ring, dev_priv, i) { | |
6689c167 | 1213 | ret = ppgtt->switch_mm(ppgtt, ring); |
82460d97 DV |
1214 | if (ret != 0) |
1215 | return ret; | |
7e0d96bc | 1216 | } |
93bd8649 | 1217 | } |
1d2a314c DV |
1218 | |
1219 | return ret; | |
1220 | } | |
4d884705 DV |
1221 | struct i915_hw_ppgtt * |
1222 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1223 | { | |
1224 | struct i915_hw_ppgtt *ppgtt; | |
1225 | int ret; | |
1226 | ||
1227 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1228 | if (!ppgtt) | |
1229 | return ERR_PTR(-ENOMEM); | |
1230 | ||
1231 | ret = i915_ppgtt_init(dev, ppgtt); | |
1232 | if (ret) { | |
1233 | kfree(ppgtt); | |
1234 | return ERR_PTR(ret); | |
1235 | } | |
1236 | ||
1237 | ppgtt->file_priv = fpriv; | |
1238 | ||
198c974d DCS |
1239 | trace_i915_ppgtt_create(&ppgtt->base); |
1240 | ||
4d884705 DV |
1241 | return ppgtt; |
1242 | } | |
1243 | ||
ee960be7 DV |
1244 | void i915_ppgtt_release(struct kref *kref) |
1245 | { | |
1246 | struct i915_hw_ppgtt *ppgtt = | |
1247 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1248 | ||
198c974d DCS |
1249 | trace_i915_ppgtt_release(&ppgtt->base); |
1250 | ||
ee960be7 DV |
1251 | /* vmas should already be unbound */ |
1252 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1253 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1254 | ||
19dd120c DV |
1255 | list_del(&ppgtt->base.global_link); |
1256 | drm_mm_takedown(&ppgtt->base.mm); | |
1257 | ||
ee960be7 DV |
1258 | ppgtt->base.cleanup(&ppgtt->base); |
1259 | kfree(ppgtt); | |
1260 | } | |
1d2a314c | 1261 | |
7e0d96bc | 1262 | static void |
6f65e29a BW |
1263 | ppgtt_bind_vma(struct i915_vma *vma, |
1264 | enum i915_cache_level cache_level, | |
1265 | u32 flags) | |
1d2a314c | 1266 | { |
24f3a8cf AG |
1267 | /* Currently applicable only to VLV */ |
1268 | if (vma->obj->gt_ro) | |
1269 | flags |= PTE_READ_ONLY; | |
1270 | ||
782f1495 | 1271 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
24f3a8cf | 1272 | cache_level, flags); |
1d2a314c DV |
1273 | } |
1274 | ||
7e0d96bc | 1275 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
7bddb01f | 1276 | { |
6f65e29a | 1277 | vma->vm->clear_range(vma->vm, |
782f1495 BW |
1278 | vma->node.start, |
1279 | vma->obj->base.size, | |
6f65e29a | 1280 | true); |
7bddb01f DV |
1281 | } |
1282 | ||
a81cc00c BW |
1283 | extern int intel_iommu_gfx_mapped; |
1284 | /* Certain Gen5 chipsets require require idling the GPU before | |
1285 | * unmapping anything from the GTT when VT-d is enabled. | |
1286 | */ | |
1287 | static inline bool needs_idle_maps(struct drm_device *dev) | |
1288 | { | |
1289 | #ifdef CONFIG_INTEL_IOMMU | |
1290 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1291 | * was loaded first. | |
1292 | */ | |
1293 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1294 | return true; | |
1295 | #endif | |
1296 | return false; | |
1297 | } | |
1298 | ||
5c042287 BW |
1299 | static bool do_idling(struct drm_i915_private *dev_priv) |
1300 | { | |
1301 | bool ret = dev_priv->mm.interruptible; | |
1302 | ||
a81cc00c | 1303 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1304 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1305 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1306 | DRM_ERROR("Couldn't idle GPU\n"); |
1307 | /* Wait a bit, in hopes it avoids the hang */ | |
1308 | udelay(10); | |
1309 | } | |
1310 | } | |
1311 | ||
1312 | return ret; | |
1313 | } | |
1314 | ||
1315 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1316 | { | |
a81cc00c | 1317 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1318 | dev_priv->mm.interruptible = interruptible; |
1319 | } | |
1320 | ||
828c7908 BW |
1321 | void i915_check_and_clear_faults(struct drm_device *dev) |
1322 | { | |
1323 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1324 | struct intel_engine_cs *ring; |
828c7908 BW |
1325 | int i; |
1326 | ||
1327 | if (INTEL_INFO(dev)->gen < 6) | |
1328 | return; | |
1329 | ||
1330 | for_each_ring(ring, dev_priv, i) { | |
1331 | u32 fault_reg; | |
1332 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1333 | if (fault_reg & RING_FAULT_VALID) { | |
1334 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 1335 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
1336 | "\tAddress space: %s\n" |
1337 | "\tSource ID: %d\n" | |
1338 | "\tType: %d\n", | |
1339 | fault_reg & PAGE_MASK, | |
1340 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1341 | RING_FAULT_SRCID(fault_reg), | |
1342 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1343 | I915_WRITE(RING_FAULT_REG(ring), | |
1344 | fault_reg & ~RING_FAULT_VALID); | |
1345 | } | |
1346 | } | |
1347 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1348 | } | |
1349 | ||
91e56499 CW |
1350 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
1351 | { | |
1352 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { | |
1353 | intel_gtt_chipset_flush(); | |
1354 | } else { | |
1355 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1356 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1357 | } | |
1358 | } | |
1359 | ||
828c7908 BW |
1360 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
1361 | { | |
1362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1363 | ||
1364 | /* Don't bother messing with faults pre GEN6 as we have little | |
1365 | * documentation supporting that it's a good idea. | |
1366 | */ | |
1367 | if (INTEL_INFO(dev)->gen < 6) | |
1368 | return; | |
1369 | ||
1370 | i915_check_and_clear_faults(dev); | |
1371 | ||
1372 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1373 | dev_priv->gtt.base.start, |
1374 | dev_priv->gtt.base.total, | |
e568af1c | 1375 | true); |
91e56499 CW |
1376 | |
1377 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
1378 | } |
1379 | ||
76aaf220 DV |
1380 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
1381 | { | |
1382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 1383 | struct drm_i915_gem_object *obj; |
80da2161 | 1384 | struct i915_address_space *vm; |
76aaf220 | 1385 | |
828c7908 BW |
1386 | i915_check_and_clear_faults(dev); |
1387 | ||
bee4a186 | 1388 | /* First fill our portion of the GTT with scratch pages */ |
853ba5d2 | 1389 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
782f1495 BW |
1390 | dev_priv->gtt.base.start, |
1391 | dev_priv->gtt.base.total, | |
828c7908 | 1392 | true); |
bee4a186 | 1393 | |
35c20a60 | 1394 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
6f65e29a BW |
1395 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
1396 | &dev_priv->gtt.base); | |
1397 | if (!vma) | |
1398 | continue; | |
1399 | ||
2c22569b | 1400 | i915_gem_clflush_object(obj, obj->pin_display); |
6f65e29a BW |
1401 | /* The bind_vma code tries to be smart about tracking mappings. |
1402 | * Unfortunately above, we've just wiped out the mappings | |
1403 | * without telling our object about it. So we need to fake it. | |
fe14d5f4 TU |
1404 | * |
1405 | * Bind is not expected to fail since this is only called on | |
1406 | * resume and assumption is all requirements exist already. | |
6f65e29a | 1407 | */ |
aff43766 | 1408 | vma->bound &= ~GLOBAL_BIND; |
fe14d5f4 | 1409 | WARN_ON(i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND)); |
76aaf220 DV |
1410 | } |
1411 | ||
80da2161 | 1412 | |
a2319c08 | 1413 | if (INTEL_INFO(dev)->gen >= 8) { |
ee0ce478 VS |
1414 | if (IS_CHERRYVIEW(dev)) |
1415 | chv_setup_private_ppat(dev_priv); | |
1416 | else | |
1417 | bdw_setup_private_ppat(dev_priv); | |
1418 | ||
80da2161 | 1419 | return; |
a2319c08 | 1420 | } |
80da2161 BW |
1421 | |
1422 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
1423 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
1424 | if (i915_is_ggtt(vm)) { | |
1425 | if (dev_priv->mm.aliasing_ppgtt) | |
1426 | gen6_write_pdes(dev_priv->mm.aliasing_ppgtt); | |
1427 | continue; | |
1428 | } | |
1429 | ||
1430 | gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base)); | |
76aaf220 DV |
1431 | } |
1432 | ||
91e56499 | 1433 | i915_ggtt_flush(dev_priv); |
76aaf220 | 1434 | } |
7c2e6fdf | 1435 | |
74163907 | 1436 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1437 | { |
9da3da66 | 1438 | if (obj->has_dma_mapping) |
74163907 | 1439 | return 0; |
9da3da66 CW |
1440 | |
1441 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1442 | obj->pages->sgl, obj->pages->nents, | |
1443 | PCI_DMA_BIDIRECTIONAL)) | |
1444 | return -ENOSPC; | |
1445 | ||
1446 | return 0; | |
7c2e6fdf DV |
1447 | } |
1448 | ||
94ec8f61 BW |
1449 | static inline void gen8_set_pte(void __iomem *addr, gen8_gtt_pte_t pte) |
1450 | { | |
1451 | #ifdef writeq | |
1452 | writeq(pte, addr); | |
1453 | #else | |
1454 | iowrite32((u32)pte, addr); | |
1455 | iowrite32(pte >> 32, addr + 4); | |
1456 | #endif | |
1457 | } | |
1458 | ||
1459 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1460 | struct sg_table *st, | |
782f1495 | 1461 | uint64_t start, |
24f3a8cf | 1462 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1463 | { |
1464 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1465 | unsigned first_entry = start >> PAGE_SHIFT; |
94ec8f61 BW |
1466 | gen8_gtt_pte_t __iomem *gtt_entries = |
1467 | (gen8_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
1468 | int i = 0; | |
1469 | struct sg_page_iter sg_iter; | |
57007df7 | 1470 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1471 | |
1472 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1473 | addr = sg_dma_address(sg_iter.sg) + | |
1474 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1475 | gen8_set_pte(>t_entries[i], | |
1476 | gen8_pte_encode(addr, level, true)); | |
1477 | i++; | |
1478 | } | |
1479 | ||
1480 | /* | |
1481 | * XXX: This serves as a posting read to make sure that the PTE has | |
1482 | * actually been updated. There is some concern that even though | |
1483 | * registers and PTEs are within the same BAR that they are potentially | |
1484 | * of NUMA access patterns. Therefore, even with the way we assume | |
1485 | * hardware should work, we must keep this posting read for paranoia. | |
1486 | */ | |
1487 | if (i != 0) | |
1488 | WARN_ON(readq(>t_entries[i-1]) | |
1489 | != gen8_pte_encode(addr, level, true)); | |
1490 | ||
94ec8f61 BW |
1491 | /* This next bit makes the above posting read even more important. We |
1492 | * want to flush the TLBs only after we're certain all the PTE updates | |
1493 | * have finished. | |
1494 | */ | |
1495 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1496 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1497 | } |
1498 | ||
e76e9aeb BW |
1499 | /* |
1500 | * Binds an object into the global gtt with the specified cache level. The object | |
1501 | * will be accessible to the GPU via commands whose operands reference offsets | |
1502 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1503 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1504 | */ | |
853ba5d2 | 1505 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1506 | struct sg_table *st, |
782f1495 | 1507 | uint64_t start, |
24f3a8cf | 1508 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1509 | { |
853ba5d2 | 1510 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1511 | unsigned first_entry = start >> PAGE_SHIFT; |
e7c2b58b BW |
1512 | gen6_gtt_pte_t __iomem *gtt_entries = |
1513 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1514 | int i = 0; |
1515 | struct sg_page_iter sg_iter; | |
57007df7 | 1516 | dma_addr_t addr = 0; |
e76e9aeb | 1517 | |
6e995e23 | 1518 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1519 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1520 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1521 | i++; |
e76e9aeb BW |
1522 | } |
1523 | ||
e76e9aeb BW |
1524 | /* XXX: This serves as a posting read to make sure that the PTE has |
1525 | * actually been updated. There is some concern that even though | |
1526 | * registers and PTEs are within the same BAR that they are potentially | |
1527 | * of NUMA access patterns. Therefore, even with the way we assume | |
1528 | * hardware should work, we must keep this posting read for paranoia. | |
1529 | */ | |
57007df7 PM |
1530 | if (i != 0) { |
1531 | unsigned long gtt = readl(>t_entries[i-1]); | |
1532 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1533 | } | |
0f9b91c7 BW |
1534 | |
1535 | /* This next bit makes the above posting read even more important. We | |
1536 | * want to flush the TLBs only after we're certain all the PTE updates | |
1537 | * have finished. | |
1538 | */ | |
1539 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1540 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1541 | } |
1542 | ||
94ec8f61 | 1543 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1544 | uint64_t start, |
1545 | uint64_t length, | |
94ec8f61 BW |
1546 | bool use_scratch) |
1547 | { | |
1548 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1549 | unsigned first_entry = start >> PAGE_SHIFT; |
1550 | unsigned num_entries = length >> PAGE_SHIFT; | |
94ec8f61 BW |
1551 | gen8_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1552 | (gen8_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
1553 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; | |
1554 | int i; | |
1555 | ||
1556 | if (WARN(num_entries > max_entries, | |
1557 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1558 | first_entry, num_entries, max_entries)) | |
1559 | num_entries = max_entries; | |
1560 | ||
1561 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1562 | I915_CACHE_LLC, | |
1563 | use_scratch); | |
1564 | for (i = 0; i < num_entries; i++) | |
1565 | gen8_set_pte(>t_base[i], scratch_pte); | |
1566 | readl(gtt_base); | |
1567 | } | |
1568 | ||
853ba5d2 | 1569 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1570 | uint64_t start, |
1571 | uint64_t length, | |
828c7908 | 1572 | bool use_scratch) |
7faf1ab2 | 1573 | { |
853ba5d2 | 1574 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1575 | unsigned first_entry = start >> PAGE_SHIFT; |
1576 | unsigned num_entries = length >> PAGE_SHIFT; | |
e7c2b58b BW |
1577 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
1578 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1579 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1580 | int i; |
1581 | ||
1582 | if (WARN(num_entries > max_entries, | |
1583 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1584 | first_entry, num_entries, max_entries)) | |
1585 | num_entries = max_entries; | |
1586 | ||
24f3a8cf | 1587 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
828c7908 | 1588 | |
7faf1ab2 DV |
1589 | for (i = 0; i < num_entries; i++) |
1590 | iowrite32(scratch_pte, >t_base[i]); | |
1591 | readl(gtt_base); | |
1592 | } | |
1593 | ||
6f65e29a BW |
1594 | |
1595 | static void i915_ggtt_bind_vma(struct i915_vma *vma, | |
1596 | enum i915_cache_level cache_level, | |
1597 | u32 unused) | |
7faf1ab2 | 1598 | { |
6f65e29a | 1599 | const unsigned long entry = vma->node.start >> PAGE_SHIFT; |
7faf1ab2 DV |
1600 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
1601 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1602 | ||
6f65e29a | 1603 | BUG_ON(!i915_is_ggtt(vma->vm)); |
fe14d5f4 | 1604 | intel_gtt_insert_sg_entries(vma->ggtt_view.pages, entry, flags); |
aff43766 | 1605 | vma->bound = GLOBAL_BIND; |
7faf1ab2 DV |
1606 | } |
1607 | ||
853ba5d2 | 1608 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1609 | uint64_t start, |
1610 | uint64_t length, | |
828c7908 | 1611 | bool unused) |
7faf1ab2 | 1612 | { |
782f1495 BW |
1613 | unsigned first_entry = start >> PAGE_SHIFT; |
1614 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1615 | intel_gtt_clear_range(first_entry, num_entries); |
1616 | } | |
1617 | ||
6f65e29a BW |
1618 | static void i915_ggtt_unbind_vma(struct i915_vma *vma) |
1619 | { | |
1620 | const unsigned int first = vma->node.start >> PAGE_SHIFT; | |
1621 | const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; | |
7faf1ab2 | 1622 | |
6f65e29a | 1623 | BUG_ON(!i915_is_ggtt(vma->vm)); |
aff43766 | 1624 | vma->bound = 0; |
6f65e29a BW |
1625 | intel_gtt_clear_range(first, size); |
1626 | } | |
7faf1ab2 | 1627 | |
6f65e29a BW |
1628 | static void ggtt_bind_vma(struct i915_vma *vma, |
1629 | enum i915_cache_level cache_level, | |
1630 | u32 flags) | |
d5bd1449 | 1631 | { |
6f65e29a | 1632 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1633 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1634 | struct drm_i915_gem_object *obj = vma->obj; |
7faf1ab2 | 1635 | |
24f3a8cf AG |
1636 | /* Currently applicable only to VLV */ |
1637 | if (obj->gt_ro) | |
1638 | flags |= PTE_READ_ONLY; | |
1639 | ||
6f65e29a BW |
1640 | /* If there is no aliasing PPGTT, or the caller needs a global mapping, |
1641 | * or we have a global mapping already but the cacheability flags have | |
1642 | * changed, set the global PTEs. | |
1643 | * | |
1644 | * If there is an aliasing PPGTT it is anecdotally faster, so use that | |
1645 | * instead if none of the above hold true. | |
1646 | * | |
1647 | * NB: A global mapping should only be needed for special regions like | |
1648 | * "gtt mappable", SNB errata, or if specified via special execbuf | |
1649 | * flags. At all other times, the GPU will use the aliasing PPGTT. | |
1650 | */ | |
1651 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { | |
aff43766 | 1652 | if (!(vma->bound & GLOBAL_BIND) || |
6f65e29a | 1653 | (cache_level != obj->cache_level)) { |
fe14d5f4 | 1654 | vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages, |
782f1495 | 1655 | vma->node.start, |
24f3a8cf | 1656 | cache_level, flags); |
aff43766 | 1657 | vma->bound |= GLOBAL_BIND; |
6f65e29a BW |
1658 | } |
1659 | } | |
d5bd1449 | 1660 | |
6f65e29a | 1661 | if (dev_priv->mm.aliasing_ppgtt && |
aff43766 | 1662 | (!(vma->bound & LOCAL_BIND) || |
6f65e29a BW |
1663 | (cache_level != obj->cache_level))) { |
1664 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; | |
1665 | appgtt->base.insert_entries(&appgtt->base, | |
fe14d5f4 | 1666 | vma->ggtt_view.pages, |
782f1495 | 1667 | vma->node.start, |
24f3a8cf | 1668 | cache_level, flags); |
aff43766 | 1669 | vma->bound |= LOCAL_BIND; |
6f65e29a | 1670 | } |
d5bd1449 CW |
1671 | } |
1672 | ||
6f65e29a | 1673 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1674 | { |
6f65e29a | 1675 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1676 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1677 | struct drm_i915_gem_object *obj = vma->obj; |
6f65e29a | 1678 | |
aff43766 | 1679 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
1680 | vma->vm->clear_range(vma->vm, |
1681 | vma->node.start, | |
1682 | obj->base.size, | |
6f65e29a | 1683 | true); |
aff43766 | 1684 | vma->bound &= ~GLOBAL_BIND; |
6f65e29a | 1685 | } |
74898d7e | 1686 | |
aff43766 | 1687 | if (vma->bound & LOCAL_BIND) { |
6f65e29a BW |
1688 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
1689 | appgtt->base.clear_range(&appgtt->base, | |
782f1495 BW |
1690 | vma->node.start, |
1691 | obj->base.size, | |
6f65e29a | 1692 | true); |
aff43766 | 1693 | vma->bound &= ~LOCAL_BIND; |
6f65e29a | 1694 | } |
74163907 DV |
1695 | } |
1696 | ||
1697 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1698 | { |
5c042287 BW |
1699 | struct drm_device *dev = obj->base.dev; |
1700 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1701 | bool interruptible; | |
1702 | ||
1703 | interruptible = do_idling(dev_priv); | |
1704 | ||
9da3da66 CW |
1705 | if (!obj->has_dma_mapping) |
1706 | dma_unmap_sg(&dev->pdev->dev, | |
1707 | obj->pages->sgl, obj->pages->nents, | |
1708 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1709 | |
1710 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1711 | } |
644ec02b | 1712 | |
42d6ab48 CW |
1713 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1714 | unsigned long color, | |
1715 | unsigned long *start, | |
1716 | unsigned long *end) | |
1717 | { | |
1718 | if (node->color != color) | |
1719 | *start += 4096; | |
1720 | ||
1721 | if (!list_empty(&node->node_list)) { | |
1722 | node = list_entry(node->node_list.next, | |
1723 | struct drm_mm_node, | |
1724 | node_list); | |
1725 | if (node->allocated && node->color != color) | |
1726 | *end -= 4096; | |
1727 | } | |
1728 | } | |
fbe5d36e | 1729 | |
f548c0e9 DV |
1730 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
1731 | unsigned long start, | |
1732 | unsigned long mappable_end, | |
1733 | unsigned long end) | |
644ec02b | 1734 | { |
e78891ca BW |
1735 | /* Let GEM Manage all of the aperture. |
1736 | * | |
1737 | * However, leave one page at the end still bound to the scratch page. | |
1738 | * There are a number of places where the hardware apparently prefetches | |
1739 | * past the end of the object, and we've seen multiple hangs with the | |
1740 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
1741 | * aperture. One page should be enough to keep any prefetching inside | |
1742 | * of the aperture. | |
1743 | */ | |
40d74980 BW |
1744 | struct drm_i915_private *dev_priv = dev->dev_private; |
1745 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
1746 | struct drm_mm_node *entry; |
1747 | struct drm_i915_gem_object *obj; | |
1748 | unsigned long hole_start, hole_end; | |
fa76da34 | 1749 | int ret; |
644ec02b | 1750 | |
35451cb6 BW |
1751 | BUG_ON(mappable_end > end); |
1752 | ||
ed2f3452 | 1753 | /* Subtract the guard page ... */ |
40d74980 | 1754 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
5dda8fa3 YZ |
1755 | |
1756 | dev_priv->gtt.base.start = start; | |
1757 | dev_priv->gtt.base.total = end - start; | |
1758 | ||
1759 | if (intel_vgpu_active(dev)) { | |
1760 | ret = intel_vgt_balloon(dev); | |
1761 | if (ret) | |
1762 | return ret; | |
1763 | } | |
1764 | ||
42d6ab48 | 1765 | if (!HAS_LLC(dev)) |
93bd8649 | 1766 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 1767 | |
ed2f3452 | 1768 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 1769 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 1770 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 1771 | |
edd41a87 | 1772 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
1773 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
1774 | ||
1775 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 1776 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
1777 | if (ret) { |
1778 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
1779 | return ret; | |
1780 | } | |
aff43766 | 1781 | vma->bound |= GLOBAL_BIND; |
ed2f3452 CW |
1782 | } |
1783 | ||
ed2f3452 | 1784 | /* Clear any non-preallocated blocks */ |
40d74980 | 1785 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
1786 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
1787 | hole_start, hole_end); | |
782f1495 BW |
1788 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
1789 | hole_end - hole_start, true); | |
ed2f3452 CW |
1790 | } |
1791 | ||
1792 | /* And finally clear the reserved guard page */ | |
782f1495 | 1793 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 1794 | |
fa76da34 DV |
1795 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
1796 | struct i915_hw_ppgtt *ppgtt; | |
1797 | ||
1798 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1799 | if (!ppgtt) | |
1800 | return -ENOMEM; | |
1801 | ||
1802 | ret = __hw_ppgtt_init(dev, ppgtt); | |
1803 | if (ret != 0) | |
1804 | return ret; | |
1805 | ||
1806 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1807 | } | |
1808 | ||
6c5566a8 | 1809 | return 0; |
e76e9aeb BW |
1810 | } |
1811 | ||
d7e5008f BW |
1812 | void i915_gem_init_global_gtt(struct drm_device *dev) |
1813 | { | |
1814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1815 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 1816 | |
853ba5d2 | 1817 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 1818 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 1819 | |
e78891ca | 1820 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
1821 | } |
1822 | ||
90d0a0e8 DV |
1823 | void i915_global_gtt_cleanup(struct drm_device *dev) |
1824 | { | |
1825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1826 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
1827 | ||
70e32544 DV |
1828 | if (dev_priv->mm.aliasing_ppgtt) { |
1829 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1830 | ||
1831 | ppgtt->base.cleanup(&ppgtt->base); | |
1832 | } | |
1833 | ||
90d0a0e8 | 1834 | if (drm_mm_initialized(&vm->mm)) { |
5dda8fa3 YZ |
1835 | if (intel_vgpu_active(dev)) |
1836 | intel_vgt_deballoon(); | |
1837 | ||
90d0a0e8 DV |
1838 | drm_mm_takedown(&vm->mm); |
1839 | list_del(&vm->global_link); | |
1840 | } | |
1841 | ||
1842 | vm->cleanup(vm); | |
1843 | } | |
70e32544 | 1844 | |
e76e9aeb BW |
1845 | static int setup_scratch_page(struct drm_device *dev) |
1846 | { | |
1847 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1848 | struct page *page; | |
1849 | dma_addr_t dma_addr; | |
1850 | ||
1851 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
1852 | if (page == NULL) | |
1853 | return -ENOMEM; | |
e76e9aeb BW |
1854 | set_pages_uc(page, 1); |
1855 | ||
1856 | #ifdef CONFIG_INTEL_IOMMU | |
1857 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
1858 | PCI_DMA_BIDIRECTIONAL); | |
1859 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
1860 | return -EINVAL; | |
1861 | #else | |
1862 | dma_addr = page_to_phys(page); | |
1863 | #endif | |
853ba5d2 BW |
1864 | dev_priv->gtt.base.scratch.page = page; |
1865 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
1866 | |
1867 | return 0; | |
1868 | } | |
1869 | ||
1870 | static void teardown_scratch_page(struct drm_device *dev) | |
1871 | { | |
1872 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
1873 | struct page *page = dev_priv->gtt.base.scratch.page; |
1874 | ||
1875 | set_pages_wb(page, 1); | |
1876 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 1877 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 | 1878 | __free_page(page); |
e76e9aeb BW |
1879 | } |
1880 | ||
1881 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
1882 | { | |
1883 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
1884 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
1885 | return snb_gmch_ctl << 20; | |
1886 | } | |
1887 | ||
9459d252 BW |
1888 | static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
1889 | { | |
1890 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
1891 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
1892 | if (bdw_gmch_ctl) | |
1893 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
1894 | |
1895 | #ifdef CONFIG_X86_32 | |
1896 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
1897 | if (bdw_gmch_ctl > 4) | |
1898 | bdw_gmch_ctl = 4; | |
1899 | #endif | |
1900 | ||
9459d252 BW |
1901 | return bdw_gmch_ctl << 20; |
1902 | } | |
1903 | ||
d7f25f23 DL |
1904 | static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
1905 | { | |
1906 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
1907 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
1908 | ||
1909 | if (gmch_ctrl) | |
1910 | return 1 << (20 + gmch_ctrl); | |
1911 | ||
1912 | return 0; | |
1913 | } | |
1914 | ||
baa09f5f | 1915 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
1916 | { |
1917 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
1918 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
1919 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
1920 | } | |
1921 | ||
9459d252 BW |
1922 | static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
1923 | { | |
1924 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1925 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1926 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
1927 | } | |
1928 | ||
d7f25f23 DL |
1929 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
1930 | { | |
1931 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
1932 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
1933 | ||
1934 | /* | |
1935 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
1936 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
1937 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
1938 | */ | |
1939 | if (gmch_ctrl < 0x11) | |
1940 | return gmch_ctrl << 25; | |
1941 | else if (gmch_ctrl < 0x17) | |
1942 | return (gmch_ctrl - 0x11 + 2) << 22; | |
1943 | else | |
1944 | return (gmch_ctrl - 0x17 + 9) << 22; | |
1945 | } | |
1946 | ||
66375014 DL |
1947 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
1948 | { | |
1949 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
1950 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
1951 | ||
1952 | if (gen9_gmch_ctl < 0xf0) | |
1953 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
1954 | else | |
1955 | /* 4MB increments starting at 0xf0 for 4MB */ | |
1956 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
1957 | } | |
1958 | ||
63340133 BW |
1959 | static int ggtt_probe_common(struct drm_device *dev, |
1960 | size_t gtt_size) | |
1961 | { | |
1962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 1963 | phys_addr_t gtt_phys_addr; |
63340133 BW |
1964 | int ret; |
1965 | ||
1966 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 1967 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
1968 | (pci_resource_len(dev->pdev, 0) / 2); |
1969 | ||
21c34607 | 1970 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
63340133 BW |
1971 | if (!dev_priv->gtt.gsm) { |
1972 | DRM_ERROR("Failed to map the gtt page table\n"); | |
1973 | return -ENOMEM; | |
1974 | } | |
1975 | ||
1976 | ret = setup_scratch_page(dev); | |
1977 | if (ret) { | |
1978 | DRM_ERROR("Scratch setup failed\n"); | |
1979 | /* iounmap will also get called at remove, but meh */ | |
1980 | iounmap(dev_priv->gtt.gsm); | |
1981 | } | |
1982 | ||
1983 | return ret; | |
1984 | } | |
1985 | ||
fbe5d36e BW |
1986 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
1987 | * bits. When using advanced contexts each context stores its own PAT, but | |
1988 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 1989 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 1990 | { |
fbe5d36e BW |
1991 | uint64_t pat; |
1992 | ||
1993 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
1994 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
1995 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
1996 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
1997 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
1998 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
1999 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2000 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2001 | ||
d6a8b72e RV |
2002 | if (!USES_PPGTT(dev_priv->dev)) |
2003 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2004 | * so RTL will always use the value corresponding to | |
2005 | * pat_sel = 000". | |
2006 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2007 | * MOCS still can be used though. | |
2008 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2009 | * before this patch, i.e. the same uncached + snooping access | |
2010 | * like on gen6/7 seems to be in effect. | |
2011 | * - So this just fixes blitter/render access. Again it looks | |
2012 | * like it's not just uncached access, but uncached + snooping. | |
2013 | * So we can still hold onto all our assumptions wrt cpu | |
2014 | * clflushing on LLC machines. | |
2015 | */ | |
2016 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2017 | ||
fbe5d36e BW |
2018 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2019 | * write would work. */ | |
2020 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2021 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2022 | } | |
2023 | ||
ee0ce478 VS |
2024 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2025 | { | |
2026 | uint64_t pat; | |
2027 | ||
2028 | /* | |
2029 | * Map WB on BDW to snooped on CHV. | |
2030 | * | |
2031 | * Only the snoop bit has meaning for CHV, the rest is | |
2032 | * ignored. | |
2033 | * | |
cf3d262e VS |
2034 | * The hardware will never snoop for certain types of accesses: |
2035 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2036 | * - PPGTT page tables | |
2037 | * - some other special cycles | |
2038 | * | |
2039 | * As with BDW, we also need to consider the following for GT accesses: | |
2040 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2041 | * so RTL will always use the value corresponding to | |
2042 | * pat_sel = 000". | |
2043 | * Which means we must set the snoop bit in PAT entry 0 | |
2044 | * in order to keep the global status page working. | |
ee0ce478 VS |
2045 | */ |
2046 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2047 | GEN8_PPAT(1, 0) | | |
2048 | GEN8_PPAT(2, 0) | | |
2049 | GEN8_PPAT(3, 0) | | |
2050 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
2051 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
2052 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
2053 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
2054 | ||
2055 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2056 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2057 | } | |
2058 | ||
63340133 BW |
2059 | static int gen8_gmch_probe(struct drm_device *dev, |
2060 | size_t *gtt_total, | |
2061 | size_t *stolen, | |
2062 | phys_addr_t *mappable_base, | |
2063 | unsigned long *mappable_end) | |
2064 | { | |
2065 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2066 | unsigned int gtt_size; | |
2067 | u16 snb_gmch_ctl; | |
2068 | int ret; | |
2069 | ||
2070 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
2071 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
2072 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2073 | ||
2074 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
2075 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
2076 | ||
2077 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
2078 | ||
66375014 DL |
2079 | if (INTEL_INFO(dev)->gen >= 9) { |
2080 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); | |
2081 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2082 | } else if (IS_CHERRYVIEW(dev)) { | |
d7f25f23 DL |
2083 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
2084 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
2085 | } else { | |
2086 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
2087 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2088 | } | |
63340133 | 2089 | |
d31eb10e | 2090 | *gtt_total = (gtt_size / sizeof(gen8_gtt_pte_t)) << PAGE_SHIFT; |
63340133 | 2091 | |
ee0ce478 VS |
2092 | if (IS_CHERRYVIEW(dev)) |
2093 | chv_setup_private_ppat(dev_priv); | |
2094 | else | |
2095 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2096 | |
63340133 BW |
2097 | ret = ggtt_probe_common(dev, gtt_size); |
2098 | ||
94ec8f61 BW |
2099 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
2100 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
63340133 BW |
2101 | |
2102 | return ret; | |
2103 | } | |
2104 | ||
baa09f5f BW |
2105 | static int gen6_gmch_probe(struct drm_device *dev, |
2106 | size_t *gtt_total, | |
41907ddc BW |
2107 | size_t *stolen, |
2108 | phys_addr_t *mappable_base, | |
2109 | unsigned long *mappable_end) | |
e76e9aeb BW |
2110 | { |
2111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2112 | unsigned int gtt_size; |
e76e9aeb | 2113 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2114 | int ret; |
2115 | ||
41907ddc BW |
2116 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2117 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2118 | ||
baa09f5f BW |
2119 | /* 64/512MB is the current min/max we actually know of, but this is just |
2120 | * a coarse sanity check. | |
e76e9aeb | 2121 | */ |
41907ddc | 2122 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
2123 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
2124 | dev_priv->gtt.mappable_end); | |
2125 | return -ENXIO; | |
e76e9aeb BW |
2126 | } |
2127 | ||
e76e9aeb BW |
2128 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2129 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2130 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2131 | |
c4ae25ec | 2132 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2133 | |
63340133 BW |
2134 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
2135 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; | |
e76e9aeb | 2136 | |
63340133 | 2137 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2138 | |
853ba5d2 BW |
2139 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2140 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
7faf1ab2 | 2141 | |
e76e9aeb BW |
2142 | return ret; |
2143 | } | |
2144 | ||
853ba5d2 | 2145 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2146 | { |
853ba5d2 BW |
2147 | |
2148 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2149 | |
853ba5d2 BW |
2150 | iounmap(gtt->gsm); |
2151 | teardown_scratch_page(vm->dev); | |
644ec02b | 2152 | } |
baa09f5f BW |
2153 | |
2154 | static int i915_gmch_probe(struct drm_device *dev, | |
2155 | size_t *gtt_total, | |
41907ddc BW |
2156 | size_t *stolen, |
2157 | phys_addr_t *mappable_base, | |
2158 | unsigned long *mappable_end) | |
baa09f5f BW |
2159 | { |
2160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2161 | int ret; | |
2162 | ||
baa09f5f BW |
2163 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2164 | if (!ret) { | |
2165 | DRM_ERROR("failed to set up gmch\n"); | |
2166 | return -EIO; | |
2167 | } | |
2168 | ||
41907ddc | 2169 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2170 | |
2171 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
853ba5d2 | 2172 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
baa09f5f | 2173 | |
c0a7f818 CW |
2174 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2175 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2176 | ||
baa09f5f BW |
2177 | return 0; |
2178 | } | |
2179 | ||
853ba5d2 | 2180 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2181 | { |
2182 | intel_gmch_remove(); | |
2183 | } | |
2184 | ||
2185 | int i915_gem_gtt_init(struct drm_device *dev) | |
2186 | { | |
2187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2188 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2189 | int ret; |
2190 | ||
baa09f5f | 2191 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2192 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2193 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2194 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2195 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2196 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2197 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2198 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2199 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2200 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2201 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2202 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2203 | else if (INTEL_INFO(dev)->gen >= 7) |
2204 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2205 | else |
350ec881 | 2206 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2207 | } else { |
2208 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2209 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2210 | } |
2211 | ||
853ba5d2 | 2212 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2213 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2214 | if (ret) |
baa09f5f | 2215 | return ret; |
baa09f5f | 2216 | |
853ba5d2 BW |
2217 | gtt->base.dev = dev; |
2218 | ||
baa09f5f | 2219 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
853ba5d2 BW |
2220 | DRM_INFO("Memory usable by graphics device = %zdM\n", |
2221 | gtt->base.total >> 20); | |
b2f21b4d BW |
2222 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2223 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
5db6c735 DV |
2224 | #ifdef CONFIG_INTEL_IOMMU |
2225 | if (intel_iommu_gfx_mapped) | |
2226 | DRM_INFO("VT-d active for gfx access\n"); | |
2227 | #endif | |
cfa7c862 DV |
2228 | /* |
2229 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2230 | * user's requested state against the hardware/driver capabilities. We | |
2231 | * do this now so that we can print out any log messages once rather | |
2232 | * than every time we check intel_enable_ppgtt(). | |
2233 | */ | |
2234 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2235 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2236 | |
2237 | return 0; | |
2238 | } | |
6f65e29a BW |
2239 | |
2240 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
fe14d5f4 TU |
2241 | struct i915_address_space *vm, |
2242 | const struct i915_ggtt_view *view) | |
6f65e29a BW |
2243 | { |
2244 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
2245 | if (vma == NULL) | |
2246 | return ERR_PTR(-ENOMEM); | |
2247 | ||
2248 | INIT_LIST_HEAD(&vma->vma_link); | |
2249 | INIT_LIST_HEAD(&vma->mm_list); | |
2250 | INIT_LIST_HEAD(&vma->exec_list); | |
2251 | vma->vm = vm; | |
2252 | vma->obj = obj; | |
fe14d5f4 | 2253 | vma->ggtt_view = *view; |
6f65e29a | 2254 | |
b1252bcf | 2255 | if (INTEL_INFO(vm->dev)->gen >= 6) { |
7e0d96bc BW |
2256 | if (i915_is_ggtt(vm)) { |
2257 | vma->unbind_vma = ggtt_unbind_vma; | |
2258 | vma->bind_vma = ggtt_bind_vma; | |
2259 | } else { | |
2260 | vma->unbind_vma = ppgtt_unbind_vma; | |
2261 | vma->bind_vma = ppgtt_bind_vma; | |
2262 | } | |
b1252bcf | 2263 | } else { |
6f65e29a BW |
2264 | BUG_ON(!i915_is_ggtt(vm)); |
2265 | vma->unbind_vma = i915_ggtt_unbind_vma; | |
2266 | vma->bind_vma = i915_ggtt_bind_vma; | |
6f65e29a BW |
2267 | } |
2268 | ||
f7635669 TU |
2269 | list_add_tail(&vma->vma_link, &obj->vma_list); |
2270 | if (!i915_is_ggtt(vm)) | |
e07f0552 | 2271 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
6f65e29a BW |
2272 | |
2273 | return vma; | |
2274 | } | |
2275 | ||
2276 | struct i915_vma * | |
fe14d5f4 TU |
2277 | i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object *obj, |
2278 | struct i915_address_space *vm, | |
2279 | const struct i915_ggtt_view *view) | |
6f65e29a BW |
2280 | { |
2281 | struct i915_vma *vma; | |
2282 | ||
fe14d5f4 | 2283 | vma = i915_gem_obj_to_vma_view(obj, vm, view); |
6f65e29a | 2284 | if (!vma) |
fe14d5f4 | 2285 | vma = __i915_gem_vma_create(obj, vm, view); |
6f65e29a BW |
2286 | |
2287 | return vma; | |
2288 | } | |
fe14d5f4 TU |
2289 | |
2290 | static inline | |
2291 | int i915_get_vma_pages(struct i915_vma *vma) | |
2292 | { | |
2293 | if (vma->ggtt_view.pages) | |
2294 | return 0; | |
2295 | ||
2296 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
2297 | vma->ggtt_view.pages = vma->obj->pages; | |
2298 | else | |
2299 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
2300 | vma->ggtt_view.type); | |
2301 | ||
2302 | if (!vma->ggtt_view.pages) { | |
2303 | DRM_ERROR("Failed to get pages for VMA view type %u!\n", | |
2304 | vma->ggtt_view.type); | |
2305 | return -EINVAL; | |
2306 | } | |
2307 | ||
2308 | return 0; | |
2309 | } | |
2310 | ||
2311 | /** | |
2312 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
2313 | * @vma: VMA to map | |
2314 | * @cache_level: mapping cache level | |
2315 | * @flags: flags like global or local mapping | |
2316 | * | |
2317 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
2318 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
2319 | * Note that DMA addresses are also the only part of the SG table we care about. | |
2320 | */ | |
2321 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2322 | u32 flags) | |
2323 | { | |
2324 | int ret = i915_get_vma_pages(vma); | |
2325 | ||
2326 | if (ret) | |
2327 | return ret; | |
2328 | ||
2329 | vma->bind_vma(vma, cache_level, flags); | |
2330 | ||
2331 | return 0; | |
2332 | } |