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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 | 29 | #include "i915_drv.h" |
5dda8fa3 | 30 | #include "i915_vgpu.h" |
76aaf220 DV |
31 | #include "i915_trace.h" |
32 | #include "intel_drv.h" | |
33 | ||
45f8f69a TU |
34 | /** |
35 | * DOC: Global GTT views | |
36 | * | |
37 | * Background and previous state | |
38 | * | |
39 | * Historically objects could exists (be bound) in global GTT space only as | |
40 | * singular instances with a view representing all of the object's backing pages | |
41 | * in a linear fashion. This view will be called a normal view. | |
42 | * | |
43 | * To support multiple views of the same object, where the number of mapped | |
44 | * pages is not equal to the backing store, or where the layout of the pages | |
45 | * is not linear, concept of a GGTT view was added. | |
46 | * | |
47 | * One example of an alternative view is a stereo display driven by a single | |
48 | * image. In this case we would have a framebuffer looking like this | |
49 | * (2x2 pages): | |
50 | * | |
51 | * 12 | |
52 | * 34 | |
53 | * | |
54 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
55 | * rendering. In contrast, fed to the display engine would be an alternative | |
56 | * view which could look something like this: | |
57 | * | |
58 | * 1212 | |
59 | * 3434 | |
60 | * | |
61 | * In this example both the size and layout of pages in the alternative view is | |
62 | * different from the normal view. | |
63 | * | |
64 | * Implementation and usage | |
65 | * | |
66 | * GGTT views are implemented using VMAs and are distinguished via enum | |
67 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
68 | * | |
69 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
70 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
71 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
72 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
73 | * |
74 | * As a helper for callers which are only interested in the normal view, | |
75 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
76 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
77 | * or with the normal GGTT view. | |
78 | * | |
79 | * Code wanting to add or use a new GGTT view needs to: | |
80 | * | |
81 | * 1. Add a new enum with a suitable name. | |
82 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
83 | * 3. Add support to i915_get_vma_pages(). | |
84 | * | |
85 | * New views are required to build a scatter-gather table from within the | |
86 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
87 | * exists for the lifetime of an VMA. | |
88 | * | |
89 | * Core API is designed to have copy semantics which means that passed in | |
90 | * struct i915_ggtt_view does not need to be persistent (left around after | |
91 | * calling the core API functions). | |
92 | * | |
93 | */ | |
94 | ||
70b9f6f8 DV |
95 | static int |
96 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
97 | ||
fe14d5f4 | 98 | const struct i915_ggtt_view i915_ggtt_view_normal; |
9abc4648 JL |
99 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
100 | .type = I915_GGTT_VIEW_ROTATED | |
101 | }; | |
fe14d5f4 | 102 | |
cfa7c862 DV |
103 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
104 | { | |
1893a71b CW |
105 | bool has_aliasing_ppgtt; |
106 | bool has_full_ppgtt; | |
107 | ||
108 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
109 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
1893a71b | 110 | |
71ba2d64 YZ |
111 | if (intel_vgpu_active(dev)) |
112 | has_full_ppgtt = false; /* emulation is too hard */ | |
113 | ||
70ee45e1 DL |
114 | /* |
115 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
116 | * execlists, the sole mechanism available to submit work. | |
117 | */ | |
118 | if (INTEL_INFO(dev)->gen < 9 && | |
119 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) | |
cfa7c862 DV |
120 | return 0; |
121 | ||
122 | if (enable_ppgtt == 1) | |
123 | return 1; | |
124 | ||
1893a71b | 125 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
126 | return 2; |
127 | ||
93a25a9e DV |
128 | #ifdef CONFIG_INTEL_IOMMU |
129 | /* Disable ppgtt on SNB if VT-d is on. */ | |
130 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
131 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 132 | return 0; |
93a25a9e DV |
133 | } |
134 | #endif | |
135 | ||
62942ed7 | 136 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
137 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
138 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
139 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
140 | return 0; | |
141 | } | |
142 | ||
2f82bbdf MT |
143 | if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) |
144 | return 2; | |
145 | else | |
146 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
147 | } |
148 | ||
70b9f6f8 DV |
149 | static int ppgtt_bind_vma(struct i915_vma *vma, |
150 | enum i915_cache_level cache_level, | |
151 | u32 unused) | |
47552659 DV |
152 | { |
153 | u32 pte_flags = 0; | |
154 | ||
155 | /* Currently applicable only to VLV */ | |
156 | if (vma->obj->gt_ro) | |
157 | pte_flags |= PTE_READ_ONLY; | |
158 | ||
159 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, | |
160 | cache_level, pte_flags); | |
70b9f6f8 DV |
161 | |
162 | return 0; | |
47552659 DV |
163 | } |
164 | ||
165 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
166 | { | |
167 | vma->vm->clear_range(vma->vm, | |
168 | vma->node.start, | |
169 | vma->obj->base.size, | |
170 | true); | |
171 | } | |
6f65e29a | 172 | |
2c642b07 DV |
173 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
174 | enum i915_cache_level level, | |
175 | bool valid) | |
94ec8f61 | 176 | { |
07749ef3 | 177 | gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
94ec8f61 | 178 | pte |= addr; |
63c42e56 BW |
179 | |
180 | switch (level) { | |
181 | case I915_CACHE_NONE: | |
fbe5d36e | 182 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
183 | break; |
184 | case I915_CACHE_WT: | |
185 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
186 | break; | |
187 | default: | |
188 | pte |= PPAT_CACHED_INDEX; | |
189 | break; | |
190 | } | |
191 | ||
94ec8f61 BW |
192 | return pte; |
193 | } | |
194 | ||
fe36f55d MK |
195 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
196 | const enum i915_cache_level level) | |
b1fe6673 | 197 | { |
07749ef3 | 198 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
199 | pde |= addr; |
200 | if (level != I915_CACHE_NONE) | |
201 | pde |= PPAT_CACHED_PDE_INDEX; | |
202 | else | |
203 | pde |= PPAT_UNCACHED_INDEX; | |
204 | return pde; | |
205 | } | |
206 | ||
762d9936 MT |
207 | #define gen8_pdpe_encode gen8_pde_encode |
208 | #define gen8_pml4e_encode gen8_pde_encode | |
209 | ||
07749ef3 MT |
210 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
211 | enum i915_cache_level level, | |
212 | bool valid, u32 unused) | |
54d12527 | 213 | { |
07749ef3 | 214 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 215 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
216 | |
217 | switch (level) { | |
350ec881 CW |
218 | case I915_CACHE_L3_LLC: |
219 | case I915_CACHE_LLC: | |
220 | pte |= GEN6_PTE_CACHE_LLC; | |
221 | break; | |
222 | case I915_CACHE_NONE: | |
223 | pte |= GEN6_PTE_UNCACHED; | |
224 | break; | |
225 | default: | |
5f77eeb0 | 226 | MISSING_CASE(level); |
350ec881 CW |
227 | } |
228 | ||
229 | return pte; | |
230 | } | |
231 | ||
07749ef3 MT |
232 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
233 | enum i915_cache_level level, | |
234 | bool valid, u32 unused) | |
350ec881 | 235 | { |
07749ef3 | 236 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
237 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
238 | ||
239 | switch (level) { | |
240 | case I915_CACHE_L3_LLC: | |
241 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
242 | break; |
243 | case I915_CACHE_LLC: | |
244 | pte |= GEN6_PTE_CACHE_LLC; | |
245 | break; | |
246 | case I915_CACHE_NONE: | |
9119708c | 247 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
248 | break; |
249 | default: | |
5f77eeb0 | 250 | MISSING_CASE(level); |
e7210c3c BW |
251 | } |
252 | ||
54d12527 BW |
253 | return pte; |
254 | } | |
255 | ||
07749ef3 MT |
256 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
257 | enum i915_cache_level level, | |
258 | bool valid, u32 flags) | |
93c34e70 | 259 | { |
07749ef3 | 260 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
261 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
262 | ||
24f3a8cf AG |
263 | if (!(flags & PTE_READ_ONLY)) |
264 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
265 | |
266 | if (level != I915_CACHE_NONE) | |
267 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
268 | ||
269 | return pte; | |
270 | } | |
271 | ||
07749ef3 MT |
272 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
273 | enum i915_cache_level level, | |
274 | bool valid, u32 unused) | |
9119708c | 275 | { |
07749ef3 | 276 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 277 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
278 | |
279 | if (level != I915_CACHE_NONE) | |
87a6b688 | 280 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
281 | |
282 | return pte; | |
283 | } | |
284 | ||
07749ef3 MT |
285 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
286 | enum i915_cache_level level, | |
287 | bool valid, u32 unused) | |
4d15c145 | 288 | { |
07749ef3 | 289 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
290 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
291 | ||
651d794f CW |
292 | switch (level) { |
293 | case I915_CACHE_NONE: | |
294 | break; | |
295 | case I915_CACHE_WT: | |
c51e9701 | 296 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
297 | break; |
298 | default: | |
c51e9701 | 299 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
300 | break; |
301 | } | |
4d15c145 BW |
302 | |
303 | return pte; | |
304 | } | |
305 | ||
c114f76a MK |
306 | static int __setup_page_dma(struct drm_device *dev, |
307 | struct i915_page_dma *p, gfp_t flags) | |
678d96fb BW |
308 | { |
309 | struct device *device = &dev->pdev->dev; | |
310 | ||
c114f76a | 311 | p->page = alloc_page(flags); |
44159ddb MK |
312 | if (!p->page) |
313 | return -ENOMEM; | |
678d96fb | 314 | |
44159ddb MK |
315 | p->daddr = dma_map_page(device, |
316 | p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL); | |
678d96fb | 317 | |
44159ddb MK |
318 | if (dma_mapping_error(device, p->daddr)) { |
319 | __free_page(p->page); | |
320 | return -EINVAL; | |
321 | } | |
1266cdb1 MT |
322 | |
323 | return 0; | |
678d96fb BW |
324 | } |
325 | ||
c114f76a MK |
326 | static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
327 | { | |
328 | return __setup_page_dma(dev, p, GFP_KERNEL); | |
329 | } | |
330 | ||
44159ddb | 331 | static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
06fda602 | 332 | { |
44159ddb | 333 | if (WARN_ON(!p->page)) |
06fda602 | 334 | return; |
678d96fb | 335 | |
44159ddb MK |
336 | dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL); |
337 | __free_page(p->page); | |
338 | memset(p, 0, sizeof(*p)); | |
339 | } | |
340 | ||
d1c54acd | 341 | static void *kmap_page_dma(struct i915_page_dma *p) |
73eeea53 | 342 | { |
d1c54acd MK |
343 | return kmap_atomic(p->page); |
344 | } | |
73eeea53 | 345 | |
d1c54acd MK |
346 | /* We use the flushing unmap only with ppgtt structures: |
347 | * page directories, page tables and scratch pages. | |
348 | */ | |
349 | static void kunmap_page_dma(struct drm_device *dev, void *vaddr) | |
350 | { | |
73eeea53 MK |
351 | /* There are only few exceptions for gen >=6. chv and bxt. |
352 | * And we are not sure about the latter so play safe for now. | |
353 | */ | |
354 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) | |
355 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
356 | ||
357 | kunmap_atomic(vaddr); | |
358 | } | |
359 | ||
567047be | 360 | #define kmap_px(px) kmap_page_dma(px_base(px)) |
d1c54acd MK |
361 | #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr)) |
362 | ||
567047be MK |
363 | #define setup_px(dev, px) setup_page_dma((dev), px_base(px)) |
364 | #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px)) | |
365 | #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v)) | |
366 | #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v)) | |
367 | ||
d1c54acd MK |
368 | static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p, |
369 | const uint64_t val) | |
370 | { | |
371 | int i; | |
372 | uint64_t * const vaddr = kmap_page_dma(p); | |
373 | ||
374 | for (i = 0; i < 512; i++) | |
375 | vaddr[i] = val; | |
376 | ||
377 | kunmap_page_dma(dev, vaddr); | |
378 | } | |
379 | ||
73eeea53 MK |
380 | static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p, |
381 | const uint32_t val32) | |
382 | { | |
383 | uint64_t v = val32; | |
384 | ||
385 | v = v << 32 | val32; | |
386 | ||
387 | fill_page_dma(dev, p, v); | |
388 | } | |
389 | ||
4ad2af1e MK |
390 | static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev) |
391 | { | |
392 | struct i915_page_scratch *sp; | |
393 | int ret; | |
394 | ||
395 | sp = kzalloc(sizeof(*sp), GFP_KERNEL); | |
396 | if (sp == NULL) | |
397 | return ERR_PTR(-ENOMEM); | |
398 | ||
399 | ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO); | |
400 | if (ret) { | |
401 | kfree(sp); | |
402 | return ERR_PTR(ret); | |
403 | } | |
404 | ||
405 | set_pages_uc(px_page(sp), 1); | |
406 | ||
407 | return sp; | |
408 | } | |
409 | ||
410 | static void free_scratch_page(struct drm_device *dev, | |
411 | struct i915_page_scratch *sp) | |
412 | { | |
413 | set_pages_wb(px_page(sp), 1); | |
414 | ||
415 | cleanup_px(dev, sp); | |
416 | kfree(sp); | |
417 | } | |
418 | ||
8a1ebd74 | 419 | static struct i915_page_table *alloc_pt(struct drm_device *dev) |
06fda602 | 420 | { |
ec565b3c | 421 | struct i915_page_table *pt; |
678d96fb BW |
422 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
423 | GEN8_PTES : GEN6_PTES; | |
424 | int ret = -ENOMEM; | |
06fda602 BW |
425 | |
426 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
427 | if (!pt) | |
428 | return ERR_PTR(-ENOMEM); | |
429 | ||
678d96fb BW |
430 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
431 | GFP_KERNEL); | |
432 | ||
433 | if (!pt->used_ptes) | |
434 | goto fail_bitmap; | |
435 | ||
567047be | 436 | ret = setup_px(dev, pt); |
678d96fb | 437 | if (ret) |
44159ddb | 438 | goto fail_page_m; |
06fda602 BW |
439 | |
440 | return pt; | |
678d96fb | 441 | |
44159ddb | 442 | fail_page_m: |
678d96fb BW |
443 | kfree(pt->used_ptes); |
444 | fail_bitmap: | |
445 | kfree(pt); | |
446 | ||
447 | return ERR_PTR(ret); | |
06fda602 BW |
448 | } |
449 | ||
2e906bea | 450 | static void free_pt(struct drm_device *dev, struct i915_page_table *pt) |
06fda602 | 451 | { |
2e906bea MK |
452 | cleanup_px(dev, pt); |
453 | kfree(pt->used_ptes); | |
454 | kfree(pt); | |
455 | } | |
456 | ||
457 | static void gen8_initialize_pt(struct i915_address_space *vm, | |
458 | struct i915_page_table *pt) | |
459 | { | |
460 | gen8_pte_t scratch_pte; | |
461 | ||
462 | scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), | |
463 | I915_CACHE_LLC, true); | |
464 | ||
465 | fill_px(vm->dev, pt, scratch_pte); | |
466 | } | |
467 | ||
468 | static void gen6_initialize_pt(struct i915_address_space *vm, | |
469 | struct i915_page_table *pt) | |
470 | { | |
471 | gen6_pte_t scratch_pte; | |
472 | ||
473 | WARN_ON(px_dma(vm->scratch_page) == 0); | |
474 | ||
475 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), | |
476 | I915_CACHE_LLC, true, 0); | |
477 | ||
478 | fill32_px(vm->dev, pt, scratch_pte); | |
06fda602 BW |
479 | } |
480 | ||
8a1ebd74 | 481 | static struct i915_page_directory *alloc_pd(struct drm_device *dev) |
06fda602 | 482 | { |
ec565b3c | 483 | struct i915_page_directory *pd; |
33c8819f | 484 | int ret = -ENOMEM; |
06fda602 BW |
485 | |
486 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
487 | if (!pd) | |
488 | return ERR_PTR(-ENOMEM); | |
489 | ||
33c8819f MT |
490 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
491 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
492 | if (!pd->used_pdes) | |
a08e111a | 493 | goto fail_bitmap; |
33c8819f | 494 | |
567047be | 495 | ret = setup_px(dev, pd); |
33c8819f | 496 | if (ret) |
a08e111a | 497 | goto fail_page_m; |
e5815a2e | 498 | |
06fda602 | 499 | return pd; |
33c8819f | 500 | |
a08e111a | 501 | fail_page_m: |
33c8819f | 502 | kfree(pd->used_pdes); |
a08e111a | 503 | fail_bitmap: |
33c8819f MT |
504 | kfree(pd); |
505 | ||
506 | return ERR_PTR(ret); | |
06fda602 BW |
507 | } |
508 | ||
2e906bea MK |
509 | static void free_pd(struct drm_device *dev, struct i915_page_directory *pd) |
510 | { | |
511 | if (px_page(pd)) { | |
512 | cleanup_px(dev, pd); | |
513 | kfree(pd->used_pdes); | |
514 | kfree(pd); | |
515 | } | |
516 | } | |
517 | ||
518 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
519 | struct i915_page_directory *pd) | |
520 | { | |
521 | gen8_pde_t scratch_pde; | |
522 | ||
523 | scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); | |
524 | ||
525 | fill_px(vm->dev, pd, scratch_pde); | |
526 | } | |
527 | ||
6ac18502 MT |
528 | static int __pdp_init(struct drm_device *dev, |
529 | struct i915_page_directory_pointer *pdp) | |
530 | { | |
531 | size_t pdpes = I915_PDPES_PER_PDP(dev); | |
532 | ||
533 | pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes), | |
534 | sizeof(unsigned long), | |
535 | GFP_KERNEL); | |
536 | if (!pdp->used_pdpes) | |
537 | return -ENOMEM; | |
538 | ||
539 | pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory), | |
540 | GFP_KERNEL); | |
541 | if (!pdp->page_directory) { | |
542 | kfree(pdp->used_pdpes); | |
543 | /* the PDP might be the statically allocated top level. Keep it | |
544 | * as clean as possible */ | |
545 | pdp->used_pdpes = NULL; | |
546 | return -ENOMEM; | |
547 | } | |
548 | ||
549 | return 0; | |
550 | } | |
551 | ||
552 | static void __pdp_fini(struct i915_page_directory_pointer *pdp) | |
553 | { | |
554 | kfree(pdp->used_pdpes); | |
555 | kfree(pdp->page_directory); | |
556 | pdp->page_directory = NULL; | |
557 | } | |
558 | ||
762d9936 MT |
559 | static struct |
560 | i915_page_directory_pointer *alloc_pdp(struct drm_device *dev) | |
561 | { | |
562 | struct i915_page_directory_pointer *pdp; | |
563 | int ret = -ENOMEM; | |
564 | ||
565 | WARN_ON(!USES_FULL_48BIT_PPGTT(dev)); | |
566 | ||
567 | pdp = kzalloc(sizeof(*pdp), GFP_KERNEL); | |
568 | if (!pdp) | |
569 | return ERR_PTR(-ENOMEM); | |
570 | ||
571 | ret = __pdp_init(dev, pdp); | |
572 | if (ret) | |
573 | goto fail_bitmap; | |
574 | ||
575 | ret = setup_px(dev, pdp); | |
576 | if (ret) | |
577 | goto fail_page_m; | |
578 | ||
579 | return pdp; | |
580 | ||
581 | fail_page_m: | |
582 | __pdp_fini(pdp); | |
583 | fail_bitmap: | |
584 | kfree(pdp); | |
585 | ||
586 | return ERR_PTR(ret); | |
587 | } | |
588 | ||
6ac18502 MT |
589 | static void free_pdp(struct drm_device *dev, |
590 | struct i915_page_directory_pointer *pdp) | |
591 | { | |
592 | __pdp_fini(pdp); | |
762d9936 MT |
593 | if (USES_FULL_48BIT_PPGTT(dev)) { |
594 | cleanup_px(dev, pdp); | |
595 | kfree(pdp); | |
596 | } | |
597 | } | |
598 | ||
599 | static void | |
600 | gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt, | |
601 | struct i915_page_directory_pointer *pdp, | |
602 | struct i915_page_directory *pd, | |
603 | int index) | |
604 | { | |
605 | gen8_ppgtt_pdpe_t *page_directorypo; | |
606 | ||
607 | if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
608 | return; | |
609 | ||
610 | page_directorypo = kmap_px(pdp); | |
611 | page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC); | |
612 | kunmap_px(ppgtt, page_directorypo); | |
613 | } | |
614 | ||
615 | static void | |
616 | gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt, | |
617 | struct i915_pml4 *pml4, | |
618 | struct i915_page_directory_pointer *pdp, | |
619 | int index) | |
620 | { | |
621 | gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4); | |
622 | ||
623 | WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)); | |
624 | pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC); | |
625 | kunmap_px(ppgtt, pagemap); | |
6ac18502 MT |
626 | } |
627 | ||
94e409c1 | 628 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 629 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
630 | unsigned entry, |
631 | dma_addr_t addr) | |
94e409c1 | 632 | { |
e85b26dc | 633 | struct intel_engine_cs *ring = req->ring; |
94e409c1 BW |
634 | int ret; |
635 | ||
636 | BUG_ON(entry >= 4); | |
637 | ||
5fb9de1a | 638 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
639 | if (ret) |
640 | return ret; | |
641 | ||
642 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
643 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
7cb6d7ac | 644 | intel_ring_emit(ring, upper_32_bits(addr)); |
94e409c1 BW |
645 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
646 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
7cb6d7ac | 647 | intel_ring_emit(ring, lower_32_bits(addr)); |
94e409c1 BW |
648 | intel_ring_advance(ring); |
649 | ||
650 | return 0; | |
651 | } | |
652 | ||
eeb9488e | 653 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 654 | struct drm_i915_gem_request *req) |
94e409c1 | 655 | { |
eeb9488e | 656 | int i, ret; |
94e409c1 | 657 | |
7cb6d7ac | 658 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
659 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
660 | ||
e85b26dc | 661 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
662 | if (ret) |
663 | return ret; | |
94e409c1 | 664 | } |
d595bd4b | 665 | |
eeb9488e | 666 | return 0; |
94e409c1 BW |
667 | } |
668 | ||
f9b5b782 MT |
669 | static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm, |
670 | struct i915_page_directory_pointer *pdp, | |
671 | uint64_t start, | |
672 | uint64_t length, | |
673 | gen8_pte_t scratch_pte) | |
459108b8 BW |
674 | { |
675 | struct i915_hw_ppgtt *ppgtt = | |
676 | container_of(vm, struct i915_hw_ppgtt, base); | |
f9b5b782 | 677 | gen8_pte_t *pt_vaddr; |
7ad47cf2 BW |
678 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
679 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
680 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 681 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
682 | unsigned last_pte, i; |
683 | ||
f9b5b782 MT |
684 | if (WARN_ON(!pdp)) |
685 | return; | |
459108b8 BW |
686 | |
687 | while (num_entries) { | |
ec565b3c MT |
688 | struct i915_page_directory *pd; |
689 | struct i915_page_table *pt; | |
06fda602 | 690 | |
d4ec9da0 | 691 | if (WARN_ON(!pdp->page_directory[pdpe])) |
00245266 | 692 | break; |
06fda602 | 693 | |
d4ec9da0 | 694 | pd = pdp->page_directory[pdpe]; |
06fda602 BW |
695 | |
696 | if (WARN_ON(!pd->page_table[pde])) | |
00245266 | 697 | break; |
06fda602 BW |
698 | |
699 | pt = pd->page_table[pde]; | |
700 | ||
567047be | 701 | if (WARN_ON(!px_page(pt))) |
00245266 | 702 | break; |
06fda602 | 703 | |
7ad47cf2 | 704 | last_pte = pte + num_entries; |
07749ef3 MT |
705 | if (last_pte > GEN8_PTES) |
706 | last_pte = GEN8_PTES; | |
459108b8 | 707 | |
d1c54acd | 708 | pt_vaddr = kmap_px(pt); |
459108b8 | 709 | |
7ad47cf2 | 710 | for (i = pte; i < last_pte; i++) { |
459108b8 | 711 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
712 | num_entries--; |
713 | } | |
459108b8 | 714 | |
d1c54acd | 715 | kunmap_px(ppgtt, pt); |
459108b8 | 716 | |
7ad47cf2 | 717 | pte = 0; |
07749ef3 | 718 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
719 | pdpe++; |
720 | pde = 0; | |
721 | } | |
459108b8 BW |
722 | } |
723 | } | |
724 | ||
f9b5b782 MT |
725 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
726 | uint64_t start, | |
727 | uint64_t length, | |
728 | bool use_scratch) | |
9df15b49 BW |
729 | { |
730 | struct i915_hw_ppgtt *ppgtt = | |
731 | container_of(vm, struct i915_hw_ppgtt, base); | |
d4ec9da0 | 732 | struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */ |
f9b5b782 MT |
733 | |
734 | gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), | |
735 | I915_CACHE_LLC, use_scratch); | |
736 | ||
737 | gen8_ppgtt_clear_pte_range(vm, pdp, start, length, scratch_pte); | |
738 | } | |
739 | ||
740 | static void | |
741 | gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm, | |
742 | struct i915_page_directory_pointer *pdp, | |
743 | struct sg_table *pages, | |
744 | uint64_t start, | |
745 | enum i915_cache_level cache_level) | |
746 | { | |
747 | struct i915_hw_ppgtt *ppgtt = | |
748 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 749 | gen8_pte_t *pt_vaddr; |
7ad47cf2 BW |
750 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
751 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
752 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
753 | struct sg_page_iter sg_iter; |
754 | ||
6f1cc993 | 755 | pt_vaddr = NULL; |
7ad47cf2 | 756 | |
9df15b49 | 757 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
76643600 | 758 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) |
7ad47cf2 BW |
759 | break; |
760 | ||
d7b3de91 | 761 | if (pt_vaddr == NULL) { |
d4ec9da0 | 762 | struct i915_page_directory *pd = pdp->page_directory[pdpe]; |
ec565b3c | 763 | struct i915_page_table *pt = pd->page_table[pde]; |
d1c54acd | 764 | pt_vaddr = kmap_px(pt); |
d7b3de91 | 765 | } |
9df15b49 | 766 | |
7ad47cf2 | 767 | pt_vaddr[pte] = |
6f1cc993 CW |
768 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
769 | cache_level, true); | |
07749ef3 | 770 | if (++pte == GEN8_PTES) { |
d1c54acd | 771 | kunmap_px(ppgtt, pt_vaddr); |
6f1cc993 | 772 | pt_vaddr = NULL; |
07749ef3 | 773 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
774 | pdpe++; |
775 | pde = 0; | |
776 | } | |
777 | pte = 0; | |
9df15b49 BW |
778 | } |
779 | } | |
d1c54acd MK |
780 | |
781 | if (pt_vaddr) | |
782 | kunmap_px(ppgtt, pt_vaddr); | |
9df15b49 BW |
783 | } |
784 | ||
f9b5b782 MT |
785 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
786 | struct sg_table *pages, | |
787 | uint64_t start, | |
788 | enum i915_cache_level cache_level, | |
789 | u32 unused) | |
790 | { | |
791 | struct i915_hw_ppgtt *ppgtt = | |
792 | container_of(vm, struct i915_hw_ppgtt, base); | |
793 | struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */ | |
794 | ||
795 | gen8_ppgtt_insert_pte_entries(vm, pdp, pages, start, cache_level); | |
796 | } | |
797 | ||
f37c0505 MT |
798 | static void gen8_free_page_tables(struct drm_device *dev, |
799 | struct i915_page_directory *pd) | |
7ad47cf2 BW |
800 | { |
801 | int i; | |
802 | ||
567047be | 803 | if (!px_page(pd)) |
7ad47cf2 BW |
804 | return; |
805 | ||
33c8819f | 806 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
807 | if (WARN_ON(!pd->page_table[i])) |
808 | continue; | |
7ad47cf2 | 809 | |
a08e111a | 810 | free_pt(dev, pd->page_table[i]); |
06fda602 BW |
811 | pd->page_table[i] = NULL; |
812 | } | |
d7b3de91 BW |
813 | } |
814 | ||
8776f02b MK |
815 | static int gen8_init_scratch(struct i915_address_space *vm) |
816 | { | |
817 | struct drm_device *dev = vm->dev; | |
818 | ||
819 | vm->scratch_page = alloc_scratch_page(dev); | |
820 | if (IS_ERR(vm->scratch_page)) | |
821 | return PTR_ERR(vm->scratch_page); | |
822 | ||
823 | vm->scratch_pt = alloc_pt(dev); | |
824 | if (IS_ERR(vm->scratch_pt)) { | |
825 | free_scratch_page(dev, vm->scratch_page); | |
826 | return PTR_ERR(vm->scratch_pt); | |
827 | } | |
828 | ||
829 | vm->scratch_pd = alloc_pd(dev); | |
830 | if (IS_ERR(vm->scratch_pd)) { | |
831 | free_pt(dev, vm->scratch_pt); | |
832 | free_scratch_page(dev, vm->scratch_page); | |
833 | return PTR_ERR(vm->scratch_pd); | |
834 | } | |
835 | ||
836 | gen8_initialize_pt(vm, vm->scratch_pt); | |
837 | gen8_initialize_pd(vm, vm->scratch_pd); | |
838 | ||
839 | return 0; | |
840 | } | |
841 | ||
842 | static void gen8_free_scratch(struct i915_address_space *vm) | |
843 | { | |
844 | struct drm_device *dev = vm->dev; | |
845 | ||
846 | free_pd(dev, vm->scratch_pd); | |
847 | free_pt(dev, vm->scratch_pt); | |
848 | free_scratch_page(dev, vm->scratch_page); | |
849 | } | |
850 | ||
762d9936 MT |
851 | static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev, |
852 | struct i915_page_directory_pointer *pdp) | |
b45a6715 BW |
853 | { |
854 | int i; | |
855 | ||
d4ec9da0 MT |
856 | for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) { |
857 | if (WARN_ON(!pdp->page_directory[i])) | |
06fda602 BW |
858 | continue; |
859 | ||
d4ec9da0 MT |
860 | gen8_free_page_tables(dev, pdp->page_directory[i]); |
861 | free_pd(dev, pdp->page_directory[i]); | |
7ad47cf2 | 862 | } |
69876bed | 863 | |
d4ec9da0 | 864 | free_pdp(dev, pdp); |
762d9936 MT |
865 | } |
866 | ||
867 | static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt) | |
868 | { | |
869 | int i; | |
870 | ||
871 | for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) { | |
872 | if (WARN_ON(!ppgtt->pml4.pdps[i])) | |
873 | continue; | |
874 | ||
875 | gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]); | |
876 | } | |
877 | ||
878 | cleanup_px(ppgtt->base.dev, &ppgtt->pml4); | |
879 | } | |
880 | ||
881 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) | |
882 | { | |
883 | struct i915_hw_ppgtt *ppgtt = | |
884 | container_of(vm, struct i915_hw_ppgtt, base); | |
885 | ||
886 | if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
887 | gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp); | |
888 | else | |
889 | gen8_ppgtt_cleanup_4lvl(ppgtt); | |
d4ec9da0 | 890 | |
8776f02b | 891 | gen8_free_scratch(vm); |
b45a6715 BW |
892 | } |
893 | ||
d7b2633d MT |
894 | /** |
895 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
d4ec9da0 MT |
896 | * @vm: Master vm structure. |
897 | * @pd: Page directory for this address range. | |
d7b2633d | 898 | * @start: Starting virtual address to begin allocations. |
d4ec9da0 | 899 | * @length: Size of the allocations. |
d7b2633d MT |
900 | * @new_pts: Bitmap set by function with new allocations. Likely used by the |
901 | * caller to free on error. | |
902 | * | |
903 | * Allocate the required number of page tables. Extremely similar to | |
904 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
905 | * the page directory boundary (instead of the page directory pointer). That | |
906 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
907 | * possible, and likely that the caller will need to use multiple calls of this | |
908 | * function to achieve the appropriate allocation. | |
909 | * | |
910 | * Return: 0 if success; negative error code otherwise. | |
911 | */ | |
d4ec9da0 | 912 | static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm, |
e5815a2e | 913 | struct i915_page_directory *pd, |
5441f0cb | 914 | uint64_t start, |
d7b2633d MT |
915 | uint64_t length, |
916 | unsigned long *new_pts) | |
bf2b4ed2 | 917 | { |
d4ec9da0 | 918 | struct drm_device *dev = vm->dev; |
d7b2633d | 919 | struct i915_page_table *pt; |
5441f0cb MT |
920 | uint64_t temp; |
921 | uint32_t pde; | |
bf2b4ed2 | 922 | |
d7b2633d MT |
923 | gen8_for_each_pde(pt, pd, start, length, temp, pde) { |
924 | /* Don't reallocate page tables */ | |
6ac18502 | 925 | if (test_bit(pde, pd->used_pdes)) { |
d7b2633d | 926 | /* Scratch is never allocated this way */ |
d4ec9da0 | 927 | WARN_ON(pt == vm->scratch_pt); |
d7b2633d MT |
928 | continue; |
929 | } | |
930 | ||
8a1ebd74 | 931 | pt = alloc_pt(dev); |
d7b2633d | 932 | if (IS_ERR(pt)) |
5441f0cb MT |
933 | goto unwind_out; |
934 | ||
d4ec9da0 | 935 | gen8_initialize_pt(vm, pt); |
d7b2633d | 936 | pd->page_table[pde] = pt; |
966082c9 | 937 | __set_bit(pde, new_pts); |
4c06ec8d | 938 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT); |
7ad47cf2 BW |
939 | } |
940 | ||
bf2b4ed2 | 941 | return 0; |
7ad47cf2 BW |
942 | |
943 | unwind_out: | |
d7b2633d | 944 | for_each_set_bit(pde, new_pts, I915_PDES) |
a08e111a | 945 | free_pt(dev, pd->page_table[pde]); |
7ad47cf2 | 946 | |
d7b3de91 | 947 | return -ENOMEM; |
bf2b4ed2 BW |
948 | } |
949 | ||
d7b2633d MT |
950 | /** |
951 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
d4ec9da0 | 952 | * @vm: Master vm structure. |
d7b2633d MT |
953 | * @pdp: Page directory pointer for this address range. |
954 | * @start: Starting virtual address to begin allocations. | |
d4ec9da0 MT |
955 | * @length: Size of the allocations. |
956 | * @new_pds: Bitmap set by function with new allocations. Likely used by the | |
d7b2633d MT |
957 | * caller to free on error. |
958 | * | |
959 | * Allocate the required number of page directories starting at the pde index of | |
960 | * @start, and ending at the pde index @start + @length. This function will skip | |
961 | * over already allocated page directories within the range, and only allocate | |
962 | * new ones, setting the appropriate pointer within the pdp as well as the | |
963 | * correct position in the bitmap @new_pds. | |
964 | * | |
965 | * The function will only allocate the pages within the range for a give page | |
966 | * directory pointer. In other words, if @start + @length straddles a virtually | |
967 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
968 | * required by the caller, This is not currently possible, and the BUG in the | |
969 | * code will prevent it. | |
970 | * | |
971 | * Return: 0 if success; negative error code otherwise. | |
972 | */ | |
d4ec9da0 MT |
973 | static int |
974 | gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm, | |
975 | struct i915_page_directory_pointer *pdp, | |
976 | uint64_t start, | |
977 | uint64_t length, | |
978 | unsigned long *new_pds) | |
bf2b4ed2 | 979 | { |
d4ec9da0 | 980 | struct drm_device *dev = vm->dev; |
d7b2633d | 981 | struct i915_page_directory *pd; |
69876bed MT |
982 | uint64_t temp; |
983 | uint32_t pdpe; | |
6ac18502 | 984 | uint32_t pdpes = I915_PDPES_PER_PDP(dev); |
69876bed | 985 | |
6ac18502 | 986 | WARN_ON(!bitmap_empty(new_pds, pdpes)); |
d7b2633d | 987 | |
d7b2633d | 988 | gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { |
6ac18502 | 989 | if (test_bit(pdpe, pdp->used_pdpes)) |
d7b2633d | 990 | continue; |
33c8819f | 991 | |
8a1ebd74 | 992 | pd = alloc_pd(dev); |
d7b2633d | 993 | if (IS_ERR(pd)) |
d7b3de91 | 994 | goto unwind_out; |
69876bed | 995 | |
d4ec9da0 | 996 | gen8_initialize_pd(vm, pd); |
d7b2633d | 997 | pdp->page_directory[pdpe] = pd; |
966082c9 | 998 | __set_bit(pdpe, new_pds); |
4c06ec8d | 999 | trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT); |
d7b3de91 BW |
1000 | } |
1001 | ||
bf2b4ed2 | 1002 | return 0; |
d7b3de91 BW |
1003 | |
1004 | unwind_out: | |
6ac18502 | 1005 | for_each_set_bit(pdpe, new_pds, pdpes) |
a08e111a | 1006 | free_pd(dev, pdp->page_directory[pdpe]); |
d7b3de91 BW |
1007 | |
1008 | return -ENOMEM; | |
bf2b4ed2 BW |
1009 | } |
1010 | ||
762d9936 MT |
1011 | /** |
1012 | * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range. | |
1013 | * @vm: Master vm structure. | |
1014 | * @pml4: Page map level 4 for this address range. | |
1015 | * @start: Starting virtual address to begin allocations. | |
1016 | * @length: Size of the allocations. | |
1017 | * @new_pdps: Bitmap set by function with new allocations. Likely used by the | |
1018 | * caller to free on error. | |
1019 | * | |
1020 | * Allocate the required number of page directory pointers. Extremely similar to | |
1021 | * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs(). | |
1022 | * The main difference is here we are limited by the pml4 boundary (instead of | |
1023 | * the page directory pointer). | |
1024 | * | |
1025 | * Return: 0 if success; negative error code otherwise. | |
1026 | */ | |
1027 | static int | |
1028 | gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm, | |
1029 | struct i915_pml4 *pml4, | |
1030 | uint64_t start, | |
1031 | uint64_t length, | |
1032 | unsigned long *new_pdps) | |
1033 | { | |
1034 | struct drm_device *dev = vm->dev; | |
1035 | struct i915_page_directory_pointer *pdp; | |
1036 | uint64_t temp; | |
1037 | uint32_t pml4e; | |
1038 | ||
1039 | WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4)); | |
1040 | ||
1041 | gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) { | |
1042 | if (!test_bit(pml4e, pml4->used_pml4es)) { | |
1043 | pdp = alloc_pdp(dev); | |
1044 | if (IS_ERR(pdp)) | |
1045 | goto unwind_out; | |
1046 | ||
1047 | pml4->pdps[pml4e] = pdp; | |
1048 | __set_bit(pml4e, new_pdps); | |
1049 | trace_i915_page_directory_pointer_entry_alloc(vm, | |
1050 | pml4e, | |
1051 | start, | |
1052 | GEN8_PML4E_SHIFT); | |
1053 | } | |
1054 | } | |
1055 | ||
1056 | return 0; | |
1057 | ||
1058 | unwind_out: | |
1059 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
1060 | free_pdp(dev, pml4->pdps[pml4e]); | |
1061 | ||
1062 | return -ENOMEM; | |
1063 | } | |
1064 | ||
d7b2633d | 1065 | static void |
6ac18502 MT |
1066 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts, |
1067 | uint32_t pdpes) | |
d7b2633d MT |
1068 | { |
1069 | int i; | |
1070 | ||
6ac18502 | 1071 | for (i = 0; i < pdpes; i++) |
d7b2633d MT |
1072 | kfree(new_pts[i]); |
1073 | kfree(new_pts); | |
1074 | kfree(new_pds); | |
1075 | } | |
1076 | ||
1077 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
1078 | * of these are based on the number of PDPEs in the system. | |
1079 | */ | |
1080 | static | |
1081 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
6ac18502 MT |
1082 | unsigned long ***new_pts, |
1083 | uint32_t pdpes) | |
d7b2633d MT |
1084 | { |
1085 | int i; | |
1086 | unsigned long *pds; | |
1087 | unsigned long **pts; | |
1088 | ||
6ac18502 | 1089 | pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_KERNEL); |
d7b2633d MT |
1090 | if (!pds) |
1091 | return -ENOMEM; | |
1092 | ||
6ac18502 | 1093 | pts = kcalloc(pdpes, sizeof(unsigned long *), GFP_KERNEL); |
d7b2633d MT |
1094 | if (!pts) { |
1095 | kfree(pds); | |
1096 | return -ENOMEM; | |
1097 | } | |
1098 | ||
6ac18502 | 1099 | for (i = 0; i < pdpes; i++) { |
d7b2633d MT |
1100 | pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES), |
1101 | sizeof(unsigned long), GFP_KERNEL); | |
1102 | if (!pts[i]) | |
1103 | goto err_out; | |
1104 | } | |
1105 | ||
1106 | *new_pds = pds; | |
1107 | *new_pts = pts; | |
1108 | ||
1109 | return 0; | |
1110 | ||
1111 | err_out: | |
6ac18502 | 1112 | free_gen8_temp_bitmaps(pds, pts, pdpes); |
d7b2633d MT |
1113 | return -ENOMEM; |
1114 | } | |
1115 | ||
5b7e4c9c MK |
1116 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
1117 | * the page table structures, we mark them dirty so that | |
1118 | * context switching/execlist queuing code takes extra steps | |
1119 | * to ensure that tlbs are flushed. | |
1120 | */ | |
1121 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
1122 | { | |
1123 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; | |
1124 | } | |
1125 | ||
762d9936 MT |
1126 | static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm, |
1127 | struct i915_page_directory_pointer *pdp, | |
1128 | uint64_t start, | |
1129 | uint64_t length) | |
bf2b4ed2 | 1130 | { |
e5815a2e MT |
1131 | struct i915_hw_ppgtt *ppgtt = |
1132 | container_of(vm, struct i915_hw_ppgtt, base); | |
d7b2633d | 1133 | unsigned long *new_page_dirs, **new_page_tables; |
d4ec9da0 | 1134 | struct drm_device *dev = vm->dev; |
5441f0cb | 1135 | struct i915_page_directory *pd; |
33c8819f MT |
1136 | const uint64_t orig_start = start; |
1137 | const uint64_t orig_length = length; | |
5441f0cb MT |
1138 | uint64_t temp; |
1139 | uint32_t pdpe; | |
d4ec9da0 | 1140 | uint32_t pdpes = I915_PDPES_PER_PDP(dev); |
bf2b4ed2 BW |
1141 | int ret; |
1142 | ||
d7b2633d MT |
1143 | /* Wrap is never okay since we can only represent 48b, and we don't |
1144 | * actually use the other side of the canonical address space. | |
1145 | */ | |
1146 | if (WARN_ON(start + length < start)) | |
a05d80ee MK |
1147 | return -ENODEV; |
1148 | ||
d4ec9da0 | 1149 | if (WARN_ON(start + length > vm->total)) |
a05d80ee | 1150 | return -ENODEV; |
d7b2633d | 1151 | |
6ac18502 | 1152 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes); |
bf2b4ed2 BW |
1153 | if (ret) |
1154 | return ret; | |
1155 | ||
d7b2633d | 1156 | /* Do the allocations first so we can easily bail out */ |
d4ec9da0 MT |
1157 | ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length, |
1158 | new_page_dirs); | |
d7b2633d | 1159 | if (ret) { |
6ac18502 | 1160 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes); |
d7b2633d MT |
1161 | return ret; |
1162 | } | |
1163 | ||
1164 | /* For every page directory referenced, allocate page tables */ | |
d4ec9da0 MT |
1165 | gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { |
1166 | ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length, | |
d7b2633d | 1167 | new_page_tables[pdpe]); |
5441f0cb MT |
1168 | if (ret) |
1169 | goto err_out; | |
5441f0cb MT |
1170 | } |
1171 | ||
33c8819f MT |
1172 | start = orig_start; |
1173 | length = orig_length; | |
1174 | ||
d7b2633d MT |
1175 | /* Allocations have completed successfully, so set the bitmaps, and do |
1176 | * the mappings. */ | |
d4ec9da0 | 1177 | gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { |
d1c54acd | 1178 | gen8_pde_t *const page_directory = kmap_px(pd); |
33c8819f | 1179 | struct i915_page_table *pt; |
09120d4e | 1180 | uint64_t pd_len = length; |
33c8819f MT |
1181 | uint64_t pd_start = start; |
1182 | uint32_t pde; | |
1183 | ||
d7b2633d MT |
1184 | /* Every pd should be allocated, we just did that above. */ |
1185 | WARN_ON(!pd); | |
1186 | ||
1187 | gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) { | |
1188 | /* Same reasoning as pd */ | |
1189 | WARN_ON(!pt); | |
1190 | WARN_ON(!pd_len); | |
1191 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
1192 | ||
1193 | /* Set our used ptes within the page table */ | |
1194 | bitmap_set(pt->used_ptes, | |
1195 | gen8_pte_index(pd_start), | |
1196 | gen8_pte_count(pd_start, pd_len)); | |
1197 | ||
1198 | /* Our pde is now pointing to the pagetable, pt */ | |
966082c9 | 1199 | __set_bit(pde, pd->used_pdes); |
d7b2633d MT |
1200 | |
1201 | /* Map the PDE to the page table */ | |
fe36f55d MK |
1202 | page_directory[pde] = gen8_pde_encode(px_dma(pt), |
1203 | I915_CACHE_LLC); | |
4c06ec8d MT |
1204 | trace_i915_page_table_entry_map(&ppgtt->base, pde, pt, |
1205 | gen8_pte_index(start), | |
1206 | gen8_pte_count(start, length), | |
1207 | GEN8_PTES); | |
d7b2633d MT |
1208 | |
1209 | /* NB: We haven't yet mapped ptes to pages. At this | |
1210 | * point we're still relying on insert_entries() */ | |
33c8819f | 1211 | } |
d7b2633d | 1212 | |
d1c54acd | 1213 | kunmap_px(ppgtt, page_directory); |
d4ec9da0 | 1214 | __set_bit(pdpe, pdp->used_pdpes); |
762d9936 | 1215 | gen8_setup_page_directory(ppgtt, pdp, pd, pdpe); |
33c8819f MT |
1216 | } |
1217 | ||
6ac18502 | 1218 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes); |
5b7e4c9c | 1219 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 1220 | return 0; |
bf2b4ed2 | 1221 | |
d7b3de91 | 1222 | err_out: |
d7b2633d MT |
1223 | while (pdpe--) { |
1224 | for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES) | |
d4ec9da0 | 1225 | free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]); |
d7b2633d MT |
1226 | } |
1227 | ||
6ac18502 | 1228 | for_each_set_bit(pdpe, new_page_dirs, pdpes) |
d4ec9da0 | 1229 | free_pd(dev, pdp->page_directory[pdpe]); |
d7b2633d | 1230 | |
6ac18502 | 1231 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes); |
5b7e4c9c | 1232 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
1233 | return ret; |
1234 | } | |
1235 | ||
762d9936 MT |
1236 | static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm, |
1237 | struct i915_pml4 *pml4, | |
1238 | uint64_t start, | |
1239 | uint64_t length) | |
1240 | { | |
1241 | DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4); | |
1242 | struct i915_hw_ppgtt *ppgtt = | |
1243 | container_of(vm, struct i915_hw_ppgtt, base); | |
1244 | struct i915_page_directory_pointer *pdp; | |
1245 | uint64_t temp, pml4e; | |
1246 | int ret = 0; | |
1247 | ||
1248 | /* Do the pml4 allocations first, so we don't need to track the newly | |
1249 | * allocated tables below the pdp */ | |
1250 | bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4); | |
1251 | ||
1252 | /* The pagedirectory and pagetable allocations are done in the shared 3 | |
1253 | * and 4 level code. Just allocate the pdps. | |
1254 | */ | |
1255 | ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length, | |
1256 | new_pdps); | |
1257 | if (ret) | |
1258 | return ret; | |
1259 | ||
1260 | WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2, | |
1261 | "The allocation has spanned more than 512GB. " | |
1262 | "It is highly likely this is incorrect."); | |
1263 | ||
1264 | gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) { | |
1265 | WARN_ON(!pdp); | |
1266 | ||
1267 | ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length); | |
1268 | if (ret) | |
1269 | goto err_out; | |
1270 | ||
1271 | gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e); | |
1272 | } | |
1273 | ||
1274 | bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es, | |
1275 | GEN8_PML4ES_PER_PML4); | |
1276 | ||
1277 | return 0; | |
1278 | ||
1279 | err_out: | |
1280 | for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4) | |
1281 | gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]); | |
1282 | ||
1283 | return ret; | |
1284 | } | |
1285 | ||
1286 | static int gen8_alloc_va_range(struct i915_address_space *vm, | |
1287 | uint64_t start, uint64_t length) | |
1288 | { | |
1289 | struct i915_hw_ppgtt *ppgtt = | |
1290 | container_of(vm, struct i915_hw_ppgtt, base); | |
1291 | ||
1292 | if (USES_FULL_48BIT_PPGTT(vm->dev)) | |
1293 | return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length); | |
1294 | else | |
1295 | return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length); | |
1296 | } | |
1297 | ||
eb0b44ad | 1298 | /* |
f3a964b9 BW |
1299 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
1300 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
1301 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
1302 | * space. | |
37aca44a | 1303 | * |
f3a964b9 | 1304 | */ |
5c5f6457 | 1305 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 1306 | { |
8776f02b | 1307 | int ret; |
7cb6d7ac | 1308 | |
8776f02b MK |
1309 | ret = gen8_init_scratch(&ppgtt->base); |
1310 | if (ret) | |
1311 | return ret; | |
69876bed | 1312 | |
d7b2633d | 1313 | ppgtt->base.start = 0; |
d7b2633d | 1314 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 1315 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 1316 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 1317 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
1318 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1319 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
d7b2633d MT |
1320 | |
1321 | ppgtt->switch_mm = gen8_mm_switch; | |
1322 | ||
762d9936 MT |
1323 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
1324 | ret = setup_px(ppgtt->base.dev, &ppgtt->pml4); | |
1325 | if (ret) | |
1326 | goto free_scratch; | |
6ac18502 | 1327 | |
762d9936 MT |
1328 | ppgtt->base.total = 1ULL << 48; |
1329 | } else { | |
1330 | ret = __pdp_init(false, &ppgtt->pdp); | |
81ba8aef MT |
1331 | if (ret) |
1332 | goto free_scratch; | |
1333 | ||
1334 | ppgtt->base.total = 1ULL << 32; | |
1335 | if (IS_ENABLED(CONFIG_X86_32)) | |
1336 | /* While we have a proliferation of size_t variables | |
1337 | * we cannot represent the full ppgtt size on 32bit, | |
1338 | * so limit it to the same size as the GGTT (currently | |
1339 | * 2GiB). | |
1340 | */ | |
1341 | ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total; | |
762d9936 MT |
1342 | |
1343 | trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base, | |
1344 | 0, 0, | |
1345 | GEN8_PML4E_SHIFT); | |
81ba8aef | 1346 | } |
6ac18502 | 1347 | |
d7b2633d | 1348 | return 0; |
6ac18502 MT |
1349 | |
1350 | free_scratch: | |
1351 | gen8_free_scratch(&ppgtt->base); | |
1352 | return ret; | |
d7b2633d MT |
1353 | } |
1354 | ||
87d60b63 BW |
1355 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
1356 | { | |
87d60b63 | 1357 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 1358 | struct i915_page_table *unused; |
07749ef3 | 1359 | gen6_pte_t scratch_pte; |
87d60b63 | 1360 | uint32_t pd_entry; |
09942c65 MT |
1361 | uint32_t pte, pde, temp; |
1362 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; | |
87d60b63 | 1363 | |
79ab9370 MK |
1364 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
1365 | I915_CACHE_LLC, true, 0); | |
87d60b63 | 1366 | |
09942c65 | 1367 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) { |
87d60b63 | 1368 | u32 expected; |
07749ef3 | 1369 | gen6_pte_t *pt_vaddr; |
567047be | 1370 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
09942c65 | 1371 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
1372 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
1373 | ||
1374 | if (pd_entry != expected) | |
1375 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
1376 | pde, | |
1377 | pd_entry, | |
1378 | expected); | |
1379 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
1380 | ||
d1c54acd MK |
1381 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
1382 | ||
07749ef3 | 1383 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1384 | unsigned long va = |
07749ef3 | 1385 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1386 | (pte * PAGE_SIZE); |
1387 | int i; | |
1388 | bool found = false; | |
1389 | for (i = 0; i < 4; i++) | |
1390 | if (pt_vaddr[pte + i] != scratch_pte) | |
1391 | found = true; | |
1392 | if (!found) | |
1393 | continue; | |
1394 | ||
1395 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1396 | for (i = 0; i < 4; i++) { | |
1397 | if (pt_vaddr[pte + i] != scratch_pte) | |
1398 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1399 | else | |
1400 | seq_puts(m, " SCRATCH "); | |
1401 | } | |
1402 | seq_puts(m, "\n"); | |
1403 | } | |
d1c54acd | 1404 | kunmap_px(ppgtt, pt_vaddr); |
87d60b63 BW |
1405 | } |
1406 | } | |
1407 | ||
678d96fb | 1408 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1409 | static void gen6_write_pde(struct i915_page_directory *pd, |
1410 | const int pde, struct i915_page_table *pt) | |
6197349b | 1411 | { |
678d96fb BW |
1412 | /* Caller needs to make sure the write completes if necessary */ |
1413 | struct i915_hw_ppgtt *ppgtt = | |
1414 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1415 | u32 pd_entry; | |
6197349b | 1416 | |
567047be | 1417 | pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); |
678d96fb | 1418 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1419 | |
678d96fb BW |
1420 | writel(pd_entry, ppgtt->pd_addr + pde); |
1421 | } | |
6197349b | 1422 | |
678d96fb BW |
1423 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1424 | * directories. */ | |
1425 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1426 | struct i915_page_directory *pd, |
678d96fb BW |
1427 | uint32_t start, uint32_t length) |
1428 | { | |
ec565b3c | 1429 | struct i915_page_table *pt; |
678d96fb BW |
1430 | uint32_t pde, temp; |
1431 | ||
1432 | gen6_for_each_pde(pt, pd, start, length, temp, pde) | |
1433 | gen6_write_pde(pd, pde, pt); | |
1434 | ||
1435 | /* Make sure write is complete before other code can use this page | |
1436 | * table. Also require for WC mapped PTEs */ | |
1437 | readl(dev_priv->gtt.gsm); | |
3e302542 BW |
1438 | } |
1439 | ||
b4a74e3a | 1440 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1441 | { |
44159ddb | 1442 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1443 | |
44159ddb | 1444 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1445 | } |
1446 | ||
90252e5c | 1447 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1448 | struct drm_i915_gem_request *req) |
90252e5c | 1449 | { |
e85b26dc | 1450 | struct intel_engine_cs *ring = req->ring; |
90252e5c BW |
1451 | int ret; |
1452 | ||
90252e5c | 1453 | /* NB: TLBs must be flushed and invalidated before a switch */ |
a84c3ae1 | 1454 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
90252e5c BW |
1455 | if (ret) |
1456 | return ret; | |
1457 | ||
5fb9de1a | 1458 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1459 | if (ret) |
1460 | return ret; | |
1461 | ||
1462 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1463 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1464 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1465 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1466 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1467 | intel_ring_emit(ring, MI_NOOP); | |
1468 | intel_ring_advance(ring); | |
1469 | ||
1470 | return 0; | |
1471 | } | |
1472 | ||
71ba2d64 | 1473 | static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1474 | struct drm_i915_gem_request *req) |
71ba2d64 | 1475 | { |
e85b26dc | 1476 | struct intel_engine_cs *ring = req->ring; |
71ba2d64 YZ |
1477 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); |
1478 | ||
1479 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
1480 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1481 | return 0; | |
1482 | } | |
1483 | ||
48a10389 | 1484 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1485 | struct drm_i915_gem_request *req) |
48a10389 | 1486 | { |
e85b26dc | 1487 | struct intel_engine_cs *ring = req->ring; |
48a10389 BW |
1488 | int ret; |
1489 | ||
48a10389 | 1490 | /* NB: TLBs must be flushed and invalidated before a switch */ |
a84c3ae1 | 1491 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
48a10389 BW |
1492 | if (ret) |
1493 | return ret; | |
1494 | ||
5fb9de1a | 1495 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1496 | if (ret) |
1497 | return ret; | |
1498 | ||
1499 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1500 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1501 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1502 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1503 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1504 | intel_ring_emit(ring, MI_NOOP); | |
1505 | intel_ring_advance(ring); | |
1506 | ||
90252e5c BW |
1507 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
1508 | if (ring->id != RCS) { | |
a84c3ae1 | 1509 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
90252e5c BW |
1510 | if (ret) |
1511 | return ret; | |
1512 | } | |
1513 | ||
48a10389 BW |
1514 | return 0; |
1515 | } | |
1516 | ||
eeb9488e | 1517 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1518 | struct drm_i915_gem_request *req) |
eeb9488e | 1519 | { |
e85b26dc | 1520 | struct intel_engine_cs *ring = req->ring; |
eeb9488e BW |
1521 | struct drm_device *dev = ppgtt->base.dev; |
1522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1523 | ||
48a10389 | 1524 | |
eeb9488e BW |
1525 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
1526 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1527 | ||
1528 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
1529 | ||
1530 | return 0; | |
1531 | } | |
1532 | ||
82460d97 | 1533 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 1534 | { |
eeb9488e | 1535 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1536 | struct intel_engine_cs *ring; |
82460d97 | 1537 | int j; |
3e302542 | 1538 | |
eeb9488e BW |
1539 | for_each_ring(ring, dev_priv, j) { |
1540 | I915_WRITE(RING_MODE_GEN7(ring), | |
1541 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 1542 | } |
eeb9488e | 1543 | } |
6197349b | 1544 | |
82460d97 | 1545 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 1546 | { |
50227e1c | 1547 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1548 | struct intel_engine_cs *ring; |
b4a74e3a | 1549 | uint32_t ecochk, ecobits; |
3e302542 | 1550 | int i; |
6197349b | 1551 | |
b4a74e3a BW |
1552 | ecobits = I915_READ(GAC_ECO_BITS); |
1553 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1554 | |
b4a74e3a BW |
1555 | ecochk = I915_READ(GAM_ECOCHK); |
1556 | if (IS_HASWELL(dev)) { | |
1557 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
1558 | } else { | |
1559 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1560 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1561 | } | |
1562 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1563 | |
b4a74e3a | 1564 | for_each_ring(ring, dev_priv, i) { |
6197349b | 1565 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
1566 | I915_WRITE(RING_MODE_GEN7(ring), |
1567 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 1568 | } |
b4a74e3a | 1569 | } |
6197349b | 1570 | |
82460d97 | 1571 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 1572 | { |
50227e1c | 1573 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 1574 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1575 | |
b4a74e3a BW |
1576 | ecobits = I915_READ(GAC_ECO_BITS); |
1577 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1578 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1579 | |
b4a74e3a BW |
1580 | gab_ctl = I915_READ(GAB_CTL); |
1581 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1582 | ||
1583 | ecochk = I915_READ(GAM_ECOCHK); | |
1584 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1585 | ||
1586 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1587 | } |
1588 | ||
1d2a314c | 1589 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1590 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1591 | uint64_t start, |
1592 | uint64_t length, | |
828c7908 | 1593 | bool use_scratch) |
1d2a314c | 1594 | { |
853ba5d2 BW |
1595 | struct i915_hw_ppgtt *ppgtt = |
1596 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1597 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1598 | unsigned first_entry = start >> PAGE_SHIFT; |
1599 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1600 | unsigned act_pt = first_entry / GEN6_PTES; |
1601 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1602 | unsigned last_pte, i; |
1d2a314c | 1603 | |
c114f76a MK |
1604 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
1605 | I915_CACHE_LLC, true, 0); | |
1d2a314c | 1606 | |
7bddb01f DV |
1607 | while (num_entries) { |
1608 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1609 | if (last_pte > GEN6_PTES) |
1610 | last_pte = GEN6_PTES; | |
7bddb01f | 1611 | |
d1c54acd | 1612 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
1d2a314c | 1613 | |
7bddb01f DV |
1614 | for (i = first_pte; i < last_pte; i++) |
1615 | pt_vaddr[i] = scratch_pte; | |
1d2a314c | 1616 | |
d1c54acd | 1617 | kunmap_px(ppgtt, pt_vaddr); |
1d2a314c | 1618 | |
7bddb01f DV |
1619 | num_entries -= last_pte - first_pte; |
1620 | first_pte = 0; | |
a15326a5 | 1621 | act_pt++; |
7bddb01f | 1622 | } |
1d2a314c DV |
1623 | } |
1624 | ||
853ba5d2 | 1625 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1626 | struct sg_table *pages, |
782f1495 | 1627 | uint64_t start, |
24f3a8cf | 1628 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1629 | { |
853ba5d2 BW |
1630 | struct i915_hw_ppgtt *ppgtt = |
1631 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1632 | gen6_pte_t *pt_vaddr; |
782f1495 | 1633 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1634 | unsigned act_pt = first_entry / GEN6_PTES; |
1635 | unsigned act_pte = first_entry % GEN6_PTES; | |
6e995e23 ID |
1636 | struct sg_page_iter sg_iter; |
1637 | ||
cc79714f | 1638 | pt_vaddr = NULL; |
6e995e23 | 1639 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f | 1640 | if (pt_vaddr == NULL) |
d1c54acd | 1641 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
6e995e23 | 1642 | |
cc79714f CW |
1643 | pt_vaddr[act_pte] = |
1644 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
1645 | cache_level, true, flags); |
1646 | ||
07749ef3 | 1647 | if (++act_pte == GEN6_PTES) { |
d1c54acd | 1648 | kunmap_px(ppgtt, pt_vaddr); |
cc79714f | 1649 | pt_vaddr = NULL; |
a15326a5 | 1650 | act_pt++; |
6e995e23 | 1651 | act_pte = 0; |
def886c3 | 1652 | } |
def886c3 | 1653 | } |
cc79714f | 1654 | if (pt_vaddr) |
d1c54acd | 1655 | kunmap_px(ppgtt, pt_vaddr); |
def886c3 DV |
1656 | } |
1657 | ||
678d96fb | 1658 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1659 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1660 | { |
4933d519 MT |
1661 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
1662 | struct drm_device *dev = vm->dev; | |
1663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
678d96fb BW |
1664 | struct i915_hw_ppgtt *ppgtt = |
1665 | container_of(vm, struct i915_hw_ppgtt, base); | |
ec565b3c | 1666 | struct i915_page_table *pt; |
a05d80ee | 1667 | uint32_t start, length, start_save, length_save; |
678d96fb | 1668 | uint32_t pde, temp; |
4933d519 MT |
1669 | int ret; |
1670 | ||
a05d80ee MK |
1671 | if (WARN_ON(start_in + length_in > ppgtt->base.total)) |
1672 | return -ENODEV; | |
1673 | ||
1674 | start = start_save = start_in; | |
1675 | length = length_save = length_in; | |
4933d519 MT |
1676 | |
1677 | bitmap_zero(new_page_tables, I915_PDES); | |
1678 | ||
1679 | /* The allocation is done in two stages so that we can bail out with | |
1680 | * minimal amount of pain. The first stage finds new page tables that | |
1681 | * need allocation. The second stage marks use ptes within the page | |
1682 | * tables. | |
1683 | */ | |
1684 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
79ab9370 | 1685 | if (pt != vm->scratch_pt) { |
4933d519 MT |
1686 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); |
1687 | continue; | |
1688 | } | |
1689 | ||
1690 | /* We've already allocated a page table */ | |
1691 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1692 | ||
8a1ebd74 | 1693 | pt = alloc_pt(dev); |
4933d519 MT |
1694 | if (IS_ERR(pt)) { |
1695 | ret = PTR_ERR(pt); | |
1696 | goto unwind_out; | |
1697 | } | |
1698 | ||
1699 | gen6_initialize_pt(vm, pt); | |
1700 | ||
1701 | ppgtt->pd.page_table[pde] = pt; | |
966082c9 | 1702 | __set_bit(pde, new_page_tables); |
72744cb1 | 1703 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1704 | } |
1705 | ||
1706 | start = start_save; | |
1707 | length = length_save; | |
678d96fb BW |
1708 | |
1709 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1710 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); | |
1711 | ||
1712 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1713 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1714 | gen6_pte_count(start, length)); | |
1715 | ||
966082c9 | 1716 | if (__test_and_clear_bit(pde, new_page_tables)) |
4933d519 MT |
1717 | gen6_write_pde(&ppgtt->pd, pde, pt); |
1718 | ||
72744cb1 MT |
1719 | trace_i915_page_table_entry_map(vm, pde, pt, |
1720 | gen6_pte_index(start), | |
1721 | gen6_pte_count(start, length), | |
1722 | GEN6_PTES); | |
4933d519 | 1723 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1724 | GEN6_PTES); |
1725 | } | |
1726 | ||
4933d519 MT |
1727 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1728 | ||
1729 | /* Make sure write is complete before other code can use this page | |
1730 | * table. Also require for WC mapped PTEs */ | |
1731 | readl(dev_priv->gtt.gsm); | |
1732 | ||
563222a7 | 1733 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1734 | return 0; |
4933d519 MT |
1735 | |
1736 | unwind_out: | |
1737 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1738 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 | 1739 | |
79ab9370 | 1740 | ppgtt->pd.page_table[pde] = vm->scratch_pt; |
a08e111a | 1741 | free_pt(vm->dev, pt); |
4933d519 MT |
1742 | } |
1743 | ||
1744 | mark_tlbs_dirty(ppgtt); | |
1745 | return ret; | |
678d96fb BW |
1746 | } |
1747 | ||
8776f02b MK |
1748 | static int gen6_init_scratch(struct i915_address_space *vm) |
1749 | { | |
1750 | struct drm_device *dev = vm->dev; | |
1751 | ||
1752 | vm->scratch_page = alloc_scratch_page(dev); | |
1753 | if (IS_ERR(vm->scratch_page)) | |
1754 | return PTR_ERR(vm->scratch_page); | |
1755 | ||
1756 | vm->scratch_pt = alloc_pt(dev); | |
1757 | if (IS_ERR(vm->scratch_pt)) { | |
1758 | free_scratch_page(dev, vm->scratch_page); | |
1759 | return PTR_ERR(vm->scratch_pt); | |
1760 | } | |
1761 | ||
1762 | gen6_initialize_pt(vm, vm->scratch_pt); | |
1763 | ||
1764 | return 0; | |
1765 | } | |
1766 | ||
1767 | static void gen6_free_scratch(struct i915_address_space *vm) | |
1768 | { | |
1769 | struct drm_device *dev = vm->dev; | |
1770 | ||
1771 | free_pt(dev, vm->scratch_pt); | |
1772 | free_scratch_page(dev, vm->scratch_page); | |
1773 | } | |
1774 | ||
061dd493 | 1775 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 1776 | { |
061dd493 DV |
1777 | struct i915_hw_ppgtt *ppgtt = |
1778 | container_of(vm, struct i915_hw_ppgtt, base); | |
09942c65 MT |
1779 | struct i915_page_table *pt; |
1780 | uint32_t pde; | |
4933d519 | 1781 | |
061dd493 DV |
1782 | drm_mm_remove_node(&ppgtt->node); |
1783 | ||
09942c65 | 1784 | gen6_for_all_pdes(pt, ppgtt, pde) { |
79ab9370 | 1785 | if (pt != vm->scratch_pt) |
a08e111a | 1786 | free_pt(ppgtt->base.dev, pt); |
4933d519 | 1787 | } |
06fda602 | 1788 | |
8776f02b | 1789 | gen6_free_scratch(vm); |
3440d265 DV |
1790 | } |
1791 | ||
b146520f | 1792 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1793 | { |
8776f02b | 1794 | struct i915_address_space *vm = &ppgtt->base; |
853ba5d2 | 1795 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1796 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1797 | bool retried = false; |
b146520f | 1798 | int ret; |
1d2a314c | 1799 | |
c8d4c0d6 BW |
1800 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1801 | * allocator works in address space sizes, so it's multiplied by page | |
1802 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1803 | */ | |
1804 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
4933d519 | 1805 | |
8776f02b MK |
1806 | ret = gen6_init_scratch(vm); |
1807 | if (ret) | |
1808 | return ret; | |
4933d519 | 1809 | |
e3cc1995 | 1810 | alloc: |
c8d4c0d6 BW |
1811 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1812 | &ppgtt->node, GEN6_PD_SIZE, | |
1813 | GEN6_PD_ALIGN, 0, | |
1814 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1815 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1816 | if (ret == -ENOSPC && !retried) { |
1817 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1818 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1819 | I915_CACHE_NONE, |
1820 | 0, dev_priv->gtt.base.total, | |
1821 | 0); | |
e3cc1995 | 1822 | if (ret) |
678d96fb | 1823 | goto err_out; |
e3cc1995 BW |
1824 | |
1825 | retried = true; | |
1826 | goto alloc; | |
1827 | } | |
c8d4c0d6 | 1828 | |
c8c26622 | 1829 | if (ret) |
678d96fb BW |
1830 | goto err_out; |
1831 | ||
c8c26622 | 1832 | |
c8d4c0d6 BW |
1833 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
1834 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1835 | |
c8c26622 | 1836 | return 0; |
678d96fb BW |
1837 | |
1838 | err_out: | |
8776f02b | 1839 | gen6_free_scratch(vm); |
678d96fb | 1840 | return ret; |
b146520f BW |
1841 | } |
1842 | ||
b146520f BW |
1843 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
1844 | { | |
2f2cf682 | 1845 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 1846 | } |
06dc68d6 | 1847 | |
4933d519 MT |
1848 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
1849 | uint64_t start, uint64_t length) | |
1850 | { | |
ec565b3c | 1851 | struct i915_page_table *unused; |
4933d519 | 1852 | uint32_t pde, temp; |
1d2a314c | 1853 | |
4933d519 | 1854 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) |
79ab9370 | 1855 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
b146520f BW |
1856 | } |
1857 | ||
5c5f6457 | 1858 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f BW |
1859 | { |
1860 | struct drm_device *dev = ppgtt->base.dev; | |
1861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1862 | int ret; | |
1863 | ||
1864 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1865 | if (IS_GEN6(dev)) { | |
b146520f BW |
1866 | ppgtt->switch_mm = gen6_mm_switch; |
1867 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1868 | ppgtt->switch_mm = hsw_mm_switch; |
1869 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1870 | ppgtt->switch_mm = gen7_mm_switch; |
1871 | } else | |
1872 | BUG(); | |
1873 | ||
71ba2d64 YZ |
1874 | if (intel_vgpu_active(dev)) |
1875 | ppgtt->switch_mm = vgpu_mm_switch; | |
1876 | ||
b146520f BW |
1877 | ret = gen6_ppgtt_alloc(ppgtt); |
1878 | if (ret) | |
1879 | return ret; | |
1880 | ||
5c5f6457 | 1881 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
1882 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
1883 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
1884 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1885 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 1886 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 1887 | ppgtt->base.start = 0; |
09942c65 | 1888 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 1889 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1890 | |
44159ddb | 1891 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 1892 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 1893 | |
678d96fb | 1894 | ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + |
44159ddb | 1895 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 1896 | |
5c5f6457 | 1897 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 1898 | |
678d96fb BW |
1899 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
1900 | ||
440fd528 | 1901 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
1902 | ppgtt->node.size >> 20, |
1903 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1904 | |
fa76da34 | 1905 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 1906 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 1907 | |
b146520f | 1908 | return 0; |
3440d265 DV |
1909 | } |
1910 | ||
5c5f6457 | 1911 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1912 | { |
853ba5d2 | 1913 | ppgtt->base.dev = dev; |
3440d265 | 1914 | |
3ed124b2 | 1915 | if (INTEL_INFO(dev)->gen < 8) |
5c5f6457 | 1916 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 1917 | else |
d7b2633d | 1918 | return gen8_ppgtt_init(ppgtt); |
fa76da34 | 1919 | } |
c114f76a | 1920 | |
fa76da34 DV |
1921 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
1922 | { | |
1923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1924 | int ret = 0; | |
3ed124b2 | 1925 | |
5c5f6457 | 1926 | ret = __hw_ppgtt_init(dev, ppgtt); |
fa76da34 | 1927 | if (ret == 0) { |
c7c48dfd | 1928 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1929 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1930 | ppgtt->base.total); | |
7e0d96bc | 1931 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1932 | } |
1d2a314c DV |
1933 | |
1934 | return ret; | |
1935 | } | |
1936 | ||
82460d97 DV |
1937 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1938 | { | |
671b5013 TD |
1939 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1940 | * and the PDPs are contained within the context itself. We don't | |
1941 | * need to do anything here. */ | |
1942 | if (i915.enable_execlists) | |
1943 | return 0; | |
1944 | ||
82460d97 DV |
1945 | if (!USES_PPGTT(dev)) |
1946 | return 0; | |
1947 | ||
1948 | if (IS_GEN6(dev)) | |
1949 | gen6_ppgtt_enable(dev); | |
1950 | else if (IS_GEN7(dev)) | |
1951 | gen7_ppgtt_enable(dev); | |
1952 | else if (INTEL_INFO(dev)->gen >= 8) | |
1953 | gen8_ppgtt_enable(dev); | |
1954 | else | |
5f77eeb0 | 1955 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 | 1956 | |
4ad2fd88 JH |
1957 | return 0; |
1958 | } | |
1d2a314c | 1959 | |
b3dd6b96 | 1960 | int i915_ppgtt_init_ring(struct drm_i915_gem_request *req) |
4ad2fd88 | 1961 | { |
b3dd6b96 | 1962 | struct drm_i915_private *dev_priv = req->ring->dev->dev_private; |
4ad2fd88 JH |
1963 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
1964 | ||
1965 | if (i915.enable_execlists) | |
1966 | return 0; | |
1967 | ||
1968 | if (!ppgtt) | |
1969 | return 0; | |
1970 | ||
e85b26dc | 1971 | return ppgtt->switch_mm(ppgtt, req); |
1d2a314c | 1972 | } |
4ad2fd88 | 1973 | |
4d884705 DV |
1974 | struct i915_hw_ppgtt * |
1975 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1976 | { | |
1977 | struct i915_hw_ppgtt *ppgtt; | |
1978 | int ret; | |
1979 | ||
1980 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1981 | if (!ppgtt) | |
1982 | return ERR_PTR(-ENOMEM); | |
1983 | ||
1984 | ret = i915_ppgtt_init(dev, ppgtt); | |
1985 | if (ret) { | |
1986 | kfree(ppgtt); | |
1987 | return ERR_PTR(ret); | |
1988 | } | |
1989 | ||
1990 | ppgtt->file_priv = fpriv; | |
1991 | ||
198c974d DCS |
1992 | trace_i915_ppgtt_create(&ppgtt->base); |
1993 | ||
4d884705 DV |
1994 | return ppgtt; |
1995 | } | |
1996 | ||
ee960be7 DV |
1997 | void i915_ppgtt_release(struct kref *kref) |
1998 | { | |
1999 | struct i915_hw_ppgtt *ppgtt = | |
2000 | container_of(kref, struct i915_hw_ppgtt, ref); | |
2001 | ||
198c974d DCS |
2002 | trace_i915_ppgtt_release(&ppgtt->base); |
2003 | ||
ee960be7 DV |
2004 | /* vmas should already be unbound */ |
2005 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
2006 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
2007 | ||
19dd120c DV |
2008 | list_del(&ppgtt->base.global_link); |
2009 | drm_mm_takedown(&ppgtt->base.mm); | |
2010 | ||
ee960be7 DV |
2011 | ppgtt->base.cleanup(&ppgtt->base); |
2012 | kfree(ppgtt); | |
2013 | } | |
1d2a314c | 2014 | |
a81cc00c BW |
2015 | extern int intel_iommu_gfx_mapped; |
2016 | /* Certain Gen5 chipsets require require idling the GPU before | |
2017 | * unmapping anything from the GTT when VT-d is enabled. | |
2018 | */ | |
2c642b07 | 2019 | static bool needs_idle_maps(struct drm_device *dev) |
a81cc00c BW |
2020 | { |
2021 | #ifdef CONFIG_INTEL_IOMMU | |
2022 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
2023 | * was loaded first. | |
2024 | */ | |
2025 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
2026 | return true; | |
2027 | #endif | |
2028 | return false; | |
2029 | } | |
2030 | ||
5c042287 BW |
2031 | static bool do_idling(struct drm_i915_private *dev_priv) |
2032 | { | |
2033 | bool ret = dev_priv->mm.interruptible; | |
2034 | ||
a81cc00c | 2035 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 2036 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 2037 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
2038 | DRM_ERROR("Couldn't idle GPU\n"); |
2039 | /* Wait a bit, in hopes it avoids the hang */ | |
2040 | udelay(10); | |
2041 | } | |
2042 | } | |
2043 | ||
2044 | return ret; | |
2045 | } | |
2046 | ||
2047 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
2048 | { | |
a81cc00c | 2049 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
2050 | dev_priv->mm.interruptible = interruptible; |
2051 | } | |
2052 | ||
828c7908 BW |
2053 | void i915_check_and_clear_faults(struct drm_device *dev) |
2054 | { | |
2055 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2056 | struct intel_engine_cs *ring; |
828c7908 BW |
2057 | int i; |
2058 | ||
2059 | if (INTEL_INFO(dev)->gen < 6) | |
2060 | return; | |
2061 | ||
2062 | for_each_ring(ring, dev_priv, i) { | |
2063 | u32 fault_reg; | |
2064 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
2065 | if (fault_reg & RING_FAULT_VALID) { | |
2066 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 2067 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
2068 | "\tAddress space: %s\n" |
2069 | "\tSource ID: %d\n" | |
2070 | "\tType: %d\n", | |
2071 | fault_reg & PAGE_MASK, | |
2072 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
2073 | RING_FAULT_SRCID(fault_reg), | |
2074 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
2075 | I915_WRITE(RING_FAULT_REG(ring), | |
2076 | fault_reg & ~RING_FAULT_VALID); | |
2077 | } | |
2078 | } | |
2079 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
2080 | } | |
2081 | ||
91e56499 CW |
2082 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
2083 | { | |
2084 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { | |
2085 | intel_gtt_chipset_flush(); | |
2086 | } else { | |
2087 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2088 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
2089 | } | |
2090 | } | |
2091 | ||
828c7908 BW |
2092 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
2093 | { | |
2094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2095 | ||
2096 | /* Don't bother messing with faults pre GEN6 as we have little | |
2097 | * documentation supporting that it's a good idea. | |
2098 | */ | |
2099 | if (INTEL_INFO(dev)->gen < 6) | |
2100 | return; | |
2101 | ||
2102 | i915_check_and_clear_faults(dev); | |
2103 | ||
2104 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
2105 | dev_priv->gtt.base.start, |
2106 | dev_priv->gtt.base.total, | |
e568af1c | 2107 | true); |
91e56499 CW |
2108 | |
2109 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
2110 | } |
2111 | ||
74163907 | 2112 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 2113 | { |
9da3da66 CW |
2114 | if (!dma_map_sg(&obj->base.dev->pdev->dev, |
2115 | obj->pages->sgl, obj->pages->nents, | |
2116 | PCI_DMA_BIDIRECTIONAL)) | |
2117 | return -ENOSPC; | |
2118 | ||
2119 | return 0; | |
7c2e6fdf DV |
2120 | } |
2121 | ||
2c642b07 | 2122 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 BW |
2123 | { |
2124 | #ifdef writeq | |
2125 | writeq(pte, addr); | |
2126 | #else | |
2127 | iowrite32((u32)pte, addr); | |
2128 | iowrite32(pte >> 32, addr + 4); | |
2129 | #endif | |
2130 | } | |
2131 | ||
2132 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
2133 | struct sg_table *st, | |
782f1495 | 2134 | uint64_t start, |
24f3a8cf | 2135 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
2136 | { |
2137 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 2138 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
2139 | gen8_pte_t __iomem *gtt_entries = |
2140 | (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
2141 | int i = 0; |
2142 | struct sg_page_iter sg_iter; | |
57007df7 | 2143 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
2144 | |
2145 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
2146 | addr = sg_dma_address(sg_iter.sg) + | |
2147 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
2148 | gen8_set_pte(>t_entries[i], | |
2149 | gen8_pte_encode(addr, level, true)); | |
2150 | i++; | |
2151 | } | |
2152 | ||
2153 | /* | |
2154 | * XXX: This serves as a posting read to make sure that the PTE has | |
2155 | * actually been updated. There is some concern that even though | |
2156 | * registers and PTEs are within the same BAR that they are potentially | |
2157 | * of NUMA access patterns. Therefore, even with the way we assume | |
2158 | * hardware should work, we must keep this posting read for paranoia. | |
2159 | */ | |
2160 | if (i != 0) | |
2161 | WARN_ON(readq(>t_entries[i-1]) | |
2162 | != gen8_pte_encode(addr, level, true)); | |
2163 | ||
94ec8f61 BW |
2164 | /* This next bit makes the above posting read even more important. We |
2165 | * want to flush the TLBs only after we're certain all the PTE updates | |
2166 | * have finished. | |
2167 | */ | |
2168 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2169 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
2170 | } |
2171 | ||
e76e9aeb BW |
2172 | /* |
2173 | * Binds an object into the global gtt with the specified cache level. The object | |
2174 | * will be accessible to the GPU via commands whose operands reference offsets | |
2175 | * within the global GTT as well as accessible by the GPU through the GMADR | |
2176 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
2177 | */ | |
853ba5d2 | 2178 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 2179 | struct sg_table *st, |
782f1495 | 2180 | uint64_t start, |
24f3a8cf | 2181 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 2182 | { |
853ba5d2 | 2183 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 2184 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
2185 | gen6_pte_t __iomem *gtt_entries = |
2186 | (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
2187 | int i = 0; |
2188 | struct sg_page_iter sg_iter; | |
57007df7 | 2189 | dma_addr_t addr = 0; |
e76e9aeb | 2190 | |
6e995e23 | 2191 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 2192 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 2193 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 2194 | i++; |
e76e9aeb BW |
2195 | } |
2196 | ||
e76e9aeb BW |
2197 | /* XXX: This serves as a posting read to make sure that the PTE has |
2198 | * actually been updated. There is some concern that even though | |
2199 | * registers and PTEs are within the same BAR that they are potentially | |
2200 | * of NUMA access patterns. Therefore, even with the way we assume | |
2201 | * hardware should work, we must keep this posting read for paranoia. | |
2202 | */ | |
57007df7 PM |
2203 | if (i != 0) { |
2204 | unsigned long gtt = readl(>t_entries[i-1]); | |
2205 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
2206 | } | |
0f9b91c7 BW |
2207 | |
2208 | /* This next bit makes the above posting read even more important. We | |
2209 | * want to flush the TLBs only after we're certain all the PTE updates | |
2210 | * have finished. | |
2211 | */ | |
2212 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
2213 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
2214 | } |
2215 | ||
94ec8f61 | 2216 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
2217 | uint64_t start, |
2218 | uint64_t length, | |
94ec8f61 BW |
2219 | bool use_scratch) |
2220 | { | |
2221 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
2222 | unsigned first_entry = start >> PAGE_SHIFT; |
2223 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
2224 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
2225 | (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
2226 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
2227 | int i; | |
2228 | ||
2229 | if (WARN(num_entries > max_entries, | |
2230 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2231 | first_entry, num_entries, max_entries)) | |
2232 | num_entries = max_entries; | |
2233 | ||
c114f76a | 2234 | scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), |
94ec8f61 BW |
2235 | I915_CACHE_LLC, |
2236 | use_scratch); | |
2237 | for (i = 0; i < num_entries; i++) | |
2238 | gen8_set_pte(>t_base[i], scratch_pte); | |
2239 | readl(gtt_base); | |
2240 | } | |
2241 | ||
853ba5d2 | 2242 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
2243 | uint64_t start, |
2244 | uint64_t length, | |
828c7908 | 2245 | bool use_scratch) |
7faf1ab2 | 2246 | { |
853ba5d2 | 2247 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
2248 | unsigned first_entry = start >> PAGE_SHIFT; |
2249 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
2250 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
2251 | (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 2252 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
2253 | int i; |
2254 | ||
2255 | if (WARN(num_entries > max_entries, | |
2256 | "First entry = %d; Num entries = %d (max=%d)\n", | |
2257 | first_entry, num_entries, max_entries)) | |
2258 | num_entries = max_entries; | |
2259 | ||
c114f76a MK |
2260 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
2261 | I915_CACHE_LLC, use_scratch, 0); | |
828c7908 | 2262 | |
7faf1ab2 DV |
2263 | for (i = 0; i < num_entries; i++) |
2264 | iowrite32(scratch_pte, >t_base[i]); | |
2265 | readl(gtt_base); | |
2266 | } | |
2267 | ||
d369d2d9 DV |
2268 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
2269 | struct sg_table *pages, | |
2270 | uint64_t start, | |
2271 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 DV |
2272 | { |
2273 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
2274 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
2275 | ||
d369d2d9 | 2276 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 2277 | |
7faf1ab2 DV |
2278 | } |
2279 | ||
853ba5d2 | 2280 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
2281 | uint64_t start, |
2282 | uint64_t length, | |
828c7908 | 2283 | bool unused) |
7faf1ab2 | 2284 | { |
782f1495 BW |
2285 | unsigned first_entry = start >> PAGE_SHIFT; |
2286 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
2287 | intel_gtt_clear_range(first_entry, num_entries); |
2288 | } | |
2289 | ||
70b9f6f8 DV |
2290 | static int ggtt_bind_vma(struct i915_vma *vma, |
2291 | enum i915_cache_level cache_level, | |
2292 | u32 flags) | |
d5bd1449 | 2293 | { |
6f65e29a | 2294 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 2295 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 2296 | struct drm_i915_gem_object *obj = vma->obj; |
ec7adb6e | 2297 | struct sg_table *pages = obj->pages; |
f329f5f6 | 2298 | u32 pte_flags = 0; |
70b9f6f8 DV |
2299 | int ret; |
2300 | ||
2301 | ret = i915_get_ggtt_vma_pages(vma); | |
2302 | if (ret) | |
2303 | return ret; | |
2304 | pages = vma->ggtt_view.pages; | |
7faf1ab2 | 2305 | |
24f3a8cf AG |
2306 | /* Currently applicable only to VLV */ |
2307 | if (obj->gt_ro) | |
f329f5f6 | 2308 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 2309 | |
ec7adb6e | 2310 | |
6f65e29a | 2311 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { |
0875546c DV |
2312 | vma->vm->insert_entries(vma->vm, pages, |
2313 | vma->node.start, | |
2314 | cache_level, pte_flags); | |
d0e30adc CW |
2315 | |
2316 | /* Note the inconsistency here is due to absence of the | |
2317 | * aliasing ppgtt on gen4 and earlier. Though we always | |
2318 | * request PIN_USER for execbuffer (translated to LOCAL_BIND), | |
2319 | * without the appgtt, we cannot honour that request and so | |
2320 | * must substitute it with a global binding. Since we do this | |
2321 | * behind the upper layers back, we need to explicitly set | |
2322 | * the bound flag ourselves. | |
2323 | */ | |
2324 | vma->bound |= GLOBAL_BIND; | |
2325 | ||
6f65e29a | 2326 | } |
d5bd1449 | 2327 | |
0875546c | 2328 | if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) { |
6f65e29a | 2329 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
ec7adb6e | 2330 | appgtt->base.insert_entries(&appgtt->base, pages, |
782f1495 | 2331 | vma->node.start, |
f329f5f6 | 2332 | cache_level, pte_flags); |
6f65e29a | 2333 | } |
70b9f6f8 DV |
2334 | |
2335 | return 0; | |
d5bd1449 CW |
2336 | } |
2337 | ||
6f65e29a | 2338 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 2339 | { |
6f65e29a | 2340 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 2341 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 2342 | struct drm_i915_gem_object *obj = vma->obj; |
06615ee5 JL |
2343 | const uint64_t size = min_t(uint64_t, |
2344 | obj->base.size, | |
2345 | vma->node.size); | |
6f65e29a | 2346 | |
aff43766 | 2347 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
2348 | vma->vm->clear_range(vma->vm, |
2349 | vma->node.start, | |
06615ee5 | 2350 | size, |
6f65e29a | 2351 | true); |
6f65e29a | 2352 | } |
74898d7e | 2353 | |
0875546c | 2354 | if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) { |
6f65e29a | 2355 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
06615ee5 | 2356 | |
6f65e29a | 2357 | appgtt->base.clear_range(&appgtt->base, |
782f1495 | 2358 | vma->node.start, |
06615ee5 | 2359 | size, |
6f65e29a | 2360 | true); |
6f65e29a | 2361 | } |
74163907 DV |
2362 | } |
2363 | ||
2364 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 2365 | { |
5c042287 BW |
2366 | struct drm_device *dev = obj->base.dev; |
2367 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2368 | bool interruptible; | |
2369 | ||
2370 | interruptible = do_idling(dev_priv); | |
2371 | ||
5ec5b516 ID |
2372 | dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents, |
2373 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
2374 | |
2375 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 2376 | } |
644ec02b | 2377 | |
42d6ab48 CW |
2378 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
2379 | unsigned long color, | |
440fd528 TR |
2380 | u64 *start, |
2381 | u64 *end) | |
42d6ab48 CW |
2382 | { |
2383 | if (node->color != color) | |
2384 | *start += 4096; | |
2385 | ||
2386 | if (!list_empty(&node->node_list)) { | |
2387 | node = list_entry(node->node_list.next, | |
2388 | struct drm_mm_node, | |
2389 | node_list); | |
2390 | if (node->allocated && node->color != color) | |
2391 | *end -= 4096; | |
2392 | } | |
2393 | } | |
fbe5d36e | 2394 | |
f548c0e9 DV |
2395 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
2396 | unsigned long start, | |
2397 | unsigned long mappable_end, | |
2398 | unsigned long end) | |
644ec02b | 2399 | { |
e78891ca BW |
2400 | /* Let GEM Manage all of the aperture. |
2401 | * | |
2402 | * However, leave one page at the end still bound to the scratch page. | |
2403 | * There are a number of places where the hardware apparently prefetches | |
2404 | * past the end of the object, and we've seen multiple hangs with the | |
2405 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2406 | * aperture. One page should be enough to keep any prefetching inside | |
2407 | * of the aperture. | |
2408 | */ | |
40d74980 BW |
2409 | struct drm_i915_private *dev_priv = dev->dev_private; |
2410 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
2411 | struct drm_mm_node *entry; |
2412 | struct drm_i915_gem_object *obj; | |
2413 | unsigned long hole_start, hole_end; | |
fa76da34 | 2414 | int ret; |
644ec02b | 2415 | |
35451cb6 BW |
2416 | BUG_ON(mappable_end > end); |
2417 | ||
ed2f3452 | 2418 | /* Subtract the guard page ... */ |
40d74980 | 2419 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
5dda8fa3 YZ |
2420 | |
2421 | dev_priv->gtt.base.start = start; | |
2422 | dev_priv->gtt.base.total = end - start; | |
2423 | ||
2424 | if (intel_vgpu_active(dev)) { | |
2425 | ret = intel_vgt_balloon(dev); | |
2426 | if (ret) | |
2427 | return ret; | |
2428 | } | |
2429 | ||
42d6ab48 | 2430 | if (!HAS_LLC(dev)) |
93bd8649 | 2431 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 2432 | |
ed2f3452 | 2433 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 2434 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 2435 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 2436 | |
edd41a87 | 2437 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
2438 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
2439 | ||
2440 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 2441 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
2442 | if (ret) { |
2443 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
2444 | return ret; | |
2445 | } | |
aff43766 | 2446 | vma->bound |= GLOBAL_BIND; |
ed2f3452 CW |
2447 | } |
2448 | ||
ed2f3452 | 2449 | /* Clear any non-preallocated blocks */ |
40d74980 | 2450 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
2451 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2452 | hole_start, hole_end); | |
782f1495 BW |
2453 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
2454 | hole_end - hole_start, true); | |
ed2f3452 CW |
2455 | } |
2456 | ||
2457 | /* And finally clear the reserved guard page */ | |
782f1495 | 2458 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 2459 | |
fa76da34 DV |
2460 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
2461 | struct i915_hw_ppgtt *ppgtt; | |
2462 | ||
2463 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2464 | if (!ppgtt) | |
2465 | return -ENOMEM; | |
2466 | ||
5c5f6457 DV |
2467 | ret = __hw_ppgtt_init(dev, ppgtt); |
2468 | if (ret) { | |
2469 | ppgtt->base.cleanup(&ppgtt->base); | |
2470 | kfree(ppgtt); | |
2471 | return ret; | |
2472 | } | |
2473 | ||
2474 | if (ppgtt->base.allocate_va_range) | |
2475 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, | |
2476 | ppgtt->base.total); | |
4933d519 | 2477 | if (ret) { |
061dd493 | 2478 | ppgtt->base.cleanup(&ppgtt->base); |
4933d519 | 2479 | kfree(ppgtt); |
fa76da34 | 2480 | return ret; |
4933d519 | 2481 | } |
fa76da34 | 2482 | |
5c5f6457 DV |
2483 | ppgtt->base.clear_range(&ppgtt->base, |
2484 | ppgtt->base.start, | |
2485 | ppgtt->base.total, | |
2486 | true); | |
2487 | ||
fa76da34 DV |
2488 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
2489 | } | |
2490 | ||
6c5566a8 | 2491 | return 0; |
e76e9aeb BW |
2492 | } |
2493 | ||
d7e5008f BW |
2494 | void i915_gem_init_global_gtt(struct drm_device *dev) |
2495 | { | |
2496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c44ef60e | 2497 | u64 gtt_size, mappable_size; |
d7e5008f | 2498 | |
853ba5d2 | 2499 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 2500 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 2501 | |
e78891ca | 2502 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
2503 | } |
2504 | ||
90d0a0e8 DV |
2505 | void i915_global_gtt_cleanup(struct drm_device *dev) |
2506 | { | |
2507 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2508 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
2509 | ||
70e32544 DV |
2510 | if (dev_priv->mm.aliasing_ppgtt) { |
2511 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2512 | ||
2513 | ppgtt->base.cleanup(&ppgtt->base); | |
2514 | } | |
2515 | ||
90d0a0e8 | 2516 | if (drm_mm_initialized(&vm->mm)) { |
5dda8fa3 YZ |
2517 | if (intel_vgpu_active(dev)) |
2518 | intel_vgt_deballoon(); | |
2519 | ||
90d0a0e8 DV |
2520 | drm_mm_takedown(&vm->mm); |
2521 | list_del(&vm->global_link); | |
2522 | } | |
2523 | ||
2524 | vm->cleanup(vm); | |
2525 | } | |
70e32544 | 2526 | |
2c642b07 | 2527 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2528 | { |
2529 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2530 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2531 | return snb_gmch_ctl << 20; | |
2532 | } | |
2533 | ||
2c642b07 | 2534 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2535 | { |
2536 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2537 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2538 | if (bdw_gmch_ctl) | |
2539 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2540 | |
2541 | #ifdef CONFIG_X86_32 | |
2542 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2543 | if (bdw_gmch_ctl > 4) | |
2544 | bdw_gmch_ctl = 4; | |
2545 | #endif | |
2546 | ||
9459d252 BW |
2547 | return bdw_gmch_ctl << 20; |
2548 | } | |
2549 | ||
2c642b07 | 2550 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2551 | { |
2552 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2553 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2554 | ||
2555 | if (gmch_ctrl) | |
2556 | return 1 << (20 + gmch_ctrl); | |
2557 | ||
2558 | return 0; | |
2559 | } | |
2560 | ||
2c642b07 | 2561 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2562 | { |
2563 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2564 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2565 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2566 | } | |
2567 | ||
2c642b07 | 2568 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2569 | { |
2570 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2571 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2572 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2573 | } | |
2574 | ||
d7f25f23 DL |
2575 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2576 | { | |
2577 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2578 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2579 | ||
2580 | /* | |
2581 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2582 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2583 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2584 | */ | |
2585 | if (gmch_ctrl < 0x11) | |
2586 | return gmch_ctrl << 25; | |
2587 | else if (gmch_ctrl < 0x17) | |
2588 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2589 | else | |
2590 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2591 | } | |
2592 | ||
66375014 DL |
2593 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2594 | { | |
2595 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2596 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2597 | ||
2598 | if (gen9_gmch_ctl < 0xf0) | |
2599 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2600 | else | |
2601 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2602 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2603 | } | |
2604 | ||
63340133 BW |
2605 | static int ggtt_probe_common(struct drm_device *dev, |
2606 | size_t gtt_size) | |
2607 | { | |
2608 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4ad2af1e | 2609 | struct i915_page_scratch *scratch_page; |
21c34607 | 2610 | phys_addr_t gtt_phys_addr; |
63340133 BW |
2611 | |
2612 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 2613 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
2614 | (pci_resource_len(dev->pdev, 0) / 2); |
2615 | ||
2a073f89 ID |
2616 | /* |
2617 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2618 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2619 | * when the WC buffer is flushed, so we can't use it, but have to | |
2620 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2621 | * readback check when writing GTT PTE entries. | |
2622 | */ | |
2623 | if (IS_BROXTON(dev)) | |
2624 | dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size); | |
2625 | else | |
2626 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); | |
63340133 BW |
2627 | if (!dev_priv->gtt.gsm) { |
2628 | DRM_ERROR("Failed to map the gtt page table\n"); | |
2629 | return -ENOMEM; | |
2630 | } | |
2631 | ||
4ad2af1e MK |
2632 | scratch_page = alloc_scratch_page(dev); |
2633 | if (IS_ERR(scratch_page)) { | |
63340133 BW |
2634 | DRM_ERROR("Scratch setup failed\n"); |
2635 | /* iounmap will also get called at remove, but meh */ | |
2636 | iounmap(dev_priv->gtt.gsm); | |
4ad2af1e | 2637 | return PTR_ERR(scratch_page); |
63340133 BW |
2638 | } |
2639 | ||
4ad2af1e MK |
2640 | dev_priv->gtt.base.scratch_page = scratch_page; |
2641 | ||
2642 | return 0; | |
63340133 BW |
2643 | } |
2644 | ||
fbe5d36e BW |
2645 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2646 | * bits. When using advanced contexts each context stores its own PAT, but | |
2647 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2648 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2649 | { |
fbe5d36e BW |
2650 | uint64_t pat; |
2651 | ||
2652 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2653 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2654 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2655 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2656 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2657 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2658 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2659 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2660 | ||
d6a8b72e RV |
2661 | if (!USES_PPGTT(dev_priv->dev)) |
2662 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2663 | * so RTL will always use the value corresponding to | |
2664 | * pat_sel = 000". | |
2665 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2666 | * MOCS still can be used though. | |
2667 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2668 | * before this patch, i.e. the same uncached + snooping access | |
2669 | * like on gen6/7 seems to be in effect. | |
2670 | * - So this just fixes blitter/render access. Again it looks | |
2671 | * like it's not just uncached access, but uncached + snooping. | |
2672 | * So we can still hold onto all our assumptions wrt cpu | |
2673 | * clflushing on LLC machines. | |
2674 | */ | |
2675 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2676 | ||
fbe5d36e BW |
2677 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2678 | * write would work. */ | |
2679 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2680 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2681 | } | |
2682 | ||
ee0ce478 VS |
2683 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2684 | { | |
2685 | uint64_t pat; | |
2686 | ||
2687 | /* | |
2688 | * Map WB on BDW to snooped on CHV. | |
2689 | * | |
2690 | * Only the snoop bit has meaning for CHV, the rest is | |
2691 | * ignored. | |
2692 | * | |
cf3d262e VS |
2693 | * The hardware will never snoop for certain types of accesses: |
2694 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2695 | * - PPGTT page tables | |
2696 | * - some other special cycles | |
2697 | * | |
2698 | * As with BDW, we also need to consider the following for GT accesses: | |
2699 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2700 | * so RTL will always use the value corresponding to | |
2701 | * pat_sel = 000". | |
2702 | * Which means we must set the snoop bit in PAT entry 0 | |
2703 | * in order to keep the global status page working. | |
ee0ce478 VS |
2704 | */ |
2705 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2706 | GEN8_PPAT(1, 0) | | |
2707 | GEN8_PPAT(2, 0) | | |
2708 | GEN8_PPAT(3, 0) | | |
2709 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
2710 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
2711 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
2712 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
2713 | ||
2714 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2715 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2716 | } | |
2717 | ||
63340133 | 2718 | static int gen8_gmch_probe(struct drm_device *dev, |
c44ef60e | 2719 | u64 *gtt_total, |
63340133 BW |
2720 | size_t *stolen, |
2721 | phys_addr_t *mappable_base, | |
c44ef60e | 2722 | u64 *mappable_end) |
63340133 BW |
2723 | { |
2724 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c44ef60e | 2725 | u64 gtt_size; |
63340133 BW |
2726 | u16 snb_gmch_ctl; |
2727 | int ret; | |
2728 | ||
2729 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
2730 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
2731 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2732 | ||
2733 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
2734 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
2735 | ||
2736 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
2737 | ||
66375014 DL |
2738 | if (INTEL_INFO(dev)->gen >= 9) { |
2739 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); | |
2740 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2741 | } else if (IS_CHERRYVIEW(dev)) { | |
d7f25f23 DL |
2742 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
2743 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
2744 | } else { | |
2745 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
2746 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2747 | } | |
63340133 | 2748 | |
07749ef3 | 2749 | *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 2750 | |
5a4e33a3 | 2751 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) |
ee0ce478 VS |
2752 | chv_setup_private_ppat(dev_priv); |
2753 | else | |
2754 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2755 | |
63340133 BW |
2756 | ret = ggtt_probe_common(dev, gtt_size); |
2757 | ||
94ec8f61 BW |
2758 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
2759 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
777dc5bb DV |
2760 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2761 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
63340133 BW |
2762 | |
2763 | return ret; | |
2764 | } | |
2765 | ||
baa09f5f | 2766 | static int gen6_gmch_probe(struct drm_device *dev, |
c44ef60e | 2767 | u64 *gtt_total, |
41907ddc BW |
2768 | size_t *stolen, |
2769 | phys_addr_t *mappable_base, | |
c44ef60e | 2770 | u64 *mappable_end) |
e76e9aeb BW |
2771 | { |
2772 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2773 | unsigned int gtt_size; |
e76e9aeb | 2774 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2775 | int ret; |
2776 | ||
41907ddc BW |
2777 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2778 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2779 | ||
baa09f5f BW |
2780 | /* 64/512MB is the current min/max we actually know of, but this is just |
2781 | * a coarse sanity check. | |
e76e9aeb | 2782 | */ |
41907ddc | 2783 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
c44ef60e | 2784 | DRM_ERROR("Unknown GMADR size (%llx)\n", |
baa09f5f BW |
2785 | dev_priv->gtt.mappable_end); |
2786 | return -ENXIO; | |
e76e9aeb BW |
2787 | } |
2788 | ||
e76e9aeb BW |
2789 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2790 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2791 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2792 | |
c4ae25ec | 2793 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2794 | |
63340133 | 2795 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
07749ef3 | 2796 | *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 2797 | |
63340133 | 2798 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2799 | |
853ba5d2 BW |
2800 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2801 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
777dc5bb DV |
2802 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2803 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
7faf1ab2 | 2804 | |
e76e9aeb BW |
2805 | return ret; |
2806 | } | |
2807 | ||
853ba5d2 | 2808 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2809 | { |
853ba5d2 BW |
2810 | |
2811 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2812 | |
853ba5d2 | 2813 | iounmap(gtt->gsm); |
4ad2af1e | 2814 | free_scratch_page(vm->dev, vm->scratch_page); |
644ec02b | 2815 | } |
baa09f5f BW |
2816 | |
2817 | static int i915_gmch_probe(struct drm_device *dev, | |
c44ef60e | 2818 | u64 *gtt_total, |
41907ddc BW |
2819 | size_t *stolen, |
2820 | phys_addr_t *mappable_base, | |
c44ef60e | 2821 | u64 *mappable_end) |
baa09f5f BW |
2822 | { |
2823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2824 | int ret; | |
2825 | ||
baa09f5f BW |
2826 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2827 | if (!ret) { | |
2828 | DRM_ERROR("failed to set up gmch\n"); | |
2829 | return -EIO; | |
2830 | } | |
2831 | ||
41907ddc | 2832 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2833 | |
2834 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
d369d2d9 | 2835 | dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; |
853ba5d2 | 2836 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
d369d2d9 DV |
2837 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2838 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
baa09f5f | 2839 | |
c0a7f818 CW |
2840 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2841 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2842 | ||
baa09f5f BW |
2843 | return 0; |
2844 | } | |
2845 | ||
853ba5d2 | 2846 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2847 | { |
2848 | intel_gmch_remove(); | |
2849 | } | |
2850 | ||
2851 | int i915_gem_gtt_init(struct drm_device *dev) | |
2852 | { | |
2853 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2854 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2855 | int ret; |
2856 | ||
baa09f5f | 2857 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2858 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2859 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2860 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2861 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2862 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2863 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2864 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2865 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2866 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2867 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2868 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2869 | else if (INTEL_INFO(dev)->gen >= 7) |
2870 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2871 | else |
350ec881 | 2872 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2873 | } else { |
2874 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2875 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2876 | } |
2877 | ||
c114f76a MK |
2878 | gtt->base.dev = dev; |
2879 | ||
853ba5d2 | 2880 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2881 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2882 | if (ret) |
baa09f5f | 2883 | return ret; |
baa09f5f | 2884 | |
baa09f5f | 2885 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 2886 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
853ba5d2 | 2887 | gtt->base.total >> 20); |
c44ef60e | 2888 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20); |
b2f21b4d | 2889 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); |
5db6c735 DV |
2890 | #ifdef CONFIG_INTEL_IOMMU |
2891 | if (intel_iommu_gfx_mapped) | |
2892 | DRM_INFO("VT-d active for gfx access\n"); | |
2893 | #endif | |
cfa7c862 DV |
2894 | /* |
2895 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2896 | * user's requested state against the hardware/driver capabilities. We | |
2897 | * do this now so that we can print out any log messages once rather | |
2898 | * than every time we check intel_enable_ppgtt(). | |
2899 | */ | |
2900 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2901 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2902 | |
2903 | return 0; | |
2904 | } | |
6f65e29a | 2905 | |
fa42331b DV |
2906 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
2907 | { | |
2908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2909 | struct drm_i915_gem_object *obj; | |
2910 | struct i915_address_space *vm; | |
2c3d9984 TU |
2911 | struct i915_vma *vma; |
2912 | bool flush; | |
fa42331b DV |
2913 | |
2914 | i915_check_and_clear_faults(dev); | |
2915 | ||
2916 | /* First fill our portion of the GTT with scratch pages */ | |
2917 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
2918 | dev_priv->gtt.base.start, | |
2919 | dev_priv->gtt.base.total, | |
2920 | true); | |
2921 | ||
2c3d9984 TU |
2922 | /* Cache flush objects bound into GGTT and rebind them. */ |
2923 | vm = &dev_priv->gtt.base; | |
fa42331b | 2924 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
2c3d9984 TU |
2925 | flush = false; |
2926 | list_for_each_entry(vma, &obj->vma_list, vma_link) { | |
2927 | if (vma->vm != vm) | |
2928 | continue; | |
fa42331b | 2929 | |
2c3d9984 TU |
2930 | WARN_ON(i915_vma_bind(vma, obj->cache_level, |
2931 | PIN_UPDATE)); | |
fa42331b | 2932 | |
2c3d9984 TU |
2933 | flush = true; |
2934 | } | |
2935 | ||
2936 | if (flush) | |
2937 | i915_gem_clflush_object(obj, obj->pin_display); | |
2938 | } | |
fa42331b DV |
2939 | |
2940 | if (INTEL_INFO(dev)->gen >= 8) { | |
2941 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) | |
2942 | chv_setup_private_ppat(dev_priv); | |
2943 | else | |
2944 | bdw_setup_private_ppat(dev_priv); | |
2945 | ||
2946 | return; | |
2947 | } | |
2948 | ||
2949 | if (USES_PPGTT(dev)) { | |
2950 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
2951 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
2952 | ||
2953 | struct i915_hw_ppgtt *ppgtt = | |
2954 | container_of(vm, struct i915_hw_ppgtt, | |
2955 | base); | |
2956 | ||
2957 | if (i915_is_ggtt(vm)) | |
2958 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2959 | ||
2960 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
2961 | 0, ppgtt->base.total); | |
2962 | } | |
2963 | } | |
2964 | ||
2965 | i915_ggtt_flush(dev_priv); | |
2966 | } | |
2967 | ||
ec7adb6e JL |
2968 | static struct i915_vma * |
2969 | __i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2970 | struct i915_address_space *vm, | |
2971 | const struct i915_ggtt_view *ggtt_view) | |
6f65e29a | 2972 | { |
dabde5c7 | 2973 | struct i915_vma *vma; |
6f65e29a | 2974 | |
ec7adb6e JL |
2975 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
2976 | return ERR_PTR(-EINVAL); | |
e20d2ab7 CW |
2977 | |
2978 | vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); | |
dabde5c7 DC |
2979 | if (vma == NULL) |
2980 | return ERR_PTR(-ENOMEM); | |
ec7adb6e | 2981 | |
6f65e29a BW |
2982 | INIT_LIST_HEAD(&vma->vma_link); |
2983 | INIT_LIST_HEAD(&vma->mm_list); | |
2984 | INIT_LIST_HEAD(&vma->exec_list); | |
2985 | vma->vm = vm; | |
2986 | vma->obj = obj; | |
2987 | ||
777dc5bb | 2988 | if (i915_is_ggtt(vm)) |
ec7adb6e | 2989 | vma->ggtt_view = *ggtt_view; |
6f65e29a | 2990 | |
f7635669 TU |
2991 | list_add_tail(&vma->vma_link, &obj->vma_list); |
2992 | if (!i915_is_ggtt(vm)) | |
e07f0552 | 2993 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
6f65e29a BW |
2994 | |
2995 | return vma; | |
2996 | } | |
2997 | ||
2998 | struct i915_vma * | |
ec7adb6e JL |
2999 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
3000 | struct i915_address_space *vm) | |
3001 | { | |
3002 | struct i915_vma *vma; | |
3003 | ||
3004 | vma = i915_gem_obj_to_vma(obj, vm); | |
3005 | if (!vma) | |
3006 | vma = __i915_gem_vma_create(obj, vm, | |
3007 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL); | |
3008 | ||
3009 | return vma; | |
3010 | } | |
3011 | ||
3012 | struct i915_vma * | |
3013 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
fe14d5f4 | 3014 | const struct i915_ggtt_view *view) |
6f65e29a | 3015 | { |
ec7adb6e | 3016 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
6f65e29a BW |
3017 | struct i915_vma *vma; |
3018 | ||
ec7adb6e JL |
3019 | if (WARN_ON(!view)) |
3020 | return ERR_PTR(-EINVAL); | |
3021 | ||
3022 | vma = i915_gem_obj_to_ggtt_view(obj, view); | |
3023 | ||
3024 | if (IS_ERR(vma)) | |
3025 | return vma; | |
3026 | ||
6f65e29a | 3027 | if (!vma) |
ec7adb6e | 3028 | vma = __i915_gem_vma_create(obj, ggtt, view); |
6f65e29a BW |
3029 | |
3030 | return vma; | |
ec7adb6e | 3031 | |
6f65e29a | 3032 | } |
fe14d5f4 | 3033 | |
50470bb0 TU |
3034 | static void |
3035 | rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height, | |
3036 | struct sg_table *st) | |
3037 | { | |
3038 | unsigned int column, row; | |
3039 | unsigned int src_idx; | |
3040 | struct scatterlist *sg = st->sgl; | |
3041 | ||
3042 | st->nents = 0; | |
3043 | ||
3044 | for (column = 0; column < width; column++) { | |
3045 | src_idx = width * (height - 1) + column; | |
3046 | for (row = 0; row < height; row++) { | |
3047 | st->nents++; | |
3048 | /* We don't need the pages, but need to initialize | |
3049 | * the entries so the sg list can be happily traversed. | |
3050 | * The only thing we need are DMA addresses. | |
3051 | */ | |
3052 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
3053 | sg_dma_address(sg) = in[src_idx]; | |
3054 | sg_dma_len(sg) = PAGE_SIZE; | |
3055 | sg = sg_next(sg); | |
3056 | src_idx -= width; | |
3057 | } | |
3058 | } | |
3059 | } | |
3060 | ||
3061 | static struct sg_table * | |
3062 | intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view, | |
3063 | struct drm_i915_gem_object *obj) | |
3064 | { | |
50470bb0 | 3065 | struct intel_rotation_info *rot_info = &ggtt_view->rotation_info; |
84fe03f7 | 3066 | unsigned int size_pages = rot_info->size >> PAGE_SHIFT; |
50470bb0 TU |
3067 | struct sg_page_iter sg_iter; |
3068 | unsigned long i; | |
3069 | dma_addr_t *page_addr_list; | |
3070 | struct sg_table *st; | |
1d00dad5 | 3071 | int ret = -ENOMEM; |
50470bb0 | 3072 | |
50470bb0 | 3073 | /* Allocate a temporary list of source pages for random access. */ |
84fe03f7 TU |
3074 | page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE, |
3075 | sizeof(dma_addr_t)); | |
50470bb0 TU |
3076 | if (!page_addr_list) |
3077 | return ERR_PTR(ret); | |
3078 | ||
3079 | /* Allocate target SG list. */ | |
3080 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3081 | if (!st) | |
3082 | goto err_st_alloc; | |
3083 | ||
84fe03f7 | 3084 | ret = sg_alloc_table(st, size_pages, GFP_KERNEL); |
50470bb0 TU |
3085 | if (ret) |
3086 | goto err_sg_alloc; | |
3087 | ||
3088 | /* Populate source page list from the object. */ | |
3089 | i = 0; | |
3090 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { | |
3091 | page_addr_list[i] = sg_page_iter_dma_address(&sg_iter); | |
3092 | i++; | |
3093 | } | |
3094 | ||
3095 | /* Rotate the pages. */ | |
84fe03f7 TU |
3096 | rotate_pages(page_addr_list, |
3097 | rot_info->width_pages, rot_info->height_pages, | |
3098 | st); | |
50470bb0 TU |
3099 | |
3100 | DRM_DEBUG_KMS( | |
84fe03f7 | 3101 | "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n", |
c9f8fd2d | 3102 | obj->base.size, rot_info->pitch, rot_info->height, |
84fe03f7 TU |
3103 | rot_info->pixel_format, rot_info->width_pages, |
3104 | rot_info->height_pages, size_pages); | |
50470bb0 TU |
3105 | |
3106 | drm_free_large(page_addr_list); | |
3107 | ||
3108 | return st; | |
3109 | ||
3110 | err_sg_alloc: | |
3111 | kfree(st); | |
3112 | err_st_alloc: | |
3113 | drm_free_large(page_addr_list); | |
3114 | ||
3115 | DRM_DEBUG_KMS( | |
84fe03f7 | 3116 | "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n", |
c9f8fd2d | 3117 | obj->base.size, ret, rot_info->pitch, rot_info->height, |
84fe03f7 TU |
3118 | rot_info->pixel_format, rot_info->width_pages, |
3119 | rot_info->height_pages, size_pages); | |
50470bb0 TU |
3120 | return ERR_PTR(ret); |
3121 | } | |
ec7adb6e | 3122 | |
8bd7ef16 JL |
3123 | static struct sg_table * |
3124 | intel_partial_pages(const struct i915_ggtt_view *view, | |
3125 | struct drm_i915_gem_object *obj) | |
3126 | { | |
3127 | struct sg_table *st; | |
3128 | struct scatterlist *sg; | |
3129 | struct sg_page_iter obj_sg_iter; | |
3130 | int ret = -ENOMEM; | |
3131 | ||
3132 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
3133 | if (!st) | |
3134 | goto err_st_alloc; | |
3135 | ||
3136 | ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL); | |
3137 | if (ret) | |
3138 | goto err_sg_alloc; | |
3139 | ||
3140 | sg = st->sgl; | |
3141 | st->nents = 0; | |
3142 | for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents, | |
3143 | view->params.partial.offset) | |
3144 | { | |
3145 | if (st->nents >= view->params.partial.size) | |
3146 | break; | |
3147 | ||
3148 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
3149 | sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter); | |
3150 | sg_dma_len(sg) = PAGE_SIZE; | |
3151 | ||
3152 | sg = sg_next(sg); | |
3153 | st->nents++; | |
3154 | } | |
3155 | ||
3156 | return st; | |
3157 | ||
3158 | err_sg_alloc: | |
3159 | kfree(st); | |
3160 | err_st_alloc: | |
3161 | return ERR_PTR(ret); | |
3162 | } | |
3163 | ||
70b9f6f8 | 3164 | static int |
50470bb0 | 3165 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 3166 | { |
50470bb0 TU |
3167 | int ret = 0; |
3168 | ||
fe14d5f4 TU |
3169 | if (vma->ggtt_view.pages) |
3170 | return 0; | |
3171 | ||
3172 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
3173 | vma->ggtt_view.pages = vma->obj->pages; | |
50470bb0 TU |
3174 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
3175 | vma->ggtt_view.pages = | |
3176 | intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj); | |
8bd7ef16 JL |
3177 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
3178 | vma->ggtt_view.pages = | |
3179 | intel_partial_pages(&vma->ggtt_view, vma->obj); | |
fe14d5f4 TU |
3180 | else |
3181 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
3182 | vma->ggtt_view.type); | |
3183 | ||
3184 | if (!vma->ggtt_view.pages) { | |
ec7adb6e | 3185 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 3186 | vma->ggtt_view.type); |
50470bb0 TU |
3187 | ret = -EINVAL; |
3188 | } else if (IS_ERR(vma->ggtt_view.pages)) { | |
3189 | ret = PTR_ERR(vma->ggtt_view.pages); | |
3190 | vma->ggtt_view.pages = NULL; | |
3191 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", | |
3192 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
3193 | } |
3194 | ||
50470bb0 | 3195 | return ret; |
fe14d5f4 TU |
3196 | } |
3197 | ||
3198 | /** | |
3199 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
3200 | * @vma: VMA to map | |
3201 | * @cache_level: mapping cache level | |
3202 | * @flags: flags like global or local mapping | |
3203 | * | |
3204 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
3205 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
3206 | * Note that DMA addresses are also the only part of the SG table we care about. | |
3207 | */ | |
3208 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
3209 | u32 flags) | |
3210 | { | |
75d04a37 MK |
3211 | int ret; |
3212 | u32 bind_flags; | |
1d335d1b | 3213 | |
75d04a37 MK |
3214 | if (WARN_ON(flags == 0)) |
3215 | return -EINVAL; | |
1d335d1b | 3216 | |
75d04a37 | 3217 | bind_flags = 0; |
0875546c DV |
3218 | if (flags & PIN_GLOBAL) |
3219 | bind_flags |= GLOBAL_BIND; | |
3220 | if (flags & PIN_USER) | |
3221 | bind_flags |= LOCAL_BIND; | |
3222 | ||
3223 | if (flags & PIN_UPDATE) | |
3224 | bind_flags |= vma->bound; | |
3225 | else | |
3226 | bind_flags &= ~vma->bound; | |
3227 | ||
75d04a37 MK |
3228 | if (bind_flags == 0) |
3229 | return 0; | |
3230 | ||
3231 | if (vma->bound == 0 && vma->vm->allocate_va_range) { | |
3232 | trace_i915_va_alloc(vma->vm, | |
3233 | vma->node.start, | |
3234 | vma->node.size, | |
3235 | VM_TO_TRACE_NAME(vma->vm)); | |
3236 | ||
b2dd4511 MK |
3237 | /* XXX: i915_vma_pin() will fix this +- hack */ |
3238 | vma->pin_count++; | |
75d04a37 MK |
3239 | ret = vma->vm->allocate_va_range(vma->vm, |
3240 | vma->node.start, | |
3241 | vma->node.size); | |
b2dd4511 | 3242 | vma->pin_count--; |
75d04a37 MK |
3243 | if (ret) |
3244 | return ret; | |
3245 | } | |
3246 | ||
3247 | ret = vma->vm->bind_vma(vma, cache_level, bind_flags); | |
70b9f6f8 DV |
3248 | if (ret) |
3249 | return ret; | |
0875546c DV |
3250 | |
3251 | vma->bound |= bind_flags; | |
fe14d5f4 TU |
3252 | |
3253 | return 0; | |
3254 | } | |
91e6711e JL |
3255 | |
3256 | /** | |
3257 | * i915_ggtt_view_size - Get the size of a GGTT view. | |
3258 | * @obj: Object the view is of. | |
3259 | * @view: The view in question. | |
3260 | * | |
3261 | * @return The size of the GGTT view in bytes. | |
3262 | */ | |
3263 | size_t | |
3264 | i915_ggtt_view_size(struct drm_i915_gem_object *obj, | |
3265 | const struct i915_ggtt_view *view) | |
3266 | { | |
9e759ff1 | 3267 | if (view->type == I915_GGTT_VIEW_NORMAL) { |
91e6711e | 3268 | return obj->base.size; |
9e759ff1 TU |
3269 | } else if (view->type == I915_GGTT_VIEW_ROTATED) { |
3270 | return view->rotation_info.size; | |
8bd7ef16 JL |
3271 | } else if (view->type == I915_GGTT_VIEW_PARTIAL) { |
3272 | return view->params.partial.size << PAGE_SHIFT; | |
91e6711e JL |
3273 | } else { |
3274 | WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type); | |
3275 | return obj->base.size; | |
3276 | } | |
3277 | } |