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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
c4ac524c | 3 | * Copyright © 2011-2014 Intel Corporation |
76aaf220 DV |
4 | * |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
22 | * IN THE SOFTWARE. | |
23 | * | |
24 | */ | |
25 | ||
0e46ce2e | 26 | #include <linux/seq_file.h> |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/i915_drm.h> | |
76aaf220 | 29 | #include "i915_drv.h" |
5dda8fa3 | 30 | #include "i915_vgpu.h" |
76aaf220 DV |
31 | #include "i915_trace.h" |
32 | #include "intel_drv.h" | |
33 | ||
45f8f69a TU |
34 | /** |
35 | * DOC: Global GTT views | |
36 | * | |
37 | * Background and previous state | |
38 | * | |
39 | * Historically objects could exists (be bound) in global GTT space only as | |
40 | * singular instances with a view representing all of the object's backing pages | |
41 | * in a linear fashion. This view will be called a normal view. | |
42 | * | |
43 | * To support multiple views of the same object, where the number of mapped | |
44 | * pages is not equal to the backing store, or where the layout of the pages | |
45 | * is not linear, concept of a GGTT view was added. | |
46 | * | |
47 | * One example of an alternative view is a stereo display driven by a single | |
48 | * image. In this case we would have a framebuffer looking like this | |
49 | * (2x2 pages): | |
50 | * | |
51 | * 12 | |
52 | * 34 | |
53 | * | |
54 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU | |
55 | * rendering. In contrast, fed to the display engine would be an alternative | |
56 | * view which could look something like this: | |
57 | * | |
58 | * 1212 | |
59 | * 3434 | |
60 | * | |
61 | * In this example both the size and layout of pages in the alternative view is | |
62 | * different from the normal view. | |
63 | * | |
64 | * Implementation and usage | |
65 | * | |
66 | * GGTT views are implemented using VMAs and are distinguished via enum | |
67 | * i915_ggtt_view_type and struct i915_ggtt_view. | |
68 | * | |
69 | * A new flavour of core GEM functions which work with GGTT bound objects were | |
ec7adb6e JL |
70 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
71 | * renaming in large amounts of code. They take the struct i915_ggtt_view | |
72 | * parameter encapsulating all metadata required to implement a view. | |
45f8f69a TU |
73 | * |
74 | * As a helper for callers which are only interested in the normal view, | |
75 | * globally const i915_ggtt_view_normal singleton instance exists. All old core | |
76 | * GEM API functions, the ones not taking the view parameter, are operating on, | |
77 | * or with the normal GGTT view. | |
78 | * | |
79 | * Code wanting to add or use a new GGTT view needs to: | |
80 | * | |
81 | * 1. Add a new enum with a suitable name. | |
82 | * 2. Extend the metadata in the i915_ggtt_view structure if required. | |
83 | * 3. Add support to i915_get_vma_pages(). | |
84 | * | |
85 | * New views are required to build a scatter-gather table from within the | |
86 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and | |
87 | * exists for the lifetime of an VMA. | |
88 | * | |
89 | * Core API is designed to have copy semantics which means that passed in | |
90 | * struct i915_ggtt_view does not need to be persistent (left around after | |
91 | * calling the core API functions). | |
92 | * | |
93 | */ | |
94 | ||
70b9f6f8 DV |
95 | static int |
96 | i915_get_ggtt_vma_pages(struct i915_vma *vma); | |
97 | ||
fe14d5f4 | 98 | const struct i915_ggtt_view i915_ggtt_view_normal; |
9abc4648 JL |
99 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
100 | .type = I915_GGTT_VIEW_ROTATED | |
101 | }; | |
fe14d5f4 | 102 | |
cfa7c862 DV |
103 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
104 | { | |
1893a71b CW |
105 | bool has_aliasing_ppgtt; |
106 | bool has_full_ppgtt; | |
107 | ||
108 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; | |
109 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; | |
1893a71b | 110 | |
71ba2d64 YZ |
111 | if (intel_vgpu_active(dev)) |
112 | has_full_ppgtt = false; /* emulation is too hard */ | |
113 | ||
70ee45e1 DL |
114 | /* |
115 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for | |
116 | * execlists, the sole mechanism available to submit work. | |
117 | */ | |
118 | if (INTEL_INFO(dev)->gen < 9 && | |
119 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) | |
cfa7c862 DV |
120 | return 0; |
121 | ||
122 | if (enable_ppgtt == 1) | |
123 | return 1; | |
124 | ||
1893a71b | 125 | if (enable_ppgtt == 2 && has_full_ppgtt) |
cfa7c862 DV |
126 | return 2; |
127 | ||
93a25a9e DV |
128 | #ifdef CONFIG_INTEL_IOMMU |
129 | /* Disable ppgtt on SNB if VT-d is on. */ | |
130 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
131 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
cfa7c862 | 132 | return 0; |
93a25a9e DV |
133 | } |
134 | #endif | |
135 | ||
62942ed7 | 136 | /* Early VLV doesn't have this */ |
ca2aed6c VS |
137 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
138 | dev->pdev->revision < 0xb) { | |
62942ed7 JB |
139 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
140 | return 0; | |
141 | } | |
142 | ||
2f82bbdf MT |
143 | if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) |
144 | return 2; | |
145 | else | |
146 | return has_aliasing_ppgtt ? 1 : 0; | |
93a25a9e DV |
147 | } |
148 | ||
70b9f6f8 DV |
149 | static int ppgtt_bind_vma(struct i915_vma *vma, |
150 | enum i915_cache_level cache_level, | |
151 | u32 unused) | |
47552659 DV |
152 | { |
153 | u32 pte_flags = 0; | |
154 | ||
155 | /* Currently applicable only to VLV */ | |
156 | if (vma->obj->gt_ro) | |
157 | pte_flags |= PTE_READ_ONLY; | |
158 | ||
159 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, | |
160 | cache_level, pte_flags); | |
70b9f6f8 DV |
161 | |
162 | return 0; | |
47552659 DV |
163 | } |
164 | ||
165 | static void ppgtt_unbind_vma(struct i915_vma *vma) | |
166 | { | |
167 | vma->vm->clear_range(vma->vm, | |
168 | vma->node.start, | |
169 | vma->obj->base.size, | |
170 | true); | |
171 | } | |
6f65e29a | 172 | |
2c642b07 DV |
173 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
174 | enum i915_cache_level level, | |
175 | bool valid) | |
94ec8f61 | 176 | { |
07749ef3 | 177 | gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
94ec8f61 | 178 | pte |= addr; |
63c42e56 BW |
179 | |
180 | switch (level) { | |
181 | case I915_CACHE_NONE: | |
fbe5d36e | 182 | pte |= PPAT_UNCACHED_INDEX; |
63c42e56 BW |
183 | break; |
184 | case I915_CACHE_WT: | |
185 | pte |= PPAT_DISPLAY_ELLC_INDEX; | |
186 | break; | |
187 | default: | |
188 | pte |= PPAT_CACHED_INDEX; | |
189 | break; | |
190 | } | |
191 | ||
94ec8f61 BW |
192 | return pte; |
193 | } | |
194 | ||
2c642b07 DV |
195 | static gen8_pde_t gen8_pde_encode(struct drm_device *dev, |
196 | dma_addr_t addr, | |
197 | enum i915_cache_level level) | |
b1fe6673 | 198 | { |
07749ef3 | 199 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
b1fe6673 BW |
200 | pde |= addr; |
201 | if (level != I915_CACHE_NONE) | |
202 | pde |= PPAT_CACHED_PDE_INDEX; | |
203 | else | |
204 | pde |= PPAT_UNCACHED_INDEX; | |
205 | return pde; | |
206 | } | |
207 | ||
07749ef3 MT |
208 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
209 | enum i915_cache_level level, | |
210 | bool valid, u32 unused) | |
54d12527 | 211 | { |
07749ef3 | 212 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
54d12527 | 213 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
214 | |
215 | switch (level) { | |
350ec881 CW |
216 | case I915_CACHE_L3_LLC: |
217 | case I915_CACHE_LLC: | |
218 | pte |= GEN6_PTE_CACHE_LLC; | |
219 | break; | |
220 | case I915_CACHE_NONE: | |
221 | pte |= GEN6_PTE_UNCACHED; | |
222 | break; | |
223 | default: | |
5f77eeb0 | 224 | MISSING_CASE(level); |
350ec881 CW |
225 | } |
226 | ||
227 | return pte; | |
228 | } | |
229 | ||
07749ef3 MT |
230 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
231 | enum i915_cache_level level, | |
232 | bool valid, u32 unused) | |
350ec881 | 233 | { |
07749ef3 | 234 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
350ec881 CW |
235 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
236 | ||
237 | switch (level) { | |
238 | case I915_CACHE_L3_LLC: | |
239 | pte |= GEN7_PTE_CACHE_L3_LLC; | |
e7210c3c BW |
240 | break; |
241 | case I915_CACHE_LLC: | |
242 | pte |= GEN6_PTE_CACHE_LLC; | |
243 | break; | |
244 | case I915_CACHE_NONE: | |
9119708c | 245 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
246 | break; |
247 | default: | |
5f77eeb0 | 248 | MISSING_CASE(level); |
e7210c3c BW |
249 | } |
250 | ||
54d12527 BW |
251 | return pte; |
252 | } | |
253 | ||
07749ef3 MT |
254 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
255 | enum i915_cache_level level, | |
256 | bool valid, u32 flags) | |
93c34e70 | 257 | { |
07749ef3 | 258 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
93c34e70 KG |
259 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
260 | ||
24f3a8cf AG |
261 | if (!(flags & PTE_READ_ONLY)) |
262 | pte |= BYT_PTE_WRITEABLE; | |
93c34e70 KG |
263 | |
264 | if (level != I915_CACHE_NONE) | |
265 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
266 | ||
267 | return pte; | |
268 | } | |
269 | ||
07749ef3 MT |
270 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
271 | enum i915_cache_level level, | |
272 | bool valid, u32 unused) | |
9119708c | 273 | { |
07749ef3 | 274 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
0d8ff15e | 275 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
276 | |
277 | if (level != I915_CACHE_NONE) | |
87a6b688 | 278 | pte |= HSW_WB_LLC_AGE3; |
9119708c KG |
279 | |
280 | return pte; | |
281 | } | |
282 | ||
07749ef3 MT |
283 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
284 | enum i915_cache_level level, | |
285 | bool valid, u32 unused) | |
4d15c145 | 286 | { |
07749ef3 | 287 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
4d15c145 BW |
288 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
289 | ||
651d794f CW |
290 | switch (level) { |
291 | case I915_CACHE_NONE: | |
292 | break; | |
293 | case I915_CACHE_WT: | |
c51e9701 | 294 | pte |= HSW_WT_ELLC_LLC_AGE3; |
651d794f CW |
295 | break; |
296 | default: | |
c51e9701 | 297 | pte |= HSW_WB_ELLC_LLC_AGE3; |
651d794f CW |
298 | break; |
299 | } | |
4d15c145 BW |
300 | |
301 | return pte; | |
302 | } | |
303 | ||
44159ddb | 304 | static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
678d96fb BW |
305 | { |
306 | struct device *device = &dev->pdev->dev; | |
307 | ||
44159ddb MK |
308 | p->page = alloc_page(GFP_KERNEL); |
309 | if (!p->page) | |
310 | return -ENOMEM; | |
678d96fb | 311 | |
44159ddb MK |
312 | p->daddr = dma_map_page(device, |
313 | p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL); | |
678d96fb | 314 | |
44159ddb MK |
315 | if (dma_mapping_error(device, p->daddr)) { |
316 | __free_page(p->page); | |
317 | return -EINVAL; | |
318 | } | |
1266cdb1 MT |
319 | |
320 | return 0; | |
678d96fb BW |
321 | } |
322 | ||
44159ddb | 323 | static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
06fda602 | 324 | { |
44159ddb | 325 | if (WARN_ON(!p->page)) |
06fda602 | 326 | return; |
678d96fb | 327 | |
44159ddb MK |
328 | dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL); |
329 | __free_page(p->page); | |
330 | memset(p, 0, sizeof(*p)); | |
331 | } | |
332 | ||
d1c54acd | 333 | static void *kmap_page_dma(struct i915_page_dma *p) |
73eeea53 | 334 | { |
d1c54acd MK |
335 | return kmap_atomic(p->page); |
336 | } | |
73eeea53 | 337 | |
d1c54acd MK |
338 | /* We use the flushing unmap only with ppgtt structures: |
339 | * page directories, page tables and scratch pages. | |
340 | */ | |
341 | static void kunmap_page_dma(struct drm_device *dev, void *vaddr) | |
342 | { | |
73eeea53 MK |
343 | /* There are only few exceptions for gen >=6. chv and bxt. |
344 | * And we are not sure about the latter so play safe for now. | |
345 | */ | |
346 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) | |
347 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
348 | ||
349 | kunmap_atomic(vaddr); | |
350 | } | |
351 | ||
d1c54acd MK |
352 | #define kmap_px(px) kmap_page_dma(&(px)->base) |
353 | #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr)) | |
354 | ||
355 | static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p, | |
356 | const uint64_t val) | |
357 | { | |
358 | int i; | |
359 | uint64_t * const vaddr = kmap_page_dma(p); | |
360 | ||
361 | for (i = 0; i < 512; i++) | |
362 | vaddr[i] = val; | |
363 | ||
364 | kunmap_page_dma(dev, vaddr); | |
365 | } | |
366 | ||
73eeea53 MK |
367 | static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p, |
368 | const uint32_t val32) | |
369 | { | |
370 | uint64_t v = val32; | |
371 | ||
372 | v = v << 32 | val32; | |
373 | ||
374 | fill_page_dma(dev, p, v); | |
375 | } | |
376 | ||
a08e111a | 377 | static void free_pt(struct drm_device *dev, struct i915_page_table *pt) |
44159ddb MK |
378 | { |
379 | cleanup_page_dma(dev, &pt->base); | |
678d96fb | 380 | kfree(pt->used_ptes); |
06fda602 BW |
381 | kfree(pt); |
382 | } | |
383 | ||
5a8e9943 | 384 | static void gen8_initialize_pt(struct i915_address_space *vm, |
e5815a2e | 385 | struct i915_page_table *pt) |
5a8e9943 | 386 | { |
73eeea53 | 387 | gen8_pte_t scratch_pte; |
5a8e9943 | 388 | |
73eeea53 | 389 | scratch_pte = gen8_pte_encode(vm->scratch.addr, I915_CACHE_LLC, true); |
5a8e9943 | 390 | |
73eeea53 | 391 | fill_page_dma(vm->dev, &pt->base, scratch_pte); |
5a8e9943 MT |
392 | } |
393 | ||
8a1ebd74 | 394 | static struct i915_page_table *alloc_pt(struct drm_device *dev) |
06fda602 | 395 | { |
ec565b3c | 396 | struct i915_page_table *pt; |
678d96fb BW |
397 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
398 | GEN8_PTES : GEN6_PTES; | |
399 | int ret = -ENOMEM; | |
06fda602 BW |
400 | |
401 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); | |
402 | if (!pt) | |
403 | return ERR_PTR(-ENOMEM); | |
404 | ||
678d96fb BW |
405 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
406 | GFP_KERNEL); | |
407 | ||
408 | if (!pt->used_ptes) | |
409 | goto fail_bitmap; | |
410 | ||
44159ddb | 411 | ret = setup_page_dma(dev, &pt->base); |
678d96fb | 412 | if (ret) |
44159ddb | 413 | goto fail_page_m; |
06fda602 BW |
414 | |
415 | return pt; | |
678d96fb | 416 | |
44159ddb | 417 | fail_page_m: |
678d96fb BW |
418 | kfree(pt->used_ptes); |
419 | fail_bitmap: | |
420 | kfree(pt); | |
421 | ||
422 | return ERR_PTR(ret); | |
06fda602 BW |
423 | } |
424 | ||
a08e111a | 425 | static void free_pd(struct drm_device *dev, struct i915_page_directory *pd) |
06fda602 | 426 | { |
44159ddb MK |
427 | if (pd->base.page) { |
428 | cleanup_page_dma(dev, &pd->base); | |
33c8819f | 429 | kfree(pd->used_pdes); |
06fda602 BW |
430 | kfree(pd); |
431 | } | |
432 | } | |
433 | ||
8a1ebd74 | 434 | static struct i915_page_directory *alloc_pd(struct drm_device *dev) |
06fda602 | 435 | { |
ec565b3c | 436 | struct i915_page_directory *pd; |
33c8819f | 437 | int ret = -ENOMEM; |
06fda602 BW |
438 | |
439 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); | |
440 | if (!pd) | |
441 | return ERR_PTR(-ENOMEM); | |
442 | ||
33c8819f MT |
443 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
444 | sizeof(*pd->used_pdes), GFP_KERNEL); | |
445 | if (!pd->used_pdes) | |
a08e111a | 446 | goto fail_bitmap; |
33c8819f | 447 | |
44159ddb | 448 | ret = setup_page_dma(dev, &pd->base); |
33c8819f | 449 | if (ret) |
a08e111a | 450 | goto fail_page_m; |
e5815a2e | 451 | |
06fda602 | 452 | return pd; |
33c8819f | 453 | |
a08e111a | 454 | fail_page_m: |
33c8819f | 455 | kfree(pd->used_pdes); |
a08e111a | 456 | fail_bitmap: |
33c8819f MT |
457 | kfree(pd); |
458 | ||
459 | return ERR_PTR(ret); | |
06fda602 BW |
460 | } |
461 | ||
94e409c1 | 462 | /* Broadwell Page Directory Pointer Descriptors */ |
e85b26dc | 463 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
7cb6d7ac MT |
464 | unsigned entry, |
465 | dma_addr_t addr) | |
94e409c1 | 466 | { |
e85b26dc | 467 | struct intel_engine_cs *ring = req->ring; |
94e409c1 BW |
468 | int ret; |
469 | ||
470 | BUG_ON(entry >= 4); | |
471 | ||
5fb9de1a | 472 | ret = intel_ring_begin(req, 6); |
94e409c1 BW |
473 | if (ret) |
474 | return ret; | |
475 | ||
476 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
477 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); | |
7cb6d7ac | 478 | intel_ring_emit(ring, upper_32_bits(addr)); |
94e409c1 BW |
479 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
480 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); | |
7cb6d7ac | 481 | intel_ring_emit(ring, lower_32_bits(addr)); |
94e409c1 BW |
482 | intel_ring_advance(ring); |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
eeb9488e | 487 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 488 | struct drm_i915_gem_request *req) |
94e409c1 | 489 | { |
eeb9488e | 490 | int i, ret; |
94e409c1 | 491 | |
7cb6d7ac | 492 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
d852c7bf MK |
493 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
494 | ||
e85b26dc | 495 | ret = gen8_write_pdp(req, i, pd_daddr); |
eeb9488e BW |
496 | if (ret) |
497 | return ret; | |
94e409c1 | 498 | } |
d595bd4b | 499 | |
eeb9488e | 500 | return 0; |
94e409c1 BW |
501 | } |
502 | ||
459108b8 | 503 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
504 | uint64_t start, |
505 | uint64_t length, | |
459108b8 BW |
506 | bool use_scratch) |
507 | { | |
508 | struct i915_hw_ppgtt *ppgtt = | |
509 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 510 | gen8_pte_t *pt_vaddr, scratch_pte; |
7ad47cf2 BW |
511 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
512 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
513 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
782f1495 | 514 | unsigned num_entries = length >> PAGE_SHIFT; |
459108b8 BW |
515 | unsigned last_pte, i; |
516 | ||
517 | scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, | |
518 | I915_CACHE_LLC, use_scratch); | |
519 | ||
520 | while (num_entries) { | |
ec565b3c MT |
521 | struct i915_page_directory *pd; |
522 | struct i915_page_table *pt; | |
06fda602 BW |
523 | |
524 | if (WARN_ON(!ppgtt->pdp.page_directory[pdpe])) | |
525 | continue; | |
526 | ||
527 | pd = ppgtt->pdp.page_directory[pdpe]; | |
528 | ||
529 | if (WARN_ON(!pd->page_table[pde])) | |
530 | continue; | |
531 | ||
532 | pt = pd->page_table[pde]; | |
533 | ||
44159ddb | 534 | if (WARN_ON(!pt->base.page)) |
06fda602 BW |
535 | continue; |
536 | ||
7ad47cf2 | 537 | last_pte = pte + num_entries; |
07749ef3 MT |
538 | if (last_pte > GEN8_PTES) |
539 | last_pte = GEN8_PTES; | |
459108b8 | 540 | |
d1c54acd | 541 | pt_vaddr = kmap_px(pt); |
459108b8 | 542 | |
7ad47cf2 | 543 | for (i = pte; i < last_pte; i++) { |
459108b8 | 544 | pt_vaddr[i] = scratch_pte; |
7ad47cf2 BW |
545 | num_entries--; |
546 | } | |
459108b8 | 547 | |
d1c54acd | 548 | kunmap_px(ppgtt, pt); |
459108b8 | 549 | |
7ad47cf2 | 550 | pte = 0; |
07749ef3 | 551 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
552 | pdpe++; |
553 | pde = 0; | |
554 | } | |
459108b8 BW |
555 | } |
556 | } | |
557 | ||
9df15b49 BW |
558 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
559 | struct sg_table *pages, | |
782f1495 | 560 | uint64_t start, |
24f3a8cf | 561 | enum i915_cache_level cache_level, u32 unused) |
9df15b49 BW |
562 | { |
563 | struct i915_hw_ppgtt *ppgtt = | |
564 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 565 | gen8_pte_t *pt_vaddr; |
7ad47cf2 BW |
566 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
567 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; | |
568 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; | |
9df15b49 BW |
569 | struct sg_page_iter sg_iter; |
570 | ||
6f1cc993 | 571 | pt_vaddr = NULL; |
7ad47cf2 | 572 | |
9df15b49 | 573 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
76643600 | 574 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) |
7ad47cf2 BW |
575 | break; |
576 | ||
d7b3de91 | 577 | if (pt_vaddr == NULL) { |
ec565b3c MT |
578 | struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe]; |
579 | struct i915_page_table *pt = pd->page_table[pde]; | |
d1c54acd | 580 | pt_vaddr = kmap_px(pt); |
d7b3de91 | 581 | } |
9df15b49 | 582 | |
7ad47cf2 | 583 | pt_vaddr[pte] = |
6f1cc993 CW |
584 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
585 | cache_level, true); | |
07749ef3 | 586 | if (++pte == GEN8_PTES) { |
d1c54acd | 587 | kunmap_px(ppgtt, pt_vaddr); |
6f1cc993 | 588 | pt_vaddr = NULL; |
07749ef3 | 589 | if (++pde == I915_PDES) { |
7ad47cf2 BW |
590 | pdpe++; |
591 | pde = 0; | |
592 | } | |
593 | pte = 0; | |
9df15b49 BW |
594 | } |
595 | } | |
d1c54acd MK |
596 | |
597 | if (pt_vaddr) | |
598 | kunmap_px(ppgtt, pt_vaddr); | |
9df15b49 BW |
599 | } |
600 | ||
69876bed MT |
601 | static void __gen8_do_map_pt(gen8_pde_t * const pde, |
602 | struct i915_page_table *pt, | |
603 | struct drm_device *dev) | |
604 | { | |
605 | gen8_pde_t entry = | |
44159ddb | 606 | gen8_pde_encode(dev, pt->base.daddr, I915_CACHE_LLC); |
69876bed MT |
607 | *pde = entry; |
608 | } | |
609 | ||
610 | static void gen8_initialize_pd(struct i915_address_space *vm, | |
611 | struct i915_page_directory *pd) | |
612 | { | |
613 | struct i915_hw_ppgtt *ppgtt = | |
73eeea53 MK |
614 | container_of(vm, struct i915_hw_ppgtt, base); |
615 | gen8_pde_t scratch_pde; | |
69876bed | 616 | |
73eeea53 MK |
617 | scratch_pde = gen8_pde_encode(vm->dev, ppgtt->scratch_pt->base.daddr, |
618 | I915_CACHE_LLC); | |
69876bed | 619 | |
73eeea53 | 620 | fill_page_dma(vm->dev, &pd->base, scratch_pde); |
e5815a2e MT |
621 | } |
622 | ||
ec565b3c | 623 | static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev) |
7ad47cf2 BW |
624 | { |
625 | int i; | |
626 | ||
44159ddb | 627 | if (!pd->base.page) |
7ad47cf2 BW |
628 | return; |
629 | ||
33c8819f | 630 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
06fda602 BW |
631 | if (WARN_ON(!pd->page_table[i])) |
632 | continue; | |
7ad47cf2 | 633 | |
a08e111a | 634 | free_pt(dev, pd->page_table[i]); |
06fda602 BW |
635 | pd->page_table[i] = NULL; |
636 | } | |
d7b3de91 BW |
637 | } |
638 | ||
061dd493 | 639 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
b45a6715 | 640 | { |
061dd493 DV |
641 | struct i915_hw_ppgtt *ppgtt = |
642 | container_of(vm, struct i915_hw_ppgtt, base); | |
b45a6715 BW |
643 | int i; |
644 | ||
33c8819f | 645 | for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) { |
06fda602 BW |
646 | if (WARN_ON(!ppgtt->pdp.page_directory[i])) |
647 | continue; | |
648 | ||
06dc68d6 | 649 | gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); |
a08e111a | 650 | free_pd(ppgtt->base.dev, ppgtt->pdp.page_directory[i]); |
7ad47cf2 | 651 | } |
69876bed | 652 | |
a08e111a MK |
653 | free_pd(ppgtt->base.dev, ppgtt->scratch_pd); |
654 | free_pt(ppgtt->base.dev, ppgtt->scratch_pt); | |
b45a6715 BW |
655 | } |
656 | ||
d7b2633d MT |
657 | /** |
658 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. | |
659 | * @ppgtt: Master ppgtt structure. | |
660 | * @pd: Page directory for this address range. | |
661 | * @start: Starting virtual address to begin allocations. | |
662 | * @length Size of the allocations. | |
663 | * @new_pts: Bitmap set by function with new allocations. Likely used by the | |
664 | * caller to free on error. | |
665 | * | |
666 | * Allocate the required number of page tables. Extremely similar to | |
667 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by | |
668 | * the page directory boundary (instead of the page directory pointer). That | |
669 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is | |
670 | * possible, and likely that the caller will need to use multiple calls of this | |
671 | * function to achieve the appropriate allocation. | |
672 | * | |
673 | * Return: 0 if success; negative error code otherwise. | |
674 | */ | |
e5815a2e MT |
675 | static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt, |
676 | struct i915_page_directory *pd, | |
5441f0cb | 677 | uint64_t start, |
d7b2633d MT |
678 | uint64_t length, |
679 | unsigned long *new_pts) | |
bf2b4ed2 | 680 | { |
e5815a2e | 681 | struct drm_device *dev = ppgtt->base.dev; |
d7b2633d | 682 | struct i915_page_table *pt; |
5441f0cb MT |
683 | uint64_t temp; |
684 | uint32_t pde; | |
bf2b4ed2 | 685 | |
d7b2633d MT |
686 | gen8_for_each_pde(pt, pd, start, length, temp, pde) { |
687 | /* Don't reallocate page tables */ | |
688 | if (pt) { | |
689 | /* Scratch is never allocated this way */ | |
690 | WARN_ON(pt == ppgtt->scratch_pt); | |
691 | continue; | |
692 | } | |
693 | ||
8a1ebd74 | 694 | pt = alloc_pt(dev); |
d7b2633d | 695 | if (IS_ERR(pt)) |
5441f0cb MT |
696 | goto unwind_out; |
697 | ||
d7b2633d MT |
698 | gen8_initialize_pt(&ppgtt->base, pt); |
699 | pd->page_table[pde] = pt; | |
700 | set_bit(pde, new_pts); | |
7ad47cf2 BW |
701 | } |
702 | ||
bf2b4ed2 | 703 | return 0; |
7ad47cf2 BW |
704 | |
705 | unwind_out: | |
d7b2633d | 706 | for_each_set_bit(pde, new_pts, I915_PDES) |
a08e111a | 707 | free_pt(dev, pd->page_table[pde]); |
7ad47cf2 | 708 | |
d7b3de91 | 709 | return -ENOMEM; |
bf2b4ed2 BW |
710 | } |
711 | ||
d7b2633d MT |
712 | /** |
713 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. | |
714 | * @ppgtt: Master ppgtt structure. | |
715 | * @pdp: Page directory pointer for this address range. | |
716 | * @start: Starting virtual address to begin allocations. | |
717 | * @length Size of the allocations. | |
718 | * @new_pds Bitmap set by function with new allocations. Likely used by the | |
719 | * caller to free on error. | |
720 | * | |
721 | * Allocate the required number of page directories starting at the pde index of | |
722 | * @start, and ending at the pde index @start + @length. This function will skip | |
723 | * over already allocated page directories within the range, and only allocate | |
724 | * new ones, setting the appropriate pointer within the pdp as well as the | |
725 | * correct position in the bitmap @new_pds. | |
726 | * | |
727 | * The function will only allocate the pages within the range for a give page | |
728 | * directory pointer. In other words, if @start + @length straddles a virtually | |
729 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations | |
730 | * required by the caller, This is not currently possible, and the BUG in the | |
731 | * code will prevent it. | |
732 | * | |
733 | * Return: 0 if success; negative error code otherwise. | |
734 | */ | |
c488dbba MT |
735 | static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, |
736 | struct i915_page_directory_pointer *pdp, | |
69876bed | 737 | uint64_t start, |
d7b2633d MT |
738 | uint64_t length, |
739 | unsigned long *new_pds) | |
bf2b4ed2 | 740 | { |
e5815a2e | 741 | struct drm_device *dev = ppgtt->base.dev; |
d7b2633d | 742 | struct i915_page_directory *pd; |
69876bed MT |
743 | uint64_t temp; |
744 | uint32_t pdpe; | |
745 | ||
d7b2633d MT |
746 | WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES)); |
747 | ||
d7b2633d MT |
748 | gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { |
749 | if (pd) | |
750 | continue; | |
33c8819f | 751 | |
8a1ebd74 | 752 | pd = alloc_pd(dev); |
d7b2633d | 753 | if (IS_ERR(pd)) |
d7b3de91 | 754 | goto unwind_out; |
69876bed | 755 | |
d7b2633d MT |
756 | gen8_initialize_pd(&ppgtt->base, pd); |
757 | pdp->page_directory[pdpe] = pd; | |
758 | set_bit(pdpe, new_pds); | |
d7b3de91 BW |
759 | } |
760 | ||
bf2b4ed2 | 761 | return 0; |
d7b3de91 BW |
762 | |
763 | unwind_out: | |
d7b2633d | 764 | for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES) |
a08e111a | 765 | free_pd(dev, pdp->page_directory[pdpe]); |
d7b3de91 BW |
766 | |
767 | return -ENOMEM; | |
bf2b4ed2 BW |
768 | } |
769 | ||
d7b2633d MT |
770 | static void |
771 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts) | |
772 | { | |
773 | int i; | |
774 | ||
775 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) | |
776 | kfree(new_pts[i]); | |
777 | kfree(new_pts); | |
778 | kfree(new_pds); | |
779 | } | |
780 | ||
781 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both | |
782 | * of these are based on the number of PDPEs in the system. | |
783 | */ | |
784 | static | |
785 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, | |
786 | unsigned long ***new_pts) | |
787 | { | |
788 | int i; | |
789 | unsigned long *pds; | |
790 | unsigned long **pts; | |
791 | ||
792 | pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL); | |
793 | if (!pds) | |
794 | return -ENOMEM; | |
795 | ||
796 | pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL); | |
797 | if (!pts) { | |
798 | kfree(pds); | |
799 | return -ENOMEM; | |
800 | } | |
801 | ||
802 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { | |
803 | pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES), | |
804 | sizeof(unsigned long), GFP_KERNEL); | |
805 | if (!pts[i]) | |
806 | goto err_out; | |
807 | } | |
808 | ||
809 | *new_pds = pds; | |
810 | *new_pts = pts; | |
811 | ||
812 | return 0; | |
813 | ||
814 | err_out: | |
815 | free_gen8_temp_bitmaps(pds, pts); | |
816 | return -ENOMEM; | |
817 | } | |
818 | ||
5b7e4c9c MK |
819 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
820 | * the page table structures, we mark them dirty so that | |
821 | * context switching/execlist queuing code takes extra steps | |
822 | * to ensure that tlbs are flushed. | |
823 | */ | |
824 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) | |
825 | { | |
826 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; | |
827 | } | |
828 | ||
e5815a2e MT |
829 | static int gen8_alloc_va_range(struct i915_address_space *vm, |
830 | uint64_t start, | |
831 | uint64_t length) | |
bf2b4ed2 | 832 | { |
e5815a2e MT |
833 | struct i915_hw_ppgtt *ppgtt = |
834 | container_of(vm, struct i915_hw_ppgtt, base); | |
d7b2633d | 835 | unsigned long *new_page_dirs, **new_page_tables; |
5441f0cb | 836 | struct i915_page_directory *pd; |
33c8819f MT |
837 | const uint64_t orig_start = start; |
838 | const uint64_t orig_length = length; | |
5441f0cb MT |
839 | uint64_t temp; |
840 | uint32_t pdpe; | |
bf2b4ed2 BW |
841 | int ret; |
842 | ||
d7b2633d MT |
843 | /* Wrap is never okay since we can only represent 48b, and we don't |
844 | * actually use the other side of the canonical address space. | |
845 | */ | |
846 | if (WARN_ON(start + length < start)) | |
a05d80ee MK |
847 | return -ENODEV; |
848 | ||
849 | if (WARN_ON(start + length > ppgtt->base.total)) | |
850 | return -ENODEV; | |
d7b2633d MT |
851 | |
852 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables); | |
bf2b4ed2 BW |
853 | if (ret) |
854 | return ret; | |
855 | ||
d7b2633d MT |
856 | /* Do the allocations first so we can easily bail out */ |
857 | ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length, | |
858 | new_page_dirs); | |
859 | if (ret) { | |
860 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); | |
861 | return ret; | |
862 | } | |
863 | ||
864 | /* For every page directory referenced, allocate page tables */ | |
5441f0cb | 865 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
d7b2633d MT |
866 | ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length, |
867 | new_page_tables[pdpe]); | |
5441f0cb MT |
868 | if (ret) |
869 | goto err_out; | |
5441f0cb MT |
870 | } |
871 | ||
33c8819f MT |
872 | start = orig_start; |
873 | length = orig_length; | |
874 | ||
d7b2633d MT |
875 | /* Allocations have completed successfully, so set the bitmaps, and do |
876 | * the mappings. */ | |
33c8819f | 877 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
d1c54acd | 878 | gen8_pde_t *const page_directory = kmap_px(pd); |
33c8819f MT |
879 | struct i915_page_table *pt; |
880 | uint64_t pd_len = gen8_clamp_pd(start, length); | |
881 | uint64_t pd_start = start; | |
882 | uint32_t pde; | |
883 | ||
d7b2633d MT |
884 | /* Every pd should be allocated, we just did that above. */ |
885 | WARN_ON(!pd); | |
886 | ||
887 | gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) { | |
888 | /* Same reasoning as pd */ | |
889 | WARN_ON(!pt); | |
890 | WARN_ON(!pd_len); | |
891 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); | |
892 | ||
893 | /* Set our used ptes within the page table */ | |
894 | bitmap_set(pt->used_ptes, | |
895 | gen8_pte_index(pd_start), | |
896 | gen8_pte_count(pd_start, pd_len)); | |
897 | ||
898 | /* Our pde is now pointing to the pagetable, pt */ | |
33c8819f | 899 | set_bit(pde, pd->used_pdes); |
d7b2633d MT |
900 | |
901 | /* Map the PDE to the page table */ | |
902 | __gen8_do_map_pt(page_directory + pde, pt, vm->dev); | |
903 | ||
904 | /* NB: We haven't yet mapped ptes to pages. At this | |
905 | * point we're still relying on insert_entries() */ | |
33c8819f | 906 | } |
d7b2633d | 907 | |
d1c54acd | 908 | kunmap_px(ppgtt, page_directory); |
d7b2633d | 909 | |
33c8819f MT |
910 | set_bit(pdpe, ppgtt->pdp.used_pdpes); |
911 | } | |
912 | ||
d7b2633d | 913 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
5b7e4c9c | 914 | mark_tlbs_dirty(ppgtt); |
d7b3de91 | 915 | return 0; |
bf2b4ed2 | 916 | |
d7b3de91 | 917 | err_out: |
d7b2633d MT |
918 | while (pdpe--) { |
919 | for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES) | |
a08e111a | 920 | free_pt(vm->dev, ppgtt->pdp.page_directory[pdpe]->page_table[temp]); |
d7b2633d MT |
921 | } |
922 | ||
923 | for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES) | |
a08e111a | 924 | free_pd(vm->dev, ppgtt->pdp.page_directory[pdpe]); |
d7b2633d MT |
925 | |
926 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); | |
5b7e4c9c | 927 | mark_tlbs_dirty(ppgtt); |
bf2b4ed2 BW |
928 | return ret; |
929 | } | |
930 | ||
eb0b44ad | 931 | /* |
f3a964b9 BW |
932 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
933 | * with a net effect resembling a 2-level page table in normal x86 terms. Each | |
934 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address | |
935 | * space. | |
37aca44a | 936 | * |
f3a964b9 | 937 | */ |
5c5f6457 | 938 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
37aca44a | 939 | { |
8a1ebd74 | 940 | ppgtt->scratch_pt = alloc_pt(ppgtt->base.dev); |
69876bed MT |
941 | if (IS_ERR(ppgtt->scratch_pt)) |
942 | return PTR_ERR(ppgtt->scratch_pt); | |
943 | ||
8a1ebd74 | 944 | ppgtt->scratch_pd = alloc_pd(ppgtt->base.dev); |
7cb6d7ac MT |
945 | if (IS_ERR(ppgtt->scratch_pd)) |
946 | return PTR_ERR(ppgtt->scratch_pd); | |
947 | ||
69876bed | 948 | gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); |
7cb6d7ac | 949 | gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd); |
69876bed | 950 | |
d7b2633d | 951 | ppgtt->base.start = 0; |
5c5f6457 | 952 | ppgtt->base.total = 1ULL << 32; |
501fd70f MT |
953 | if (IS_ENABLED(CONFIG_X86_32)) |
954 | /* While we have a proliferation of size_t variables | |
955 | * we cannot represent the full ppgtt size on 32bit, | |
956 | * so limit it to the same size as the GGTT (currently | |
957 | * 2GiB). | |
958 | */ | |
959 | ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total; | |
d7b2633d | 960 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
5c5f6457 | 961 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
d7b2633d | 962 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
c7e16f22 | 963 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
777dc5bb DV |
964 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
965 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
d7b2633d MT |
966 | |
967 | ppgtt->switch_mm = gen8_mm_switch; | |
968 | ||
969 | return 0; | |
970 | } | |
971 | ||
87d60b63 BW |
972 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
973 | { | |
87d60b63 | 974 | struct i915_address_space *vm = &ppgtt->base; |
09942c65 | 975 | struct i915_page_table *unused; |
07749ef3 | 976 | gen6_pte_t scratch_pte; |
87d60b63 | 977 | uint32_t pd_entry; |
09942c65 MT |
978 | uint32_t pte, pde, temp; |
979 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; | |
87d60b63 | 980 | |
24f3a8cf | 981 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
87d60b63 | 982 | |
09942c65 | 983 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) { |
87d60b63 | 984 | u32 expected; |
07749ef3 | 985 | gen6_pte_t *pt_vaddr; |
44159ddb | 986 | dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->base.daddr; |
09942c65 | 987 | pd_entry = readl(ppgtt->pd_addr + pde); |
87d60b63 BW |
988 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
989 | ||
990 | if (pd_entry != expected) | |
991 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", | |
992 | pde, | |
993 | pd_entry, | |
994 | expected); | |
995 | seq_printf(m, "\tPDE: %x\n", pd_entry); | |
996 | ||
d1c54acd MK |
997 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
998 | ||
07749ef3 | 999 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
87d60b63 | 1000 | unsigned long va = |
07749ef3 | 1001 | (pde * PAGE_SIZE * GEN6_PTES) + |
87d60b63 BW |
1002 | (pte * PAGE_SIZE); |
1003 | int i; | |
1004 | bool found = false; | |
1005 | for (i = 0; i < 4; i++) | |
1006 | if (pt_vaddr[pte + i] != scratch_pte) | |
1007 | found = true; | |
1008 | if (!found) | |
1009 | continue; | |
1010 | ||
1011 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); | |
1012 | for (i = 0; i < 4; i++) { | |
1013 | if (pt_vaddr[pte + i] != scratch_pte) | |
1014 | seq_printf(m, " %08x", pt_vaddr[pte + i]); | |
1015 | else | |
1016 | seq_puts(m, " SCRATCH "); | |
1017 | } | |
1018 | seq_puts(m, "\n"); | |
1019 | } | |
d1c54acd | 1020 | kunmap_px(ppgtt, pt_vaddr); |
87d60b63 BW |
1021 | } |
1022 | } | |
1023 | ||
678d96fb | 1024 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
ec565b3c MT |
1025 | static void gen6_write_pde(struct i915_page_directory *pd, |
1026 | const int pde, struct i915_page_table *pt) | |
6197349b | 1027 | { |
678d96fb BW |
1028 | /* Caller needs to make sure the write completes if necessary */ |
1029 | struct i915_hw_ppgtt *ppgtt = | |
1030 | container_of(pd, struct i915_hw_ppgtt, pd); | |
1031 | u32 pd_entry; | |
6197349b | 1032 | |
44159ddb | 1033 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt->base.daddr); |
678d96fb | 1034 | pd_entry |= GEN6_PDE_VALID; |
6197349b | 1035 | |
678d96fb BW |
1036 | writel(pd_entry, ppgtt->pd_addr + pde); |
1037 | } | |
6197349b | 1038 | |
678d96fb BW |
1039 | /* Write all the page tables found in the ppgtt structure to incrementing page |
1040 | * directories. */ | |
1041 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, | |
ec565b3c | 1042 | struct i915_page_directory *pd, |
678d96fb BW |
1043 | uint32_t start, uint32_t length) |
1044 | { | |
ec565b3c | 1045 | struct i915_page_table *pt; |
678d96fb BW |
1046 | uint32_t pde, temp; |
1047 | ||
1048 | gen6_for_each_pde(pt, pd, start, length, temp, pde) | |
1049 | gen6_write_pde(pd, pde, pt); | |
1050 | ||
1051 | /* Make sure write is complete before other code can use this page | |
1052 | * table. Also require for WC mapped PTEs */ | |
1053 | readl(dev_priv->gtt.gsm); | |
3e302542 BW |
1054 | } |
1055 | ||
b4a74e3a | 1056 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
3e302542 | 1057 | { |
44159ddb | 1058 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
b4a74e3a | 1059 | |
44159ddb | 1060 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
b4a74e3a BW |
1061 | } |
1062 | ||
90252e5c | 1063 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1064 | struct drm_i915_gem_request *req) |
90252e5c | 1065 | { |
e85b26dc | 1066 | struct intel_engine_cs *ring = req->ring; |
90252e5c BW |
1067 | int ret; |
1068 | ||
90252e5c | 1069 | /* NB: TLBs must be flushed and invalidated before a switch */ |
a84c3ae1 | 1070 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
90252e5c BW |
1071 | if (ret) |
1072 | return ret; | |
1073 | ||
5fb9de1a | 1074 | ret = intel_ring_begin(req, 6); |
90252e5c BW |
1075 | if (ret) |
1076 | return ret; | |
1077 | ||
1078 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1079 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1080 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1081 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1082 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1083 | intel_ring_emit(ring, MI_NOOP); | |
1084 | intel_ring_advance(ring); | |
1085 | ||
1086 | return 0; | |
1087 | } | |
1088 | ||
71ba2d64 | 1089 | static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1090 | struct drm_i915_gem_request *req) |
71ba2d64 | 1091 | { |
e85b26dc | 1092 | struct intel_engine_cs *ring = req->ring; |
71ba2d64 YZ |
1093 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); |
1094 | ||
1095 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
1096 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1097 | return 0; | |
1098 | } | |
1099 | ||
48a10389 | 1100 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1101 | struct drm_i915_gem_request *req) |
48a10389 | 1102 | { |
e85b26dc | 1103 | struct intel_engine_cs *ring = req->ring; |
48a10389 BW |
1104 | int ret; |
1105 | ||
48a10389 | 1106 | /* NB: TLBs must be flushed and invalidated before a switch */ |
a84c3ae1 | 1107 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
48a10389 BW |
1108 | if (ret) |
1109 | return ret; | |
1110 | ||
5fb9de1a | 1111 | ret = intel_ring_begin(req, 6); |
48a10389 BW |
1112 | if (ret) |
1113 | return ret; | |
1114 | ||
1115 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); | |
1116 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); | |
1117 | intel_ring_emit(ring, PP_DIR_DCLV_2G); | |
1118 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); | |
1119 | intel_ring_emit(ring, get_pd_offset(ppgtt)); | |
1120 | intel_ring_emit(ring, MI_NOOP); | |
1121 | intel_ring_advance(ring); | |
1122 | ||
90252e5c BW |
1123 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
1124 | if (ring->id != RCS) { | |
a84c3ae1 | 1125 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
90252e5c BW |
1126 | if (ret) |
1127 | return ret; | |
1128 | } | |
1129 | ||
48a10389 BW |
1130 | return 0; |
1131 | } | |
1132 | ||
eeb9488e | 1133 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
e85b26dc | 1134 | struct drm_i915_gem_request *req) |
eeb9488e | 1135 | { |
e85b26dc | 1136 | struct intel_engine_cs *ring = req->ring; |
eeb9488e BW |
1137 | struct drm_device *dev = ppgtt->base.dev; |
1138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1139 | ||
48a10389 | 1140 | |
eeb9488e BW |
1141 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
1142 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); | |
1143 | ||
1144 | POSTING_READ(RING_PP_DIR_DCLV(ring)); | |
1145 | ||
1146 | return 0; | |
1147 | } | |
1148 | ||
82460d97 | 1149 | static void gen8_ppgtt_enable(struct drm_device *dev) |
eeb9488e | 1150 | { |
eeb9488e | 1151 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1152 | struct intel_engine_cs *ring; |
82460d97 | 1153 | int j; |
3e302542 | 1154 | |
eeb9488e BW |
1155 | for_each_ring(ring, dev_priv, j) { |
1156 | I915_WRITE(RING_MODE_GEN7(ring), | |
1157 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
eeb9488e | 1158 | } |
eeb9488e | 1159 | } |
6197349b | 1160 | |
82460d97 | 1161 | static void gen7_ppgtt_enable(struct drm_device *dev) |
3e302542 | 1162 | { |
50227e1c | 1163 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 1164 | struct intel_engine_cs *ring; |
b4a74e3a | 1165 | uint32_t ecochk, ecobits; |
3e302542 | 1166 | int i; |
6197349b | 1167 | |
b4a74e3a BW |
1168 | ecobits = I915_READ(GAC_ECO_BITS); |
1169 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
a65c2fcd | 1170 | |
b4a74e3a BW |
1171 | ecochk = I915_READ(GAM_ECOCHK); |
1172 | if (IS_HASWELL(dev)) { | |
1173 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
1174 | } else { | |
1175 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
1176 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
1177 | } | |
1178 | I915_WRITE(GAM_ECOCHK, ecochk); | |
a65c2fcd | 1179 | |
b4a74e3a | 1180 | for_each_ring(ring, dev_priv, i) { |
6197349b | 1181 | /* GFX_MODE is per-ring on gen7+ */ |
b4a74e3a BW |
1182 | I915_WRITE(RING_MODE_GEN7(ring), |
1183 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b | 1184 | } |
b4a74e3a | 1185 | } |
6197349b | 1186 | |
82460d97 | 1187 | static void gen6_ppgtt_enable(struct drm_device *dev) |
b4a74e3a | 1188 | { |
50227e1c | 1189 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4a74e3a | 1190 | uint32_t ecochk, gab_ctl, ecobits; |
a65c2fcd | 1191 | |
b4a74e3a BW |
1192 | ecobits = I915_READ(GAC_ECO_BITS); |
1193 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | | |
1194 | ECOBITS_PPGTT_CACHE64B); | |
6197349b | 1195 | |
b4a74e3a BW |
1196 | gab_ctl = I915_READ(GAB_CTL); |
1197 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
1198 | ||
1199 | ecochk = I915_READ(GAM_ECOCHK); | |
1200 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); | |
1201 | ||
1202 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
6197349b BW |
1203 | } |
1204 | ||
1d2a314c | 1205 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
853ba5d2 | 1206 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1207 | uint64_t start, |
1208 | uint64_t length, | |
828c7908 | 1209 | bool use_scratch) |
1d2a314c | 1210 | { |
853ba5d2 BW |
1211 | struct i915_hw_ppgtt *ppgtt = |
1212 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1213 | gen6_pte_t *pt_vaddr, scratch_pte; |
782f1495 BW |
1214 | unsigned first_entry = start >> PAGE_SHIFT; |
1215 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1216 | unsigned act_pt = first_entry / GEN6_PTES; |
1217 | unsigned first_pte = first_entry % GEN6_PTES; | |
7bddb01f | 1218 | unsigned last_pte, i; |
1d2a314c | 1219 | |
24f3a8cf | 1220 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
1d2a314c | 1221 | |
7bddb01f DV |
1222 | while (num_entries) { |
1223 | last_pte = first_pte + num_entries; | |
07749ef3 MT |
1224 | if (last_pte > GEN6_PTES) |
1225 | last_pte = GEN6_PTES; | |
7bddb01f | 1226 | |
d1c54acd | 1227 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
1d2a314c | 1228 | |
7bddb01f DV |
1229 | for (i = first_pte; i < last_pte; i++) |
1230 | pt_vaddr[i] = scratch_pte; | |
1d2a314c | 1231 | |
d1c54acd | 1232 | kunmap_px(ppgtt, pt_vaddr); |
1d2a314c | 1233 | |
7bddb01f DV |
1234 | num_entries -= last_pte - first_pte; |
1235 | first_pte = 0; | |
a15326a5 | 1236 | act_pt++; |
7bddb01f | 1237 | } |
1d2a314c DV |
1238 | } |
1239 | ||
853ba5d2 | 1240 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
def886c3 | 1241 | struct sg_table *pages, |
782f1495 | 1242 | uint64_t start, |
24f3a8cf | 1243 | enum i915_cache_level cache_level, u32 flags) |
def886c3 | 1244 | { |
853ba5d2 BW |
1245 | struct i915_hw_ppgtt *ppgtt = |
1246 | container_of(vm, struct i915_hw_ppgtt, base); | |
07749ef3 | 1247 | gen6_pte_t *pt_vaddr; |
782f1495 | 1248 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1249 | unsigned act_pt = first_entry / GEN6_PTES; |
1250 | unsigned act_pte = first_entry % GEN6_PTES; | |
6e995e23 ID |
1251 | struct sg_page_iter sg_iter; |
1252 | ||
cc79714f | 1253 | pt_vaddr = NULL; |
6e995e23 | 1254 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
cc79714f | 1255 | if (pt_vaddr == NULL) |
d1c54acd | 1256 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
6e995e23 | 1257 | |
cc79714f CW |
1258 | pt_vaddr[act_pte] = |
1259 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), | |
24f3a8cf AG |
1260 | cache_level, true, flags); |
1261 | ||
07749ef3 | 1262 | if (++act_pte == GEN6_PTES) { |
d1c54acd | 1263 | kunmap_px(ppgtt, pt_vaddr); |
cc79714f | 1264 | pt_vaddr = NULL; |
a15326a5 | 1265 | act_pt++; |
6e995e23 | 1266 | act_pte = 0; |
def886c3 | 1267 | } |
def886c3 | 1268 | } |
cc79714f | 1269 | if (pt_vaddr) |
d1c54acd | 1270 | kunmap_px(ppgtt, pt_vaddr); |
def886c3 DV |
1271 | } |
1272 | ||
4933d519 | 1273 | static void gen6_initialize_pt(struct i915_address_space *vm, |
73eeea53 | 1274 | struct i915_page_table *pt) |
4933d519 | 1275 | { |
73eeea53 | 1276 | gen6_pte_t scratch_pte; |
4933d519 MT |
1277 | |
1278 | WARN_ON(vm->scratch.addr == 0); | |
1279 | ||
73eeea53 | 1280 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); |
4933d519 | 1281 | |
73eeea53 | 1282 | fill_page_dma_32(vm->dev, &pt->base, scratch_pte); |
4933d519 MT |
1283 | } |
1284 | ||
678d96fb | 1285 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
a05d80ee | 1286 | uint64_t start_in, uint64_t length_in) |
678d96fb | 1287 | { |
4933d519 MT |
1288 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
1289 | struct drm_device *dev = vm->dev; | |
1290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
678d96fb BW |
1291 | struct i915_hw_ppgtt *ppgtt = |
1292 | container_of(vm, struct i915_hw_ppgtt, base); | |
ec565b3c | 1293 | struct i915_page_table *pt; |
a05d80ee | 1294 | uint32_t start, length, start_save, length_save; |
678d96fb | 1295 | uint32_t pde, temp; |
4933d519 MT |
1296 | int ret; |
1297 | ||
a05d80ee MK |
1298 | if (WARN_ON(start_in + length_in > ppgtt->base.total)) |
1299 | return -ENODEV; | |
1300 | ||
1301 | start = start_save = start_in; | |
1302 | length = length_save = length_in; | |
4933d519 MT |
1303 | |
1304 | bitmap_zero(new_page_tables, I915_PDES); | |
1305 | ||
1306 | /* The allocation is done in two stages so that we can bail out with | |
1307 | * minimal amount of pain. The first stage finds new page tables that | |
1308 | * need allocation. The second stage marks use ptes within the page | |
1309 | * tables. | |
1310 | */ | |
1311 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1312 | if (pt != ppgtt->scratch_pt) { | |
1313 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1314 | continue; | |
1315 | } | |
1316 | ||
1317 | /* We've already allocated a page table */ | |
1318 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); | |
1319 | ||
8a1ebd74 | 1320 | pt = alloc_pt(dev); |
4933d519 MT |
1321 | if (IS_ERR(pt)) { |
1322 | ret = PTR_ERR(pt); | |
1323 | goto unwind_out; | |
1324 | } | |
1325 | ||
1326 | gen6_initialize_pt(vm, pt); | |
1327 | ||
1328 | ppgtt->pd.page_table[pde] = pt; | |
1329 | set_bit(pde, new_page_tables); | |
72744cb1 | 1330 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
4933d519 MT |
1331 | } |
1332 | ||
1333 | start = start_save; | |
1334 | length = length_save; | |
678d96fb BW |
1335 | |
1336 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { | |
1337 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); | |
1338 | ||
1339 | bitmap_zero(tmp_bitmap, GEN6_PTES); | |
1340 | bitmap_set(tmp_bitmap, gen6_pte_index(start), | |
1341 | gen6_pte_count(start, length)); | |
1342 | ||
4933d519 MT |
1343 | if (test_and_clear_bit(pde, new_page_tables)) |
1344 | gen6_write_pde(&ppgtt->pd, pde, pt); | |
1345 | ||
72744cb1 MT |
1346 | trace_i915_page_table_entry_map(vm, pde, pt, |
1347 | gen6_pte_index(start), | |
1348 | gen6_pte_count(start, length), | |
1349 | GEN6_PTES); | |
4933d519 | 1350 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
678d96fb BW |
1351 | GEN6_PTES); |
1352 | } | |
1353 | ||
4933d519 MT |
1354 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
1355 | ||
1356 | /* Make sure write is complete before other code can use this page | |
1357 | * table. Also require for WC mapped PTEs */ | |
1358 | readl(dev_priv->gtt.gsm); | |
1359 | ||
563222a7 | 1360 | mark_tlbs_dirty(ppgtt); |
678d96fb | 1361 | return 0; |
4933d519 MT |
1362 | |
1363 | unwind_out: | |
1364 | for_each_set_bit(pde, new_page_tables, I915_PDES) { | |
ec565b3c | 1365 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
4933d519 MT |
1366 | |
1367 | ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; | |
a08e111a | 1368 | free_pt(vm->dev, pt); |
4933d519 MT |
1369 | } |
1370 | ||
1371 | mark_tlbs_dirty(ppgtt); | |
1372 | return ret; | |
678d96fb BW |
1373 | } |
1374 | ||
061dd493 | 1375 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
a00d825d | 1376 | { |
061dd493 DV |
1377 | struct i915_hw_ppgtt *ppgtt = |
1378 | container_of(vm, struct i915_hw_ppgtt, base); | |
09942c65 MT |
1379 | struct i915_page_table *pt; |
1380 | uint32_t pde; | |
4933d519 | 1381 | |
061dd493 DV |
1382 | |
1383 | drm_mm_remove_node(&ppgtt->node); | |
1384 | ||
09942c65 | 1385 | gen6_for_all_pdes(pt, ppgtt, pde) { |
4933d519 | 1386 | if (pt != ppgtt->scratch_pt) |
a08e111a | 1387 | free_pt(ppgtt->base.dev, pt); |
4933d519 | 1388 | } |
06fda602 | 1389 | |
a08e111a | 1390 | free_pt(ppgtt->base.dev, ppgtt->scratch_pt); |
3440d265 DV |
1391 | } |
1392 | ||
b146520f | 1393 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
3440d265 | 1394 | { |
853ba5d2 | 1395 | struct drm_device *dev = ppgtt->base.dev; |
1d2a314c | 1396 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3cc1995 | 1397 | bool retried = false; |
b146520f | 1398 | int ret; |
1d2a314c | 1399 | |
c8d4c0d6 BW |
1400 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
1401 | * allocator works in address space sizes, so it's multiplied by page | |
1402 | * size. We allocate at the top of the GTT to avoid fragmentation. | |
1403 | */ | |
1404 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); | |
8a1ebd74 | 1405 | ppgtt->scratch_pt = alloc_pt(ppgtt->base.dev); |
4933d519 MT |
1406 | if (IS_ERR(ppgtt->scratch_pt)) |
1407 | return PTR_ERR(ppgtt->scratch_pt); | |
1408 | ||
1409 | gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); | |
1410 | ||
e3cc1995 | 1411 | alloc: |
c8d4c0d6 BW |
1412 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
1413 | &ppgtt->node, GEN6_PD_SIZE, | |
1414 | GEN6_PD_ALIGN, 0, | |
1415 | 0, dev_priv->gtt.base.total, | |
3e8b5ae9 | 1416 | DRM_MM_TOPDOWN); |
e3cc1995 BW |
1417 | if (ret == -ENOSPC && !retried) { |
1418 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, | |
1419 | GEN6_PD_SIZE, GEN6_PD_ALIGN, | |
d23db88c CW |
1420 | I915_CACHE_NONE, |
1421 | 0, dev_priv->gtt.base.total, | |
1422 | 0); | |
e3cc1995 | 1423 | if (ret) |
678d96fb | 1424 | goto err_out; |
e3cc1995 BW |
1425 | |
1426 | retried = true; | |
1427 | goto alloc; | |
1428 | } | |
c8d4c0d6 | 1429 | |
c8c26622 | 1430 | if (ret) |
678d96fb BW |
1431 | goto err_out; |
1432 | ||
c8c26622 | 1433 | |
c8d4c0d6 BW |
1434 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
1435 | DRM_DEBUG("Forced to use aperture for PDEs\n"); | |
1d2a314c | 1436 | |
c8c26622 | 1437 | return 0; |
678d96fb BW |
1438 | |
1439 | err_out: | |
a08e111a | 1440 | free_pt(ppgtt->base.dev, ppgtt->scratch_pt); |
678d96fb | 1441 | return ret; |
b146520f BW |
1442 | } |
1443 | ||
b146520f BW |
1444 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
1445 | { | |
2f2cf682 | 1446 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
4933d519 | 1447 | } |
06dc68d6 | 1448 | |
4933d519 MT |
1449 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
1450 | uint64_t start, uint64_t length) | |
1451 | { | |
ec565b3c | 1452 | struct i915_page_table *unused; |
4933d519 | 1453 | uint32_t pde, temp; |
1d2a314c | 1454 | |
4933d519 MT |
1455 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) |
1456 | ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; | |
b146520f BW |
1457 | } |
1458 | ||
5c5f6457 | 1459 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
b146520f BW |
1460 | { |
1461 | struct drm_device *dev = ppgtt->base.dev; | |
1462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1463 | int ret; | |
1464 | ||
1465 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; | |
1466 | if (IS_GEN6(dev)) { | |
b146520f BW |
1467 | ppgtt->switch_mm = gen6_mm_switch; |
1468 | } else if (IS_HASWELL(dev)) { | |
b146520f BW |
1469 | ppgtt->switch_mm = hsw_mm_switch; |
1470 | } else if (IS_GEN7(dev)) { | |
b146520f BW |
1471 | ppgtt->switch_mm = gen7_mm_switch; |
1472 | } else | |
1473 | BUG(); | |
1474 | ||
71ba2d64 YZ |
1475 | if (intel_vgpu_active(dev)) |
1476 | ppgtt->switch_mm = vgpu_mm_switch; | |
1477 | ||
b146520f BW |
1478 | ret = gen6_ppgtt_alloc(ppgtt); |
1479 | if (ret) | |
1480 | return ret; | |
1481 | ||
5c5f6457 | 1482 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
b146520f BW |
1483 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
1484 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; | |
777dc5bb DV |
1485 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
1486 | ppgtt->base.bind_vma = ppgtt_bind_vma; | |
b146520f | 1487 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
b146520f | 1488 | ppgtt->base.start = 0; |
09942c65 | 1489 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
87d60b63 | 1490 | ppgtt->debug_dump = gen6_dump_ppgtt; |
1d2a314c | 1491 | |
44159ddb | 1492 | ppgtt->pd.base.ggtt_offset = |
07749ef3 | 1493 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
1d2a314c | 1494 | |
678d96fb | 1495 | ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + |
44159ddb | 1496 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
678d96fb | 1497 | |
5c5f6457 | 1498 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
1d2a314c | 1499 | |
678d96fb BW |
1500 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
1501 | ||
440fd528 | 1502 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
b146520f BW |
1503 | ppgtt->node.size >> 20, |
1504 | ppgtt->node.start / PAGE_SIZE); | |
3440d265 | 1505 | |
fa76da34 | 1506 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
44159ddb | 1507 | ppgtt->pd.base.ggtt_offset << 10); |
fa76da34 | 1508 | |
b146520f | 1509 | return 0; |
3440d265 DV |
1510 | } |
1511 | ||
5c5f6457 | 1512 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
3440d265 DV |
1513 | { |
1514 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3440d265 | 1515 | |
853ba5d2 | 1516 | ppgtt->base.dev = dev; |
8407bb91 | 1517 | ppgtt->base.scratch = dev_priv->gtt.base.scratch; |
3440d265 | 1518 | |
3ed124b2 | 1519 | if (INTEL_INFO(dev)->gen < 8) |
5c5f6457 | 1520 | return gen6_ppgtt_init(ppgtt); |
3ed124b2 | 1521 | else |
d7b2633d | 1522 | return gen8_ppgtt_init(ppgtt); |
fa76da34 DV |
1523 | } |
1524 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) | |
1525 | { | |
1526 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1527 | int ret = 0; | |
3ed124b2 | 1528 | |
5c5f6457 | 1529 | ret = __hw_ppgtt_init(dev, ppgtt); |
fa76da34 | 1530 | if (ret == 0) { |
c7c48dfd | 1531 | kref_init(&ppgtt->ref); |
93bd8649 BW |
1532 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
1533 | ppgtt->base.total); | |
7e0d96bc | 1534 | i915_init_vm(dev_priv, &ppgtt->base); |
93bd8649 | 1535 | } |
1d2a314c DV |
1536 | |
1537 | return ret; | |
1538 | } | |
1539 | ||
82460d97 DV |
1540 | int i915_ppgtt_init_hw(struct drm_device *dev) |
1541 | { | |
671b5013 TD |
1542 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
1543 | * and the PDPs are contained within the context itself. We don't | |
1544 | * need to do anything here. */ | |
1545 | if (i915.enable_execlists) | |
1546 | return 0; | |
1547 | ||
82460d97 DV |
1548 | if (!USES_PPGTT(dev)) |
1549 | return 0; | |
1550 | ||
1551 | if (IS_GEN6(dev)) | |
1552 | gen6_ppgtt_enable(dev); | |
1553 | else if (IS_GEN7(dev)) | |
1554 | gen7_ppgtt_enable(dev); | |
1555 | else if (INTEL_INFO(dev)->gen >= 8) | |
1556 | gen8_ppgtt_enable(dev); | |
1557 | else | |
5f77eeb0 | 1558 | MISSING_CASE(INTEL_INFO(dev)->gen); |
82460d97 | 1559 | |
4ad2fd88 JH |
1560 | return 0; |
1561 | } | |
1d2a314c | 1562 | |
b3dd6b96 | 1563 | int i915_ppgtt_init_ring(struct drm_i915_gem_request *req) |
4ad2fd88 | 1564 | { |
b3dd6b96 | 1565 | struct drm_i915_private *dev_priv = req->ring->dev->dev_private; |
4ad2fd88 JH |
1566 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
1567 | ||
1568 | if (i915.enable_execlists) | |
1569 | return 0; | |
1570 | ||
1571 | if (!ppgtt) | |
1572 | return 0; | |
1573 | ||
e85b26dc | 1574 | return ppgtt->switch_mm(ppgtt, req); |
1d2a314c | 1575 | } |
4ad2fd88 | 1576 | |
4d884705 DV |
1577 | struct i915_hw_ppgtt * |
1578 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) | |
1579 | { | |
1580 | struct i915_hw_ppgtt *ppgtt; | |
1581 | int ret; | |
1582 | ||
1583 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
1584 | if (!ppgtt) | |
1585 | return ERR_PTR(-ENOMEM); | |
1586 | ||
1587 | ret = i915_ppgtt_init(dev, ppgtt); | |
1588 | if (ret) { | |
1589 | kfree(ppgtt); | |
1590 | return ERR_PTR(ret); | |
1591 | } | |
1592 | ||
1593 | ppgtt->file_priv = fpriv; | |
1594 | ||
198c974d DCS |
1595 | trace_i915_ppgtt_create(&ppgtt->base); |
1596 | ||
4d884705 DV |
1597 | return ppgtt; |
1598 | } | |
1599 | ||
ee960be7 DV |
1600 | void i915_ppgtt_release(struct kref *kref) |
1601 | { | |
1602 | struct i915_hw_ppgtt *ppgtt = | |
1603 | container_of(kref, struct i915_hw_ppgtt, ref); | |
1604 | ||
198c974d DCS |
1605 | trace_i915_ppgtt_release(&ppgtt->base); |
1606 | ||
ee960be7 DV |
1607 | /* vmas should already be unbound */ |
1608 | WARN_ON(!list_empty(&ppgtt->base.active_list)); | |
1609 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); | |
1610 | ||
19dd120c DV |
1611 | list_del(&ppgtt->base.global_link); |
1612 | drm_mm_takedown(&ppgtt->base.mm); | |
1613 | ||
ee960be7 DV |
1614 | ppgtt->base.cleanup(&ppgtt->base); |
1615 | kfree(ppgtt); | |
1616 | } | |
1d2a314c | 1617 | |
a81cc00c BW |
1618 | extern int intel_iommu_gfx_mapped; |
1619 | /* Certain Gen5 chipsets require require idling the GPU before | |
1620 | * unmapping anything from the GTT when VT-d is enabled. | |
1621 | */ | |
2c642b07 | 1622 | static bool needs_idle_maps(struct drm_device *dev) |
a81cc00c BW |
1623 | { |
1624 | #ifdef CONFIG_INTEL_IOMMU | |
1625 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
1626 | * was loaded first. | |
1627 | */ | |
1628 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
1629 | return true; | |
1630 | #endif | |
1631 | return false; | |
1632 | } | |
1633 | ||
5c042287 BW |
1634 | static bool do_idling(struct drm_i915_private *dev_priv) |
1635 | { | |
1636 | bool ret = dev_priv->mm.interruptible; | |
1637 | ||
a81cc00c | 1638 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 1639 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 1640 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
1641 | DRM_ERROR("Couldn't idle GPU\n"); |
1642 | /* Wait a bit, in hopes it avoids the hang */ | |
1643 | udelay(10); | |
1644 | } | |
1645 | } | |
1646 | ||
1647 | return ret; | |
1648 | } | |
1649 | ||
1650 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
1651 | { | |
a81cc00c | 1652 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
1653 | dev_priv->mm.interruptible = interruptible; |
1654 | } | |
1655 | ||
828c7908 BW |
1656 | void i915_check_and_clear_faults(struct drm_device *dev) |
1657 | { | |
1658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1659 | struct intel_engine_cs *ring; |
828c7908 BW |
1660 | int i; |
1661 | ||
1662 | if (INTEL_INFO(dev)->gen < 6) | |
1663 | return; | |
1664 | ||
1665 | for_each_ring(ring, dev_priv, i) { | |
1666 | u32 fault_reg; | |
1667 | fault_reg = I915_READ(RING_FAULT_REG(ring)); | |
1668 | if (fault_reg & RING_FAULT_VALID) { | |
1669 | DRM_DEBUG_DRIVER("Unexpected fault\n" | |
59a5d290 | 1670 | "\tAddr: 0x%08lx\n" |
828c7908 BW |
1671 | "\tAddress space: %s\n" |
1672 | "\tSource ID: %d\n" | |
1673 | "\tType: %d\n", | |
1674 | fault_reg & PAGE_MASK, | |
1675 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", | |
1676 | RING_FAULT_SRCID(fault_reg), | |
1677 | RING_FAULT_FAULT_TYPE(fault_reg)); | |
1678 | I915_WRITE(RING_FAULT_REG(ring), | |
1679 | fault_reg & ~RING_FAULT_VALID); | |
1680 | } | |
1681 | } | |
1682 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); | |
1683 | } | |
1684 | ||
91e56499 CW |
1685 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
1686 | { | |
1687 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { | |
1688 | intel_gtt_chipset_flush(); | |
1689 | } else { | |
1690 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1691 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
1692 | } | |
1693 | } | |
1694 | ||
828c7908 BW |
1695 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
1696 | { | |
1697 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1698 | ||
1699 | /* Don't bother messing with faults pre GEN6 as we have little | |
1700 | * documentation supporting that it's a good idea. | |
1701 | */ | |
1702 | if (INTEL_INFO(dev)->gen < 6) | |
1703 | return; | |
1704 | ||
1705 | i915_check_and_clear_faults(dev); | |
1706 | ||
1707 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
782f1495 BW |
1708 | dev_priv->gtt.base.start, |
1709 | dev_priv->gtt.base.total, | |
e568af1c | 1710 | true); |
91e56499 CW |
1711 | |
1712 | i915_ggtt_flush(dev_priv); | |
828c7908 BW |
1713 | } |
1714 | ||
74163907 | 1715 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 1716 | { |
9da3da66 | 1717 | if (obj->has_dma_mapping) |
74163907 | 1718 | return 0; |
9da3da66 CW |
1719 | |
1720 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
1721 | obj->pages->sgl, obj->pages->nents, | |
1722 | PCI_DMA_BIDIRECTIONAL)) | |
1723 | return -ENOSPC; | |
1724 | ||
1725 | return 0; | |
7c2e6fdf DV |
1726 | } |
1727 | ||
2c642b07 | 1728 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
94ec8f61 BW |
1729 | { |
1730 | #ifdef writeq | |
1731 | writeq(pte, addr); | |
1732 | #else | |
1733 | iowrite32((u32)pte, addr); | |
1734 | iowrite32(pte >> 32, addr + 4); | |
1735 | #endif | |
1736 | } | |
1737 | ||
1738 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, | |
1739 | struct sg_table *st, | |
782f1495 | 1740 | uint64_t start, |
24f3a8cf | 1741 | enum i915_cache_level level, u32 unused) |
94ec8f61 BW |
1742 | { |
1743 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 | 1744 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1745 | gen8_pte_t __iomem *gtt_entries = |
1746 | (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1747 | int i = 0; |
1748 | struct sg_page_iter sg_iter; | |
57007df7 | 1749 | dma_addr_t addr = 0; /* shut up gcc */ |
94ec8f61 BW |
1750 | |
1751 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { | |
1752 | addr = sg_dma_address(sg_iter.sg) + | |
1753 | (sg_iter.sg_pgoffset << PAGE_SHIFT); | |
1754 | gen8_set_pte(>t_entries[i], | |
1755 | gen8_pte_encode(addr, level, true)); | |
1756 | i++; | |
1757 | } | |
1758 | ||
1759 | /* | |
1760 | * XXX: This serves as a posting read to make sure that the PTE has | |
1761 | * actually been updated. There is some concern that even though | |
1762 | * registers and PTEs are within the same BAR that they are potentially | |
1763 | * of NUMA access patterns. Therefore, even with the way we assume | |
1764 | * hardware should work, we must keep this posting read for paranoia. | |
1765 | */ | |
1766 | if (i != 0) | |
1767 | WARN_ON(readq(>t_entries[i-1]) | |
1768 | != gen8_pte_encode(addr, level, true)); | |
1769 | ||
94ec8f61 BW |
1770 | /* This next bit makes the above posting read even more important. We |
1771 | * want to flush the TLBs only after we're certain all the PTE updates | |
1772 | * have finished. | |
1773 | */ | |
1774 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1775 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
94ec8f61 BW |
1776 | } |
1777 | ||
e76e9aeb BW |
1778 | /* |
1779 | * Binds an object into the global gtt with the specified cache level. The object | |
1780 | * will be accessible to the GPU via commands whose operands reference offsets | |
1781 | * within the global GTT as well as accessible by the GPU through the GMADR | |
1782 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
1783 | */ | |
853ba5d2 | 1784 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
7faf1ab2 | 1785 | struct sg_table *st, |
782f1495 | 1786 | uint64_t start, |
24f3a8cf | 1787 | enum i915_cache_level level, u32 flags) |
e76e9aeb | 1788 | { |
853ba5d2 | 1789 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 | 1790 | unsigned first_entry = start >> PAGE_SHIFT; |
07749ef3 MT |
1791 | gen6_pte_t __iomem *gtt_entries = |
1792 | (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
1793 | int i = 0; |
1794 | struct sg_page_iter sg_iter; | |
57007df7 | 1795 | dma_addr_t addr = 0; |
e76e9aeb | 1796 | |
6e995e23 | 1797 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 1798 | addr = sg_page_iter_dma_address(&sg_iter); |
24f3a8cf | 1799 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
6e995e23 | 1800 | i++; |
e76e9aeb BW |
1801 | } |
1802 | ||
e76e9aeb BW |
1803 | /* XXX: This serves as a posting read to make sure that the PTE has |
1804 | * actually been updated. There is some concern that even though | |
1805 | * registers and PTEs are within the same BAR that they are potentially | |
1806 | * of NUMA access patterns. Therefore, even with the way we assume | |
1807 | * hardware should work, we must keep this posting read for paranoia. | |
1808 | */ | |
57007df7 PM |
1809 | if (i != 0) { |
1810 | unsigned long gtt = readl(>t_entries[i-1]); | |
1811 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); | |
1812 | } | |
0f9b91c7 BW |
1813 | |
1814 | /* This next bit makes the above posting read even more important. We | |
1815 | * want to flush the TLBs only after we're certain all the PTE updates | |
1816 | * have finished. | |
1817 | */ | |
1818 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
1819 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
1820 | } |
1821 | ||
94ec8f61 | 1822 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1823 | uint64_t start, |
1824 | uint64_t length, | |
94ec8f61 BW |
1825 | bool use_scratch) |
1826 | { | |
1827 | struct drm_i915_private *dev_priv = vm->dev->dev_private; | |
782f1495 BW |
1828 | unsigned first_entry = start >> PAGE_SHIFT; |
1829 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1830 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
1831 | (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
94ec8f61 BW |
1832 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
1833 | int i; | |
1834 | ||
1835 | if (WARN(num_entries > max_entries, | |
1836 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1837 | first_entry, num_entries, max_entries)) | |
1838 | num_entries = max_entries; | |
1839 | ||
1840 | scratch_pte = gen8_pte_encode(vm->scratch.addr, | |
1841 | I915_CACHE_LLC, | |
1842 | use_scratch); | |
1843 | for (i = 0; i < num_entries; i++) | |
1844 | gen8_set_pte(>t_base[i], scratch_pte); | |
1845 | readl(gtt_base); | |
1846 | } | |
1847 | ||
853ba5d2 | 1848 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1849 | uint64_t start, |
1850 | uint64_t length, | |
828c7908 | 1851 | bool use_scratch) |
7faf1ab2 | 1852 | { |
853ba5d2 | 1853 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
782f1495 BW |
1854 | unsigned first_entry = start >> PAGE_SHIFT; |
1855 | unsigned num_entries = length >> PAGE_SHIFT; | |
07749ef3 MT |
1856 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
1857 | (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 1858 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
1859 | int i; |
1860 | ||
1861 | if (WARN(num_entries > max_entries, | |
1862 | "First entry = %d; Num entries = %d (max=%d)\n", | |
1863 | first_entry, num_entries, max_entries)) | |
1864 | num_entries = max_entries; | |
1865 | ||
24f3a8cf | 1866 | scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); |
828c7908 | 1867 | |
7faf1ab2 DV |
1868 | for (i = 0; i < num_entries; i++) |
1869 | iowrite32(scratch_pte, >t_base[i]); | |
1870 | readl(gtt_base); | |
1871 | } | |
1872 | ||
d369d2d9 DV |
1873 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
1874 | struct sg_table *pages, | |
1875 | uint64_t start, | |
1876 | enum i915_cache_level cache_level, u32 unused) | |
7faf1ab2 DV |
1877 | { |
1878 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
1879 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
1880 | ||
d369d2d9 | 1881 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
0875546c | 1882 | |
7faf1ab2 DV |
1883 | } |
1884 | ||
853ba5d2 | 1885 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
782f1495 BW |
1886 | uint64_t start, |
1887 | uint64_t length, | |
828c7908 | 1888 | bool unused) |
7faf1ab2 | 1889 | { |
782f1495 BW |
1890 | unsigned first_entry = start >> PAGE_SHIFT; |
1891 | unsigned num_entries = length >> PAGE_SHIFT; | |
7faf1ab2 DV |
1892 | intel_gtt_clear_range(first_entry, num_entries); |
1893 | } | |
1894 | ||
70b9f6f8 DV |
1895 | static int ggtt_bind_vma(struct i915_vma *vma, |
1896 | enum i915_cache_level cache_level, | |
1897 | u32 flags) | |
d5bd1449 | 1898 | { |
6f65e29a | 1899 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1900 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1901 | struct drm_i915_gem_object *obj = vma->obj; |
ec7adb6e | 1902 | struct sg_table *pages = obj->pages; |
f329f5f6 | 1903 | u32 pte_flags = 0; |
70b9f6f8 DV |
1904 | int ret; |
1905 | ||
1906 | ret = i915_get_ggtt_vma_pages(vma); | |
1907 | if (ret) | |
1908 | return ret; | |
1909 | pages = vma->ggtt_view.pages; | |
7faf1ab2 | 1910 | |
24f3a8cf AG |
1911 | /* Currently applicable only to VLV */ |
1912 | if (obj->gt_ro) | |
f329f5f6 | 1913 | pte_flags |= PTE_READ_ONLY; |
24f3a8cf | 1914 | |
ec7adb6e | 1915 | |
6f65e29a | 1916 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { |
0875546c DV |
1917 | vma->vm->insert_entries(vma->vm, pages, |
1918 | vma->node.start, | |
1919 | cache_level, pte_flags); | |
6f65e29a | 1920 | } |
d5bd1449 | 1921 | |
0875546c | 1922 | if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) { |
6f65e29a | 1923 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
ec7adb6e | 1924 | appgtt->base.insert_entries(&appgtt->base, pages, |
782f1495 | 1925 | vma->node.start, |
f329f5f6 | 1926 | cache_level, pte_flags); |
6f65e29a | 1927 | } |
70b9f6f8 DV |
1928 | |
1929 | return 0; | |
d5bd1449 CW |
1930 | } |
1931 | ||
6f65e29a | 1932 | static void ggtt_unbind_vma(struct i915_vma *vma) |
74163907 | 1933 | { |
6f65e29a | 1934 | struct drm_device *dev = vma->vm->dev; |
7faf1ab2 | 1935 | struct drm_i915_private *dev_priv = dev->dev_private; |
6f65e29a | 1936 | struct drm_i915_gem_object *obj = vma->obj; |
06615ee5 JL |
1937 | const uint64_t size = min_t(uint64_t, |
1938 | obj->base.size, | |
1939 | vma->node.size); | |
6f65e29a | 1940 | |
aff43766 | 1941 | if (vma->bound & GLOBAL_BIND) { |
782f1495 BW |
1942 | vma->vm->clear_range(vma->vm, |
1943 | vma->node.start, | |
06615ee5 | 1944 | size, |
6f65e29a | 1945 | true); |
6f65e29a | 1946 | } |
74898d7e | 1947 | |
0875546c | 1948 | if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) { |
6f65e29a | 1949 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
06615ee5 | 1950 | |
6f65e29a | 1951 | appgtt->base.clear_range(&appgtt->base, |
782f1495 | 1952 | vma->node.start, |
06615ee5 | 1953 | size, |
6f65e29a | 1954 | true); |
6f65e29a | 1955 | } |
74163907 DV |
1956 | } |
1957 | ||
1958 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 1959 | { |
5c042287 BW |
1960 | struct drm_device *dev = obj->base.dev; |
1961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1962 | bool interruptible; | |
1963 | ||
1964 | interruptible = do_idling(dev_priv); | |
1965 | ||
9da3da66 CW |
1966 | if (!obj->has_dma_mapping) |
1967 | dma_unmap_sg(&dev->pdev->dev, | |
1968 | obj->pages->sgl, obj->pages->nents, | |
1969 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
1970 | |
1971 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 1972 | } |
644ec02b | 1973 | |
42d6ab48 CW |
1974 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
1975 | unsigned long color, | |
440fd528 TR |
1976 | u64 *start, |
1977 | u64 *end) | |
42d6ab48 CW |
1978 | { |
1979 | if (node->color != color) | |
1980 | *start += 4096; | |
1981 | ||
1982 | if (!list_empty(&node->node_list)) { | |
1983 | node = list_entry(node->node_list.next, | |
1984 | struct drm_mm_node, | |
1985 | node_list); | |
1986 | if (node->allocated && node->color != color) | |
1987 | *end -= 4096; | |
1988 | } | |
1989 | } | |
fbe5d36e | 1990 | |
f548c0e9 DV |
1991 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
1992 | unsigned long start, | |
1993 | unsigned long mappable_end, | |
1994 | unsigned long end) | |
644ec02b | 1995 | { |
e78891ca BW |
1996 | /* Let GEM Manage all of the aperture. |
1997 | * | |
1998 | * However, leave one page at the end still bound to the scratch page. | |
1999 | * There are a number of places where the hardware apparently prefetches | |
2000 | * past the end of the object, and we've seen multiple hangs with the | |
2001 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
2002 | * aperture. One page should be enough to keep any prefetching inside | |
2003 | * of the aperture. | |
2004 | */ | |
40d74980 BW |
2005 | struct drm_i915_private *dev_priv = dev->dev_private; |
2006 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
ed2f3452 CW |
2007 | struct drm_mm_node *entry; |
2008 | struct drm_i915_gem_object *obj; | |
2009 | unsigned long hole_start, hole_end; | |
fa76da34 | 2010 | int ret; |
644ec02b | 2011 | |
35451cb6 BW |
2012 | BUG_ON(mappable_end > end); |
2013 | ||
ed2f3452 | 2014 | /* Subtract the guard page ... */ |
40d74980 | 2015 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
5dda8fa3 YZ |
2016 | |
2017 | dev_priv->gtt.base.start = start; | |
2018 | dev_priv->gtt.base.total = end - start; | |
2019 | ||
2020 | if (intel_vgpu_active(dev)) { | |
2021 | ret = intel_vgt_balloon(dev); | |
2022 | if (ret) | |
2023 | return ret; | |
2024 | } | |
2025 | ||
42d6ab48 | 2026 | if (!HAS_LLC(dev)) |
93bd8649 | 2027 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
644ec02b | 2028 | |
ed2f3452 | 2029 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 2030 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
40d74980 | 2031 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
fa76da34 | 2032 | |
edd41a87 | 2033 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
2034 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
2035 | ||
2036 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
40d74980 | 2037 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
6c5566a8 DV |
2038 | if (ret) { |
2039 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); | |
2040 | return ret; | |
2041 | } | |
aff43766 | 2042 | vma->bound |= GLOBAL_BIND; |
ed2f3452 CW |
2043 | } |
2044 | ||
ed2f3452 | 2045 | /* Clear any non-preallocated blocks */ |
40d74980 | 2046 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
ed2f3452 CW |
2047 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
2048 | hole_start, hole_end); | |
782f1495 BW |
2049 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
2050 | hole_end - hole_start, true); | |
ed2f3452 CW |
2051 | } |
2052 | ||
2053 | /* And finally clear the reserved guard page */ | |
782f1495 | 2054 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
6c5566a8 | 2055 | |
fa76da34 DV |
2056 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
2057 | struct i915_hw_ppgtt *ppgtt; | |
2058 | ||
2059 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
2060 | if (!ppgtt) | |
2061 | return -ENOMEM; | |
2062 | ||
5c5f6457 DV |
2063 | ret = __hw_ppgtt_init(dev, ppgtt); |
2064 | if (ret) { | |
2065 | ppgtt->base.cleanup(&ppgtt->base); | |
2066 | kfree(ppgtt); | |
2067 | return ret; | |
2068 | } | |
2069 | ||
2070 | if (ppgtt->base.allocate_va_range) | |
2071 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, | |
2072 | ppgtt->base.total); | |
4933d519 | 2073 | if (ret) { |
061dd493 | 2074 | ppgtt->base.cleanup(&ppgtt->base); |
4933d519 | 2075 | kfree(ppgtt); |
fa76da34 | 2076 | return ret; |
4933d519 | 2077 | } |
fa76da34 | 2078 | |
5c5f6457 DV |
2079 | ppgtt->base.clear_range(&ppgtt->base, |
2080 | ppgtt->base.start, | |
2081 | ppgtt->base.total, | |
2082 | true); | |
2083 | ||
fa76da34 DV |
2084 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
2085 | } | |
2086 | ||
6c5566a8 | 2087 | return 0; |
e76e9aeb BW |
2088 | } |
2089 | ||
d7e5008f BW |
2090 | void i915_gem_init_global_gtt(struct drm_device *dev) |
2091 | { | |
2092 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c44ef60e | 2093 | u64 gtt_size, mappable_size; |
d7e5008f | 2094 | |
853ba5d2 | 2095 | gtt_size = dev_priv->gtt.base.total; |
93d18799 | 2096 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f | 2097 | |
e78891ca | 2098 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
2099 | } |
2100 | ||
90d0a0e8 DV |
2101 | void i915_global_gtt_cleanup(struct drm_device *dev) |
2102 | { | |
2103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2104 | struct i915_address_space *vm = &dev_priv->gtt.base; | |
2105 | ||
70e32544 DV |
2106 | if (dev_priv->mm.aliasing_ppgtt) { |
2107 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2108 | ||
2109 | ppgtt->base.cleanup(&ppgtt->base); | |
2110 | } | |
2111 | ||
90d0a0e8 | 2112 | if (drm_mm_initialized(&vm->mm)) { |
5dda8fa3 YZ |
2113 | if (intel_vgpu_active(dev)) |
2114 | intel_vgt_deballoon(); | |
2115 | ||
90d0a0e8 DV |
2116 | drm_mm_takedown(&vm->mm); |
2117 | list_del(&vm->global_link); | |
2118 | } | |
2119 | ||
2120 | vm->cleanup(vm); | |
2121 | } | |
70e32544 | 2122 | |
e76e9aeb BW |
2123 | static int setup_scratch_page(struct drm_device *dev) |
2124 | { | |
2125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2126 | struct page *page; | |
2127 | dma_addr_t dma_addr; | |
2128 | ||
2129 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
2130 | if (page == NULL) | |
2131 | return -ENOMEM; | |
e76e9aeb BW |
2132 | set_pages_uc(page, 1); |
2133 | ||
2134 | #ifdef CONFIG_INTEL_IOMMU | |
2135 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
2136 | PCI_DMA_BIDIRECTIONAL); | |
ea3f5d26 MK |
2137 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) { |
2138 | __free_page(page); | |
e76e9aeb | 2139 | return -EINVAL; |
ea3f5d26 | 2140 | } |
e76e9aeb BW |
2141 | #else |
2142 | dma_addr = page_to_phys(page); | |
2143 | #endif | |
853ba5d2 BW |
2144 | dev_priv->gtt.base.scratch.page = page; |
2145 | dev_priv->gtt.base.scratch.addr = dma_addr; | |
e76e9aeb BW |
2146 | |
2147 | return 0; | |
2148 | } | |
2149 | ||
2150 | static void teardown_scratch_page(struct drm_device *dev) | |
2151 | { | |
2152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
853ba5d2 BW |
2153 | struct page *page = dev_priv->gtt.base.scratch.page; |
2154 | ||
2155 | set_pages_wb(page, 1); | |
2156 | pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, | |
e76e9aeb | 2157 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
853ba5d2 | 2158 | __free_page(page); |
e76e9aeb BW |
2159 | } |
2160 | ||
2c642b07 | 2161 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2162 | { |
2163 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
2164 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
2165 | return snb_gmch_ctl << 20; | |
2166 | } | |
2167 | ||
2c642b07 | 2168 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2169 | { |
2170 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; | |
2171 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; | |
2172 | if (bdw_gmch_ctl) | |
2173 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; | |
562d55d9 BW |
2174 | |
2175 | #ifdef CONFIG_X86_32 | |
2176 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ | |
2177 | if (bdw_gmch_ctl > 4) | |
2178 | bdw_gmch_ctl = 4; | |
2179 | #endif | |
2180 | ||
9459d252 BW |
2181 | return bdw_gmch_ctl << 20; |
2182 | } | |
2183 | ||
2c642b07 | 2184 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
d7f25f23 DL |
2185 | { |
2186 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; | |
2187 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; | |
2188 | ||
2189 | if (gmch_ctrl) | |
2190 | return 1 << (20 + gmch_ctrl); | |
2191 | ||
2192 | return 0; | |
2193 | } | |
2194 | ||
2c642b07 | 2195 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
2196 | { |
2197 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
2198 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
2199 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
2200 | } | |
2201 | ||
2c642b07 | 2202 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
9459d252 BW |
2203 | { |
2204 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2205 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2206 | return bdw_gmch_ctl << 25; /* 32 MB units */ | |
2207 | } | |
2208 | ||
d7f25f23 DL |
2209 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
2210 | { | |
2211 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; | |
2212 | gmch_ctrl &= SNB_GMCH_GMS_MASK; | |
2213 | ||
2214 | /* | |
2215 | * 0x0 to 0x10: 32MB increments starting at 0MB | |
2216 | * 0x11 to 0x16: 4MB increments starting at 8MB | |
2217 | * 0x17 to 0x1d: 4MB increments start at 36MB | |
2218 | */ | |
2219 | if (gmch_ctrl < 0x11) | |
2220 | return gmch_ctrl << 25; | |
2221 | else if (gmch_ctrl < 0x17) | |
2222 | return (gmch_ctrl - 0x11 + 2) << 22; | |
2223 | else | |
2224 | return (gmch_ctrl - 0x17 + 9) << 22; | |
2225 | } | |
2226 | ||
66375014 DL |
2227 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
2228 | { | |
2229 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; | |
2230 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; | |
2231 | ||
2232 | if (gen9_gmch_ctl < 0xf0) | |
2233 | return gen9_gmch_ctl << 25; /* 32 MB units */ | |
2234 | else | |
2235 | /* 4MB increments starting at 0xf0 for 4MB */ | |
2236 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; | |
2237 | } | |
2238 | ||
63340133 BW |
2239 | static int ggtt_probe_common(struct drm_device *dev, |
2240 | size_t gtt_size) | |
2241 | { | |
2242 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21c34607 | 2243 | phys_addr_t gtt_phys_addr; |
63340133 BW |
2244 | int ret; |
2245 | ||
2246 | /* For Modern GENs the PTEs and register space are split in the BAR */ | |
21c34607 | 2247 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
63340133 BW |
2248 | (pci_resource_len(dev->pdev, 0) / 2); |
2249 | ||
2a073f89 ID |
2250 | /* |
2251 | * On BXT writes larger than 64 bit to the GTT pagetable range will be | |
2252 | * dropped. For WC mappings in general we have 64 byte burst writes | |
2253 | * when the WC buffer is flushed, so we can't use it, but have to | |
2254 | * resort to an uncached mapping. The WC issue is easily caught by the | |
2255 | * readback check when writing GTT PTE entries. | |
2256 | */ | |
2257 | if (IS_BROXTON(dev)) | |
2258 | dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size); | |
2259 | else | |
2260 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); | |
63340133 BW |
2261 | if (!dev_priv->gtt.gsm) { |
2262 | DRM_ERROR("Failed to map the gtt page table\n"); | |
2263 | return -ENOMEM; | |
2264 | } | |
2265 | ||
2266 | ret = setup_scratch_page(dev); | |
2267 | if (ret) { | |
2268 | DRM_ERROR("Scratch setup failed\n"); | |
2269 | /* iounmap will also get called at remove, but meh */ | |
2270 | iounmap(dev_priv->gtt.gsm); | |
2271 | } | |
2272 | ||
2273 | return ret; | |
2274 | } | |
2275 | ||
fbe5d36e BW |
2276 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
2277 | * bits. When using advanced contexts each context stores its own PAT, but | |
2278 | * writing this data shouldn't be harmful even in those cases. */ | |
ee0ce478 | 2279 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
fbe5d36e | 2280 | { |
fbe5d36e BW |
2281 | uint64_t pat; |
2282 | ||
2283 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ | |
2284 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ | |
2285 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ | |
2286 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ | |
2287 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | | |
2288 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | | |
2289 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | | |
2290 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); | |
2291 | ||
d6a8b72e RV |
2292 | if (!USES_PPGTT(dev_priv->dev)) |
2293 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2294 | * so RTL will always use the value corresponding to | |
2295 | * pat_sel = 000". | |
2296 | * So let's disable cache for GGTT to avoid screen corruptions. | |
2297 | * MOCS still can be used though. | |
2298 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work | |
2299 | * before this patch, i.e. the same uncached + snooping access | |
2300 | * like on gen6/7 seems to be in effect. | |
2301 | * - So this just fixes blitter/render access. Again it looks | |
2302 | * like it's not just uncached access, but uncached + snooping. | |
2303 | * So we can still hold onto all our assumptions wrt cpu | |
2304 | * clflushing on LLC machines. | |
2305 | */ | |
2306 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); | |
2307 | ||
fbe5d36e BW |
2308 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
2309 | * write would work. */ | |
2310 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2311 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2312 | } | |
2313 | ||
ee0ce478 VS |
2314 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
2315 | { | |
2316 | uint64_t pat; | |
2317 | ||
2318 | /* | |
2319 | * Map WB on BDW to snooped on CHV. | |
2320 | * | |
2321 | * Only the snoop bit has meaning for CHV, the rest is | |
2322 | * ignored. | |
2323 | * | |
cf3d262e VS |
2324 | * The hardware will never snoop for certain types of accesses: |
2325 | * - CPU GTT (GMADR->GGTT->no snoop->memory) | |
2326 | * - PPGTT page tables | |
2327 | * - some other special cycles | |
2328 | * | |
2329 | * As with BDW, we also need to consider the following for GT accesses: | |
2330 | * "For GGTT, there is NO pat_sel[2:0] from the entry, | |
2331 | * so RTL will always use the value corresponding to | |
2332 | * pat_sel = 000". | |
2333 | * Which means we must set the snoop bit in PAT entry 0 | |
2334 | * in order to keep the global status page working. | |
ee0ce478 VS |
2335 | */ |
2336 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | | |
2337 | GEN8_PPAT(1, 0) | | |
2338 | GEN8_PPAT(2, 0) | | |
2339 | GEN8_PPAT(3, 0) | | |
2340 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | | |
2341 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | | |
2342 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | | |
2343 | GEN8_PPAT(7, CHV_PPAT_SNOOP); | |
2344 | ||
2345 | I915_WRITE(GEN8_PRIVATE_PAT, pat); | |
2346 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); | |
2347 | } | |
2348 | ||
63340133 | 2349 | static int gen8_gmch_probe(struct drm_device *dev, |
c44ef60e | 2350 | u64 *gtt_total, |
63340133 BW |
2351 | size_t *stolen, |
2352 | phys_addr_t *mappable_base, | |
c44ef60e | 2353 | u64 *mappable_end) |
63340133 BW |
2354 | { |
2355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c44ef60e | 2356 | u64 gtt_size; |
63340133 BW |
2357 | u16 snb_gmch_ctl; |
2358 | int ret; | |
2359 | ||
2360 | /* TODO: We're not aware of mappable constraints on gen8 yet */ | |
2361 | *mappable_base = pci_resource_start(dev->pdev, 2); | |
2362 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2363 | ||
2364 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) | |
2365 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); | |
2366 | ||
2367 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); | |
2368 | ||
66375014 DL |
2369 | if (INTEL_INFO(dev)->gen >= 9) { |
2370 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); | |
2371 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2372 | } else if (IS_CHERRYVIEW(dev)) { | |
d7f25f23 DL |
2373 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
2374 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); | |
2375 | } else { | |
2376 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); | |
2377 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); | |
2378 | } | |
63340133 | 2379 | |
07749ef3 | 2380 | *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
63340133 | 2381 | |
5a4e33a3 | 2382 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) |
ee0ce478 VS |
2383 | chv_setup_private_ppat(dev_priv); |
2384 | else | |
2385 | bdw_setup_private_ppat(dev_priv); | |
fbe5d36e | 2386 | |
63340133 BW |
2387 | ret = ggtt_probe_common(dev, gtt_size); |
2388 | ||
94ec8f61 BW |
2389 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
2390 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; | |
777dc5bb DV |
2391 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2392 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
63340133 BW |
2393 | |
2394 | return ret; | |
2395 | } | |
2396 | ||
baa09f5f | 2397 | static int gen6_gmch_probe(struct drm_device *dev, |
c44ef60e | 2398 | u64 *gtt_total, |
41907ddc BW |
2399 | size_t *stolen, |
2400 | phys_addr_t *mappable_base, | |
c44ef60e | 2401 | u64 *mappable_end) |
e76e9aeb BW |
2402 | { |
2403 | struct drm_i915_private *dev_priv = dev->dev_private; | |
baa09f5f | 2404 | unsigned int gtt_size; |
e76e9aeb | 2405 | u16 snb_gmch_ctl; |
e76e9aeb BW |
2406 | int ret; |
2407 | ||
41907ddc BW |
2408 | *mappable_base = pci_resource_start(dev->pdev, 2); |
2409 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
2410 | ||
baa09f5f BW |
2411 | /* 64/512MB is the current min/max we actually know of, but this is just |
2412 | * a coarse sanity check. | |
e76e9aeb | 2413 | */ |
41907ddc | 2414 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
c44ef60e | 2415 | DRM_ERROR("Unknown GMADR size (%llx)\n", |
baa09f5f BW |
2416 | dev_priv->gtt.mappable_end); |
2417 | return -ENXIO; | |
e76e9aeb BW |
2418 | } |
2419 | ||
e76e9aeb BW |
2420 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
2421 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 2422 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
e76e9aeb | 2423 | |
c4ae25ec | 2424 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
a93e4161 | 2425 | |
63340133 | 2426 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
07749ef3 | 2427 | *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 2428 | |
63340133 | 2429 | ret = ggtt_probe_common(dev, gtt_size); |
e76e9aeb | 2430 | |
853ba5d2 BW |
2431 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
2432 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; | |
777dc5bb DV |
2433 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2434 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
7faf1ab2 | 2435 | |
e76e9aeb BW |
2436 | return ret; |
2437 | } | |
2438 | ||
853ba5d2 | 2439 | static void gen6_gmch_remove(struct i915_address_space *vm) |
e76e9aeb | 2440 | { |
853ba5d2 BW |
2441 | |
2442 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); | |
5ed16782 | 2443 | |
853ba5d2 BW |
2444 | iounmap(gtt->gsm); |
2445 | teardown_scratch_page(vm->dev); | |
644ec02b | 2446 | } |
baa09f5f BW |
2447 | |
2448 | static int i915_gmch_probe(struct drm_device *dev, | |
c44ef60e | 2449 | u64 *gtt_total, |
41907ddc BW |
2450 | size_t *stolen, |
2451 | phys_addr_t *mappable_base, | |
c44ef60e | 2452 | u64 *mappable_end) |
baa09f5f BW |
2453 | { |
2454 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2455 | int ret; | |
2456 | ||
baa09f5f BW |
2457 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
2458 | if (!ret) { | |
2459 | DRM_ERROR("failed to set up gmch\n"); | |
2460 | return -EIO; | |
2461 | } | |
2462 | ||
41907ddc | 2463 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
2464 | |
2465 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
d369d2d9 | 2466 | dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; |
853ba5d2 | 2467 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
d369d2d9 DV |
2468 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
2469 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; | |
baa09f5f | 2470 | |
c0a7f818 CW |
2471 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
2472 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); | |
2473 | ||
baa09f5f BW |
2474 | return 0; |
2475 | } | |
2476 | ||
853ba5d2 | 2477 | static void i915_gmch_remove(struct i915_address_space *vm) |
baa09f5f BW |
2478 | { |
2479 | intel_gmch_remove(); | |
2480 | } | |
2481 | ||
2482 | int i915_gem_gtt_init(struct drm_device *dev) | |
2483 | { | |
2484 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2485 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
2486 | int ret; |
2487 | ||
baa09f5f | 2488 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d | 2489 | gtt->gtt_probe = i915_gmch_probe; |
853ba5d2 | 2490 | gtt->base.cleanup = i915_gmch_remove; |
63340133 | 2491 | } else if (INTEL_INFO(dev)->gen < 8) { |
b2f21b4d | 2492 | gtt->gtt_probe = gen6_gmch_probe; |
853ba5d2 | 2493 | gtt->base.cleanup = gen6_gmch_remove; |
4d15c145 | 2494 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
853ba5d2 | 2495 | gtt->base.pte_encode = iris_pte_encode; |
4d15c145 | 2496 | else if (IS_HASWELL(dev)) |
853ba5d2 | 2497 | gtt->base.pte_encode = hsw_pte_encode; |
b2f21b4d | 2498 | else if (IS_VALLEYVIEW(dev)) |
853ba5d2 | 2499 | gtt->base.pte_encode = byt_pte_encode; |
350ec881 CW |
2500 | else if (INTEL_INFO(dev)->gen >= 7) |
2501 | gtt->base.pte_encode = ivb_pte_encode; | |
b2f21b4d | 2502 | else |
350ec881 | 2503 | gtt->base.pte_encode = snb_pte_encode; |
63340133 BW |
2504 | } else { |
2505 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; | |
2506 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; | |
baa09f5f BW |
2507 | } |
2508 | ||
853ba5d2 | 2509 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
b2f21b4d | 2510 | >t->mappable_base, >t->mappable_end); |
a54c0c27 | 2511 | if (ret) |
baa09f5f | 2512 | return ret; |
baa09f5f | 2513 | |
853ba5d2 BW |
2514 | gtt->base.dev = dev; |
2515 | ||
baa09f5f | 2516 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
c44ef60e | 2517 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
853ba5d2 | 2518 | gtt->base.total >> 20); |
c44ef60e | 2519 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20); |
b2f21b4d | 2520 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); |
5db6c735 DV |
2521 | #ifdef CONFIG_INTEL_IOMMU |
2522 | if (intel_iommu_gfx_mapped) | |
2523 | DRM_INFO("VT-d active for gfx access\n"); | |
2524 | #endif | |
cfa7c862 DV |
2525 | /* |
2526 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | |
2527 | * user's requested state against the hardware/driver capabilities. We | |
2528 | * do this now so that we can print out any log messages once rather | |
2529 | * than every time we check intel_enable_ppgtt(). | |
2530 | */ | |
2531 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | |
2532 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | |
baa09f5f BW |
2533 | |
2534 | return 0; | |
2535 | } | |
6f65e29a | 2536 | |
fa42331b DV |
2537 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
2538 | { | |
2539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2540 | struct drm_i915_gem_object *obj; | |
2541 | struct i915_address_space *vm; | |
2542 | ||
2543 | i915_check_and_clear_faults(dev); | |
2544 | ||
2545 | /* First fill our portion of the GTT with scratch pages */ | |
2546 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, | |
2547 | dev_priv->gtt.base.start, | |
2548 | dev_priv->gtt.base.total, | |
2549 | true); | |
2550 | ||
2551 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
2552 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, | |
2553 | &dev_priv->gtt.base); | |
2554 | if (!vma) | |
2555 | continue; | |
2556 | ||
2557 | i915_gem_clflush_object(obj, obj->pin_display); | |
2558 | WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE)); | |
2559 | } | |
2560 | ||
2561 | ||
2562 | if (INTEL_INFO(dev)->gen >= 8) { | |
2563 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) | |
2564 | chv_setup_private_ppat(dev_priv); | |
2565 | else | |
2566 | bdw_setup_private_ppat(dev_priv); | |
2567 | ||
2568 | return; | |
2569 | } | |
2570 | ||
2571 | if (USES_PPGTT(dev)) { | |
2572 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { | |
2573 | /* TODO: Perhaps it shouldn't be gen6 specific */ | |
2574 | ||
2575 | struct i915_hw_ppgtt *ppgtt = | |
2576 | container_of(vm, struct i915_hw_ppgtt, | |
2577 | base); | |
2578 | ||
2579 | if (i915_is_ggtt(vm)) | |
2580 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2581 | ||
2582 | gen6_write_page_range(dev_priv, &ppgtt->pd, | |
2583 | 0, ppgtt->base.total); | |
2584 | } | |
2585 | } | |
2586 | ||
2587 | i915_ggtt_flush(dev_priv); | |
2588 | } | |
2589 | ||
ec7adb6e JL |
2590 | static struct i915_vma * |
2591 | __i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
2592 | struct i915_address_space *vm, | |
2593 | const struct i915_ggtt_view *ggtt_view) | |
6f65e29a | 2594 | { |
dabde5c7 | 2595 | struct i915_vma *vma; |
6f65e29a | 2596 | |
ec7adb6e JL |
2597 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
2598 | return ERR_PTR(-EINVAL); | |
e20d2ab7 CW |
2599 | |
2600 | vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); | |
dabde5c7 DC |
2601 | if (vma == NULL) |
2602 | return ERR_PTR(-ENOMEM); | |
ec7adb6e | 2603 | |
6f65e29a BW |
2604 | INIT_LIST_HEAD(&vma->vma_link); |
2605 | INIT_LIST_HEAD(&vma->mm_list); | |
2606 | INIT_LIST_HEAD(&vma->exec_list); | |
2607 | vma->vm = vm; | |
2608 | vma->obj = obj; | |
2609 | ||
777dc5bb | 2610 | if (i915_is_ggtt(vm)) |
ec7adb6e | 2611 | vma->ggtt_view = *ggtt_view; |
6f65e29a | 2612 | |
f7635669 TU |
2613 | list_add_tail(&vma->vma_link, &obj->vma_list); |
2614 | if (!i915_is_ggtt(vm)) | |
e07f0552 | 2615 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
6f65e29a BW |
2616 | |
2617 | return vma; | |
2618 | } | |
2619 | ||
2620 | struct i915_vma * | |
ec7adb6e JL |
2621 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
2622 | struct i915_address_space *vm) | |
2623 | { | |
2624 | struct i915_vma *vma; | |
2625 | ||
2626 | vma = i915_gem_obj_to_vma(obj, vm); | |
2627 | if (!vma) | |
2628 | vma = __i915_gem_vma_create(obj, vm, | |
2629 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL); | |
2630 | ||
2631 | return vma; | |
2632 | } | |
2633 | ||
2634 | struct i915_vma * | |
2635 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
fe14d5f4 | 2636 | const struct i915_ggtt_view *view) |
6f65e29a | 2637 | { |
ec7adb6e | 2638 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
6f65e29a BW |
2639 | struct i915_vma *vma; |
2640 | ||
ec7adb6e JL |
2641 | if (WARN_ON(!view)) |
2642 | return ERR_PTR(-EINVAL); | |
2643 | ||
2644 | vma = i915_gem_obj_to_ggtt_view(obj, view); | |
2645 | ||
2646 | if (IS_ERR(vma)) | |
2647 | return vma; | |
2648 | ||
6f65e29a | 2649 | if (!vma) |
ec7adb6e | 2650 | vma = __i915_gem_vma_create(obj, ggtt, view); |
6f65e29a BW |
2651 | |
2652 | return vma; | |
ec7adb6e | 2653 | |
6f65e29a | 2654 | } |
fe14d5f4 | 2655 | |
50470bb0 TU |
2656 | static void |
2657 | rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height, | |
2658 | struct sg_table *st) | |
2659 | { | |
2660 | unsigned int column, row; | |
2661 | unsigned int src_idx; | |
2662 | struct scatterlist *sg = st->sgl; | |
2663 | ||
2664 | st->nents = 0; | |
2665 | ||
2666 | for (column = 0; column < width; column++) { | |
2667 | src_idx = width * (height - 1) + column; | |
2668 | for (row = 0; row < height; row++) { | |
2669 | st->nents++; | |
2670 | /* We don't need the pages, but need to initialize | |
2671 | * the entries so the sg list can be happily traversed. | |
2672 | * The only thing we need are DMA addresses. | |
2673 | */ | |
2674 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
2675 | sg_dma_address(sg) = in[src_idx]; | |
2676 | sg_dma_len(sg) = PAGE_SIZE; | |
2677 | sg = sg_next(sg); | |
2678 | src_idx -= width; | |
2679 | } | |
2680 | } | |
2681 | } | |
2682 | ||
2683 | static struct sg_table * | |
2684 | intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view, | |
2685 | struct drm_i915_gem_object *obj) | |
2686 | { | |
50470bb0 | 2687 | struct intel_rotation_info *rot_info = &ggtt_view->rotation_info; |
84fe03f7 | 2688 | unsigned int size_pages = rot_info->size >> PAGE_SHIFT; |
50470bb0 TU |
2689 | struct sg_page_iter sg_iter; |
2690 | unsigned long i; | |
2691 | dma_addr_t *page_addr_list; | |
2692 | struct sg_table *st; | |
1d00dad5 | 2693 | int ret = -ENOMEM; |
50470bb0 | 2694 | |
50470bb0 | 2695 | /* Allocate a temporary list of source pages for random access. */ |
84fe03f7 TU |
2696 | page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE, |
2697 | sizeof(dma_addr_t)); | |
50470bb0 TU |
2698 | if (!page_addr_list) |
2699 | return ERR_PTR(ret); | |
2700 | ||
2701 | /* Allocate target SG list. */ | |
2702 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
2703 | if (!st) | |
2704 | goto err_st_alloc; | |
2705 | ||
84fe03f7 | 2706 | ret = sg_alloc_table(st, size_pages, GFP_KERNEL); |
50470bb0 TU |
2707 | if (ret) |
2708 | goto err_sg_alloc; | |
2709 | ||
2710 | /* Populate source page list from the object. */ | |
2711 | i = 0; | |
2712 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { | |
2713 | page_addr_list[i] = sg_page_iter_dma_address(&sg_iter); | |
2714 | i++; | |
2715 | } | |
2716 | ||
2717 | /* Rotate the pages. */ | |
84fe03f7 TU |
2718 | rotate_pages(page_addr_list, |
2719 | rot_info->width_pages, rot_info->height_pages, | |
2720 | st); | |
50470bb0 TU |
2721 | |
2722 | DRM_DEBUG_KMS( | |
84fe03f7 | 2723 | "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n", |
c9f8fd2d | 2724 | obj->base.size, rot_info->pitch, rot_info->height, |
84fe03f7 TU |
2725 | rot_info->pixel_format, rot_info->width_pages, |
2726 | rot_info->height_pages, size_pages); | |
50470bb0 TU |
2727 | |
2728 | drm_free_large(page_addr_list); | |
2729 | ||
2730 | return st; | |
2731 | ||
2732 | err_sg_alloc: | |
2733 | kfree(st); | |
2734 | err_st_alloc: | |
2735 | drm_free_large(page_addr_list); | |
2736 | ||
2737 | DRM_DEBUG_KMS( | |
84fe03f7 | 2738 | "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n", |
c9f8fd2d | 2739 | obj->base.size, ret, rot_info->pitch, rot_info->height, |
84fe03f7 TU |
2740 | rot_info->pixel_format, rot_info->width_pages, |
2741 | rot_info->height_pages, size_pages); | |
50470bb0 TU |
2742 | return ERR_PTR(ret); |
2743 | } | |
ec7adb6e | 2744 | |
8bd7ef16 JL |
2745 | static struct sg_table * |
2746 | intel_partial_pages(const struct i915_ggtt_view *view, | |
2747 | struct drm_i915_gem_object *obj) | |
2748 | { | |
2749 | struct sg_table *st; | |
2750 | struct scatterlist *sg; | |
2751 | struct sg_page_iter obj_sg_iter; | |
2752 | int ret = -ENOMEM; | |
2753 | ||
2754 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
2755 | if (!st) | |
2756 | goto err_st_alloc; | |
2757 | ||
2758 | ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL); | |
2759 | if (ret) | |
2760 | goto err_sg_alloc; | |
2761 | ||
2762 | sg = st->sgl; | |
2763 | st->nents = 0; | |
2764 | for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents, | |
2765 | view->params.partial.offset) | |
2766 | { | |
2767 | if (st->nents >= view->params.partial.size) | |
2768 | break; | |
2769 | ||
2770 | sg_set_page(sg, NULL, PAGE_SIZE, 0); | |
2771 | sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter); | |
2772 | sg_dma_len(sg) = PAGE_SIZE; | |
2773 | ||
2774 | sg = sg_next(sg); | |
2775 | st->nents++; | |
2776 | } | |
2777 | ||
2778 | return st; | |
2779 | ||
2780 | err_sg_alloc: | |
2781 | kfree(st); | |
2782 | err_st_alloc: | |
2783 | return ERR_PTR(ret); | |
2784 | } | |
2785 | ||
70b9f6f8 | 2786 | static int |
50470bb0 | 2787 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
fe14d5f4 | 2788 | { |
50470bb0 TU |
2789 | int ret = 0; |
2790 | ||
fe14d5f4 TU |
2791 | if (vma->ggtt_view.pages) |
2792 | return 0; | |
2793 | ||
2794 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
2795 | vma->ggtt_view.pages = vma->obj->pages; | |
50470bb0 TU |
2796 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
2797 | vma->ggtt_view.pages = | |
2798 | intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj); | |
8bd7ef16 JL |
2799 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
2800 | vma->ggtt_view.pages = | |
2801 | intel_partial_pages(&vma->ggtt_view, vma->obj); | |
fe14d5f4 TU |
2802 | else |
2803 | WARN_ONCE(1, "GGTT view %u not implemented!\n", | |
2804 | vma->ggtt_view.type); | |
2805 | ||
2806 | if (!vma->ggtt_view.pages) { | |
ec7adb6e | 2807 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
fe14d5f4 | 2808 | vma->ggtt_view.type); |
50470bb0 TU |
2809 | ret = -EINVAL; |
2810 | } else if (IS_ERR(vma->ggtt_view.pages)) { | |
2811 | ret = PTR_ERR(vma->ggtt_view.pages); | |
2812 | vma->ggtt_view.pages = NULL; | |
2813 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", | |
2814 | vma->ggtt_view.type, ret); | |
fe14d5f4 TU |
2815 | } |
2816 | ||
50470bb0 | 2817 | return ret; |
fe14d5f4 TU |
2818 | } |
2819 | ||
2820 | /** | |
2821 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. | |
2822 | * @vma: VMA to map | |
2823 | * @cache_level: mapping cache level | |
2824 | * @flags: flags like global or local mapping | |
2825 | * | |
2826 | * DMA addresses are taken from the scatter-gather table of this object (or of | |
2827 | * this VMA in case of non-default GGTT views) and PTE entries set up. | |
2828 | * Note that DMA addresses are also the only part of the SG table we care about. | |
2829 | */ | |
2830 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2831 | u32 flags) | |
2832 | { | |
75d04a37 MK |
2833 | int ret; |
2834 | u32 bind_flags; | |
1d335d1b | 2835 | |
75d04a37 MK |
2836 | if (WARN_ON(flags == 0)) |
2837 | return -EINVAL; | |
1d335d1b | 2838 | |
75d04a37 | 2839 | bind_flags = 0; |
0875546c DV |
2840 | if (flags & PIN_GLOBAL) |
2841 | bind_flags |= GLOBAL_BIND; | |
2842 | if (flags & PIN_USER) | |
2843 | bind_flags |= LOCAL_BIND; | |
2844 | ||
2845 | if (flags & PIN_UPDATE) | |
2846 | bind_flags |= vma->bound; | |
2847 | else | |
2848 | bind_flags &= ~vma->bound; | |
2849 | ||
75d04a37 MK |
2850 | if (bind_flags == 0) |
2851 | return 0; | |
2852 | ||
2853 | if (vma->bound == 0 && vma->vm->allocate_va_range) { | |
2854 | trace_i915_va_alloc(vma->vm, | |
2855 | vma->node.start, | |
2856 | vma->node.size, | |
2857 | VM_TO_TRACE_NAME(vma->vm)); | |
2858 | ||
2859 | ret = vma->vm->allocate_va_range(vma->vm, | |
2860 | vma->node.start, | |
2861 | vma->node.size); | |
2862 | if (ret) | |
2863 | return ret; | |
2864 | } | |
2865 | ||
2866 | ret = vma->vm->bind_vma(vma, cache_level, bind_flags); | |
70b9f6f8 DV |
2867 | if (ret) |
2868 | return ret; | |
0875546c DV |
2869 | |
2870 | vma->bound |= bind_flags; | |
fe14d5f4 TU |
2871 | |
2872 | return 0; | |
2873 | } | |
91e6711e JL |
2874 | |
2875 | /** | |
2876 | * i915_ggtt_view_size - Get the size of a GGTT view. | |
2877 | * @obj: Object the view is of. | |
2878 | * @view: The view in question. | |
2879 | * | |
2880 | * @return The size of the GGTT view in bytes. | |
2881 | */ | |
2882 | size_t | |
2883 | i915_ggtt_view_size(struct drm_i915_gem_object *obj, | |
2884 | const struct i915_ggtt_view *view) | |
2885 | { | |
9e759ff1 | 2886 | if (view->type == I915_GGTT_VIEW_NORMAL) { |
91e6711e | 2887 | return obj->base.size; |
9e759ff1 TU |
2888 | } else if (view->type == I915_GGTT_VIEW_ROTATED) { |
2889 | return view->rotation_info.size; | |
8bd7ef16 JL |
2890 | } else if (view->type == I915_GGTT_VIEW_PARTIAL) { |
2891 | return view->params.partial.size << PAGE_SHIFT; | |
91e6711e JL |
2892 | } else { |
2893 | WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type); | |
2894 | return obj->base.size; | |
2895 | } | |
2896 | } |